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--- /dev/null
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--- /dev/null
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--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1470429543" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
+ <provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1626908118750363851" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1653259917" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
+ <provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1626908118750363851" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal.c:138:19:HAL_Init 8 static
+stm32f7xx_hal.c:168:19:HAL_DeInit 8 static
+stm32f7xx_hal.c:197:13:HAL_MspInit 4 static
+stm32f7xx_hal.c:208:13:HAL_MspDeInit 4 static
+stm32f7xx_hal.c:231:26:HAL_InitTick 16 static
+stm32f7xx_hal.c:290:13:HAL_IncTick 4 static
+stm32f7xx_hal.c:301:17:HAL_GetTick 4 static
+stm32f7xx_hal.c:310:10:HAL_GetTickPrio 4 static
+stm32f7xx_hal.c:319:19:HAL_SetTickFreq 24 static
+stm32f7xx_hal.c:339:21:HAL_GetTickFreq 4 static
+stm32f7xx_hal.c:355:13:HAL_Delay 24 static
+stm32f7xx_hal.c:381:13:HAL_SuspendTick 4 static
+stm32f7xx_hal.c:397:13:HAL_ResumeTick 4 static
+stm32f7xx_hal.c:407:10:HAL_GetHalVersion 4 static
+stm32f7xx_hal.c:416:10:HAL_GetREVID 4 static
+stm32f7xx_hal.c:425:10:HAL_GetDEVID 4 static
+stm32f7xx_hal.c:434:10:HAL_GetUIDw0 4 static
+stm32f7xx_hal.c:443:10:HAL_GetUIDw1 4 static
+stm32f7xx_hal.c:452:10:HAL_GetUIDw2 4 static
+stm32f7xx_hal.c:461:6:HAL_DBGMCU_EnableDBGSleepMode 4 static
+stm32f7xx_hal.c:470:6:HAL_DBGMCU_DisableDBGSleepMode 4 static
+stm32f7xx_hal.c:479:6:HAL_DBGMCU_EnableDBGStopMode 4 static
+stm32f7xx_hal.c:488:6:HAL_DBGMCU_DisableDBGStopMode 4 static
+stm32f7xx_hal.c:497:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static
+stm32f7xx_hal.c:506:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static
+stm32f7xx_hal.c:517:6:HAL_EnableCompensationCell 4 static
+stm32f7xx_hal.c:528:6:HAL_DisableCompensationCell 4 static
+stm32f7xx_hal.c:541:6:HAL_EnableFMCMemorySwapping 4 static
+stm32f7xx_hal.c:554:6:HAL_DisableFMCMemorySwapping 4 static
+stm32f7xx_hal.c:571:6:HAL_EnableMemorySwappingBank 4 static
+stm32f7xx_hal.c:586:6:HAL_DisableMemorySwappingBank 4 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+core_cm7.h:1865:22:__NVIC_SetPriorityGrouping 24 static
+core_cm7.h:1884:26:__NVIC_GetPriorityGrouping 4 static
+core_cm7.h:1896:22:__NVIC_EnableIRQ 16 static
+core_cm7.h:1932:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm
+core_cm7.h:1951:26:__NVIC_GetPendingIRQ 16 static
+core_cm7.h:1970:22:__NVIC_SetPendingIRQ 16 static
+core_cm7.h:1985:22:__NVIC_ClearPendingIRQ 16 static
+core_cm7.h:2002:26:__NVIC_GetActive 16 static
+core_cm7.h:2024:22:__NVIC_SetPriority 16 static
+core_cm7.h:2046:26:__NVIC_GetPriority 16 static
+core_cm7.h:2071:26:NVIC_EncodePriority 40 static
+core_cm7.h:2098:22:NVIC_DecodePriority 40 static
+core_cm7.h:2147:34:__NVIC_SystemReset 4 static,ignoring_inline_asm
+core_cm7.h:2564:26:SysTick_Config 16 static
+stm32f7xx_hal_cortex.c:143:6:HAL_NVIC_SetPriorityGrouping 16 static
+stm32f7xx_hal_cortex.c:165:6:HAL_NVIC_SetPriority 32 static
+stm32f7xx_hal_cortex.c:187:6:HAL_NVIC_EnableIRQ 16 static
+stm32f7xx_hal_cortex.c:203:6:HAL_NVIC_DisableIRQ 16 static
+stm32f7xx_hal_cortex.c:216:6:HAL_NVIC_SystemReset 8 static
+stm32f7xx_hal_cortex.c:229:10:HAL_SYSTICK_Config 16 static
+stm32f7xx_hal_cortex.c:258:6:HAL_MPU_Disable 4 static,ignoring_inline_asm
+stm32f7xx_hal_cortex.c:281:6:HAL_MPU_Enable 16 static,ignoring_inline_asm
+stm32f7xx_hal_cortex.c:300:6:HAL_MPU_ConfigRegion 16 static
+stm32f7xx_hal_cortex.c:344:10:HAL_NVIC_GetPriorityGrouping 8 static
+stm32f7xx_hal_cortex.c:371:6:HAL_NVIC_GetPriority 24 static
+stm32f7xx_hal_cortex.c:386:6:HAL_NVIC_SetPendingIRQ 16 static
+stm32f7xx_hal_cortex.c:404:10:HAL_NVIC_GetPendingIRQ 16 static
+stm32f7xx_hal_cortex.c:420:6:HAL_NVIC_ClearPendingIRQ 16 static
+stm32f7xx_hal_cortex.c:437:10:HAL_NVIC_GetActive 16 static
+stm32f7xx_hal_cortex.c:454:6:HAL_SYSTICK_CLKSourceConfig 16 static
+stm32f7xx_hal_cortex.c:472:6:HAL_SYSTICK_IRQHandler 8 static
+stm32f7xx_hal_cortex.c:481:13:HAL_SYSTICK_Callback 4 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_dma.c:172:19:HAL_DMA_Init 32 static
+stm32f7xx_hal_dma.c:311:19:HAL_DMA_DeInit 24 static
+stm32f7xx_hal_dma.c:409:19:HAL_DMA_Start 32 static
+stm32f7xx_hal_dma.c:453:19:HAL_DMA_Start_IT 32 static
+stm32f7xx_hal_dma.c:516:19:HAL_DMA_Abort 24 static
+stm32f7xx_hal_dma.c:583:19:HAL_DMA_Abort_IT 16 static
+stm32f7xx_hal_dma.c:613:19:HAL_DMA_PollForTransfer 48 static
+stm32f7xx_hal_dma.c:749:6:HAL_DMA_IRQHandler 32 static
+stm32f7xx_hal_dma.c:970:19:HAL_DMA_RegisterCallback 32 static
+stm32f7xx_hal_dma.c:1030:19:HAL_DMA_UnRegisterCallback 24 static
+stm32f7xx_hal_dma.c:1115:22:HAL_DMA_GetState 16 static
+stm32f7xx_hal_dma.c:1126:10:HAL_DMA_GetError 16 static
+stm32f7xx_hal_dma.c:1152:13:DMA_SetConfig 24 static
+stm32f7xx_hal_dma.c:1186:17:DMA_CalcBaseAndBitshift 24 static
+stm32f7xx_hal_dma.c:1214:26:DMA_CheckFifoParam 24 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_dma_ex.c:103:19:HAL_DMAEx_MultiBufferStart 32 static
+stm32f7xx_hal_dma_ex.c:157:19:HAL_DMAEx_MultiBufferStart_IT 32 static
+stm32f7xx_hal_dma_ex.c:235:19:HAL_DMAEx_ChangeMemory 24 static
+stm32f7xx_hal_dma_ex.c:272:13:DMA_MultiBufferSetConfig 24 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_exti.c:144:19:HAL_EXTI_SetConfigLine 24 static
+stm32f7xx_hal_exti.c:197:19:HAL_EXTI_GetConfigLine 16 static
+stm32f7xx_hal_exti.c:256:19:HAL_EXTI_ClearConfigLine 16 static
+stm32f7xx_hal_exti.c:288:19:HAL_EXTI_RegisterCallback 32 static
+stm32f7xx_hal_exti.c:313:19:HAL_EXTI_GetHandle 16 static
+stm32f7xx_hal_exti.c:353:6:HAL_EXTI_IRQHandler 24 static
+stm32f7xx_hal_exti.c:384:10:HAL_EXTI_GetPending 32 static,ignoring_inline_asm
+stm32f7xx_hal_exti.c:411:6:HAL_EXTI_ClearPending 16 static
+stm32f7xx_hal_exti.c:426:6:HAL_EXTI_GenerateSWI 16 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_flash.c:164:19:HAL_FLASH_Program 32 static
+stm32f7xx_hal_flash.c:233:19:HAL_FLASH_Program_IT 32 static
+stm32f7xx_hal_flash.c:295:6:HAL_FLASH_IRQHandler 16 static
+stm32f7xx_hal_flash.c:430:13:HAL_FLASH_EndOfOperationCallback 16 static
+stm32f7xx_hal_flash.c:448:13:HAL_FLASH_OperationErrorCallback 16 static
+stm32f7xx_hal_flash.c:480:19:HAL_FLASH_Unlock 16 static
+stm32f7xx_hal_flash.c:504:19:HAL_FLASH_Lock 4 static
+stm32f7xx_hal_flash.c:516:19:HAL_FLASH_OB_Unlock 4 static
+stm32f7xx_hal_flash.c:536:19:HAL_FLASH_OB_Lock 4 static
+stm32f7xx_hal_flash.c:548:19:HAL_FLASH_OB_Launch 8 static
+stm32f7xx_hal_flash.c:584:10:HAL_FLASH_GetError 4 static
+stm32f7xx_hal_flash.c:598:19:FLASH_WaitForLastOperation 24 static
+stm32f7xx_hal_flash.c:653:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm
+stm32f7xx_hal_flash.c:685:13:FLASH_Program_Word 16 static,ignoring_inline_asm
+stm32f7xx_hal_flash.c:714:13:FLASH_Program_HalfWord 16 static,ignoring_inline_asm
+stm32f7xx_hal_flash.c:744:13:FLASH_Program_Byte 16 static,ignoring_inline_asm
+stm32f7xx_hal_flash.c:765:13:FLASH_SetErrorCode 4 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_flash_ex.c:158:19:HAL_FLASHEx_Erase 24 static
+stm32f7xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 24 static
+stm32f7xx_hal_flash_ex.c:287:19:HAL_FLASHEx_OBProgram 56 static
+stm32f7xx_hal_flash_ex.c:386:6:HAL_FLASHEx_OBGetConfig 16 static
+stm32f7xx_hal_flash_ex.c:442:13:FLASH_MassErase 16 static,ignoring_inline_asm
+stm32f7xx_hal_flash_ex.c:488:6:FLASH_Erase_Sector 24 static,ignoring_inline_asm
+stm32f7xx_hal_flash_ex.c:535:17:FLASH_OB_GetWRP 4 static
+stm32f7xx_hal_flash_ex.c:578:26:FLASH_OB_UserConfig 40 static
+stm32f7xx_hal_flash_ex.c:619:17:FLASH_OB_GetUser 4 static
+stm32f7xx_hal_flash_ex.c:808:26:FLASH_OB_EnableWRP 24 static
+stm32f7xx_hal_flash_ex.c:844:26:FLASH_OB_DisableWRP 24 static
+stm32f7xx_hal_flash_ex.c:875:26:FLASH_OB_RDP_LevelConfig 24 static
+stm32f7xx_hal_flash_ex.c:903:26:FLASH_OB_BOR_LevelConfig 16 static
+stm32f7xx_hal_flash_ex.c:934:26:FLASH_OB_BootAddressConfig 24 static
+stm32f7xx_hal_flash_ex.c:967:16:FLASH_OB_GetRDP 16 static
+stm32f7xx_hal_flash_ex.c:995:17:FLASH_OB_GetBOR 4 static
+stm32f7xx_hal_flash_ex.c:1018:17:FLASH_OB_GetBootAddress 24 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_gpio.c:169:6:HAL_GPIO_Init 40 static
+stm32f7xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 32 static
+stm32f7xx_hal_gpio.c:373:15:HAL_GPIO_ReadPin 24 static
+stm32f7xx_hal_gpio.c:407:6:HAL_GPIO_WritePin 16 static
+stm32f7xx_hal_gpio.c:429:6:HAL_GPIO_TogglePin 16 static
+stm32f7xx_hal_gpio.c:455:19:HAL_GPIO_LockPin 24 static
+stm32f7xx_hal_gpio.c:488:6:HAL_GPIO_EXTI_IRQHandler 16 static
+stm32f7xx_hal_gpio.c:503:13:HAL_GPIO_EXTI_Callback 16 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_i2c.c:469:19:HAL_I2C_Init 16 static
+stm32f7xx_hal_i2c.c:578:19:HAL_I2C_DeInit 16 static
+stm32f7xx_hal_i2c.c:624:13:HAL_I2C_MspInit 16 static
+stm32f7xx_hal_i2c.c:640:13:HAL_I2C_MspDeInit 16 static
+stm32f7xx_hal_i2c.c:1060:19:HAL_I2C_Master_Transmit 40 static
+stm32f7xx_hal_i2c.c:1174:19:HAL_I2C_Master_Receive 40 static
+stm32f7xx_hal_i2c.c:1287:19:HAL_I2C_Slave_Transmit 40 static
+stm32f7xx_hal_i2c.c:1424:19:HAL_I2C_Slave_Receive 40 static
+stm32f7xx_hal_i2c.c:1550:19:HAL_I2C_Master_Transmit_IT 40 static
+stm32f7xx_hal_i2c.c:1619:19:HAL_I2C_Master_Receive_IT 40 static
+stm32f7xx_hal_i2c.c:1686:19:HAL_I2C_Slave_Transmit_IT 24 static
+stm32f7xx_hal_i2c.c:1735:19:HAL_I2C_Slave_Receive_IT 24 static
+stm32f7xx_hal_i2c.c:1786:19:HAL_I2C_Master_Transmit_DMA 40 static
+stm32f7xx_hal_i2c.c:1929:19:HAL_I2C_Master_Receive_DMA 40 static
+stm32f7xx_hal_i2c.c:2070:19:HAL_I2C_Slave_Transmit_DMA 32 static
+stm32f7xx_hal_i2c.c:2173:19:HAL_I2C_Slave_Receive_DMA 32 static
+stm32f7xx_hal_i2c.c:2280:19:HAL_I2C_Mem_Write 40 static
+stm32f7xx_hal_i2c.c:2415:19:HAL_I2C_Mem_Read 40 static
+stm32f7xx_hal_i2c.c:2548:19:HAL_I2C_Mem_Write_IT 40 static
+stm32f7xx_hal_i2c.c:2639:19:HAL_I2C_Mem_Read_IT 40 static
+stm32f7xx_hal_i2c.c:2729:19:HAL_I2C_Mem_Write_DMA 48 static
+stm32f7xx_hal_i2c.c:2873:19:HAL_I2C_Mem_Read_DMA 48 static
+stm32f7xx_hal_i2c.c:3014:19:HAL_I2C_IsDeviceReady 48 static
+stm32f7xx_hal_i2c.c:3156:19:HAL_I2C_Master_Seq_Transmit_IT 40 static
+stm32f7xx_hal_i2c.c:3240:19:HAL_I2C_Master_Seq_Transmit_DMA 48 static
+stm32f7xx_hal_i2c.c:3402:19:HAL_I2C_Master_Seq_Receive_IT 40 static
+stm32f7xx_hal_i2c.c:3486:19:HAL_I2C_Master_Seq_Receive_DMA 48 static
+stm32f7xx_hal_i2c.c:3646:19:HAL_I2C_Slave_Seq_Transmit_IT 24 static
+stm32f7xx_hal_i2c.c:3741:19:HAL_I2C_Slave_Seq_Transmit_DMA 32 static
+stm32f7xx_hal_i2c.c:3920:19:HAL_I2C_Slave_Seq_Receive_IT 24 static
+stm32f7xx_hal_i2c.c:4015:19:HAL_I2C_Slave_Seq_Receive_DMA 32 static
+stm32f7xx_hal_i2c.c:4190:19:HAL_I2C_EnableListen_IT 16 static
+stm32f7xx_hal_i2c.c:4214:19:HAL_I2C_DisableListen_IT 24 static
+stm32f7xx_hal_i2c.c:4247:19:HAL_I2C_Master_Abort_IT 24 static
+stm32f7xx_hal_i2c.c:4297:6:HAL_I2C_EV_IRQHandler 24 static
+stm32f7xx_hal_i2c.c:4316:6:HAL_I2C_ER_IRQHandler 32 static
+stm32f7xx_hal_i2c.c:4365:13:HAL_I2C_MasterTxCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4381:13:HAL_I2C_MasterRxCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4396:13:HAL_I2C_SlaveTxCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4412:13:HAL_I2C_SlaveRxCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4430:13:HAL_I2C_AddrCallback 16 static
+stm32f7xx_hal_i2c.c:4448:13:HAL_I2C_ListenCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4464:13:HAL_I2C_MemTxCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4480:13:HAL_I2C_MemRxCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4496:13:HAL_I2C_ErrorCallback 16 static
+stm32f7xx_hal_i2c.c:4512:13:HAL_I2C_AbortCpltCallback 16 static
+stm32f7xx_hal_i2c.c:4547:22:HAL_I2C_GetState 16 static
+stm32f7xx_hal_i2c.c:4559:21:HAL_I2C_GetMode 16 static
+stm32f7xx_hal_i2c.c:4570:10:HAL_I2C_GetError 16 static
+stm32f7xx_hal_i2c.c:4595:26:I2C_Master_ISR_IT 40 static
+stm32f7xx_hal_i2c.c:4732:26:I2C_Slave_ISR_IT 32 static
+stm32f7xx_hal_i2c.c:4868:26:I2C_Master_ISR_DMA 40 static
+stm32f7xx_hal_i2c.c:5003:26:I2C_Slave_ISR_DMA 32 static
+stm32f7xx_hal_i2c.c:5123:26:I2C_RequestMemoryWrite 32 static
+stm32f7xx_hal_i2c.c:5176:26:I2C_RequestMemoryRead 32 static
+stm32f7xx_hal_i2c.c:5223:13:I2C_ITAddrCplt 24 static
+stm32f7xx_hal_i2c.c:5318:13:I2C_ITMasterSeqCplt 16 static
+stm32f7xx_hal_i2c.c:5371:13:I2C_ITSlaveSeqCplt 16 static
+stm32f7xx_hal_i2c.c:5427:13:I2C_ITMasterCplt 24 static
+stm32f7xx_hal_i2c.c:5546:13:I2C_ITSlaveCplt 24 static
+stm32f7xx_hal_i2c.c:5683:13:I2C_ITListenCplt 16 static
+stm32f7xx_hal_i2c.c:5734:13:I2C_ITError 24 static
+stm32f7xx_hal_i2c.c:5852:13:I2C_Flush_TXDR 16 static
+stm32f7xx_hal_i2c.c:5873:13:I2C_DMAMasterTransmitCplt 24 static
+stm32f7xx_hal_i2c.c:5921:13:I2C_DMASlaveTransmitCplt 24 static
+stm32f7xx_hal_i2c.c:5948:13:I2C_DMAMasterReceiveCplt 24 static
+stm32f7xx_hal_i2c.c:5996:13:I2C_DMASlaveReceiveCplt 24 static
+stm32f7xx_hal_i2c.c:6023:13:I2C_DMAError 24 static
+stm32f7xx_hal_i2c.c:6061:13:I2C_DMAAbort 24 static
+stm32f7xx_hal_i2c.c:6102:26:I2C_WaitOnFlagUntilTimeout 24 static
+stm32f7xx_hal_i2c.c:6132:26:I2C_WaitOnTXISFlagUntilTimeout 24 static
+stm32f7xx_hal_i2c.c:6169:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static
+stm32f7xx_hal_i2c.c:6203:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static
+stm32f7xx_hal_i2c.c:6266:26:I2C_IsAcknowledgeFailed 24 static
+stm32f7xx_hal_i2c.c:6334:13:I2C_TransferConfig 24 static
+stm32f7xx_hal_i2c.c:6353:13:I2C_Enable_IRQ 24 static
+stm32f7xx_hal_i2c.c:6424:13:I2C_Disable_IRQ 24 static
+stm32f7xx_hal_i2c.c:6487:13:I2C_ConvertOtherXferOptions 16 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_i2c_ex.c:92:19:HAL_I2CEx_ConfigAnalogFilter 16 static
+stm32f7xx_hal_i2c_ex.c:136:19:HAL_I2CEx_ConfigDigitalFilter 24 static
+stm32f7xx_hal_i2c_ex.c:199:6:HAL_I2CEx_EnableFastModePlus 24 static
+stm32f7xx_hal_i2c_ex.c:228:6:HAL_I2CEx_DisableFastModePlus 24 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_pwr.c:100:6:HAL_PWR_DeInit 4 static
+stm32f7xx_hal_pwr.c:113:6:HAL_PWR_EnableBkUpAccess 4 static
+stm32f7xx_hal_pwr.c:126:6:HAL_PWR_DisableBkUpAccess 4 static
+stm32f7xx_hal_pwr.c:260:6:HAL_PWR_ConfigPVD 16 static
+stm32f7xx_hal_pwr.c:303:6:HAL_PWR_EnablePVD 4 static
+stm32f7xx_hal_pwr.c:313:6:HAL_PWR_DisablePVD 4 static
+stm32f7xx_hal_pwr.c:336:6:HAL_PWR_EnableWakeUpPin 16 static
+stm32f7xx_hal_pwr.c:360:6:HAL_PWR_DisableWakeUpPin 16 static
+stm32f7xx_hal_pwr.c:387:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm
+stm32f7xx_hal_pwr.c:434:6:HAL_PWR_EnterSTOPMode 24 static,ignoring_inline_asm
+stm32f7xx_hal_pwr.c:487:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm
+stm32f7xx_hal_pwr.c:508:6:HAL_PWR_PVD_IRQHandler 8 static
+stm32f7xx_hal_pwr.c:525:13:HAL_PWR_PVDCallback 4 static
+stm32f7xx_hal_pwr.c:540:6:HAL_PWR_EnableSleepOnExit 4 static
+stm32f7xx_hal_pwr.c:552:6:HAL_PWR_DisableSleepOnExit 4 static
+stm32f7xx_hal_pwr.c:564:6:HAL_PWR_EnableSEVOnPend 4 static
+stm32f7xx_hal_pwr.c:576:6:HAL_PWR_DisableSEVOnPend 4 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_pwr_ex.c:135:19:HAL_PWREx_EnableBkUpReg 16 static
+stm32f7xx_hal_pwr_ex.c:164:19:HAL_PWREx_DisableBkUpReg 16 static
+stm32f7xx_hal_pwr_ex.c:193:6:HAL_PWREx_EnableFlashPowerDown 4 static
+stm32f7xx_hal_pwr_ex.c:203:6:HAL_PWREx_DisableFlashPowerDown 4 static
+stm32f7xx_hal_pwr_ex.c:213:6:HAL_PWREx_EnableMainRegulatorLowVoltage 4 static
+stm32f7xx_hal_pwr_ex.c:223:6:HAL_PWREx_DisableMainRegulatorLowVoltage 4 static
+stm32f7xx_hal_pwr_ex.c:233:6:HAL_PWREx_EnableLowRegulatorLowVoltage 4 static
+stm32f7xx_hal_pwr_ex.c:243:6:HAL_PWREx_DisableLowRegulatorLowVoltage 4 static
+stm32f7xx_hal_pwr_ex.c:259:19:HAL_PWREx_EnableOverDrive 16 static
+stm32f7xx_hal_pwr_ex.c:305:19:HAL_PWREx_DisableOverDrive 16 static
+stm32f7xx_hal_pwr_ex.c:379:19:HAL_PWREx_EnterUnderDriveSTOPMode 32 static,ignoring_inline_asm
+stm32f7xx_hal_pwr_ex.c:445:10:HAL_PWREx_GetVoltageRange 4 static
+stm32f7xx_hal_pwr_ex.c:477:19:HAL_PWREx_ControlVoltageScaling 32 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_rcc.c:198:19:HAL_RCC_DeInit 16 static
+stm32f7xx_hal_rcc.c:344:19:HAL_RCC_OscConfig 32 static
+stm32f7xx_hal_rcc.c:703:19:HAL_RCC_ClockConfig 24 static
+stm32f7xx_hal_rcc.c:884:6:HAL_RCC_MCOConfig 56 static
+stm32f7xx_hal_rcc.c:938:6:HAL_RCC_EnableCSS 4 static
+stm32f7xx_hal_rcc.c:947:6:HAL_RCC_DisableCSS 4 static
+stm32f7xx_hal_rcc.c:982:10:HAL_RCC_GetSysClockFreq 40 static
+stm32f7xx_hal_rcc.c:1036:10:HAL_RCC_GetHCLKFreq 4 static
+stm32f7xx_hal_rcc.c:1047:10:HAL_RCC_GetPCLK1Freq 8 static
+stm32f7xx_hal_rcc.c:1059:10:HAL_RCC_GetPCLK2Freq 8 static
+stm32f7xx_hal_rcc.c:1072:6:HAL_RCC_GetOscConfig 24 static,ignoring_inline_asm
+stm32f7xx_hal_rcc.c:1154:6:HAL_RCC_GetClockConfig 16 static
+stm32f7xx_hal_rcc.c:1180:6:HAL_RCC_NMI_IRQHandler 8 static
+stm32f7xx_hal_rcc.c:1197:13:HAL_RCC_CSSCallback 4 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_rcc_ex.c:107:19:HAL_RCCEx_PeriphCLKConfig 40 static
+stm32f7xx_hal_rcc_ex.c:667:6:HAL_RCCEx_GetPeriphCLKConfig 24 static
+stm32f7xx_hal_rcc_ex.c:1385:10:HAL_RCCEx_GetPeriphCLKFreq 32 static
+stm32f7xx_hal_rcc_ex.c:1588:19:HAL_RCCEx_EnablePLLI2S 24 static
+stm32f7xx_hal_rcc_ex.c:1649:19:HAL_RCCEx_DisablePLLI2S 16 static
+stm32f7xx_hal_rcc_ex.c:1676:19:HAL_RCCEx_EnablePLLSAI 24 static
+stm32f7xx_hal_rcc_ex.c:1738:19:HAL_RCCEx_DisablePLLSAI 16 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_tim.c:260:19:HAL_TIM_Base_Init 16 static
+stm32f7xx_hal_tim.c:312:19:HAL_TIM_Base_DeInit 16 static
+stm32f7xx_hal_tim.c:348:13:HAL_TIM_Base_MspInit 16 static
+stm32f7xx_hal_tim.c:363:13:HAL_TIM_Base_MspDeInit 16 static
+stm32f7xx_hal_tim.c:379:19:HAL_TIM_Base_Start 24 static
+stm32f7xx_hal_tim.c:408:19:HAL_TIM_Base_Stop 16 static
+stm32f7xx_hal_tim.c:431:19:HAL_TIM_Base_Start_IT 24 static
+stm32f7xx_hal_tim.c:457:19:HAL_TIM_Base_Stop_IT 16 static
+stm32f7xx_hal_tim.c:478:19:HAL_TIM_Base_Start_DMA 32 static
+stm32f7xx_hal_tim.c:537:19:HAL_TIM_Base_Stop_DMA 16 static
+stm32f7xx_hal_tim.c:592:19:HAL_TIM_OC_Init 16 static
+stm32f7xx_hal_tim.c:644:19:HAL_TIM_OC_DeInit 16 static
+stm32f7xx_hal_tim.c:680:13:HAL_TIM_OC_MspInit 16 static
+stm32f7xx_hal_tim.c:695:13:HAL_TIM_OC_MspDeInit 16 static
+stm32f7xx_hal_tim.c:718:19:HAL_TIM_OC_Start 24 static
+stm32f7xx_hal_tim.c:758:19:HAL_TIM_OC_Stop 16 static
+stm32f7xx_hal_tim.c:790:19:HAL_TIM_OC_Start_IT 24 static
+stm32f7xx_hal_tim.c:862:19:HAL_TIM_OC_Stop_IT 16 static
+stm32f7xx_hal_tim.c:930:19:HAL_TIM_OC_Start_DMA 32 static
+stm32f7xx_hal_tim.c:1072:19:HAL_TIM_OC_Stop_DMA 16 static
+stm32f7xx_hal_tim.c:1169:19:HAL_TIM_PWM_Init 16 static
+stm32f7xx_hal_tim.c:1221:19:HAL_TIM_PWM_DeInit 16 static
+stm32f7xx_hal_tim.c:1257:13:HAL_TIM_PWM_MspInit 16 static
+stm32f7xx_hal_tim.c:1272:13:HAL_TIM_PWM_MspDeInit 16 static
+stm32f7xx_hal_tim.c:1295:19:HAL_TIM_PWM_Start 24 static
+stm32f7xx_hal_tim.c:1335:19:HAL_TIM_PWM_Stop 16 static
+stm32f7xx_hal_tim.c:1370:19:HAL_TIM_PWM_Start_IT 24 static
+stm32f7xx_hal_tim.c:1441:19:HAL_TIM_PWM_Stop_IT 16 static
+stm32f7xx_hal_tim.c:1509:19:HAL_TIM_PWM_Start_DMA 32 static
+stm32f7xx_hal_tim.c:1650:19:HAL_TIM_PWM_Stop_DMA 16 static
+stm32f7xx_hal_tim.c:1747:19:HAL_TIM_IC_Init 16 static
+stm32f7xx_hal_tim.c:1799:19:HAL_TIM_IC_DeInit 16 static
+stm32f7xx_hal_tim.c:1835:13:HAL_TIM_IC_MspInit 16 static
+stm32f7xx_hal_tim.c:1850:13:HAL_TIM_IC_MspDeInit 16 static
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+stm32f7xx_hal_tim.c:1903:19:HAL_TIM_IC_Stop 16 static
+stm32f7xx_hal_tim.c:1929:19:HAL_TIM_IC_Start_IT 24 static
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+stm32f7xx_hal_tim.c:2056:19:HAL_TIM_IC_Start_DMA 32 static
+stm32f7xx_hal_tim.c:2191:19:HAL_TIM_IC_Stop_DMA 16 static
+stm32f7xx_hal_tim.c:2286:19:HAL_TIM_OnePulse_Init 16 static
+stm32f7xx_hal_tim.c:2345:19:HAL_TIM_OnePulse_DeInit 16 static
+stm32f7xx_hal_tim.c:2381:13:HAL_TIM_OnePulse_MspInit 16 static
+stm32f7xx_hal_tim.c:2396:13:HAL_TIM_OnePulse_MspDeInit 16 static
+stm32f7xx_hal_tim.c:2415:19:HAL_TIM_OnePulse_Start 16 static
+stm32f7xx_hal_tim.c:2451:19:HAL_TIM_OnePulse_Stop 16 static
+stm32f7xx_hal_tim.c:2487:19:HAL_TIM_OnePulse_Start_IT 16 static
+stm32f7xx_hal_tim.c:2529:19:HAL_TIM_OnePulse_Stop_IT 16 static
+stm32f7xx_hal_tim.c:2599:19:HAL_TIM_Encoder_Init 32 static
+stm32f7xx_hal_tim.c:2704:19:HAL_TIM_Encoder_DeInit 16 static
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+stm32f7xx_hal_tim.c:2755:13:HAL_TIM_Encoder_MspDeInit 16 static
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+stm32f7xx_hal_tim.c:2819:19:HAL_TIM_Encoder_Stop 16 static
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+stm32f7xx_hal_tim.c:2969:19:HAL_TIM_Encoder_Start_DMA 24 static
+stm32f7xx_hal_tim.c:3103:19:HAL_TIM_Encoder_Stop_DMA 16 static
+stm32f7xx_hal_tim.c:3169:6:HAL_TIM_IRQHandler 16 static
+stm32f7xx_hal_tim.c:3399:19:HAL_TIM_OC_ConfigChannel 24 static
+stm32f7xx_hal_tim.c:3499:19:HAL_TIM_IC_ConfigChannel 24 static
+stm32f7xx_hal_tim.c:3598:19:HAL_TIM_PWM_ConfigChannel 24 static
+stm32f7xx_hal_tim.c:3743:19:HAL_TIM_OnePulse_ConfigChannel 56 static
+stm32f7xx_hal_tim.c:3888:19:HAL_TIM_DMABurst_WriteStart 24 static
+stm32f7xx_hal_tim.c:4051:19:HAL_TIM_DMABurst_WriteStop 24 static
+stm32f7xx_hal_tim.c:4154:19:HAL_TIM_DMABurst_ReadStart 24 static
+stm32f7xx_hal_tim.c:4318:19:HAL_TIM_DMABurst_ReadStop 24 static
+stm32f7xx_hal_tim.c:4397:19:HAL_TIM_GenerateEvent 16 static
+stm32f7xx_hal_tim.c:4436:19:HAL_TIM_ConfigOCrefClear 24 static
+stm32f7xx_hal_tim.c:4588:19:HAL_TIM_ConfigClockSource 24 static
+stm32f7xx_hal_tim.c:4740:19:HAL_TIM_ConfigTI1Input 24 static
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+stm32f7xx_hal_tim.c:4812:19:HAL_TIM_SlaveConfigSynchro_IT 16 static
+stm32f7xx_hal_tim.c:4855:10:HAL_TIM_ReadCapturedValue 24 static
+stm32f7xx_hal_tim.c:4939:13:HAL_TIM_PeriodElapsedCallback 16 static
+stm32f7xx_hal_tim.c:4954:13:HAL_TIM_PeriodElapsedHalfCpltCallback 16 static
+stm32f7xx_hal_tim.c:4969:13:HAL_TIM_OC_DelayElapsedCallback 16 static
+stm32f7xx_hal_tim.c:4984:13:HAL_TIM_IC_CaptureCallback 16 static
+stm32f7xx_hal_tim.c:4999:13:HAL_TIM_IC_CaptureHalfCpltCallback 16 static
+stm32f7xx_hal_tim.c:5014:13:HAL_TIM_PWM_PulseFinishedCallback 16 static
+stm32f7xx_hal_tim.c:5029:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 16 static
+stm32f7xx_hal_tim.c:5044:13:HAL_TIM_TriggerCallback 16 static
+stm32f7xx_hal_tim.c:5059:13:HAL_TIM_TriggerHalfCpltCallback 16 static
+stm32f7xx_hal_tim.c:5074:13:HAL_TIM_ErrorCallback 16 static
+stm32f7xx_hal_tim.c:5600:22:HAL_TIM_Base_GetState 16 static
+stm32f7xx_hal_tim.c:5610:22:HAL_TIM_OC_GetState 16 static
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+stm32f7xx_hal_tim.c:5630:22:HAL_TIM_IC_GetState 16 static
+stm32f7xx_hal_tim.c:5640:22:HAL_TIM_OnePulse_GetState 16 static
+stm32f7xx_hal_tim.c:5650:22:HAL_TIM_Encoder_GetState 16 static
+stm32f7xx_hal_tim.c:5672:6:TIM_DMAError 24 static
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+stm32f7xx_hal_tim.c:5854:13:TIM_DMAPeriodElapsedCplt 24 static
+stm32f7xx_hal_tim.c:5872:13:TIM_DMAPeriodElapsedHalfCplt 24 static
+stm32f7xx_hal_tim.c:5890:13:TIM_DMATriggerCplt 24 static
+stm32f7xx_hal_tim.c:5908:13:TIM_DMATriggerHalfCplt 24 static
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+stm32f7xx_hal_tim.c:6313:13:TIM_OC6_SetConfig 32 static
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+stm32f7xx_hal_tim.c:6498:6:TIM_TI1_SetConfig 32 static
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+stm32f7xx_hal_tim.c:6671:13:TIM_TI3_SetConfig 32 static
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+stm32f7xx_hal_tim.c:6762:13:TIM_ITRx_SetConfig 24 static
+stm32f7xx_hal_tim.c:6792:6:TIM_ETR_SetConfig 32 static
+stm32f7xx_hal_tim.c:6824:6:TIM_CCxChannelCmd 32 static
--- /dev/null
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: \
+ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_tim_ex.c:131:19:HAL_TIMEx_HallSensor_Init 48 static
+stm32f7xx_hal_tim_ex.c:223:19:HAL_TIMEx_HallSensor_DeInit 16 static
+stm32f7xx_hal_tim_ex.c:259:13:HAL_TIMEx_HallSensor_MspInit 16 static
+stm32f7xx_hal_tim_ex.c:274:13:HAL_TIMEx_HallSensor_MspDeInit 16 static
+stm32f7xx_hal_tim_ex.c:289:19:HAL_TIMEx_HallSensor_Start 24 static
+stm32f7xx_hal_tim_ex.c:316:19:HAL_TIMEx_HallSensor_Stop 16 static
+stm32f7xx_hal_tim_ex.c:337:19:HAL_TIMEx_HallSensor_Start_IT 24 static
+stm32f7xx_hal_tim_ex.c:367:19:HAL_TIMEx_HallSensor_Stop_IT 16 static
+stm32f7xx_hal_tim_ex.c:393:19:HAL_TIMEx_HallSensor_Start_DMA 32 static
+stm32f7xx_hal_tim_ex.c:453:19:HAL_TIMEx_HallSensor_Stop_DMA 16 static
+stm32f7xx_hal_tim_ex.c:509:19:HAL_TIMEx_OCN_Start 24 static
+stm32f7xx_hal_tim_ex.c:544:19:HAL_TIMEx_OCN_Stop 16 static
+stm32f7xx_hal_tim_ex.c:573:19:HAL_TIMEx_OCN_Start_IT 24 static
+stm32f7xx_hal_tim_ex.c:639:19:HAL_TIMEx_OCN_Stop_IT 24 static
+stm32f7xx_hal_tim_ex.c:705:19:HAL_TIMEx_OCN_Start_DMA 32 static
+stm32f7xx_hal_tim_ex.c:823:19:HAL_TIMEx_OCN_Stop_DMA 16 static
+stm32f7xx_hal_tim_ex.c:918:19:HAL_TIMEx_PWMN_Start 24 static
+stm32f7xx_hal_tim_ex.c:952:19:HAL_TIMEx_PWMN_Stop 16 static
+stm32f7xx_hal_tim_ex.c:981:19:HAL_TIMEx_PWMN_Start_IT 24 static
+stm32f7xx_hal_tim_ex.c:1046:19:HAL_TIMEx_PWMN_Stop_IT 24 static
+stm32f7xx_hal_tim_ex.c:1113:19:HAL_TIMEx_PWMN_Start_DMA 32 static
+stm32f7xx_hal_tim_ex.c:1230:19:HAL_TIMEx_PWMN_Stop_DMA 16 static
+stm32f7xx_hal_tim_ex.c:1313:19:HAL_TIMEx_OnePulseN_Start 16 static
+stm32f7xx_hal_tim_ex.c:1338:19:HAL_TIMEx_OnePulseN_Stop 16 static
+stm32f7xx_hal_tim_ex.c:1367:19:HAL_TIMEx_OnePulseN_Start_IT 16 static
+stm32f7xx_hal_tim_ex.c:1398:19:HAL_TIMEx_OnePulseN_Stop_IT 16 static
+stm32f7xx_hal_tim_ex.c:1469:19:HAL_TIMEx_ConfigCommutEvent 24 static
+stm32f7xx_hal_tim_ex.c:1524:19:HAL_TIMEx_ConfigCommutEvent_IT 24 static
+stm32f7xx_hal_tim_ex.c:1580:19:HAL_TIMEx_ConfigCommutEvent_DMA 24 static
+stm32f7xx_hal_tim_ex.c:1628:19:HAL_TIMEx_MasterConfigSynchronization 24 static
+stm32f7xx_hal_tim_ex.c:1695:19:HAL_TIMEx_ConfigBreakDeadTime 24 static
+stm32f7xx_hal_tim_ex.c:1760:19:HAL_TIMEx_ConfigBreakInput 48 static
+stm32f7xx_hal_tim_ex.c:1887:19:HAL_TIMEx_RemapConfig 16 static
+stm32f7xx_hal_tim_ex.c:1916:19:HAL_TIMEx_GroupChannel5 16 static
+stm32f7xx_hal_tim_ex.c:1966:13:HAL_TIMEx_CommutCallback 16 static
+stm32f7xx_hal_tim_ex.c:1980:13:HAL_TIMEx_CommutHalfCpltCallback 16 static
+stm32f7xx_hal_tim_ex.c:1995:13:HAL_TIMEx_BreakCallback 16 static
+stm32f7xx_hal_tim_ex.c:2010:13:HAL_TIMEx_Break2Callback 16 static
+stm32f7xx_hal_tim_ex.c:2043:22:HAL_TIMEx_HallSensor_GetState 16 static
+stm32f7xx_hal_tim_ex.c:2066:6:TIMEx_DMACommutationCplt 24 static
+stm32f7xx_hal_tim_ex.c:2085:6:TIMEx_DMACommutationHalfCplt 24 static
+stm32f7xx_hal_tim_ex.c:2112:13:TIM_CCxNChannelCmd 32 static
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
+../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
+
+OBJS += \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o
+
+C_DEPS += \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \
+./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
--- /dev/null
+Src/main.o: ../Src/main.c ../Inc/main.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Inc/main.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+main.c:71:5:main 16 static
+main.c:139:6:SystemClock_Config 88 static
+main.c:178:13:MX_TIM2_Init 56 static
+main.c:227:13:MX_TIM5_Init 56 static
+main.c:276:13:MX_GPIO_Init 16 static
+main.c:293:6:Error_Handler 4 static
--- /dev/null
+Src/stm32f7xx_hal_msp.o: ../Src/stm32f7xx_hal_msp.c ../Inc/main.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Inc/main.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+stm32f7xx_hal_msp.c:64:6:HAL_MspInit 16 static
+stm32f7xx_hal_msp.c:86:6:HAL_TIM_Encoder_MspInit 56 static
+stm32f7xx_hal_msp.c:154:6:HAL_TIM_Encoder_MspDeInit 16 static
--- /dev/null
+Src/stm32f7xx_it.o: ../Src/stm32f7xx_it.c ../Inc/main.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \
+ ../Inc/stm32f7xx_it.h
+
+../Inc/main.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
+
+../Inc/stm32f7xx_it.h:
--- /dev/null
+stm32f7xx_it.c:70:6:NMI_Handler 4 static
+stm32f7xx_it.c:83:6:HardFault_Handler 4 static
+stm32f7xx_it.c:98:6:MemManage_Handler 4 static
+stm32f7xx_it.c:113:6:BusFault_Handler 4 static
+stm32f7xx_it.c:128:6:UsageFault_Handler 4 static
+stm32f7xx_it.c:143:6:SVC_Handler 4 static
+stm32f7xx_it.c:156:6:DebugMon_Handler 4 static
+stm32f7xx_it.c:169:6:PendSV_Handler 4 static
+stm32f7xx_it.c:182:6:SysTick_Handler 8 static
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Src/main.c \
+../Src/stm32f7xx_hal_msp.c \
+../Src/stm32f7xx_it.c \
+../Src/syscalls.c \
+../Src/sysmem.c \
+../Src/system_stm32f7xx.c
+
+OBJS += \
+./Src/main.o \
+./Src/stm32f7xx_hal_msp.o \
+./Src/stm32f7xx_it.o \
+./Src/syscalls.o \
+./Src/sysmem.o \
+./Src/system_stm32f7xx.o
+
+C_DEPS += \
+./Src/main.d \
+./Src/stm32f7xx_hal_msp.d \
+./Src/stm32f7xx_it.d \
+./Src/syscalls.d \
+./Src/sysmem.d \
+./Src/system_stm32f7xx.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Src/main.o: ../Src/main.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Src/stm32f7xx_hal_msp.o: ../Src/stm32f7xx_hal_msp.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Src/stm32f7xx_it.o: ../Src/stm32f7xx_it.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Src/syscalls.o: ../Src/syscalls.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Src/sysmem.o: ../Src/sysmem.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+Src/system_stm32f7xx.o: ../Src/system_stm32f7xx.c
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Inc -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
--- /dev/null
+Src/syscalls.o: ../Src/syscalls.c
--- /dev/null
+syscalls.c:73:6:initialise_monitor_handles 4 static
+syscalls.c:77:5:_getpid 4 static
+syscalls.c:82:5:_kill 16 static
+syscalls.c:88:6:_exit 16 static
+syscalls.c:94:27:_read 32 static
+syscalls.c:106:27:_write 32 static
+syscalls.c:117:5:_close 16 static
+syscalls.c:123:5:_fstat 16 static
+syscalls.c:129:5:_isatty 16 static
+syscalls.c:134:5:_lseek 24 static
+syscalls.c:139:5:_open 12 static
+syscalls.c:145:5:_wait 16 static
+syscalls.c:151:5:_unlink 16 static
+syscalls.c:157:5:_times 16 static
+syscalls.c:162:5:_stat 16 static
+syscalls.c:168:5:_link 16 static
+syscalls.c:174:5:_fork 8 static
+syscalls.c:180:5:_execve 24 static
--- /dev/null
+Src/sysmem.o: ../Src/sysmem.c
--- /dev/null
+sysmem.c:63:9:_sbrk 24 static
--- /dev/null
+Src/system_stm32f7xx.o: ../Src/system_stm32f7xx.c \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \
+ ../Inc/stm32f7xx_hal_conf.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \
+ ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h:
+
+../Drivers/CMSIS/Include/core_cm7.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Include/mpu_armv7.h:
+
+../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h:
+
+../Inc/stm32f7xx_hal_conf.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h:
+
+../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h:
--- /dev/null
+system_stm32f7xx.c:150:6:SystemInit 4 static
+system_stm32f7xx.c:219:6:SystemCoreClockUpdate 32 static
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+S_SRCS += \
+../Startup/startup_stm32f767zitx.s
+
+OBJS += \
+./Startup/startup_stm32f767zitx.o
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Startup/%.o: ../Startup/%.s
+ arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -I../ -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
+
--- /dev/null
+
+encoder.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 1 .text 00001b28 080001f8 080001f8 000101f8 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 2 .rodata 00000010 08001d20 08001d20 00011d20 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 3 .ARM.extab 00000000 08001d30 08001d30 0002000c 2**0
+ CONTENTS
+ 4 .ARM 00000008 08001d30 08001d30 00011d30 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 5 .preinit_array 00000000 08001d38 08001d38 0002000c 2**0
+ CONTENTS, ALLOC, LOAD, DATA
+ 6 .init_array 00000004 08001d38 08001d38 00011d38 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 7 .fini_array 00000004 08001d3c 08001d3c 00011d3c 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 8 .data 0000000c 20000000 08001d40 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 9 .bss 000000a0 2000000c 08001d4c 0002000c 2**2
+ ALLOC
+ 10 ._user_heap_stack 00000604 200000ac 08001d4c 000200ac 2**0
+ ALLOC
+ 11 .ARM.attributes 0000002e 00000000 00000000 0002000c 2**0
+ CONTENTS, READONLY
+ 12 .debug_info 000084ef 00000000 00000000 0002003a 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 13 .debug_abbrev 00001303 00000000 00000000 00028529 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 14 .debug_aranges 00000950 00000000 00000000 00029830 2**3
+ CONTENTS, READONLY, DEBUGGING
+ 15 .debug_ranges 000008a8 00000000 00000000 0002a180 2**3
+ CONTENTS, READONLY, DEBUGGING
+ 16 .debug_macro 00025363 00000000 00000000 0002aa28 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 17 .debug_line 0000682c 00000000 00000000 0004fd8b 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 18 .debug_str 000eb673 00000000 00000000 000565b7 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 19 .comment 0000007b 00000000 00000000 00141c2a 2**0
+ CONTENTS, READONLY
+ 20 .debug_frame 000026bc 00000000 00000000 00141ca8 2**2
+ CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+080001f8 <__do_global_dtors_aux>:
+ 80001f8: b510 push {r4, lr}
+ 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
+ 80001fc: 7823 ldrb r3, [r4, #0]
+ 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
+ 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
+ 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
+ 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
+ 8000206: f3af 8000 nop.w
+ 800020a: 2301 movs r3, #1
+ 800020c: 7023 strb r3, [r4, #0]
+ 800020e: bd10 pop {r4, pc}
+ 8000210: 2000000c .word 0x2000000c
+ 8000214: 00000000 .word 0x00000000
+ 8000218: 08001d08 .word 0x08001d08
+
+0800021c <frame_dummy>:
+ 800021c: b508 push {r3, lr}
+ 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
+ 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
+ 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
+ 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
+ 8000226: f3af 8000 nop.w
+ 800022a: bd08 pop {r3, pc}
+ 800022c: 00000000 .word 0x00000000
+ 8000230: 20000010 .word 0x20000010
+ 8000234: 08001d08 .word 0x08001d08
+
+08000238 <__aeabi_uldivmod>:
+ 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
+ 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
+ 800023c: 2900 cmp r1, #0
+ 800023e: bf08 it eq
+ 8000240: 2800 cmpeq r0, #0
+ 8000242: bf1c itt ne
+ 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
+ 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
+ 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0>
+ 8000250: f1ad 0c08 sub.w ip, sp, #8
+ 8000254: e96d ce04 strd ip, lr, [sp, #-16]!
+ 8000258: f000 f806 bl 8000268 <__udivmoddi4>
+ 800025c: f8dd e004 ldr.w lr, [sp, #4]
+ 8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
+ 8000264: b004 add sp, #16
+ 8000266: 4770 bx lr
+
+08000268 <__udivmoddi4>:
+ 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 800026c: 9e08 ldr r6, [sp, #32]
+ 800026e: 4604 mov r4, r0
+ 8000270: 4688 mov r8, r1
+ 8000272: 2b00 cmp r3, #0
+ 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6>
+ 8000276: 428a cmp r2, r1
+ 8000278: 4615 mov r5, r2
+ 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4>
+ 800027c: fab2 f282 clz r2, r2
+ 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e>
+ 8000282: f1c2 0720 rsb r7, r2, #32
+ 8000286: fa01 f302 lsl.w r3, r1, r2
+ 800028a: fa20 f707 lsr.w r7, r0, r7
+ 800028e: 4095 lsls r5, r2
+ 8000290: ea47 0803 orr.w r8, r7, r3
+ 8000294: 4094 lsls r4, r2
+ 8000296: ea4f 4e15 mov.w lr, r5, lsr #16
+ 800029a: 0c23 lsrs r3, r4, #16
+ 800029c: fbb8 f7fe udiv r7, r8, lr
+ 80002a0: fa1f fc85 uxth.w ip, r5
+ 80002a4: fb0e 8817 mls r8, lr, r7, r8
+ 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16
+ 80002ac: fb07 f10c mul.w r1, r7, ip
+ 80002b0: 4299 cmp r1, r3
+ 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60>
+ 80002b4: 18eb adds r3, r5, r3
+ 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
+ 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c>
+ 80002be: 4299 cmp r1, r3
+ 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c>
+ 80002c4: 3f02 subs r7, #2
+ 80002c6: 442b add r3, r5
+ 80002c8: 1a5b subs r3, r3, r1
+ 80002ca: b2a4 uxth r4, r4
+ 80002cc: fbb3 f0fe udiv r0, r3, lr
+ 80002d0: fb0e 3310 mls r3, lr, r0, r3
+ 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16
+ 80002d8: fb00 fc0c mul.w ip, r0, ip
+ 80002dc: 45a4 cmp ip, r4
+ 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c>
+ 80002e0: 192c adds r4, r5, r4
+ 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
+ 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290>
+ 80002ea: 45a4 cmp ip, r4
+ 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290>
+ 80002f0: 3802 subs r0, #2
+ 80002f2: 442c add r4, r5
+ 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16
+ 80002f8: eba4 040c sub.w r4, r4, ip
+ 80002fc: 2700 movs r7, #0
+ 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0>
+ 8000300: 40d4 lsrs r4, r2
+ 8000302: 2300 movs r3, #0
+ 8000304: e9c6 4300 strd r4, r3, [r6]
+ 8000308: 4639 mov r1, r7
+ 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 800030e: 428b cmp r3, r1
+ 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe>
+ 8000312: 2e00 cmp r6, #0
+ 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286>
+ 8000318: 2700 movs r7, #0
+ 800031a: e9c6 0100 strd r0, r1, [r6]
+ 800031e: 4638 mov r0, r7
+ 8000320: 4639 mov r1, r7
+ 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 8000326: fab3 f783 clz r7, r3
+ 800032a: 2f00 cmp r7, #0
+ 800032c: d147 bne.n 80003be <__udivmoddi4+0x156>
+ 800032e: 428b cmp r3, r1
+ 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0>
+ 8000332: 4282 cmp r2, r0
+ 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4>
+ 8000338: 1a84 subs r4, r0, r2
+ 800033a: eb61 0303 sbc.w r3, r1, r3
+ 800033e: 2001 movs r0, #1
+ 8000340: 4698 mov r8, r3
+ 8000342: 2e00 cmp r6, #0
+ 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0>
+ 8000346: e9c6 4800 strd r4, r8, [r6]
+ 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0>
+ 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8>
+ 800034e: deff udf #255 ; 0xff
+ 8000350: fab2 f282 clz r2, r2
+ 8000354: 2a00 cmp r2, #0
+ 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210>
+ 800035a: 1b49 subs r1, r1, r5
+ 800035c: ea4f 4e15 mov.w lr, r5, lsr #16
+ 8000360: fa1f f885 uxth.w r8, r5
+ 8000364: 2701 movs r7, #1
+ 8000366: fbb1 fcfe udiv ip, r1, lr
+ 800036a: 0c23 lsrs r3, r4, #16
+ 800036c: fb0e 111c mls r1, lr, ip, r1
+ 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16
+ 8000374: fb08 f10c mul.w r1, r8, ip
+ 8000378: 4299 cmp r1, r3
+ 800037a: d907 bls.n 800038c <__udivmoddi4+0x124>
+ 800037c: 18eb adds r3, r5, r3
+ 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
+ 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122>
+ 8000384: 4299 cmp r1, r3
+ 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc>
+ 800038a: 4684 mov ip, r0
+ 800038c: 1a59 subs r1, r3, r1
+ 800038e: b2a3 uxth r3, r4
+ 8000390: fbb1 f0fe udiv r0, r1, lr
+ 8000394: fb0e 1410 mls r4, lr, r0, r1
+ 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16
+ 800039c: fb08 f800 mul.w r8, r8, r0
+ 80003a0: 45a0 cmp r8, r4
+ 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c>
+ 80003a4: 192c adds r4, r5, r4
+ 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
+ 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a>
+ 80003ac: 45a0 cmp r8, r4
+ 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6>
+ 80003b2: 4618 mov r0, r3
+ 80003b4: eba4 0408 sub.w r4, r4, r8
+ 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16
+ 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96>
+ 80003be: f1c7 0c20 rsb ip, r7, #32
+ 80003c2: 40bb lsls r3, r7
+ 80003c4: fa22 fe0c lsr.w lr, r2, ip
+ 80003c8: ea4e 0e03 orr.w lr, lr, r3
+ 80003cc: fa01 f407 lsl.w r4, r1, r7
+ 80003d0: fa20 f50c lsr.w r5, r0, ip
+ 80003d4: fa21 f30c lsr.w r3, r1, ip
+ 80003d8: ea4f 481e mov.w r8, lr, lsr #16
+ 80003dc: 4325 orrs r5, r4
+ 80003de: fbb3 f9f8 udiv r9, r3, r8
+ 80003e2: 0c2c lsrs r4, r5, #16
+ 80003e4: fb08 3319 mls r3, r8, r9, r3
+ 80003e8: fa1f fa8e uxth.w sl, lr
+ 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16
+ 80003f0: fb09 f40a mul.w r4, r9, sl
+ 80003f4: 429c cmp r4, r3
+ 80003f6: fa02 f207 lsl.w r2, r2, r7
+ 80003fa: fa00 f107 lsl.w r1, r0, r7
+ 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0>
+ 8000400: eb1e 0303 adds.w r3, lr, r3
+ 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
+ 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2>
+ 800040c: 429c cmp r4, r3
+ 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2>
+ 8000412: f1a9 0902 sub.w r9, r9, #2
+ 8000416: 4473 add r3, lr
+ 8000418: 1b1b subs r3, r3, r4
+ 800041a: b2ad uxth r5, r5
+ 800041c: fbb3 f0f8 udiv r0, r3, r8
+ 8000420: fb08 3310 mls r3, r8, r0, r3
+ 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16
+ 8000428: fb00 fa0a mul.w sl, r0, sl
+ 800042c: 45a2 cmp sl, r4
+ 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da>
+ 8000430: eb1e 0404 adds.w r4, lr, r4
+ 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
+ 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa>
+ 800043a: 45a2 cmp sl, r4
+ 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa>
+ 800043e: 3802 subs r0, #2
+ 8000440: 4474 add r4, lr
+ 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16
+ 8000446: fba0 8902 umull r8, r9, r0, r2
+ 800044a: eba4 040a sub.w r4, r4, sl
+ 800044e: 454c cmp r4, r9
+ 8000450: 46c2 mov sl, r8
+ 8000452: 464b mov r3, r9
+ 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298>
+ 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294>
+ 8000458: 2e00 cmp r6, #0
+ 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8>
+ 800045c: ebb1 050a subs.w r5, r1, sl
+ 8000460: eb64 0403 sbc.w r4, r4, r3
+ 8000464: fa04 fc0c lsl.w ip, r4, ip
+ 8000468: 40fd lsrs r5, r7
+ 800046a: 40fc lsrs r4, r7
+ 800046c: ea4c 0505 orr.w r5, ip, r5
+ 8000470: e9c6 5400 strd r5, r4, [r6]
+ 8000474: 2700 movs r7, #0
+ 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0>
+ 8000478: f1c2 0320 rsb r3, r2, #32
+ 800047c: fa20 f703 lsr.w r7, r0, r3
+ 8000480: 4095 lsls r5, r2
+ 8000482: fa01 f002 lsl.w r0, r1, r2
+ 8000486: fa21 f303 lsr.w r3, r1, r3
+ 800048a: ea4f 4e15 mov.w lr, r5, lsr #16
+ 800048e: 4338 orrs r0, r7
+ 8000490: 0c01 lsrs r1, r0, #16
+ 8000492: fbb3 f7fe udiv r7, r3, lr
+ 8000496: fa1f f885 uxth.w r8, r5
+ 800049a: fb0e 3317 mls r3, lr, r7, r3
+ 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
+ 80004a2: fb07 f308 mul.w r3, r7, r8
+ 80004a6: 428b cmp r3, r1
+ 80004a8: fa04 f402 lsl.w r4, r4, r2
+ 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256>
+ 80004ae: 1869 adds r1, r5, r1
+ 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
+ 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae>
+ 80004b6: 428b cmp r3, r1
+ 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae>
+ 80004ba: 3f02 subs r7, #2
+ 80004bc: 4429 add r1, r5
+ 80004be: 1acb subs r3, r1, r3
+ 80004c0: b281 uxth r1, r0
+ 80004c2: fbb3 f0fe udiv r0, r3, lr
+ 80004c6: fb0e 3310 mls r3, lr, r0, r3
+ 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16
+ 80004ce: fb00 f308 mul.w r3, r0, r8
+ 80004d2: 428b cmp r3, r1
+ 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e>
+ 80004d6: 1869 adds r1, r5, r1
+ 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
+ 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6>
+ 80004de: 428b cmp r3, r1
+ 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6>
+ 80004e2: 3802 subs r0, #2
+ 80004e4: 4429 add r1, r5
+ 80004e6: 1ac9 subs r1, r1, r3
+ 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16
+ 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe>
+ 80004ee: 4637 mov r7, r6
+ 80004f0: 4630 mov r0, r6
+ 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0>
+ 80004f4: 4607 mov r7, r0
+ 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60>
+ 80004f8: 4618 mov r0, r3
+ 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c>
+ 80004fc: 4541 cmp r1, r8
+ 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0>
+ 8000500: ebb8 0a02 subs.w sl, r8, r2
+ 8000504: eb69 020e sbc.w r2, r9, lr
+ 8000508: 3801 subs r0, #1
+ 800050a: 4613 mov r3, r2
+ 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0>
+ 800050e: 4660 mov r0, ip
+ 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e>
+ 8000512: 4618 mov r0, r3
+ 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da>
+ 8000516: 4667 mov r7, ip
+ 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256>
+ 800051a: 4681 mov r9, r0
+ 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0>
+ 800051e: 3802 subs r0, #2
+ 8000520: 442c add r4, r5
+ 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c>
+ 8000524: f1ac 0c02 sub.w ip, ip, #2
+ 8000528: 442b add r3, r5
+ 800052a: e72f b.n 800038c <__udivmoddi4+0x124>
+ 800052c: 4638 mov r0, r7
+ 800052e: e708 b.n 8000342 <__udivmoddi4+0xda>
+ 8000530: 4637 mov r7, r6
+ 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0>
+
+08000534 <__aeabi_idiv0>:
+ 8000534: 4770 bx lr
+ 8000536: bf00 nop
+
+08000538 <HAL_Init>:
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct HAL operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 8000538: b580 push {r7, lr}
+ 800053a: af00 add r7, sp, #0
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 800053c: 2003 movs r0, #3
+ 800053e: f000 f90b bl 8000758 <HAL_NVIC_SetPriorityGrouping>
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+ 8000542: 2000 movs r0, #0
+ 8000544: f000 f806 bl 8000554 <HAL_InitTick>
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+ 8000548: f001 fa70 bl 8001a2c <HAL_MspInit>
+
+ /* Return function status */
+ return HAL_OK;
+ 800054c: 2300 movs r3, #0
+}
+ 800054e: 4618 mov r0, r3
+ 8000550: bd80 pop {r7, pc}
+ ...
+
+08000554 <HAL_InitTick>:
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 8000554: b580 push {r7, lr}
+ 8000556: b082 sub sp, #8
+ 8000558: af00 add r7, sp, #0
+ 800055a: 6078 str r0, [r7, #4]
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 800055c: 4b12 ldr r3, [pc, #72] ; (80005a8 <HAL_InitTick+0x54>)
+ 800055e: 681a ldr r2, [r3, #0]
+ 8000560: 4b12 ldr r3, [pc, #72] ; (80005ac <HAL_InitTick+0x58>)
+ 8000562: 781b ldrb r3, [r3, #0]
+ 8000564: 4619 mov r1, r3
+ 8000566: f44f 737a mov.w r3, #1000 ; 0x3e8
+ 800056a: fbb3 f3f1 udiv r3, r3, r1
+ 800056e: fbb2 f3f3 udiv r3, r2, r3
+ 8000572: 4618 mov r0, r3
+ 8000574: f000 f917 bl 80007a6 <HAL_SYSTICK_Config>
+ 8000578: 4603 mov r3, r0
+ 800057a: 2b00 cmp r3, #0
+ 800057c: d001 beq.n 8000582 <HAL_InitTick+0x2e>
+ {
+ return HAL_ERROR;
+ 800057e: 2301 movs r3, #1
+ 8000580: e00e b.n 80005a0 <HAL_InitTick+0x4c>
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 8000582: 687b ldr r3, [r7, #4]
+ 8000584: 2b0f cmp r3, #15
+ 8000586: d80a bhi.n 800059e <HAL_InitTick+0x4a>
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 8000588: 2200 movs r2, #0
+ 800058a: 6879 ldr r1, [r7, #4]
+ 800058c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8000590: f000 f8ed bl 800076e <HAL_NVIC_SetPriority>
+ uwTickPrio = TickPriority;
+ 8000594: 4a06 ldr r2, [pc, #24] ; (80005b0 <HAL_InitTick+0x5c>)
+ 8000596: 687b ldr r3, [r7, #4]
+ 8000598: 6013 str r3, [r2, #0]
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ 800059a: 2300 movs r3, #0
+ 800059c: e000 b.n 80005a0 <HAL_InitTick+0x4c>
+ return HAL_ERROR;
+ 800059e: 2301 movs r3, #1
+}
+ 80005a0: 4618 mov r0, r3
+ 80005a2: 3708 adds r7, #8
+ 80005a4: 46bd mov sp, r7
+ 80005a6: bd80 pop {r7, pc}
+ 80005a8: 20000008 .word 0x20000008
+ 80005ac: 20000004 .word 0x20000004
+ 80005b0: 20000000 .word 0x20000000
+
+080005b4 <HAL_IncTick>:
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ 80005b4: b480 push {r7}
+ 80005b6: af00 add r7, sp, #0
+ uwTick += uwTickFreq;
+ 80005b8: 4b06 ldr r3, [pc, #24] ; (80005d4 <HAL_IncTick+0x20>)
+ 80005ba: 781b ldrb r3, [r3, #0]
+ 80005bc: 461a mov r2, r3
+ 80005be: 4b06 ldr r3, [pc, #24] ; (80005d8 <HAL_IncTick+0x24>)
+ 80005c0: 681b ldr r3, [r3, #0]
+ 80005c2: 4413 add r3, r2
+ 80005c4: 4a04 ldr r2, [pc, #16] ; (80005d8 <HAL_IncTick+0x24>)
+ 80005c6: 6013 str r3, [r2, #0]
+}
+ 80005c8: bf00 nop
+ 80005ca: 46bd mov sp, r7
+ 80005cc: f85d 7b04 ldr.w r7, [sp], #4
+ 80005d0: 4770 bx lr
+ 80005d2: bf00 nop
+ 80005d4: 20000004 .word 0x20000004
+ 80005d8: 20000028 .word 0x20000028
+
+080005dc <HAL_GetTick>:
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ 80005dc: b480 push {r7}
+ 80005de: af00 add r7, sp, #0
+ return uwTick;
+ 80005e0: 4b03 ldr r3, [pc, #12] ; (80005f0 <HAL_GetTick+0x14>)
+ 80005e2: 681b ldr r3, [r3, #0]
+}
+ 80005e4: 4618 mov r0, r3
+ 80005e6: 46bd mov sp, r7
+ 80005e8: f85d 7b04 ldr.w r7, [sp], #4
+ 80005ec: 4770 bx lr
+ 80005ee: bf00 nop
+ 80005f0: 20000028 .word 0x20000028
+
+080005f4 <__NVIC_SetPriorityGrouping>:
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 80005f4: b480 push {r7}
+ 80005f6: b085 sub sp, #20
+ 80005f8: af00 add r7, sp, #0
+ 80005fa: 6078 str r0, [r7, #4]
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 80005fc: 687b ldr r3, [r7, #4]
+ 80005fe: f003 0307 and.w r3, r3, #7
+ 8000602: 60fb str r3, [r7, #12]
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ 8000604: 4b0b ldr r3, [pc, #44] ; (8000634 <__NVIC_SetPriorityGrouping+0x40>)
+ 8000606: 68db ldr r3, [r3, #12]
+ 8000608: 60bb str r3, [r7, #8]
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ 800060a: 68ba ldr r2, [r7, #8]
+ 800060c: f64f 03ff movw r3, #63743 ; 0xf8ff
+ 8000610: 4013 ands r3, r2
+ 8000612: 60bb str r3, [r7, #8]
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ 8000614: 68fb ldr r3, [r7, #12]
+ 8000616: 021a lsls r2, r3, #8
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 8000618: 68bb ldr r3, [r7, #8]
+ 800061a: 431a orrs r2, r3
+ reg_value = (reg_value |
+ 800061c: 4b06 ldr r3, [pc, #24] ; (8000638 <__NVIC_SetPriorityGrouping+0x44>)
+ 800061e: 4313 orrs r3, r2
+ 8000620: 60bb str r3, [r7, #8]
+ SCB->AIRCR = reg_value;
+ 8000622: 4a04 ldr r2, [pc, #16] ; (8000634 <__NVIC_SetPriorityGrouping+0x40>)
+ 8000624: 68bb ldr r3, [r7, #8]
+ 8000626: 60d3 str r3, [r2, #12]
+}
+ 8000628: bf00 nop
+ 800062a: 3714 adds r7, #20
+ 800062c: 46bd mov sp, r7
+ 800062e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000632: 4770 bx lr
+ 8000634: e000ed00 .word 0xe000ed00
+ 8000638: 05fa0000 .word 0x05fa0000
+
+0800063c <__NVIC_GetPriorityGrouping>:
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ 800063c: b480 push {r7}
+ 800063e: af00 add r7, sp, #0
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 8000640: 4b04 ldr r3, [pc, #16] ; (8000654 <__NVIC_GetPriorityGrouping+0x18>)
+ 8000642: 68db ldr r3, [r3, #12]
+ 8000644: 0a1b lsrs r3, r3, #8
+ 8000646: f003 0307 and.w r3, r3, #7
+}
+ 800064a: 4618 mov r0, r3
+ 800064c: 46bd mov sp, r7
+ 800064e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000652: 4770 bx lr
+ 8000654: e000ed00 .word 0xe000ed00
+
+08000658 <__NVIC_SetPriority>:
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 8000658: b480 push {r7}
+ 800065a: b083 sub sp, #12
+ 800065c: af00 add r7, sp, #0
+ 800065e: 4603 mov r3, r0
+ 8000660: 6039 str r1, [r7, #0]
+ 8000662: 71fb strb r3, [r7, #7]
+ if ((int32_t)(IRQn) >= 0)
+ 8000664: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000668: 2b00 cmp r3, #0
+ 800066a: db0a blt.n 8000682 <__NVIC_SetPriority+0x2a>
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 800066c: 683b ldr r3, [r7, #0]
+ 800066e: b2da uxtb r2, r3
+ 8000670: 490c ldr r1, [pc, #48] ; (80006a4 <__NVIC_SetPriority+0x4c>)
+ 8000672: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000676: 0112 lsls r2, r2, #4
+ 8000678: b2d2 uxtb r2, r2
+ 800067a: 440b add r3, r1
+ 800067c: f883 2300 strb.w r2, [r3, #768] ; 0x300
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+ 8000680: e00a b.n 8000698 <__NVIC_SetPriority+0x40>
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 8000682: 683b ldr r3, [r7, #0]
+ 8000684: b2da uxtb r2, r3
+ 8000686: 4908 ldr r1, [pc, #32] ; (80006a8 <__NVIC_SetPriority+0x50>)
+ 8000688: 79fb ldrb r3, [r7, #7]
+ 800068a: f003 030f and.w r3, r3, #15
+ 800068e: 3b04 subs r3, #4
+ 8000690: 0112 lsls r2, r2, #4
+ 8000692: b2d2 uxtb r2, r2
+ 8000694: 440b add r3, r1
+ 8000696: 761a strb r2, [r3, #24]
+}
+ 8000698: bf00 nop
+ 800069a: 370c adds r7, #12
+ 800069c: 46bd mov sp, r7
+ 800069e: f85d 7b04 ldr.w r7, [sp], #4
+ 80006a2: 4770 bx lr
+ 80006a4: e000e100 .word 0xe000e100
+ 80006a8: e000ed00 .word 0xe000ed00
+
+080006ac <NVIC_EncodePriority>:
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 80006ac: b480 push {r7}
+ 80006ae: b089 sub sp, #36 ; 0x24
+ 80006b0: af00 add r7, sp, #0
+ 80006b2: 60f8 str r0, [r7, #12]
+ 80006b4: 60b9 str r1, [r7, #8]
+ 80006b6: 607a str r2, [r7, #4]
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 80006b8: 68fb ldr r3, [r7, #12]
+ 80006ba: f003 0307 and.w r3, r3, #7
+ 80006be: 61fb str r3, [r7, #28]
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ 80006c0: 69fb ldr r3, [r7, #28]
+ 80006c2: f1c3 0307 rsb r3, r3, #7
+ 80006c6: 2b04 cmp r3, #4
+ 80006c8: bf28 it cs
+ 80006ca: 2304 movcs r3, #4
+ 80006cc: 61bb str r3, [r7, #24]
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ 80006ce: 69fb ldr r3, [r7, #28]
+ 80006d0: 3304 adds r3, #4
+ 80006d2: 2b06 cmp r3, #6
+ 80006d4: d902 bls.n 80006dc <NVIC_EncodePriority+0x30>
+ 80006d6: 69fb ldr r3, [r7, #28]
+ 80006d8: 3b03 subs r3, #3
+ 80006da: e000 b.n 80006de <NVIC_EncodePriority+0x32>
+ 80006dc: 2300 movs r3, #0
+ 80006de: 617b str r3, [r7, #20]
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 80006e0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 80006e4: 69bb ldr r3, [r7, #24]
+ 80006e6: fa02 f303 lsl.w r3, r2, r3
+ 80006ea: 43da mvns r2, r3
+ 80006ec: 68bb ldr r3, [r7, #8]
+ 80006ee: 401a ands r2, r3
+ 80006f0: 697b ldr r3, [r7, #20]
+ 80006f2: 409a lsls r2, r3
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ 80006f4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
+ 80006f8: 697b ldr r3, [r7, #20]
+ 80006fa: fa01 f303 lsl.w r3, r1, r3
+ 80006fe: 43d9 mvns r1, r3
+ 8000700: 687b ldr r3, [r7, #4]
+ 8000702: 400b ands r3, r1
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8000704: 4313 orrs r3, r2
+ );
+}
+ 8000706: 4618 mov r0, r3
+ 8000708: 3724 adds r7, #36 ; 0x24
+ 800070a: 46bd mov sp, r7
+ 800070c: f85d 7b04 ldr.w r7, [sp], #4
+ 8000710: 4770 bx lr
+ ...
+
+08000714 <SysTick_Config>:
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ 8000714: b580 push {r7, lr}
+ 8000716: b082 sub sp, #8
+ 8000718: af00 add r7, sp, #0
+ 800071a: 6078 str r0, [r7, #4]
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 800071c: 687b ldr r3, [r7, #4]
+ 800071e: 3b01 subs r3, #1
+ 8000720: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
+ 8000724: d301 bcc.n 800072a <SysTick_Config+0x16>
+ {
+ return (1UL); /* Reload value impossible */
+ 8000726: 2301 movs r3, #1
+ 8000728: e00f b.n 800074a <SysTick_Config+0x36>
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ 800072a: 4a0a ldr r2, [pc, #40] ; (8000754 <SysTick_Config+0x40>)
+ 800072c: 687b ldr r3, [r7, #4]
+ 800072e: 3b01 subs r3, #1
+ 8000730: 6053 str r3, [r2, #4]
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8000732: 210f movs r1, #15
+ 8000734: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8000738: f7ff ff8e bl 8000658 <__NVIC_SetPriority>
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 800073c: 4b05 ldr r3, [pc, #20] ; (8000754 <SysTick_Config+0x40>)
+ 800073e: 2200 movs r2, #0
+ 8000740: 609a str r2, [r3, #8]
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 8000742: 4b04 ldr r3, [pc, #16] ; (8000754 <SysTick_Config+0x40>)
+ 8000744: 2207 movs r2, #7
+ 8000746: 601a str r2, [r3, #0]
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+ 8000748: 2300 movs r3, #0
+}
+ 800074a: 4618 mov r0, r3
+ 800074c: 3708 adds r7, #8
+ 800074e: 46bd mov sp, r7
+ 8000750: bd80 pop {r7, pc}
+ 8000752: bf00 nop
+ 8000754: e000e010 .word 0xe000e010
+
+08000758 <HAL_NVIC_SetPriorityGrouping>:
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8000758: b580 push {r7, lr}
+ 800075a: b082 sub sp, #8
+ 800075c: af00 add r7, sp, #0
+ 800075e: 6078 str r0, [r7, #4]
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+ 8000760: 6878 ldr r0, [r7, #4]
+ 8000762: f7ff ff47 bl 80005f4 <__NVIC_SetPriorityGrouping>
+}
+ 8000766: bf00 nop
+ 8000768: 3708 adds r7, #8
+ 800076a: 46bd mov sp, r7
+ 800076c: bd80 pop {r7, pc}
+
+0800076e <HAL_NVIC_SetPriority>:
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 800076e: b580 push {r7, lr}
+ 8000770: b086 sub sp, #24
+ 8000772: af00 add r7, sp, #0
+ 8000774: 4603 mov r3, r0
+ 8000776: 60b9 str r1, [r7, #8]
+ 8000778: 607a str r2, [r7, #4]
+ 800077a: 73fb strb r3, [r7, #15]
+ uint32_t prioritygroup = 0x00;
+ 800077c: 2300 movs r3, #0
+ 800077e: 617b str r3, [r7, #20]
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+ 8000780: f7ff ff5c bl 800063c <__NVIC_GetPriorityGrouping>
+ 8000784: 6178 str r0, [r7, #20]
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 8000786: 687a ldr r2, [r7, #4]
+ 8000788: 68b9 ldr r1, [r7, #8]
+ 800078a: 6978 ldr r0, [r7, #20]
+ 800078c: f7ff ff8e bl 80006ac <NVIC_EncodePriority>
+ 8000790: 4602 mov r2, r0
+ 8000792: f997 300f ldrsb.w r3, [r7, #15]
+ 8000796: 4611 mov r1, r2
+ 8000798: 4618 mov r0, r3
+ 800079a: f7ff ff5d bl 8000658 <__NVIC_SetPriority>
+}
+ 800079e: bf00 nop
+ 80007a0: 3718 adds r7, #24
+ 80007a2: 46bd mov sp, r7
+ 80007a4: bd80 pop {r7, pc}
+
+080007a6 <HAL_SYSTICK_Config>:
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 80007a6: b580 push {r7, lr}
+ 80007a8: b082 sub sp, #8
+ 80007aa: af00 add r7, sp, #0
+ 80007ac: 6078 str r0, [r7, #4]
+ return SysTick_Config(TicksNumb);
+ 80007ae: 6878 ldr r0, [r7, #4]
+ 80007b0: f7ff ffb0 bl 8000714 <SysTick_Config>
+ 80007b4: 4603 mov r3, r0
+}
+ 80007b6: 4618 mov r0, r3
+ 80007b8: 3708 adds r7, #8
+ 80007ba: 46bd mov sp, r7
+ 80007bc: bd80 pop {r7, pc}
+ ...
+
+080007c0 <HAL_GPIO_Init>:
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 80007c0: b480 push {r7}
+ 80007c2: b089 sub sp, #36 ; 0x24
+ 80007c4: af00 add r7, sp, #0
+ 80007c6: 6078 str r0, [r7, #4]
+ 80007c8: 6039 str r1, [r7, #0]
+ uint32_t position = 0x00;
+ 80007ca: 2300 movs r3, #0
+ 80007cc: 61fb str r3, [r7, #28]
+ uint32_t ioposition = 0x00;
+ 80007ce: 2300 movs r3, #0
+ 80007d0: 617b str r3, [r7, #20]
+ uint32_t iocurrent = 0x00;
+ 80007d2: 2300 movs r3, #0
+ 80007d4: 613b str r3, [r7, #16]
+ uint32_t temp = 0x00;
+ 80007d6: 2300 movs r3, #0
+ 80007d8: 61bb str r3, [r7, #24]
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ for(position = 0; position < GPIO_NUMBER; position++)
+ 80007da: 2300 movs r3, #0
+ 80007dc: 61fb str r3, [r7, #28]
+ 80007de: e175 b.n 8000acc <HAL_GPIO_Init+0x30c>
+ {
+ /* Get the IO position */
+ ioposition = ((uint32_t)0x01) << position;
+ 80007e0: 2201 movs r2, #1
+ 80007e2: 69fb ldr r3, [r7, #28]
+ 80007e4: fa02 f303 lsl.w r3, r2, r3
+ 80007e8: 617b str r3, [r7, #20]
+ /* Get the current IO position */
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+ 80007ea: 683b ldr r3, [r7, #0]
+ 80007ec: 681b ldr r3, [r3, #0]
+ 80007ee: 697a ldr r2, [r7, #20]
+ 80007f0: 4013 ands r3, r2
+ 80007f2: 613b str r3, [r7, #16]
+
+ if(iocurrent == ioposition)
+ 80007f4: 693a ldr r2, [r7, #16]
+ 80007f6: 697b ldr r3, [r7, #20]
+ 80007f8: 429a cmp r2, r3
+ 80007fa: f040 8164 bne.w 8000ac6 <HAL_GPIO_Init+0x306>
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 80007fe: 683b ldr r3, [r7, #0]
+ 8000800: 685b ldr r3, [r3, #4]
+ 8000802: 2b02 cmp r3, #2
+ 8000804: d003 beq.n 800080e <HAL_GPIO_Init+0x4e>
+ 8000806: 683b ldr r3, [r7, #0]
+ 8000808: 685b ldr r3, [r3, #4]
+ 800080a: 2b12 cmp r3, #18
+ 800080c: d123 bne.n 8000856 <HAL_GPIO_Init+0x96>
+ {
+ /* Check the Alternate function parameter */
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3];
+ 800080e: 69fb ldr r3, [r7, #28]
+ 8000810: 08da lsrs r2, r3, #3
+ 8000812: 687b ldr r3, [r7, #4]
+ 8000814: 3208 adds r2, #8
+ 8000816: f853 3022 ldr.w r3, [r3, r2, lsl #2]
+ 800081a: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ 800081c: 69fb ldr r3, [r7, #28]
+ 800081e: f003 0307 and.w r3, r3, #7
+ 8000822: 009b lsls r3, r3, #2
+ 8000824: 220f movs r2, #15
+ 8000826: fa02 f303 lsl.w r3, r2, r3
+ 800082a: 43db mvns r3, r3
+ 800082c: 69ba ldr r2, [r7, #24]
+ 800082e: 4013 ands r3, r2
+ 8000830: 61bb str r3, [r7, #24]
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ 8000832: 683b ldr r3, [r7, #0]
+ 8000834: 691a ldr r2, [r3, #16]
+ 8000836: 69fb ldr r3, [r7, #28]
+ 8000838: f003 0307 and.w r3, r3, #7
+ 800083c: 009b lsls r3, r3, #2
+ 800083e: fa02 f303 lsl.w r3, r2, r3
+ 8000842: 69ba ldr r2, [r7, #24]
+ 8000844: 4313 orrs r3, r2
+ 8000846: 61bb str r3, [r7, #24]
+ GPIOx->AFR[position >> 3] = temp;
+ 8000848: 69fb ldr r3, [r7, #28]
+ 800084a: 08da lsrs r2, r3, #3
+ 800084c: 687b ldr r3, [r7, #4]
+ 800084e: 3208 adds r2, #8
+ 8000850: 69b9 ldr r1, [r7, #24]
+ 8000852: f843 1022 str.w r1, [r3, r2, lsl #2]
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ 8000856: 687b ldr r3, [r7, #4]
+ 8000858: 681b ldr r3, [r3, #0]
+ 800085a: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ 800085c: 69fb ldr r3, [r7, #28]
+ 800085e: 005b lsls r3, r3, #1
+ 8000860: 2203 movs r2, #3
+ 8000862: fa02 f303 lsl.w r3, r2, r3
+ 8000866: 43db mvns r3, r3
+ 8000868: 69ba ldr r2, [r7, #24]
+ 800086a: 4013 ands r3, r2
+ 800086c: 61bb str r3, [r7, #24]
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ 800086e: 683b ldr r3, [r7, #0]
+ 8000870: 685b ldr r3, [r3, #4]
+ 8000872: f003 0203 and.w r2, r3, #3
+ 8000876: 69fb ldr r3, [r7, #28]
+ 8000878: 005b lsls r3, r3, #1
+ 800087a: fa02 f303 lsl.w r3, r2, r3
+ 800087e: 69ba ldr r2, [r7, #24]
+ 8000880: 4313 orrs r3, r2
+ 8000882: 61bb str r3, [r7, #24]
+ GPIOx->MODER = temp;
+ 8000884: 687b ldr r3, [r7, #4]
+ 8000886: 69ba ldr r2, [r7, #24]
+ 8000888: 601a str r2, [r3, #0]
+
+ /* In case of Output or Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 800088a: 683b ldr r3, [r7, #0]
+ 800088c: 685b ldr r3, [r3, #4]
+ 800088e: 2b01 cmp r3, #1
+ 8000890: d00b beq.n 80008aa <HAL_GPIO_Init+0xea>
+ 8000892: 683b ldr r3, [r7, #0]
+ 8000894: 685b ldr r3, [r3, #4]
+ 8000896: 2b02 cmp r3, #2
+ 8000898: d007 beq.n 80008aa <HAL_GPIO_Init+0xea>
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 800089a: 683b ldr r3, [r7, #0]
+ 800089c: 685b ldr r3, [r3, #4]
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 800089e: 2b11 cmp r3, #17
+ 80008a0: d003 beq.n 80008aa <HAL_GPIO_Init+0xea>
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 80008a2: 683b ldr r3, [r7, #0]
+ 80008a4: 685b ldr r3, [r3, #4]
+ 80008a6: 2b12 cmp r3, #18
+ 80008a8: d130 bne.n 800090c <HAL_GPIO_Init+0x14c>
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ 80008aa: 687b ldr r3, [r7, #4]
+ 80008ac: 689b ldr r3, [r3, #8]
+ 80008ae: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ 80008b0: 69fb ldr r3, [r7, #28]
+ 80008b2: 005b lsls r3, r3, #1
+ 80008b4: 2203 movs r2, #3
+ 80008b6: fa02 f303 lsl.w r3, r2, r3
+ 80008ba: 43db mvns r3, r3
+ 80008bc: 69ba ldr r2, [r7, #24]
+ 80008be: 4013 ands r3, r2
+ 80008c0: 61bb str r3, [r7, #24]
+ temp |= (GPIO_Init->Speed << (position * 2));
+ 80008c2: 683b ldr r3, [r7, #0]
+ 80008c4: 68da ldr r2, [r3, #12]
+ 80008c6: 69fb ldr r3, [r7, #28]
+ 80008c8: 005b lsls r3, r3, #1
+ 80008ca: fa02 f303 lsl.w r3, r2, r3
+ 80008ce: 69ba ldr r2, [r7, #24]
+ 80008d0: 4313 orrs r3, r2
+ 80008d2: 61bb str r3, [r7, #24]
+ GPIOx->OSPEEDR = temp;
+ 80008d4: 687b ldr r3, [r7, #4]
+ 80008d6: 69ba ldr r2, [r7, #24]
+ 80008d8: 609a str r2, [r3, #8]
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ 80008da: 687b ldr r3, [r7, #4]
+ 80008dc: 685b ldr r3, [r3, #4]
+ 80008de: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 80008e0: 2201 movs r2, #1
+ 80008e2: 69fb ldr r3, [r7, #28]
+ 80008e4: fa02 f303 lsl.w r3, r2, r3
+ 80008e8: 43db mvns r3, r3
+ 80008ea: 69ba ldr r2, [r7, #24]
+ 80008ec: 4013 ands r3, r2
+ 80008ee: 61bb str r3, [r7, #24]
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ 80008f0: 683b ldr r3, [r7, #0]
+ 80008f2: 685b ldr r3, [r3, #4]
+ 80008f4: 091b lsrs r3, r3, #4
+ 80008f6: f003 0201 and.w r2, r3, #1
+ 80008fa: 69fb ldr r3, [r7, #28]
+ 80008fc: fa02 f303 lsl.w r3, r2, r3
+ 8000900: 69ba ldr r2, [r7, #24]
+ 8000902: 4313 orrs r3, r2
+ 8000904: 61bb str r3, [r7, #24]
+ GPIOx->OTYPER = temp;
+ 8000906: 687b ldr r3, [r7, #4]
+ 8000908: 69ba ldr r2, [r7, #24]
+ 800090a: 605a str r2, [r3, #4]
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ 800090c: 687b ldr r3, [r7, #4]
+ 800090e: 68db ldr r3, [r3, #12]
+ 8000910: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ 8000912: 69fb ldr r3, [r7, #28]
+ 8000914: 005b lsls r3, r3, #1
+ 8000916: 2203 movs r2, #3
+ 8000918: fa02 f303 lsl.w r3, r2, r3
+ 800091c: 43db mvns r3, r3
+ 800091e: 69ba ldr r2, [r7, #24]
+ 8000920: 4013 ands r3, r2
+ 8000922: 61bb str r3, [r7, #24]
+ temp |= ((GPIO_Init->Pull) << (position * 2));
+ 8000924: 683b ldr r3, [r7, #0]
+ 8000926: 689a ldr r2, [r3, #8]
+ 8000928: 69fb ldr r3, [r7, #28]
+ 800092a: 005b lsls r3, r3, #1
+ 800092c: fa02 f303 lsl.w r3, r2, r3
+ 8000930: 69ba ldr r2, [r7, #24]
+ 8000932: 4313 orrs r3, r2
+ 8000934: 61bb str r3, [r7, #24]
+ GPIOx->PUPDR = temp;
+ 8000936: 687b ldr r3, [r7, #4]
+ 8000938: 69ba ldr r2, [r7, #24]
+ 800093a: 60da str r2, [r3, #12]
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ 800093c: 683b ldr r3, [r7, #0]
+ 800093e: 685b ldr r3, [r3, #4]
+ 8000940: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000944: 2b00 cmp r3, #0
+ 8000946: f000 80be beq.w 8000ac6 <HAL_GPIO_Init+0x306>
+ {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 800094a: 4b65 ldr r3, [pc, #404] ; (8000ae0 <HAL_GPIO_Init+0x320>)
+ 800094c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800094e: 4a64 ldr r2, [pc, #400] ; (8000ae0 <HAL_GPIO_Init+0x320>)
+ 8000950: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000954: 6453 str r3, [r2, #68] ; 0x44
+ 8000956: 4b62 ldr r3, [pc, #392] ; (8000ae0 <HAL_GPIO_Init+0x320>)
+ 8000958: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800095a: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 800095e: 60fb str r3, [r7, #12]
+ 8000960: 68fb ldr r3, [r7, #12]
+
+ temp = SYSCFG->EXTICR[position >> 2];
+ 8000962: 4a60 ldr r2, [pc, #384] ; (8000ae4 <HAL_GPIO_Init+0x324>)
+ 8000964: 69fb ldr r3, [r7, #28]
+ 8000966: 089b lsrs r3, r3, #2
+ 8000968: 3302 adds r3, #2
+ 800096a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
+ 800096e: 61bb str r3, [r7, #24]
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 8000970: 69fb ldr r3, [r7, #28]
+ 8000972: f003 0303 and.w r3, r3, #3
+ 8000976: 009b lsls r3, r3, #2
+ 8000978: 220f movs r2, #15
+ 800097a: fa02 f303 lsl.w r3, r2, r3
+ 800097e: 43db mvns r3, r3
+ 8000980: 69ba ldr r2, [r7, #24]
+ 8000982: 4013 ands r3, r2
+ 8000984: 61bb str r3, [r7, #24]
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 8000986: 687b ldr r3, [r7, #4]
+ 8000988: 4a57 ldr r2, [pc, #348] ; (8000ae8 <HAL_GPIO_Init+0x328>)
+ 800098a: 4293 cmp r3, r2
+ 800098c: d037 beq.n 80009fe <HAL_GPIO_Init+0x23e>
+ 800098e: 687b ldr r3, [r7, #4]
+ 8000990: 4a56 ldr r2, [pc, #344] ; (8000aec <HAL_GPIO_Init+0x32c>)
+ 8000992: 4293 cmp r3, r2
+ 8000994: d031 beq.n 80009fa <HAL_GPIO_Init+0x23a>
+ 8000996: 687b ldr r3, [r7, #4]
+ 8000998: 4a55 ldr r2, [pc, #340] ; (8000af0 <HAL_GPIO_Init+0x330>)
+ 800099a: 4293 cmp r3, r2
+ 800099c: d02b beq.n 80009f6 <HAL_GPIO_Init+0x236>
+ 800099e: 687b ldr r3, [r7, #4]
+ 80009a0: 4a54 ldr r2, [pc, #336] ; (8000af4 <HAL_GPIO_Init+0x334>)
+ 80009a2: 4293 cmp r3, r2
+ 80009a4: d025 beq.n 80009f2 <HAL_GPIO_Init+0x232>
+ 80009a6: 687b ldr r3, [r7, #4]
+ 80009a8: 4a53 ldr r2, [pc, #332] ; (8000af8 <HAL_GPIO_Init+0x338>)
+ 80009aa: 4293 cmp r3, r2
+ 80009ac: d01f beq.n 80009ee <HAL_GPIO_Init+0x22e>
+ 80009ae: 687b ldr r3, [r7, #4]
+ 80009b0: 4a52 ldr r2, [pc, #328] ; (8000afc <HAL_GPIO_Init+0x33c>)
+ 80009b2: 4293 cmp r3, r2
+ 80009b4: d019 beq.n 80009ea <HAL_GPIO_Init+0x22a>
+ 80009b6: 687b ldr r3, [r7, #4]
+ 80009b8: 4a51 ldr r2, [pc, #324] ; (8000b00 <HAL_GPIO_Init+0x340>)
+ 80009ba: 4293 cmp r3, r2
+ 80009bc: d013 beq.n 80009e6 <HAL_GPIO_Init+0x226>
+ 80009be: 687b ldr r3, [r7, #4]
+ 80009c0: 4a50 ldr r2, [pc, #320] ; (8000b04 <HAL_GPIO_Init+0x344>)
+ 80009c2: 4293 cmp r3, r2
+ 80009c4: d00d beq.n 80009e2 <HAL_GPIO_Init+0x222>
+ 80009c6: 687b ldr r3, [r7, #4]
+ 80009c8: 4a4f ldr r2, [pc, #316] ; (8000b08 <HAL_GPIO_Init+0x348>)
+ 80009ca: 4293 cmp r3, r2
+ 80009cc: d007 beq.n 80009de <HAL_GPIO_Init+0x21e>
+ 80009ce: 687b ldr r3, [r7, #4]
+ 80009d0: 4a4e ldr r2, [pc, #312] ; (8000b0c <HAL_GPIO_Init+0x34c>)
+ 80009d2: 4293 cmp r3, r2
+ 80009d4: d101 bne.n 80009da <HAL_GPIO_Init+0x21a>
+ 80009d6: 2309 movs r3, #9
+ 80009d8: e012 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009da: 230a movs r3, #10
+ 80009dc: e010 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009de: 2308 movs r3, #8
+ 80009e0: e00e b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009e2: 2307 movs r3, #7
+ 80009e4: e00c b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009e6: 2306 movs r3, #6
+ 80009e8: e00a b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009ea: 2305 movs r3, #5
+ 80009ec: e008 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009ee: 2304 movs r3, #4
+ 80009f0: e006 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009f2: 2303 movs r3, #3
+ 80009f4: e004 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009f6: 2302 movs r3, #2
+ 80009f8: e002 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009fa: 2301 movs r3, #1
+ 80009fc: e000 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009fe: 2300 movs r3, #0
+ 8000a00: 69fa ldr r2, [r7, #28]
+ 8000a02: f002 0203 and.w r2, r2, #3
+ 8000a06: 0092 lsls r2, r2, #2
+ 8000a08: 4093 lsls r3, r2
+ 8000a0a: 69ba ldr r2, [r7, #24]
+ 8000a0c: 4313 orrs r3, r2
+ 8000a0e: 61bb str r3, [r7, #24]
+ SYSCFG->EXTICR[position >> 2] = temp;
+ 8000a10: 4934 ldr r1, [pc, #208] ; (8000ae4 <HAL_GPIO_Init+0x324>)
+ 8000a12: 69fb ldr r3, [r7, #28]
+ 8000a14: 089b lsrs r3, r3, #2
+ 8000a16: 3302 adds r3, #2
+ 8000a18: 69ba ldr r2, [r7, #24]
+ 8000a1a: f841 2023 str.w r2, [r1, r3, lsl #2]
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ 8000a1e: 4b3c ldr r3, [pc, #240] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a20: 681b ldr r3, [r3, #0]
+ 8000a22: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000a24: 693b ldr r3, [r7, #16]
+ 8000a26: 43db mvns r3, r3
+ 8000a28: 69ba ldr r2, [r7, #24]
+ 8000a2a: 4013 ands r3, r2
+ 8000a2c: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 8000a2e: 683b ldr r3, [r7, #0]
+ 8000a30: 685b ldr r3, [r3, #4]
+ 8000a32: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8000a36: 2b00 cmp r3, #0
+ 8000a38: d003 beq.n 8000a42 <HAL_GPIO_Init+0x282>
+ {
+ temp |= iocurrent;
+ 8000a3a: 69ba ldr r2, [r7, #24]
+ 8000a3c: 693b ldr r3, [r7, #16]
+ 8000a3e: 4313 orrs r3, r2
+ 8000a40: 61bb str r3, [r7, #24]
+ }
+ EXTI->IMR = temp;
+ 8000a42: 4a33 ldr r2, [pc, #204] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a44: 69bb ldr r3, [r7, #24]
+ 8000a46: 6013 str r3, [r2, #0]
+
+ temp = EXTI->EMR;
+ 8000a48: 4b31 ldr r3, [pc, #196] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a4a: 685b ldr r3, [r3, #4]
+ 8000a4c: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000a4e: 693b ldr r3, [r7, #16]
+ 8000a50: 43db mvns r3, r3
+ 8000a52: 69ba ldr r2, [r7, #24]
+ 8000a54: 4013 ands r3, r2
+ 8000a56: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 8000a58: 683b ldr r3, [r7, #0]
+ 8000a5a: 685b ldr r3, [r3, #4]
+ 8000a5c: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000a60: 2b00 cmp r3, #0
+ 8000a62: d003 beq.n 8000a6c <HAL_GPIO_Init+0x2ac>
+ {
+ temp |= iocurrent;
+ 8000a64: 69ba ldr r2, [r7, #24]
+ 8000a66: 693b ldr r3, [r7, #16]
+ 8000a68: 4313 orrs r3, r2
+ 8000a6a: 61bb str r3, [r7, #24]
+ }
+ EXTI->EMR = temp;
+ 8000a6c: 4a28 ldr r2, [pc, #160] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a6e: 69bb ldr r3, [r7, #24]
+ 8000a70: 6053 str r3, [r2, #4]
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ 8000a72: 4b27 ldr r3, [pc, #156] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a74: 689b ldr r3, [r3, #8]
+ 8000a76: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000a78: 693b ldr r3, [r7, #16]
+ 8000a7a: 43db mvns r3, r3
+ 8000a7c: 69ba ldr r2, [r7, #24]
+ 8000a7e: 4013 ands r3, r2
+ 8000a80: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 8000a82: 683b ldr r3, [r7, #0]
+ 8000a84: 685b ldr r3, [r3, #4]
+ 8000a86: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8000a8a: 2b00 cmp r3, #0
+ 8000a8c: d003 beq.n 8000a96 <HAL_GPIO_Init+0x2d6>
+ {
+ temp |= iocurrent;
+ 8000a8e: 69ba ldr r2, [r7, #24]
+ 8000a90: 693b ldr r3, [r7, #16]
+ 8000a92: 4313 orrs r3, r2
+ 8000a94: 61bb str r3, [r7, #24]
+ }
+ EXTI->RTSR = temp;
+ 8000a96: 4a1e ldr r2, [pc, #120] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a98: 69bb ldr r3, [r7, #24]
+ 8000a9a: 6093 str r3, [r2, #8]
+
+ temp = EXTI->FTSR;
+ 8000a9c: 4b1c ldr r3, [pc, #112] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a9e: 68db ldr r3, [r3, #12]
+ 8000aa0: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8000aa2: 693b ldr r3, [r7, #16]
+ 8000aa4: 43db mvns r3, r3
+ 8000aa6: 69ba ldr r2, [r7, #24]
+ 8000aa8: 4013 ands r3, r2
+ 8000aaa: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 8000aac: 683b ldr r3, [r7, #0]
+ 8000aae: 685b ldr r3, [r3, #4]
+ 8000ab0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8000ab4: 2b00 cmp r3, #0
+ 8000ab6: d003 beq.n 8000ac0 <HAL_GPIO_Init+0x300>
+ {
+ temp |= iocurrent;
+ 8000ab8: 69ba ldr r2, [r7, #24]
+ 8000aba: 693b ldr r3, [r7, #16]
+ 8000abc: 4313 orrs r3, r2
+ 8000abe: 61bb str r3, [r7, #24]
+ }
+ EXTI->FTSR = temp;
+ 8000ac0: 4a13 ldr r2, [pc, #76] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000ac2: 69bb ldr r3, [r7, #24]
+ 8000ac4: 60d3 str r3, [r2, #12]
+ for(position = 0; position < GPIO_NUMBER; position++)
+ 8000ac6: 69fb ldr r3, [r7, #28]
+ 8000ac8: 3301 adds r3, #1
+ 8000aca: 61fb str r3, [r7, #28]
+ 8000acc: 69fb ldr r3, [r7, #28]
+ 8000ace: 2b0f cmp r3, #15
+ 8000ad0: f67f ae86 bls.w 80007e0 <HAL_GPIO_Init+0x20>
+ }
+ }
+ }
+}
+ 8000ad4: bf00 nop
+ 8000ad6: 3724 adds r7, #36 ; 0x24
+ 8000ad8: 46bd mov sp, r7
+ 8000ada: f85d 7b04 ldr.w r7, [sp], #4
+ 8000ade: 4770 bx lr
+ 8000ae0: 40023800 .word 0x40023800
+ 8000ae4: 40013800 .word 0x40013800
+ 8000ae8: 40020000 .word 0x40020000
+ 8000aec: 40020400 .word 0x40020400
+ 8000af0: 40020800 .word 0x40020800
+ 8000af4: 40020c00 .word 0x40020c00
+ 8000af8: 40021000 .word 0x40021000
+ 8000afc: 40021400 .word 0x40021400
+ 8000b00: 40021800 .word 0x40021800
+ 8000b04: 40021c00 .word 0x40021c00
+ 8000b08: 40022000 .word 0x40022000
+ 8000b0c: 40022400 .word 0x40022400
+ 8000b10: 40013c00 .word 0x40013c00
+
+08000b14 <HAL_RCC_OscConfig>:
+ * supported by this function. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ 8000b14: b580 push {r7, lr}
+ 8000b16: b086 sub sp, #24
+ 8000b18: af00 add r7, sp, #0
+ 8000b1a: 6078 str r0, [r7, #4]
+ uint32_t tickstart;
+ FlagStatus pwrclkchanged = RESET;
+ 8000b1c: 2300 movs r3, #0
+ 8000b1e: 75fb strb r3, [r7, #23]
+
+ /* Check Null pointer */
+ if(RCC_OscInitStruct == NULL)
+ 8000b20: 687b ldr r3, [r7, #4]
+ 8000b22: 2b00 cmp r3, #0
+ 8000b24: d101 bne.n 8000b2a <HAL_RCC_OscConfig+0x16>
+ {
+ return HAL_ERROR;
+ 8000b26: 2301 movs r3, #1
+ 8000b28: e25e b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 8000b2a: 687b ldr r3, [r7, #4]
+ 8000b2c: 681b ldr r3, [r3, #0]
+ 8000b2e: f003 0301 and.w r3, r3, #1
+ 8000b32: 2b00 cmp r3, #0
+ 8000b34: f000 8087 beq.w 8000c46 <HAL_RCC_OscConfig+0x132>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ 8000b38: 4b96 ldr r3, [pc, #600] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b3a: 689b ldr r3, [r3, #8]
+ 8000b3c: f003 030c and.w r3, r3, #12
+ 8000b40: 2b04 cmp r3, #4
+ 8000b42: d00c beq.n 8000b5e <HAL_RCC_OscConfig+0x4a>
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ 8000b44: 4b93 ldr r3, [pc, #588] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b46: 689b ldr r3, [r3, #8]
+ 8000b48: f003 030c and.w r3, r3, #12
+ 8000b4c: 2b08 cmp r3, #8
+ 8000b4e: d112 bne.n 8000b76 <HAL_RCC_OscConfig+0x62>
+ 8000b50: 4b90 ldr r3, [pc, #576] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b52: 685b ldr r3, [r3, #4]
+ 8000b54: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8000b58: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8000b5c: d10b bne.n 8000b76 <HAL_RCC_OscConfig+0x62>
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8000b5e: 4b8d ldr r3, [pc, #564] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b60: 681b ldr r3, [r3, #0]
+ 8000b62: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000b66: 2b00 cmp r3, #0
+ 8000b68: d06c beq.n 8000c44 <HAL_RCC_OscConfig+0x130>
+ 8000b6a: 687b ldr r3, [r7, #4]
+ 8000b6c: 685b ldr r3, [r3, #4]
+ 8000b6e: 2b00 cmp r3, #0
+ 8000b70: d168 bne.n 8000c44 <HAL_RCC_OscConfig+0x130>
+ {
+ return HAL_ERROR;
+ 8000b72: 2301 movs r3, #1
+ 8000b74: e238 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 8000b76: 687b ldr r3, [r7, #4]
+ 8000b78: 685b ldr r3, [r3, #4]
+ 8000b7a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8000b7e: d106 bne.n 8000b8e <HAL_RCC_OscConfig+0x7a>
+ 8000b80: 4b84 ldr r3, [pc, #528] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b82: 681b ldr r3, [r3, #0]
+ 8000b84: 4a83 ldr r2, [pc, #524] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b86: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8000b8a: 6013 str r3, [r2, #0]
+ 8000b8c: e02e b.n 8000bec <HAL_RCC_OscConfig+0xd8>
+ 8000b8e: 687b ldr r3, [r7, #4]
+ 8000b90: 685b ldr r3, [r3, #4]
+ 8000b92: 2b00 cmp r3, #0
+ 8000b94: d10c bne.n 8000bb0 <HAL_RCC_OscConfig+0x9c>
+ 8000b96: 4b7f ldr r3, [pc, #508] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b98: 681b ldr r3, [r3, #0]
+ 8000b9a: 4a7e ldr r2, [pc, #504] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b9c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8000ba0: 6013 str r3, [r2, #0]
+ 8000ba2: 4b7c ldr r3, [pc, #496] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000ba4: 681b ldr r3, [r3, #0]
+ 8000ba6: 4a7b ldr r2, [pc, #492] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000ba8: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8000bac: 6013 str r3, [r2, #0]
+ 8000bae: e01d b.n 8000bec <HAL_RCC_OscConfig+0xd8>
+ 8000bb0: 687b ldr r3, [r7, #4]
+ 8000bb2: 685b ldr r3, [r3, #4]
+ 8000bb4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
+ 8000bb8: d10c bne.n 8000bd4 <HAL_RCC_OscConfig+0xc0>
+ 8000bba: 4b76 ldr r3, [pc, #472] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bbc: 681b ldr r3, [r3, #0]
+ 8000bbe: 4a75 ldr r2, [pc, #468] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bc0: f443 2380 orr.w r3, r3, #262144 ; 0x40000
+ 8000bc4: 6013 str r3, [r2, #0]
+ 8000bc6: 4b73 ldr r3, [pc, #460] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bc8: 681b ldr r3, [r3, #0]
+ 8000bca: 4a72 ldr r2, [pc, #456] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bcc: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8000bd0: 6013 str r3, [r2, #0]
+ 8000bd2: e00b b.n 8000bec <HAL_RCC_OscConfig+0xd8>
+ 8000bd4: 4b6f ldr r3, [pc, #444] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bd6: 681b ldr r3, [r3, #0]
+ 8000bd8: 4a6e ldr r2, [pc, #440] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bda: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8000bde: 6013 str r3, [r2, #0]
+ 8000be0: 4b6c ldr r3, [pc, #432] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000be2: 681b ldr r3, [r3, #0]
+ 8000be4: 4a6b ldr r2, [pc, #428] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000be6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8000bea: 6013 str r3, [r2, #0]
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 8000bec: 687b ldr r3, [r7, #4]
+ 8000bee: 685b ldr r3, [r3, #4]
+ 8000bf0: 2b00 cmp r3, #0
+ 8000bf2: d013 beq.n 8000c1c <HAL_RCC_OscConfig+0x108>
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000bf4: f7ff fcf2 bl 80005dc <HAL_GetTick>
+ 8000bf8: 6138 str r0, [r7, #16]
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 8000bfa: e008 b.n 8000c0e <HAL_RCC_OscConfig+0xfa>
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 8000bfc: f7ff fcee bl 80005dc <HAL_GetTick>
+ 8000c00: 4602 mov r2, r0
+ 8000c02: 693b ldr r3, [r7, #16]
+ 8000c04: 1ad3 subs r3, r2, r3
+ 8000c06: 2b64 cmp r3, #100 ; 0x64
+ 8000c08: d901 bls.n 8000c0e <HAL_RCC_OscConfig+0xfa>
+ {
+ return HAL_TIMEOUT;
+ 8000c0a: 2303 movs r3, #3
+ 8000c0c: e1ec b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 8000c0e: 4b61 ldr r3, [pc, #388] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c10: 681b ldr r3, [r3, #0]
+ 8000c12: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000c16: 2b00 cmp r3, #0
+ 8000c18: d0f0 beq.n 8000bfc <HAL_RCC_OscConfig+0xe8>
+ 8000c1a: e014 b.n 8000c46 <HAL_RCC_OscConfig+0x132>
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000c1c: f7ff fcde bl 80005dc <HAL_GetTick>
+ 8000c20: 6138 str r0, [r7, #16]
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 8000c22: e008 b.n 8000c36 <HAL_RCC_OscConfig+0x122>
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 8000c24: f7ff fcda bl 80005dc <HAL_GetTick>
+ 8000c28: 4602 mov r2, r0
+ 8000c2a: 693b ldr r3, [r7, #16]
+ 8000c2c: 1ad3 subs r3, r2, r3
+ 8000c2e: 2b64 cmp r3, #100 ; 0x64
+ 8000c30: d901 bls.n 8000c36 <HAL_RCC_OscConfig+0x122>
+ {
+ return HAL_TIMEOUT;
+ 8000c32: 2303 movs r3, #3
+ 8000c34: e1d8 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 8000c36: 4b57 ldr r3, [pc, #348] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c38: 681b ldr r3, [r3, #0]
+ 8000c3a: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000c3e: 2b00 cmp r3, #0
+ 8000c40: d1f0 bne.n 8000c24 <HAL_RCC_OscConfig+0x110>
+ 8000c42: e000 b.n 8000c46 <HAL_RCC_OscConfig+0x132>
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8000c44: bf00 nop
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 8000c46: 687b ldr r3, [r7, #4]
+ 8000c48: 681b ldr r3, [r3, #0]
+ 8000c4a: f003 0302 and.w r3, r3, #2
+ 8000c4e: 2b00 cmp r3, #0
+ 8000c50: d069 beq.n 8000d26 <HAL_RCC_OscConfig+0x212>
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ 8000c52: 4b50 ldr r3, [pc, #320] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c54: 689b ldr r3, [r3, #8]
+ 8000c56: f003 030c and.w r3, r3, #12
+ 8000c5a: 2b00 cmp r3, #0
+ 8000c5c: d00b beq.n 8000c76 <HAL_RCC_OscConfig+0x162>
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ 8000c5e: 4b4d ldr r3, [pc, #308] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c60: 689b ldr r3, [r3, #8]
+ 8000c62: f003 030c and.w r3, r3, #12
+ 8000c66: 2b08 cmp r3, #8
+ 8000c68: d11c bne.n 8000ca4 <HAL_RCC_OscConfig+0x190>
+ 8000c6a: 4b4a ldr r3, [pc, #296] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c6c: 685b ldr r3, [r3, #4]
+ 8000c6e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8000c72: 2b00 cmp r3, #0
+ 8000c74: d116 bne.n 8000ca4 <HAL_RCC_OscConfig+0x190>
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 8000c76: 4b47 ldr r3, [pc, #284] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c78: 681b ldr r3, [r3, #0]
+ 8000c7a: f003 0302 and.w r3, r3, #2
+ 8000c7e: 2b00 cmp r3, #0
+ 8000c80: d005 beq.n 8000c8e <HAL_RCC_OscConfig+0x17a>
+ 8000c82: 687b ldr r3, [r7, #4]
+ 8000c84: 68db ldr r3, [r3, #12]
+ 8000c86: 2b01 cmp r3, #1
+ 8000c88: d001 beq.n 8000c8e <HAL_RCC_OscConfig+0x17a>
+ {
+ return HAL_ERROR;
+ 8000c8a: 2301 movs r3, #1
+ 8000c8c: e1ac b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8000c8e: 4b41 ldr r3, [pc, #260] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c90: 681b ldr r3, [r3, #0]
+ 8000c92: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 8000c96: 687b ldr r3, [r7, #4]
+ 8000c98: 691b ldr r3, [r3, #16]
+ 8000c9a: 00db lsls r3, r3, #3
+ 8000c9c: 493d ldr r1, [pc, #244] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c9e: 4313 orrs r3, r2
+ 8000ca0: 600b str r3, [r1, #0]
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 8000ca2: e040 b.n 8000d26 <HAL_RCC_OscConfig+0x212>
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ 8000ca4: 687b ldr r3, [r7, #4]
+ 8000ca6: 68db ldr r3, [r3, #12]
+ 8000ca8: 2b00 cmp r3, #0
+ 8000caa: d023 beq.n 8000cf4 <HAL_RCC_OscConfig+0x1e0>
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+ 8000cac: 4b39 ldr r3, [pc, #228] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cae: 681b ldr r3, [r3, #0]
+ 8000cb0: 4a38 ldr r2, [pc, #224] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cb2: f043 0301 orr.w r3, r3, #1
+ 8000cb6: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000cb8: f7ff fc90 bl 80005dc <HAL_GetTick>
+ 8000cbc: 6138 str r0, [r7, #16]
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8000cbe: e008 b.n 8000cd2 <HAL_RCC_OscConfig+0x1be>
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 8000cc0: f7ff fc8c bl 80005dc <HAL_GetTick>
+ 8000cc4: 4602 mov r2, r0
+ 8000cc6: 693b ldr r3, [r7, #16]
+ 8000cc8: 1ad3 subs r3, r2, r3
+ 8000cca: 2b02 cmp r3, #2
+ 8000ccc: d901 bls.n 8000cd2 <HAL_RCC_OscConfig+0x1be>
+ {
+ return HAL_TIMEOUT;
+ 8000cce: 2303 movs r3, #3
+ 8000cd0: e18a b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8000cd2: 4b30 ldr r3, [pc, #192] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cd4: 681b ldr r3, [r3, #0]
+ 8000cd6: f003 0302 and.w r3, r3, #2
+ 8000cda: 2b00 cmp r3, #0
+ 8000cdc: d0f0 beq.n 8000cc0 <HAL_RCC_OscConfig+0x1ac>
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8000cde: 4b2d ldr r3, [pc, #180] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000ce0: 681b ldr r3, [r3, #0]
+ 8000ce2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 8000ce6: 687b ldr r3, [r7, #4]
+ 8000ce8: 691b ldr r3, [r3, #16]
+ 8000cea: 00db lsls r3, r3, #3
+ 8000cec: 4929 ldr r1, [pc, #164] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cee: 4313 orrs r3, r2
+ 8000cf0: 600b str r3, [r1, #0]
+ 8000cf2: e018 b.n 8000d26 <HAL_RCC_OscConfig+0x212>
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+ 8000cf4: 4b27 ldr r3, [pc, #156] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cf6: 681b ldr r3, [r3, #0]
+ 8000cf8: 4a26 ldr r2, [pc, #152] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cfa: f023 0301 bic.w r3, r3, #1
+ 8000cfe: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000d00: f7ff fc6c bl 80005dc <HAL_GetTick>
+ 8000d04: 6138 str r0, [r7, #16]
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 8000d06: e008 b.n 8000d1a <HAL_RCC_OscConfig+0x206>
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 8000d08: f7ff fc68 bl 80005dc <HAL_GetTick>
+ 8000d0c: 4602 mov r2, r0
+ 8000d0e: 693b ldr r3, [r7, #16]
+ 8000d10: 1ad3 subs r3, r2, r3
+ 8000d12: 2b02 cmp r3, #2
+ 8000d14: d901 bls.n 8000d1a <HAL_RCC_OscConfig+0x206>
+ {
+ return HAL_TIMEOUT;
+ 8000d16: 2303 movs r3, #3
+ 8000d18: e166 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 8000d1a: 4b1e ldr r3, [pc, #120] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d1c: 681b ldr r3, [r3, #0]
+ 8000d1e: f003 0302 and.w r3, r3, #2
+ 8000d22: 2b00 cmp r3, #0
+ 8000d24: d1f0 bne.n 8000d08 <HAL_RCC_OscConfig+0x1f4>
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 8000d26: 687b ldr r3, [r7, #4]
+ 8000d28: 681b ldr r3, [r3, #0]
+ 8000d2a: f003 0308 and.w r3, r3, #8
+ 8000d2e: 2b00 cmp r3, #0
+ 8000d30: d038 beq.n 8000da4 <HAL_RCC_OscConfig+0x290>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ 8000d32: 687b ldr r3, [r7, #4]
+ 8000d34: 695b ldr r3, [r3, #20]
+ 8000d36: 2b00 cmp r3, #0
+ 8000d38: d019 beq.n 8000d6e <HAL_RCC_OscConfig+0x25a>
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+ 8000d3a: 4b16 ldr r3, [pc, #88] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d3c: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d3e: 4a15 ldr r2, [pc, #84] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d40: f043 0301 orr.w r3, r3, #1
+ 8000d44: 6753 str r3, [r2, #116] ; 0x74
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000d46: f7ff fc49 bl 80005dc <HAL_GetTick>
+ 8000d4a: 6138 str r0, [r7, #16]
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 8000d4c: e008 b.n 8000d60 <HAL_RCC_OscConfig+0x24c>
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 8000d4e: f7ff fc45 bl 80005dc <HAL_GetTick>
+ 8000d52: 4602 mov r2, r0
+ 8000d54: 693b ldr r3, [r7, #16]
+ 8000d56: 1ad3 subs r3, r2, r3
+ 8000d58: 2b02 cmp r3, #2
+ 8000d5a: d901 bls.n 8000d60 <HAL_RCC_OscConfig+0x24c>
+ {
+ return HAL_TIMEOUT;
+ 8000d5c: 2303 movs r3, #3
+ 8000d5e: e143 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 8000d60: 4b0c ldr r3, [pc, #48] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d62: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d64: f003 0302 and.w r3, r3, #2
+ 8000d68: 2b00 cmp r3, #0
+ 8000d6a: d0f0 beq.n 8000d4e <HAL_RCC_OscConfig+0x23a>
+ 8000d6c: e01a b.n 8000da4 <HAL_RCC_OscConfig+0x290>
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+ 8000d6e: 4b09 ldr r3, [pc, #36] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d70: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d72: 4a08 ldr r2, [pc, #32] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d74: f023 0301 bic.w r3, r3, #1
+ 8000d78: 6753 str r3, [r2, #116] ; 0x74
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000d7a: f7ff fc2f bl 80005dc <HAL_GetTick>
+ 8000d7e: 6138 str r0, [r7, #16]
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 8000d80: e00a b.n 8000d98 <HAL_RCC_OscConfig+0x284>
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 8000d82: f7ff fc2b bl 80005dc <HAL_GetTick>
+ 8000d86: 4602 mov r2, r0
+ 8000d88: 693b ldr r3, [r7, #16]
+ 8000d8a: 1ad3 subs r3, r2, r3
+ 8000d8c: 2b02 cmp r3, #2
+ 8000d8e: d903 bls.n 8000d98 <HAL_RCC_OscConfig+0x284>
+ {
+ return HAL_TIMEOUT;
+ 8000d90: 2303 movs r3, #3
+ 8000d92: e129 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ 8000d94: 40023800 .word 0x40023800
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 8000d98: 4b95 ldr r3, [pc, #596] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000d9a: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d9c: f003 0302 and.w r3, r3, #2
+ 8000da0: 2b00 cmp r3, #0
+ 8000da2: d1ee bne.n 8000d82 <HAL_RCC_OscConfig+0x26e>
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 8000da4: 687b ldr r3, [r7, #4]
+ 8000da6: 681b ldr r3, [r3, #0]
+ 8000da8: f003 0304 and.w r3, r3, #4
+ 8000dac: 2b00 cmp r3, #0
+ 8000dae: f000 80a4 beq.w 8000efa <HAL_RCC_OscConfig+0x3e6>
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 8000db2: 4b8f ldr r3, [pc, #572] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000db4: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000db6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000dba: 2b00 cmp r3, #0
+ 8000dbc: d10d bne.n 8000dda <HAL_RCC_OscConfig+0x2c6>
+ {
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8000dbe: 4b8c ldr r3, [pc, #560] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000dc0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000dc2: 4a8b ldr r2, [pc, #556] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000dc4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000dc8: 6413 str r3, [r2, #64] ; 0x40
+ 8000dca: 4b89 ldr r3, [pc, #548] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000dcc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000dce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000dd2: 60fb str r3, [r7, #12]
+ 8000dd4: 68fb ldr r3, [r7, #12]
+ pwrclkchanged = SET;
+ 8000dd6: 2301 movs r3, #1
+ 8000dd8: 75fb strb r3, [r7, #23]
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 8000dda: 4b86 ldr r3, [pc, #536] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000ddc: 681b ldr r3, [r3, #0]
+ 8000dde: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8000de2: 2b00 cmp r3, #0
+ 8000de4: d118 bne.n 8000e18 <HAL_RCC_OscConfig+0x304>
+ {
+ /* Enable write access to Backup domain */
+ PWR->CR1 |= PWR_CR1_DBP;
+ 8000de6: 4b83 ldr r3, [pc, #524] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000de8: 681b ldr r3, [r3, #0]
+ 8000dea: 4a82 ldr r2, [pc, #520] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000dec: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 8000df0: 6013 str r3, [r2, #0]
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+ 8000df2: f7ff fbf3 bl 80005dc <HAL_GetTick>
+ 8000df6: 6138 str r0, [r7, #16]
+
+ while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 8000df8: e008 b.n 8000e0c <HAL_RCC_OscConfig+0x2f8>
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ 8000dfa: f7ff fbef bl 80005dc <HAL_GetTick>
+ 8000dfe: 4602 mov r2, r0
+ 8000e00: 693b ldr r3, [r7, #16]
+ 8000e02: 1ad3 subs r3, r2, r3
+ 8000e04: 2b64 cmp r3, #100 ; 0x64
+ 8000e06: d901 bls.n 8000e0c <HAL_RCC_OscConfig+0x2f8>
+ {
+ return HAL_TIMEOUT;
+ 8000e08: 2303 movs r3, #3
+ 8000e0a: e0ed b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 8000e0c: 4b79 ldr r3, [pc, #484] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000e0e: 681b ldr r3, [r3, #0]
+ 8000e10: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8000e14: 2b00 cmp r3, #0
+ 8000e16: d0f0 beq.n 8000dfa <HAL_RCC_OscConfig+0x2e6>
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 8000e18: 687b ldr r3, [r7, #4]
+ 8000e1a: 689b ldr r3, [r3, #8]
+ 8000e1c: 2b01 cmp r3, #1
+ 8000e1e: d106 bne.n 8000e2e <HAL_RCC_OscConfig+0x31a>
+ 8000e20: 4b73 ldr r3, [pc, #460] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e22: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e24: 4a72 ldr r2, [pc, #456] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e26: f043 0301 orr.w r3, r3, #1
+ 8000e2a: 6713 str r3, [r2, #112] ; 0x70
+ 8000e2c: e02d b.n 8000e8a <HAL_RCC_OscConfig+0x376>
+ 8000e2e: 687b ldr r3, [r7, #4]
+ 8000e30: 689b ldr r3, [r3, #8]
+ 8000e32: 2b00 cmp r3, #0
+ 8000e34: d10c bne.n 8000e50 <HAL_RCC_OscConfig+0x33c>
+ 8000e36: 4b6e ldr r3, [pc, #440] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e38: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e3a: 4a6d ldr r2, [pc, #436] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e3c: f023 0301 bic.w r3, r3, #1
+ 8000e40: 6713 str r3, [r2, #112] ; 0x70
+ 8000e42: 4b6b ldr r3, [pc, #428] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e44: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e46: 4a6a ldr r2, [pc, #424] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e48: f023 0304 bic.w r3, r3, #4
+ 8000e4c: 6713 str r3, [r2, #112] ; 0x70
+ 8000e4e: e01c b.n 8000e8a <HAL_RCC_OscConfig+0x376>
+ 8000e50: 687b ldr r3, [r7, #4]
+ 8000e52: 689b ldr r3, [r3, #8]
+ 8000e54: 2b05 cmp r3, #5
+ 8000e56: d10c bne.n 8000e72 <HAL_RCC_OscConfig+0x35e>
+ 8000e58: 4b65 ldr r3, [pc, #404] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e5a: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e5c: 4a64 ldr r2, [pc, #400] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e5e: f043 0304 orr.w r3, r3, #4
+ 8000e62: 6713 str r3, [r2, #112] ; 0x70
+ 8000e64: 4b62 ldr r3, [pc, #392] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e66: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e68: 4a61 ldr r2, [pc, #388] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e6a: f043 0301 orr.w r3, r3, #1
+ 8000e6e: 6713 str r3, [r2, #112] ; 0x70
+ 8000e70: e00b b.n 8000e8a <HAL_RCC_OscConfig+0x376>
+ 8000e72: 4b5f ldr r3, [pc, #380] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e74: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e76: 4a5e ldr r2, [pc, #376] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e78: f023 0301 bic.w r3, r3, #1
+ 8000e7c: 6713 str r3, [r2, #112] ; 0x70
+ 8000e7e: 4b5c ldr r3, [pc, #368] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e80: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e82: 4a5b ldr r2, [pc, #364] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e84: f023 0304 bic.w r3, r3, #4
+ 8000e88: 6713 str r3, [r2, #112] ; 0x70
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ 8000e8a: 687b ldr r3, [r7, #4]
+ 8000e8c: 689b ldr r3, [r3, #8]
+ 8000e8e: 2b00 cmp r3, #0
+ 8000e90: d015 beq.n 8000ebe <HAL_RCC_OscConfig+0x3aa>
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000e92: f7ff fba3 bl 80005dc <HAL_GetTick>
+ 8000e96: 6138 str r0, [r7, #16]
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 8000e98: e00a b.n 8000eb0 <HAL_RCC_OscConfig+0x39c>
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 8000e9a: f7ff fb9f bl 80005dc <HAL_GetTick>
+ 8000e9e: 4602 mov r2, r0
+ 8000ea0: 693b ldr r3, [r7, #16]
+ 8000ea2: 1ad3 subs r3, r2, r3
+ 8000ea4: f241 3288 movw r2, #5000 ; 0x1388
+ 8000ea8: 4293 cmp r3, r2
+ 8000eaa: d901 bls.n 8000eb0 <HAL_RCC_OscConfig+0x39c>
+ {
+ return HAL_TIMEOUT;
+ 8000eac: 2303 movs r3, #3
+ 8000eae: e09b b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 8000eb0: 4b4f ldr r3, [pc, #316] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000eb2: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000eb4: f003 0302 and.w r3, r3, #2
+ 8000eb8: 2b00 cmp r3, #0
+ 8000eba: d0ee beq.n 8000e9a <HAL_RCC_OscConfig+0x386>
+ 8000ebc: e014 b.n 8000ee8 <HAL_RCC_OscConfig+0x3d4>
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000ebe: f7ff fb8d bl 80005dc <HAL_GetTick>
+ 8000ec2: 6138 str r0, [r7, #16]
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 8000ec4: e00a b.n 8000edc <HAL_RCC_OscConfig+0x3c8>
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 8000ec6: f7ff fb89 bl 80005dc <HAL_GetTick>
+ 8000eca: 4602 mov r2, r0
+ 8000ecc: 693b ldr r3, [r7, #16]
+ 8000ece: 1ad3 subs r3, r2, r3
+ 8000ed0: f241 3288 movw r2, #5000 ; 0x1388
+ 8000ed4: 4293 cmp r3, r2
+ 8000ed6: d901 bls.n 8000edc <HAL_RCC_OscConfig+0x3c8>
+ {
+ return HAL_TIMEOUT;
+ 8000ed8: 2303 movs r3, #3
+ 8000eda: e085 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 8000edc: 4b44 ldr r3, [pc, #272] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000ede: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000ee0: f003 0302 and.w r3, r3, #2
+ 8000ee4: 2b00 cmp r3, #0
+ 8000ee6: d1ee bne.n 8000ec6 <HAL_RCC_OscConfig+0x3b2>
+ }
+ }
+ }
+
+ /* Restore clock configuration if changed */
+ if(pwrclkchanged == SET)
+ 8000ee8: 7dfb ldrb r3, [r7, #23]
+ 8000eea: 2b01 cmp r3, #1
+ 8000eec: d105 bne.n 8000efa <HAL_RCC_OscConfig+0x3e6>
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ 8000eee: 4b40 ldr r3, [pc, #256] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000ef0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000ef2: 4a3f ldr r2, [pc, #252] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000ef4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 8000ef8: 6413 str r3, [r2, #64] ; 0x40
+ }
+ }
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 8000efa: 687b ldr r3, [r7, #4]
+ 8000efc: 699b ldr r3, [r3, #24]
+ 8000efe: 2b00 cmp r3, #0
+ 8000f00: d071 beq.n 8000fe6 <HAL_RCC_OscConfig+0x4d2>
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 8000f02: 4b3b ldr r3, [pc, #236] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f04: 689b ldr r3, [r3, #8]
+ 8000f06: f003 030c and.w r3, r3, #12
+ 8000f0a: 2b08 cmp r3, #8
+ 8000f0c: d069 beq.n 8000fe2 <HAL_RCC_OscConfig+0x4ce>
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 8000f0e: 687b ldr r3, [r7, #4]
+ 8000f10: 699b ldr r3, [r3, #24]
+ 8000f12: 2b02 cmp r3, #2
+ 8000f14: d14b bne.n 8000fae <HAL_RCC_OscConfig+0x49a>
+#if defined (RCC_PLLCFGR_PLLR)
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+#endif
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+ 8000f16: 4b36 ldr r3, [pc, #216] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f18: 681b ldr r3, [r3, #0]
+ 8000f1a: 4a35 ldr r2, [pc, #212] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f1c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8000f20: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000f22: f7ff fb5b bl 80005dc <HAL_GetTick>
+ 8000f26: 6138 str r0, [r7, #16]
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 8000f28: e008 b.n 8000f3c <HAL_RCC_OscConfig+0x428>
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8000f2a: f7ff fb57 bl 80005dc <HAL_GetTick>
+ 8000f2e: 4602 mov r2, r0
+ 8000f30: 693b ldr r3, [r7, #16]
+ 8000f32: 1ad3 subs r3, r2, r3
+ 8000f34: 2b02 cmp r3, #2
+ 8000f36: d901 bls.n 8000f3c <HAL_RCC_OscConfig+0x428>
+ {
+ return HAL_TIMEOUT;
+ 8000f38: 2303 movs r3, #3
+ 8000f3a: e055 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 8000f3c: 4b2c ldr r3, [pc, #176] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f3e: 681b ldr r3, [r3, #0]
+ 8000f40: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8000f44: 2b00 cmp r3, #0
+ 8000f46: d1f0 bne.n 8000f2a <HAL_RCC_OscConfig+0x416>
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division factors. */
+#if defined (RCC_PLLCFGR_PLLR)
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 8000f48: 687b ldr r3, [r7, #4]
+ 8000f4a: 69da ldr r2, [r3, #28]
+ 8000f4c: 687b ldr r3, [r7, #4]
+ 8000f4e: 6a1b ldr r3, [r3, #32]
+ 8000f50: 431a orrs r2, r3
+ 8000f52: 687b ldr r3, [r7, #4]
+ 8000f54: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8000f56: 019b lsls r3, r3, #6
+ 8000f58: 431a orrs r2, r3
+ 8000f5a: 687b ldr r3, [r7, #4]
+ 8000f5c: 6a9b ldr r3, [r3, #40] ; 0x28
+ 8000f5e: 085b lsrs r3, r3, #1
+ 8000f60: 3b01 subs r3, #1
+ 8000f62: 041b lsls r3, r3, #16
+ 8000f64: 431a orrs r2, r3
+ 8000f66: 687b ldr r3, [r7, #4]
+ 8000f68: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000f6a: 061b lsls r3, r3, #24
+ 8000f6c: 431a orrs r2, r3
+ 8000f6e: 687b ldr r3, [r7, #4]
+ 8000f70: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000f72: 071b lsls r3, r3, #28
+ 8000f74: 491e ldr r1, [pc, #120] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f76: 4313 orrs r3, r2
+ 8000f78: 604b str r3, [r1, #4]
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ);
+#endif
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+ 8000f7a: 4b1d ldr r3, [pc, #116] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f7c: 681b ldr r3, [r3, #0]
+ 8000f7e: 4a1c ldr r2, [pc, #112] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f80: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
+ 8000f84: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000f86: f7ff fb29 bl 80005dc <HAL_GetTick>
+ 8000f8a: 6138 str r0, [r7, #16]
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 8000f8c: e008 b.n 8000fa0 <HAL_RCC_OscConfig+0x48c>
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8000f8e: f7ff fb25 bl 80005dc <HAL_GetTick>
+ 8000f92: 4602 mov r2, r0
+ 8000f94: 693b ldr r3, [r7, #16]
+ 8000f96: 1ad3 subs r3, r2, r3
+ 8000f98: 2b02 cmp r3, #2
+ 8000f9a: d901 bls.n 8000fa0 <HAL_RCC_OscConfig+0x48c>
+ {
+ return HAL_TIMEOUT;
+ 8000f9c: 2303 movs r3, #3
+ 8000f9e: e023 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 8000fa0: 4b13 ldr r3, [pc, #76] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fa2: 681b ldr r3, [r3, #0]
+ 8000fa4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8000fa8: 2b00 cmp r3, #0
+ 8000faa: d0f0 beq.n 8000f8e <HAL_RCC_OscConfig+0x47a>
+ 8000fac: e01b b.n 8000fe6 <HAL_RCC_OscConfig+0x4d2>
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+ 8000fae: 4b10 ldr r3, [pc, #64] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fb0: 681b ldr r3, [r3, #0]
+ 8000fb2: 4a0f ldr r2, [pc, #60] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fb4: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8000fb8: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8000fba: f7ff fb0f bl 80005dc <HAL_GetTick>
+ 8000fbe: 6138 str r0, [r7, #16]
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 8000fc0: e008 b.n 8000fd4 <HAL_RCC_OscConfig+0x4c0>
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8000fc2: f7ff fb0b bl 80005dc <HAL_GetTick>
+ 8000fc6: 4602 mov r2, r0
+ 8000fc8: 693b ldr r3, [r7, #16]
+ 8000fca: 1ad3 subs r3, r2, r3
+ 8000fcc: 2b02 cmp r3, #2
+ 8000fce: d901 bls.n 8000fd4 <HAL_RCC_OscConfig+0x4c0>
+ {
+ return HAL_TIMEOUT;
+ 8000fd0: 2303 movs r3, #3
+ 8000fd2: e009 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 8000fd4: 4b06 ldr r3, [pc, #24] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fd6: 681b ldr r3, [r3, #0]
+ 8000fd8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8000fdc: 2b00 cmp r3, #0
+ 8000fde: d1f0 bne.n 8000fc2 <HAL_RCC_OscConfig+0x4ae>
+ 8000fe0: e001 b.n 8000fe6 <HAL_RCC_OscConfig+0x4d2>
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ 8000fe2: 2301 movs r3, #1
+ 8000fe4: e000 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ }
+ }
+ return HAL_OK;
+ 8000fe6: 2300 movs r3, #0
+}
+ 8000fe8: 4618 mov r0, r3
+ 8000fea: 3718 adds r7, #24
+ 8000fec: 46bd mov sp, r7
+ 8000fee: bd80 pop {r7, pc}
+ 8000ff0: 40023800 .word 0x40023800
+ 8000ff4: 40007000 .word 0x40007000
+
+08000ff8 <HAL_RCC_ClockConfig>:
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above "Initialization/de-initialization functions")
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ 8000ff8: b580 push {r7, lr}
+ 8000ffa: b084 sub sp, #16
+ 8000ffc: af00 add r7, sp, #0
+ 8000ffe: 6078 str r0, [r7, #4]
+ 8001000: 6039 str r1, [r7, #0]
+ uint32_t tickstart = 0;
+ 8001002: 2300 movs r3, #0
+ 8001004: 60fb str r3, [r7, #12]
+
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ 8001006: 687b ldr r3, [r7, #4]
+ 8001008: 2b00 cmp r3, #0
+ 800100a: d101 bne.n 8001010 <HAL_RCC_ClockConfig+0x18>
+ {
+ return HAL_ERROR;
+ 800100c: 2301 movs r3, #1
+ 800100e: e0ce b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device. */
+
+ /* Increasing the CPU frequency */
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
+ 8001010: 4b69 ldr r3, [pc, #420] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001012: 681b ldr r3, [r3, #0]
+ 8001014: f003 030f and.w r3, r3, #15
+ 8001018: 683a ldr r2, [r7, #0]
+ 800101a: 429a cmp r2, r3
+ 800101c: d910 bls.n 8001040 <HAL_RCC_ClockConfig+0x48>
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+ 800101e: 4b66 ldr r3, [pc, #408] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001020: 681b ldr r3, [r3, #0]
+ 8001022: f023 020f bic.w r2, r3, #15
+ 8001026: 4964 ldr r1, [pc, #400] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001028: 683b ldr r3, [r7, #0]
+ 800102a: 4313 orrs r3, r2
+ 800102c: 600b str r3, [r1, #0]
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 800102e: 4b62 ldr r3, [pc, #392] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001030: 681b ldr r3, [r3, #0]
+ 8001032: f003 030f and.w r3, r3, #15
+ 8001036: 683a ldr r2, [r7, #0]
+ 8001038: 429a cmp r2, r3
+ 800103a: d001 beq.n 8001040 <HAL_RCC_ClockConfig+0x48>
+ {
+ return HAL_ERROR;
+ 800103c: 2301 movs r3, #1
+ 800103e: e0b6 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 8001040: 687b ldr r3, [r7, #4]
+ 8001042: 681b ldr r3, [r3, #0]
+ 8001044: f003 0302 and.w r3, r3, #2
+ 8001048: 2b00 cmp r3, #0
+ 800104a: d020 beq.n 800108e <HAL_RCC_ClockConfig+0x96>
+ {
+ /* Set the highest APBx dividers in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 800104c: 687b ldr r3, [r7, #4]
+ 800104e: 681b ldr r3, [r3, #0]
+ 8001050: f003 0304 and.w r3, r3, #4
+ 8001054: 2b00 cmp r3, #0
+ 8001056: d005 beq.n 8001064 <HAL_RCC_ClockConfig+0x6c>
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ 8001058: 4b58 ldr r3, [pc, #352] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800105a: 689b ldr r3, [r3, #8]
+ 800105c: 4a57 ldr r2, [pc, #348] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800105e: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
+ 8001062: 6093 str r3, [r2, #8]
+ }
+
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 8001064: 687b ldr r3, [r7, #4]
+ 8001066: 681b ldr r3, [r3, #0]
+ 8001068: f003 0308 and.w r3, r3, #8
+ 800106c: 2b00 cmp r3, #0
+ 800106e: d005 beq.n 800107c <HAL_RCC_ClockConfig+0x84>
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ 8001070: 4b52 ldr r3, [pc, #328] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001072: 689b ldr r3, [r3, #8]
+ 8001074: 4a51 ldr r2, [pc, #324] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001076: f443 4360 orr.w r3, r3, #57344 ; 0xe000
+ 800107a: 6093 str r3, [r2, #8]
+ }
+
+ /* Set the new HCLK clock divider */
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 800107c: 4b4f ldr r3, [pc, #316] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800107e: 689b ldr r3, [r3, #8]
+ 8001080: f023 02f0 bic.w r2, r3, #240 ; 0xf0
+ 8001084: 687b ldr r3, [r7, #4]
+ 8001086: 689b ldr r3, [r3, #8]
+ 8001088: 494c ldr r1, [pc, #304] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800108a: 4313 orrs r3, r2
+ 800108c: 608b str r3, [r1, #8]
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 800108e: 687b ldr r3, [r7, #4]
+ 8001090: 681b ldr r3, [r3, #0]
+ 8001092: f003 0301 and.w r3, r3, #1
+ 8001096: 2b00 cmp r3, #0
+ 8001098: d040 beq.n 800111c <HAL_RCC_ClockConfig+0x124>
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 800109a: 687b ldr r3, [r7, #4]
+ 800109c: 685b ldr r3, [r3, #4]
+ 800109e: 2b01 cmp r3, #1
+ 80010a0: d107 bne.n 80010b2 <HAL_RCC_ClockConfig+0xba>
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 80010a2: 4b46 ldr r3, [pc, #280] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010a4: 681b ldr r3, [r3, #0]
+ 80010a6: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80010aa: 2b00 cmp r3, #0
+ 80010ac: d115 bne.n 80010da <HAL_RCC_ClockConfig+0xe2>
+ {
+ return HAL_ERROR;
+ 80010ae: 2301 movs r3, #1
+ 80010b0: e07d b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 80010b2: 687b ldr r3, [r7, #4]
+ 80010b4: 685b ldr r3, [r3, #4]
+ 80010b6: 2b02 cmp r3, #2
+ 80010b8: d107 bne.n 80010ca <HAL_RCC_ClockConfig+0xd2>
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 80010ba: 4b40 ldr r3, [pc, #256] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010bc: 681b ldr r3, [r3, #0]
+ 80010be: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 80010c2: 2b00 cmp r3, #0
+ 80010c4: d109 bne.n 80010da <HAL_RCC_ClockConfig+0xe2>
+ {
+ return HAL_ERROR;
+ 80010c6: 2301 movs r3, #1
+ 80010c8: e071 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 80010ca: 4b3c ldr r3, [pc, #240] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010cc: 681b ldr r3, [r3, #0]
+ 80010ce: f003 0302 and.w r3, r3, #2
+ 80010d2: 2b00 cmp r3, #0
+ 80010d4: d101 bne.n 80010da <HAL_RCC_ClockConfig+0xe2>
+ {
+ return HAL_ERROR;
+ 80010d6: 2301 movs r3, #1
+ 80010d8: e069 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 80010da: 4b38 ldr r3, [pc, #224] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010dc: 689b ldr r3, [r3, #8]
+ 80010de: f023 0203 bic.w r2, r3, #3
+ 80010e2: 687b ldr r3, [r7, #4]
+ 80010e4: 685b ldr r3, [r3, #4]
+ 80010e6: 4935 ldr r1, [pc, #212] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010e8: 4313 orrs r3, r2
+ 80010ea: 608b str r3, [r1, #8]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 80010ec: f7ff fa76 bl 80005dc <HAL_GetTick>
+ 80010f0: 60f8 str r0, [r7, #12]
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 80010f2: e00a b.n 800110a <HAL_RCC_ClockConfig+0x112>
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 80010f4: f7ff fa72 bl 80005dc <HAL_GetTick>
+ 80010f8: 4602 mov r2, r0
+ 80010fa: 68fb ldr r3, [r7, #12]
+ 80010fc: 1ad3 subs r3, r2, r3
+ 80010fe: f241 3288 movw r2, #5000 ; 0x1388
+ 8001102: 4293 cmp r3, r2
+ 8001104: d901 bls.n 800110a <HAL_RCC_ClockConfig+0x112>
+ {
+ return HAL_TIMEOUT;
+ 8001106: 2303 movs r3, #3
+ 8001108: e051 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 800110a: 4b2c ldr r3, [pc, #176] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800110c: 689b ldr r3, [r3, #8]
+ 800110e: f003 020c and.w r2, r3, #12
+ 8001112: 687b ldr r3, [r7, #4]
+ 8001114: 685b ldr r3, [r3, #4]
+ 8001116: 009b lsls r3, r3, #2
+ 8001118: 429a cmp r2, r3
+ 800111a: d1eb bne.n 80010f4 <HAL_RCC_ClockConfig+0xfc>
+ }
+ }
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
+ 800111c: 4b26 ldr r3, [pc, #152] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 800111e: 681b ldr r3, [r3, #0]
+ 8001120: f003 030f and.w r3, r3, #15
+ 8001124: 683a ldr r2, [r7, #0]
+ 8001126: 429a cmp r2, r3
+ 8001128: d210 bcs.n 800114c <HAL_RCC_ClockConfig+0x154>
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+ 800112a: 4b23 ldr r3, [pc, #140] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 800112c: 681b ldr r3, [r3, #0]
+ 800112e: f023 020f bic.w r2, r3, #15
+ 8001132: 4921 ldr r1, [pc, #132] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001134: 683b ldr r3, [r7, #0]
+ 8001136: 4313 orrs r3, r2
+ 8001138: 600b str r3, [r1, #0]
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 800113a: 4b1f ldr r3, [pc, #124] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 800113c: 681b ldr r3, [r3, #0]
+ 800113e: f003 030f and.w r3, r3, #15
+ 8001142: 683a ldr r2, [r7, #0]
+ 8001144: 429a cmp r2, r3
+ 8001146: d001 beq.n 800114c <HAL_RCC_ClockConfig+0x154>
+ {
+ return HAL_ERROR;
+ 8001148: 2301 movs r3, #1
+ 800114a: e030 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 800114c: 687b ldr r3, [r7, #4]
+ 800114e: 681b ldr r3, [r3, #0]
+ 8001150: f003 0304 and.w r3, r3, #4
+ 8001154: 2b00 cmp r3, #0
+ 8001156: d008 beq.n 800116a <HAL_RCC_ClockConfig+0x172>
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 8001158: 4b18 ldr r3, [pc, #96] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800115a: 689b ldr r3, [r3, #8]
+ 800115c: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
+ 8001160: 687b ldr r3, [r7, #4]
+ 8001162: 68db ldr r3, [r3, #12]
+ 8001164: 4915 ldr r1, [pc, #84] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001166: 4313 orrs r3, r2
+ 8001168: 608b str r3, [r1, #8]
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 800116a: 687b ldr r3, [r7, #4]
+ 800116c: 681b ldr r3, [r3, #0]
+ 800116e: f003 0308 and.w r3, r3, #8
+ 8001172: 2b00 cmp r3, #0
+ 8001174: d009 beq.n 800118a <HAL_RCC_ClockConfig+0x192>
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ 8001176: 4b11 ldr r3, [pc, #68] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001178: 689b ldr r3, [r3, #8]
+ 800117a: f423 4260 bic.w r2, r3, #57344 ; 0xe000
+ 800117e: 687b ldr r3, [r7, #4]
+ 8001180: 691b ldr r3, [r3, #16]
+ 8001182: 00db lsls r3, r3, #3
+ 8001184: 490d ldr r1, [pc, #52] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001186: 4313 orrs r3, r2
+ 8001188: 608b str r3, [r1, #8]
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+ 800118a: f000 f81d bl 80011c8 <HAL_RCC_GetSysClockFreq>
+ 800118e: 4601 mov r1, r0
+ 8001190: 4b0a ldr r3, [pc, #40] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001192: 689b ldr r3, [r3, #8]
+ 8001194: 091b lsrs r3, r3, #4
+ 8001196: f003 030f and.w r3, r3, #15
+ 800119a: 4a09 ldr r2, [pc, #36] ; (80011c0 <HAL_RCC_ClockConfig+0x1c8>)
+ 800119c: 5cd3 ldrb r3, [r2, r3]
+ 800119e: fa21 f303 lsr.w r3, r1, r3
+ 80011a2: 4a08 ldr r2, [pc, #32] ; (80011c4 <HAL_RCC_ClockConfig+0x1cc>)
+ 80011a4: 6013 str r3, [r2, #0]
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+ 80011a6: 2000 movs r0, #0
+ 80011a8: f7ff f9d4 bl 8000554 <HAL_InitTick>
+
+ return HAL_OK;
+ 80011ac: 2300 movs r3, #0
+}
+ 80011ae: 4618 mov r0, r3
+ 80011b0: 3710 adds r7, #16
+ 80011b2: 46bd mov sp, r7
+ 80011b4: bd80 pop {r7, pc}
+ 80011b6: bf00 nop
+ 80011b8: 40023c00 .word 0x40023c00
+ 80011bc: 40023800 .word 0x40023800
+ 80011c0: 08001d20 .word 0x08001d20
+ 80011c4: 20000008 .word 0x20000008
+
+080011c8 <HAL_RCC_GetSysClockFreq>:
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ 80011c8: b5f0 push {r4, r5, r6, r7, lr}
+ 80011ca: b085 sub sp, #20
+ 80011cc: af00 add r7, sp, #0
+ uint32_t pllm = 0, pllvco = 0, pllp = 0;
+ 80011ce: 2300 movs r3, #0
+ 80011d0: 607b str r3, [r7, #4]
+ 80011d2: 2300 movs r3, #0
+ 80011d4: 60fb str r3, [r7, #12]
+ 80011d6: 2300 movs r3, #0
+ 80011d8: 603b str r3, [r7, #0]
+ uint32_t sysclockfreq = 0;
+ 80011da: 2300 movs r3, #0
+ 80011dc: 60bb str r3, [r7, #8]
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ 80011de: 4b50 ldr r3, [pc, #320] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80011e0: 689b ldr r3, [r3, #8]
+ 80011e2: f003 030c and.w r3, r3, #12
+ 80011e6: 2b04 cmp r3, #4
+ 80011e8: d007 beq.n 80011fa <HAL_RCC_GetSysClockFreq+0x32>
+ 80011ea: 2b08 cmp r3, #8
+ 80011ec: d008 beq.n 8001200 <HAL_RCC_GetSysClockFreq+0x38>
+ 80011ee: 2b00 cmp r3, #0
+ 80011f0: f040 808d bne.w 800130e <HAL_RCC_GetSysClockFreq+0x146>
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ {
+ sysclockfreq = HSI_VALUE;
+ 80011f4: 4b4b ldr r3, [pc, #300] ; (8001324 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 80011f6: 60bb str r3, [r7, #8]
+ break;
+ 80011f8: e08c b.n 8001314 <HAL_RCC_GetSysClockFreq+0x14c>
+ }
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ {
+ sysclockfreq = HSE_VALUE;
+ 80011fa: 4b4b ldr r3, [pc, #300] ; (8001328 <HAL_RCC_GetSysClockFreq+0x160>)
+ 80011fc: 60bb str r3, [r7, #8]
+ break;
+ 80011fe: e089 b.n 8001314 <HAL_RCC_GetSysClockFreq+0x14c>
+ }
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ 8001200: 4b47 ldr r3, [pc, #284] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001202: 685b ldr r3, [r3, #4]
+ 8001204: f003 033f and.w r3, r3, #63 ; 0x3f
+ 8001208: 607b str r3, [r7, #4]
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
+ 800120a: 4b45 ldr r3, [pc, #276] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 800120c: 685b ldr r3, [r3, #4]
+ 800120e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8001212: 2b00 cmp r3, #0
+ 8001214: d023 beq.n 800125e <HAL_RCC_GetSysClockFreq+0x96>
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ 8001216: 4b42 ldr r3, [pc, #264] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001218: 685b ldr r3, [r3, #4]
+ 800121a: 099b lsrs r3, r3, #6
+ 800121c: f04f 0400 mov.w r4, #0
+ 8001220: f240 11ff movw r1, #511 ; 0x1ff
+ 8001224: f04f 0200 mov.w r2, #0
+ 8001228: ea03 0501 and.w r5, r3, r1
+ 800122c: ea04 0602 and.w r6, r4, r2
+ 8001230: 4a3d ldr r2, [pc, #244] ; (8001328 <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001232: fb02 f106 mul.w r1, r2, r6
+ 8001236: 2200 movs r2, #0
+ 8001238: fb02 f205 mul.w r2, r2, r5
+ 800123c: 440a add r2, r1
+ 800123e: 493a ldr r1, [pc, #232] ; (8001328 <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001240: fba5 0101 umull r0, r1, r5, r1
+ 8001244: 1853 adds r3, r2, r1
+ 8001246: 4619 mov r1, r3
+ 8001248: 687b ldr r3, [r7, #4]
+ 800124a: f04f 0400 mov.w r4, #0
+ 800124e: 461a mov r2, r3
+ 8001250: 4623 mov r3, r4
+ 8001252: f7fe fff1 bl 8000238 <__aeabi_uldivmod>
+ 8001256: 4603 mov r3, r0
+ 8001258: 460c mov r4, r1
+ 800125a: 60fb str r3, [r7, #12]
+ 800125c: e049 b.n 80012f2 <HAL_RCC_GetSysClockFreq+0x12a>
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ 800125e: 4b30 ldr r3, [pc, #192] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001260: 685b ldr r3, [r3, #4]
+ 8001262: 099b lsrs r3, r3, #6
+ 8001264: f04f 0400 mov.w r4, #0
+ 8001268: f240 11ff movw r1, #511 ; 0x1ff
+ 800126c: f04f 0200 mov.w r2, #0
+ 8001270: ea03 0501 and.w r5, r3, r1
+ 8001274: ea04 0602 and.w r6, r4, r2
+ 8001278: 4629 mov r1, r5
+ 800127a: 4632 mov r2, r6
+ 800127c: f04f 0300 mov.w r3, #0
+ 8001280: f04f 0400 mov.w r4, #0
+ 8001284: 0154 lsls r4, r2, #5
+ 8001286: ea44 64d1 orr.w r4, r4, r1, lsr #27
+ 800128a: 014b lsls r3, r1, #5
+ 800128c: 4619 mov r1, r3
+ 800128e: 4622 mov r2, r4
+ 8001290: 1b49 subs r1, r1, r5
+ 8001292: eb62 0206 sbc.w r2, r2, r6
+ 8001296: f04f 0300 mov.w r3, #0
+ 800129a: f04f 0400 mov.w r4, #0
+ 800129e: 0194 lsls r4, r2, #6
+ 80012a0: ea44 6491 orr.w r4, r4, r1, lsr #26
+ 80012a4: 018b lsls r3, r1, #6
+ 80012a6: 1a5b subs r3, r3, r1
+ 80012a8: eb64 0402 sbc.w r4, r4, r2
+ 80012ac: f04f 0100 mov.w r1, #0
+ 80012b0: f04f 0200 mov.w r2, #0
+ 80012b4: 00e2 lsls r2, r4, #3
+ 80012b6: ea42 7253 orr.w r2, r2, r3, lsr #29
+ 80012ba: 00d9 lsls r1, r3, #3
+ 80012bc: 460b mov r3, r1
+ 80012be: 4614 mov r4, r2
+ 80012c0: 195b adds r3, r3, r5
+ 80012c2: eb44 0406 adc.w r4, r4, r6
+ 80012c6: f04f 0100 mov.w r1, #0
+ 80012ca: f04f 0200 mov.w r2, #0
+ 80012ce: 02a2 lsls r2, r4, #10
+ 80012d0: ea42 5293 orr.w r2, r2, r3, lsr #22
+ 80012d4: 0299 lsls r1, r3, #10
+ 80012d6: 460b mov r3, r1
+ 80012d8: 4614 mov r4, r2
+ 80012da: 4618 mov r0, r3
+ 80012dc: 4621 mov r1, r4
+ 80012de: 687b ldr r3, [r7, #4]
+ 80012e0: f04f 0400 mov.w r4, #0
+ 80012e4: 461a mov r2, r3
+ 80012e6: 4623 mov r3, r4
+ 80012e8: f7fe ffa6 bl 8000238 <__aeabi_uldivmod>
+ 80012ec: 4603 mov r3, r0
+ 80012ee: 460c mov r4, r1
+ 80012f0: 60fb str r3, [r7, #12]
+ }
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
+ 80012f2: 4b0b ldr r3, [pc, #44] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80012f4: 685b ldr r3, [r3, #4]
+ 80012f6: 0c1b lsrs r3, r3, #16
+ 80012f8: f003 0303 and.w r3, r3, #3
+ 80012fc: 3301 adds r3, #1
+ 80012fe: 005b lsls r3, r3, #1
+ 8001300: 603b str r3, [r7, #0]
+
+ sysclockfreq = pllvco/pllp;
+ 8001302: 68fa ldr r2, [r7, #12]
+ 8001304: 683b ldr r3, [r7, #0]
+ 8001306: fbb2 f3f3 udiv r3, r2, r3
+ 800130a: 60bb str r3, [r7, #8]
+ break;
+ 800130c: e002 b.n 8001314 <HAL_RCC_GetSysClockFreq+0x14c>
+ }
+ default:
+ {
+ sysclockfreq = HSI_VALUE;
+ 800130e: 4b05 ldr r3, [pc, #20] ; (8001324 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 8001310: 60bb str r3, [r7, #8]
+ break;
+ 8001312: bf00 nop
+ }
+ }
+ return sysclockfreq;
+ 8001314: 68bb ldr r3, [r7, #8]
+}
+ 8001316: 4618 mov r0, r3
+ 8001318: 3714 adds r7, #20
+ 800131a: 46bd mov sp, r7
+ 800131c: bdf0 pop {r4, r5, r6, r7, pc}
+ 800131e: bf00 nop
+ 8001320: 40023800 .word 0x40023800
+ 8001324: 00f42400 .word 0x00f42400
+ 8001328: 017d7840 .word 0x017d7840
+
+0800132c <HAL_TIM_Encoder_Init>:
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+{
+ 800132c: b580 push {r7, lr}
+ 800132e: b086 sub sp, #24
+ 8001330: af00 add r7, sp, #0
+ 8001332: 6078 str r0, [r7, #4]
+ 8001334: 6039 str r1, [r7, #0]
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ 8001336: 687b ldr r3, [r7, #4]
+ 8001338: 2b00 cmp r3, #0
+ 800133a: d101 bne.n 8001340 <HAL_TIM_Encoder_Init+0x14>
+ {
+ return HAL_ERROR;
+ 800133c: 2301 movs r3, #1
+ 800133e: e07b b.n 8001438 <HAL_TIM_Encoder_Init+0x10c>
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ 8001340: 687b ldr r3, [r7, #4]
+ 8001342: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
+ 8001346: b2db uxtb r3, r3
+ 8001348: 2b00 cmp r3, #0
+ 800134a: d106 bne.n 800135a <HAL_TIM_Encoder_Init+0x2e>
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ 800134c: 687b ldr r3, [r7, #4]
+ 800134e: 2200 movs r2, #0
+ 8001350: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+ 8001354: 6878 ldr r0, [r7, #4]
+ 8001356: f000 fb8d bl 8001a74 <HAL_TIM_Encoder_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+ 800135a: 687b ldr r3, [r7, #4]
+ 800135c: 2202 movs r2, #2
+ 800135e: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+ 8001362: 687b ldr r3, [r7, #4]
+ 8001364: 681b ldr r3, [r3, #0]
+ 8001366: 6899 ldr r1, [r3, #8]
+ 8001368: 687b ldr r3, [r7, #4]
+ 800136a: 681a ldr r2, [r3, #0]
+ 800136c: 4b34 ldr r3, [pc, #208] ; (8001440 <HAL_TIM_Encoder_Init+0x114>)
+ 800136e: 400b ands r3, r1
+ 8001370: 6093 str r3, [r2, #8]
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8001372: 687b ldr r3, [r7, #4]
+ 8001374: 681a ldr r2, [r3, #0]
+ 8001376: 687b ldr r3, [r7, #4]
+ 8001378: 3304 adds r3, #4
+ 800137a: 4619 mov r1, r3
+ 800137c: 4610 mov r0, r2
+ 800137e: f000 f89f bl 80014c0 <TIM_Base_SetConfig>
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ 8001382: 687b ldr r3, [r7, #4]
+ 8001384: 681b ldr r3, [r3, #0]
+ 8001386: 689b ldr r3, [r3, #8]
+ 8001388: 617b str r3, [r7, #20]
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+ 800138a: 687b ldr r3, [r7, #4]
+ 800138c: 681b ldr r3, [r3, #0]
+ 800138e: 699b ldr r3, [r3, #24]
+ 8001390: 613b str r3, [r7, #16]
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+ 8001392: 687b ldr r3, [r7, #4]
+ 8001394: 681b ldr r3, [r3, #0]
+ 8001396: 6a1b ldr r3, [r3, #32]
+ 8001398: 60fb str r3, [r7, #12]
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+ 800139a: 683b ldr r3, [r7, #0]
+ 800139c: 681b ldr r3, [r3, #0]
+ 800139e: 697a ldr r2, [r7, #20]
+ 80013a0: 4313 orrs r3, r2
+ 80013a2: 617b str r3, [r7, #20]
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ 80013a4: 693a ldr r2, [r7, #16]
+ 80013a6: 4b27 ldr r3, [pc, #156] ; (8001444 <HAL_TIM_Encoder_Init+0x118>)
+ 80013a8: 4013 ands r3, r2
+ 80013aa: 613b str r3, [r7, #16]
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 80013ac: 683b ldr r3, [r7, #0]
+ 80013ae: 689a ldr r2, [r3, #8]
+ 80013b0: 683b ldr r3, [r7, #0]
+ 80013b2: 699b ldr r3, [r3, #24]
+ 80013b4: 021b lsls r3, r3, #8
+ 80013b6: 4313 orrs r3, r2
+ 80013b8: 693a ldr r2, [r7, #16]
+ 80013ba: 4313 orrs r3, r2
+ 80013bc: 613b str r3, [r7, #16]
+
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ 80013be: 693a ldr r2, [r7, #16]
+ 80013c0: 4b21 ldr r3, [pc, #132] ; (8001448 <HAL_TIM_Encoder_Init+0x11c>)
+ 80013c2: 4013 ands r3, r2
+ 80013c4: 613b str r3, [r7, #16]
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ 80013c6: 693a ldr r2, [r7, #16]
+ 80013c8: 4b20 ldr r3, [pc, #128] ; (800144c <HAL_TIM_Encoder_Init+0x120>)
+ 80013ca: 4013 ands r3, r2
+ 80013cc: 613b str r3, [r7, #16]
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 80013ce: 683b ldr r3, [r7, #0]
+ 80013d0: 68da ldr r2, [r3, #12]
+ 80013d2: 683b ldr r3, [r7, #0]
+ 80013d4: 69db ldr r3, [r3, #28]
+ 80013d6: 021b lsls r3, r3, #8
+ 80013d8: 4313 orrs r3, r2
+ 80013da: 693a ldr r2, [r7, #16]
+ 80013dc: 4313 orrs r3, r2
+ 80013de: 613b str r3, [r7, #16]
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 80013e0: 683b ldr r3, [r7, #0]
+ 80013e2: 691b ldr r3, [r3, #16]
+ 80013e4: 011a lsls r2, r3, #4
+ 80013e6: 683b ldr r3, [r7, #0]
+ 80013e8: 6a1b ldr r3, [r3, #32]
+ 80013ea: 031b lsls r3, r3, #12
+ 80013ec: 4313 orrs r3, r2
+ 80013ee: 693a ldr r2, [r7, #16]
+ 80013f0: 4313 orrs r3, r2
+ 80013f2: 613b str r3, [r7, #16]
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ 80013f4: 68fb ldr r3, [r7, #12]
+ 80013f6: f023 0322 bic.w r3, r3, #34 ; 0x22
+ 80013fa: 60fb str r3, [r7, #12]
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ 80013fc: 68fb ldr r3, [r7, #12]
+ 80013fe: f023 0388 bic.w r3, r3, #136 ; 0x88
+ 8001402: 60fb str r3, [r7, #12]
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 8001404: 683b ldr r3, [r7, #0]
+ 8001406: 685a ldr r2, [r3, #4]
+ 8001408: 683b ldr r3, [r7, #0]
+ 800140a: 695b ldr r3, [r3, #20]
+ 800140c: 011b lsls r3, r3, #4
+ 800140e: 4313 orrs r3, r2
+ 8001410: 68fa ldr r2, [r7, #12]
+ 8001412: 4313 orrs r3, r2
+ 8001414: 60fb str r3, [r7, #12]
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ 8001416: 687b ldr r3, [r7, #4]
+ 8001418: 681b ldr r3, [r3, #0]
+ 800141a: 697a ldr r2, [r7, #20]
+ 800141c: 609a str r2, [r3, #8]
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+ 800141e: 687b ldr r3, [r7, #4]
+ 8001420: 681b ldr r3, [r3, #0]
+ 8001422: 693a ldr r2, [r7, #16]
+ 8001424: 619a str r2, [r3, #24]
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+ 8001426: 687b ldr r3, [r7, #4]
+ 8001428: 681b ldr r3, [r3, #0]
+ 800142a: 68fa ldr r2, [r7, #12]
+ 800142c: 621a str r2, [r3, #32]
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+ 800142e: 687b ldr r3, [r7, #4]
+ 8001430: 2201 movs r2, #1
+ 8001432: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ return HAL_OK;
+ 8001436: 2300 movs r3, #0
+}
+ 8001438: 4618 mov r0, r3
+ 800143a: 3718 adds r7, #24
+ 800143c: 46bd mov sp, r7
+ 800143e: bd80 pop {r7, pc}
+ 8001440: fffebff8 .word 0xfffebff8
+ 8001444: fffffcfc .word 0xfffffcfc
+ 8001448: fffff3f3 .word 0xfffff3f3
+ 800144c: ffff0f0f .word 0xffff0f0f
+
+08001450 <HAL_TIM_Encoder_Start>:
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ 8001450: b580 push {r7, lr}
+ 8001452: b082 sub sp, #8
+ 8001454: af00 add r7, sp, #0
+ 8001456: 6078 str r0, [r7, #4]
+ 8001458: 6039 str r1, [r7, #0]
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ 800145a: 683b ldr r3, [r7, #0]
+ 800145c: 2b00 cmp r3, #0
+ 800145e: d002 beq.n 8001466 <HAL_TIM_Encoder_Start+0x16>
+ 8001460: 2b04 cmp r3, #4
+ 8001462: d008 beq.n 8001476 <HAL_TIM_Encoder_Start+0x26>
+ 8001464: e00f b.n 8001486 <HAL_TIM_Encoder_Start+0x36>
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 8001466: 687b ldr r3, [r7, #4]
+ 8001468: 681b ldr r3, [r3, #0]
+ 800146a: 2201 movs r2, #1
+ 800146c: 2100 movs r1, #0
+ 800146e: 4618 mov r0, r3
+ 8001470: f000 f8c6 bl 8001600 <TIM_CCxChannelCmd>
+ break;
+ 8001474: e016 b.n 80014a4 <HAL_TIM_Encoder_Start+0x54>
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 8001476: 687b ldr r3, [r7, #4]
+ 8001478: 681b ldr r3, [r3, #0]
+ 800147a: 2201 movs r2, #1
+ 800147c: 2104 movs r1, #4
+ 800147e: 4618 mov r0, r3
+ 8001480: f000 f8be bl 8001600 <TIM_CCxChannelCmd>
+ break;
+ 8001484: e00e b.n 80014a4 <HAL_TIM_Encoder_Start+0x54>
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 8001486: 687b ldr r3, [r7, #4]
+ 8001488: 681b ldr r3, [r3, #0]
+ 800148a: 2201 movs r2, #1
+ 800148c: 2100 movs r1, #0
+ 800148e: 4618 mov r0, r3
+ 8001490: f000 f8b6 bl 8001600 <TIM_CCxChannelCmd>
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 8001494: 687b ldr r3, [r7, #4]
+ 8001496: 681b ldr r3, [r3, #0]
+ 8001498: 2201 movs r2, #1
+ 800149a: 2104 movs r1, #4
+ 800149c: 4618 mov r0, r3
+ 800149e: f000 f8af bl 8001600 <TIM_CCxChannelCmd>
+ break;
+ 80014a2: bf00 nop
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+ 80014a4: 687b ldr r3, [r7, #4]
+ 80014a6: 681b ldr r3, [r3, #0]
+ 80014a8: 681a ldr r2, [r3, #0]
+ 80014aa: 687b ldr r3, [r7, #4]
+ 80014ac: 681b ldr r3, [r3, #0]
+ 80014ae: f042 0201 orr.w r2, r2, #1
+ 80014b2: 601a str r2, [r3, #0]
+
+ /* Return function status */
+ return HAL_OK;
+ 80014b4: 2300 movs r3, #0
+}
+ 80014b6: 4618 mov r0, r3
+ 80014b8: 3708 adds r7, #8
+ 80014ba: 46bd mov sp, r7
+ 80014bc: bd80 pop {r7, pc}
+ ...
+
+080014c0 <TIM_Base_SetConfig>:
+ * @param TIMx TIM peripheral
+ * @param Structure TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ 80014c0: b480 push {r7}
+ 80014c2: b085 sub sp, #20
+ 80014c4: af00 add r7, sp, #0
+ 80014c6: 6078 str r0, [r7, #4]
+ 80014c8: 6039 str r1, [r7, #0]
+ uint32_t tmpcr1;
+ tmpcr1 = TIMx->CR1;
+ 80014ca: 687b ldr r3, [r7, #4]
+ 80014cc: 681b ldr r3, [r3, #0]
+ 80014ce: 60fb str r3, [r7, #12]
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 80014d0: 687b ldr r3, [r7, #4]
+ 80014d2: 4a40 ldr r2, [pc, #256] ; (80015d4 <TIM_Base_SetConfig+0x114>)
+ 80014d4: 4293 cmp r3, r2
+ 80014d6: d013 beq.n 8001500 <TIM_Base_SetConfig+0x40>
+ 80014d8: 687b ldr r3, [r7, #4]
+ 80014da: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 80014de: d00f beq.n 8001500 <TIM_Base_SetConfig+0x40>
+ 80014e0: 687b ldr r3, [r7, #4]
+ 80014e2: 4a3d ldr r2, [pc, #244] ; (80015d8 <TIM_Base_SetConfig+0x118>)
+ 80014e4: 4293 cmp r3, r2
+ 80014e6: d00b beq.n 8001500 <TIM_Base_SetConfig+0x40>
+ 80014e8: 687b ldr r3, [r7, #4]
+ 80014ea: 4a3c ldr r2, [pc, #240] ; (80015dc <TIM_Base_SetConfig+0x11c>)
+ 80014ec: 4293 cmp r3, r2
+ 80014ee: d007 beq.n 8001500 <TIM_Base_SetConfig+0x40>
+ 80014f0: 687b ldr r3, [r7, #4]
+ 80014f2: 4a3b ldr r2, [pc, #236] ; (80015e0 <TIM_Base_SetConfig+0x120>)
+ 80014f4: 4293 cmp r3, r2
+ 80014f6: d003 beq.n 8001500 <TIM_Base_SetConfig+0x40>
+ 80014f8: 687b ldr r3, [r7, #4]
+ 80014fa: 4a3a ldr r2, [pc, #232] ; (80015e4 <TIM_Base_SetConfig+0x124>)
+ 80014fc: 4293 cmp r3, r2
+ 80014fe: d108 bne.n 8001512 <TIM_Base_SetConfig+0x52>
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 8001500: 68fb ldr r3, [r7, #12]
+ 8001502: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 8001506: 60fb str r3, [r7, #12]
+ tmpcr1 |= Structure->CounterMode;
+ 8001508: 683b ldr r3, [r7, #0]
+ 800150a: 685b ldr r3, [r3, #4]
+ 800150c: 68fa ldr r2, [r7, #12]
+ 800150e: 4313 orrs r3, r2
+ 8001510: 60fb str r3, [r7, #12]
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 8001512: 687b ldr r3, [r7, #4]
+ 8001514: 4a2f ldr r2, [pc, #188] ; (80015d4 <TIM_Base_SetConfig+0x114>)
+ 8001516: 4293 cmp r3, r2
+ 8001518: d02b beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 800151a: 687b ldr r3, [r7, #4]
+ 800151c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 8001520: d027 beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 8001522: 687b ldr r3, [r7, #4]
+ 8001524: 4a2c ldr r2, [pc, #176] ; (80015d8 <TIM_Base_SetConfig+0x118>)
+ 8001526: 4293 cmp r3, r2
+ 8001528: d023 beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 800152a: 687b ldr r3, [r7, #4]
+ 800152c: 4a2b ldr r2, [pc, #172] ; (80015dc <TIM_Base_SetConfig+0x11c>)
+ 800152e: 4293 cmp r3, r2
+ 8001530: d01f beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 8001532: 687b ldr r3, [r7, #4]
+ 8001534: 4a2a ldr r2, [pc, #168] ; (80015e0 <TIM_Base_SetConfig+0x120>)
+ 8001536: 4293 cmp r3, r2
+ 8001538: d01b beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 800153a: 687b ldr r3, [r7, #4]
+ 800153c: 4a29 ldr r2, [pc, #164] ; (80015e4 <TIM_Base_SetConfig+0x124>)
+ 800153e: 4293 cmp r3, r2
+ 8001540: d017 beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 8001542: 687b ldr r3, [r7, #4]
+ 8001544: 4a28 ldr r2, [pc, #160] ; (80015e8 <TIM_Base_SetConfig+0x128>)
+ 8001546: 4293 cmp r3, r2
+ 8001548: d013 beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 800154a: 687b ldr r3, [r7, #4]
+ 800154c: 4a27 ldr r2, [pc, #156] ; (80015ec <TIM_Base_SetConfig+0x12c>)
+ 800154e: 4293 cmp r3, r2
+ 8001550: d00f beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 8001552: 687b ldr r3, [r7, #4]
+ 8001554: 4a26 ldr r2, [pc, #152] ; (80015f0 <TIM_Base_SetConfig+0x130>)
+ 8001556: 4293 cmp r3, r2
+ 8001558: d00b beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 800155a: 687b ldr r3, [r7, #4]
+ 800155c: 4a25 ldr r2, [pc, #148] ; (80015f4 <TIM_Base_SetConfig+0x134>)
+ 800155e: 4293 cmp r3, r2
+ 8001560: d007 beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 8001562: 687b ldr r3, [r7, #4]
+ 8001564: 4a24 ldr r2, [pc, #144] ; (80015f8 <TIM_Base_SetConfig+0x138>)
+ 8001566: 4293 cmp r3, r2
+ 8001568: d003 beq.n 8001572 <TIM_Base_SetConfig+0xb2>
+ 800156a: 687b ldr r3, [r7, #4]
+ 800156c: 4a23 ldr r2, [pc, #140] ; (80015fc <TIM_Base_SetConfig+0x13c>)
+ 800156e: 4293 cmp r3, r2
+ 8001570: d108 bne.n 8001584 <TIM_Base_SetConfig+0xc4>
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ 8001572: 68fb ldr r3, [r7, #12]
+ 8001574: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8001578: 60fb str r3, [r7, #12]
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 800157a: 683b ldr r3, [r7, #0]
+ 800157c: 68db ldr r3, [r3, #12]
+ 800157e: 68fa ldr r2, [r7, #12]
+ 8001580: 4313 orrs r3, r2
+ 8001582: 60fb str r3, [r7, #12]
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 8001584: 68fb ldr r3, [r7, #12]
+ 8001586: f023 0280 bic.w r2, r3, #128 ; 0x80
+ 800158a: 683b ldr r3, [r7, #0]
+ 800158c: 695b ldr r3, [r3, #20]
+ 800158e: 4313 orrs r3, r2
+ 8001590: 60fb str r3, [r7, #12]
+
+ TIMx->CR1 = tmpcr1;
+ 8001592: 687b ldr r3, [r7, #4]
+ 8001594: 68fa ldr r2, [r7, #12]
+ 8001596: 601a str r2, [r3, #0]
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+ 8001598: 683b ldr r3, [r7, #0]
+ 800159a: 689a ldr r2, [r3, #8]
+ 800159c: 687b ldr r3, [r7, #4]
+ 800159e: 62da str r2, [r3, #44] ; 0x2c
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Structure->Prescaler;
+ 80015a0: 683b ldr r3, [r7, #0]
+ 80015a2: 681a ldr r2, [r3, #0]
+ 80015a4: 687b ldr r3, [r7, #4]
+ 80015a6: 629a str r2, [r3, #40] ; 0x28
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ 80015a8: 687b ldr r3, [r7, #4]
+ 80015aa: 4a0a ldr r2, [pc, #40] ; (80015d4 <TIM_Base_SetConfig+0x114>)
+ 80015ac: 4293 cmp r3, r2
+ 80015ae: d003 beq.n 80015b8 <TIM_Base_SetConfig+0xf8>
+ 80015b0: 687b ldr r3, [r7, #4]
+ 80015b2: 4a0c ldr r2, [pc, #48] ; (80015e4 <TIM_Base_SetConfig+0x124>)
+ 80015b4: 4293 cmp r3, r2
+ 80015b6: d103 bne.n 80015c0 <TIM_Base_SetConfig+0x100>
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ 80015b8: 683b ldr r3, [r7, #0]
+ 80015ba: 691a ldr r2, [r3, #16]
+ 80015bc: 687b ldr r3, [r7, #4]
+ 80015be: 631a str r2, [r3, #48] ; 0x30
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+ 80015c0: 687b ldr r3, [r7, #4]
+ 80015c2: 2201 movs r2, #1
+ 80015c4: 615a str r2, [r3, #20]
+}
+ 80015c6: bf00 nop
+ 80015c8: 3714 adds r7, #20
+ 80015ca: 46bd mov sp, r7
+ 80015cc: f85d 7b04 ldr.w r7, [sp], #4
+ 80015d0: 4770 bx lr
+ 80015d2: bf00 nop
+ 80015d4: 40010000 .word 0x40010000
+ 80015d8: 40000400 .word 0x40000400
+ 80015dc: 40000800 .word 0x40000800
+ 80015e0: 40000c00 .word 0x40000c00
+ 80015e4: 40010400 .word 0x40010400
+ 80015e8: 40014000 .word 0x40014000
+ 80015ec: 40014400 .word 0x40014400
+ 80015f0: 40014800 .word 0x40014800
+ 80015f4: 40001800 .word 0x40001800
+ 80015f8: 40001c00 .word 0x40001c00
+ 80015fc: 40002000 .word 0x40002000
+
+08001600 <TIM_CCxChannelCmd>:
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ 8001600: b480 push {r7}
+ 8001602: b087 sub sp, #28
+ 8001604: af00 add r7, sp, #0
+ 8001606: 60f8 str r0, [r7, #12]
+ 8001608: 60b9 str r1, [r7, #8]
+ 800160a: 607a str r2, [r7, #4]
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ 800160c: 68bb ldr r3, [r7, #8]
+ 800160e: f003 031f and.w r3, r3, #31
+ 8001612: 2201 movs r2, #1
+ 8001614: fa02 f303 lsl.w r3, r2, r3
+ 8001618: 617b str r3, [r7, #20]
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+ 800161a: 68fb ldr r3, [r7, #12]
+ 800161c: 6a1a ldr r2, [r3, #32]
+ 800161e: 697b ldr r3, [r7, #20]
+ 8001620: 43db mvns r3, r3
+ 8001622: 401a ands r2, r3
+ 8001624: 68fb ldr r3, [r7, #12]
+ 8001626: 621a str r2, [r3, #32]
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 8001628: 68fb ldr r3, [r7, #12]
+ 800162a: 6a1a ldr r2, [r3, #32]
+ 800162c: 68bb ldr r3, [r7, #8]
+ 800162e: f003 031f and.w r3, r3, #31
+ 8001632: 6879 ldr r1, [r7, #4]
+ 8001634: fa01 f303 lsl.w r3, r1, r3
+ 8001638: 431a orrs r2, r3
+ 800163a: 68fb ldr r3, [r7, #12]
+ 800163c: 621a str r2, [r3, #32]
+}
+ 800163e: bf00 nop
+ 8001640: 371c adds r7, #28
+ 8001642: 46bd mov sp, r7
+ 8001644: f85d 7b04 ldr.w r7, [sp], #4
+ 8001648: 4770 bx lr
+ ...
+
+0800164c <HAL_TIMEx_MasterConfigSynchronization>:
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ 800164c: b480 push {r7}
+ 800164e: b085 sub sp, #20
+ 8001650: af00 add r7, sp, #0
+ 8001652: 6078 str r0, [r7, #4]
+ 8001654: 6039 str r1, [r7, #0]
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+ 8001656: 687b ldr r3, [r7, #4]
+ 8001658: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 800165c: 2b01 cmp r3, #1
+ 800165e: d101 bne.n 8001664 <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 8001660: 2302 movs r3, #2
+ 8001662: e045 b.n 80016f0 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
+ 8001664: 687b ldr r3, [r7, #4]
+ 8001666: 2201 movs r2, #1
+ 8001668: f883 203c strb.w r2, [r3, #60] ; 0x3c
+
+ /* Change the handler state */
+ htim->State = HAL_TIM_STATE_BUSY;
+ 800166c: 687b ldr r3, [r7, #4]
+ 800166e: 2202 movs r2, #2
+ 8001670: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+ 8001674: 687b ldr r3, [r7, #4]
+ 8001676: 681b ldr r3, [r3, #0]
+ 8001678: 685b ldr r3, [r3, #4]
+ 800167a: 60fb str r3, [r7, #12]
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ 800167c: 687b ldr r3, [r7, #4]
+ 800167e: 681b ldr r3, [r3, #0]
+ 8001680: 689b ldr r3, [r3, #8]
+ 8001682: 60bb str r3, [r7, #8]
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ 8001684: 687b ldr r3, [r7, #4]
+ 8001686: 681b ldr r3, [r3, #0]
+ 8001688: 4a1c ldr r2, [pc, #112] ; (80016fc <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
+ 800168a: 4293 cmp r3, r2
+ 800168c: d004 beq.n 8001698 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
+ 800168e: 687b ldr r3, [r7, #4]
+ 8001690: 681b ldr r3, [r3, #0]
+ 8001692: 4a1b ldr r2, [pc, #108] ; (8001700 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
+ 8001694: 4293 cmp r3, r2
+ 8001696: d108 bne.n 80016aa <HAL_TIMEx_MasterConfigSynchronization+0x5e>
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ 8001698: 68fb ldr r3, [r7, #12]
+ 800169a: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
+ 800169e: 60fb str r3, [r7, #12]
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ 80016a0: 683b ldr r3, [r7, #0]
+ 80016a2: 685b ldr r3, [r3, #4]
+ 80016a4: 68fa ldr r2, [r7, #12]
+ 80016a6: 4313 orrs r3, r2
+ 80016a8: 60fb str r3, [r7, #12]
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ 80016aa: 68fb ldr r3, [r7, #12]
+ 80016ac: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 80016b0: 60fb str r3, [r7, #12]
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+ 80016b2: 683b ldr r3, [r7, #0]
+ 80016b4: 681b ldr r3, [r3, #0]
+ 80016b6: 68fa ldr r2, [r7, #12]
+ 80016b8: 4313 orrs r3, r2
+ 80016ba: 60fb str r3, [r7, #12]
+
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ 80016bc: 68bb ldr r3, [r7, #8]
+ 80016be: f023 0380 bic.w r3, r3, #128 ; 0x80
+ 80016c2: 60bb str r3, [r7, #8]
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+ 80016c4: 683b ldr r3, [r7, #0]
+ 80016c6: 689b ldr r3, [r3, #8]
+ 80016c8: 68ba ldr r2, [r7, #8]
+ 80016ca: 4313 orrs r3, r2
+ 80016cc: 60bb str r3, [r7, #8]
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+ 80016ce: 687b ldr r3, [r7, #4]
+ 80016d0: 681b ldr r3, [r3, #0]
+ 80016d2: 68fa ldr r2, [r7, #12]
+ 80016d4: 605a str r2, [r3, #4]
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ 80016d6: 687b ldr r3, [r7, #4]
+ 80016d8: 681b ldr r3, [r3, #0]
+ 80016da: 68ba ldr r2, [r7, #8]
+ 80016dc: 609a str r2, [r3, #8]
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+ 80016de: 687b ldr r3, [r7, #4]
+ 80016e0: 2201 movs r2, #1
+ 80016e2: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ __HAL_UNLOCK(htim);
+ 80016e6: 687b ldr r3, [r7, #4]
+ 80016e8: 2200 movs r2, #0
+ 80016ea: f883 203c strb.w r2, [r3, #60] ; 0x3c
+
+ return HAL_OK;
+ 80016ee: 2300 movs r3, #0
+}
+ 80016f0: 4618 mov r0, r3
+ 80016f2: 3714 adds r7, #20
+ 80016f4: 46bd mov sp, r7
+ 80016f6: f85d 7b04 ldr.w r7, [sp], #4
+ 80016fa: 4770 bx lr
+ 80016fc: 40010000 .word 0x40010000
+ 8001700: 40010400 .word 0x40010400
+
+08001704 <main>:
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ 8001704: b580 push {r7, lr}
+ 8001706: b082 sub sp, #8
+ 8001708: af00 add r7, sp, #0
+
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ 800170a: f7fe ff15 bl 8000538 <HAL_Init>
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+ 800170e: f000 f859 bl 80017c4 <SystemClock_Config>
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ 8001712: f000 f95f bl 80019d4 <MX_GPIO_Init>
+ MX_TIM2_Init();
+ 8001716: f000 f8b1 bl 800187c <MX_TIM2_Init>
+ MX_TIM5_Init();
+ 800171a: f000 f905 bl 8001928 <MX_TIM5_Init>
+ /* USER CODE BEGIN 2 */
+ HAL_TIM_Encoder_Start(&htim2, TIM_CHANNEL_ALL);
+ 800171e: 213c movs r1, #60 ; 0x3c
+ 8001720: 4826 ldr r0, [pc, #152] ; (80017bc <main+0xb8>)
+ 8001722: f7ff fe95 bl 8001450 <HAL_TIM_Encoder_Start>
+ HAL_TIM_Encoder_Start(&htim5, TIM_CHANNEL_ALL);
+ 8001726: 213c movs r1, #60 ; 0x3c
+ 8001728: 4825 ldr r0, [pc, #148] ; (80017c0 <main+0xbc>)
+ 800172a: f7ff fe91 bl 8001450 <HAL_TIM_Encoder_Start>
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ uint32_t i = 0;
+ 800172e: 2300 movs r3, #0
+ 8001730: 607b str r3, [r7, #4]
+ /* USER CODE BEGIN 3 */
+ /*
+ * un giro completo usando risoluzione 4x (encoder mode TI1 and TI2) è 148000
+ * un giro completo usando risoluzine 2x è 74000
+ */
+ i = TIM2->CNT;
+ 8001732: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 8001736: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001738: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 800173a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 800173e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001740: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 8001742: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 8001746: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001748: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 800174a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 800174e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001750: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 8001752: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 8001756: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001758: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 800175a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 800175e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001760: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 8001762: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 8001766: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001768: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 800176a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 800176e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001770: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 8001772: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 8001776: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001778: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 800177a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 800177e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001780: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 8001782: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 8001786: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001788: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 800178a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 800178e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001790: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 8001792: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 8001796: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001798: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 800179a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 800179e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80017a0: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 80017a2: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 80017a6: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80017a8: 607b str r3, [r7, #4]
+ i = TIM2->CNT;
+ 80017aa: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 80017ae: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80017b0: 607b str r3, [r7, #4]
+
+ TIM2->CNT=0;
+ 80017b2: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
+ 80017b6: 2200 movs r2, #0
+ 80017b8: 625a str r2, [r3, #36] ; 0x24
+ i = TIM2->CNT;
+ 80017ba: e7ba b.n 8001732 <main+0x2e>
+ 80017bc: 2000006c .word 0x2000006c
+ 80017c0: 2000002c .word 0x2000002c
+
+080017c4 <SystemClock_Config>:
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ 80017c4: b580 push {r7, lr}
+ 80017c6: b094 sub sp, #80 ; 0x50
+ 80017c8: af00 add r7, sp, #0
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 80017ca: f107 031c add.w r3, r7, #28
+ 80017ce: 2234 movs r2, #52 ; 0x34
+ 80017d0: 2100 movs r1, #0
+ 80017d2: 4618 mov r0, r3
+ 80017d4: f000 fa90 bl 8001cf8 <memset>
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 80017d8: f107 0308 add.w r3, r7, #8
+ 80017dc: 2200 movs r2, #0
+ 80017de: 601a str r2, [r3, #0]
+ 80017e0: 605a str r2, [r3, #4]
+ 80017e2: 609a str r2, [r3, #8]
+ 80017e4: 60da str r2, [r3, #12]
+ 80017e6: 611a str r2, [r3, #16]
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 80017e8: 4b22 ldr r3, [pc, #136] ; (8001874 <SystemClock_Config+0xb0>)
+ 80017ea: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80017ec: 4a21 ldr r2, [pc, #132] ; (8001874 <SystemClock_Config+0xb0>)
+ 80017ee: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 80017f2: 6413 str r3, [r2, #64] ; 0x40
+ 80017f4: 4b1f ldr r3, [pc, #124] ; (8001874 <SystemClock_Config+0xb0>)
+ 80017f6: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80017f8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 80017fc: 607b str r3, [r7, #4]
+ 80017fe: 687b ldr r3, [r7, #4]
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+ 8001800: 4b1d ldr r3, [pc, #116] ; (8001878 <SystemClock_Config+0xb4>)
+ 8001802: 681b ldr r3, [r3, #0]
+ 8001804: f423 4340 bic.w r3, r3, #49152 ; 0xc000
+ 8001808: 4a1b ldr r2, [pc, #108] ; (8001878 <SystemClock_Config+0xb4>)
+ 800180a: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 800180e: 6013 str r3, [r2, #0]
+ 8001810: 4b19 ldr r3, [pc, #100] ; (8001878 <SystemClock_Config+0xb4>)
+ 8001812: 681b ldr r3, [r3, #0]
+ 8001814: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 8001818: 603b str r3, [r7, #0]
+ 800181a: 683b ldr r3, [r7, #0]
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ 800181c: 2302 movs r3, #2
+ 800181e: 61fb str r3, [r7, #28]
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ 8001820: 2301 movs r3, #1
+ 8001822: 62bb str r3, [r7, #40] ; 0x28
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ 8001824: 2310 movs r3, #16
+ 8001826: 62fb str r3, [r7, #44] ; 0x2c
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ 8001828: 2300 movs r3, #0
+ 800182a: 637b str r3, [r7, #52] ; 0x34
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 800182c: f107 031c add.w r3, r7, #28
+ 8001830: 4618 mov r0, r3
+ 8001832: f7ff f96f bl 8000b14 <HAL_RCC_OscConfig>
+ 8001836: 4603 mov r3, r0
+ 8001838: 2b00 cmp r3, #0
+ 800183a: d001 beq.n 8001840 <SystemClock_Config+0x7c>
+ {
+ Error_Handler();
+ 800183c: f000 f8ee bl 8001a1c <Error_Handler>
+ }
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 8001840: 230f movs r3, #15
+ 8001842: 60bb str r3, [r7, #8]
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ 8001844: 2300 movs r3, #0
+ 8001846: 60fb str r3, [r7, #12]
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 8001848: 2300 movs r3, #0
+ 800184a: 613b str r3, [r7, #16]
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 800184c: 2300 movs r3, #0
+ 800184e: 617b str r3, [r7, #20]
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 8001850: 2300 movs r3, #0
+ 8001852: 61bb str r3, [r7, #24]
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ 8001854: f107 0308 add.w r3, r7, #8
+ 8001858: 2100 movs r1, #0
+ 800185a: 4618 mov r0, r3
+ 800185c: f7ff fbcc bl 8000ff8 <HAL_RCC_ClockConfig>
+ 8001860: 4603 mov r3, r0
+ 8001862: 2b00 cmp r3, #0
+ 8001864: d001 beq.n 800186a <SystemClock_Config+0xa6>
+ {
+ Error_Handler();
+ 8001866: f000 f8d9 bl 8001a1c <Error_Handler>
+ }
+}
+ 800186a: bf00 nop
+ 800186c: 3750 adds r7, #80 ; 0x50
+ 800186e: 46bd mov sp, r7
+ 8001870: bd80 pop {r7, pc}
+ 8001872: bf00 nop
+ 8001874: 40023800 .word 0x40023800
+ 8001878: 40007000 .word 0x40007000
+
+0800187c <MX_TIM2_Init>:
+ * @brief TIM2 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM2_Init(void)
+{
+ 800187c: b580 push {r7, lr}
+ 800187e: b08c sub sp, #48 ; 0x30
+ 8001880: af00 add r7, sp, #0
+
+ /* USER CODE BEGIN TIM2_Init 0 */
+
+ /* USER CODE END TIM2_Init 0 */
+
+ TIM_Encoder_InitTypeDef sConfig = {0};
+ 8001882: f107 030c add.w r3, r7, #12
+ 8001886: 2224 movs r2, #36 ; 0x24
+ 8001888: 2100 movs r1, #0
+ 800188a: 4618 mov r0, r3
+ 800188c: f000 fa34 bl 8001cf8 <memset>
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8001890: 463b mov r3, r7
+ 8001892: 2200 movs r2, #0
+ 8001894: 601a str r2, [r3, #0]
+ 8001896: 605a str r2, [r3, #4]
+ 8001898: 609a str r2, [r3, #8]
+
+ /* USER CODE BEGIN TIM2_Init 1 */
+
+ /* USER CODE END TIM2_Init 1 */
+ htim2.Instance = TIM2;
+ 800189a: 4b21 ldr r3, [pc, #132] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 800189c: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
+ 80018a0: 601a str r2, [r3, #0]
+ htim2.Init.Prescaler = 0;
+ 80018a2: 4b1f ldr r3, [pc, #124] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 80018a4: 2200 movs r2, #0
+ 80018a6: 605a str r2, [r3, #4]
+ htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 80018a8: 4b1d ldr r3, [pc, #116] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 80018aa: 2200 movs r2, #0
+ 80018ac: 609a str r2, [r3, #8]
+ htim2.Init.Period = 148000;
+ 80018ae: 4b1c ldr r3, [pc, #112] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 80018b0: 4a1c ldr r2, [pc, #112] ; (8001924 <MX_TIM2_Init+0xa8>)
+ 80018b2: 60da str r2, [r3, #12]
+ htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 80018b4: 4b1a ldr r3, [pc, #104] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 80018b6: 2200 movs r2, #0
+ 80018b8: 611a str r2, [r3, #16]
+ htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 80018ba: 4b19 ldr r3, [pc, #100] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 80018bc: 2200 movs r2, #0
+ 80018be: 619a str r2, [r3, #24]
+ sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
+ 80018c0: 2303 movs r3, #3
+ 80018c2: 60fb str r3, [r7, #12]
+ sConfig.IC1Polarity = TIM_ICPOLARITY_FALLING;
+ 80018c4: 2302 movs r3, #2
+ 80018c6: 613b str r3, [r7, #16]
+ sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+ 80018c8: 2301 movs r3, #1
+ 80018ca: 617b str r3, [r7, #20]
+ sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
+ 80018cc: 2300 movs r3, #0
+ 80018ce: 61bb str r3, [r7, #24]
+ sConfig.IC1Filter = 0;
+ 80018d0: 2300 movs r3, #0
+ 80018d2: 61fb str r3, [r7, #28]
+ sConfig.IC2Polarity = TIM_ICPOLARITY_FALLING;
+ 80018d4: 2302 movs r3, #2
+ 80018d6: 623b str r3, [r7, #32]
+ sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+ 80018d8: 2301 movs r3, #1
+ 80018da: 627b str r3, [r7, #36] ; 0x24
+ sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
+ 80018dc: 2300 movs r3, #0
+ 80018de: 62bb str r3, [r7, #40] ; 0x28
+ sConfig.IC2Filter = 0;
+ 80018e0: 2300 movs r3, #0
+ 80018e2: 62fb str r3, [r7, #44] ; 0x2c
+ if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)
+ 80018e4: f107 030c add.w r3, r7, #12
+ 80018e8: 4619 mov r1, r3
+ 80018ea: 480d ldr r0, [pc, #52] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 80018ec: f7ff fd1e bl 800132c <HAL_TIM_Encoder_Init>
+ 80018f0: 4603 mov r3, r0
+ 80018f2: 2b00 cmp r3, #0
+ 80018f4: d001 beq.n 80018fa <MX_TIM2_Init+0x7e>
+ {
+ Error_Handler();
+ 80018f6: f000 f891 bl 8001a1c <Error_Handler>
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 80018fa: 2300 movs r3, #0
+ 80018fc: 603b str r3, [r7, #0]
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 80018fe: 2300 movs r3, #0
+ 8001900: 60bb str r3, [r7, #8]
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+ 8001902: 463b mov r3, r7
+ 8001904: 4619 mov r1, r3
+ 8001906: 4806 ldr r0, [pc, #24] ; (8001920 <MX_TIM2_Init+0xa4>)
+ 8001908: f7ff fea0 bl 800164c <HAL_TIMEx_MasterConfigSynchronization>
+ 800190c: 4603 mov r3, r0
+ 800190e: 2b00 cmp r3, #0
+ 8001910: d001 beq.n 8001916 <MX_TIM2_Init+0x9a>
+ {
+ Error_Handler();
+ 8001912: f000 f883 bl 8001a1c <Error_Handler>
+ }
+ /* USER CODE BEGIN TIM2_Init 2 */
+
+ /* USER CODE END TIM2_Init 2 */
+
+}
+ 8001916: bf00 nop
+ 8001918: 3730 adds r7, #48 ; 0x30
+ 800191a: 46bd mov sp, r7
+ 800191c: bd80 pop {r7, pc}
+ 800191e: bf00 nop
+ 8001920: 2000006c .word 0x2000006c
+ 8001924: 00024220 .word 0x00024220
+
+08001928 <MX_TIM5_Init>:
+ * @brief TIM5 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM5_Init(void)
+{
+ 8001928: b580 push {r7, lr}
+ 800192a: b08c sub sp, #48 ; 0x30
+ 800192c: af00 add r7, sp, #0
+
+ /* USER CODE BEGIN TIM5_Init 0 */
+
+ /* USER CODE END TIM5_Init 0 */
+
+ TIM_Encoder_InitTypeDef sConfig = {0};
+ 800192e: f107 030c add.w r3, r7, #12
+ 8001932: 2224 movs r2, #36 ; 0x24
+ 8001934: 2100 movs r1, #0
+ 8001936: 4618 mov r0, r3
+ 8001938: f000 f9de bl 8001cf8 <memset>
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 800193c: 463b mov r3, r7
+ 800193e: 2200 movs r2, #0
+ 8001940: 601a str r2, [r3, #0]
+ 8001942: 605a str r2, [r3, #4]
+ 8001944: 609a str r2, [r3, #8]
+
+ /* USER CODE BEGIN TIM5_Init 1 */
+
+ /* USER CODE END TIM5_Init 1 */
+ htim5.Instance = TIM5;
+ 8001946: 4b21 ldr r3, [pc, #132] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 8001948: 4a21 ldr r2, [pc, #132] ; (80019d0 <MX_TIM5_Init+0xa8>)
+ 800194a: 601a str r2, [r3, #0]
+ htim5.Init.Prescaler = 0;
+ 800194c: 4b1f ldr r3, [pc, #124] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 800194e: 2200 movs r2, #0
+ 8001950: 605a str r2, [r3, #4]
+ htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001952: 4b1e ldr r3, [pc, #120] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 8001954: 2200 movs r2, #0
+ 8001956: 609a str r2, [r3, #8]
+ htim5.Init.Period = 4294967295;
+ 8001958: 4b1c ldr r3, [pc, #112] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 800195a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 800195e: 60da str r2, [r3, #12]
+ htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8001960: 4b1a ldr r3, [pc, #104] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 8001962: 2200 movs r2, #0
+ 8001964: 611a str r2, [r3, #16]
+ htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8001966: 4b19 ldr r3, [pc, #100] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 8001968: 2200 movs r2, #0
+ 800196a: 619a str r2, [r3, #24]
+ sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
+ 800196c: 2301 movs r3, #1
+ 800196e: 60fb str r3, [r7, #12]
+ sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
+ 8001970: 2300 movs r3, #0
+ 8001972: 613b str r3, [r7, #16]
+ sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+ 8001974: 2301 movs r3, #1
+ 8001976: 617b str r3, [r7, #20]
+ sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
+ 8001978: 2300 movs r3, #0
+ 800197a: 61bb str r3, [r7, #24]
+ sConfig.IC1Filter = 0;
+ 800197c: 2300 movs r3, #0
+ 800197e: 61fb str r3, [r7, #28]
+ sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
+ 8001980: 2300 movs r3, #0
+ 8001982: 623b str r3, [r7, #32]
+ sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+ 8001984: 2301 movs r3, #1
+ 8001986: 627b str r3, [r7, #36] ; 0x24
+ sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
+ 8001988: 2300 movs r3, #0
+ 800198a: 62bb str r3, [r7, #40] ; 0x28
+ sConfig.IC2Filter = 0;
+ 800198c: 2300 movs r3, #0
+ 800198e: 62fb str r3, [r7, #44] ; 0x2c
+ if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK)
+ 8001990: f107 030c add.w r3, r7, #12
+ 8001994: 4619 mov r1, r3
+ 8001996: 480d ldr r0, [pc, #52] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 8001998: f7ff fcc8 bl 800132c <HAL_TIM_Encoder_Init>
+ 800199c: 4603 mov r3, r0
+ 800199e: 2b00 cmp r3, #0
+ 80019a0: d001 beq.n 80019a6 <MX_TIM5_Init+0x7e>
+ {
+ Error_Handler();
+ 80019a2: f000 f83b bl 8001a1c <Error_Handler>
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 80019a6: 2300 movs r3, #0
+ 80019a8: 603b str r3, [r7, #0]
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 80019aa: 2300 movs r3, #0
+ 80019ac: 60bb str r3, [r7, #8]
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
+ 80019ae: 463b mov r3, r7
+ 80019b0: 4619 mov r1, r3
+ 80019b2: 4806 ldr r0, [pc, #24] ; (80019cc <MX_TIM5_Init+0xa4>)
+ 80019b4: f7ff fe4a bl 800164c <HAL_TIMEx_MasterConfigSynchronization>
+ 80019b8: 4603 mov r3, r0
+ 80019ba: 2b00 cmp r3, #0
+ 80019bc: d001 beq.n 80019c2 <MX_TIM5_Init+0x9a>
+ {
+ Error_Handler();
+ 80019be: f000 f82d bl 8001a1c <Error_Handler>
+ }
+ /* USER CODE BEGIN TIM5_Init 2 */
+
+ /* USER CODE END TIM5_Init 2 */
+
+}
+ 80019c2: bf00 nop
+ 80019c4: 3730 adds r7, #48 ; 0x30
+ 80019c6: 46bd mov sp, r7
+ 80019c8: bd80 pop {r7, pc}
+ 80019ca: bf00 nop
+ 80019cc: 2000002c .word 0x2000002c
+ 80019d0: 40000c00 .word 0x40000c00
+
+080019d4 <MX_GPIO_Init>:
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ 80019d4: b480 push {r7}
+ 80019d6: b083 sub sp, #12
+ 80019d8: af00 add r7, sp, #0
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80019da: 4b0f ldr r3, [pc, #60] ; (8001a18 <MX_GPIO_Init+0x44>)
+ 80019dc: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80019de: 4a0e ldr r2, [pc, #56] ; (8001a18 <MX_GPIO_Init+0x44>)
+ 80019e0: f043 0301 orr.w r3, r3, #1
+ 80019e4: 6313 str r3, [r2, #48] ; 0x30
+ 80019e6: 4b0c ldr r3, [pc, #48] ; (8001a18 <MX_GPIO_Init+0x44>)
+ 80019e8: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80019ea: f003 0301 and.w r3, r3, #1
+ 80019ee: 607b str r3, [r7, #4]
+ 80019f0: 687b ldr r3, [r7, #4]
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ 80019f2: 4b09 ldr r3, [pc, #36] ; (8001a18 <MX_GPIO_Init+0x44>)
+ 80019f4: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80019f6: 4a08 ldr r2, [pc, #32] ; (8001a18 <MX_GPIO_Init+0x44>)
+ 80019f8: f043 0302 orr.w r3, r3, #2
+ 80019fc: 6313 str r3, [r2, #48] ; 0x30
+ 80019fe: 4b06 ldr r3, [pc, #24] ; (8001a18 <MX_GPIO_Init+0x44>)
+ 8001a00: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001a02: f003 0302 and.w r3, r3, #2
+ 8001a06: 603b str r3, [r7, #0]
+ 8001a08: 683b ldr r3, [r7, #0]
+
+}
+ 8001a0a: bf00 nop
+ 8001a0c: 370c adds r7, #12
+ 8001a0e: 46bd mov sp, r7
+ 8001a10: f85d 7b04 ldr.w r7, [sp], #4
+ 8001a14: 4770 bx lr
+ 8001a16: bf00 nop
+ 8001a18: 40023800 .word 0x40023800
+
+08001a1c <Error_Handler>:
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ 8001a1c: b480 push {r7}
+ 8001a1e: af00 add r7, sp, #0
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+
+ /* USER CODE END Error_Handler_Debug */
+}
+ 8001a20: bf00 nop
+ 8001a22: 46bd mov sp, r7
+ 8001a24: f85d 7b04 ldr.w r7, [sp], #4
+ 8001a28: 4770 bx lr
+ ...
+
+08001a2c <HAL_MspInit>:
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ 8001a2c: b480 push {r7}
+ 8001a2e: b083 sub sp, #12
+ 8001a30: af00 add r7, sp, #0
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8001a32: 4b0f ldr r3, [pc, #60] ; (8001a70 <HAL_MspInit+0x44>)
+ 8001a34: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001a36: 4a0e ldr r2, [pc, #56] ; (8001a70 <HAL_MspInit+0x44>)
+ 8001a38: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8001a3c: 6413 str r3, [r2, #64] ; 0x40
+ 8001a3e: 4b0c ldr r3, [pc, #48] ; (8001a70 <HAL_MspInit+0x44>)
+ 8001a40: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001a42: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001a46: 607b str r3, [r7, #4]
+ 8001a48: 687b ldr r3, [r7, #4]
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8001a4a: 4b09 ldr r3, [pc, #36] ; (8001a70 <HAL_MspInit+0x44>)
+ 8001a4c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001a4e: 4a08 ldr r2, [pc, #32] ; (8001a70 <HAL_MspInit+0x44>)
+ 8001a50: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8001a54: 6453 str r3, [r2, #68] ; 0x44
+ 8001a56: 4b06 ldr r3, [pc, #24] ; (8001a70 <HAL_MspInit+0x44>)
+ 8001a58: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001a5a: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8001a5e: 603b str r3, [r7, #0]
+ 8001a60: 683b ldr r3, [r7, #0]
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+ 8001a62: bf00 nop
+ 8001a64: 370c adds r7, #12
+ 8001a66: 46bd mov sp, r7
+ 8001a68: f85d 7b04 ldr.w r7, [sp], #4
+ 8001a6c: 4770 bx lr
+ 8001a6e: bf00 nop
+ 8001a70: 40023800 .word 0x40023800
+
+08001a74 <HAL_TIM_Encoder_MspInit>:
+* This function configures the hardware resources used in this example
+* @param htim_encoder: TIM_Encoder handle pointer
+* @retval None
+*/
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
+{
+ 8001a74: b580 push {r7, lr}
+ 8001a76: b08c sub sp, #48 ; 0x30
+ 8001a78: af00 add r7, sp, #0
+ 8001a7a: 6078 str r0, [r7, #4]
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001a7c: f107 031c add.w r3, r7, #28
+ 8001a80: 2200 movs r2, #0
+ 8001a82: 601a str r2, [r3, #0]
+ 8001a84: 605a str r2, [r3, #4]
+ 8001a86: 609a str r2, [r3, #8]
+ 8001a88: 60da str r2, [r3, #12]
+ 8001a8a: 611a str r2, [r3, #16]
+ if(htim_encoder->Instance==TIM2)
+ 8001a8c: 687b ldr r3, [r7, #4]
+ 8001a8e: 681b ldr r3, [r3, #0]
+ 8001a90: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 8001a94: d144 bne.n 8001b20 <HAL_TIM_Encoder_MspInit+0xac>
+ {
+ /* USER CODE BEGIN TIM2_MspInit 0 */
+
+ /* USER CODE END TIM2_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM2_CLK_ENABLE();
+ 8001a96: 4b3b ldr r3, [pc, #236] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001a98: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001a9a: 4a3a ldr r2, [pc, #232] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001a9c: f043 0301 orr.w r3, r3, #1
+ 8001aa0: 6413 str r3, [r2, #64] ; 0x40
+ 8001aa2: 4b38 ldr r3, [pc, #224] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001aa4: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001aa6: f003 0301 and.w r3, r3, #1
+ 8001aaa: 61bb str r3, [r7, #24]
+ 8001aac: 69bb ldr r3, [r7, #24]
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8001aae: 4b35 ldr r3, [pc, #212] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001ab0: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001ab2: 4a34 ldr r2, [pc, #208] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001ab4: f043 0301 orr.w r3, r3, #1
+ 8001ab8: 6313 str r3, [r2, #48] ; 0x30
+ 8001aba: 4b32 ldr r3, [pc, #200] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001abc: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001abe: f003 0301 and.w r3, r3, #1
+ 8001ac2: 617b str r3, [r7, #20]
+ 8001ac4: 697b ldr r3, [r7, #20]
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8001ac6: 4b2f ldr r3, [pc, #188] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001ac8: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001aca: 4a2e ldr r2, [pc, #184] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001acc: f043 0302 orr.w r3, r3, #2
+ 8001ad0: 6313 str r3, [r2, #48] ; 0x30
+ 8001ad2: 4b2c ldr r3, [pc, #176] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001ad4: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001ad6: f003 0302 and.w r3, r3, #2
+ 8001ada: 613b str r3, [r7, #16]
+ 8001adc: 693b ldr r3, [r7, #16]
+ /**TIM2 GPIO Configuration
+ PA5 ------> TIM2_CH1
+ PB3 ------> TIM2_CH2
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_5;
+ 8001ade: 2320 movs r3, #32
+ 8001ae0: 61fb str r3, [r7, #28]
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001ae2: 2302 movs r3, #2
+ 8001ae4: 623b str r3, [r7, #32]
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 8001ae6: 2301 movs r3, #1
+ 8001ae8: 627b str r3, [r7, #36] ; 0x24
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001aea: 2300 movs r3, #0
+ 8001aec: 62bb str r3, [r7, #40] ; 0x28
+ GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+ 8001aee: 2301 movs r3, #1
+ 8001af0: 62fb str r3, [r7, #44] ; 0x2c
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8001af2: f107 031c add.w r3, r7, #28
+ 8001af6: 4619 mov r1, r3
+ 8001af8: 4823 ldr r0, [pc, #140] ; (8001b88 <HAL_TIM_Encoder_MspInit+0x114>)
+ 8001afa: f7fe fe61 bl 80007c0 <HAL_GPIO_Init>
+
+ GPIO_InitStruct.Pin = GPIO_PIN_3;
+ 8001afe: 2308 movs r3, #8
+ 8001b00: 61fb str r3, [r7, #28]
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001b02: 2302 movs r3, #2
+ 8001b04: 623b str r3, [r7, #32]
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 8001b06: 2301 movs r3, #1
+ 8001b08: 627b str r3, [r7, #36] ; 0x24
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001b0a: 2300 movs r3, #0
+ 8001b0c: 62bb str r3, [r7, #40] ; 0x28
+ GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+ 8001b0e: 2301 movs r3, #1
+ 8001b10: 62fb str r3, [r7, #44] ; 0x2c
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001b12: f107 031c add.w r3, r7, #28
+ 8001b16: 4619 mov r1, r3
+ 8001b18: 481c ldr r0, [pc, #112] ; (8001b8c <HAL_TIM_Encoder_MspInit+0x118>)
+ 8001b1a: f7fe fe51 bl 80007c0 <HAL_GPIO_Init>
+ /* USER CODE BEGIN TIM5_MspInit 1 */
+
+ /* USER CODE END TIM5_MspInit 1 */
+ }
+
+}
+ 8001b1e: e02c b.n 8001b7a <HAL_TIM_Encoder_MspInit+0x106>
+ else if(htim_encoder->Instance==TIM5)
+ 8001b20: 687b ldr r3, [r7, #4]
+ 8001b22: 681b ldr r3, [r3, #0]
+ 8001b24: 4a1a ldr r2, [pc, #104] ; (8001b90 <HAL_TIM_Encoder_MspInit+0x11c>)
+ 8001b26: 4293 cmp r3, r2
+ 8001b28: d127 bne.n 8001b7a <HAL_TIM_Encoder_MspInit+0x106>
+ __HAL_RCC_TIM5_CLK_ENABLE();
+ 8001b2a: 4b16 ldr r3, [pc, #88] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001b2c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001b2e: 4a15 ldr r2, [pc, #84] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001b30: f043 0308 orr.w r3, r3, #8
+ 8001b34: 6413 str r3, [r2, #64] ; 0x40
+ 8001b36: 4b13 ldr r3, [pc, #76] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001b38: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001b3a: f003 0308 and.w r3, r3, #8
+ 8001b3e: 60fb str r3, [r7, #12]
+ 8001b40: 68fb ldr r3, [r7, #12]
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8001b42: 4b10 ldr r3, [pc, #64] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001b44: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001b46: 4a0f ldr r2, [pc, #60] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001b48: f043 0301 orr.w r3, r3, #1
+ 8001b4c: 6313 str r3, [r2, #48] ; 0x30
+ 8001b4e: 4b0d ldr r3, [pc, #52] ; (8001b84 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001b50: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001b52: f003 0301 and.w r3, r3, #1
+ 8001b56: 60bb str r3, [r7, #8]
+ 8001b58: 68bb ldr r3, [r7, #8]
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+ 8001b5a: 2303 movs r3, #3
+ 8001b5c: 61fb str r3, [r7, #28]
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8001b5e: 2302 movs r3, #2
+ 8001b60: 623b str r3, [r7, #32]
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001b62: 2300 movs r3, #0
+ 8001b64: 627b str r3, [r7, #36] ; 0x24
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001b66: 2300 movs r3, #0
+ 8001b68: 62bb str r3, [r7, #40] ; 0x28
+ GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
+ 8001b6a: 2302 movs r3, #2
+ 8001b6c: 62fb str r3, [r7, #44] ; 0x2c
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8001b6e: f107 031c add.w r3, r7, #28
+ 8001b72: 4619 mov r1, r3
+ 8001b74: 4804 ldr r0, [pc, #16] ; (8001b88 <HAL_TIM_Encoder_MspInit+0x114>)
+ 8001b76: f7fe fe23 bl 80007c0 <HAL_GPIO_Init>
+}
+ 8001b7a: bf00 nop
+ 8001b7c: 3730 adds r7, #48 ; 0x30
+ 8001b7e: 46bd mov sp, r7
+ 8001b80: bd80 pop {r7, pc}
+ 8001b82: bf00 nop
+ 8001b84: 40023800 .word 0x40023800
+ 8001b88: 40020000 .word 0x40020000
+ 8001b8c: 40020400 .word 0x40020400
+ 8001b90: 40000c00 .word 0x40000c00
+
+08001b94 <NMI_Handler>:
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ 8001b94: b480 push {r7}
+ 8001b96: af00 add r7, sp, #0
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+ 8001b98: bf00 nop
+ 8001b9a: 46bd mov sp, r7
+ 8001b9c: f85d 7b04 ldr.w r7, [sp], #4
+ 8001ba0: 4770 bx lr
+
+08001ba2 <HardFault_Handler>:
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ 8001ba2: b480 push {r7}
+ 8001ba4: af00 add r7, sp, #0
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ 8001ba6: e7fe b.n 8001ba6 <HardFault_Handler+0x4>
+
+08001ba8 <MemManage_Handler>:
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ 8001ba8: b480 push {r7}
+ 8001baa: af00 add r7, sp, #0
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ 8001bac: e7fe b.n 8001bac <MemManage_Handler+0x4>
+
+08001bae <BusFault_Handler>:
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ 8001bae: b480 push {r7}
+ 8001bb0: af00 add r7, sp, #0
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ 8001bb2: e7fe b.n 8001bb2 <BusFault_Handler+0x4>
+
+08001bb4 <UsageFault_Handler>:
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ 8001bb4: b480 push {r7}
+ 8001bb6: af00 add r7, sp, #0
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ 8001bb8: e7fe b.n 8001bb8 <UsageFault_Handler+0x4>
+
+08001bba <SVC_Handler>:
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ 8001bba: b480 push {r7}
+ 8001bbc: af00 add r7, sp, #0
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+ 8001bbe: bf00 nop
+ 8001bc0: 46bd mov sp, r7
+ 8001bc2: f85d 7b04 ldr.w r7, [sp], #4
+ 8001bc6: 4770 bx lr
+
+08001bc8 <DebugMon_Handler>:
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ 8001bc8: b480 push {r7}
+ 8001bca: af00 add r7, sp, #0
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+ 8001bcc: bf00 nop
+ 8001bce: 46bd mov sp, r7
+ 8001bd0: f85d 7b04 ldr.w r7, [sp], #4
+ 8001bd4: 4770 bx lr
+
+08001bd6 <PendSV_Handler>:
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ 8001bd6: b480 push {r7}
+ 8001bd8: af00 add r7, sp, #0
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+ 8001bda: bf00 nop
+ 8001bdc: 46bd mov sp, r7
+ 8001bde: f85d 7b04 ldr.w r7, [sp], #4
+ 8001be2: 4770 bx lr
+
+08001be4 <SysTick_Handler>:
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ 8001be4: b580 push {r7, lr}
+ 8001be6: af00 add r7, sp, #0
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ 8001be8: f7fe fce4 bl 80005b4 <HAL_IncTick>
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+ 8001bec: bf00 nop
+ 8001bee: bd80 pop {r7, pc}
+
+08001bf0 <SystemInit>:
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ 8001bf0: b480 push {r7}
+ 8001bf2: af00 add r7, sp, #0
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ 8001bf4: 4b15 ldr r3, [pc, #84] ; (8001c4c <SystemInit+0x5c>)
+ 8001bf6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001bfa: 4a14 ldr r2, [pc, #80] ; (8001c4c <SystemInit+0x5c>)
+ 8001bfc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
+ 8001c00: f8c2 3088 str.w r3, [r2, #136] ; 0x88
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+ 8001c04: 4b12 ldr r3, [pc, #72] ; (8001c50 <SystemInit+0x60>)
+ 8001c06: 681b ldr r3, [r3, #0]
+ 8001c08: 4a11 ldr r2, [pc, #68] ; (8001c50 <SystemInit+0x60>)
+ 8001c0a: f043 0301 orr.w r3, r3, #1
+ 8001c0e: 6013 str r3, [r2, #0]
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+ 8001c10: 4b0f ldr r3, [pc, #60] ; (8001c50 <SystemInit+0x60>)
+ 8001c12: 2200 movs r2, #0
+ 8001c14: 609a str r2, [r3, #8]
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+ 8001c16: 4b0e ldr r3, [pc, #56] ; (8001c50 <SystemInit+0x60>)
+ 8001c18: 681a ldr r2, [r3, #0]
+ 8001c1a: 490d ldr r1, [pc, #52] ; (8001c50 <SystemInit+0x60>)
+ 8001c1c: 4b0d ldr r3, [pc, #52] ; (8001c54 <SystemInit+0x64>)
+ 8001c1e: 4013 ands r3, r2
+ 8001c20: 600b str r3, [r1, #0]
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+ 8001c22: 4b0b ldr r3, [pc, #44] ; (8001c50 <SystemInit+0x60>)
+ 8001c24: 4a0c ldr r2, [pc, #48] ; (8001c58 <SystemInit+0x68>)
+ 8001c26: 605a str r2, [r3, #4]
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+ 8001c28: 4b09 ldr r3, [pc, #36] ; (8001c50 <SystemInit+0x60>)
+ 8001c2a: 681b ldr r3, [r3, #0]
+ 8001c2c: 4a08 ldr r2, [pc, #32] ; (8001c50 <SystemInit+0x60>)
+ 8001c2e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8001c32: 6013 str r3, [r2, #0]
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+ 8001c34: 4b06 ldr r3, [pc, #24] ; (8001c50 <SystemInit+0x60>)
+ 8001c36: 2200 movs r2, #0
+ 8001c38: 60da str r2, [r3, #12]
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ 8001c3a: 4b04 ldr r3, [pc, #16] ; (8001c4c <SystemInit+0x5c>)
+ 8001c3c: f04f 6200 mov.w r2, #134217728 ; 0x8000000
+ 8001c40: 609a str r2, [r3, #8]
+#endif
+}
+ 8001c42: bf00 nop
+ 8001c44: 46bd mov sp, r7
+ 8001c46: f85d 7b04 ldr.w r7, [sp], #4
+ 8001c4a: 4770 bx lr
+ 8001c4c: e000ed00 .word 0xe000ed00
+ 8001c50: 40023800 .word 0x40023800
+ 8001c54: fef6ffff .word 0xfef6ffff
+ 8001c58: 24003010 .word 0x24003010
+
+08001c5c <Reset_Handler>:
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+ 8001c5c: f8df d034 ldr.w sp, [pc, #52] ; 8001c94 <LoopFillZerobss+0x14>
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ 8001c60: 2100 movs r1, #0
+ b LoopCopyDataInit
+ 8001c62: e003 b.n 8001c6c <LoopCopyDataInit>
+
+08001c64 <CopyDataInit>:
+
+CopyDataInit:
+ ldr r3, =_sidata
+ 8001c64: 4b0c ldr r3, [pc, #48] ; (8001c98 <LoopFillZerobss+0x18>)
+ ldr r3, [r3, r1]
+ 8001c66: 585b ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ 8001c68: 5043 str r3, [r0, r1]
+ adds r1, r1, #4
+ 8001c6a: 3104 adds r1, #4
+
+08001c6c <LoopCopyDataInit>:
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ 8001c6c: 480b ldr r0, [pc, #44] ; (8001c9c <LoopFillZerobss+0x1c>)
+ ldr r3, =_edata
+ 8001c6e: 4b0c ldr r3, [pc, #48] ; (8001ca0 <LoopFillZerobss+0x20>)
+ adds r2, r0, r1
+ 8001c70: 1842 adds r2, r0, r1
+ cmp r2, r3
+ 8001c72: 429a cmp r2, r3
+ bcc CopyDataInit
+ 8001c74: d3f6 bcc.n 8001c64 <CopyDataInit>
+ ldr r2, =_sbss
+ 8001c76: 4a0b ldr r2, [pc, #44] ; (8001ca4 <LoopFillZerobss+0x24>)
+ b LoopFillZerobss
+ 8001c78: e002 b.n 8001c80 <LoopFillZerobss>
+
+08001c7a <FillZerobss>:
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ 8001c7a: 2300 movs r3, #0
+ str r3, [r2], #4
+ 8001c7c: f842 3b04 str.w r3, [r2], #4
+
+08001c80 <LoopFillZerobss>:
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ 8001c80: 4b09 ldr r3, [pc, #36] ; (8001ca8 <LoopFillZerobss+0x28>)
+ cmp r2, r3
+ 8001c82: 429a cmp r2, r3
+ bcc FillZerobss
+ 8001c84: d3f9 bcc.n 8001c7a <FillZerobss>
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+ 8001c86: f7ff ffb3 bl 8001bf0 <SystemInit>
+/* Call static constructors */
+ bl __libc_init_array
+ 8001c8a: f000 f811 bl 8001cb0 <__libc_init_array>
+/* Call the application's entry point.*/
+ bl main
+ 8001c8e: f7ff fd39 bl 8001704 <main>
+ bx lr
+ 8001c92: 4770 bx lr
+ ldr sp, =_estack /* set stack pointer */
+ 8001c94: 20080000 .word 0x20080000
+ ldr r3, =_sidata
+ 8001c98: 08001d40 .word 0x08001d40
+ ldr r0, =_sdata
+ 8001c9c: 20000000 .word 0x20000000
+ ldr r3, =_edata
+ 8001ca0: 2000000c .word 0x2000000c
+ ldr r2, =_sbss
+ 8001ca4: 2000000c .word 0x2000000c
+ ldr r3, = _ebss
+ 8001ca8: 200000ac .word 0x200000ac
+
+08001cac <ADC_IRQHandler>:
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ 8001cac: e7fe b.n 8001cac <ADC_IRQHandler>
+ ...
+
+08001cb0 <__libc_init_array>:
+ 8001cb0: b570 push {r4, r5, r6, lr}
+ 8001cb2: 4e0d ldr r6, [pc, #52] ; (8001ce8 <__libc_init_array+0x38>)
+ 8001cb4: 4c0d ldr r4, [pc, #52] ; (8001cec <__libc_init_array+0x3c>)
+ 8001cb6: 1ba4 subs r4, r4, r6
+ 8001cb8: 10a4 asrs r4, r4, #2
+ 8001cba: 2500 movs r5, #0
+ 8001cbc: 42a5 cmp r5, r4
+ 8001cbe: d109 bne.n 8001cd4 <__libc_init_array+0x24>
+ 8001cc0: 4e0b ldr r6, [pc, #44] ; (8001cf0 <__libc_init_array+0x40>)
+ 8001cc2: 4c0c ldr r4, [pc, #48] ; (8001cf4 <__libc_init_array+0x44>)
+ 8001cc4: f000 f820 bl 8001d08 <_init>
+ 8001cc8: 1ba4 subs r4, r4, r6
+ 8001cca: 10a4 asrs r4, r4, #2
+ 8001ccc: 2500 movs r5, #0
+ 8001cce: 42a5 cmp r5, r4
+ 8001cd0: d105 bne.n 8001cde <__libc_init_array+0x2e>
+ 8001cd2: bd70 pop {r4, r5, r6, pc}
+ 8001cd4: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8001cd8: 4798 blx r3
+ 8001cda: 3501 adds r5, #1
+ 8001cdc: e7ee b.n 8001cbc <__libc_init_array+0xc>
+ 8001cde: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8001ce2: 4798 blx r3
+ 8001ce4: 3501 adds r5, #1
+ 8001ce6: e7f2 b.n 8001cce <__libc_init_array+0x1e>
+ 8001ce8: 08001d38 .word 0x08001d38
+ 8001cec: 08001d38 .word 0x08001d38
+ 8001cf0: 08001d38 .word 0x08001d38
+ 8001cf4: 08001d3c .word 0x08001d3c
+
+08001cf8 <memset>:
+ 8001cf8: 4402 add r2, r0
+ 8001cfa: 4603 mov r3, r0
+ 8001cfc: 4293 cmp r3, r2
+ 8001cfe: d100 bne.n 8001d02 <memset+0xa>
+ 8001d00: 4770 bx lr
+ 8001d02: f803 1b01 strb.w r1, [r3], #1
+ 8001d06: e7f9 b.n 8001cfc <memset+0x4>
+
+08001d08 <_init>:
+ 8001d08: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8001d0a: bf00 nop
+ 8001d0c: bcf8 pop {r3, r4, r5, r6, r7}
+ 8001d0e: bc08 pop {r3}
+ 8001d10: 469e mov lr, r3
+ 8001d12: 4770 bx lr
+
+08001d14 <_fini>:
+ 8001d14: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8001d16: bf00 nop
+ 8001d18: bcf8 pop {r3, r4, r5, r6, r7}
+ 8001d1a: bc08 pop {r3}
+ 8001d1c: 469e mov lr, r3
+ 8001d1e: 4770 bx lr
--- /dev/null
+Archive member included to satisfy reference by file (symbol)
+
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+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/crti.o
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/crtbegin.o
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/crt0.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o
+LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o
+LOAD Src/main.o
+LOAD Src/stm32f7xx_hal_msp.o
+LOAD Src/stm32f7xx_it.o
+LOAD Src/syscalls.o
+LOAD Src/sysmem.o
+LOAD Src/system_stm32f7xx.o
+LOAD Startup/startup_stm32f767zitx.o
+START GROUP
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libm.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/libgcc.a
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libc_nano.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/libgcc.a
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libnosys.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/libgcc.a
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libnosys.a
+END GROUP
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/crtend.o
+LOAD /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/crtn.o
+ 0x0000000020080000 _estack = 0x20080000
+ 0x0000000000000200 _Min_Heap_Size = 0x200
+ 0x0000000000000400 _Min_Stack_Size = 0x400
+
+.isr_vector 0x0000000008000000 0x1f8
+ 0x0000000008000000 . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector 0x0000000008000000 0x1f8 Startup/startup_stm32f767zitx.o
+ 0x0000000008000000 g_pfnVectors
+ 0x00000000080001f8 . = ALIGN (0x4)
+
+.text 0x00000000080001f8 0x1b28
+ 0x00000000080001f8 . = ALIGN (0x4)
+ *(.text)
+ .text 0x00000000080001f8 0x40 /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/crtbegin.o
+ .text 0x0000000008000238 0x30 /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/libgcc.a(_aeabi_uldivmod.o)
+ 0x0000000008000238 __aeabi_uldivmod
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+ 0x0000000008000268 __udivmoddi4
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+ 0x0000000008000534 __aeabi_ldiv0
+ 0x0000000008000534 __aeabi_idiv0
+ *(.text*)
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+ 0x0000000008000538 HAL_Init
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+ 0x00000000080005dc HAL_GetTick
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+ .text.__NVIC_GetPriorityGrouping
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+ .text.__NVIC_SetPriority
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+ .text.NVIC_EncodePriority
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+ *fill* 0x0000000008000712 0x2
+ .text.SysTick_Config
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+ 0x0000000008000758 HAL_NVIC_SetPriorityGrouping
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+ 0x000000000800076e HAL_NVIC_SetPriority
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+ 0x00000000080007a6 HAL_SYSTICK_Config
+ *fill* 0x00000000080007be 0x2
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+ 0x00000000080007c0 HAL_GPIO_Init
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+ 0x0000000008000b14 HAL_RCC_OscConfig
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+ 0x0000000008000ff8 HAL_RCC_ClockConfig
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+ 0x00000000080011c8 0x164 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o
+ 0x00000000080011c8 HAL_RCC_GetSysClockFreq
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+ 0x000000000800132c HAL_TIM_Encoder_Init
+ .text.HAL_TIM_Encoder_Start
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+ 0x0000000008001450 HAL_TIM_Encoder_Start
+ *fill* 0x00000000080014be 0x2
+ .text.TIM_Base_SetConfig
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+ 0x00000000080014c0 TIM_Base_SetConfig
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+ 0x0000000008001600 TIM_CCxChannelCmd
+ *fill* 0x000000000800164a 0x2
+ .text.HAL_TIMEx_MasterConfigSynchronization
+ 0x000000000800164c 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o
+ 0x000000000800164c HAL_TIMEx_MasterConfigSynchronization
+ .text.main 0x0000000008001704 0xc0 Src/main.o
+ 0x0000000008001704 main
+ .text.SystemClock_Config
+ 0x00000000080017c4 0xb8 Src/main.o
+ 0x00000000080017c4 SystemClock_Config
+ .text.MX_TIM2_Init
+ 0x000000000800187c 0xac Src/main.o
+ .text.MX_TIM5_Init
+ 0x0000000008001928 0xac Src/main.o
+ .text.MX_GPIO_Init
+ 0x00000000080019d4 0x48 Src/main.o
+ .text.Error_Handler
+ 0x0000000008001a1c 0xe Src/main.o
+ 0x0000000008001a1c Error_Handler
+ *fill* 0x0000000008001a2a 0x2
+ .text.HAL_MspInit
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+ 0x0000000008001a2c HAL_MspInit
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+ 0x0000000008001a74 HAL_TIM_Encoder_MspInit
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+ 0x0000000008001be4 SysTick_Handler
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+
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+ *(SORT_BY_NAME(.init_array.*))
+ *(.init_array*)
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+ 0x0000000008001d3c PROVIDE (__init_array_end = .)
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+ 0x0000000008001d3c . = ALIGN (0x4)
+ [!provide] PROVIDE (__fini_array_start = .)
+ *(SORT_BY_NAME(.fini_array.*))
+ *(.fini_array*)
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+ .debug_frame 0x000000000000088c 0x14c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o
+ .debug_frame 0x00000000000009d8 0x1f4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o
+ .debug_frame 0x0000000000000bcc 0x1144 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o
+ .debug_frame 0x0000000000001d10 0x638 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o
+ .debug_frame 0x0000000000002348 0xe4 Src/main.o
+ .debug_frame 0x000000000000242c 0x80 Src/stm32f7xx_hal_msp.o
+ .debug_frame 0x00000000000024ac 0x10c Src/stm32f7xx_it.o
+ .debug_frame 0x00000000000025b8 0x58 Src/system_stm32f7xx.o
+ .debug_frame 0x0000000000002610 0x2c /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libc_nano.a(lib_a-init.o)
+ .debug_frame 0x000000000000263c 0x20 /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/libc_nano.a(lib_a-memset.o)
+ .debug_frame 0x000000000000265c 0x2c /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/libgcc.a(_aeabi_uldivmod.o)
+ .debug_frame 0x0000000000002688 0x34 /opt/st/stm32cubeide_1.0.2/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.0.0.201904181610/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv5/hard/libgcc.a(_udivmoddi4.o)
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Startup/subdir.mk
+-include Src/subdir.mk
+-include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+EXECUTABLES += \
+encoder.elf \
+
+SIZE_OUTPUT += \
+default.size.stdout \
+
+OBJDUMP_LIST += \
+encoder.list \
+
+
+# All Target
+all: encoder.elf secondary-outputs
+
+# Tool invocations
+encoder.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/stm32-tests/encoder/STM32F767ZITX_FLASH.ld
+ arm-none-eabi-gcc -o "encoder.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/stm32-tests/encoder/STM32F767ZITX_FLASH.ld" --specs=nosys.specs -Wl,-Map="encoder.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+default.size.stdout: $(EXECUTABLES)
+ arm-none-eabi-size $(EXECUTABLES)
+ @echo 'Finished building: $@'
+ @echo ' '
+
+encoder.list: $(EXECUTABLES)
+ arm-none-eabi-objdump -h -S $(EXECUTABLES) > "encoder.list"
+ @echo 'Finished building: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) *
+ -@echo ' '
+
+secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
--- /dev/null
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o"
+"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o"
+"Src/main.o"
+"Src/stm32f7xx_hal_msp.o"
+"Src/stm32f7xx_it.o"
+"Src/syscalls.o"
+"Src/sysmem.o"
+"Src/system_stm32f7xx.o"
+"Startup/startup_stm32f767zitx.o"
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS :=
+OBJ_SRCS :=
+S_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+O_SRCS :=
+SIZE_OUTPUT :=
+OBJDUMP_LIST :=
+EXECUTABLES :=
+OBJS :=
+C_DEPS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Drivers/STM32F7xx_HAL_Driver/Src \
+Src \
+Startup \
+
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f767xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.\r
+ *\r
+ * This file contains:\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral\92s registers hardware\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS_Device\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f767xx\r
+ * @{\r
+ */\r
+\r
+#ifndef __STM32F767xx_H\r
+#define __STM32F767xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device\r
+ * in @ref Library_configuration_section\r
+ */\r
+typedef enum\r
+{\r
+/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */\r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+ FMC_IRQn = 48, /*!< FMC global Interrupt */\r
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */\r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
+ RNG_IRQn = 80, /*!< RNG global interrupt */\r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */\r
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */\r
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */\r
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */\r
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */\r
+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */\r
+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */\r
+ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */\r
+ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */\r
+ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */\r
+ SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */\r
+ DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */\r
+ DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */\r
+ DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */\r
+ DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */\r
+ SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */\r
+ CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */\r
+ CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */\r
+ CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */\r
+ CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */\r
+ JPEG_IRQn = 108, /*!< JPEG global Interrupt */\r
+ MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals\r
+ */\r
+#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */\r
+#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */\r
+#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */\r
+#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */\r
+\r
+\r
+#include "system_stm32f7xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Analog to Digital Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
+ AND triple modes, Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Controller Area Network TxMailBox\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/**\r
+ * @brief Controller Area Network FIFOMailBox\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/**\r
+ * @brief Controller Area Network FilterRegister\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/**\r
+ * @brief Controller Area Network\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */\r
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
+} CAN_TypeDef;\r
+\r
+/**\r
+ * @brief HDMI-CEC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */\r
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */\r
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */\r
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */\r
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */\r
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */\r
+}CEC_TypeDef;\r
+\r
+/**\r
+ * @brief CRC calculation unit\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */\r
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\r
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\r
+} CRC_TypeDef;\r
+\r
+/**\r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/**\r
+ * @brief DFSDM module registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */\r
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */\r
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */\r
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */\r
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */\r
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */\r
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */\r
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */\r
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */\r
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */\r
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */\r
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */\r
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */\r
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */\r
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */\r
+} DFSDM_Filter_TypeDef;\r
+\r
+/**\r
+ * @brief DFSDM channel configuration registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */\r
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */\r
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and\r
+ short circuit detector register, Address offset: 0x08 */\r
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */\r
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */\r
+} DFSDM_Channel_TypeDef;\r
+\r
+/**\r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/**\r
+ * @brief DCMI\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/**\r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+/**\r
+ * @brief DMA2D Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */\r
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */\r
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */\r
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */\r
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */\r
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */\r
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */\r
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */\r
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */\r
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */\r
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */\r
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */\r
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */\r
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */\r
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */\r
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */\r
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */\r
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */\r
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */\r
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */\r
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */\r
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */\r
+} DMA2D_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Ethernet MAC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACFFR;\r
+ __IO uint32_t MACHTHR;\r
+ __IO uint32_t MACHTLR;\r
+ __IO uint32_t MACMIIAR;\r
+ __IO uint32_t MACMIIDR;\r
+ __IO uint32_t MACFCR;\r
+ __IO uint32_t MACVLANTR; /* 8 */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t MACRWUFFR; /* 11 */\r
+ __IO uint32_t MACPMTCSR;\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t MACDBGR;\r
+ __IO uint32_t MACSR; /* 15 */\r
+ __IO uint32_t MACIMR;\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR; /* 24 */\r
+ uint32_t RESERVED2[40];\r
+ __IO uint32_t MMCCR; /* 65 */\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR; /* 69 */\r
+ uint32_t RESERVED3[14];\r
+ __IO uint32_t MMCTGFSCCR; /* 84 */\r
+ __IO uint32_t MMCTGFMSCCR;\r
+ uint32_t RESERVED4[5];\r
+ __IO uint32_t MMCTGFCR;\r
+ uint32_t RESERVED5[10];\r
+ __IO uint32_t MMCRFCECR;\r
+ __IO uint32_t MMCRFAECR;\r
+ uint32_t RESERVED6[10];\r
+ __IO uint32_t MMCRGUFCR;\r
+ uint32_t RESERVED7[334];\r
+ __IO uint32_t PTPTSCR;\r
+ __IO uint32_t PTPSSIR;\r
+ __IO uint32_t PTPTSHR;\r
+ __IO uint32_t PTPTSLR;\r
+ __IO uint32_t PTPTSHUR;\r
+ __IO uint32_t PTPTSLUR;\r
+ __IO uint32_t PTPTSAR;\r
+ __IO uint32_t PTPTTHR;\r
+ __IO uint32_t PTPTTLR;\r
+ __IO uint32_t RESERVED8;\r
+ __IO uint32_t PTPTSSR;\r
+ uint32_t RESERVED9[565];\r
+ __IO uint32_t DMABMR;\r
+ __IO uint32_t DMATPDR;\r
+ __IO uint32_t DMARPDR;\r
+ __IO uint32_t DMARDLAR;\r
+ __IO uint32_t DMATDLAR;\r
+ __IO uint32_t DMASR;\r
+ __IO uint32_t DMAOMR;\r
+ __IO uint32_t DMAIER;\r
+ __IO uint32_t DMAMFBOCR;\r
+ __IO uint32_t DMARSWTR;\r
+ uint32_t RESERVED10[8];\r
+ __IO uint32_t DMACHTDR;\r
+ __IO uint32_t DMACHRDR;\r
+ __IO uint32_t DMACHTBAR;\r
+ __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/**\r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/**\r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */\r
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */\r
+} FLASH_TypeDef;\r
+\r
+\r
+\r
+/**\r
+ * @brief Flexible Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r
+} FMC_Bank1_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank1E\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank3\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */\r
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */\r
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */\r
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank5_6\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
+} FMC_Bank5_6_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/**\r
+ * @brief System configuration controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ uint32_t RESERVED; /*!< Reserved, 0x18 */\r
+ __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */\r
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
+} SYSCFG_TypeDef;\r
+\r
+/**\r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\r
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\r
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\r
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\r
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\r
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\r
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */\r
+} I2C_TypeDef;\r
+\r
+/**\r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief LCD-TFT Display Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */\r
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */\r
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */\r
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */\r
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */\r
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */\r
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */\r
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */\r
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */\r
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */\r
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */\r
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */\r
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */\r
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */\r
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */\r
+} LTDC_TypeDef;\r
+\r
+/**\r
+ * @brief LCD-TFT Display layer x Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */\r
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */\r
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */\r
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */\r
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */\r
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */\r
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */\r
+ uint32_t RESERVED0[2]; /*!< Reserved */\r
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */\r
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */\r
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */\r
+ uint32_t RESERVED1[3]; /*!< Reserved */\r
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */\r
+\r
+} LTDC_Layer_TypeDef;\r
+\r
+/**\r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */\r
+ __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */\r
+} PWR_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */\r
+ __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */\r
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */\r
+\r
+} RCC_TypeDef;\r
+\r
+/**\r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ uint32_t reserved; /*!< Reserved */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Serial Audio Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+\r
+/**\r
+ * @brief SPDIF-RX Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */\r
+ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */\r
+ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */\r
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */\r
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */\r
+} SPDIFRX_TypeDef;\r
+\r
+/**\r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */\r
+} SDMMC_TypeDef;\r
+\r
+/**\r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+} SPI_TypeDef;\r
+\r
+/**\r
+ * @brief QUAD Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */\r
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */\r
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */\r
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */\r
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */\r
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */\r
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */\r
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */\r
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */\r
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */\r
+} QUADSPI_TypeDef;\r
+\r
+/**\r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */\r
+ __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */\r
+ __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */\r
+ __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */\r
+ __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */\r
+\r
+} TIM_TypeDef;\r
+\r
+/**\r
+ * @brief LPTIMIMER\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\r
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\r
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\r
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\r
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\r
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\r
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\r
+} LPTIM_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\r
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */\r
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */\r
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\r
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\r
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\r
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\r
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\r
+} USART_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief RNG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief USB_OTG_Core_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */\r
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */\r
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */\r
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */\r
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */\r
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */\r
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */\r
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */\r
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */\r
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */\r
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */\r
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */\r
+ uint32_t Reserved30[2]; /*!< Reserved 030h */\r
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */\r
+ __IO uint32_t CID; /*!< User ID Register 03Ch */\r
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */\r
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */\r
+ uint32_t Reserved6; /*!< Reserved 050h */\r
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */\r
+ uint32_t Reserved7; /*!< Reserved 058h */\r
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */\r
+ uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */\r
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */\r
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */\r
+} USB_OTG_GlobalTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_device_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */\r
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */\r
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */\r
+ uint32_t Reserved0C; /*!< Reserved 80Ch */\r
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */\r
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */\r
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */\r
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */\r
+ uint32_t Reserved20; /*!< Reserved 820h */\r
+ uint32_t Reserved9; /*!< Reserved 824h */\r
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */\r
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */\r
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */\r
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */\r
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */\r
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */\r
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */\r
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */\r
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */\r
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */\r
+} USB_OTG_DeviceTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_IN_Endpoint-Specific_Register\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */\r
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r
+} USB_OTG_INEndpointTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */\r
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r
+} USB_OTG_OUTEndpointTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_Host_Mode_Register_Structures\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */\r
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */\r
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */\r
+ uint32_t Reserved40C; /*!< Reserved 40Ch */\r
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */\r
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */\r
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */\r
+} USB_OTG_HostTypeDef;\r
+\r
+/**\r
+ * @brief USB_OTG_Host_Channel_Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */\r
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */\r
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */\r
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */\r
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */\r
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */\r
+ uint32_t Reserved[2]; /*!< Reserved */\r
+} USB_OTG_HostChannelTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief JPEG Codec\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */\r
+ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */\r
+ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */\r
+ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */\r
+ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */\r
+ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */\r
+ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */\r
+ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */\r
+ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */\r
+ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */\r
+ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */\r
+ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */\r
+ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */\r
+ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */\r
+ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */\r
+ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */\r
+ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */\r
+ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */\r
+ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */\r
+ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */\r
+ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */\r
+ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */\r
+ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */\r
+ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */\r
+ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */\r
+ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */\r
+ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */\r
+ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */\r
+ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */\r
+\r
+} JPEG_TypeDef;\r
+\r
+/**\r
+ * @brief MDIOS\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */\r
+ __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */\r
+ __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */\r
+ __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */\r
+ __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */\r
+ __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */\r
+ __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */\r
+ uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */\r
+ __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */\r
+ __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */\r
+ __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */\r
+ __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */\r
+ __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */\r
+ __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */\r
+ __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */\r
+ __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */\r
+ __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */\r
+ __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */\r
+ __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */\r
+ __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */\r
+ __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */\r
+ __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */\r
+ __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */\r
+ __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */\r
+ __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */\r
+ __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */\r
+ __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */\r
+ __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */\r
+ __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */\r
+ __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */\r
+ __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */\r
+ __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */\r
+ __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */\r
+ __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */\r
+ __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */\r
+ __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */\r
+ __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */\r
+ __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */\r
+ __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */\r
+ __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */\r
+ __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */\r
+ __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */\r
+ __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */\r
+ __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */\r
+ __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */\r
+ __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */\r
+ __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */\r
+ __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */\r
+ __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */\r
+ __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */\r
+ __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */\r
+ __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */\r
+ __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */\r
+ __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */\r
+ __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */\r
+ __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */\r
+ __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */\r
+ __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */\r
+ __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */\r
+ __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */\r
+ __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */\r
+ __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */\r
+ __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */\r
+ __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */\r
+ __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */\r
+ __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */\r
+ __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */\r
+ __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */\r
+ __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */\r
+ __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */\r
+ __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */\r
+ __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */\r
+} MDIOS_TypeDef;\r
+\r
+\r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */\r
+#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */\r
+#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */\r
+#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 128KB system data RAM accessible over DTCM */\r
+#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */\r
+#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */\r
+#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */\r
+#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */\r
+#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */\r
+#define SRAM1_BASE 0x20020000UL /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */\r
+#define SRAM2_BASE 0x2007C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */\r
+#define FLASH_END 0x081FFFFFUL /*!< FLASH end address */\r
+#define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */\r
+#define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */\r
+\r
+/* Legacy define */\r
+#define FLASH_BASE FLASHAXI_BASE\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)\r
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)\r
+#define CAN3_BASE (APB1PERIPH_BASE + 0x3400UL)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)\r
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)\r
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)\r
+#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)\r
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)\r
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)\r
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)\r
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)\r
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)\r
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)\r
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)\r
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)\r
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)\r
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)\r
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)\r
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)\r
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)\r
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)\r
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)\r
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)\r
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)\r
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL)\r
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL)\r
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400UL)\r
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)\r
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)\r
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)\r
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)\r
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)\r
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)\r
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)\r
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)\r
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)\r
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)\r
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)\r
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)\r
+#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800UL)\r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)\r
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)\r
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)\r
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)\r
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)\r
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)\r
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)\r
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)\r
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)\r
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)\r
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)\r
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)\r
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)\r
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)\r
+#define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */\r
+#define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */\r
+#define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */\r
+/* Legacy define */\r
+#define PACKAGESIZE_BASE PACKAGE_BASE\r
+\r
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)\r
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)\r
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)\r
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)\r
+/*!< AHB2 peripherals */\r
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)\r
+#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000UL)\r
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)\r
+/*!< FMC Bankx registers base address */\r
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)\r
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)\r
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)\r
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE 0xE0042000UL\r
+\r
+/*!< USB registers base address */\r
+#define USB_OTG_HS_PERIPH_BASE 0x40040000UL\r
+#define USB_OTG_FS_PERIPH_BASE 0x50000000UL\r
+\r
+#define USB_OTG_GLOBAL_BASE 0x0000UL\r
+#define USB_OTG_DEVICE_BASE 0x0800UL\r
+#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL\r
+#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL\r
+#define USB_OTG_EP_REG_SIZE 0x0020UL\r
+#define USB_OTG_HOST_BASE 0x0400UL\r
+#define USB_OTG_HOST_PORT_BASE 0x0440UL\r
+#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL\r
+#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL\r
+#define USB_OTG_PCGCCTL_BASE 0x0E00UL\r
+#define USB_OTG_FIFO_BASE 0x1000UL\r
+#define USB_OTG_FIFO_SIZE 0x1000UL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\r
+#define UART7 ((USART_TypeDef *) UART7_BASE)\r
+#define UART8 ((USART_TypeDef *) UART8_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)\r
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)\r
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)\r
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)\r
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define ETH ((ETH_TypeDef *) ETH_BASE)\r
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)\r
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\r
+#define CAN3 ((CAN_TypeDef *) CAN3_BASE)\r
+#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)\r
+#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)\r
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\r
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\r
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\r
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\r
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\r
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\r
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\r
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\r
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\r
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\r
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\r
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\r
+#define JPEG ((JPEG_TypeDef *) JPEG_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+\r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD_Pos (0U) \r
+#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */\r
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC_Pos (1U) \r
+#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */\r
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */\r
+#define ADC_SR_JEOC_Pos (2U) \r
+#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */\r
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT_Pos (3U) \r
+#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */\r
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT_Pos (4U) \r
+#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */\r
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */\r
+#define ADC_SR_OVR_Pos (5U) \r
+#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */\r
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH_Pos (0U) \r
+#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */\r
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */\r
+#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */\r
+#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */\r
+#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */\r
+#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */\r
+#define ADC_CR1_EOCIE_Pos (5U) \r
+#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */\r
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE_Pos (6U) \r
+#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */\r
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE_Pos (7U) \r
+#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */\r
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN_Pos (8U) \r
+#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */\r
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL_Pos (9U) \r
+#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */\r
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO_Pos (10U) \r
+#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */\r
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN_Pos (11U) \r
+#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */\r
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN_Pos (12U) \r
+#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */\r
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */\r
+#define ADC_CR1_DISCNUM_Pos (13U) \r
+#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */\r
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */\r
+#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */\r
+#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */\r
+#define ADC_CR1_JAWDEN_Pos (22U) \r
+#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */\r
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN_Pos (23U) \r
+#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */\r
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */\r
+#define ADC_CR1_RES_Pos (24U) \r
+#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */\r
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */\r
+#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */\r
+#define ADC_CR1_OVRIE_Pos (26U) \r
+#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */\r
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */\r
+\r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON_Pos (0U) \r
+#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */\r
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT_Pos (1U) \r
+#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */\r
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */\r
+#define ADC_CR2_DMA_Pos (8U) \r
+#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */\r
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */\r
+#define ADC_CR2_DDS_Pos (9U) \r
+#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */\r
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS_Pos (10U) \r
+#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */\r
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */\r
+#define ADC_CR2_ALIGN_Pos (11U) \r
+#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */\r
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */\r
+#define ADC_CR2_JEXTSEL_Pos (16U) \r
+#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */\r
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */\r
+#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */\r
+#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */\r
+#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */\r
+#define ADC_CR2_JEXTEN_Pos (20U) \r
+#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */\r
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */\r
+#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */\r
+#define ADC_CR2_JSWSTART_Pos (22U) \r
+#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */\r
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_EXTSEL_Pos (24U) \r
+#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */\r
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */\r
+#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */\r
+#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */\r
+#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */\r
+#define ADC_CR2_EXTEN_Pos (28U) \r
+#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */\r
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */\r
+#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */\r
+#define ADC_CR2_SWSTART_Pos (30U) \r
+#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */\r
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10_Pos (0U) \r
+#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */\r
+#define ADC_SMPR1_SMP11_Pos (3U) \r
+#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */\r
+#define ADC_SMPR1_SMP12_Pos (6U) \r
+#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */\r
+#define ADC_SMPR1_SMP13_Pos (9U) \r
+#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */\r
+#define ADC_SMPR1_SMP14_Pos (12U) \r
+#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */\r
+#define ADC_SMPR1_SMP15_Pos (15U) \r
+#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */\r
+#define ADC_SMPR1_SMP16_Pos (18U) \r
+#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */\r
+#define ADC_SMPR1_SMP17_Pos (21U) \r
+#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */\r
+#define ADC_SMPR1_SMP18_Pos (24U) \r
+#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0_Pos (0U) \r
+#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */\r
+#define ADC_SMPR2_SMP1_Pos (3U) \r
+#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */\r
+#define ADC_SMPR2_SMP2_Pos (6U) \r
+#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */\r
+#define ADC_SMPR2_SMP3_Pos (9U) \r
+#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */\r
+#define ADC_SMPR2_SMP4_Pos (12U) \r
+#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */\r
+#define ADC_SMPR2_SMP5_Pos (15U) \r
+#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */\r
+#define ADC_SMPR2_SMP6_Pos (18U) \r
+#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */\r
+#define ADC_SMPR2_SMP7_Pos (21U) \r
+#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */\r
+#define ADC_SMPR2_SMP8_Pos (24U) \r
+#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */\r
+#define ADC_SMPR2_SMP9_Pos (27U) \r
+#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */\r
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */\r
+#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */\r
+#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1_Pos (0U) \r
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2_Pos (0U) \r
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3_Pos (0U) \r
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4_Pos (0U) \r
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT_Pos (0U) \r
+#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */\r
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT_Pos (0U) \r
+#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */\r
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13_Pos (0U) \r
+#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */\r
+#define ADC_SQR1_SQ14_Pos (5U) \r
+#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR1_SQ15_Pos (10U) \r
+#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR1_SQ16_Pos (15U) \r
+#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR1_L_Pos (20U) \r
+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */\r
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7_Pos (0U) \r
+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */\r
+#define ADC_SQR2_SQ8_Pos (5U) \r
+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR2_SQ9_Pos (10U) \r
+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR2_SQ10_Pos (15U) \r
+#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR2_SQ11_Pos (20U) \r
+#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */\r
+#define ADC_SQR2_SQ12_Pos (25U) \r
+#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1_Pos (0U) \r
+#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */\r
+#define ADC_SQR3_SQ2_Pos (5U) \r
+#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR3_SQ3_Pos (10U) \r
+#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR3_SQ4_Pos (15U) \r
+#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR3_SQ5_Pos (20U) \r
+#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */\r
+#define ADC_SQR3_SQ6_Pos (25U) \r
+#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1_Pos (0U) \r
+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */\r
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */\r
+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */\r
+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */\r
+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */\r
+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */\r
+#define ADC_JSQR_JSQ2_Pos (5U) \r
+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */\r
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */\r
+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */\r
+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */\r
+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */\r
+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */\r
+#define ADC_JSQR_JSQ3_Pos (10U) \r
+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */\r
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */\r
+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */\r
+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */\r
+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */\r
+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */\r
+#define ADC_JSQR_JSQ4_Pos (15U) \r
+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */\r
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */\r
+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */\r
+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */\r
+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */\r
+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */\r
+#define ADC_JSQR_JL_Pos (20U) \r
+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */\r
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */\r
+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA_Pos (0U) \r
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */\r
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */\r
+#define ADC_DR_ADC2DATA_Pos (16U) \r
+#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */\r
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1_Pos (0U) \r
+#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */\r
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1_Pos (1U) \r
+#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */\r
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1_Pos (2U) \r
+#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */\r
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1_Pos (3U) \r
+#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */\r
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1_Pos (4U) \r
+#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */\r
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */\r
+#define ADC_CSR_OVR1_Pos (5U) \r
+#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */\r
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */\r
+#define ADC_CSR_AWD2_Pos (8U) \r
+#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */\r
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */\r
+#define ADC_CSR_EOC2_Pos (9U) \r
+#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */\r
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */\r
+#define ADC_CSR_JEOC2_Pos (10U) \r
+#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */\r
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT2_Pos (11U) \r
+#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */\r
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */\r
+#define ADC_CSR_STRT2_Pos (12U) \r
+#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */\r
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */\r
+#define ADC_CSR_OVR2_Pos (13U) \r
+#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */\r
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */\r
+#define ADC_CSR_AWD3_Pos (16U) \r
+#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */\r
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */\r
+#define ADC_CSR_EOC3_Pos (17U) \r
+#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */\r
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */\r
+#define ADC_CSR_JEOC3_Pos (18U) \r
+#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */\r
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT3_Pos (19U) \r
+#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */\r
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */\r
+#define ADC_CSR_STRT3_Pos (20U) \r
+#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */\r
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */\r
+#define ADC_CSR_OVR3_Pos (21U) \r
+#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */\r
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */\r
+\r
+/* Legacy defines */\r
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1\r
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2\r
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3\r
+\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_MULTI_Pos (0U) \r
+#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */\r
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\r
+#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */\r
+#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */\r
+#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */\r
+#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */\r
+#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */\r
+#define ADC_CCR_DELAY_Pos (8U) \r
+#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */\r
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\r
+#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */\r
+#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */\r
+#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */\r
+#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */\r
+#define ADC_CCR_DDS_Pos (13U) \r
+#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */\r
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */\r
+#define ADC_CCR_DMA_Pos (14U) \r
+#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */\r
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\r
+#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */\r
+#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */\r
+#define ADC_CCR_ADCPRE_Pos (16U) \r
+#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */\r
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */\r
+#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */\r
+#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */\r
+#define ADC_CCR_VBATE_Pos (22U) \r
+#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */\r
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */\r
+#define ADC_CCR_TSVREFE_Pos (23U) \r
+#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */\r
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************* Bit definition for ADC_CDR register ********************/\r
+#define ADC_CDR_DATA1_Pos (0U) \r
+#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */\r
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */\r
+#define ADC_CDR_DATA2_Pos (16U) \r
+#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */\r
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */\r
+\r
+/* Legacy defines */\r
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1\r
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ_Pos (0U) \r
+#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP_Pos (1U) \r
+#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */\r
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP_Pos (2U) \r
+#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */\r
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM_Pos (3U) \r
+#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */\r
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART_Pos (4U) \r
+#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */\r
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM_Pos (5U) \r
+#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */\r
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM_Pos (6U) \r
+#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */\r
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM_Pos (7U) \r
+#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */\r
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET_Pos (15U) \r
+#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */\r
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */\r
+\r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK_Pos (0U) \r
+#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */\r
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK_Pos (1U) \r
+#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */\r
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI_Pos (2U) \r
+#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */\r
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI_Pos (3U) \r
+#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */\r
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI_Pos (4U) \r
+#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */\r
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM_Pos (8U) \r
+#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */\r
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */\r
+#define CAN_MSR_RXM_Pos (9U) \r
+#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */\r
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */\r
+#define CAN_MSR_SAMP_Pos (10U) \r
+#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */\r
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */\r
+#define CAN_MSR_RX_Pos (11U) \r
+#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */\r
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0_Pos (0U) \r
+#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */\r
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0_Pos (1U) \r
+#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */\r
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0_Pos (2U) \r
+#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */\r
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0_Pos (3U) \r
+#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */\r
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0_Pos (7U) \r
+#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */\r
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1_Pos (8U) \r
+#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */\r
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1_Pos (9U) \r
+#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */\r
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1_Pos (10U) \r
+#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */\r
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1_Pos (11U) \r
+#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */\r
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1_Pos (15U) \r
+#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */\r
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2_Pos (16U) \r
+#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */\r
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2_Pos (17U) \r
+#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */\r
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2_Pos (18U) \r
+#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */\r
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2_Pos (19U) \r
+#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */\r
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2_Pos (23U) \r
+#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */\r
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE_Pos (24U) \r
+#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */\r
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME_Pos (26U) \r
+#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */\r
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0_Pos (26U) \r
+#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */\r
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1_Pos (27U) \r
+#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */\r
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2_Pos (28U) \r
+#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */\r
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW_Pos (29U) \r
+#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */\r
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0_Pos (29U) \r
+#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */\r
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1_Pos (30U) \r
+#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */\r
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2_Pos (31U) \r
+#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */\r
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0_Pos (0U) \r
+#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */\r
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0_Pos (3U) \r
+#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */\r
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0_Pos (4U) \r
+#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */\r
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0_Pos (5U) \r
+#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */\r
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1_Pos (0U) \r
+#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */\r
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1_Pos (3U) \r
+#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */\r
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1_Pos (4U) \r
+#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */\r
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1_Pos (5U) \r
+#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */\r
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE_Pos (0U) \r
+#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */\r
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0_Pos (1U) \r
+#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */\r
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0_Pos (2U) \r
+#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */\r
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0_Pos (3U) \r
+#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */\r
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1_Pos (4U) \r
+#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */\r
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1_Pos (5U) \r
+#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */\r
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1_Pos (6U) \r
+#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */\r
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE_Pos (8U) \r
+#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */\r
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE_Pos (9U) \r
+#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */\r
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE_Pos (10U) \r
+#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */\r
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE_Pos (11U) \r
+#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */\r
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE_Pos (15U) \r
+#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */\r
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE_Pos (16U) \r
+#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */\r
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE_Pos (17U) \r
+#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */\r
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF_Pos (0U) \r
+#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */\r
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF_Pos (1U) \r
+#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */\r
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF_Pos (2U) \r
+#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */\r
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC_Pos (4U) \r
+#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */\r
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */\r
+#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */\r
+#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */\r
+\r
+#define CAN_ESR_TEC_Pos (16U) \r
+#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */\r
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC_Pos (24U) \r
+#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */\r
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP_Pos (0U) \r
+#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */\r
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1_Pos (16U) \r
+#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */\r
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */\r
+#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */\r
+#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */\r
+#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */\r
+#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */\r
+#define CAN_BTR_TS2_Pos (20U) \r
+#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */\r
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */\r
+#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */\r
+#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */\r
+#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */\r
+#define CAN_BTR_SJW_Pos (24U) \r
+#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */\r
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */\r
+#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */\r
+#define CAN_BTR_LBKM_Pos (30U) \r
+#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */\r
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM_Pos (31U) \r
+#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */\r
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ_Pos (0U) \r
+#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR_Pos (1U) \r
+#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE_Pos (2U) \r
+#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID_Pos (3U) \r
+#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */\r
+#define CAN_TI0R_STID_Pos (21U) \r
+#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC_Pos (0U) \r
+#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT_Pos (8U) \r
+#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */\r
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME_Pos (16U) \r
+#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0_Pos (0U) \r
+#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1_Pos (8U) \r
+#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2_Pos (16U) \r
+#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3_Pos (24U) \r
+#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4_Pos (0U) \r
+#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5_Pos (8U) \r
+#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6_Pos (16U) \r
+#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7_Pos (24U) \r
+#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ_Pos (0U) \r
+#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR_Pos (1U) \r
+#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE_Pos (2U) \r
+#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID_Pos (3U) \r
+#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */\r
+#define CAN_TI1R_STID_Pos (21U) \r
+#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC_Pos (0U) \r
+#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT_Pos (8U) \r
+#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */\r
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME_Pos (16U) \r
+#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0_Pos (0U) \r
+#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1_Pos (8U) \r
+#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2_Pos (16U) \r
+#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3_Pos (24U) \r
+#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4_Pos (0U) \r
+#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5_Pos (8U) \r
+#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6_Pos (16U) \r
+#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7_Pos (24U) \r
+#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ_Pos (0U) \r
+#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR_Pos (1U) \r
+#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE_Pos (2U) \r
+#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID_Pos (3U) \r
+#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */\r
+#define CAN_TI2R_STID_Pos (21U) \r
+#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/\r
+#define CAN_TDT2R_DLC_Pos (0U) \r
+#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT_Pos (8U) \r
+#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */\r
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME_Pos (16U) \r
+#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0_Pos (0U) \r
+#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1_Pos (8U) \r
+#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2_Pos (16U) \r
+#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3_Pos (24U) \r
+#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4_Pos (0U) \r
+#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5_Pos (8U) \r
+#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6_Pos (16U) \r
+#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7_Pos (24U) \r
+#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR_Pos (1U) \r
+#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE_Pos (2U) \r
+#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID_Pos (3U) \r
+#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */\r
+#define CAN_RI0R_STID_Pos (21U) \r
+#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC_Pos (0U) \r
+#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI_Pos (8U) \r
+#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME_Pos (16U) \r
+#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0_Pos (0U) \r
+#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1_Pos (8U) \r
+#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2_Pos (16U) \r
+#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3_Pos (24U) \r
+#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4_Pos (0U) \r
+#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5_Pos (8U) \r
+#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6_Pos (16U) \r
+#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7_Pos (24U) \r
+#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR_Pos (1U) \r
+#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE_Pos (2U) \r
+#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID_Pos (3U) \r
+#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */\r
+#define CAN_RI1R_STID_Pos (21U) \r
+#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC_Pos (0U) \r
+#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI_Pos (8U) \r
+#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME_Pos (16U) \r
+#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0_Pos (0U) \r
+#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1_Pos (8U) \r
+#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2_Pos (16U) \r
+#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3_Pos (24U) \r
+#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4_Pos (0U) \r
+#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5_Pos (8U) \r
+#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6_Pos (16U) \r
+#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7_Pos (24U) \r
+#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */\r
+#define CAN_FMR_CAN2SB_Pos (8U) \r
+#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */\r
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM_Pos (0U) \r
+#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */\r
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0_Pos (0U) \r
+#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */\r
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1_Pos (1U) \r
+#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */\r
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2_Pos (2U) \r
+#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */\r
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3_Pos (3U) \r
+#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */\r
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4_Pos (4U) \r
+#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */\r
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5_Pos (5U) \r
+#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */\r
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6_Pos (6U) \r
+#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */\r
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7_Pos (7U) \r
+#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */\r
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8_Pos (8U) \r
+#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */\r
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9_Pos (9U) \r
+#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */\r
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10_Pos (10U) \r
+#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */\r
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11_Pos (11U) \r
+#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */\r
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12_Pos (12U) \r
+#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */\r
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13_Pos (13U) \r
+#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */\r
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC_Pos (0U) \r
+#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */\r
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0_Pos (0U) \r
+#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */\r
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1_Pos (1U) \r
+#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */\r
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2_Pos (2U) \r
+#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */\r
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3_Pos (3U) \r
+#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */\r
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4_Pos (4U) \r
+#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */\r
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5_Pos (5U) \r
+#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */\r
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6_Pos (6U) \r
+#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */\r
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7_Pos (7U) \r
+#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */\r
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8_Pos (8U) \r
+#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */\r
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9_Pos (9U) \r
+#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */\r
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10_Pos (10U) \r
+#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */\r
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11_Pos (11U) \r
+#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */\r
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12_Pos (12U) \r
+#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */\r
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13_Pos (13U) \r
+#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */\r
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA_Pos (0U) \r
+#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */\r
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0_Pos (0U) \r
+#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */\r
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1_Pos (1U) \r
+#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */\r
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2_Pos (2U) \r
+#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */\r
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3_Pos (3U) \r
+#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */\r
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4_Pos (4U) \r
+#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */\r
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5_Pos (5U) \r
+#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */\r
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6_Pos (6U) \r
+#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */\r
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7_Pos (7U) \r
+#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */\r
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8_Pos (8U) \r
+#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */\r
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9_Pos (9U) \r
+#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */\r
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10_Pos (10U) \r
+#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */\r
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11_Pos (11U) \r
+#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */\r
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12_Pos (12U) \r
+#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */\r
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13_Pos (13U) \r
+#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */\r
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT_Pos (0U) \r
+#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */\r
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */\r
+#define CAN_FA1R_FACT0_Pos (0U) \r
+#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */\r
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1_Pos (1U) \r
+#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */\r
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2_Pos (2U) \r
+#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */\r
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3_Pos (3U) \r
+#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */\r
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4_Pos (4U) \r
+#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */\r
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5_Pos (5U) \r
+#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */\r
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6_Pos (6U) \r
+#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */\r
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7_Pos (7U) \r
+#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */\r
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8_Pos (8U) \r
+#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */\r
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9_Pos (9U) \r
+#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */\r
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10_Pos (10U) \r
+#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */\r
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11_Pos (11U) \r
+#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */\r
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12_Pos (12U) \r
+#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */\r
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13_Pos (13U) \r
+#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */\r
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0_Pos (0U) \r
+#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1_Pos (1U) \r
+#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2_Pos (2U) \r
+#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3_Pos (3U) \r
+#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4_Pos (4U) \r
+#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5_Pos (5U) \r
+#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6_Pos (6U) \r
+#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7_Pos (7U) \r
+#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8_Pos (8U) \r
+#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9_Pos (9U) \r
+#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10_Pos (10U) \r
+#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11_Pos (11U) \r
+#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12_Pos (12U) \r
+#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13_Pos (13U) \r
+#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14_Pos (14U) \r
+#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15_Pos (15U) \r
+#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16_Pos (16U) \r
+#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17_Pos (17U) \r
+#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18_Pos (18U) \r
+#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19_Pos (19U) \r
+#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20_Pos (20U) \r
+#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21_Pos (21U) \r
+#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22_Pos (22U) \r
+#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23_Pos (23U) \r
+#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24_Pos (24U) \r
+#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25_Pos (25U) \r
+#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26_Pos (26U) \r
+#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27_Pos (27U) \r
+#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28_Pos (28U) \r
+#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29_Pos (29U) \r
+#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30_Pos (30U) \r
+#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31_Pos (31U) \r
+#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0_Pos (0U) \r
+#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1_Pos (1U) \r
+#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2_Pos (2U) \r
+#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3_Pos (3U) \r
+#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4_Pos (4U) \r
+#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5_Pos (5U) \r
+#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6_Pos (6U) \r
+#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7_Pos (7U) \r
+#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8_Pos (8U) \r
+#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9_Pos (9U) \r
+#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10_Pos (10U) \r
+#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11_Pos (11U) \r
+#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12_Pos (12U) \r
+#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13_Pos (13U) \r
+#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14_Pos (14U) \r
+#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15_Pos (15U) \r
+#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16_Pos (16U) \r
+#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17_Pos (17U) \r
+#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18_Pos (18U) \r
+#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19_Pos (19U) \r
+#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20_Pos (20U) \r
+#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21_Pos (21U) \r
+#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22_Pos (22U) \r
+#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23_Pos (23U) \r
+#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24_Pos (24U) \r
+#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25_Pos (25U) \r
+#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26_Pos (26U) \r
+#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27_Pos (27U) \r
+#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28_Pos (28U) \r
+#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29_Pos (29U) \r
+#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30_Pos (30U) \r
+#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31_Pos (31U) \r
+#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0_Pos (0U) \r
+#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1_Pos (1U) \r
+#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2_Pos (2U) \r
+#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3_Pos (3U) \r
+#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4_Pos (4U) \r
+#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5_Pos (5U) \r
+#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6_Pos (6U) \r
+#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7_Pos (7U) \r
+#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8_Pos (8U) \r
+#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9_Pos (9U) \r
+#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10_Pos (10U) \r
+#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11_Pos (11U) \r
+#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12_Pos (12U) \r
+#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13_Pos (13U) \r
+#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14_Pos (14U) \r
+#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15_Pos (15U) \r
+#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16_Pos (16U) \r
+#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17_Pos (17U) \r
+#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18_Pos (18U) \r
+#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19_Pos (19U) \r
+#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20_Pos (20U) \r
+#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21_Pos (21U) \r
+#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22_Pos (22U) \r
+#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23_Pos (23U) \r
+#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24_Pos (24U) \r
+#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25_Pos (25U) \r
+#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26_Pos (26U) \r
+#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27_Pos (27U) \r
+#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28_Pos (28U) \r
+#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29_Pos (29U) \r
+#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30_Pos (30U) \r
+#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31_Pos (31U) \r
+#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0_Pos (0U) \r
+#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1_Pos (1U) \r
+#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2_Pos (2U) \r
+#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3_Pos (3U) \r
+#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4_Pos (4U) \r
+#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5_Pos (5U) \r
+#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6_Pos (6U) \r
+#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7_Pos (7U) \r
+#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8_Pos (8U) \r
+#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9_Pos (9U) \r
+#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10_Pos (10U) \r
+#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11_Pos (11U) \r
+#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12_Pos (12U) \r
+#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13_Pos (13U) \r
+#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14_Pos (14U) \r
+#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15_Pos (15U) \r
+#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16_Pos (16U) \r
+#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17_Pos (17U) \r
+#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18_Pos (18U) \r
+#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19_Pos (19U) \r
+#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20_Pos (20U) \r
+#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21_Pos (21U) \r
+#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22_Pos (22U) \r
+#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23_Pos (23U) \r
+#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24_Pos (24U) \r
+#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25_Pos (25U) \r
+#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26_Pos (26U) \r
+#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27_Pos (27U) \r
+#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28_Pos (28U) \r
+#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29_Pos (29U) \r
+#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30_Pos (30U) \r
+#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31_Pos (31U) \r
+#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0_Pos (0U) \r
+#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1_Pos (1U) \r
+#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2_Pos (2U) \r
+#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3_Pos (3U) \r
+#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4_Pos (4U) \r
+#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5_Pos (5U) \r
+#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6_Pos (6U) \r
+#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7_Pos (7U) \r
+#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8_Pos (8U) \r
+#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9_Pos (9U) \r
+#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10_Pos (10U) \r
+#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11_Pos (11U) \r
+#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12_Pos (12U) \r
+#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13_Pos (13U) \r
+#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14_Pos (14U) \r
+#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15_Pos (15U) \r
+#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16_Pos (16U) \r
+#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17_Pos (17U) \r
+#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18_Pos (18U) \r
+#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19_Pos (19U) \r
+#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20_Pos (20U) \r
+#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21_Pos (21U) \r
+#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22_Pos (22U) \r
+#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23_Pos (23U) \r
+#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24_Pos (24U) \r
+#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25_Pos (25U) \r
+#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26_Pos (26U) \r
+#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27_Pos (27U) \r
+#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28_Pos (28U) \r
+#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29_Pos (29U) \r
+#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30_Pos (30U) \r
+#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31_Pos (31U) \r
+#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0_Pos (0U) \r
+#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1_Pos (1U) \r
+#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2_Pos (2U) \r
+#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3_Pos (3U) \r
+#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4_Pos (4U) \r
+#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5_Pos (5U) \r
+#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6_Pos (6U) \r
+#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7_Pos (7U) \r
+#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8_Pos (8U) \r
+#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9_Pos (9U) \r
+#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10_Pos (10U) \r
+#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11_Pos (11U) \r
+#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12_Pos (12U) \r
+#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13_Pos (13U) \r
+#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14_Pos (14U) \r
+#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15_Pos (15U) \r
+#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16_Pos (16U) \r
+#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17_Pos (17U) \r
+#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18_Pos (18U) \r
+#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19_Pos (19U) \r
+#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20_Pos (20U) \r
+#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21_Pos (21U) \r
+#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22_Pos (22U) \r
+#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23_Pos (23U) \r
+#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24_Pos (24U) \r
+#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25_Pos (25U) \r
+#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26_Pos (26U) \r
+#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27_Pos (27U) \r
+#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28_Pos (28U) \r
+#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29_Pos (29U) \r
+#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30_Pos (30U) \r
+#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31_Pos (31U) \r
+#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0_Pos (0U) \r
+#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1_Pos (1U) \r
+#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2_Pos (2U) \r
+#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3_Pos (3U) \r
+#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4_Pos (4U) \r
+#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5_Pos (5U) \r
+#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6_Pos (6U) \r
+#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7_Pos (7U) \r
+#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8_Pos (8U) \r
+#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9_Pos (9U) \r
+#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10_Pos (10U) \r
+#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11_Pos (11U) \r
+#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12_Pos (12U) \r
+#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13_Pos (13U) \r
+#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14_Pos (14U) \r
+#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15_Pos (15U) \r
+#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16_Pos (16U) \r
+#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17_Pos (17U) \r
+#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18_Pos (18U) \r
+#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19_Pos (19U) \r
+#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20_Pos (20U) \r
+#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21_Pos (21U) \r
+#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22_Pos (22U) \r
+#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23_Pos (23U) \r
+#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24_Pos (24U) \r
+#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25_Pos (25U) \r
+#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26_Pos (26U) \r
+#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27_Pos (27U) \r
+#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28_Pos (28U) \r
+#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29_Pos (29U) \r
+#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30_Pos (30U) \r
+#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31_Pos (31U) \r
+#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0_Pos (0U) \r
+#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1_Pos (1U) \r
+#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2_Pos (2U) \r
+#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3_Pos (3U) \r
+#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4_Pos (4U) \r
+#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5_Pos (5U) \r
+#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6_Pos (6U) \r
+#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7_Pos (7U) \r
+#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8_Pos (8U) \r
+#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9_Pos (9U) \r
+#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10_Pos (10U) \r
+#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11_Pos (11U) \r
+#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12_Pos (12U) \r
+#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13_Pos (13U) \r
+#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14_Pos (14U) \r
+#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15_Pos (15U) \r
+#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16_Pos (16U) \r
+#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17_Pos (17U) \r
+#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18_Pos (18U) \r
+#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19_Pos (19U) \r
+#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20_Pos (20U) \r
+#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21_Pos (21U) \r
+#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22_Pos (22U) \r
+#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23_Pos (23U) \r
+#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24_Pos (24U) \r
+#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25_Pos (25U) \r
+#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26_Pos (26U) \r
+#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27_Pos (27U) \r
+#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28_Pos (28U) \r
+#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29_Pos (29U) \r
+#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30_Pos (30U) \r
+#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31_Pos (31U) \r
+#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0_Pos (0U) \r
+#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1_Pos (1U) \r
+#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2_Pos (2U) \r
+#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3_Pos (3U) \r
+#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4_Pos (4U) \r
+#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5_Pos (5U) \r
+#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6_Pos (6U) \r
+#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7_Pos (7U) \r
+#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8_Pos (8U) \r
+#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9_Pos (9U) \r
+#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10_Pos (10U) \r
+#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11_Pos (11U) \r
+#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12_Pos (12U) \r
+#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13_Pos (13U) \r
+#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14_Pos (14U) \r
+#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15_Pos (15U) \r
+#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16_Pos (16U) \r
+#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17_Pos (17U) \r
+#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18_Pos (18U) \r
+#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19_Pos (19U) \r
+#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20_Pos (20U) \r
+#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21_Pos (21U) \r
+#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22_Pos (22U) \r
+#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23_Pos (23U) \r
+#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24_Pos (24U) \r
+#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25_Pos (25U) \r
+#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26_Pos (26U) \r
+#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27_Pos (27U) \r
+#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28_Pos (28U) \r
+#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29_Pos (29U) \r
+#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30_Pos (30U) \r
+#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31_Pos (31U) \r
+#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0_Pos (0U) \r
+#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1_Pos (1U) \r
+#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2_Pos (2U) \r
+#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3_Pos (3U) \r
+#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4_Pos (4U) \r
+#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5_Pos (5U) \r
+#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6_Pos (6U) \r
+#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7_Pos (7U) \r
+#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8_Pos (8U) \r
+#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9_Pos (9U) \r
+#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10_Pos (10U) \r
+#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11_Pos (11U) \r
+#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12_Pos (12U) \r
+#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13_Pos (13U) \r
+#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14_Pos (14U) \r
+#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15_Pos (15U) \r
+#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16_Pos (16U) \r
+#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17_Pos (17U) \r
+#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18_Pos (18U) \r
+#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19_Pos (19U) \r
+#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20_Pos (20U) \r
+#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21_Pos (21U) \r
+#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22_Pos (22U) \r
+#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23_Pos (23U) \r
+#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24_Pos (24U) \r
+#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25_Pos (25U) \r
+#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26_Pos (26U) \r
+#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27_Pos (27U) \r
+#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28_Pos (28U) \r
+#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29_Pos (29U) \r
+#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30_Pos (30U) \r
+#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31_Pos (31U) \r
+#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0_Pos (0U) \r
+#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1_Pos (1U) \r
+#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2_Pos (2U) \r
+#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3_Pos (3U) \r
+#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4_Pos (4U) \r
+#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5_Pos (5U) \r
+#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6_Pos (6U) \r
+#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7_Pos (7U) \r
+#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8_Pos (8U) \r
+#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9_Pos (9U) \r
+#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10_Pos (10U) \r
+#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11_Pos (11U) \r
+#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12_Pos (12U) \r
+#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13_Pos (13U) \r
+#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14_Pos (14U) \r
+#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15_Pos (15U) \r
+#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16_Pos (16U) \r
+#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17_Pos (17U) \r
+#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18_Pos (18U) \r
+#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19_Pos (19U) \r
+#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20_Pos (20U) \r
+#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21_Pos (21U) \r
+#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22_Pos (22U) \r
+#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23_Pos (23U) \r
+#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24_Pos (24U) \r
+#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25_Pos (25U) \r
+#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26_Pos (26U) \r
+#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27_Pos (27U) \r
+#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28_Pos (28U) \r
+#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29_Pos (29U) \r
+#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30_Pos (30U) \r
+#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31_Pos (31U) \r
+#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0_Pos (0U) \r
+#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1_Pos (1U) \r
+#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2_Pos (2U) \r
+#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3_Pos (3U) \r
+#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4_Pos (4U) \r
+#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5_Pos (5U) \r
+#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6_Pos (6U) \r
+#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7_Pos (7U) \r
+#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8_Pos (8U) \r
+#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9_Pos (9U) \r
+#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10_Pos (10U) \r
+#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11_Pos (11U) \r
+#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12_Pos (12U) \r
+#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13_Pos (13U) \r
+#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14_Pos (14U) \r
+#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15_Pos (15U) \r
+#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16_Pos (16U) \r
+#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17_Pos (17U) \r
+#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18_Pos (18U) \r
+#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19_Pos (19U) \r
+#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20_Pos (20U) \r
+#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21_Pos (21U) \r
+#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22_Pos (22U) \r
+#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23_Pos (23U) \r
+#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24_Pos (24U) \r
+#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25_Pos (25U) \r
+#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26_Pos (26U) \r
+#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27_Pos (27U) \r
+#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28_Pos (28U) \r
+#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29_Pos (29U) \r
+#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30_Pos (30U) \r
+#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31_Pos (31U) \r
+#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0_Pos (0U) \r
+#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1_Pos (1U) \r
+#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2_Pos (2U) \r
+#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3_Pos (3U) \r
+#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4_Pos (4U) \r
+#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5_Pos (5U) \r
+#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6_Pos (6U) \r
+#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7_Pos (7U) \r
+#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8_Pos (8U) \r
+#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9_Pos (9U) \r
+#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10_Pos (10U) \r
+#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11_Pos (11U) \r
+#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12_Pos (12U) \r
+#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13_Pos (13U) \r
+#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14_Pos (14U) \r
+#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15_Pos (15U) \r
+#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16_Pos (16U) \r
+#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17_Pos (17U) \r
+#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18_Pos (18U) \r
+#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19_Pos (19U) \r
+#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20_Pos (20U) \r
+#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21_Pos (21U) \r
+#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22_Pos (22U) \r
+#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23_Pos (23U) \r
+#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24_Pos (24U) \r
+#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25_Pos (25U) \r
+#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26_Pos (26U) \r
+#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27_Pos (27U) \r
+#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28_Pos (28U) \r
+#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29_Pos (29U) \r
+#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30_Pos (30U) \r
+#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31_Pos (31U) \r
+#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0_Pos (0U) \r
+#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1_Pos (1U) \r
+#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2_Pos (2U) \r
+#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3_Pos (3U) \r
+#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4_Pos (4U) \r
+#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5_Pos (5U) \r
+#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6_Pos (6U) \r
+#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7_Pos (7U) \r
+#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8_Pos (8U) \r
+#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9_Pos (9U) \r
+#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10_Pos (10U) \r
+#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11_Pos (11U) \r
+#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12_Pos (12U) \r
+#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13_Pos (13U) \r
+#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14_Pos (14U) \r
+#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15_Pos (15U) \r
+#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16_Pos (16U) \r
+#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17_Pos (17U) \r
+#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18_Pos (18U) \r
+#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19_Pos (19U) \r
+#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20_Pos (20U) \r
+#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21_Pos (21U) \r
+#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22_Pos (22U) \r
+#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23_Pos (23U) \r
+#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24_Pos (24U) \r
+#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25_Pos (25U) \r
+#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26_Pos (26U) \r
+#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27_Pos (27U) \r
+#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28_Pos (28U) \r
+#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29_Pos (29U) \r
+#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30_Pos (30U) \r
+#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31_Pos (31U) \r
+#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0_Pos (0U) \r
+#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1_Pos (1U) \r
+#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2_Pos (2U) \r
+#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3_Pos (3U) \r
+#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4_Pos (4U) \r
+#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5_Pos (5U) \r
+#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6_Pos (6U) \r
+#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7_Pos (7U) \r
+#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8_Pos (8U) \r
+#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9_Pos (9U) \r
+#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10_Pos (10U) \r
+#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11_Pos (11U) \r
+#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12_Pos (12U) \r
+#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13_Pos (13U) \r
+#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14_Pos (14U) \r
+#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15_Pos (15U) \r
+#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16_Pos (16U) \r
+#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17_Pos (17U) \r
+#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18_Pos (18U) \r
+#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19_Pos (19U) \r
+#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20_Pos (20U) \r
+#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21_Pos (21U) \r
+#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22_Pos (22U) \r
+#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23_Pos (23U) \r
+#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24_Pos (24U) \r
+#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25_Pos (25U) \r
+#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26_Pos (26U) \r
+#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27_Pos (27U) \r
+#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28_Pos (28U) \r
+#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29_Pos (29U) \r
+#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30_Pos (30U) \r
+#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31_Pos (31U) \r
+#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0_Pos (0U) \r
+#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1_Pos (1U) \r
+#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2_Pos (2U) \r
+#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3_Pos (3U) \r
+#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4_Pos (4U) \r
+#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5_Pos (5U) \r
+#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6_Pos (6U) \r
+#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7_Pos (7U) \r
+#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8_Pos (8U) \r
+#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9_Pos (9U) \r
+#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10_Pos (10U) \r
+#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11_Pos (11U) \r
+#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12_Pos (12U) \r
+#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13_Pos (13U) \r
+#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14_Pos (14U) \r
+#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15_Pos (15U) \r
+#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16_Pos (16U) \r
+#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17_Pos (17U) \r
+#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18_Pos (18U) \r
+#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19_Pos (19U) \r
+#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20_Pos (20U) \r
+#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21_Pos (21U) \r
+#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22_Pos (22U) \r
+#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23_Pos (23U) \r
+#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24_Pos (24U) \r
+#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25_Pos (25U) \r
+#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26_Pos (26U) \r
+#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27_Pos (27U) \r
+#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28_Pos (28U) \r
+#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29_Pos (29U) \r
+#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30_Pos (30U) \r
+#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31_Pos (31U) \r
+#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0_Pos (0U) \r
+#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1_Pos (1U) \r
+#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2_Pos (2U) \r
+#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3_Pos (3U) \r
+#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4_Pos (4U) \r
+#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5_Pos (5U) \r
+#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6_Pos (6U) \r
+#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7_Pos (7U) \r
+#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8_Pos (8U) \r
+#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9_Pos (9U) \r
+#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10_Pos (10U) \r
+#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11_Pos (11U) \r
+#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12_Pos (12U) \r
+#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13_Pos (13U) \r
+#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14_Pos (14U) \r
+#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15_Pos (15U) \r
+#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16_Pos (16U) \r
+#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17_Pos (17U) \r
+#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18_Pos (18U) \r
+#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19_Pos (19U) \r
+#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20_Pos (20U) \r
+#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21_Pos (21U) \r
+#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22_Pos (22U) \r
+#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23_Pos (23U) \r
+#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24_Pos (24U) \r
+#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25_Pos (25U) \r
+#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26_Pos (26U) \r
+#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27_Pos (27U) \r
+#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28_Pos (28U) \r
+#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29_Pos (29U) \r
+#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30_Pos (30U) \r
+#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31_Pos (31U) \r
+#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0_Pos (0U) \r
+#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1_Pos (1U) \r
+#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2_Pos (2U) \r
+#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3_Pos (3U) \r
+#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4_Pos (4U) \r
+#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5_Pos (5U) \r
+#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6_Pos (6U) \r
+#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7_Pos (7U) \r
+#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8_Pos (8U) \r
+#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9_Pos (9U) \r
+#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10_Pos (10U) \r
+#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11_Pos (11U) \r
+#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12_Pos (12U) \r
+#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13_Pos (13U) \r
+#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14_Pos (14U) \r
+#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15_Pos (15U) \r
+#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16_Pos (16U) \r
+#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17_Pos (17U) \r
+#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18_Pos (18U) \r
+#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19_Pos (19U) \r
+#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20_Pos (20U) \r
+#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21_Pos (21U) \r
+#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22_Pos (22U) \r
+#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23_Pos (23U) \r
+#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24_Pos (24U) \r
+#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25_Pos (25U) \r
+#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26_Pos (26U) \r
+#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27_Pos (27U) \r
+#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28_Pos (28U) \r
+#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29_Pos (29U) \r
+#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30_Pos (30U) \r
+#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31_Pos (31U) \r
+#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0_Pos (0U) \r
+#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1_Pos (1U) \r
+#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2_Pos (2U) \r
+#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3_Pos (3U) \r
+#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4_Pos (4U) \r
+#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5_Pos (5U) \r
+#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6_Pos (6U) \r
+#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7_Pos (7U) \r
+#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8_Pos (8U) \r
+#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9_Pos (9U) \r
+#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10_Pos (10U) \r
+#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11_Pos (11U) \r
+#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12_Pos (12U) \r
+#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13_Pos (13U) \r
+#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14_Pos (14U) \r
+#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15_Pos (15U) \r
+#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16_Pos (16U) \r
+#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17_Pos (17U) \r
+#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18_Pos (18U) \r
+#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19_Pos (19U) \r
+#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20_Pos (20U) \r
+#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21_Pos (21U) \r
+#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22_Pos (22U) \r
+#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23_Pos (23U) \r
+#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24_Pos (24U) \r
+#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25_Pos (25U) \r
+#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26_Pos (26U) \r
+#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27_Pos (27U) \r
+#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28_Pos (28U) \r
+#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29_Pos (29U) \r
+#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30_Pos (30U) \r
+#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31_Pos (31U) \r
+#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0_Pos (0U) \r
+#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1_Pos (1U) \r
+#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2_Pos (2U) \r
+#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3_Pos (3U) \r
+#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4_Pos (4U) \r
+#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5_Pos (5U) \r
+#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6_Pos (6U) \r
+#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7_Pos (7U) \r
+#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8_Pos (8U) \r
+#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9_Pos (9U) \r
+#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10_Pos (10U) \r
+#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11_Pos (11U) \r
+#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12_Pos (12U) \r
+#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13_Pos (13U) \r
+#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14_Pos (14U) \r
+#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15_Pos (15U) \r
+#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16_Pos (16U) \r
+#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17_Pos (17U) \r
+#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18_Pos (18U) \r
+#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19_Pos (19U) \r
+#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20_Pos (20U) \r
+#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21_Pos (21U) \r
+#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22_Pos (22U) \r
+#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23_Pos (23U) \r
+#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24_Pos (24U) \r
+#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25_Pos (25U) \r
+#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26_Pos (26U) \r
+#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27_Pos (27U) \r
+#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28_Pos (28U) \r
+#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29_Pos (29U) \r
+#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30_Pos (30U) \r
+#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31_Pos (31U) \r
+#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0_Pos (0U) \r
+#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1_Pos (1U) \r
+#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2_Pos (2U) \r
+#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3_Pos (3U) \r
+#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4_Pos (4U) \r
+#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5_Pos (5U) \r
+#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6_Pos (6U) \r
+#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7_Pos (7U) \r
+#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8_Pos (8U) \r
+#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9_Pos (9U) \r
+#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10_Pos (10U) \r
+#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11_Pos (11U) \r
+#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12_Pos (12U) \r
+#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13_Pos (13U) \r
+#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14_Pos (14U) \r
+#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15_Pos (15U) \r
+#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16_Pos (16U) \r
+#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17_Pos (17U) \r
+#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18_Pos (18U) \r
+#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19_Pos (19U) \r
+#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20_Pos (20U) \r
+#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21_Pos (21U) \r
+#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22_Pos (22U) \r
+#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23_Pos (23U) \r
+#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24_Pos (24U) \r
+#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25_Pos (25U) \r
+#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26_Pos (26U) \r
+#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27_Pos (27U) \r
+#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28_Pos (28U) \r
+#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29_Pos (29U) \r
+#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30_Pos (30U) \r
+#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31_Pos (31U) \r
+#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0_Pos (0U) \r
+#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1_Pos (1U) \r
+#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2_Pos (2U) \r
+#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3_Pos (3U) \r
+#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4_Pos (4U) \r
+#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5_Pos (5U) \r
+#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6_Pos (6U) \r
+#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7_Pos (7U) \r
+#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8_Pos (8U) \r
+#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9_Pos (9U) \r
+#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10_Pos (10U) \r
+#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11_Pos (11U) \r
+#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12_Pos (12U) \r
+#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13_Pos (13U) \r
+#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14_Pos (14U) \r
+#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15_Pos (15U) \r
+#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16_Pos (16U) \r
+#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17_Pos (17U) \r
+#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18_Pos (18U) \r
+#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19_Pos (19U) \r
+#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20_Pos (20U) \r
+#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21_Pos (21U) \r
+#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22_Pos (22U) \r
+#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23_Pos (23U) \r
+#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24_Pos (24U) \r
+#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25_Pos (25U) \r
+#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26_Pos (26U) \r
+#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27_Pos (27U) \r
+#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28_Pos (28U) \r
+#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29_Pos (29U) \r
+#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30_Pos (30U) \r
+#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31_Pos (31U) \r
+#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0_Pos (0U) \r
+#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1_Pos (1U) \r
+#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2_Pos (2U) \r
+#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3_Pos (3U) \r
+#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4_Pos (4U) \r
+#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5_Pos (5U) \r
+#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6_Pos (6U) \r
+#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7_Pos (7U) \r
+#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8_Pos (8U) \r
+#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9_Pos (9U) \r
+#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10_Pos (10U) \r
+#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11_Pos (11U) \r
+#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12_Pos (12U) \r
+#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13_Pos (13U) \r
+#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14_Pos (14U) \r
+#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15_Pos (15U) \r
+#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16_Pos (16U) \r
+#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17_Pos (17U) \r
+#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18_Pos (18U) \r
+#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19_Pos (19U) \r
+#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20_Pos (20U) \r
+#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21_Pos (21U) \r
+#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22_Pos (22U) \r
+#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23_Pos (23U) \r
+#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24_Pos (24U) \r
+#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25_Pos (25U) \r
+#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26_Pos (26U) \r
+#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27_Pos (27U) \r
+#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28_Pos (28U) \r
+#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29_Pos (29U) \r
+#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30_Pos (30U) \r
+#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31_Pos (31U) \r
+#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0_Pos (0U) \r
+#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1_Pos (1U) \r
+#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2_Pos (2U) \r
+#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3_Pos (3U) \r
+#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4_Pos (4U) \r
+#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5_Pos (5U) \r
+#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6_Pos (6U) \r
+#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7_Pos (7U) \r
+#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8_Pos (8U) \r
+#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9_Pos (9U) \r
+#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10_Pos (10U) \r
+#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11_Pos (11U) \r
+#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12_Pos (12U) \r
+#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13_Pos (13U) \r
+#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14_Pos (14U) \r
+#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15_Pos (15U) \r
+#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16_Pos (16U) \r
+#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17_Pos (17U) \r
+#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18_Pos (18U) \r
+#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19_Pos (19U) \r
+#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20_Pos (20U) \r
+#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21_Pos (21U) \r
+#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22_Pos (22U) \r
+#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23_Pos (23U) \r
+#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24_Pos (24U) \r
+#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25_Pos (25U) \r
+#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26_Pos (26U) \r
+#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27_Pos (27U) \r
+#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28_Pos (28U) \r
+#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29_Pos (29U) \r
+#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30_Pos (30U) \r
+#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31_Pos (31U) \r
+#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0_Pos (0U) \r
+#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1_Pos (1U) \r
+#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2_Pos (2U) \r
+#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3_Pos (3U) \r
+#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4_Pos (4U) \r
+#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5_Pos (5U) \r
+#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6_Pos (6U) \r
+#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7_Pos (7U) \r
+#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8_Pos (8U) \r
+#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9_Pos (9U) \r
+#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10_Pos (10U) \r
+#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11_Pos (11U) \r
+#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12_Pos (12U) \r
+#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13_Pos (13U) \r
+#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14_Pos (14U) \r
+#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15_Pos (15U) \r
+#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16_Pos (16U) \r
+#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17_Pos (17U) \r
+#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18_Pos (18U) \r
+#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19_Pos (19U) \r
+#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20_Pos (20U) \r
+#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21_Pos (21U) \r
+#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22_Pos (22U) \r
+#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23_Pos (23U) \r
+#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24_Pos (24U) \r
+#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25_Pos (25U) \r
+#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26_Pos (26U) \r
+#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27_Pos (27U) \r
+#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28_Pos (28U) \r
+#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29_Pos (29U) \r
+#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30_Pos (30U) \r
+#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31_Pos (31U) \r
+#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0_Pos (0U) \r
+#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1_Pos (1U) \r
+#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2_Pos (2U) \r
+#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3_Pos (3U) \r
+#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4_Pos (4U) \r
+#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5_Pos (5U) \r
+#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6_Pos (6U) \r
+#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7_Pos (7U) \r
+#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8_Pos (8U) \r
+#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9_Pos (9U) \r
+#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10_Pos (10U) \r
+#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11_Pos (11U) \r
+#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12_Pos (12U) \r
+#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13_Pos (13U) \r
+#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14_Pos (14U) \r
+#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15_Pos (15U) \r
+#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16_Pos (16U) \r
+#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17_Pos (17U) \r
+#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18_Pos (18U) \r
+#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19_Pos (19U) \r
+#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20_Pos (20U) \r
+#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21_Pos (21U) \r
+#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22_Pos (22U) \r
+#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23_Pos (23U) \r
+#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24_Pos (24U) \r
+#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25_Pos (25U) \r
+#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26_Pos (26U) \r
+#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27_Pos (27U) \r
+#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28_Pos (28U) \r
+#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29_Pos (29U) \r
+#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30_Pos (30U) \r
+#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31_Pos (31U) \r
+#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0_Pos (0U) \r
+#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1_Pos (1U) \r
+#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2_Pos (2U) \r
+#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3_Pos (3U) \r
+#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4_Pos (4U) \r
+#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5_Pos (5U) \r
+#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6_Pos (6U) \r
+#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7_Pos (7U) \r
+#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8_Pos (8U) \r
+#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9_Pos (9U) \r
+#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10_Pos (10U) \r
+#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11_Pos (11U) \r
+#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12_Pos (12U) \r
+#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13_Pos (13U) \r
+#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14_Pos (14U) \r
+#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15_Pos (15U) \r
+#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16_Pos (16U) \r
+#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17_Pos (17U) \r
+#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18_Pos (18U) \r
+#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19_Pos (19U) \r
+#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20_Pos (20U) \r
+#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21_Pos (21U) \r
+#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22_Pos (22U) \r
+#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23_Pos (23U) \r
+#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24_Pos (24U) \r
+#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25_Pos (25U) \r
+#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26_Pos (26U) \r
+#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27_Pos (27U) \r
+#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28_Pos (28U) \r
+#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29_Pos (29U) \r
+#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30_Pos (30U) \r
+#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31_Pos (31U) \r
+#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0_Pos (0U) \r
+#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1_Pos (1U) \r
+#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2_Pos (2U) \r
+#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3_Pos (3U) \r
+#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4_Pos (4U) \r
+#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5_Pos (5U) \r
+#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6_Pos (6U) \r
+#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7_Pos (7U) \r
+#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8_Pos (8U) \r
+#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9_Pos (9U) \r
+#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10_Pos (10U) \r
+#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11_Pos (11U) \r
+#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12_Pos (12U) \r
+#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13_Pos (13U) \r
+#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14_Pos (14U) \r
+#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15_Pos (15U) \r
+#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16_Pos (16U) \r
+#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17_Pos (17U) \r
+#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18_Pos (18U) \r
+#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19_Pos (19U) \r
+#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20_Pos (20U) \r
+#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21_Pos (21U) \r
+#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22_Pos (22U) \r
+#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23_Pos (23U) \r
+#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24_Pos (24U) \r
+#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25_Pos (25U) \r
+#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26_Pos (26U) \r
+#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27_Pos (27U) \r
+#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28_Pos (28U) \r
+#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29_Pos (29U) \r
+#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30_Pos (30U) \r
+#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31_Pos (31U) \r
+#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HDMI-CEC (CEC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CEC_CR register *********************/\r
+#define CEC_CR_CECEN_Pos (0U) \r
+#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */\r
+#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */\r
+#define CEC_CR_TXSOM_Pos (1U) \r
+#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */\r
+#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */\r
+#define CEC_CR_TXEOM_Pos (2U) \r
+#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */\r
+#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */\r
+\r
+/******************* Bit definition for CEC_CFGR register *******************/\r
+#define CEC_CFGR_SFT_Pos (0U) \r
+#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */\r
+#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */\r
+#define CEC_CFGR_RXTOL_Pos (3U) \r
+#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */\r
+#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */\r
+#define CEC_CFGR_BRESTP_Pos (4U) \r
+#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */\r
+#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */\r
+#define CEC_CFGR_BREGEN_Pos (5U) \r
+#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */\r
+#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */\r
+#define CEC_CFGR_LBPEGEN_Pos (6U) \r
+#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */\r
+#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Period Error generation */\r
+#define CEC_CFGR_BRDNOGEN_Pos (7U) \r
+#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */\r
+#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast no Error generation */\r
+#define CEC_CFGR_SFTOPT_Pos (8U) \r
+#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */\r
+#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */\r
+#define CEC_CFGR_OAR_Pos (16U) \r
+#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */\r
+#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */\r
+#define CEC_CFGR_LSTN_Pos (31U) \r
+#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */\r
+#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */\r
+\r
+/******************* Bit definition for CEC_TXDR register *******************/\r
+#define CEC_TXDR_TXD_Pos (0U) \r
+#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */\r
+#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */\r
+\r
+/******************* Bit definition for CEC_RXDR register *******************/\r
+#define CEC_RXDR_RXD_Pos (0U) \r
+#define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */\r
+#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */\r
+\r
+/******************* Bit definition for CEC_ISR register ********************/\r
+#define CEC_ISR_RXBR_Pos (0U) \r
+#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */\r
+#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */\r
+#define CEC_ISR_RXEND_Pos (1U) \r
+#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */\r
+#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */\r
+#define CEC_ISR_RXOVR_Pos (2U) \r
+#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */\r
+#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */\r
+#define CEC_ISR_BRE_Pos (3U) \r
+#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */\r
+#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */\r
+#define CEC_ISR_SBPE_Pos (4U) \r
+#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */\r
+#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */\r
+#define CEC_ISR_LBPE_Pos (5U) \r
+#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */\r
+#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */\r
+#define CEC_ISR_RXACKE_Pos (6U) \r
+#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */\r
+#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */\r
+#define CEC_ISR_ARBLST_Pos (7U) \r
+#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */\r
+#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */\r
+#define CEC_ISR_TXBR_Pos (8U) \r
+#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */\r
+#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */\r
+#define CEC_ISR_TXEND_Pos (9U) \r
+#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */\r
+#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */\r
+#define CEC_ISR_TXUDR_Pos (10U) \r
+#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */\r
+#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */\r
+#define CEC_ISR_TXERR_Pos (11U) \r
+#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */\r
+#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */\r
+#define CEC_ISR_TXACKE_Pos (12U) \r
+#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */\r
+#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */\r
+\r
+/******************* Bit definition for CEC_IER register ********************/\r
+#define CEC_IER_RXBRIE_Pos (0U) \r
+#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */\r
+#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */\r
+#define CEC_IER_RXENDIE_Pos (1U) \r
+#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */\r
+#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */\r
+#define CEC_IER_RXOVRIE_Pos (2U) \r
+#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */\r
+#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */\r
+#define CEC_IER_BREIE_Pos (3U) \r
+#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */\r
+#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */\r
+#define CEC_IER_SBPEIE_Pos (4U) \r
+#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */\r
+#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/\r
+#define CEC_IER_LBPEIE_Pos (5U) \r
+#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */\r
+#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */\r
+#define CEC_IER_RXACKEIE_Pos (6U) \r
+#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */\r
+#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */\r
+#define CEC_IER_ARBLSTIE_Pos (7U) \r
+#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */\r
+#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */\r
+#define CEC_IER_TXBRIE_Pos (8U) \r
+#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */\r
+#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */\r
+#define CEC_IER_TXENDIE_Pos (9U) \r
+#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */\r
+#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */\r
+#define CEC_IER_TXUDRIE_Pos (10U) \r
+#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */\r
+#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */\r
+#define CEC_IER_TXERRIE_Pos (11U) \r
+#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */\r
+#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */\r
+#define CEC_IER_TXACKEIE_Pos (12U) \r
+#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */\r
+#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR_Pos (0U) \r
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR_Pos (0U) \r
+#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */\r
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET_Pos (0U) \r
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\r
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_POLYSIZE_Pos (3U) \r
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */\r
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */\r
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */\r
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */\r
+#define CRC_CR_REV_IN_Pos (5U) \r
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */\r
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */\r
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */\r
+#define CRC_CR_REV_OUT_Pos (7U) \r
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */\r
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/******************* Bit definition for CRC_INIT register *******************/\r
+#define CRC_INIT_INIT_Pos (0U) \r
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */\r
+\r
+/******************* Bit definition for CRC_POL register ********************/\r
+#define CRC_POL_POL_Pos (0U) \r
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1_Pos (0U) \r
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\r
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1_Pos (1U) \r
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */\r
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1_Pos (2U) \r
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */\r
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */\r
+#define DAC_CR_TSEL1_Pos (3U) \r
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */\r
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */\r
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */\r
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */\r
+#define DAC_CR_WAVE1_Pos (6U) \r
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */\r
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */\r
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */\r
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */\r
+#define DAC_CR_MAMP1_Pos (8U) \r
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */\r
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */\r
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */\r
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */\r
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */\r
+#define DAC_CR_DMAEN1_Pos (12U) \r
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */\r
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1_Pos (13U) \r
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */\r
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */\r
+#define DAC_CR_EN2_Pos (16U) \r
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\r
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2_Pos (17U) \r
+#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */\r
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2_Pos (18U) \r
+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */\r
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */\r
+#define DAC_CR_TSEL2_Pos (19U) \r
+#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */\r
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */\r
+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */\r
+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */\r
+#define DAC_CR_WAVE2_Pos (22U) \r
+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */\r
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */\r
+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */\r
+#define DAC_CR_MAMP2_Pos (24U) \r
+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */\r
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */\r
+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */\r
+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */\r
+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */\r
+#define DAC_CR_DMAEN2_Pos (28U) \r
+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */\r
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */\r
+#define DAC_CR_DMAUDRIE2_Pos (29U) \r
+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */\r
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U) \r
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\r
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U) \r
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */\r
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR_Pos (0U) \r
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR_Pos (4U) \r
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR_Pos (0U) \r
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR_Pos (0U) \r
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR_Pos (4U) \r
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR_Pos (0U) \r
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR_Pos (0U) \r
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR_Pos (16U) \r
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */\r
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR_Pos (4U) \r
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR_Pos (20U) \r
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */\r
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR_Pos (0U) \r
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR_Pos (8U) \r
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */\r
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR_Pos (0U) \r
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR_Pos (0U) \r
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1_Pos (13U) \r
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */\r
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2_Pos (29U) \r
+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */\r
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital Filter for Sigma Delta Modulators */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** DFSDM channel configuration registers ********************/\r
+\r
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/\r
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U) \r
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */\r
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */\r
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U) \r
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */\r
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */\r
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U) \r
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */\r
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U) \r
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */\r
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */\r
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */\r
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */\r
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U) \r
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */\r
+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */\r
+#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */\r
+#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */\r
+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U) \r
+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */\r
+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */\r
+#define DFSDM_CHCFGR1_CHEN_Pos (7U) \r
+#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */\r
+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */\r
+#define DFSDM_CHCFGR1_CKABEN_Pos (6U) \r
+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */\r
+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SCDEN_Pos (5U) \r
+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */\r
+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U) \r
+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */\r
+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */\r
+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */\r
+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */\r
+#define DFSDM_CHCFGR1_SITP_Pos (0U) \r
+#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */\r
+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */\r
+#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */\r
+#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */\r
+\r
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/\r
+#define DFSDM_CHCFGR2_OFFSET_Pos (8U) \r
+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\r
+#define DFSDM_CHCFGR2_DTRBS_Pos (3U) \r
+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */\r
+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */\r
+\r
+/****************** Bit definition for DFSDM_CHAWSCDR register *****************/\r
+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U) \r
+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */\r
+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\r
+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */\r
+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */\r
+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U) \r
+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */\r
+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\r
+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U) \r
+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */\r
+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\r
+#define DFSDM_CHAWSCDR_SCDT_Pos (0U) \r
+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */\r
+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */\r
+\r
+/**************** Bit definition for DFSDM_CHWDATR register *******************/\r
+#define DFSDM_CHWDATR_WDATA_Pos (0U) \r
+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */\r
+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */\r
+\r
+/**************** Bit definition for DFSDM_CHDATINR register *****************/\r
+#define DFSDM_CHDATINR_INDAT0_Pos (0U) \r
+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\r
+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\r
+#define DFSDM_CHDATINR_INDAT1_Pos (16U) \r
+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\r
+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */\r
+\r
+/************************ DFSDM module registers ****************************/\r
+\r
+/******************** Bit definition for DFSDM_FLTCR1 register *******************/\r
+#define DFSDM_FLTCR1_AWFSEL_Pos (30U) \r
+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */\r
+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */\r
+#define DFSDM_FLTCR1_FAST_Pos (29U) \r
+#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */\r
+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */\r
+#define DFSDM_FLTCR1_RCH_Pos (24U) \r
+#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */\r
+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */\r
+#define DFSDM_FLTCR1_RDMAEN_Pos (21U) \r
+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */\r
+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */\r
+#define DFSDM_FLTCR1_RSYNC_Pos (19U) \r
+#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */\r
+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */\r
+#define DFSDM_FLTCR1_RCONT_Pos (18U) \r
+#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */\r
+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */\r
+#define DFSDM_FLTCR1_RSWSTART_Pos (17U) \r
+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */\r
+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */\r
+#define DFSDM_FLTCR1_JEXTEN_Pos (13U) \r
+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */\r
+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\r
+#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */\r
+#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */\r
+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U) \r
+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */\r
+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */\r
+#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */\r
+#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */\r
+#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */\r
+#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */\r
+#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */\r
+#define DFSDM_FLTCR1_JDMAEN_Pos (5U) \r
+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */\r
+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */\r
+#define DFSDM_FLTCR1_JSCAN_Pos (4U) \r
+#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */\r
+#define DFSDM_FLTCR1_JSYNC_Pos (3U) \r
+#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */\r
+#define DFSDM_FLTCR1_JSWSTART_Pos (1U) \r
+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */\r
+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */\r
+#define DFSDM_FLTCR1_DFEN_Pos (0U) \r
+#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */\r
+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */\r
+\r
+/******************** Bit definition for DFSDM_FLTCR2 register *******************/\r
+#define DFSDM_FLTCR2_AWDCH_Pos (16U) \r
+#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */\r
+#define DFSDM_FLTCR2_EXCH_Pos (8U) \r
+#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */\r
+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */\r
+#define DFSDM_FLTCR2_CKABIE_Pos (6U) \r
+#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */\r
+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */\r
+#define DFSDM_FLTCR2_SCDIE_Pos (5U) \r
+#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */\r
+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */\r
+#define DFSDM_FLTCR2_AWDIE_Pos (4U) \r
+#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */\r
+#define DFSDM_FLTCR2_ROVRIE_Pos (3U) \r
+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_JOVRIE_Pos (2U) \r
+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */\r
+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */\r
+#define DFSDM_FLTCR2_REOCIE_Pos (1U) \r
+#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */\r
+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */\r
+#define DFSDM_FLTCR2_JEOCIE_Pos (0U) \r
+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */\r
+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */\r
+\r
+/******************** Bit definition for DFSDM_FLTISR register *******************/\r
+#define DFSDM_FLTISR_SCDF_Pos (24U) \r
+#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */\r
+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */\r
+#define DFSDM_FLTISR_CKABF_Pos (16U) \r
+#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */\r
+#define DFSDM_FLTISR_RCIP_Pos (14U) \r
+#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */\r
+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */\r
+#define DFSDM_FLTISR_JCIP_Pos (13U) \r
+#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */\r
+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */\r
+#define DFSDM_FLTISR_AWDF_Pos (4U) \r
+#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */\r
+#define DFSDM_FLTISR_ROVRF_Pos (3U) \r
+#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */\r
+#define DFSDM_FLTISR_JOVRF_Pos (2U) \r
+#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */\r
+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */\r
+#define DFSDM_FLTISR_REOCF_Pos (1U) \r
+#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */\r
+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */\r
+#define DFSDM_FLTISR_JEOCF_Pos (0U) \r
+#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */\r
+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */\r
+\r
+/******************** Bit definition for DFSDM_FLTICR register *******************/\r
+#define DFSDM_FLTICR_CLRSCDF_Pos (24U) \r
+#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */\r
+#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\r
+#define DFSDM_FLTICR_CLRCKABF_Pos (16U) \r
+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */\r
+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */\r
+#define DFSDM_FLTICR_CLRROVRF_Pos (3U) \r
+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */\r
+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */\r
+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U) \r
+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */\r
+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */\r
+\r
+/******************* Bit definition for DFSDM_FLTJCHGR register ******************/\r
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U) \r
+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */\r
+\r
+/******************** Bit definition for DFSDM_FLTFCR register *******************/\r
+#define DFSDM_FLTFCR_FORD_Pos (29U) \r
+#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */\r
+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */\r
+#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */\r
+#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */\r
+#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */\r
+#define DFSDM_FLTFCR_FOSR_Pos (16U) \r
+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */\r
+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\r
+#define DFSDM_FLTFCR_IOSR_Pos (0U) \r
+#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\r
+\r
+/****************** Bit definition for DFSDM_FLTJDATAR register *****************/\r
+#define DFSDM_FLTJDATAR_JDATA_Pos (8U) \r
+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */\r
+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U) \r
+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */\r
+\r
+/****************** Bit definition for DFSDM_FLTRDATAR register *****************/\r
+#define DFSDM_FLTRDATAR_RDATA_Pos (8U) \r
+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */\r
+#define DFSDM_FLTRDATAR_RPEND_Pos (4U) \r
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */\r
+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */\r
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U) \r
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWHTR register ******************/\r
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U) \r
+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */\r
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U) \r
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */\r
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWLTR register ******************/\r
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U) \r
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */\r
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U) \r
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */\r
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWSR register ******************/\r
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U) \r
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */\r
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\r
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U) \r
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\r
+\r
+/****************** Bit definition for DFSDM_FLTAWCFR register *****************/\r
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U) \r
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\r
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\r
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U) \r
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\r
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\r
+\r
+/****************** Bit definition for DFSDM_FLTEXMAX register ******************/\r
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U) \r
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */\r
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U) \r
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\r
+\r
+/****************** Bit definition for DFSDM_FLTEXMIN register ******************/\r
+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U) \r
+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\r
+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */\r
+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U) \r
+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */\r
+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */\r
+\r
+/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/\r
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U) \r
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\r
+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\r
+\r
+/* Legacy Defines */\r
+#define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos \r
+#define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk\r
+#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DCMI */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DCMI_CR register ******************/\r
+#define DCMI_CR_CAPTURE_Pos (0U) \r
+#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */\r
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk \r
+#define DCMI_CR_CM_Pos (1U) \r
+#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */\r
+#define DCMI_CR_CM DCMI_CR_CM_Msk \r
+#define DCMI_CR_CROP_Pos (2U) \r
+#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */\r
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk \r
+#define DCMI_CR_JPEG_Pos (3U) \r
+#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */\r
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk \r
+#define DCMI_CR_ESS_Pos (4U) \r
+#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */\r
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk \r
+#define DCMI_CR_PCKPOL_Pos (5U) \r
+#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */\r
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk \r
+#define DCMI_CR_HSPOL_Pos (6U) \r
+#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */\r
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk \r
+#define DCMI_CR_VSPOL_Pos (7U) \r
+#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */\r
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk \r
+#define DCMI_CR_FCRC_0 0x00000100U \r
+#define DCMI_CR_FCRC_1 0x00000200U \r
+#define DCMI_CR_EDM_0 0x00000400U \r
+#define DCMI_CR_EDM_1 0x00000800U \r
+#define DCMI_CR_CRE_Pos (12U) \r
+#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */\r
+#define DCMI_CR_CRE DCMI_CR_CRE_Msk \r
+#define DCMI_CR_ENABLE_Pos (14U) \r
+#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */\r
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk \r
+#define DCMI_CR_BSM_Pos (16U) \r
+#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */\r
+#define DCMI_CR_BSM DCMI_CR_BSM_Msk \r
+#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */\r
+#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */\r
+#define DCMI_CR_OEBS_Pos (18U) \r
+#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */\r
+#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk \r
+#define DCMI_CR_LSM_Pos (19U) \r
+#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */\r
+#define DCMI_CR_LSM DCMI_CR_LSM_Msk \r
+#define DCMI_CR_OELS_Pos (20U) \r
+#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */\r
+#define DCMI_CR_OELS DCMI_CR_OELS_Msk \r
+\r
+/******************** Bits definition for DCMI_SR register ******************/\r
+#define DCMI_SR_HSYNC_Pos (0U) \r
+#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */\r
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk \r
+#define DCMI_SR_VSYNC_Pos (1U) \r
+#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */\r
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk \r
+#define DCMI_SR_FNE_Pos (2U) \r
+#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */\r
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk \r
+\r
+/******************** Bits definition for DCMI_RIS register ****************/\r
+#define DCMI_RIS_FRAME_RIS_Pos (0U) \r
+#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */\r
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk \r
+#define DCMI_RIS_OVR_RIS_Pos (1U) \r
+#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */\r
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk \r
+#define DCMI_RIS_ERR_RIS_Pos (2U) \r
+#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */\r
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk \r
+#define DCMI_RIS_VSYNC_RIS_Pos (3U) \r
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */\r
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk \r
+#define DCMI_RIS_LINE_RIS_Pos (4U) \r
+#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */\r
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk \r
+\r
+/* Legacy defines */\r
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS\r
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS\r
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS\r
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS\r
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS\r
+\r
+/******************** Bits definition for DCMI_IER register *****************/\r
+#define DCMI_IER_FRAME_IE_Pos (0U) \r
+#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */\r
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk \r
+#define DCMI_IER_OVR_IE_Pos (1U) \r
+#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */\r
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk \r
+#define DCMI_IER_ERR_IE_Pos (2U) \r
+#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */\r
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk \r
+#define DCMI_IER_VSYNC_IE_Pos (3U) \r
+#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */\r
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk \r
+#define DCMI_IER_LINE_IE_Pos (4U) \r
+#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */\r
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk \r
+\r
+\r
+/******************** Bits definition for DCMI_MIS register *****************/\r
+#define DCMI_MIS_FRAME_MIS_Pos (0U) \r
+#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */\r
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk \r
+#define DCMI_MIS_OVR_MIS_Pos (1U) \r
+#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */\r
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk \r
+#define DCMI_MIS_ERR_MIS_Pos (2U) \r
+#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */\r
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk \r
+#define DCMI_MIS_VSYNC_MIS_Pos (3U) \r
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */\r
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk \r
+#define DCMI_MIS_LINE_MIS_Pos (4U) \r
+#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */\r
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk \r
+\r
+\r
+/******************** Bits definition for DCMI_ICR register *****************/\r
+#define DCMI_ICR_FRAME_ISC_Pos (0U) \r
+#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */\r
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk \r
+#define DCMI_ICR_OVR_ISC_Pos (1U) \r
+#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */\r
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk \r
+#define DCMI_ICR_ERR_ISC_Pos (2U) \r
+#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */\r
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk \r
+#define DCMI_ICR_VSYNC_ISC_Pos (3U) \r
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */\r
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk \r
+#define DCMI_ICR_LINE_ISC_Pos (4U) \r
+#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */\r
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk \r
+\r
+\r
+/******************** Bits definition for DCMI_ESCR register ******************/\r
+#define DCMI_ESCR_FSC_Pos (0U) \r
+#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */\r
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk \r
+#define DCMI_ESCR_LSC_Pos (8U) \r
+#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */\r
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk \r
+#define DCMI_ESCR_LEC_Pos (16U) \r
+#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */\r
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk \r
+#define DCMI_ESCR_FEC_Pos (24U) \r
+#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */\r
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk \r
+\r
+/******************** Bits definition for DCMI_ESUR register ******************/\r
+#define DCMI_ESUR_FSU_Pos (0U) \r
+#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */\r
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk \r
+#define DCMI_ESUR_LSU_Pos (8U) \r
+#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */\r
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk \r
+#define DCMI_ESUR_LEU_Pos (16U) \r
+#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */\r
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk \r
+#define DCMI_ESUR_FEU_Pos (24U) \r
+#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */\r
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk \r
+\r
+/******************** Bits definition for DCMI_CWSTRT register ******************/\r
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U) \r
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */\r
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk \r
+#define DCMI_CWSTRT_VST_Pos (16U) \r
+#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */\r
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk \r
+\r
+/******************** Bits definition for DCMI_CWSIZE register ******************/\r
+#define DCMI_CWSIZE_CAPCNT_Pos (0U) \r
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */\r
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk \r
+#define DCMI_CWSIZE_VLINE_Pos (16U) \r
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */\r
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk \r
+\r
+/******************** Bits definition for DCMI_DR register ******************/\r
+#define DCMI_DR_BYTE0_Pos (0U) \r
+#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */\r
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk \r
+#define DCMI_DR_BYTE1_Pos (8U) \r
+#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */\r
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk \r
+#define DCMI_DR_BYTE2_Pos (16U) \r
+#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */\r
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk \r
+#define DCMI_DR_BYTE3_Pos (24U) \r
+#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */\r
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/\r
+#define DMA_SxCR_CHSEL_Pos (25U) \r
+#define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */\r
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk \r
+#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */\r
+#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */\r
+#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */\r
+#define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */\r
+#define DMA_SxCR_MBURST_Pos (23U) \r
+#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */\r
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk \r
+#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */\r
+#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */\r
+#define DMA_SxCR_PBURST_Pos (21U) \r
+#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */\r
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk \r
+#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */\r
+#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */\r
+#define DMA_SxCR_CT_Pos (19U) \r
+#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */\r
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk \r
+#define DMA_SxCR_DBM_Pos (18U) \r
+#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */\r
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk \r
+#define DMA_SxCR_PL_Pos (16U) \r
+#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */\r
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk \r
+#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */\r
+#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */\r
+#define DMA_SxCR_PINCOS_Pos (15U) \r
+#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */\r
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk \r
+#define DMA_SxCR_MSIZE_Pos (13U) \r
+#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */\r
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk \r
+#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */\r
+#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */\r
+#define DMA_SxCR_PSIZE_Pos (11U) \r
+#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */\r
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk \r
+#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */\r
+#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */\r
+#define DMA_SxCR_MINC_Pos (10U) \r
+#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */\r
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk \r
+#define DMA_SxCR_PINC_Pos (9U) \r
+#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */\r
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk \r
+#define DMA_SxCR_CIRC_Pos (8U) \r
+#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */\r
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk \r
+#define DMA_SxCR_DIR_Pos (6U) \r
+#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */\r
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk \r
+#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */\r
+#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */\r
+#define DMA_SxCR_PFCTRL_Pos (5U) \r
+#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */\r
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk \r
+#define DMA_SxCR_TCIE_Pos (4U) \r
+#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */\r
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk \r
+#define DMA_SxCR_HTIE_Pos (3U) \r
+#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */\r
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk \r
+#define DMA_SxCR_TEIE_Pos (2U) \r
+#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */\r
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk \r
+#define DMA_SxCR_DMEIE_Pos (1U) \r
+#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */\r
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk \r
+#define DMA_SxCR_EN_Pos (0U) \r
+#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */\r
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk \r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT_Pos (0U) \r
+#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_SxNDT DMA_SxNDT_Msk \r
+#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */\r
+#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */\r
+#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */\r
+#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */\r
+#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */\r
+#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */\r
+#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */\r
+#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */\r
+#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */\r
+#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */\r
+#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */\r
+#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */\r
+#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */\r
+#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */\r
+#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */\r
+#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/\r
+#define DMA_SxFCR_FEIE_Pos (7U) \r
+#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */\r
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk \r
+#define DMA_SxFCR_FS_Pos (3U) \r
+#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */\r
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk \r
+#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */\r
+#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */\r
+#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */\r
+#define DMA_SxFCR_DMDIS_Pos (2U) \r
+#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */\r
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk \r
+#define DMA_SxFCR_FTH_Pos (0U) \r
+#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */\r
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk \r
+#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */\r
+#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/\r
+#define DMA_LISR_TCIF3_Pos (27U) \r
+#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */\r
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk \r
+#define DMA_LISR_HTIF3_Pos (26U) \r
+#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */\r
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk \r
+#define DMA_LISR_TEIF3_Pos (25U) \r
+#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */\r
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk \r
+#define DMA_LISR_DMEIF3_Pos (24U) \r
+#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */\r
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk \r
+#define DMA_LISR_FEIF3_Pos (22U) \r
+#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */\r
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk \r
+#define DMA_LISR_TCIF2_Pos (21U) \r
+#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */\r
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk \r
+#define DMA_LISR_HTIF2_Pos (20U) \r
+#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */\r
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk \r
+#define DMA_LISR_TEIF2_Pos (19U) \r
+#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */\r
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk \r
+#define DMA_LISR_DMEIF2_Pos (18U) \r
+#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */\r
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk \r
+#define DMA_LISR_FEIF2_Pos (16U) \r
+#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */\r
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk \r
+#define DMA_LISR_TCIF1_Pos (11U) \r
+#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */\r
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk \r
+#define DMA_LISR_HTIF1_Pos (10U) \r
+#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */\r
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk \r
+#define DMA_LISR_TEIF1_Pos (9U) \r
+#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */\r
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk \r
+#define DMA_LISR_DMEIF1_Pos (8U) \r
+#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */\r
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk \r
+#define DMA_LISR_FEIF1_Pos (6U) \r
+#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */\r
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk \r
+#define DMA_LISR_TCIF0_Pos (5U) \r
+#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */\r
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk \r
+#define DMA_LISR_HTIF0_Pos (4U) \r
+#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */\r
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk \r
+#define DMA_LISR_TEIF0_Pos (3U) \r
+#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */\r
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk \r
+#define DMA_LISR_DMEIF0_Pos (2U) \r
+#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */\r
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk \r
+#define DMA_LISR_FEIF0_Pos (0U) \r
+#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */\r
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk \r
+\r
+/******************** Bits definition for DMA_HISR register *****************/\r
+#define DMA_HISR_TCIF7_Pos (27U) \r
+#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk \r
+#define DMA_HISR_HTIF7_Pos (26U) \r
+#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk \r
+#define DMA_HISR_TEIF7_Pos (25U) \r
+#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk \r
+#define DMA_HISR_DMEIF7_Pos (24U) \r
+#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk \r
+#define DMA_HISR_FEIF7_Pos (22U) \r
+#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */\r
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk \r
+#define DMA_HISR_TCIF6_Pos (21U) \r
+#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk \r
+#define DMA_HISR_HTIF6_Pos (20U) \r
+#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk \r
+#define DMA_HISR_TEIF6_Pos (19U) \r
+#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */\r
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk \r
+#define DMA_HISR_DMEIF6_Pos (18U) \r
+#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */\r
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk \r
+#define DMA_HISR_FEIF6_Pos (16U) \r
+#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */\r
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk \r
+#define DMA_HISR_TCIF5_Pos (11U) \r
+#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */\r
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk \r
+#define DMA_HISR_HTIF5_Pos (10U) \r
+#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */\r
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk \r
+#define DMA_HISR_TEIF5_Pos (9U) \r
+#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */\r
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk \r
+#define DMA_HISR_DMEIF5_Pos (8U) \r
+#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */\r
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk \r
+#define DMA_HISR_FEIF5_Pos (6U) \r
+#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */\r
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk \r
+#define DMA_HISR_TCIF4_Pos (5U) \r
+#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */\r
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk \r
+#define DMA_HISR_HTIF4_Pos (4U) \r
+#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */\r
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk \r
+#define DMA_HISR_TEIF4_Pos (3U) \r
+#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */\r
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk \r
+#define DMA_HISR_DMEIF4_Pos (2U) \r
+#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */\r
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk \r
+#define DMA_HISR_FEIF4_Pos (0U) \r
+#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */\r
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk \r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/\r
+#define DMA_LIFCR_CTCIF3_Pos (27U) \r
+#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */\r
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk \r
+#define DMA_LIFCR_CHTIF3_Pos (26U) \r
+#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */\r
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk \r
+#define DMA_LIFCR_CTEIF3_Pos (25U) \r
+#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */\r
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk \r
+#define DMA_LIFCR_CDMEIF3_Pos (24U) \r
+#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */\r
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk \r
+#define DMA_LIFCR_CFEIF3_Pos (22U) \r
+#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */\r
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk \r
+#define DMA_LIFCR_CTCIF2_Pos (21U) \r
+#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */\r
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk \r
+#define DMA_LIFCR_CHTIF2_Pos (20U) \r
+#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */\r
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk \r
+#define DMA_LIFCR_CTEIF2_Pos (19U) \r
+#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */\r
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk \r
+#define DMA_LIFCR_CDMEIF2_Pos (18U) \r
+#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */\r
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk \r
+#define DMA_LIFCR_CFEIF2_Pos (16U) \r
+#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */\r
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk \r
+#define DMA_LIFCR_CTCIF1_Pos (11U) \r
+#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */\r
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk \r
+#define DMA_LIFCR_CHTIF1_Pos (10U) \r
+#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */\r
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk \r
+#define DMA_LIFCR_CTEIF1_Pos (9U) \r
+#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */\r
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk \r
+#define DMA_LIFCR_CDMEIF1_Pos (8U) \r
+#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */\r
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk \r
+#define DMA_LIFCR_CFEIF1_Pos (6U) \r
+#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */\r
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk \r
+#define DMA_LIFCR_CTCIF0_Pos (5U) \r
+#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */\r
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk \r
+#define DMA_LIFCR_CHTIF0_Pos (4U) \r
+#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */\r
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk \r
+#define DMA_LIFCR_CTEIF0_Pos (3U) \r
+#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */\r
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk \r
+#define DMA_LIFCR_CDMEIF0_Pos (2U) \r
+#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */\r
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk \r
+#define DMA_LIFCR_CFEIF0_Pos (0U) \r
+#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */\r
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk \r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/\r
+#define DMA_HIFCR_CTCIF7_Pos (27U) \r
+#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk \r
+#define DMA_HIFCR_CHTIF7_Pos (26U) \r
+#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk \r
+#define DMA_HIFCR_CTEIF7_Pos (25U) \r
+#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk \r
+#define DMA_HIFCR_CDMEIF7_Pos (24U) \r
+#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk \r
+#define DMA_HIFCR_CFEIF7_Pos (22U) \r
+#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */\r
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk \r
+#define DMA_HIFCR_CTCIF6_Pos (21U) \r
+#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk \r
+#define DMA_HIFCR_CHTIF6_Pos (20U) \r
+#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk \r
+#define DMA_HIFCR_CTEIF6_Pos (19U) \r
+#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */\r
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk \r
+#define DMA_HIFCR_CDMEIF6_Pos (18U) \r
+#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */\r
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk \r
+#define DMA_HIFCR_CFEIF6_Pos (16U) \r
+#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */\r
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk \r
+#define DMA_HIFCR_CTCIF5_Pos (11U) \r
+#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */\r
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk \r
+#define DMA_HIFCR_CHTIF5_Pos (10U) \r
+#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */\r
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk \r
+#define DMA_HIFCR_CTEIF5_Pos (9U) \r
+#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */\r
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk \r
+#define DMA_HIFCR_CDMEIF5_Pos (8U) \r
+#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */\r
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk \r
+#define DMA_HIFCR_CFEIF5_Pos (6U) \r
+#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */\r
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk \r
+#define DMA_HIFCR_CTCIF4_Pos (5U) \r
+#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */\r
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk \r
+#define DMA_HIFCR_CHTIF4_Pos (4U) \r
+#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */\r
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk \r
+#define DMA_HIFCR_CTEIF4_Pos (3U) \r
+#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */\r
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk \r
+#define DMA_HIFCR_CDMEIF4_Pos (2U) \r
+#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */\r
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk \r
+#define DMA_HIFCR_CFEIF4_Pos (0U) \r
+#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */\r
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk \r
+\r
+/****************** Bit definition for DMA_SxPAR register ********************/\r
+#define DMA_SxPAR_PA_Pos (0U) \r
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_SxM0AR register ********************/\r
+#define DMA_SxM0AR_M0A_Pos (0U) \r
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_SxM1AR register ********************/\r
+#define DMA_SxM1AR_M1A_Pos (0U) \r
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* AHB Master DMA2D Controller (DMA2D) */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)\r
+ */\r
+#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT\r
+/******************** Bit definition for DMA2D_CR register ******************/\r
+\r
+#define DMA2D_CR_START_Pos (0U) \r
+#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */\r
+#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */\r
+#define DMA2D_CR_SUSP_Pos (1U) \r
+#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */\r
+#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */\r
+#define DMA2D_CR_ABORT_Pos (2U) \r
+#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */\r
+#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */\r
+#define DMA2D_CR_TEIE_Pos (8U) \r
+#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */\r
+#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */\r
+#define DMA2D_CR_TCIE_Pos (9U) \r
+#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */\r
+#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_TWIE_Pos (10U) \r
+#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */\r
+#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */\r
+#define DMA2D_CR_CAEIE_Pos (11U) \r
+#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */\r
+#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */\r
+#define DMA2D_CR_CTCIE_Pos (12U) \r
+#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */\r
+#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_CEIE_Pos (13U) \r
+#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */\r
+#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */\r
+#define DMA2D_CR_MODE_Pos (16U) \r
+#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */\r
+#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */\r
+#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */\r
+#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */\r
+\r
+/******************** Bit definition for DMA2D_ISR register *****************/\r
+\r
+#define DMA2D_ISR_TEIF_Pos (0U) \r
+#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */\r
+#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */\r
+#define DMA2D_ISR_TCIF_Pos (1U) \r
+#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */\r
+#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_TWIF_Pos (2U) \r
+#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */\r
+#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_ISR_CAEIF_Pos (3U) \r
+#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */\r
+#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */\r
+#define DMA2D_ISR_CTCIF_Pos (4U) \r
+#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */\r
+#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_CEIF_Pos (5U) \r
+#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */\r
+#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_IFCR register ****************/\r
+\r
+#define DMA2D_IFCR_CTEIF_Pos (0U) \r
+#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */\r
+#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFCR_CTCIF_Pos (1U) \r
+#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */\r
+#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFCR_CTWIF_Pos (2U) \r
+#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */\r
+#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFCR_CAECIF_Pos (3U) \r
+#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */\r
+#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFCR_CCTCIF_Pos (4U) \r
+#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */\r
+#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFCR_CCEIF_Pos (5U) \r
+#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */\r
+#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/* Legacy defines */\r
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_FGMAR register ***************/\r
+\r
+#define DMA2D_FGMAR_MA_Pos (0U) \r
+#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_FGOR register ****************/\r
+\r
+#define DMA2D_FGOR_LO_Pos (0U) \r
+#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */\r
+#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_BGMAR register ***************/\r
+\r
+#define DMA2D_BGMAR_MA_Pos (0U) \r
+#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGOR register ****************/\r
+\r
+#define DMA2D_BGOR_LO_Pos (0U) \r
+#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */\r
+#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_FGPFCCR register *************/\r
+\r
+#define DMA2D_FGPFCCR_CM_Pos (0U) \r
+#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */\r
+#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */\r
+#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */\r
+#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */\r
+#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */\r
+#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */\r
+#define DMA2D_FGPFCCR_CCM_Pos (4U) \r
+#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */\r
+#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */\r
+#define DMA2D_FGPFCCR_START_Pos (5U) \r
+#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */\r
+#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */\r
+#define DMA2D_FGPFCCR_CS_Pos (8U) \r
+#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */\r
+#define DMA2D_FGPFCCR_AM_Pos (16U) \r
+#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */\r
+#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */\r
+#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */\r
+#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */\r
+#define DMA2D_FGPFCCR_AI_Pos (20U) \r
+#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */\r
+#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */\r
+#define DMA2D_FGPFCCR_RBS_Pos (21U) \r
+#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */\r
+#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */\r
+#define DMA2D_FGPFCCR_ALPHA_Pos (24U) \r
+#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */\r
+#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_FGCOLR register **************/\r
+\r
+#define DMA2D_FGCOLR_BLUE_Pos (0U) \r
+#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */\r
+#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */\r
+#define DMA2D_FGCOLR_GREEN_Pos (8U) \r
+#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */\r
+#define DMA2D_FGCOLR_RED_Pos (16U) \r
+#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */\r
+#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */\r
+\r
+/******************** Bit definition for DMA2D_BGPFCCR register *************/\r
+\r
+#define DMA2D_BGPFCCR_CM_Pos (0U) \r
+#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */\r
+#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */\r
+#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */\r
+#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */\r
+#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */\r
+#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */\r
+#define DMA2D_BGPFCCR_CCM_Pos (4U) \r
+#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */\r
+#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */\r
+#define DMA2D_BGPFCCR_START_Pos (5U) \r
+#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */\r
+#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */\r
+#define DMA2D_BGPFCCR_CS_Pos (8U) \r
+#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */\r
+#define DMA2D_BGPFCCR_AM_Pos (16U) \r
+#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */\r
+#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */\r
+#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */\r
+#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */\r
+#define DMA2D_BGPFCCR_AI_Pos (20U) \r
+#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */\r
+#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */\r
+#define DMA2D_BGPFCCR_RBS_Pos (21U) \r
+#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */\r
+#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */\r
+#define DMA2D_BGPFCCR_ALPHA_Pos (24U) \r
+#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */\r
+#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_BGCOLR register **************/\r
+\r
+#define DMA2D_BGCOLR_BLUE_Pos (0U) \r
+#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */\r
+#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */\r
+#define DMA2D_BGCOLR_GREEN_Pos (8U) \r
+#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */\r
+#define DMA2D_BGCOLR_RED_Pos (16U) \r
+#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */\r
+#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */\r
+\r
+/******************** Bit definition for DMA2D_FGCMAR register **************/\r
+\r
+#define DMA2D_FGCMAR_MA_Pos (0U) \r
+#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGCMAR register **************/\r
+\r
+#define DMA2D_BGCMAR_MA_Pos (0U) \r
+#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OPFCCR register **************/\r
+\r
+#define DMA2D_OPFCCR_CM_Pos (0U) \r
+#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */\r
+#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */\r
+#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */\r
+#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */\r
+#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */\r
+#define DMA2D_OPFCCR_AI_Pos (20U) \r
+#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */\r
+#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */\r
+#define DMA2D_OPFCCR_RBS_Pos (21U) \r
+#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */\r
+#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */\r
+\r
+/******************** Bit definition for DMA2D_OCOLR register ***************/\r
+\r
+/*!<Mode_ARGB8888/RGB888 */\r
+\r
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_RGB565 */\r
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */\r
+\r
+/*!<Mode_ARGB1555 */\r
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_ARGB4444 */\r
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */\r
+\r
+/******************** Bit definition for DMA2D_OMAR register ****************/\r
+\r
+#define DMA2D_OMAR_MA_Pos (0U) \r
+#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OOR register *****************/\r
+\r
+#define DMA2D_OOR_LO_Pos (0U) \r
+#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */\r
+#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_NLR register *****************/\r
+\r
+#define DMA2D_NLR_NL_Pos (0U) \r
+#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */\r
+#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */\r
+#define DMA2D_NLR_PL_Pos (16U) \r
+#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */\r
+#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */\r
+\r
+/******************** Bit definition for DMA2D_LWR register *****************/\r
+\r
+#define DMA2D_LWR_LW_Pos (0U) \r
+#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */\r
+#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */\r
+\r
+/******************** Bit definition for DMA2D_AMTCR register ***************/\r
+\r
+#define DMA2D_AMTCR_EN_Pos (0U) \r
+#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */\r
+#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */\r
+#define DMA2D_AMTCR_DT_Pos (8U) \r
+#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */\r
+#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */\r
+\r
+\r
+/******************** Bit definition for DMA2D_FGCLUT register **************/\r
+\r
+/******************** Bit definition for DMA2D_BGCLUT register **************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0_Pos (0U) \r
+#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1_Pos (1U) \r
+#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2_Pos (2U) \r
+#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3_Pos (3U) \r
+#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4_Pos (4U) \r
+#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5_Pos (5U) \r
+#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6_Pos (6U) \r
+#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7_Pos (7U) \r
+#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8_Pos (8U) \r
+#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9_Pos (9U) \r
+#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10_Pos (10U) \r
+#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11_Pos (11U) \r
+#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12_Pos (12U) \r
+#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13_Pos (13U) \r
+#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14_Pos (14U) \r
+#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15_Pos (15U) \r
+#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16_Pos (16U) \r
+#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17_Pos (17U) \r
+#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18_Pos (18U) \r
+#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19_Pos (19U) \r
+#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20_Pos (20U) \r
+#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21_Pos (21U) \r
+#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22_Pos (22U) \r
+#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23_Pos (23U) \r
+#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */\r
+#define EXTI_IMR_MR24_Pos (24U) \r
+#define EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */\r
+#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */\r
+\r
+/* Reference Defines */\r
+#define EXTI_IMR_IM0 EXTI_IMR_MR0\r
+#define EXTI_IMR_IM1 EXTI_IMR_MR1\r
+#define EXTI_IMR_IM2 EXTI_IMR_MR2\r
+#define EXTI_IMR_IM3 EXTI_IMR_MR3\r
+#define EXTI_IMR_IM4 EXTI_IMR_MR4\r
+#define EXTI_IMR_IM5 EXTI_IMR_MR5\r
+#define EXTI_IMR_IM6 EXTI_IMR_MR6\r
+#define EXTI_IMR_IM7 EXTI_IMR_MR7\r
+#define EXTI_IMR_IM8 EXTI_IMR_MR8\r
+#define EXTI_IMR_IM9 EXTI_IMR_MR9\r
+#define EXTI_IMR_IM10 EXTI_IMR_MR10\r
+#define EXTI_IMR_IM11 EXTI_IMR_MR11\r
+#define EXTI_IMR_IM12 EXTI_IMR_MR12\r
+#define EXTI_IMR_IM13 EXTI_IMR_MR13\r
+#define EXTI_IMR_IM14 EXTI_IMR_MR14\r
+#define EXTI_IMR_IM15 EXTI_IMR_MR15\r
+#define EXTI_IMR_IM16 EXTI_IMR_MR16\r
+#define EXTI_IMR_IM17 EXTI_IMR_MR17\r
+#define EXTI_IMR_IM18 EXTI_IMR_MR18\r
+#define EXTI_IMR_IM19 EXTI_IMR_MR19\r
+#define EXTI_IMR_IM20 EXTI_IMR_MR20\r
+#define EXTI_IMR_IM21 EXTI_IMR_MR21\r
+#define EXTI_IMR_IM22 EXTI_IMR_MR22\r
+#define EXTI_IMR_IM23 EXTI_IMR_MR23\r
+#define EXTI_IMR_IM24 EXTI_IMR_MR24\r
+\r
+#define EXTI_IMR_IM_Pos (0U) \r
+#define EXTI_IMR_IM_Msk (0x1FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x01FFFFFF */\r
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0_Pos (0U) \r
+#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1_Pos (1U) \r
+#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2_Pos (2U) \r
+#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3_Pos (3U) \r
+#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4_Pos (4U) \r
+#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5_Pos (5U) \r
+#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6_Pos (6U) \r
+#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7_Pos (7U) \r
+#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8_Pos (8U) \r
+#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9_Pos (9U) \r
+#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10_Pos (10U) \r
+#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11_Pos (11U) \r
+#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12_Pos (12U) \r
+#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13_Pos (13U) \r
+#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14_Pos (14U) \r
+#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15_Pos (15U) \r
+#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16_Pos (16U) \r
+#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17_Pos (17U) \r
+#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18_Pos (18U) \r
+#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19_Pos (19U) \r
+#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20_Pos (20U) \r
+#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21_Pos (21U) \r
+#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22_Pos (22U) \r
+#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23_Pos (23U) \r
+#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */\r
+#define EXTI_EMR_MR24_Pos (24U) \r
+#define EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */\r
+#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */\r
+\r
+/* Reference Defines */\r
+#define EXTI_EMR_EM0 EXTI_EMR_MR0\r
+#define EXTI_EMR_EM1 EXTI_EMR_MR1\r
+#define EXTI_EMR_EM2 EXTI_EMR_MR2\r
+#define EXTI_EMR_EM3 EXTI_EMR_MR3\r
+#define EXTI_EMR_EM4 EXTI_EMR_MR4\r
+#define EXTI_EMR_EM5 EXTI_EMR_MR5\r
+#define EXTI_EMR_EM6 EXTI_EMR_MR6\r
+#define EXTI_EMR_EM7 EXTI_EMR_MR7\r
+#define EXTI_EMR_EM8 EXTI_EMR_MR8\r
+#define EXTI_EMR_EM9 EXTI_EMR_MR9\r
+#define EXTI_EMR_EM10 EXTI_EMR_MR10\r
+#define EXTI_EMR_EM11 EXTI_EMR_MR11\r
+#define EXTI_EMR_EM12 EXTI_EMR_MR12\r
+#define EXTI_EMR_EM13 EXTI_EMR_MR13\r
+#define EXTI_EMR_EM14 EXTI_EMR_MR14\r
+#define EXTI_EMR_EM15 EXTI_EMR_MR15\r
+#define EXTI_EMR_EM16 EXTI_EMR_MR16\r
+#define EXTI_EMR_EM17 EXTI_EMR_MR17\r
+#define EXTI_EMR_EM18 EXTI_EMR_MR18\r
+#define EXTI_EMR_EM19 EXTI_EMR_MR19\r
+#define EXTI_EMR_EM20 EXTI_EMR_MR20\r
+#define EXTI_EMR_EM21 EXTI_EMR_MR21\r
+#define EXTI_EMR_EM22 EXTI_EMR_MR22\r
+#define EXTI_EMR_EM23 EXTI_EMR_MR23\r
+#define EXTI_EMR_EM24 EXTI_EMR_MR24\r
+\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0_Pos (0U) \r
+#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1_Pos (1U) \r
+#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2_Pos (2U) \r
+#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3_Pos (3U) \r
+#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4_Pos (4U) \r
+#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5_Pos (5U) \r
+#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6_Pos (6U) \r
+#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7_Pos (7U) \r
+#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8_Pos (8U) \r
+#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9_Pos (9U) \r
+#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10_Pos (10U) \r
+#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11_Pos (11U) \r
+#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12_Pos (12U) \r
+#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13_Pos (13U) \r
+#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14_Pos (14U) \r
+#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15_Pos (15U) \r
+#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16_Pos (16U) \r
+#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17_Pos (17U) \r
+#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18_Pos (18U) \r
+#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19_Pos (19U) \r
+#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20_Pos (20U) \r
+#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21_Pos (21U) \r
+#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22_Pos (22U) \r
+#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */\r
+#define EXTI_RTSR_TR23_Pos (23U) \r
+#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */\r
+#define EXTI_RTSR_TR24_Pos (24U) \r
+#define EXTI_RTSR_TR24_Msk (0x1UL << EXTI_RTSR_TR24_Pos) /*!< 0x01000000 */\r
+#define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk /*!< Rising trigger event configuration bit of line 24 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0_Pos (0U) \r
+#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1_Pos (1U) \r
+#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2_Pos (2U) \r
+#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3_Pos (3U) \r
+#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4_Pos (4U) \r
+#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5_Pos (5U) \r
+#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6_Pos (6U) \r
+#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7_Pos (7U) \r
+#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8_Pos (8U) \r
+#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9_Pos (9U) \r
+#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10_Pos (10U) \r
+#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11_Pos (11U) \r
+#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12_Pos (12U) \r
+#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13_Pos (13U) \r
+#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14_Pos (14U) \r
+#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15_Pos (15U) \r
+#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16_Pos (16U) \r
+#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17_Pos (17U) \r
+#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18_Pos (18U) \r
+#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19_Pos (19U) \r
+#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20_Pos (20U) \r
+#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21_Pos (21U) \r
+#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22_Pos (22U) \r
+#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */\r
+#define EXTI_FTSR_TR23_Pos (23U) \r
+#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */\r
+#define EXTI_FTSR_TR24_Pos (24U) \r
+#define EXTI_FTSR_TR24_Msk (0x1UL << EXTI_FTSR_TR24_Pos) /*!< 0x01000000 */\r
+#define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk /*!< Falling trigger event configuration bit of line 24 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0_Pos (0U) \r
+#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */\r
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1_Pos (1U) \r
+#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */\r
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2_Pos (2U) \r
+#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */\r
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3_Pos (3U) \r
+#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */\r
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4_Pos (4U) \r
+#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */\r
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5_Pos (5U) \r
+#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */\r
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6_Pos (6U) \r
+#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */\r
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7_Pos (7U) \r
+#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */\r
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8_Pos (8U) \r
+#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */\r
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9_Pos (9U) \r
+#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */\r
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10_Pos (10U) \r
+#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */\r
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11_Pos (11U) \r
+#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */\r
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12_Pos (12U) \r
+#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */\r
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13_Pos (13U) \r
+#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */\r
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14_Pos (14U) \r
+#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */\r
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15_Pos (15U) \r
+#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */\r
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16_Pos (16U) \r
+#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */\r
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17_Pos (17U) \r
+#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */\r
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18_Pos (18U) \r
+#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */\r
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19_Pos (19U) \r
+#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */\r
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20_Pos (20U) \r
+#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */\r
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21_Pos (21U) \r
+#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */\r
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22_Pos (22U) \r
+#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */\r
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */\r
+#define EXTI_SWIER_SWIER23_Pos (23U) \r
+#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */\r
+#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */\r
+#define EXTI_SWIER_SWIER24_Pos (24U) \r
+#define EXTI_SWIER_SWIER24_Msk (0x1UL << EXTI_SWIER_SWIER24_Pos) /*!< 0x01000000 */\r
+#define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk /*!< Software Interrupt on line 24 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0_Pos (0U) \r
+#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1_Pos (1U) \r
+#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2_Pos (2U) \r
+#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3_Pos (3U) \r
+#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4_Pos (4U) \r
+#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5_Pos (5U) \r
+#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6_Pos (6U) \r
+#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7_Pos (7U) \r
+#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8_Pos (8U) \r
+#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9_Pos (9U) \r
+#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10_Pos (10U) \r
+#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11_Pos (11U) \r
+#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12_Pos (12U) \r
+#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13_Pos (13U) \r
+#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14_Pos (14U) \r
+#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15_Pos (15U) \r
+#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16_Pos (16U) \r
+#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17_Pos (17U) \r
+#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18_Pos (18U) \r
+#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19_Pos (19U) \r
+#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */\r
+#define EXTI_PR_PR20_Pos (20U) \r
+#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */\r
+#define EXTI_PR_PR21_Pos (21U) \r
+#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */\r
+#define EXTI_PR_PR22_Pos (22U) \r
+#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */\r
+#define EXTI_PR_PR23_Pos (23U) \r
+#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */\r
+#define EXTI_PR_PR24_Pos (24U) \r
+#define EXTI_PR_PR24_Msk (0x1UL << EXTI_PR_PR24_Pos) /*!< 0x01000000 */\r
+#define EXTI_PR_PR24 EXTI_PR_PR24_Msk /*!< Pending bit for line 24 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+* @brief FLASH Total Sectors Number\r
+*/\r
+#define FLASH_SECTOR_TOTAL 24\r
+\r
+/******************* Bits definition for FLASH_ACR register *****************/\r
+#define FLASH_ACR_LATENCY_Pos (0U) \r
+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */\r
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk \r
+#define FLASH_ACR_LATENCY_0WS 0x00000000U \r
+#define FLASH_ACR_LATENCY_1WS 0x00000001U \r
+#define FLASH_ACR_LATENCY_2WS 0x00000002U \r
+#define FLASH_ACR_LATENCY_3WS 0x00000003U \r
+#define FLASH_ACR_LATENCY_4WS 0x00000004U \r
+#define FLASH_ACR_LATENCY_5WS 0x00000005U \r
+#define FLASH_ACR_LATENCY_6WS 0x00000006U \r
+#define FLASH_ACR_LATENCY_7WS 0x00000007U \r
+#define FLASH_ACR_LATENCY_8WS 0x00000008U \r
+#define FLASH_ACR_LATENCY_9WS 0x00000009U \r
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU \r
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU \r
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU \r
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU \r
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU \r
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU \r
+#define FLASH_ACR_PRFTEN_Pos (8U) \r
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */\r
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk \r
+#define FLASH_ACR_ARTEN_Pos (9U) \r
+#define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */\r
+#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk \r
+#define FLASH_ACR_ARTRST_Pos (11U) \r
+#define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */\r
+#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk \r
+\r
+/******************* Bits definition for FLASH_SR register ******************/\r
+#define FLASH_SR_EOP_Pos (0U) \r
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */\r
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk \r
+#define FLASH_SR_OPERR_Pos (1U) \r
+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */\r
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk \r
+#define FLASH_SR_WRPERR_Pos (4U) \r
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */\r
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk \r
+#define FLASH_SR_PGAERR_Pos (5U) \r
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */\r
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk \r
+#define FLASH_SR_PGPERR_Pos (6U) \r
+#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */\r
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk \r
+#define FLASH_SR_ERSERR_Pos (7U) \r
+#define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */\r
+#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk \r
+#define FLASH_SR_BSY_Pos (16U) \r
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */\r
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk \r
+\r
+/******************* Bits definition for FLASH_CR register ******************/\r
+#define FLASH_CR_PG_Pos (0U) \r
+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */\r
+#define FLASH_CR_PG FLASH_CR_PG_Msk \r
+#define FLASH_CR_SER_Pos (1U) \r
+#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */\r
+#define FLASH_CR_SER FLASH_CR_SER_Msk \r
+#define FLASH_CR_MER_Pos (2U) \r
+#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */\r
+#define FLASH_CR_MER FLASH_CR_MER_Msk \r
+#define FLASH_CR_MER1 FLASH_CR_MER\r
+#define FLASH_CR_SNB_Pos (3U) \r
+#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */\r
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk \r
+#define FLASH_CR_SNB_0 0x00000008U \r
+#define FLASH_CR_SNB_1 0x00000010U \r
+#define FLASH_CR_SNB_2 0x00000020U \r
+#define FLASH_CR_SNB_3 0x00000040U \r
+#define FLASH_CR_SNB_4 0x00000080U \r
+#define FLASH_CR_PSIZE_Pos (8U) \r
+#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */\r
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk \r
+#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */\r
+#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */\r
+#define FLASH_CR_MER2_Pos (15U) \r
+#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */\r
+#define FLASH_CR_MER2 FLASH_CR_MER2_Msk \r
+#define FLASH_CR_STRT_Pos (16U) \r
+#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */\r
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk \r
+#define FLASH_CR_EOPIE_Pos (24U) \r
+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */\r
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk \r
+#define FLASH_CR_ERRIE_Pos (25U) \r
+#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */\r
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk \r
+#define FLASH_CR_LOCK_Pos (31U) \r
+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */\r
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk \r
+\r
+/******************* Bits definition for FLASH_OPTCR register ***************/\r
+#define FLASH_OPTCR_OPTLOCK_Pos (0U) \r
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */\r
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk \r
+#define FLASH_OPTCR_OPTSTRT_Pos (1U) \r
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */\r
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk \r
+#define FLASH_OPTCR_BOR_LEV_Pos (2U) \r
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */\r
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk \r
+#define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000004 */\r
+#define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000008 */\r
+#define FLASH_OPTCR_WWDG_SW_Pos (4U) \r
+#define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos) /*!< 0x00000010 */\r
+#define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk \r
+#define FLASH_OPTCR_IWDG_SW_Pos (5U) \r
+#define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos) /*!< 0x00000020 */\r
+#define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk \r
+#define FLASH_OPTCR_nRST_STOP_Pos (6U) \r
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */\r
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk \r
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U) \r
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */\r
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk \r
+#define FLASH_OPTCR_RDP_Pos (8U) \r
+#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */\r
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk \r
+#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */\r
+#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */\r
+#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */\r
+#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */\r
+#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */\r
+#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */\r
+#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */\r
+#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */\r
+#define FLASH_OPTCR_nWRP_Pos (16U) \r
+#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */\r
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk \r
+#define FLASH_OPTCR_nWRP_0 0x00010000U \r
+#define FLASH_OPTCR_nWRP_1 0x00020000U \r
+#define FLASH_OPTCR_nWRP_2 0x00040000U \r
+#define FLASH_OPTCR_nWRP_3 0x00080000U \r
+#define FLASH_OPTCR_nWRP_4 0x00100000U \r
+#define FLASH_OPTCR_nWRP_5 0x00200000U \r
+#define FLASH_OPTCR_nWRP_6 0x00400000U \r
+#define FLASH_OPTCR_nWRP_7 0x00800000U \r
+#define FLASH_OPTCR_nWRP_8 0x01000000U \r
+#define FLASH_OPTCR_nWRP_9 0x02000000U \r
+#define FLASH_OPTCR_nWRP_10 0x04000000U \r
+#define FLASH_OPTCR_nWRP_11 0x08000000U \r
+#define FLASH_OPTCR_nDBOOT_Pos (28U) \r
+#define FLASH_OPTCR_nDBOOT_Msk (0x1UL << FLASH_OPTCR_nDBOOT_Pos) /*!< 0x10000000 */\r
+#define FLASH_OPTCR_nDBOOT FLASH_OPTCR_nDBOOT_Msk \r
+#define FLASH_OPTCR_nDBANK_Pos (29U) \r
+#define FLASH_OPTCR_nDBANK_Msk (0x1UL << FLASH_OPTCR_nDBANK_Pos) /*!< 0x20000000 */\r
+#define FLASH_OPTCR_nDBANK FLASH_OPTCR_nDBANK_Msk \r
+#define FLASH_OPTCR_IWDG_STDBY_Pos (30U) \r
+#define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos) /*!< 0x40000000 */\r
+#define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk \r
+#define FLASH_OPTCR_IWDG_STOP_Pos (31U) \r
+#define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos) /*!< 0x80000000 */\r
+#define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk \r
+\r
+/******************* Bits definition for FLASH_OPTCR1 register ***************/\r
+#define FLASH_OPTCR1_BOOT_ADD0_Pos (0U) \r
+#define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk \r
+#define FLASH_OPTCR1_BOOT_ADD1_Pos (16U) \r
+#define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */\r
+#define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk \r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FMC_BCR1 register *******************/\r
+#define FMC_BCR1_MBKEN_Pos (0U) \r
+#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR1_MUXEN_Pos (1U) \r
+#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR1_MTYP_Pos (2U) \r
+#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR1_MWID_Pos (4U) \r
+#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR1_FACCEN_Pos (6U) \r
+#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR1_BURSTEN_Pos (8U) \r
+#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR1_WAITPOL_Pos (9U) \r
+#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR1_WRAPMOD_Pos (10U) \r
+#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR1_WAITCFG_Pos (11U) \r
+#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR1_WREN_Pos (12U) \r
+#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR1_WAITEN_Pos (13U) \r
+#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR1_EXTMOD_Pos (14U) \r
+#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR1_ASYNCWAIT_Pos (15U) \r
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR1_CPSIZE_Pos (16U) \r
+#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR1_CBURSTRW_Pos (19U) \r
+#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */\r
+#define FMC_BCR1_CCLKEN_Pos (20U) \r
+#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */\r
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */\r
+#define FMC_BCR1_WFDIS_Pos (21U) \r
+#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */\r
+#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */\r
+\r
+/****************** Bit definition for FMC_BCR2 register *******************/\r
+#define FMC_BCR2_MBKEN_Pos (0U) \r
+#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR2_MUXEN_Pos (1U) \r
+#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR2_MTYP_Pos (2U) \r
+#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR2_MWID_Pos (4U) \r
+#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR2_FACCEN_Pos (6U) \r
+#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR2_BURSTEN_Pos (8U) \r
+#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR2_WAITPOL_Pos (9U) \r
+#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR2_WRAPMOD_Pos (10U) \r
+#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR2_WAITCFG_Pos (11U) \r
+#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR2_WREN_Pos (12U) \r
+#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR2_WAITEN_Pos (13U) \r
+#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR2_EXTMOD_Pos (14U) \r
+#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR2_ASYNCWAIT_Pos (15U) \r
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR2_CPSIZE_Pos (16U) \r
+#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR2_CBURSTRW_Pos (19U) \r
+#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR3 register *******************/\r
+#define FMC_BCR3_MBKEN_Pos (0U) \r
+#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR3_MUXEN_Pos (1U) \r
+#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR3_MTYP_Pos (2U) \r
+#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR3_MWID_Pos (4U) \r
+#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR3_FACCEN_Pos (6U) \r
+#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR3_BURSTEN_Pos (8U) \r
+#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR3_WAITPOL_Pos (9U) \r
+#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR3_WRAPMOD_Pos (10U) \r
+#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR3_WAITCFG_Pos (11U) \r
+#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR3_WREN_Pos (12U) \r
+#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR3_WAITEN_Pos (13U) \r
+#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR3_EXTMOD_Pos (14U) \r
+#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR3_ASYNCWAIT_Pos (15U) \r
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR3_CPSIZE_Pos (16U) \r
+#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR3_CBURSTRW_Pos (19U) \r
+#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR4 register *******************/\r
+#define FMC_BCR4_MBKEN_Pos (0U) \r
+#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR4_MUXEN_Pos (1U) \r
+#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR4_MTYP_Pos (2U) \r
+#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR4_MWID_Pos (4U) \r
+#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR4_FACCEN_Pos (6U) \r
+#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR4_BURSTEN_Pos (8U) \r
+#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR4_WAITPOL_Pos (9U) \r
+#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR4_WRAPMOD_Pos (10U) \r
+#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR4_WAITCFG_Pos (11U) \r
+#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR4_WREN_Pos (12U) \r
+#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR4_WAITEN_Pos (13U) \r
+#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR4_EXTMOD_Pos (14U) \r
+#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR4_ASYNCWAIT_Pos (15U) \r
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR4_CPSIZE_Pos (16U) \r
+#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR4_CBURSTRW_Pos (19U) \r
+#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BTR1 register ******************/\r
+#define FMC_BTR1_ADDSET_Pos (0U) \r
+#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR1_ADDHLD_Pos (4U) \r
+#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR1_DATAST_Pos (8U) \r
+#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR1_BUSTURN_Pos (16U) \r
+#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR1_CLKDIV_Pos (20U) \r
+#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR1_DATLAT_Pos (24U) \r
+#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR1_ACCMOD_Pos (28U) \r
+#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BTR2 register *******************/\r
+#define FMC_BTR2_ADDSET_Pos (0U) \r
+#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR2_ADDHLD_Pos (4U) \r
+#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR2_DATAST_Pos (8U) \r
+#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR2_BUSTURN_Pos (16U) \r
+#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR2_CLKDIV_Pos (20U) \r
+#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR2_DATLAT_Pos (24U) \r
+#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR2_ACCMOD_Pos (28U) \r
+#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for FMC_BTR3 register *******************/\r
+#define FMC_BTR3_ADDSET_Pos (0U) \r
+#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR3_ADDHLD_Pos (4U) \r
+#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR3_DATAST_Pos (8U) \r
+#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR3_BUSTURN_Pos (16U) \r
+#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR3_CLKDIV_Pos (20U) \r
+#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR3_DATLAT_Pos (24U) \r
+#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR3_ACCMOD_Pos (28U) \r
+#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BTR4 register *******************/\r
+#define FMC_BTR4_ADDSET_Pos (0U) \r
+#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR4_ADDHLD_Pos (4U) \r
+#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR4_DATAST_Pos (8U) \r
+#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR4_BUSTURN_Pos (16U) \r
+#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR4_CLKDIV_Pos (20U) \r
+#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR4_DATLAT_Pos (24U) \r
+#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR4_ACCMOD_Pos (28U) \r
+#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR1 register ******************/\r
+#define FMC_BWTR1_ADDSET_Pos (0U) \r
+#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR1_ADDHLD_Pos (4U) \r
+#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR1_DATAST_Pos (8U) \r
+#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR1_BUSTURN_Pos (16U) \r
+#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR1_ACCMOD_Pos (28U) \r
+#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR2 register ******************/\r
+#define FMC_BWTR2_ADDSET_Pos (0U) \r
+#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR2_ADDHLD_Pos (4U) \r
+#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR2_DATAST_Pos (8U) \r
+#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR2_BUSTURN_Pos (16U) \r
+#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR2_ACCMOD_Pos (28U) \r
+#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR3 register ******************/\r
+#define FMC_BWTR3_ADDSET_Pos (0U) \r
+#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR3_ADDHLD_Pos (4U) \r
+#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR3_DATAST_Pos (8U) \r
+#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR3_BUSTURN_Pos (16U) \r
+#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR3_ACCMOD_Pos (28U) \r
+#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR4 register ******************/\r
+#define FMC_BWTR4_ADDSET_Pos (0U) \r
+#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR4_ADDHLD_Pos (4U) \r
+#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR4_DATAST_Pos (8U) \r
+#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR4_BUSTURN_Pos (16U) \r
+#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR4_ACCMOD_Pos (28U) \r
+#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_PCR register *******************/\r
+#define FMC_PCR_PWAITEN_Pos (1U) \r
+#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */\r
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */\r
+#define FMC_PCR_PBKEN_Pos (2U) \r
+#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */\r
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR_PTYP_Pos (3U) \r
+#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */\r
+#define FMC_PCR_PWID_Pos (4U) \r
+#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */\r
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */\r
+#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */\r
+#define FMC_PCR_ECCEN_Pos (6U) \r
+#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */\r
+#define FMC_PCR_TCLR_Pos (9U) \r
+#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */\r
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */\r
+#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */\r
+#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */\r
+#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */\r
+#define FMC_PCR_TAR_Pos (13U) \r
+#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */\r
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */\r
+#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */\r
+#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */\r
+#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */\r
+#define FMC_PCR_ECCPS_Pos (17U) \r
+#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */\r
+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */\r
+#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */\r
+#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */\r
+\r
+/******************* Bit definition for FMC_SR register *******************/\r
+#define FMC_SR_IRS_Pos (0U) \r
+#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */\r
+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */\r
+#define FMC_SR_ILS_Pos (1U) \r
+#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */\r
+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */\r
+#define FMC_SR_IFS_Pos (2U) \r
+#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */\r
+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */\r
+#define FMC_SR_IREN_Pos (3U) \r
+#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */\r
+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR_ILEN_Pos (4U) \r
+#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */\r
+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR_IFEN_Pos (5U) \r
+#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */\r
+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR_FEMPT_Pos (6U) \r
+#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */\r
+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FMC_PMEM register ******************/\r
+#define FMC_PMEM_MEMSET3_Pos (0U) \r
+#define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */\r
+#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */\r
+#define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */\r
+#define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */\r
+#define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */\r
+#define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */\r
+#define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */\r
+#define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */\r
+#define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */\r
+#define FMC_PMEM_MEMWAIT3_Pos (8U) \r
+#define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */\r
+#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */\r
+#define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */\r
+#define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */\r
+#define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */\r
+#define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */\r
+#define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */\r
+#define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */\r
+#define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */\r
+#define FMC_PMEM_MEMHOLD3_Pos (16U) \r
+#define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */\r
+#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */\r
+#define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */\r
+#define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */\r
+#define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */\r
+#define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */\r
+#define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */\r
+#define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */\r
+#define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */\r
+#define FMC_PMEM_MEMHIZ3_Pos (24U) \r
+#define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */\r
+#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */\r
+#define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */\r
+#define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */\r
+#define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */\r
+#define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */\r
+#define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */\r
+#define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */\r
+#define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for FMC_PATT register ******************/\r
+#define FMC_PATT_ATTSET3_Pos (0U) \r
+#define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */\r
+#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */\r
+#define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */\r
+#define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */\r
+#define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */\r
+#define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */\r
+#define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */\r
+#define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */\r
+#define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */\r
+#define FMC_PATT_ATTWAIT3_Pos (8U) \r
+#define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */\r
+#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */\r
+#define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */\r
+#define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */\r
+#define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */\r
+#define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */\r
+#define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */\r
+#define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */\r
+#define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */\r
+#define FMC_PATT_ATTHOLD3_Pos (16U) \r
+#define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */\r
+#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */\r
+#define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */\r
+#define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */\r
+#define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */\r
+#define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */\r
+#define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */\r
+#define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */\r
+#define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */\r
+#define FMC_PATT_ATTHIZ3_Pos (24U) \r
+#define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */\r
+#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */\r
+#define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */\r
+#define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */\r
+#define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */\r
+#define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */\r
+#define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */\r
+#define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */\r
+#define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for FMC_ECCR register ******************/\r
+#define FMC_ECCR_ECC3_Pos (0U) \r
+#define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos) /*!< 0xFFFFFFFF */\r
+#define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_SDCR1 register ******************/\r
+#define FMC_SDCR1_NC_Pos (0U) \r
+#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */\r
+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */\r
+#define FMC_SDCR1_NR_Pos (2U) \r
+#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */\r
+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */\r
+#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */\r
+#define FMC_SDCR1_MWID_Pos (4U) \r
+#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_SDCR1_NB_Pos (6U) \r
+#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */\r
+#define FMC_SDCR1_CAS_Pos (7U) \r
+#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */\r
+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDCR1_WP_Pos (9U) \r
+#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */\r
+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */\r
+#define FMC_SDCR1_SDCLK_Pos (10U) \r
+#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */\r
+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */\r
+#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */\r
+#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */\r
+#define FMC_SDCR1_RBURST_Pos (12U) \r
+#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */\r
+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */\r
+#define FMC_SDCR1_RPIPE_Pos (13U) \r
+#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */\r
+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */\r
+#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */\r
+#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */\r
+\r
+/****************** Bit definition for FMC_SDCR2 register ******************/\r
+#define FMC_SDCR2_NC_Pos (0U) \r
+#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */\r
+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */\r
+#define FMC_SDCR2_NR_Pos (2U) \r
+#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */\r
+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */\r
+#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */\r
+#define FMC_SDCR2_MWID_Pos (4U) \r
+#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_SDCR2_NB_Pos (6U) \r
+#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */\r
+#define FMC_SDCR2_CAS_Pos (7U) \r
+#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */\r
+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDCR2_WP_Pos (9U) \r
+#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */\r
+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */\r
+#define FMC_SDCR2_SDCLK_Pos (10U) \r
+#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */\r
+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
+#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */\r
+#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */\r
+#define FMC_SDCR2_RBURST_Pos (12U) \r
+#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */\r
+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */\r
+#define FMC_SDCR2_RPIPE_Pos (13U) \r
+#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */\r
+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */\r
+#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */\r
+#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */\r
+\r
+/****************** Bit definition for FMC_SDTR1 register ******************/\r
+#define FMC_SDTR1_TMRD_Pos (0U) \r
+#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */\r
+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */\r
+#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */\r
+#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */\r
+#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */\r
+#define FMC_SDTR1_TXSR_Pos (4U) \r
+#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */\r
+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */\r
+#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */\r
+#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */\r
+#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */\r
+#define FMC_SDTR1_TRAS_Pos (8U) \r
+#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */\r
+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */\r
+#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */\r
+#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */\r
+#define FMC_SDTR1_TRC_Pos (12U) \r
+#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */\r
+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */\r
+#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */\r
+#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */\r
+#define FMC_SDTR1_TWR_Pos (16U) \r
+#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */\r
+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */\r
+#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */\r
+#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */\r
+#define FMC_SDTR1_TRP_Pos (20U) \r
+#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */\r
+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */\r
+#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */\r
+#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */\r
+#define FMC_SDTR1_TRCD_Pos (24U) \r
+#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */\r
+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */\r
+#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */\r
+#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */\r
+\r
+/****************** Bit definition for FMC_SDTR2 register ******************/\r
+#define FMC_SDTR2_TMRD_Pos (0U) \r
+#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */\r
+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */\r
+#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */\r
+#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */\r
+#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */\r
+#define FMC_SDTR2_TXSR_Pos (4U) \r
+#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */\r
+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */\r
+#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */\r
+#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */\r
+#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */\r
+#define FMC_SDTR2_TRAS_Pos (8U) \r
+#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */\r
+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */\r
+#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */\r
+#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */\r
+#define FMC_SDTR2_TRC_Pos (12U) \r
+#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */\r
+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */\r
+#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */\r
+#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */\r
+#define FMC_SDTR2_TWR_Pos (16U) \r
+#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */\r
+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */\r
+#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */\r
+#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */\r
+#define FMC_SDTR2_TRP_Pos (20U) \r
+#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */\r
+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */\r
+#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */\r
+#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */\r
+#define FMC_SDTR2_TRCD_Pos (24U) \r
+#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */\r
+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */\r
+#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */\r
+#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */\r
+\r
+/****************** Bit definition for FMC_SDCMR register ******************/\r
+#define FMC_SDCMR_MODE_Pos (0U) \r
+#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */\r
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */\r
+#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */\r
+#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */\r
+#define FMC_SDCMR_CTB2_Pos (3U) \r
+#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */\r
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */\r
+#define FMC_SDCMR_CTB1_Pos (4U) \r
+#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */\r
+#define FMC_SDCMR_NRFS_Pos (5U) \r
+#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */\r
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */\r
+#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDCMR_MRD_Pos (9U) \r
+#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */\r
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/****************** Bit definition for FMC_SDRTR register ******************/\r
+#define FMC_SDRTR_CRE_Pos (0U) \r
+#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */\r
+#define FMC_SDRTR_COUNT_Pos (1U) \r
+#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */\r
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */\r
+#define FMC_SDRTR_REIE_Pos (14U) \r
+#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */\r
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */\r
+\r
+/****************** Bit definition for FMC_SDSR register ******************/\r
+#define FMC_SDSR_RE_Pos (0U) \r
+#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */\r
+#define FMC_SDSR_MODES1_Pos (1U) \r
+#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */\r
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */\r
+#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */\r
+#define FMC_SDSR_MODES2_Pos (3U) \r
+#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */\r
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */\r
+#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */\r
+#define FMC_SDSR_BUSY_Pos (5U) \r
+#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */\r
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0_Pos (0U) \r
+#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */\r
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk \r
+#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */\r
+#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */\r
+#define GPIO_MODER_MODER1_Pos (2U) \r
+#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */\r
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk \r
+#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */\r
+#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */\r
+#define GPIO_MODER_MODER2_Pos (4U) \r
+#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */\r
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk \r
+#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */\r
+#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */\r
+#define GPIO_MODER_MODER3_Pos (6U) \r
+#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk \r
+#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */\r
+#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */\r
+#define GPIO_MODER_MODER4_Pos (8U) \r
+#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */\r
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk \r
+#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */\r
+#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */\r
+#define GPIO_MODER_MODER5_Pos (10U) \r
+#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk \r
+#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */\r
+#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */\r
+#define GPIO_MODER_MODER6_Pos (12U) \r
+#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */\r
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk \r
+#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */\r
+#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */\r
+#define GPIO_MODER_MODER7_Pos (14U) \r
+#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk \r
+#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */\r
+#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */\r
+#define GPIO_MODER_MODER8_Pos (16U) \r
+#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */\r
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk \r
+#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */\r
+#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */\r
+#define GPIO_MODER_MODER9_Pos (18U) \r
+#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk \r
+#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */\r
+#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */\r
+#define GPIO_MODER_MODER10_Pos (20U) \r
+#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */\r
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk \r
+#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */\r
+#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */\r
+#define GPIO_MODER_MODER11_Pos (22U) \r
+#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk \r
+#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */\r
+#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */\r
+#define GPIO_MODER_MODER12_Pos (24U) \r
+#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */\r
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk \r
+#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */\r
+#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */\r
+#define GPIO_MODER_MODER13_Pos (26U) \r
+#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk \r
+#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */\r
+#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */\r
+#define GPIO_MODER_MODER14_Pos (28U) \r
+#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */\r
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk \r
+#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */\r
+#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */\r
+#define GPIO_MODER_MODER15_Pos (30U) \r
+#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk \r
+#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */\r
+#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT_0 0x00000001U \r
+#define GPIO_OTYPER_OT_1 0x00000002U \r
+#define GPIO_OTYPER_OT_2 0x00000004U \r
+#define GPIO_OTYPER_OT_3 0x00000008U \r
+#define GPIO_OTYPER_OT_4 0x00000010U \r
+#define GPIO_OTYPER_OT_5 0x00000020U \r
+#define GPIO_OTYPER_OT_6 0x00000040U \r
+#define GPIO_OTYPER_OT_7 0x00000080U \r
+#define GPIO_OTYPER_OT_8 0x00000100U \r
+#define GPIO_OTYPER_OT_9 0x00000200U \r
+#define GPIO_OTYPER_OT_10 0x00000400U \r
+#define GPIO_OTYPER_OT_11 0x00000800U \r
+#define GPIO_OTYPER_OT_12 0x00001000U \r
+#define GPIO_OTYPER_OT_13 0x00002000U \r
+#define GPIO_OTYPER_OT_14 0x00004000U \r
+#define GPIO_OTYPER_OT_15 0x00008000U \r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) \r
+#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */\r
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */\r
+#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) \r
+#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */\r
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */\r
+#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) \r
+#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */\r
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */\r
+#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) \r
+#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */\r
+#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) \r
+#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */\r
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */\r
+#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) \r
+#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */\r
+#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) \r
+#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */\r
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */\r
+#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) \r
+#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */\r
+#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) \r
+#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */\r
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */\r
+#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) \r
+#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */\r
+#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) \r
+#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */\r
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */\r
+#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) \r
+#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */\r
+#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) \r
+#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) \r
+#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) \r
+#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) \r
+#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk \r
+#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0_Pos (0U) \r
+#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */\r
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk \r
+#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */\r
+#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */\r
+#define GPIO_PUPDR_PUPDR1_Pos (2U) \r
+#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */\r
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk \r
+#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */\r
+#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */\r
+#define GPIO_PUPDR_PUPDR2_Pos (4U) \r
+#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */\r
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk \r
+#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */\r
+#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */\r
+#define GPIO_PUPDR_PUPDR3_Pos (6U) \r
+#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk \r
+#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */\r
+#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */\r
+#define GPIO_PUPDR_PUPDR4_Pos (8U) \r
+#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */\r
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk \r
+#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */\r
+#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */\r
+#define GPIO_PUPDR_PUPDR5_Pos (10U) \r
+#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk \r
+#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */\r
+#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */\r
+#define GPIO_PUPDR_PUPDR6_Pos (12U) \r
+#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */\r
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk \r
+#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */\r
+#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */\r
+#define GPIO_PUPDR_PUPDR7_Pos (14U) \r
+#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk \r
+#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */\r
+#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */\r
+#define GPIO_PUPDR_PUPDR8_Pos (16U) \r
+#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */\r
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk \r
+#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */\r
+#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */\r
+#define GPIO_PUPDR_PUPDR9_Pos (18U) \r
+#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk \r
+#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */\r
+#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */\r
+#define GPIO_PUPDR_PUPDR10_Pos (20U) \r
+#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */\r
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk \r
+#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */\r
+#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */\r
+#define GPIO_PUPDR_PUPDR11_Pos (22U) \r
+#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk \r
+#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */\r
+#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */\r
+#define GPIO_PUPDR_PUPDR12_Pos (24U) \r
+#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */\r
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk \r
+#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */\r
+#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */\r
+#define GPIO_PUPDR_PUPDR13_Pos (26U) \r
+#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk \r
+#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */\r
+#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */\r
+#define GPIO_PUPDR_PUPDR14_Pos (28U) \r
+#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */\r
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk \r
+#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */\r
+#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */\r
+#define GPIO_PUPDR_PUPDR15_Pos (30U) \r
+#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk \r
+#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */\r
+#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 0x00000001U \r
+#define GPIO_IDR_IDR_1 0x00000002U \r
+#define GPIO_IDR_IDR_2 0x00000004U \r
+#define GPIO_IDR_IDR_3 0x00000008U \r
+#define GPIO_IDR_IDR_4 0x00000010U \r
+#define GPIO_IDR_IDR_5 0x00000020U \r
+#define GPIO_IDR_IDR_6 0x00000040U \r
+#define GPIO_IDR_IDR_7 0x00000080U \r
+#define GPIO_IDR_IDR_8 0x00000100U \r
+#define GPIO_IDR_IDR_9 0x00000200U \r
+#define GPIO_IDR_IDR_10 0x00000400U \r
+#define GPIO_IDR_IDR_11 0x00000800U \r
+#define GPIO_IDR_IDR_12 0x00001000U \r
+#define GPIO_IDR_IDR_13 0x00002000U \r
+#define GPIO_IDR_IDR_14 0x00004000U \r
+#define GPIO_IDR_IDR_15 0x00008000U \r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 0x00000001U \r
+#define GPIO_ODR_ODR_1 0x00000002U \r
+#define GPIO_ODR_ODR_2 0x00000004U \r
+#define GPIO_ODR_ODR_3 0x00000008U \r
+#define GPIO_ODR_ODR_4 0x00000010U \r
+#define GPIO_ODR_ODR_5 0x00000020U \r
+#define GPIO_ODR_ODR_6 0x00000040U \r
+#define GPIO_ODR_ODR_7 0x00000080U \r
+#define GPIO_ODR_ODR_8 0x00000100U \r
+#define GPIO_ODR_ODR_9 0x00000200U \r
+#define GPIO_ODR_ODR_10 0x00000400U \r
+#define GPIO_ODR_ODR_11 0x00000800U \r
+#define GPIO_ODR_ODR_12 0x00001000U \r
+#define GPIO_ODR_ODR_13 0x00002000U \r
+#define GPIO_ODR_ODR_14 0x00004000U \r
+#define GPIO_ODR_ODR_15 0x00008000U \r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS_0 0x00000001U \r
+#define GPIO_BSRR_BS_1 0x00000002U \r
+#define GPIO_BSRR_BS_2 0x00000004U \r
+#define GPIO_BSRR_BS_3 0x00000008U \r
+#define GPIO_BSRR_BS_4 0x00000010U \r
+#define GPIO_BSRR_BS_5 0x00000020U \r
+#define GPIO_BSRR_BS_6 0x00000040U \r
+#define GPIO_BSRR_BS_7 0x00000080U \r
+#define GPIO_BSRR_BS_8 0x00000100U \r
+#define GPIO_BSRR_BS_9 0x00000200U \r
+#define GPIO_BSRR_BS_10 0x00000400U \r
+#define GPIO_BSRR_BS_11 0x00000800U \r
+#define GPIO_BSRR_BS_12 0x00001000U \r
+#define GPIO_BSRR_BS_13 0x00002000U \r
+#define GPIO_BSRR_BS_14 0x00004000U \r
+#define GPIO_BSRR_BS_15 0x00008000U \r
+#define GPIO_BSRR_BR_0 0x00010000U \r
+#define GPIO_BSRR_BR_1 0x00020000U \r
+#define GPIO_BSRR_BR_2 0x00040000U \r
+#define GPIO_BSRR_BR_3 0x00080000U \r
+#define GPIO_BSRR_BR_4 0x00100000U \r
+#define GPIO_BSRR_BR_5 0x00200000U \r
+#define GPIO_BSRR_BR_6 0x00400000U \r
+#define GPIO_BSRR_BR_7 0x00800000U \r
+#define GPIO_BSRR_BR_8 0x01000000U \r
+#define GPIO_BSRR_BR_9 0x02000000U \r
+#define GPIO_BSRR_BR_10 0x04000000U \r
+#define GPIO_BSRR_BR_11 0x08000000U \r
+#define GPIO_BSRR_BR_12 0x10000000U \r
+#define GPIO_BSRR_BR_13 0x20000000U \r
+#define GPIO_BSRR_BR_14 0x40000000U \r
+#define GPIO_BSRR_BR_15 0x80000000U \r
+\r
+/****************** Bit definition for GPIO_LCKR register *********************/\r
+#define GPIO_LCKR_LCK0_Pos (0U) \r
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */\r
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk \r
+#define GPIO_LCKR_LCK1_Pos (1U) \r
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */\r
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk \r
+#define GPIO_LCKR_LCK2_Pos (2U) \r
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */\r
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk \r
+#define GPIO_LCKR_LCK3_Pos (3U) \r
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */\r
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk \r
+#define GPIO_LCKR_LCK4_Pos (4U) \r
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */\r
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk \r
+#define GPIO_LCKR_LCK5_Pos (5U) \r
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */\r
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk \r
+#define GPIO_LCKR_LCK6_Pos (6U) \r
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */\r
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk \r
+#define GPIO_LCKR_LCK7_Pos (7U) \r
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */\r
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk \r
+#define GPIO_LCKR_LCK8_Pos (8U) \r
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */\r
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk \r
+#define GPIO_LCKR_LCK9_Pos (9U) \r
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */\r
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk \r
+#define GPIO_LCKR_LCK10_Pos (10U) \r
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */\r
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk \r
+#define GPIO_LCKR_LCK11_Pos (11U) \r
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */\r
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk \r
+#define GPIO_LCKR_LCK12_Pos (12U) \r
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */\r
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk \r
+#define GPIO_LCKR_LCK13_Pos (13U) \r
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */\r
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk \r
+#define GPIO_LCKR_LCK14_Pos (14U) \r
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */\r
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk \r
+#define GPIO_LCKR_LCK15_Pos (15U) \r
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */\r
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk \r
+#define GPIO_LCKR_LCKK_Pos (16U) \r
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */\r
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk \r
+\r
+/****************** Bit definition for GPIO_AFRL register *********************/\r
+#define GPIO_AFRL_AFRL0_Pos (0U) \r
+#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk \r
+#define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000001 */\r
+#define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000002 */\r
+#define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000004 */\r
+#define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000008 */\r
+#define GPIO_AFRL_AFRL1_Pos (4U) \r
+#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk \r
+#define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000010 */\r
+#define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000020 */\r
+#define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000040 */\r
+#define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000080 */\r
+#define GPIO_AFRL_AFRL2_Pos (8U) \r
+#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk \r
+#define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000100 */\r
+#define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000200 */\r
+#define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000400 */\r
+#define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000800 */\r
+#define GPIO_AFRL_AFRL3_Pos (12U) \r
+#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk \r
+#define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00001000 */\r
+#define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00002000 */\r
+#define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00004000 */\r
+#define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00008000 */\r
+#define GPIO_AFRL_AFRL4_Pos (16U) \r
+#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk \r
+#define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00010000 */\r
+#define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00020000 */\r
+#define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00040000 */\r
+#define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00080000 */\r
+#define GPIO_AFRL_AFRL5_Pos (20U) \r
+#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk \r
+#define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00100000 */\r
+#define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00200000 */\r
+#define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00400000 */\r
+#define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00800000 */\r
+#define GPIO_AFRL_AFRL6_Pos (24U) \r
+#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk \r
+#define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x01000000 */\r
+#define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x02000000 */\r
+#define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x04000000 */\r
+#define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x08000000 */\r
+#define GPIO_AFRL_AFRL7_Pos (28U) \r
+#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk \r
+#define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x10000000 */\r
+#define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x20000000 */\r
+#define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x40000000 */\r
+#define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for GPIO_AFRH register *********************/\r
+#define GPIO_AFRH_AFRH0_Pos (0U) \r
+#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk \r
+#define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000001 */\r
+#define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000002 */\r
+#define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000004 */\r
+#define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000008 */\r
+#define GPIO_AFRH_AFRH1_Pos (4U) \r
+#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk \r
+#define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000010 */\r
+#define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000020 */\r
+#define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000040 */\r
+#define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000080 */\r
+#define GPIO_AFRH_AFRH2_Pos (8U) \r
+#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk \r
+#define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000100 */\r
+#define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000200 */\r
+#define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000400 */\r
+#define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000800 */\r
+#define GPIO_AFRH_AFRH3_Pos (12U) \r
+#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk \r
+#define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00001000 */\r
+#define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00002000 */\r
+#define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00004000 */\r
+#define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00008000 */\r
+#define GPIO_AFRH_AFRH4_Pos (16U) \r
+#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk \r
+#define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00010000 */\r
+#define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00020000 */\r
+#define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00040000 */\r
+#define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00080000 */\r
+#define GPIO_AFRH_AFRH5_Pos (20U) \r
+#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk \r
+#define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00100000 */\r
+#define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00200000 */\r
+#define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00400000 */\r
+#define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00800000 */\r
+#define GPIO_AFRH_AFRH6_Pos (24U) \r
+#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk \r
+#define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x01000000 */\r
+#define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x02000000 */\r
+#define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x04000000 */\r
+#define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x08000000 */\r
+#define GPIO_AFRH_AFRH7_Pos (28U) \r
+#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk \r
+#define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x10000000 */\r
+#define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x20000000 */\r
+#define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x40000000 */\r
+#define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x80000000 */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register *******************/\r
+#define I2C_CR1_PE_Pos (0U) \r
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */\r
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */\r
+#define I2C_CR1_TXIE_Pos (1U) \r
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */\r
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */\r
+#define I2C_CR1_RXIE_Pos (2U) \r
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */\r
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */\r
+#define I2C_CR1_ADDRIE_Pos (3U) \r
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */\r
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */\r
+#define I2C_CR1_NACKIE_Pos (4U) \r
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */\r
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */\r
+#define I2C_CR1_STOPIE_Pos (5U) \r
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */\r
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */\r
+#define I2C_CR1_TCIE_Pos (6U) \r
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */\r
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */\r
+#define I2C_CR1_ERRIE_Pos (7U) \r
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */\r
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */\r
+#define I2C_CR1_DNF_Pos (8U) \r
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */\r
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */\r
+#define I2C_CR1_ANFOFF_Pos (12U) \r
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */\r
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */\r
+#define I2C_CR1_TXDMAEN_Pos (14U) \r
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */\r
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */\r
+#define I2C_CR1_RXDMAEN_Pos (15U) \r
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */\r
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */\r
+#define I2C_CR1_SBC_Pos (16U) \r
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */\r
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */\r
+#define I2C_CR1_NOSTRETCH_Pos (17U) \r
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */\r
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */\r
+#define I2C_CR1_GCEN_Pos (19U) \r
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */\r
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */\r
+#define I2C_CR1_SMBHEN_Pos (20U) \r
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */\r
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */\r
+#define I2C_CR1_SMBDEN_Pos (21U) \r
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */\r
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN_Pos (22U) \r
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */\r
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */\r
+#define I2C_CR1_PECEN_Pos (23U) \r
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */\r
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */\r
+\r
+\r
+/****************** Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_SADD_Pos (0U) \r
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */\r
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */\r
+#define I2C_CR2_RD_WRN_Pos (10U) \r
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */\r
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */\r
+#define I2C_CR2_ADD10_Pos (11U) \r
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */\r
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */\r
+#define I2C_CR2_HEAD10R_Pos (12U) \r
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */\r
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START_Pos (13U) \r
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */\r
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */\r
+#define I2C_CR2_STOP_Pos (14U) \r
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */\r
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */\r
+#define I2C_CR2_NACK_Pos (15U) \r
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */\r
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */\r
+#define I2C_CR2_NBYTES_Pos (16U) \r
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */\r
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */\r
+#define I2C_CR2_RELOAD_Pos (24U) \r
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */\r
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */\r
+#define I2C_CR2_AUTOEND_Pos (25U) \r
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */\r
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */\r
+#define I2C_CR2_PECBYTE_Pos (26U) \r
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */\r
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */\r
+\r
+/******************* Bit definition for I2C_OAR1 register ******************/\r
+#define I2C_OAR1_OA1_Pos (0U) \r
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */\r
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */\r
+#define I2C_OAR1_OA1MODE_Pos (10U) \r
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */\r
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN_Pos (15U) \r
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */\r
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */\r
+\r
+/******************* Bit definition for I2C_OAR2 register ******************/\r
+#define I2C_OAR2_OA2_Pos (1U) \r
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */\r
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */\r
+#define I2C_OAR2_OA2MSK_Pos (8U) \r
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */\r
+#define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */\r
+#define I2C_OAR2_OA2MASK01_Pos (8U) \r
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */\r
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r
+#define I2C_OAR2_OA2MASK02_Pos (9U) \r
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */\r
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r
+#define I2C_OAR2_OA2MASK03_Pos (8U) \r
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */\r
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r
+#define I2C_OAR2_OA2MASK04_Pos (10U) \r
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */\r
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r
+#define I2C_OAR2_OA2MASK05_Pos (8U) \r
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */\r
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r
+#define I2C_OAR2_OA2MASK06_Pos (9U) \r
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */\r
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r
+#define I2C_OAR2_OA2MASK07_Pos (8U) \r
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */\r
+#define I2C_OAR2_OA2EN_Pos (15U) \r
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */\r
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */\r
+\r
+/******************* Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL_Pos (0U) \r
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */\r
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */\r
+#define I2C_TIMINGR_SCLH_Pos (8U) \r
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */\r
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL_Pos (16U) \r
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */\r
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */\r
+#define I2C_TIMINGR_SCLDEL_Pos (20U) \r
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */\r
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */\r
+#define I2C_TIMINGR_PRESC_Pos (28U) \r
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */\r
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) \r
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\r
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */\r
+#define I2C_TIMEOUTR_TIDLE_Pos (12U) \r
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */\r
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */\r
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) \r
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\r
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */\r
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) \r
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\r
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */\r
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U) \r
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */\r
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */\r
+\r
+/****************** Bit definition for I2C_ISR register *********************/\r
+#define I2C_ISR_TXE_Pos (0U) \r
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */\r
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */\r
+#define I2C_ISR_TXIS_Pos (1U) \r
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */\r
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */\r
+#define I2C_ISR_RXNE_Pos (2U) \r
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */\r
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR_Pos (3U) \r
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */\r
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */\r
+#define I2C_ISR_NACKF_Pos (4U) \r
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */\r
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */\r
+#define I2C_ISR_STOPF_Pos (5U) \r
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */\r
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */\r
+#define I2C_ISR_TC_Pos (6U) \r
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */\r
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR_Pos (7U) \r
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */\r
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */\r
+#define I2C_ISR_BERR_Pos (8U) \r
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */\r
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */\r
+#define I2C_ISR_ARLO_Pos (9U) \r
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */\r
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */\r
+#define I2C_ISR_OVR_Pos (10U) \r
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */\r
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */\r
+#define I2C_ISR_PECERR_Pos (11U) \r
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */\r
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */\r
+#define I2C_ISR_TIMEOUT_Pos (12U) \r
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */\r
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */\r
+#define I2C_ISR_ALERT_Pos (13U) \r
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */\r
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */\r
+#define I2C_ISR_BUSY_Pos (15U) \r
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */\r
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */\r
+#define I2C_ISR_DIR_Pos (16U) \r
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */\r
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE_Pos (17U) \r
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */\r
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */\r
+\r
+/****************** Bit definition for I2C_ICR register *********************/\r
+#define I2C_ICR_ADDRCF_Pos (3U) \r
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */\r
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */\r
+#define I2C_ICR_NACKCF_Pos (4U) \r
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */\r
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */\r
+#define I2C_ICR_STOPCF_Pos (5U) \r
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */\r
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */\r
+#define I2C_ICR_BERRCF_Pos (8U) \r
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */\r
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */\r
+#define I2C_ICR_ARLOCF_Pos (9U) \r
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */\r
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF_Pos (10U) \r
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */\r
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF_Pos (11U) \r
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */\r
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */\r
+#define I2C_ICR_TIMOUTCF_Pos (12U) \r
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */\r
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */\r
+#define I2C_ICR_ALERTCF_Pos (13U) \r
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */\r
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */\r
+\r
+/****************** Bit definition for I2C_PECR register *********************/\r
+#define I2C_PECR_PEC_Pos (0U) \r
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */\r
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */\r
+\r
+/****************** Bit definition for I2C_RXDR register *********************/\r
+#define I2C_RXDR_RXDATA_Pos (0U) \r
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */\r
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */\r
+\r
+/****************** Bit definition for I2C_TXDR register *********************/\r
+#define I2C_TXDR_TXDATA_Pos (0U) \r
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */\r
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY_Pos (0U) \r
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */\r
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR_Pos (0U) \r
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */\r
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */\r
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */\r
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL_Pos (0U) \r
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */\r
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU_Pos (0U) \r
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */\r
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU_Pos (1U) \r
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */\r
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU_Pos (2U) \r
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */\r
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_WINR_WIN_Pos (0U) \r
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */\r
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* LCD-TFT Display Controller (LTDC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for LTDC_SSCR register *****************/\r
+\r
+#define LTDC_SSCR_VSH_Pos (0U) \r
+#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */\r
+#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */\r
+#define LTDC_SSCR_HSW_Pos (16U) \r
+#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */\r
+\r
+/******************** Bit definition for LTDC_BPCR register *****************/\r
+\r
+#define LTDC_BPCR_AVBP_Pos (0U) \r
+#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */\r
+#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */\r
+#define LTDC_BPCR_AHBP_Pos (16U) \r
+#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */\r
+\r
+/******************** Bit definition for LTDC_AWCR register *****************/\r
+\r
+#define LTDC_AWCR_AAH_Pos (0U) \r
+#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */\r
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */\r
+#define LTDC_AWCR_AAW_Pos (16U) \r
+#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */\r
+\r
+/******************** Bit definition for LTDC_TWCR register *****************/\r
+\r
+#define LTDC_TWCR_TOTALH_Pos (0U) \r
+#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */\r
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */\r
+#define LTDC_TWCR_TOTALW_Pos (16U) \r
+#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */\r
+#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */\r
+\r
+/******************** Bit definition for LTDC_GCR register ******************/\r
+\r
+#define LTDC_GCR_LTDCEN_Pos (0U) \r
+#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */\r
+#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */\r
+#define LTDC_GCR_DBW_Pos (4U) \r
+#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */\r
+#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */\r
+#define LTDC_GCR_DGW_Pos (8U) \r
+#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */\r
+#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */\r
+#define LTDC_GCR_DRW_Pos (12U) \r
+#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */\r
+#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */\r
+#define LTDC_GCR_DEN_Pos (16U) \r
+#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */\r
+#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */\r
+#define LTDC_GCR_PCPOL_Pos (28U) \r
+#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */\r
+#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */\r
+#define LTDC_GCR_DEPOL_Pos (29U) \r
+#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */\r
+#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */\r
+#define LTDC_GCR_VSPOL_Pos (30U) \r
+#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */\r
+#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */\r
+#define LTDC_GCR_HSPOL_Pos (31U) \r
+#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */\r
+#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */\r
+\r
+\r
+/******************** Bit definition for LTDC_SRCR register *****************/\r
+\r
+#define LTDC_SRCR_IMR_Pos (0U) \r
+#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */\r
+#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */\r
+#define LTDC_SRCR_VBR_Pos (1U) \r
+#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */\r
+#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */\r
+\r
+/******************** Bit definition for LTDC_BCCR register *****************/\r
+\r
+#define LTDC_BCCR_BCBLUE_Pos (0U) \r
+#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */\r
+#define LTDC_BCCR_BCGREEN_Pos (8U) \r
+#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */\r
+#define LTDC_BCCR_BCRED_Pos (16U) \r
+#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */\r
+\r
+/******************** Bit definition for LTDC_IER register ******************/\r
+\r
+#define LTDC_IER_LIE_Pos (0U) \r
+#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */\r
+#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */\r
+#define LTDC_IER_FUIE_Pos (1U) \r
+#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */\r
+#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */\r
+#define LTDC_IER_TERRIE_Pos (2U) \r
+#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */\r
+#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */\r
+#define LTDC_IER_RRIE_Pos (3U) \r
+#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */\r
+#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */\r
+\r
+/******************** Bit definition for LTDC_ISR register ******************/\r
+\r
+#define LTDC_ISR_LIF_Pos (0U) \r
+#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */\r
+#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */\r
+#define LTDC_ISR_FUIF_Pos (1U) \r
+#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */\r
+#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */\r
+#define LTDC_ISR_TERRIF_Pos (2U) \r
+#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */\r
+#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */\r
+#define LTDC_ISR_RRIF_Pos (3U) \r
+#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */\r
+#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_ICR register ******************/\r
+\r
+#define LTDC_ICR_CLIF_Pos (0U) \r
+#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */\r
+#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */\r
+#define LTDC_ICR_CFUIF_Pos (1U) \r
+#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */\r
+#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */\r
+#define LTDC_ICR_CTERRIF_Pos (2U) \r
+#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */\r
+#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */\r
+#define LTDC_ICR_CRRIF_Pos (3U) \r
+#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */\r
+#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_LIPCR register ****************/\r
+\r
+#define LTDC_LIPCR_LIPOS_Pos (0U) \r
+#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */\r
+#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */\r
+\r
+/******************** Bit definition for LTDC_CPSR register *****************/\r
+\r
+#define LTDC_CPSR_CYPOS_Pos (0U) \r
+#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */\r
+#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */\r
+#define LTDC_CPSR_CXPOS_Pos (16U) \r
+#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */\r
+#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */\r
+\r
+/******************** Bit definition for LTDC_CDSR register *****************/\r
+\r
+#define LTDC_CDSR_VDES_Pos (0U) \r
+#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */\r
+#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */\r
+#define LTDC_CDSR_HDES_Pos (1U) \r
+#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */\r
+#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */\r
+#define LTDC_CDSR_VSYNCS_Pos (2U) \r
+#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */\r
+#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */\r
+#define LTDC_CDSR_HSYNCS_Pos (3U) \r
+#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */\r
+#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */\r
+\r
+/******************** Bit definition for LTDC_LxCR register *****************/\r
+\r
+#define LTDC_LxCR_LEN_Pos (0U) \r
+#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */\r
+#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */\r
+#define LTDC_LxCR_COLKEN_Pos (1U) \r
+#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */\r
+#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */\r
+#define LTDC_LxCR_CLUTEN_Pos (4U) \r
+#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */\r
+#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */\r
+\r
+/******************** Bit definition for LTDC_LxWHPCR register **************/\r
+\r
+#define LTDC_LxWHPCR_WHSTPOS_Pos (0U) \r
+#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */\r
+#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */\r
+#define LTDC_LxWHPCR_WHSPPOS_Pos (16U) \r
+#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */\r
+#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxWVPCR register **************/\r
+\r
+#define LTDC_LxWVPCR_WVSTPOS_Pos (0U) \r
+#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */\r
+#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */\r
+#define LTDC_LxWVPCR_WVSPPOS_Pos (16U) \r
+#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */\r
+#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxCKCR register ***************/\r
+\r
+#define LTDC_LxCKCR_CKBLUE_Pos (0U) \r
+#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */\r
+#define LTDC_LxCKCR_CKGREEN_Pos (8U) \r
+#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */\r
+#define LTDC_LxCKCR_CKRED_Pos (16U) \r
+#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */\r
+\r
+/******************** Bit definition for LTDC_LxPFCR register ***************/\r
+\r
+#define LTDC_LxPFCR_PF_Pos (0U) \r
+#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */\r
+#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */\r
+\r
+/******************** Bit definition for LTDC_LxCACR register ***************/\r
+\r
+#define LTDC_LxCACR_CONSTA_Pos (0U) \r
+#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxDCCR register ***************/\r
+\r
+#define LTDC_LxDCCR_DCBLUE_Pos (0U) \r
+#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */\r
+#define LTDC_LxDCCR_DCGREEN_Pos (8U) \r
+#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */\r
+#define LTDC_LxDCCR_DCRED_Pos (16U) \r
+#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */\r
+#define LTDC_LxDCCR_DCALPHA_Pos (24U) \r
+#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */\r
+#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxBFCR register ***************/\r
+\r
+#define LTDC_LxBFCR_BF2_Pos (0U) \r
+#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */\r
+#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */\r
+#define LTDC_LxBFCR_BF1_Pos (8U) \r
+#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */\r
+#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */\r
+\r
+/******************** Bit definition for LTDC_LxCFBAR register **************/\r
+\r
+#define LTDC_LxCFBAR_CFBADD_Pos (0U) \r
+#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */\r
+#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLR register **************/\r
+\r
+#define LTDC_LxCFBLR_CFBLL_Pos (0U) \r
+#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */\r
+#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */\r
+#define LTDC_LxCFBLR_CFBP_Pos (16U) \r
+#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */\r
+#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLNR register *************/\r
+\r
+#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U) \r
+#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */\r
+#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */\r
+\r
+/******************** Bit definition for LTDC_LxCLUTWR register *************/\r
+\r
+#define LTDC_LxCLUTWR_BLUE_Pos (0U) \r
+#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */\r
+#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */\r
+#define LTDC_LxCLUTWR_GREEN_Pos (8U) \r
+#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */\r
+#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */\r
+#define LTDC_LxCLUTWR_RED_Pos (16U) \r
+#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */\r
+#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */\r
+#define LTDC_LxCLUTWR_CLUTADD_Pos (24U) \r
+#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */\r
+#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for PWR_CR1 register ********************/\r
+#define PWR_CR1_LPDS_Pos (0U) \r
+#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */\r
+#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low-Power Deepsleep */\r
+#define PWR_CR1_PDDS_Pos (1U) \r
+#define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos) /*!< 0x00000002 */\r
+#define PWR_CR1_PDDS PWR_CR1_PDDS_Msk /*!< Power Down Deepsleep */\r
+#define PWR_CR1_CSBF_Pos (3U) \r
+#define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos) /*!< 0x00000008 */\r
+#define PWR_CR1_CSBF PWR_CR1_CSBF_Msk /*!< Clear Standby Flag */\r
+#define PWR_CR1_PVDE_Pos (4U) \r
+#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */\r
+#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Power Voltage Detector Enable */\r
+#define PWR_CR1_PLS_Pos (5U) \r
+#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */\r
+#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */\r
+#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */\r
+#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */\r
+#define PWR_CR1_PLS_LEV1_Pos (5U) \r
+#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */\r
+#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */\r
+#define PWR_CR1_PLS_LEV2_Pos (6U) \r
+#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */\r
+#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */\r
+#define PWR_CR1_PLS_LEV3_Pos (5U) \r
+#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */\r
+#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */\r
+#define PWR_CR1_PLS_LEV4_Pos (7U) \r
+#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */\r
+#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */\r
+#define PWR_CR1_PLS_LEV5_Pos (5U) \r
+#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */\r
+#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */\r
+#define PWR_CR1_PLS_LEV6_Pos (6U) \r
+#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */\r
+#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */\r
+#define PWR_CR1_PLS_LEV7_Pos (5U) \r
+#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */\r
+#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */\r
+#define PWR_CR1_DBP_Pos (8U) \r
+#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */\r
+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */\r
+#define PWR_CR1_FPDS_Pos (9U) \r
+#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000200 */\r
+#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down in Stop mode */\r
+#define PWR_CR1_LPUDS_Pos (10U) \r
+#define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos) /*!< 0x00000400 */\r
+#define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk /*!< Low-power regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_MRUDS_Pos (11U) \r
+#define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos) /*!< 0x00000800 */\r
+#define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk /*!< Main regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_ADCDC1_Pos (13U) \r
+#define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos) /*!< 0x00002000 */\r
+#define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define PWR_CR1_VOS_Pos (14U) \r
+#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */\r
+#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00004000 */\r
+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00008000 */\r
+#define PWR_CR1_ODEN_Pos (16U) \r
+#define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos) /*!< 0x00010000 */\r
+#define PWR_CR1_ODEN PWR_CR1_ODEN_Msk /*!< Over Drive enable */\r
+#define PWR_CR1_ODSWEN_Pos (17U) \r
+#define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos) /*!< 0x00020000 */\r
+#define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk /*!< Over Drive switch enabled */\r
+#define PWR_CR1_UDEN_Pos (18U) \r
+#define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */\r
+#define PWR_CR1_UDEN PWR_CR1_UDEN_Msk /*!< Under Drive enable in stop mode */\r
+#define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */\r
+#define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */\r
+\r
+/******************* Bit definition for PWR_CSR1 register ********************/\r
+#define PWR_CSR1_WUIF_Pos (0U) \r
+#define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos) /*!< 0x00000001 */\r
+#define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk /*!< Wake up internal Flag */\r
+#define PWR_CSR1_SBF_Pos (1U) \r
+#define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos) /*!< 0x00000002 */\r
+#define PWR_CSR1_SBF PWR_CSR1_SBF_Msk /*!< Standby Flag */\r
+#define PWR_CSR1_PVDO_Pos (2U) \r
+#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000004 */\r
+#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< PVD Output */\r
+#define PWR_CSR1_BRR_Pos (3U) \r
+#define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos) /*!< 0x00000008 */\r
+#define PWR_CSR1_BRR PWR_CSR1_BRR_Msk /*!< Backup regulator ready */\r
+#define PWR_CSR1_EIWUP_Pos (8U) \r
+#define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos) /*!< 0x00000100 */\r
+#define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk /*!< Enable internal wakeup */\r
+#define PWR_CSR1_BRE_Pos (9U) \r
+#define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos) /*!< 0x00000200 */\r
+#define PWR_CSR1_BRE PWR_CSR1_BRE_Msk /*!< Backup regulator enable */\r
+#define PWR_CSR1_VOSRDY_Pos (14U) \r
+#define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos) /*!< 0x00004000 */\r
+#define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */\r
+#define PWR_CSR1_ODRDY_Pos (16U) \r
+#define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos) /*!< 0x00010000 */\r
+#define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk /*!< Over Drive generator ready */\r
+#define PWR_CSR1_ODSWRDY_Pos (17U) \r
+#define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos) /*!< 0x00020000 */\r
+#define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk /*!< Over Drive Switch ready */\r
+#define PWR_CSR1_UDRDY_Pos (18U) \r
+#define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos) /*!< 0x000C0000 */\r
+#define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk /*!< Under Drive ready */\r
+\r
+\r
+/******************** Bit definition for PWR_CR2 register ********************/\r
+#define PWR_CR2_CWUPF1_Pos (0U) \r
+#define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos) /*!< 0x00000001 */\r
+#define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk /*!< Clear Wakeup Pin Flag for PA0 */\r
+#define PWR_CR2_CWUPF2_Pos (1U) \r
+#define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos) /*!< 0x00000002 */\r
+#define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk /*!< Clear Wakeup Pin Flag for PA2 */\r
+#define PWR_CR2_CWUPF3_Pos (2U) \r
+#define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos) /*!< 0x00000004 */\r
+#define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk /*!< Clear Wakeup Pin Flag for PC1 */\r
+#define PWR_CR2_CWUPF4_Pos (3U) \r
+#define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos) /*!< 0x00000008 */\r
+#define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk /*!< Clear Wakeup Pin Flag for PC13 */\r
+#define PWR_CR2_CWUPF5_Pos (4U) \r
+#define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos) /*!< 0x00000010 */\r
+#define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk /*!< Clear Wakeup Pin Flag for PI8 */\r
+#define PWR_CR2_CWUPF6_Pos (5U) \r
+#define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos) /*!< 0x00000020 */\r
+#define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk /*!< Clear Wakeup Pin Flag for PI11 */\r
+#define PWR_CR2_WUPP1_Pos (8U) \r
+#define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos) /*!< 0x00000100 */\r
+#define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk /*!< Wakeup Pin Polarity bit for PA0 */\r
+#define PWR_CR2_WUPP2_Pos (9U) \r
+#define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos) /*!< 0x00000200 */\r
+#define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk /*!< Wakeup Pin Polarity bit for PA2 */\r
+#define PWR_CR2_WUPP3_Pos (10U) \r
+#define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos) /*!< 0x00000400 */\r
+#define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk /*!< Wakeup Pin Polarity bit for PC1 */\r
+#define PWR_CR2_WUPP4_Pos (11U) \r
+#define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos) /*!< 0x00000800 */\r
+#define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk /*!< Wakeup Pin Polarity bit for PC13 */\r
+#define PWR_CR2_WUPP5_Pos (12U) \r
+#define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos) /*!< 0x00001000 */\r
+#define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk /*!< Wakeup Pin Polarity bit for PI8 */\r
+#define PWR_CR2_WUPP6_Pos (13U) \r
+#define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos) /*!< 0x00002000 */\r
+#define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk /*!< Wakeup Pin Polarity bit for PI11 */\r
+\r
+/******************* Bit definition for PWR_CSR2 register ********************/\r
+#define PWR_CSR2_WUPF1_Pos (0U) \r
+#define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos) /*!< 0x00000001 */\r
+#define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk /*!< Wakeup Pin Flag for PA0 */\r
+#define PWR_CSR2_WUPF2_Pos (1U) \r
+#define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos) /*!< 0x00000002 */\r
+#define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk /*!< Wakeup Pin Flag for PA2 */\r
+#define PWR_CSR2_WUPF3_Pos (2U) \r
+#define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos) /*!< 0x00000004 */\r
+#define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk /*!< Wakeup Pin Flag for PC1 */\r
+#define PWR_CSR2_WUPF4_Pos (3U) \r
+#define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos) /*!< 0x00000008 */\r
+#define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk /*!< Wakeup Pin Flag for PC13 */\r
+#define PWR_CSR2_WUPF5_Pos (4U) \r
+#define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos) /*!< 0x00000010 */\r
+#define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk /*!< Wakeup Pin Flag for PI8 */\r
+#define PWR_CSR2_WUPF6_Pos (5U) \r
+#define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos) /*!< 0x00000020 */\r
+#define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk /*!< Wakeup Pin Flag for PI11 */\r
+#define PWR_CSR2_EWUP1_Pos (8U) \r
+#define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos) /*!< 0x00000100 */\r
+#define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk /*!< Enable Wakeup Pin PA0 */\r
+#define PWR_CSR2_EWUP2_Pos (9U) \r
+#define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos) /*!< 0x00000200 */\r
+#define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk /*!< Enable Wakeup Pin PA2 */\r
+#define PWR_CSR2_EWUP3_Pos (10U) \r
+#define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos) /*!< 0x00000400 */\r
+#define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk /*!< Enable Wakeup Pin PC1 */\r
+#define PWR_CSR2_EWUP4_Pos (11U) \r
+#define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos) /*!< 0x00000800 */\r
+#define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk /*!< Enable Wakeup Pin PC13 */\r
+#define PWR_CSR2_EWUP5_Pos (12U) \r
+#define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos) /*!< 0x00001000 */\r
+#define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk /*!< Enable Wakeup Pin PI8 */\r
+#define PWR_CSR2_EWUP6_Pos (13U) \r
+#define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos) /*!< 0x00002000 */\r
+#define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk /*!< Enable Wakeup Pin PI11 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* QUADSPI */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for QUADSPI_CR register *******************/\r
+#define QUADSPI_CR_EN_Pos (0U) \r
+#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */\r
+#define QUADSPI_CR_ABORT_Pos (1U) \r
+#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */\r
+#define QUADSPI_CR_DMAEN_Pos (2U) \r
+#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */\r
+#define QUADSPI_CR_TCEN_Pos (3U) \r
+#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */\r
+#define QUADSPI_CR_SSHIFT_Pos (4U) \r
+#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */\r
+#define QUADSPI_CR_DFM_Pos (6U) \r
+#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */\r
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */\r
+#define QUADSPI_CR_FSEL_Pos (7U) \r
+#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */\r
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */\r
+#define QUADSPI_CR_FTHRES_Pos (8U) \r
+#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */\r
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */\r
+#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_CR_TEIE_Pos (16U) \r
+#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */\r
+#define QUADSPI_CR_TCIE_Pos (17U) \r
+#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */\r
+#define QUADSPI_CR_FTIE_Pos (18U) \r
+#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */\r
+#define QUADSPI_CR_SMIE_Pos (19U) \r
+#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */\r
+#define QUADSPI_CR_TOIE_Pos (20U) \r
+#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */\r
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */\r
+#define QUADSPI_CR_APMS_Pos (22U) \r
+#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */\r
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */\r
+#define QUADSPI_CR_PMM_Pos (23U) \r
+#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */\r
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */\r
+#define QUADSPI_CR_PRESCALER_Pos (24U) \r
+#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */\r
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */\r
+#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */\r
+#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */\r
+#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */\r
+#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */\r
+#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */\r
+#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */\r
+#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */\r
+#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */\r
+\r
+/***************** Bit definition for QUADSPI_DCR register ******************/\r
+#define QUADSPI_DCR_CKMODE_Pos (0U) \r
+#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */\r
+#define QUADSPI_DCR_CSHT_Pos (8U) \r
+#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */\r
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */\r
+#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_DCR_FSIZE_Pos (16U) \r
+#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */\r
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */\r
+#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */\r
+\r
+/****************** Bit definition for QUADSPI_SR register *******************/\r
+#define QUADSPI_SR_TEF_Pos (0U) \r
+#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */\r
+#define QUADSPI_SR_TCF_Pos (1U) \r
+#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */\r
+#define QUADSPI_SR_FTF_Pos (2U) \r
+#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_SMF_Pos (3U) \r
+#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */\r
+#define QUADSPI_SR_TOF_Pos (4U) \r
+#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */\r
+#define QUADSPI_SR_BUSY_Pos (5U) \r
+#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */\r
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */\r
+#define QUADSPI_SR_FLEVEL_Pos (8U) \r
+#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */\r
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */\r
+\r
+/****************** Bit definition for QUADSPI_FCR register ******************/\r
+#define QUADSPI_FCR_CTEF_Pos (0U) \r
+#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */\r
+#define QUADSPI_FCR_CTCF_Pos (1U) \r
+#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */\r
+#define QUADSPI_FCR_CSMF_Pos (3U) \r
+#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */\r
+#define QUADSPI_FCR_CTOF_Pos (4U) \r
+#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */\r
+\r
+/****************** Bit definition for QUADSPI_DLR register ******************/\r
+#define QUADSPI_DLR_DL_Pos (0U) \r
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */\r
+\r
+/****************** Bit definition for QUADSPI_CCR register ******************/\r
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U) \r
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\r
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */\r
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\r
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\r
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\r
+#define QUADSPI_CCR_IMODE_Pos (8U) \r
+#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */\r
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_CCR_ADMODE_Pos (10U) \r
+#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */\r
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */\r
+#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_CCR_ADSIZE_Pos (12U) \r
+#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */\r
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */\r
+#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */\r
+#define QUADSPI_CCR_ABMODE_Pos (14U) \r
+#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */\r
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
+#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */\r
+#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */\r
+#define QUADSPI_CCR_ABSIZE_Pos (16U) \r
+#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */\r
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_CCR_DCYC_Pos (18U) \r
+#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */\r
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */\r
+#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */\r
+#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */\r
+#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */\r
+#define QUADSPI_CCR_DMODE_Pos (24U) \r
+#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */\r
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */\r
+#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */\r
+#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */\r
+#define QUADSPI_CCR_FMODE_Pos (26U) \r
+#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */\r
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */\r
+#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */\r
+#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */\r
+#define QUADSPI_CCR_SIOO_Pos (28U) \r
+#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */\r
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */\r
+#define QUADSPI_CCR_DHHC_Pos (30U) \r
+#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */\r
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */\r
+#define QUADSPI_CCR_DDRM_Pos (31U) \r
+#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */\r
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */\r
+/****************** Bit definition for QUADSPI_AR register *******************/\r
+#define QUADSPI_AR_ADDRESS_Pos (0U) \r
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */\r
+\r
+/****************** Bit definition for QUADSPI_ABR register ******************/\r
+#define QUADSPI_ABR_ALTERNATE_Pos (0U) \r
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */\r
+\r
+/****************** Bit definition for QUADSPI_DR register *******************/\r
+#define QUADSPI_DR_DATA_Pos (0U) \r
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */\r
+\r
+/****************** Bit definition for QUADSPI_PSMKR register ****************/\r
+#define QUADSPI_PSMKR_MASK_Pos (0U) \r
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */\r
+\r
+/****************** Bit definition for QUADSPI_PSMAR register ****************/\r
+#define QUADSPI_PSMAR_MATCH_Pos (0U) \r
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */\r
+\r
+/****************** Bit definition for QUADSPI_PIR register *****************/\r
+#define QUADSPI_PIR_INTERVAL_Pos (0U) \r
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\r
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */\r
+\r
+/****************** Bit definition for QUADSPI_LPTR register *****************/\r
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U) \r
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\r
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION_Pos (0U) \r
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CR_HSION RCC_CR_HSION_Msk \r
+#define RCC_CR_HSIRDY_Pos (1U) \r
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */\r
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk \r
+#define RCC_CR_HSITRIM_Pos (3U) \r
+#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */\r
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk \r
+#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */\r
+#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */\r
+#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */\r
+#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */\r
+#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */\r
+#define RCC_CR_HSICAL_Pos (8U) \r
+#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */\r
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk \r
+#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */\r
+#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */\r
+#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */\r
+#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */\r
+#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */\r
+#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */\r
+#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */\r
+#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */\r
+#define RCC_CR_HSEON_Pos (16U) \r
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */\r
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk \r
+#define RCC_CR_HSERDY_Pos (17U) \r
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */\r
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk \r
+#define RCC_CR_HSEBYP_Pos (18U) \r
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */\r
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk \r
+#define RCC_CR_CSSON_Pos (19U) \r
+#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */\r
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk \r
+#define RCC_CR_PLLON_Pos (24U) \r
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */\r
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk \r
+#define RCC_CR_PLLRDY_Pos (25U) \r
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */\r
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk \r
+#define RCC_CR_PLLI2SON_Pos (26U) \r
+#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */\r
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk \r
+#define RCC_CR_PLLI2SRDY_Pos (27U) \r
+#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */\r
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk \r
+#define RCC_CR_PLLSAION_Pos (28U) \r
+#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */\r
+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk \r
+#define RCC_CR_PLLSAIRDY_Pos (29U) \r
+#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */\r
+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk \r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+#define RCC_PLLCFGR_PLLM_Pos (0U) \r
+#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */\r
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk \r
+#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */\r
+#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */\r
+#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */\r
+#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */\r
+#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */\r
+#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */\r
+#define RCC_PLLCFGR_PLLN_Pos (6U) \r
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */\r
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk \r
+#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLCFGR_PLLP_Pos (16U) \r
+#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */\r
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk \r
+#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLCFGR_PLLSRC_Pos (22U) \r
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */\r
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk \r
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U) \r
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\r
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk \r
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U \r
+#define RCC_PLLCFGR_PLLQ_Pos (24U) \r
+#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */\r
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk \r
+#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */\r
+#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */\r
+\r
+#define RCC_PLLCFGR_PLLR_Pos (28U) \r
+#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */\r
+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk \r
+#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */\r
+#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */\r
+#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_Pos (0U) \r
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */\r
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */\r
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */\r
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_Pos (2U) \r
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */\r
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */\r
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */\r
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE_Pos (4U) \r
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */\r
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */\r
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */\r
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */\r
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1_Pos (10U) \r
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */\r
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */\r
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */\r
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2_Pos (13U) \r
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */\r
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */\r
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */\r
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE_Pos (16U) \r
+#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */\r
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk \r
+#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */\r
+#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */\r
+#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */\r
+#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */\r
+#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1_Pos (21U) \r
+#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */\r
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk \r
+#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */\r
+#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */\r
+\r
+#define RCC_CFGR_I2SSRC_Pos (23U) \r
+#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */\r
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk \r
+\r
+#define RCC_CFGR_MCO1PRE_Pos (24U) \r
+#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */\r
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk \r
+#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */\r
+#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */\r
+#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */\r
+\r
+#define RCC_CFGR_MCO2PRE_Pos (27U) \r
+#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */\r
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk \r
+#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */\r
+#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */\r
+#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */\r
+\r
+#define RCC_CFGR_MCO2_Pos (30U) \r
+#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */\r
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk \r
+#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */\r
+#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for RCC_CIR register *******************/\r
+#define RCC_CIR_LSIRDYF_Pos (0U) \r
+#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */\r
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk \r
+#define RCC_CIR_LSERDYF_Pos (1U) \r
+#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */\r
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk \r
+#define RCC_CIR_HSIRDYF_Pos (2U) \r
+#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */\r
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk \r
+#define RCC_CIR_HSERDYF_Pos (3U) \r
+#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */\r
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk \r
+#define RCC_CIR_PLLRDYF_Pos (4U) \r
+#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */\r
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk \r
+#define RCC_CIR_PLLI2SRDYF_Pos (5U) \r
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */\r
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk \r
+#define RCC_CIR_PLLSAIRDYF_Pos (6U) \r
+#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */\r
+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk \r
+#define RCC_CIR_CSSF_Pos (7U) \r
+#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */\r
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk \r
+#define RCC_CIR_LSIRDYIE_Pos (8U) \r
+#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */\r
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk \r
+#define RCC_CIR_LSERDYIE_Pos (9U) \r
+#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */\r
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk \r
+#define RCC_CIR_HSIRDYIE_Pos (10U) \r
+#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */\r
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk \r
+#define RCC_CIR_HSERDYIE_Pos (11U) \r
+#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */\r
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk \r
+#define RCC_CIR_PLLRDYIE_Pos (12U) \r
+#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */\r
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk \r
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U) \r
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */\r
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk \r
+#define RCC_CIR_PLLSAIRDYIE_Pos (14U) \r
+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */\r
+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk \r
+#define RCC_CIR_LSIRDYC_Pos (16U) \r
+#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */\r
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk \r
+#define RCC_CIR_LSERDYC_Pos (17U) \r
+#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */\r
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk \r
+#define RCC_CIR_HSIRDYC_Pos (18U) \r
+#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */\r
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk \r
+#define RCC_CIR_HSERDYC_Pos (19U) \r
+#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */\r
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk \r
+#define RCC_CIR_PLLRDYC_Pos (20U) \r
+#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */\r
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk \r
+#define RCC_CIR_PLLI2SRDYC_Pos (21U) \r
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */\r
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk \r
+#define RCC_CIR_PLLSAIRDYC_Pos (22U) \r
+#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */\r
+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk \r
+#define RCC_CIR_CSSC_Pos (23U) \r
+#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */\r
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk \r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register **************/\r
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U) \r
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk \r
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U) \r
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk \r
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U) \r
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk \r
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U) \r
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk \r
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U) \r
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk \r
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U) \r
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk \r
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U) \r
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk \r
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U) \r
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk \r
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U) \r
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk \r
+#define RCC_AHB1RSTR_GPIOJRST_Pos (9U) \r
+#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk \r
+#define RCC_AHB1RSTR_GPIOKRST_Pos (10U) \r
+#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */\r
+#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk \r
+#define RCC_AHB1RSTR_CRCRST_Pos (12U) \r
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk \r
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U) \r
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk \r
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U) \r
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk \r
+#define RCC_AHB1RSTR_DMA2DRST_Pos (23U) \r
+#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */\r
+#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk \r
+#define RCC_AHB1RSTR_ETHMACRST_Pos (25U) \r
+#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk \r
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U) \r
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk \r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register **************/\r
+#define RCC_AHB2RSTR_DCMIRST_Pos (0U) \r
+#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk \r
+#define RCC_AHB2RSTR_JPEGRST_Pos (1U) \r
+#define RCC_AHB2RSTR_JPEGRST_Msk (0x1UL << RCC_AHB2RSTR_JPEGRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB2RSTR_JPEGRST RCC_AHB2RSTR_JPEGRST_Msk \r
+#define RCC_AHB2RSTR_RNGRST_Pos (6U) \r
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk \r
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U) \r
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk \r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register **************/\r
+\r
+#define RCC_AHB3RSTR_FMCRST_Pos (0U) \r
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk \r
+#define RCC_AHB3RSTR_QSPIRST_Pos (1U) \r
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk \r
+\r
+/******************** Bit definition for RCC_APB1RSTR register **************/\r
+#define RCC_APB1RSTR_TIM2RST_Pos (0U) \r
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk \r
+#define RCC_APB1RSTR_TIM3RST_Pos (1U) \r
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk \r
+#define RCC_APB1RSTR_TIM4RST_Pos (2U) \r
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk \r
+#define RCC_APB1RSTR_TIM5RST_Pos (3U) \r
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk \r
+#define RCC_APB1RSTR_TIM6RST_Pos (4U) \r
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk \r
+#define RCC_APB1RSTR_TIM7RST_Pos (5U) \r
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk \r
+#define RCC_APB1RSTR_TIM12RST_Pos (6U) \r
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk \r
+#define RCC_APB1RSTR_TIM13RST_Pos (7U) \r
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk \r
+#define RCC_APB1RSTR_TIM14RST_Pos (8U) \r
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk \r
+#define RCC_APB1RSTR_LPTIM1RST_Pos (9U) \r
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk \r
+#define RCC_APB1RSTR_WWDGRST_Pos (11U) \r
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk \r
+#define RCC_APB1RSTR_CAN3RST_Pos (13U) \r
+#define RCC_APB1RSTR_CAN3RST_Msk (0x1UL << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x00002000 */\r
+#define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk \r
+#define RCC_APB1RSTR_SPI2RST_Pos (14U) \r
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk \r
+#define RCC_APB1RSTR_SPI3RST_Pos (15U) \r
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk \r
+#define RCC_APB1RSTR_SPDIFRXRST_Pos (16U) \r
+#define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */\r
+#define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk \r
+#define RCC_APB1RSTR_USART2RST_Pos (17U) \r
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk \r
+#define RCC_APB1RSTR_USART3RST_Pos (18U) \r
+#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk \r
+#define RCC_APB1RSTR_UART4RST_Pos (19U) \r
+#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk \r
+#define RCC_APB1RSTR_UART5RST_Pos (20U) \r
+#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk \r
+#define RCC_APB1RSTR_I2C1RST_Pos (21U) \r
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk \r
+#define RCC_APB1RSTR_I2C2RST_Pos (22U) \r
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk \r
+#define RCC_APB1RSTR_I2C3RST_Pos (23U) \r
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk \r
+#define RCC_APB1RSTR_I2C4RST_Pos (24U) \r
+#define RCC_APB1RSTR_I2C4RST_Msk (0x1UL << RCC_APB1RSTR_I2C4RST_Pos) /*!< 0x01000000 */\r
+#define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk \r
+#define RCC_APB1RSTR_CAN1RST_Pos (25U) \r
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk \r
+#define RCC_APB1RSTR_CAN2RST_Pos (26U) \r
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */\r
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk \r
+#define RCC_APB1RSTR_CECRST_Pos (27U) \r
+#define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */\r
+#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk \r
+#define RCC_APB1RSTR_PWRRST_Pos (28U) \r
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk \r
+#define RCC_APB1RSTR_DACRST_Pos (29U) \r
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk \r
+#define RCC_APB1RSTR_UART7RST_Pos (30U) \r
+#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk \r
+#define RCC_APB1RSTR_UART8RST_Pos (31U) \r
+#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk \r
+\r
+/******************** Bit definition for RCC_APB2RSTR register **************/\r
+#define RCC_APB2RSTR_TIM1RST_Pos (0U) \r
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk \r
+#define RCC_APB2RSTR_TIM8RST_Pos (1U) \r
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk \r
+#define RCC_APB2RSTR_USART1RST_Pos (4U) \r
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk \r
+#define RCC_APB2RSTR_USART6RST_Pos (5U) \r
+#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk \r
+#define RCC_APB2RSTR_SDMMC2RST_Pos (7U) \r
+#define RCC_APB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */\r
+#define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk \r
+#define RCC_APB2RSTR_ADCRST_Pos (8U) \r
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */\r
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk \r
+#define RCC_APB2RSTR_SDMMC1RST_Pos (11U) \r
+#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk \r
+#define RCC_APB2RSTR_SPI1RST_Pos (12U) \r
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk \r
+#define RCC_APB2RSTR_SPI4RST_Pos (13U) \r
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk \r
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U) \r
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk \r
+#define RCC_APB2RSTR_TIM9RST_Pos (16U) \r
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk \r
+#define RCC_APB2RSTR_TIM10RST_Pos (17U) \r
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk \r
+#define RCC_APB2RSTR_TIM11RST_Pos (18U) \r
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk \r
+#define RCC_APB2RSTR_SPI5RST_Pos (20U) \r
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk \r
+#define RCC_APB2RSTR_SPI6RST_Pos (21U) \r
+#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk \r
+#define RCC_APB2RSTR_SAI1RST_Pos (22U) \r
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk \r
+#define RCC_APB2RSTR_SAI2RST_Pos (23U) \r
+#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk \r
+#define RCC_APB2RSTR_LTDCRST_Pos (26U) \r
+#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */\r
+#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk \r
+#define RCC_APB2RSTR_DFSDM1RST_Pos (29U) \r
+#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x20000000 */\r
+#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk \r
+#define RCC_APB2RSTR_MDIORST_Pos (30U) \r
+#define RCC_APB2RSTR_MDIORST_Msk (0x1UL << RCC_APB2RSTR_MDIORST_Pos) /*!< 0x40000000 */\r
+#define RCC_APB2RSTR_MDIORST RCC_APB2RSTR_MDIORST_Msk \r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U) \r
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk \r
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U) \r
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk \r
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U) \r
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk \r
+#define RCC_AHB1ENR_GPIODEN_Pos (3U) \r
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk \r
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U) \r
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk \r
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U) \r
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk \r
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U) \r
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk \r
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U) \r
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk \r
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U) \r
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk \r
+#define RCC_AHB1ENR_GPIOJEN_Pos (9U) \r
+#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk \r
+#define RCC_AHB1ENR_GPIOKEN_Pos (10U) \r
+#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */\r
+#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk \r
+#define RCC_AHB1ENR_CRCEN_Pos (12U) \r
+#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk \r
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U) \r
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\r
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk \r
+#define RCC_AHB1ENR_DTCMRAMEN_Pos (20U) \r
+#define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */\r
+#define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk \r
+#define RCC_AHB1ENR_DMA1EN_Pos (21U) \r
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk \r
+#define RCC_AHB1ENR_DMA2EN_Pos (22U) \r
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk \r
+#define RCC_AHB1ENR_DMA2DEN_Pos (23U) \r
+#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */\r
+#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk \r
+#define RCC_AHB1ENR_ETHMACEN_Pos (25U) \r
+#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk \r
+#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U) \r
+#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */\r
+#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk \r
+#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U) \r
+#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */\r
+#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk \r
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U) \r
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk \r
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U) \r
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk \r
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U) \r
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk \r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_DCMIEN_Pos (0U) \r
+#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk \r
+#define RCC_AHB2ENR_JPEGEN_Pos (1U) \r
+#define RCC_AHB2ENR_JPEGEN_Msk (0x1UL << RCC_AHB2ENR_JPEGEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB2ENR_JPEGEN RCC_AHB2ENR_JPEGEN_Msk \r
+#define RCC_AHB2ENR_RNGEN_Pos (6U) \r
+#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk \r
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U) \r
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk \r
+\r
+/******************** Bit definition for RCC_AHB3ENR register ***************/\r
+#define RCC_AHB3ENR_FMCEN_Pos (0U) \r
+#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk \r
+#define RCC_AHB3ENR_QSPIEN_Pos (1U) \r
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk \r
+\r
+/******************** Bit definition for RCC_APB1ENR register ***************/\r
+#define RCC_APB1ENR_TIM2EN_Pos (0U) \r
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk \r
+#define RCC_APB1ENR_TIM3EN_Pos (1U) \r
+#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk \r
+#define RCC_APB1ENR_TIM4EN_Pos (2U) \r
+#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk \r
+#define RCC_APB1ENR_TIM5EN_Pos (3U) \r
+#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk \r
+#define RCC_APB1ENR_TIM6EN_Pos (4U) \r
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk \r
+#define RCC_APB1ENR_TIM7EN_Pos (5U) \r
+#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk \r
+#define RCC_APB1ENR_TIM12EN_Pos (6U) \r
+#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk \r
+#define RCC_APB1ENR_TIM13EN_Pos (7U) \r
+#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk \r
+#define RCC_APB1ENR_TIM14EN_Pos (8U) \r
+#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk \r
+#define RCC_APB1ENR_LPTIM1EN_Pos (9U) \r
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk \r
+#define RCC_APB1ENR_RTCEN_Pos (10U) \r
+#define RCC_APB1ENR_RTCEN_Msk (0x1UL << RCC_APB1ENR_RTCEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk \r
+#define RCC_APB1ENR_WWDGEN_Pos (11U) \r
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk \r
+#define RCC_APB1ENR_CAN3EN_Pos (13U) \r
+#define RCC_APB1ENR_CAN3EN_Msk (0x1UL << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk \r
+#define RCC_APB1ENR_SPI2EN_Pos (14U) \r
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk \r
+#define RCC_APB1ENR_SPI3EN_Pos (15U) \r
+#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk \r
+#define RCC_APB1ENR_SPDIFRXEN_Pos (16U) \r
+#define RCC_APB1ENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk \r
+#define RCC_APB1ENR_USART2EN_Pos (17U) \r
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk \r
+#define RCC_APB1ENR_USART3EN_Pos (18U) \r
+#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk \r
+#define RCC_APB1ENR_UART4EN_Pos (19U) \r
+#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk \r
+#define RCC_APB1ENR_UART5EN_Pos (20U) \r
+#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk \r
+#define RCC_APB1ENR_I2C1EN_Pos (21U) \r
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk \r
+#define RCC_APB1ENR_I2C2EN_Pos (22U) \r
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk \r
+#define RCC_APB1ENR_I2C3EN_Pos (23U) \r
+#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk \r
+#define RCC_APB1ENR_I2C4EN_Pos (24U) \r
+#define RCC_APB1ENR_I2C4EN_Msk (0x1UL << RCC_APB1ENR_I2C4EN_Pos) /*!< 0x01000000 */\r
+#define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk \r
+#define RCC_APB1ENR_CAN1EN_Pos (25U) \r
+#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk \r
+#define RCC_APB1ENR_CAN2EN_Pos (26U) \r
+#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */\r
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk \r
+#define RCC_APB1ENR_CECEN_Pos (27U) \r
+#define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */\r
+#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk \r
+#define RCC_APB1ENR_PWREN_Pos (28U) \r
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk \r
+#define RCC_APB1ENR_DACEN_Pos (29U) \r
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk \r
+#define RCC_APB1ENR_UART7EN_Pos (30U) \r
+#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk \r
+#define RCC_APB1ENR_UART8EN_Pos (31U) \r
+#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk \r
+\r
+/******************** Bit definition for RCC_APB2ENR register ***************/\r
+#define RCC_APB2ENR_TIM1EN_Pos (0U) \r
+#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk \r
+#define RCC_APB2ENR_TIM8EN_Pos (1U) \r
+#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk \r
+#define RCC_APB2ENR_USART1EN_Pos (4U) \r
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk \r
+#define RCC_APB2ENR_USART6EN_Pos (5U) \r
+#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk \r
+#define RCC_APB2ENR_SDMMC2EN_Pos (7U) \r
+#define RCC_APB2ENR_SDMMC2EN_Msk (0x1UL << RCC_APB2ENR_SDMMC2EN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk \r
+#define RCC_APB2ENR_ADC1EN_Pos (8U) \r
+#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk \r
+#define RCC_APB2ENR_ADC2EN_Pos (9U) \r
+#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk \r
+#define RCC_APB2ENR_ADC3EN_Pos (10U) \r
+#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk \r
+#define RCC_APB2ENR_SDMMC1EN_Pos (11U) \r
+#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk \r
+#define RCC_APB2ENR_SPI1EN_Pos (12U) \r
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk \r
+#define RCC_APB2ENR_SPI4EN_Pos (13U) \r
+#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk \r
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U) \r
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk \r
+#define RCC_APB2ENR_TIM9EN_Pos (16U) \r
+#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk \r
+#define RCC_APB2ENR_TIM10EN_Pos (17U) \r
+#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk \r
+#define RCC_APB2ENR_TIM11EN_Pos (18U) \r
+#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk \r
+#define RCC_APB2ENR_SPI5EN_Pos (20U) \r
+#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk \r
+#define RCC_APB2ENR_SPI6EN_Pos (21U) \r
+#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk \r
+#define RCC_APB2ENR_SAI1EN_Pos (22U) \r
+#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk \r
+#define RCC_APB2ENR_SAI2EN_Pos (23U) \r
+#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk \r
+#define RCC_APB2ENR_LTDCEN_Pos (26U) \r
+#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */\r
+#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk \r
+#define RCC_APB2ENR_DFSDM1EN_Pos (29U) \r
+#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk \r
+#define RCC_APB2ENR_MDIOEN_Pos (30U) \r
+#define RCC_APB2ENR_MDIOEN_Msk (0x1UL << RCC_APB2ENR_MDIOEN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB2ENR_MDIOEN RCC_APB2ENR_MDIOEN_Msk \r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register *************/\r
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U) \r
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U) \r
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U) \r
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk \r
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U) \r
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U) \r
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U) \r
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U) \r
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U) \r
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U) \r
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U) \r
+#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk \r
+#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U) \r
+#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\r
+#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk \r
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) \r
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk \r
+#define RCC_AHB1LPENR_AXILPEN_Pos (13U) \r
+#define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */\r
+#define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk \r
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U) \r
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk \r
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U) \r
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk \r
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U) \r
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk \r
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U) \r
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk \r
+#define RCC_AHB1LPENR_DTCMLPEN_Pos (20U) \r
+#define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk \r
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U) \r
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk \r
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U) \r
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk \r
+#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U) \r
+#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk \r
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U) \r
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */\r
+#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk \r
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U) \r
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */\r
+#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk \r
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U) \r
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */\r
+#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk \r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U) \r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk \r
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U) \r
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk \r
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U) \r
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk \r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register *************/\r
+#define RCC_AHB2LPENR_DCMILPEN_Pos (0U) \r
+#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk \r
+#define RCC_AHB2LPENR_JPEGLPEN_Pos (1U) \r
+#define RCC_AHB2LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB2LPENR_JPEGLPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB2LPENR_JPEGLPEN RCC_AHB2LPENR_JPEGLPEN_Msk \r
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U) \r
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk \r
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U) \r
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk \r
+\r
+/******************** Bit definition for RCC_AHB3LPENR register *************/\r
+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U) \r
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk \r
+#define RCC_AHB3LPENR_QSPILPEN_Pos (1U) \r
+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk \r
+/******************** Bit definition for RCC_APB1LPENR register *************/\r
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U) \r
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk \r
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U) \r
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk \r
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U) \r
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk \r
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U) \r
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk \r
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U) \r
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk \r
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U) \r
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk \r
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U) \r
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk \r
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U) \r
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk \r
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U) \r
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk \r
+#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U) \r
+#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk \r
+#define RCC_APB1LPENR_RTCLPEN_Pos (10U) \r
+#define RCC_APB1LPENR_RTCLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCLPEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk \r
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U) \r
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk \r
+#define RCC_APB1LPENR_CAN3LPEN_Pos (13U) \r
+#define RCC_APB1LPENR_CAN3LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk \r
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U) \r
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk \r
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U) \r
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk \r
+#define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U) \r
+#define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk \r
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U) \r
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk \r
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U) \r
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk \r
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U) \r
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk \r
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U) \r
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk \r
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U) \r
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk \r
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U) \r
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk \r
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U) \r
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk \r
+#define RCC_APB1LPENR_I2C4LPEN_Pos (24U) \r
+#define RCC_APB1LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */\r
+#define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk \r
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U) \r
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk \r
+#define RCC_APB1LPENR_CAN2LPEN_Pos (26U) \r
+#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\r
+#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk \r
+#define RCC_APB1LPENR_CECLPEN_Pos (27U) \r
+#define RCC_APB1LPENR_CECLPEN_Msk (0x1UL << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */\r
+#define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk \r
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U) \r
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk \r
+#define RCC_APB1LPENR_DACLPEN_Pos (29U) \r
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk \r
+#define RCC_APB1LPENR_UART7LPEN_Pos (30U) \r
+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk \r
+#define RCC_APB1LPENR_UART8LPEN_Pos (31U) \r
+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk \r
+\r
+/******************** Bit definition for RCC_APB2LPENR register *************/\r
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) \r
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk \r
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U) \r
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk \r
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U) \r
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk \r
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U) \r
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk \r
+#define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U) \r
+#define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk \r
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U) \r
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk \r
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U) \r
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk \r
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U) \r
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk \r
+#define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U) \r
+#define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk \r
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) \r
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk \r
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) \r
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk \r
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U) \r
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk \r
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U) \r
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk \r
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U) \r
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk \r
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U) \r
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk \r
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) \r
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk \r
+#define RCC_APB2LPENR_SPI6LPEN_Pos (21U) \r
+#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk \r
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U) \r
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk \r
+#define RCC_APB2LPENR_SAI2LPEN_Pos (23U) \r
+#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk \r
+#define RCC_APB2LPENR_LTDCLPEN_Pos (26U) \r
+#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */\r
+#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk \r
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos (29U) \r
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk \r
+#define RCC_APB2LPENR_MDIOLPEN_Pos (30U) \r
+#define RCC_APB2LPENR_MDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_MDIOLPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB2LPENR_MDIOLPEN RCC_APB2LPENR_MDIOLPEN_Msk \r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON_Pos (0U) \r
+#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */\r
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk \r
+#define RCC_BDCR_LSERDY_Pos (1U) \r
+#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */\r
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk \r
+#define RCC_BDCR_LSEBYP_Pos (2U) \r
+#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */\r
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk \r
+#define RCC_BDCR_LSEDRV_Pos (3U) \r
+#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */\r
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk \r
+#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */\r
+#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */\r
+#define RCC_BDCR_RTCSEL_Pos (8U) \r
+#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */\r
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk \r
+#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */\r
+#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */\r
+#define RCC_BDCR_RTCEN_Pos (15U) \r
+#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */\r
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk \r
+#define RCC_BDCR_BDRST_Pos (16U) \r
+#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */\r
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk \r
+\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION_Pos (0U) \r
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk \r
+#define RCC_CSR_LSIRDY_Pos (1U) \r
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */\r
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk \r
+#define RCC_CSR_RMVF_Pos (24U) \r
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */\r
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk \r
+#define RCC_CSR_BORRSTF_Pos (25U) \r
+#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */\r
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk \r
+#define RCC_CSR_PINRSTF_Pos (26U) \r
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */\r
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk \r
+#define RCC_CSR_PORRSTF_Pos (27U) \r
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */\r
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk \r
+#define RCC_CSR_SFTRSTF_Pos (28U) \r
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */\r
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk \r
+#define RCC_CSR_IWDGRSTF_Pos (29U) \r
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */\r
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk \r
+#define RCC_CSR_WWDGRSTF_Pos (30U) \r
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */\r
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk \r
+#define RCC_CSR_LPWRRSTF_Pos (31U) \r
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */\r
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk \r
+\r
+/******************** Bit definition for RCC_SSCGR register *****************/\r
+#define RCC_SSCGR_MODPER_Pos (0U) \r
+#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */\r
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk \r
+#define RCC_SSCGR_INCSTEP_Pos (13U) \r
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */\r
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk \r
+#define RCC_SSCGR_SPREADSEL_Pos (30U) \r
+#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */\r
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk \r
+#define RCC_SSCGR_SSCGEN_Pos (31U) \r
+#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */\r
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk \r
+\r
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) \r
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk \r
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U) \r
+#define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk \r
+#define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U) \r
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk \r
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) \r
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk \r
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for RCC_PLLSAICFGR register ************/\r
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U) \r
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */\r
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk \r
+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U) \r
+#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */\r
+#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk \r
+#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U) \r
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk \r
+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U) \r
+#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk \r
+#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for RCC_DCKCFGR1 register ***************/\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U) \r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk \r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U) \r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk \r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) \r
+#define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk \r
+#define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */\r
+\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)\r
+ */\r
+#define RCC_SAI1SEL_PLLSRC_SUPPORT\r
+#define RCC_DCKCFGR1_SAI1SEL_Pos (20U) \r
+#define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00300000 */\r
+#define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk \r
+#define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00100000 */\r
+#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */\r
+\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)\r
+ */\r
+#define RCC_SAI2SEL_PLLSRC_SUPPORT\r
+#define RCC_DCKCFGR1_SAI2SEL_Pos (22U) \r
+#define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00C00000 */\r
+#define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk \r
+#define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00400000 */\r
+#define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00800000 */\r
+\r
+#define RCC_DCKCFGR1_TIMPRE_Pos (24U) \r
+#define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos) /*!< 0x01000000 */\r
+#define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk \r
+#define RCC_DCKCFGR1_DFSDM1SEL_Pos (25U) \r
+#define RCC_DCKCFGR1_DFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_DFSDM1SEL_Pos) /*!< 0x02000000 */\r
+#define RCC_DCKCFGR1_DFSDM1SEL RCC_DCKCFGR1_DFSDM1SEL_Msk \r
+#define RCC_DCKCFGR1_ADFSDM1SEL_Pos (26U) \r
+#define RCC_DCKCFGR1_ADFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_ADFSDM1SEL_Pos) /*!< 0x04000000 */\r
+#define RCC_DCKCFGR1_ADFSDM1SEL RCC_DCKCFGR1_ADFSDM1SEL_Msk \r
+\r
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/\r
+#define RCC_DCKCFGR2_USART1SEL_Pos (0U) \r
+#define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */\r
+#define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk \r
+#define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */\r
+#define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */\r
+#define RCC_DCKCFGR2_USART2SEL_Pos (2U) \r
+#define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */\r
+#define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk \r
+#define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */\r
+#define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */\r
+#define RCC_DCKCFGR2_USART3SEL_Pos (4U) \r
+#define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */\r
+#define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk \r
+#define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */\r
+#define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */\r
+#define RCC_DCKCFGR2_UART4SEL_Pos (6U) \r
+#define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */\r
+#define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk \r
+#define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */\r
+#define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */\r
+#define RCC_DCKCFGR2_UART5SEL_Pos (8U) \r
+#define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */\r
+#define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk \r
+#define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */\r
+#define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */\r
+#define RCC_DCKCFGR2_USART6SEL_Pos (10U) \r
+#define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */\r
+#define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk \r
+#define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */\r
+#define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */\r
+#define RCC_DCKCFGR2_UART7SEL_Pos (12U) \r
+#define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */\r
+#define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk \r
+#define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */\r
+#define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */\r
+#define RCC_DCKCFGR2_UART8SEL_Pos (14U) \r
+#define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */\r
+#define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk \r
+#define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */\r
+#define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */\r
+#define RCC_DCKCFGR2_I2C1SEL_Pos (16U) \r
+#define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00030000 */\r
+#define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk \r
+#define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00010000 */\r
+#define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00020000 */\r
+#define RCC_DCKCFGR2_I2C2SEL_Pos (18U) \r
+#define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x000C0000 */\r
+#define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk \r
+#define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00040000 */\r
+#define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00080000 */\r
+#define RCC_DCKCFGR2_I2C3SEL_Pos (20U) \r
+#define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00300000 */\r
+#define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk \r
+#define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00100000 */\r
+#define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00200000 */\r
+#define RCC_DCKCFGR2_I2C4SEL_Pos (22U) \r
+#define RCC_DCKCFGR2_I2C4SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00C00000 */\r
+#define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk \r
+#define RCC_DCKCFGR2_I2C4SEL_0 (0x1UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00400000 */\r
+#define RCC_DCKCFGR2_I2C4SEL_1 (0x2UL << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00800000 */\r
+#define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U) \r
+#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */\r
+#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk \r
+#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */\r
+#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */\r
+#define RCC_DCKCFGR2_CECSEL_Pos (26U) \r
+#define RCC_DCKCFGR2_CECSEL_Msk (0x1UL << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */\r
+#define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk \r
+#define RCC_DCKCFGR2_CK48MSEL_Pos (27U) \r
+#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\r
+#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk \r
+#define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U) \r
+#define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */\r
+#define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk \r
+#define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U) \r
+#define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC2SEL_Pos) /*!< 0x20000000 */\r
+#define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN_Pos (2U) \r
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */\r
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk \r
+#define RNG_CR_IE_Pos (3U) \r
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */\r
+#define RNG_CR_IE RNG_CR_IE_Msk \r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY_Pos (0U) \r
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */\r
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk \r
+#define RNG_SR_CECS_Pos (1U) \r
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */\r
+#define RNG_SR_CECS RNG_SR_CECS_Msk \r
+#define RNG_SR_SECS_Pos (2U) \r
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */\r
+#define RNG_SR_SECS RNG_SR_SECS_Msk \r
+#define RNG_SR_CEIS_Pos (5U) \r
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */\r
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk \r
+#define RNG_SR_SEIS_Pos (6U) \r
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */\r
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM_Pos (22U) \r
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TR_PM RTC_TR_PM_Msk \r
+#define RTC_TR_HT_Pos (20U) \r
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TR_HT RTC_TR_HT_Msk \r
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TR_HU_Pos (16U) \r
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TR_HU RTC_TR_HU_Msk \r
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TR_MNT_Pos (12U) \r
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TR_MNT RTC_TR_MNT_Msk \r
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TR_MNU_Pos (8U) \r
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TR_MNU RTC_TR_MNU_Msk \r
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TR_ST_Pos (4U) \r
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TR_ST RTC_TR_ST_Msk \r
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TR_SU_Pos (0U) \r
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TR_SU RTC_TR_SU_Msk \r
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT_Pos (20U) \r
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */\r
+#define RTC_DR_YT RTC_DR_YT_Msk \r
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */\r
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */\r
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */\r
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */\r
+#define RTC_DR_YU_Pos (16U) \r
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */\r
+#define RTC_DR_YU RTC_DR_YU_Msk \r
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */\r
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */\r
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */\r
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */\r
+#define RTC_DR_WDU_Pos (13U) \r
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_DR_WDU RTC_DR_WDU_Msk \r
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_DR_MT_Pos (12U) \r
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_DR_MT RTC_DR_MT_Msk \r
+#define RTC_DR_MU_Pos (8U) \r
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_DR_MU RTC_DR_MU_Msk \r
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_DR_DT_Pos (4U) \r
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_DR_DT RTC_DR_DT_Msk \r
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_DR_DU_Pos (0U) \r
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_DR_DU RTC_DR_DU_Msk \r
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_ITSE_Pos (24U) \r
+#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */\r
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk \r
+#define RTC_CR_COE_Pos (23U) \r
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */\r
+#define RTC_CR_COE RTC_CR_COE_Msk \r
+#define RTC_CR_OSEL_Pos (21U) \r
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */\r
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk \r
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */\r
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */\r
+#define RTC_CR_POL_Pos (20U) \r
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */\r
+#define RTC_CR_POL RTC_CR_POL_Msk \r
+#define RTC_CR_COSEL_Pos (19U) \r
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */\r
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk \r
+#define RTC_CR_BKP_Pos (18U) \r
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */\r
+#define RTC_CR_BKP RTC_CR_BKP_Msk \r
+#define RTC_CR_SUB1H_Pos (17U) \r
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */\r
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk \r
+#define RTC_CR_ADD1H_Pos (16U) \r
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */\r
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk \r
+#define RTC_CR_TSIE_Pos (15U) \r
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */\r
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk \r
+#define RTC_CR_WUTIE_Pos (14U) \r
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */\r
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk \r
+#define RTC_CR_ALRBIE_Pos (13U) \r
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */\r
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk \r
+#define RTC_CR_ALRAIE_Pos (12U) \r
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */\r
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk \r
+#define RTC_CR_TSE_Pos (11U) \r
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */\r
+#define RTC_CR_TSE RTC_CR_TSE_Msk \r
+#define RTC_CR_WUTE_Pos (10U) \r
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */\r
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk \r
+#define RTC_CR_ALRBE_Pos (9U) \r
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */\r
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk \r
+#define RTC_CR_ALRAE_Pos (8U) \r
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */\r
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk \r
+#define RTC_CR_FMT_Pos (6U) \r
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */\r
+#define RTC_CR_FMT RTC_CR_FMT_Msk \r
+#define RTC_CR_BYPSHAD_Pos (5U) \r
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */\r
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk \r
+#define RTC_CR_REFCKON_Pos (4U) \r
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */\r
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk \r
+#define RTC_CR_TSEDGE_Pos (3U) \r
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */\r
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk \r
+#define RTC_CR_WUCKSEL_Pos (0U) \r
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */\r
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk \r
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */\r
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */\r
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */\r
+\r
+/* Legacy define */\r
+#define RTC_CR_BCK RTC_CR_BKP\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_ITSF_Pos (17U) \r
+#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */\r
+#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk \r
+#define RTC_ISR_RECALPF_Pos (16U) \r
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */\r
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk \r
+#define RTC_ISR_TAMP3F_Pos (15U) \r
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */\r
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk \r
+#define RTC_ISR_TAMP2F_Pos (14U) \r
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */\r
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk \r
+#define RTC_ISR_TAMP1F_Pos (13U) \r
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */\r
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk \r
+#define RTC_ISR_TSOVF_Pos (12U) \r
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */\r
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk \r
+#define RTC_ISR_TSF_Pos (11U) \r
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */\r
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk \r
+#define RTC_ISR_WUTF_Pos (10U) \r
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */\r
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk \r
+#define RTC_ISR_ALRBF_Pos (9U) \r
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */\r
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk \r
+#define RTC_ISR_ALRAF_Pos (8U) \r
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */\r
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk \r
+#define RTC_ISR_INIT_Pos (7U) \r
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */\r
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk \r
+#define RTC_ISR_INITF_Pos (6U) \r
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */\r
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk \r
+#define RTC_ISR_RSF_Pos (5U) \r
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */\r
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk \r
+#define RTC_ISR_INITS_Pos (4U) \r
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */\r
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk \r
+#define RTC_ISR_SHPF_Pos (3U) \r
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */\r
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk \r
+#define RTC_ISR_WUTWF_Pos (2U) \r
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */\r
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk \r
+#define RTC_ISR_ALRBWF_Pos (1U) \r
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */\r
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk \r
+#define RTC_ISR_ALRAWF_Pos (0U) \r
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */\r
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk \r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A_Pos (16U) \r
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */\r
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk \r
+#define RTC_PRER_PREDIV_S_Pos (0U) \r
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */\r
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk \r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT_Pos (0U) \r
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */\r
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk \r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4_Pos (31U) \r
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk \r
+#define RTC_ALRMAR_WDSEL_Pos (30U) \r
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk \r
+#define RTC_ALRMAR_DT_Pos (28U) \r
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk \r
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMAR_DU_Pos (24U) \r
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk \r
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMAR_MSK3_Pos (23U) \r
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk \r
+#define RTC_ALRMAR_PM_Pos (22U) \r
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk \r
+#define RTC_ALRMAR_HT_Pos (20U) \r
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk \r
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMAR_HU_Pos (16U) \r
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk \r
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMAR_MSK2_Pos (15U) \r
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk \r
+#define RTC_ALRMAR_MNT_Pos (12U) \r
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk \r
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMAR_MNU_Pos (8U) \r
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk \r
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMAR_MSK1_Pos (7U) \r
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk \r
+#define RTC_ALRMAR_ST_Pos (4U) \r
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk \r
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMAR_SU_Pos (0U) \r
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk \r
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4_Pos (31U) \r
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk \r
+#define RTC_ALRMBR_WDSEL_Pos (30U) \r
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk \r
+#define RTC_ALRMBR_DT_Pos (28U) \r
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk \r
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMBR_DU_Pos (24U) \r
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk \r
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBR_MSK3_Pos (23U) \r
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk \r
+#define RTC_ALRMBR_PM_Pos (22U) \r
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk \r
+#define RTC_ALRMBR_HT_Pos (20U) \r
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk \r
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMBR_HU_Pos (16U) \r
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk \r
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMBR_MSK2_Pos (15U) \r
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk \r
+#define RTC_ALRMBR_MNT_Pos (12U) \r
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk \r
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMBR_MNU_Pos (8U) \r
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk \r
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMBR_MSK1_Pos (7U) \r
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk \r
+#define RTC_ALRMBR_ST_Pos (4U) \r
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk \r
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMBR_SU_Pos (0U) \r
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk \r
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY_Pos (0U) \r
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */\r
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk \r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS_Pos (0U) \r
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_SSR_SS RTC_SSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS_Pos (0U) \r
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */\r
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk \r
+#define RTC_SHIFTR_ADD1S_Pos (31U) \r
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */\r
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk \r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM_Pos (22U) \r
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk \r
+#define RTC_TSTR_HT_Pos (20U) \r
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk \r
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TSTR_HU_Pos (16U) \r
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk \r
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TSTR_MNT_Pos (12U) \r
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk \r
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TSTR_MNU_Pos (8U) \r
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk \r
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSTR_ST_Pos (4U) \r
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk \r
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TSTR_SU_Pos (0U) \r
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk \r
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU_Pos (13U) \r
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk \r
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_TSDR_MT_Pos (12U) \r
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk \r
+#define RTC_TSDR_MU_Pos (8U) \r
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk \r
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSDR_DT_Pos (4U) \r
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk \r
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_TSDR_DU_Pos (0U) \r
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk \r
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS_Pos (0U) \r
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP_Pos (15U) \r
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */\r
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk \r
+#define RTC_CALR_CALW8_Pos (14U) \r
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */\r
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk \r
+#define RTC_CALR_CALW16_Pos (13U) \r
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */\r
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk \r
+#define RTC_CALR_CALM_Pos (0U) \r
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */\r
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk \r
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */\r
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */\r
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */\r
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */\r
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */\r
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */\r
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */\r
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */\r
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */\r
+\r
+/******************** Bits definition for RTC_TAMPCR register ****************/\r
+#define RTC_TAMPCR_TAMP3MF_Pos (24U) \r
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */\r
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk \r
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) \r
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */\r
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk \r
+#define RTC_TAMPCR_TAMP3IE_Pos (22U) \r
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */\r
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk \r
+#define RTC_TAMPCR_TAMP2MF_Pos (21U) \r
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */\r
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk \r
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) \r
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */\r
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk \r
+#define RTC_TAMPCR_TAMP2IE_Pos (19U) \r
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */\r
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk \r
+#define RTC_TAMPCR_TAMP1MF_Pos (18U) \r
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */\r
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk \r
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) \r
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */\r
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk \r
+#define RTC_TAMPCR_TAMP1IE_Pos (16U) \r
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */\r
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk \r
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) \r
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */\r
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk \r
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U) \r
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */\r
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk \r
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */\r
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */\r
+#define RTC_TAMPCR_TAMPFLT_Pos (11U) \r
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */\r
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk \r
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */\r
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */\r
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U) \r
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */\r
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk \r
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */\r
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */\r
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */\r
+#define RTC_TAMPCR_TAMPTS_Pos (7U) \r
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */\r
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk \r
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U) \r
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */\r
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk \r
+#define RTC_TAMPCR_TAMP3E_Pos (5U) \r
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */\r
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk \r
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U) \r
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */\r
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk \r
+#define RTC_TAMPCR_TAMP2E_Pos (3U) \r
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */\r
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk \r
+#define RTC_TAMPCR_TAMPIE_Pos (2U) \r
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */\r
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk \r
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U) \r
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */\r
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk \r
+#define RTC_TAMPCR_TAMP1E_Pos (0U) \r
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */\r
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk \r
+\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS_Pos (24U) \r
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk \r
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMASSR_SS_Pos (0U) \r
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS_Pos (24U) \r
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk \r
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBSSR_SS_Pos (0U) \r
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk \r
+\r
+/******************** Bits definition for RTC_OR register ****************/\r
+#define RTC_OR_TSINSEL_Pos (1U) \r
+#define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000006 */\r
+#define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk \r
+#define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000002 */\r
+#define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000004 */\r
+#define RTC_OR_ALARMOUTTYPE_Pos (3U) \r
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000008 */\r
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk\r
+/* Legacy defines*/ \r
+#define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R_Pos (0U) \r
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP0R RTC_BKP0R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R_Pos (0U) \r
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP1R RTC_BKP1R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R_Pos (0U) \r
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP2R RTC_BKP2R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R_Pos (0U) \r
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP3R RTC_BKP3R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R_Pos (0U) \r
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP4R RTC_BKP4R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R_Pos (0U) \r
+#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP5R RTC_BKP5R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R_Pos (0U) \r
+#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP6R RTC_BKP6R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R_Pos (0U) \r
+#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP7R RTC_BKP7R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R_Pos (0U) \r
+#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP8R RTC_BKP8R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R_Pos (0U) \r
+#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP9R RTC_BKP9R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R_Pos (0U) \r
+#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP10R RTC_BKP10R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R_Pos (0U) \r
+#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP11R RTC_BKP11R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R_Pos (0U) \r
+#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP12R RTC_BKP12R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R_Pos (0U) \r
+#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP13R RTC_BKP13R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R_Pos (0U) \r
+#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP14R RTC_BKP14R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R_Pos (0U) \r
+#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP15R RTC_BKP15R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R_Pos (0U) \r
+#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP16R RTC_BKP16R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R_Pos (0U) \r
+#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP17R RTC_BKP17R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R_Pos (0U) \r
+#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP18R RTC_BKP18R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R_Pos (0U) \r
+#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP19R RTC_BKP19R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R_Pos (0U) \r
+#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP20R RTC_BKP20R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R_Pos (0U) \r
+#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP21R RTC_BKP21R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R_Pos (0U) \r
+#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP22R RTC_BKP22R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R_Pos (0U) \r
+#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP23R RTC_BKP23R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R_Pos (0U) \r
+#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP24R RTC_BKP24R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R_Pos (0U) \r
+#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP25R RTC_BKP25R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R_Pos (0U) \r
+#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP26R RTC_BKP26R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R_Pos (0U) \r
+#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP27R RTC_BKP27R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R_Pos (0U) \r
+#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP28R RTC_BKP28R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R_Pos (0U) \r
+#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP29R RTC_BKP29R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R_Pos (0U) \r
+#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP30R RTC_BKP30R_Msk \r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R_Pos (0U) \r
+#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP31R RTC_BKP31R_Msk \r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER 0x00000020U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Audio Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SAI_GCR register *******************/\r
+#define SAI_GCR_SYNCIN_Pos (0U) \r
+#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */\r
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
+#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */\r
+#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */\r
+\r
+#define SAI_GCR_SYNCOUT_Pos (4U) \r
+#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */\r
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */\r
+#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */\r
+\r
+/******************* Bit definition for SAI_xCR1 register *******************/\r
+#define SAI_xCR1_MODE_Pos (0U) \r
+#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */\r
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */\r
+#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */\r
+#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */\r
+\r
+#define SAI_xCR1_PRTCFG_Pos (2U) \r
+#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */\r
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
+#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */\r
+\r
+#define SAI_xCR1_DS_Pos (5U) \r
+#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */\r
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */\r
+#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */\r
+#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xCR1_LSBFIRST_Pos (8U) \r
+#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */\r
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */\r
+#define SAI_xCR1_CKSTR_Pos (9U) \r
+#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */\r
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */\r
+\r
+#define SAI_xCR1_SYNCEN_Pos (10U) \r
+#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */\r
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */\r
+#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */\r
+\r
+#define SAI_xCR1_MONO_Pos (12U) \r
+#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */\r
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */\r
+#define SAI_xCR1_OUTDRIV_Pos (13U) \r
+#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */\r
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */\r
+#define SAI_xCR1_SAIEN_Pos (16U) \r
+#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */\r
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */\r
+#define SAI_xCR1_DMAEN_Pos (17U) \r
+#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */\r
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */\r
+#define SAI_xCR1_NODIV_Pos (19U) \r
+#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */\r
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */\r
+\r
+#define SAI_xCR1_MCKDIV_Pos (20U) \r
+#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */\r
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */\r
+#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */\r
+#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */\r
+#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */\r
+#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */\r
+\r
+/******************* Bit definition for SAI_xCR2 register *******************/\r
+#define SAI_xCR2_FTH_Pos (0U) \r
+#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */\r
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */\r
+#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */\r
+#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */\r
+#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */\r
+\r
+#define SAI_xCR2_FFLUSH_Pos (3U) \r
+#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */\r
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */\r
+#define SAI_xCR2_TRIS_Pos (4U) \r
+#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */\r
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE_Pos (5U) \r
+#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */\r
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */\r
+#define SAI_xCR2_MUTEVAL_Pos (6U) \r
+#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */\r
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */\r
+\r
+#define SAI_xCR2_MUTECNT_Pos (7U) \r
+#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */\r
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */\r
+#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */\r
+#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */\r
+#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */\r
+#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */\r
+#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */\r
+\r
+#define SAI_xCR2_CPL_Pos (13U) \r
+#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */\r
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */\r
+\r
+#define SAI_xCR2_COMP_Pos (14U) \r
+#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */\r
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */\r
+#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */\r
+\r
+/****************** Bit definition for SAI_xFRCR register *******************/\r
+#define SAI_xFRCR_FRL_Pos (0U) \r
+#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */\r
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */\r
+#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */\r
+#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */\r
+#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */\r
+#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */\r
+#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */\r
+#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */\r
+#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */\r
+#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xFRCR_FSALL_Pos (8U) \r
+#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */\r
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */\r
+#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */\r
+#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */\r
+#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */\r
+#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */\r
+#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */\r
+#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */\r
+#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */\r
+\r
+#define SAI_xFRCR_FSDEF_Pos (16U) \r
+#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */\r
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPOL_Pos (17U) \r
+#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */\r
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */\r
+#define SAI_xFRCR_FSOFF_Pos (18U) \r
+#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */\r
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */\r
+\r
+/* Legacy define */\r
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL\r
+\r
+/****************** Bit definition for SAI_xSLOTR register *******************/\r
+#define SAI_xSLOTR_FBOFF_Pos (0U) \r
+#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */\r
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */\r
+#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */\r
+#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */\r
+#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */\r
+#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */\r
+#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */\r
+\r
+#define SAI_xSLOTR_SLOTSZ_Pos (6U) \r
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */\r
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */\r
+#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */\r
+#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xSLOTR_NBSLOT_Pos (8U) \r
+#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */\r
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
+#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */\r
+#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */\r
+#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */\r
+#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */\r
+\r
+#define SAI_xSLOTR_SLOTEN_Pos (16U) \r
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */\r
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */\r
+\r
+/******************* Bit definition for SAI_xIMR register *******************/\r
+#define SAI_xIMR_OVRUDRIE_Pos (0U) \r
+#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */\r
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */\r
+#define SAI_xIMR_MUTEDETIE_Pos (1U) \r
+#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */\r
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */\r
+#define SAI_xIMR_WCKCFGIE_Pos (2U) \r
+#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */\r
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */\r
+#define SAI_xIMR_FREQIE_Pos (3U) \r
+#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */\r
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */\r
+#define SAI_xIMR_CNRDYIE_Pos (4U) \r
+#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */\r
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */\r
+#define SAI_xIMR_AFSDETIE_Pos (5U) \r
+#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */\r
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */\r
+#define SAI_xIMR_LFSDETIE_Pos (6U) \r
+#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */\r
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */\r
+\r
+/******************** Bit definition for SAI_xSR register *******************/\r
+#define SAI_xSR_OVRUDR_Pos (0U) \r
+#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */\r
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */\r
+#define SAI_xSR_MUTEDET_Pos (1U) \r
+#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */\r
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */\r
+#define SAI_xSR_WCKCFG_Pos (2U) \r
+#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */\r
+#define SAI_xSR_FREQ_Pos (3U) \r
+#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */\r
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */\r
+#define SAI_xSR_CNRDY_Pos (4U) \r
+#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */\r
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */\r
+#define SAI_xSR_AFSDET_Pos (5U) \r
+#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */\r
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */\r
+#define SAI_xSR_LFSDET_Pos (6U) \r
+#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */\r
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */\r
+\r
+#define SAI_xSR_FLVL_Pos (16U) \r
+#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */\r
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */\r
+#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */\r
+#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */\r
+#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */\r
+\r
+/****************** Bit definition for SAI_xCLRFR register ******************/\r
+#define SAI_xCLRFR_COVRUDR_Pos (0U) \r
+#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */\r
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */\r
+#define SAI_xCLRFR_CMUTEDET_Pos (1U) \r
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */\r
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */\r
+#define SAI_xCLRFR_CWCKCFG_Pos (2U) \r
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */\r
+#define SAI_xCLRFR_CFREQ_Pos (3U) \r
+#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */\r
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */\r
+#define SAI_xCLRFR_CCNRDY_Pos (4U) \r
+#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */\r
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */\r
+#define SAI_xCLRFR_CAFSDET_Pos (5U) \r
+#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */\r
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */\r
+#define SAI_xCLRFR_CLFSDET_Pos (6U) \r
+#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */\r
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */\r
+\r
+/****************** Bit definition for SAI_xDR register *********************/\r
+#define SAI_xDR_DATA_Pos (0U) \r
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SPDIF-RX Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SPDIF_CR register *******************/\r
+#define SPDIFRX_CR_SPDIFEN_Pos (0U) \r
+#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */\r
+#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */\r
+#define SPDIFRX_CR_RXDMAEN_Pos (2U) \r
+#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */\r
+#define SPDIFRX_CR_RXSTEO_Pos (3U) \r
+#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */\r
+#define SPDIFRX_CR_DRFMT_Pos (4U) \r
+#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */\r
+#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */\r
+#define SPDIFRX_CR_PMSK_Pos (6U) \r
+#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */\r
+#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */\r
+#define SPDIFRX_CR_VMSK_Pos (7U) \r
+#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */\r
+#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */\r
+#define SPDIFRX_CR_CUMSK_Pos (8U) \r
+#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */\r
+#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */\r
+#define SPDIFRX_CR_PTMSK_Pos (9U) \r
+#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */\r
+#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */\r
+#define SPDIFRX_CR_CBDMAEN_Pos (10U) \r
+#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */\r
+#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */\r
+#define SPDIFRX_CR_CHSEL_Pos (11U) \r
+#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */\r
+#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */\r
+#define SPDIFRX_CR_NBTR_Pos (12U) \r
+#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */\r
+#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */\r
+#define SPDIFRX_CR_WFA_Pos (14U) \r
+#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */\r
+#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */\r
+#define SPDIFRX_CR_INSEL_Pos (16U) \r
+#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */\r
+#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */\r
+\r
+/******************* Bit definition for SPDIFRX_IMR register *******************/\r
+#define SPDIFRX_IMR_RXNEIE_Pos (0U) \r
+#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */\r
+#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */\r
+#define SPDIFRX_IMR_CSRNEIE_Pos (1U) \r
+#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */\r
+#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */\r
+#define SPDIFRX_IMR_PERRIE_Pos (2U) \r
+#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */\r
+#define SPDIFRX_IMR_OVRIE_Pos (3U) \r
+#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */\r
+#define SPDIFRX_IMR_SBLKIE_Pos (4U) \r
+#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */\r
+#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */\r
+#define SPDIFRX_IMR_SYNCDIE_Pos (5U) \r
+#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */\r
+#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */\r
+#define SPDIFRX_IMR_IFEIE_Pos (6U) \r
+#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */\r
+#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */\r
+\r
+/******************* Bit definition for SPDIFRX_SR register *******************/\r
+#define SPDIFRX_SR_RXNE_Pos (0U) \r
+#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */\r
+#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */\r
+#define SPDIFRX_SR_CSRNE_Pos (1U) \r
+#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */\r
+#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */\r
+#define SPDIFRX_SR_PERR_Pos (2U) \r
+#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */\r
+#define SPDIFRX_SR_OVR_Pos (3U) \r
+#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */\r
+#define SPDIFRX_SR_SBD_Pos (4U) \r
+#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */\r
+#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */\r
+#define SPDIFRX_SR_SYNCD_Pos (5U) \r
+#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */\r
+#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */\r
+#define SPDIFRX_SR_FERR_Pos (6U) \r
+#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */\r
+#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */\r
+#define SPDIFRX_SR_SERR_Pos (7U) \r
+#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */\r
+#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */\r
+#define SPDIFRX_SR_TERR_Pos (8U) \r
+#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */\r
+#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */\r
+#define SPDIFRX_SR_WIDTH5_Pos (16U) \r
+#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */\r
+#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */\r
+\r
+/******************* Bit definition for SPDIFRX_IFCR register *******************/\r
+#define SPDIFRX_IFCR_PERRCF_Pos (2U) \r
+#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */\r
+#define SPDIFRX_IFCR_OVRCF_Pos (3U) \r
+#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */\r
+#define SPDIFRX_IFCR_SBDCF_Pos (4U) \r
+#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */\r
+#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */\r
+#define SPDIFRX_IFCR_SYNCDCF_Pos (5U) \r
+#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */\r
+#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/\r
+#define SPDIFRX_DR0_DR_Pos (0U) \r
+#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */\r
+#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */\r
+#define SPDIFRX_DR0_PE_Pos (24U) \r
+#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */\r
+#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */\r
+#define SPDIFRX_DR0_V_Pos (25U) \r
+#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */\r
+#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */\r
+#define SPDIFRX_DR0_U_Pos (26U) \r
+#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */\r
+#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */\r
+#define SPDIFRX_DR0_C_Pos (27U) \r
+#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */\r
+#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */\r
+#define SPDIFRX_DR0_PT_Pos (28U) \r
+#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */\r
+#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/\r
+#define SPDIFRX_DR1_DR_Pos (8U) \r
+#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */\r
+#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */\r
+#define SPDIFRX_DR1_PT_Pos (4U) \r
+#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */\r
+#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */\r
+#define SPDIFRX_DR1_C_Pos (3U) \r
+#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */\r
+#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */\r
+#define SPDIFRX_DR1_U_Pos (2U) \r
+#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */\r
+#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */\r
+#define SPDIFRX_DR1_V_Pos (1U) \r
+#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */\r
+#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */\r
+#define SPDIFRX_DR1_PE_Pos (0U) \r
+#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */\r
+#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */\r
+\r
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/\r
+#define SPDIFRX_DR1_DRNL1_Pos (16U) \r
+#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */\r
+#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */\r
+#define SPDIFRX_DR1_DRNL2_Pos (0U) \r
+#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */\r
+#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */\r
+\r
+/******************* Bit definition for SPDIFRX_CSR register *******************/\r
+#define SPDIFRX_CSR_USR_Pos (0U) \r
+#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */\r
+#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */\r
+#define SPDIFRX_CSR_CS_Pos (16U) \r
+#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */\r
+#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */\r
+#define SPDIFRX_CSR_SOB_Pos (24U) \r
+#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */\r
+#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */\r
+\r
+/******************* Bit definition for SPDIFRX_DIR register *******************/\r
+#define SPDIFRX_DIR_THI_Pos (0U) \r
+#define SPDIFRX_DIR_THI_Msk (0x13FFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */\r
+#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */\r
+#define SPDIFRX_DIR_TLO_Pos (16U) \r
+#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */\r
+#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDMMC_POWER register ******************/\r
+#define SDMMC_POWER_PWRCTRL_Pos (0U) \r
+#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */\r
+#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x01 */\r
+#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x02 */\r
+\r
+/****************** Bit definition for SDMMC_CLKCR register ******************/\r
+#define SDMMC_CLKCR_CLKDIV_Pos (0U) \r
+#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */\r
+#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */\r
+#define SDMMC_CLKCR_CLKEN_Pos (8U) \r
+#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */\r
+#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */\r
+#define SDMMC_CLKCR_PWRSAV_Pos (9U) \r
+#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */\r
+#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */\r
+#define SDMMC_CLKCR_BYPASS_Pos (10U) \r
+#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */\r
+#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */\r
+\r
+#define SDMMC_CLKCR_WIDBUS_Pos (11U) \r
+#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */\r
+#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0800 */\r
+#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x1000 */\r
+\r
+#define SDMMC_CLKCR_NEGEDGE_Pos (13U) \r
+#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */\r
+#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */\r
+#define SDMMC_CLKCR_HWFC_EN_Pos (14U) \r
+#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */\r
+#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDMMC_ARG register *******************/\r
+#define SDMMC_ARG_CMDARG_Pos (0U) \r
+#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */\r
+\r
+/******************* Bit definition for SDMMC_CMD register *******************/\r
+#define SDMMC_CMD_CMDINDEX_Pos (0U) \r
+#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */\r
+#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */\r
+\r
+#define SDMMC_CMD_WAITRESP_Pos (6U) \r
+#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */\r
+#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0040 */\r
+#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0080 */\r
+\r
+#define SDMMC_CMD_WAITINT_Pos (8U) \r
+#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */\r
+#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */\r
+#define SDMMC_CMD_WAITPEND_Pos (9U) \r
+#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */\r
+#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDMMC_CMD_CPSMEN_Pos (10U) \r
+#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */\r
+#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDMMC_CMD_SDIOSUSPEND_Pos (11U) \r
+#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */\r
+#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */\r
+\r
+/***************** Bit definition for SDMMC_RESPCMD register *****************/\r
+#define SDMMC_RESPCMD_RESPCMD_Pos (0U) \r
+#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */\r
+#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */\r
+\r
+/****************** Bit definition for SDMMC_RESP0 register ******************/\r
+#define SDMMC_RESP0_CARDSTATUS0_Pos (0U) \r
+#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP1 register ******************/\r
+#define SDMMC_RESP1_CARDSTATUS1_Pos (0U) \r
+#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP2 register ******************/\r
+#define SDMMC_RESP2_CARDSTATUS2_Pos (0U) \r
+#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP3 register ******************/\r
+#define SDMMC_RESP3_CARDSTATUS3_Pos (0U) \r
+#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP4 register ******************/\r
+#define SDMMC_RESP4_CARDSTATUS4_Pos (0U) \r
+#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_DTIMER register *****************/\r
+#define SDMMC_DTIMER_DATATIME_Pos (0U) \r
+#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDMMC_DLEN register *******************/\r
+#define SDMMC_DLEN_DATALENGTH_Pos (0U) \r
+#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */\r
+\r
+/****************** Bit definition for SDMMC_DCTRL register ******************/\r
+#define SDMMC_DCTRL_DTEN_Pos (0U) \r
+#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */\r
+#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */\r
+#define SDMMC_DCTRL_DTDIR_Pos (1U) \r
+#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */\r
+#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */\r
+#define SDMMC_DCTRL_DTMODE_Pos (2U) \r
+#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */\r
+#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */\r
+#define SDMMC_DCTRL_DMAEN_Pos (3U) \r
+#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */\r
+#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */\r
+\r
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U) \r
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */\r
+\r
+#define SDMMC_DCTRL_RWSTART_Pos (8U) \r
+#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */\r
+#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */\r
+#define SDMMC_DCTRL_RWSTOP_Pos (9U) \r
+#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */\r
+#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */\r
+#define SDMMC_DCTRL_RWMOD_Pos (10U) \r
+#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */\r
+#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */\r
+#define SDMMC_DCTRL_SDIOEN_Pos (11U) \r
+#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */\r
+#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDMMC_DCOUNT register *****************/\r
+#define SDMMC_DCOUNT_DATACOUNT_Pos (0U) \r
+#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */\r
+\r
+/****************** Bit definition for SDMMC_STA registe ********************/\r
+#define SDMMC_STA_CCRCFAIL_Pos (0U) \r
+#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */\r
+#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */\r
+#define SDMMC_STA_DCRCFAIL_Pos (1U) \r
+#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */\r
+#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */\r
+#define SDMMC_STA_CTIMEOUT_Pos (2U) \r
+#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */\r
+#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */\r
+#define SDMMC_STA_DTIMEOUT_Pos (3U) \r
+#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */\r
+#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */\r
+#define SDMMC_STA_TXUNDERR_Pos (4U) \r
+#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */\r
+#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */\r
+#define SDMMC_STA_RXOVERR_Pos (5U) \r
+#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */\r
+#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */\r
+#define SDMMC_STA_CMDREND_Pos (6U) \r
+#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */\r
+#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */\r
+#define SDMMC_STA_CMDSENT_Pos (7U) \r
+#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */\r
+#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */\r
+#define SDMMC_STA_DATAEND_Pos (8U) \r
+#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */\r
+#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDMMC_STA_DBCKEND_Pos (10U) \r
+#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */\r
+#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */\r
+#define SDMMC_STA_CMDACT_Pos (11U) \r
+#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */\r
+#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */\r
+#define SDMMC_STA_TXACT_Pos (12U) \r
+#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */\r
+#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */\r
+#define SDMMC_STA_RXACT_Pos (13U) \r
+#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */\r
+#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */\r
+#define SDMMC_STA_TXFIFOHE_Pos (14U) \r
+#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */\r
+#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDMMC_STA_RXFIFOHF_Pos (15U) \r
+#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */\r
+#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDMMC_STA_TXFIFOF_Pos (16U) \r
+#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */\r
+#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */\r
+#define SDMMC_STA_RXFIFOF_Pos (17U) \r
+#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */\r
+#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */\r
+#define SDMMC_STA_TXFIFOE_Pos (18U) \r
+#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */\r
+#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */\r
+#define SDMMC_STA_RXFIFOE_Pos (19U) \r
+#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */\r
+#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */\r
+#define SDMMC_STA_TXDAVL_Pos (20U) \r
+#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */\r
+#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */\r
+#define SDMMC_STA_RXDAVL_Pos (21U) \r
+#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */\r
+#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */\r
+#define SDMMC_STA_SDIOIT_Pos (22U) \r
+#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */\r
+#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDMMC interrupt received */\r
+\r
+/******************* Bit definition for SDMMC_ICR register *******************/\r
+#define SDMMC_ICR_CCRCFAILC_Pos (0U) \r
+#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */\r
+#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_DCRCFAILC_Pos (1U) \r
+#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */\r
+#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_CTIMEOUTC_Pos (2U) \r
+#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */\r
+#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_DTIMEOUTC_Pos (3U) \r
+#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */\r
+#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_TXUNDERRC_Pos (4U) \r
+#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */\r
+#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */\r
+#define SDMMC_ICR_RXOVERRC_Pos (5U) \r
+#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */\r
+#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */\r
+#define SDMMC_ICR_CMDRENDC_Pos (6U) \r
+#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */\r
+#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */\r
+#define SDMMC_ICR_CMDSENTC_Pos (7U) \r
+#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */\r
+#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */\r
+#define SDMMC_ICR_DATAENDC_Pos (8U) \r
+#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */\r
+#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */\r
+#define SDMMC_ICR_DBCKENDC_Pos (10U) \r
+#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */\r
+#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */\r
+#define SDMMC_ICR_SDIOITC_Pos (22U) \r
+#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */\r
+#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDMMCIT flag clear bit */\r
+\r
+/****************** Bit definition for SDMMC_MASK register *******************/\r
+#define SDMMC_MASK_CCRCFAILIE_Pos (0U) \r
+#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */\r
+#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_DCRCFAILIE_Pos (1U) \r
+#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */\r
+#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_CTIMEOUTIE_Pos (2U) \r
+#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */\r
+#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_DTIMEOUTIE_Pos (3U) \r
+#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */\r
+#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_TXUNDERRIE_Pos (4U) \r
+#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */\r
+#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDMMC_MASK_RXOVERRIE_Pos (5U) \r
+#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */\r
+#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDMMC_MASK_CMDRENDIE_Pos (6U) \r
+#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */\r
+#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */\r
+#define SDMMC_MASK_CMDSENTIE_Pos (7U) \r
+#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */\r
+#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */\r
+#define SDMMC_MASK_DATAENDIE_Pos (8U) \r
+#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */\r
+#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */\r
+#define SDMMC_MASK_DBCKENDIE_Pos (10U) \r
+#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */\r
+#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */\r
+#define SDMMC_MASK_CMDACTIE_Pos (11U) \r
+#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */\r
+#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */\r
+#define SDMMC_MASK_TXACTIE_Pos (12U) \r
+#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */\r
+#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDMMC_MASK_RXACTIE_Pos (13U) \r
+#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */\r
+#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */\r
+#define SDMMC_MASK_TXFIFOHEIE_Pos (14U) \r
+#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */\r
+#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOHFIE_Pos (15U) \r
+#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */\r
+#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOFIE_Pos (16U) \r
+#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */\r
+#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOFIE_Pos (17U) \r
+#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */\r
+#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOEIE_Pos (18U) \r
+#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */\r
+#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOEIE_Pos (19U) \r
+#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */\r
+#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_TXDAVLIE_Pos (20U) \r
+#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */\r
+#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDMMC_MASK_RXDAVLIE_Pos (21U) \r
+#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */\r
+#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDMMC_MASK_SDIOITIE_Pos (22U) \r
+#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */\r
+#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */\r
+\r
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/\r
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U) \r
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\r
+#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDMMC_FIFO register *******************/\r
+#define SDMMC_FIFO_FIFODATA_Pos (0U) \r
+#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA_Pos (0U) \r
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */\r
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */\r
+#define SPI_CR1_CPOL_Pos (1U) \r
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */\r
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR_Pos (2U) \r
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */\r
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */\r
+#define SPI_CR1_BR_Pos (3U) \r
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */\r
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */\r
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */\r
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */\r
+#define SPI_CR1_SPE_Pos (6U) \r
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */\r
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST_Pos (7U) \r
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */\r
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */\r
+#define SPI_CR1_SSI_Pos (8U) \r
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */\r
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */\r
+#define SPI_CR1_SSM_Pos (9U) \r
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */\r
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */\r
+#define SPI_CR1_RXONLY_Pos (10U) \r
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */\r
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */\r
+#define SPI_CR1_CRCL_Pos (11U) \r
+#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */\r
+#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */\r
+#define SPI_CR1_CRCNEXT_Pos (12U) \r
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */\r
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN_Pos (13U) \r
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */\r
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE_Pos (14U) \r
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */\r
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE_Pos (15U) \r
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */\r
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN_Pos (0U) \r
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */\r
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN_Pos (1U) \r
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */\r
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE_Pos (2U) \r
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */\r
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */\r
+#define SPI_CR2_NSSP_Pos (3U) \r
+#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */\r
+#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */\r
+#define SPI_CR2_FRF_Pos (4U) \r
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */\r
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */\r
+#define SPI_CR2_ERRIE_Pos (5U) \r
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */\r
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE_Pos (6U) \r
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */\r
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE_Pos (7U) \r
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */\r
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */\r
+#define SPI_CR2_DS_Pos (8U) \r
+#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */\r
+#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */\r
+#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */\r
+#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */\r
+#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */\r
+#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */\r
+#define SPI_CR2_FRXTH_Pos (12U) \r
+#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */\r
+#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */\r
+#define SPI_CR2_LDMARX_Pos (13U) \r
+#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */\r
+#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */\r
+#define SPI_CR2_LDMATX_Pos (14U) \r
+#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */\r
+#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE_Pos (0U) \r
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */\r
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE_Pos (1U) \r
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */\r
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE_Pos (2U) \r
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */\r
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */\r
+#define SPI_SR_UDR_Pos (3U) \r
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */\r
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */\r
+#define SPI_SR_CRCERR_Pos (4U) \r
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */\r
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */\r
+#define SPI_SR_MODF_Pos (5U) \r
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */\r
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */\r
+#define SPI_SR_OVR_Pos (6U) \r
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */\r
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */\r
+#define SPI_SR_BSY_Pos (7U) \r
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */\r
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */\r
+#define SPI_SR_FRE_Pos (8U) \r
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */\r
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */\r
+#define SPI_SR_FRLVL_Pos (9U) \r
+#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */\r
+#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */\r
+#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */\r
+#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */\r
+#define SPI_SR_FTLVL_Pos (11U) \r
+#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */\r
+#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */\r
+#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */\r
+#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR_Pos (0U) \r
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */\r
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY_Pos (0U) \r
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */\r
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC_Pos (0U) \r
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */\r
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC_Pos (0U) \r
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */\r
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN_Pos (0U) \r
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */\r
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */\r
+#define SPI_I2SCFGR_DATLEN_Pos (1U) \r
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */\r
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */\r
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */\r
+#define SPI_I2SCFGR_CKPOL_Pos (3U) \r
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */\r
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */\r
+#define SPI_I2SCFGR_I2SSTD_Pos (4U) \r
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */\r
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */\r
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */\r
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U) \r
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */\r
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */\r
+#define SPI_I2SCFGR_I2SCFG_Pos (8U) \r
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */\r
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */\r
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */\r
+#define SPI_I2SCFGR_I2SE_Pos (10U) \r
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */\r
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD_Pos (11U) \r
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */\r
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */\r
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U) \r
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */\r
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV_Pos (0U) \r
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */\r
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD_Pos (8U) \r
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */\r
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE_Pos (9U) \r
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */\r
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/\r
+#define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U) \r
+#define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk /*!< Boot information after Reset */\r
+\r
+#define SYSCFG_MEMRMP_SWP_FB_Pos (8U) \r
+#define SYSCFG_MEMRMP_SWP_FB_Msk (0x1UL << SYSCFG_MEMRMP_SWP_FB_Pos) /*!< 0x00000100 */\r
+#define SYSCFG_MEMRMP_SWP_FB SYSCFG_MEMRMP_SWP_FB_Msk /*!< User Flash Bank swap */\r
+\r
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U) \r
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */\r
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC Memory Mapping swapping */\r
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */\r
+#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */\r
+\r
+/****************** Bit definition for SYSCFG_PMC register ******************/\r
+#define SYSCFG_PMC_I2C1_FMP_Pos (0U) \r
+#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C2_FMP_Pos (1U) \r
+#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */\r
+#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C3_FMP_Pos (2U) \r
+#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */\r
+#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C4_FMP_Pos (3U) \r
+#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */\r
+#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U) \r
+#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */\r
+#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U) \r
+#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */\r
+#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U) \r
+#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */\r
+#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U) \r
+#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */\r
+#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */\r
+\r
+#define SYSCFG_PMC_ADCxDC2_Pos (16U) \r
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */\r
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC1DC2_Pos (16U) \r
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC2DC2_Pos (17U) \r
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */\r
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC3DC2_Pos (18U) \r
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */\r
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+\r
+#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U) \r
+#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */\r
+#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U) \r
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U) \r
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U) \r
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U) \r
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */\r
+/**\r
+ * @brief EXTI0 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */\r
+\r
+/**\r
+ * @brief EXTI1 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */\r
+\r
+/**\r
+ * @brief EXTI2 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */\r
+\r
+/**\r
+ * @brief EXTI3 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U) \r
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U) \r
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U) \r
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U) \r
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */\r
+/**\r
+ * @brief EXTI4 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */\r
+\r
+/**\r
+ * @brief EXTI5 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */\r
+\r
+/**\r
+ * @brief EXTI6 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */\r
+\r
+/**\r
+ * @brief EXTI7 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U) \r
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U) \r
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U) \r
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U) \r
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */\r
+\r
+/**\r
+ * @brief EXTI8 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */\r
+\r
+/**\r
+ * @brief EXTI9 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */\r
+\r
+/**\r
+ * @brief EXTI10 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */\r
+\r
+/**\r
+ * @brief EXTI11 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */\r
+\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U) \r
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U) \r
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U) \r
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U) \r
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */\r
+/**\r
+ * @brief EXTI12 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */\r
+\r
+/**\r
+ * @brief EXTI13 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */\r
+\r
+/**\r
+ * @brief EXTI14 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */\r
+\r
+/**\r
+ * @brief EXTI15 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */\r
+\r
+/****************** Bit definition for SYSCFG_CBR register ******************/\r
+#define SYSCFG_CBR_CLL_Pos (0U) \r
+#define SYSCFG_CBR_CLL_Msk (0x1UL << SYSCFG_CBR_CLL_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!<Core Lockup Lock */\r
+#define SYSCFG_CBR_PVDL_Pos (2U) \r
+#define SYSCFG_CBR_PVDL_Msk (0x1UL << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */\r
+#define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!<PVD Lock */\r
+\r
+/****************** Bit definition for SYSCFG_CMPCR register ****************/\r
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U) \r
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell power-down */\r
+#define SYSCFG_CMPCR_READY_Pos (8U) \r
+#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */\r
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell ready flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)\r
+ */\r
+#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN_Pos (0U) \r
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */\r
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */\r
+#define TIM_CR1_UDIS_Pos (1U) \r
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */\r
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */\r
+#define TIM_CR1_URS_Pos (2U) \r
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */\r
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */\r
+#define TIM_CR1_OPM_Pos (3U) \r
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */\r
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */\r
+#define TIM_CR1_DIR_Pos (4U) \r
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */\r
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */\r
+\r
+#define TIM_CR1_CMS_Pos (5U) \r
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */\r
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */\r
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */\r
+\r
+#define TIM_CR1_ARPE_Pos (7U) \r
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */\r
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD_Pos (8U) \r
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */\r
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */\r
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */\r
+#define TIM_CR1_UIFREMAP_Pos (11U) \r
+#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */\r
+#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<UIF status bit */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC_Pos (0U) \r
+#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */\r
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS_Pos (2U) \r
+#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */\r
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS_Pos (3U) \r
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */\r
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_OIS5_Pos (16U) \r
+#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */\r
+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS6_Pos (18U) \r
+#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */\r
+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */\r
+\r
+#define TIM_CR2_MMS_Pos (4U) \r
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */\r
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */\r
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */\r
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */\r
+\r
+#define TIM_CR2_MMS2_Pos (20U) \r
+#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */\r
+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */\r
+#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */\r
+#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */\r
+#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */\r
+\r
+#define TIM_CR2_TI1S_Pos (7U) \r
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */\r
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1_Pos (8U) \r
+#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */\r
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N_Pos (9U) \r
+#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */\r
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2_Pos (10U) \r
+#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */\r
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N_Pos (11U) \r
+#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */\r
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3_Pos (12U) \r
+#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */\r
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N_Pos (13U) \r
+#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */\r
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4_Pos (14U) \r
+#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */\r
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS_Pos (0U) \r
+#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */\r
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */\r
+#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */\r
+#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */\r
+#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_SMCR_TS_Pos (4U) \r
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */\r
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */\r
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */\r
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */\r
+\r
+#define TIM_SMCR_MSM_Pos (7U) \r
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */\r
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF_Pos (8U) \r
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */\r
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */\r
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */\r
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */\r
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */\r
+\r
+#define TIM_SMCR_ETPS_Pos (12U) \r
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */\r
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */\r
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */\r
+\r
+#define TIM_SMCR_ECE_Pos (14U) \r
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */\r
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */\r
+#define TIM_SMCR_ETP_Pos (15U) \r
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */\r
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE_Pos (0U) \r
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */\r
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE_Pos (1U) \r
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */\r
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE_Pos (2U) \r
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */\r
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE_Pos (3U) \r
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */\r
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE_Pos (4U) \r
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */\r
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE_Pos (5U) \r
+#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */\r
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE_Pos (6U) \r
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */\r
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE_Pos (7U) \r
+#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */\r
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE_Pos (8U) \r
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */\r
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE_Pos (9U) \r
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */\r
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE_Pos (10U) \r
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */\r
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE_Pos (11U) \r
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */\r
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE_Pos (12U) \r
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */\r
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE_Pos (13U) \r
+#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */\r
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE_Pos (14U) \r
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */\r
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF_Pos (0U) \r
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */\r
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF_Pos (1U) \r
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */\r
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF_Pos (2U) \r
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */\r
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF_Pos (3U) \r
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */\r
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF_Pos (4U) \r
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */\r
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF_Pos (5U) \r
+#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */\r
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF_Pos (6U) \r
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */\r
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF_Pos (7U) \r
+#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */\r
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */\r
+#define TIM_SR_B2IF_Pos (8U) \r
+#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */\r
+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */\r
+#define TIM_SR_CC1OF_Pos (9U) \r
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */\r
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF_Pos (10U) \r
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */\r
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF_Pos (11U) \r
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */\r
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF_Pos (12U) \r
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */\r
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */\r
+#define TIM_SR_SBIF_Pos (13U) \r
+#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */\r
+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */\r
+#define TIM_SR_CC5IF_Pos (16U) \r
+#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */\r
+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */\r
+#define TIM_SR_CC6IF_Pos (17U) \r
+#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */\r
+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG_Pos (0U) \r
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */\r
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */\r
+#define TIM_EGR_CC1G_Pos (1U) \r
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */\r
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G_Pos (2U) \r
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */\r
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G_Pos (3U) \r
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */\r
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G_Pos (4U) \r
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */\r
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG_Pos (5U) \r
+#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */\r
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG_Pos (6U) \r
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */\r
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */\r
+#define TIM_EGR_BG_Pos (7U) \r
+#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */\r
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */\r
+#define TIM_EGR_B2G_Pos (8U) \r
+#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */\r
+#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break2 Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S_Pos (0U) \r
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR1_OC1FE_Pos (2U) \r
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE_Pos (3U) \r
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M_Pos (4U) \r
+#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */\r
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR1_OC1CE_Pos (7U) \r
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S_Pos (8U) \r
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR1_OC2FE_Pos (10U) \r
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE_Pos (11U) \r
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M_Pos (12U) \r
+#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */\r
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR1_OC2CE_Pos (15U) \r
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC_Pos (2U) \r
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */\r
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */\r
+\r
+#define TIM_CCMR1_IC1F_Pos (4U) \r
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */\r
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */\r
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */\r
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */\r
+\r
+#define TIM_CCMR1_IC2PSC_Pos (10U) \r
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */\r
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */\r
+\r
+#define TIM_CCMR1_IC2F_Pos (12U) \r
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */\r
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */\r
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */\r
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S_Pos (0U) \r
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR2_OC3FE_Pos (2U) \r
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE_Pos (3U) \r
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M_Pos (4U) \r
+#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */\r
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */\r
+\r
+\r
+\r
+#define TIM_CCMR2_OC3CE_Pos (7U) \r
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S_Pos (8U) \r
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR2_OC4FE_Pos (10U) \r
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE_Pos (11U) \r
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M_Pos (12U) \r
+#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */\r
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR2_OC4CE_Pos (15U) \r
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC_Pos (2U) \r
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */\r
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */\r
+\r
+#define TIM_CCMR2_IC3F_Pos (4U) \r
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */\r
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */\r
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */\r
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */\r
+\r
+#define TIM_CCMR2_IC4PSC_Pos (10U) \r
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */\r
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */\r
+\r
+#define TIM_CCMR2_IC4F_Pos (12U) \r
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */\r
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */\r
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */\r
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E_Pos (0U) \r
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */\r
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P_Pos (1U) \r
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */\r
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE_Pos (2U) \r
+#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP_Pos (3U) \r
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */\r
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E_Pos (4U) \r
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */\r
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P_Pos (5U) \r
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */\r
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE_Pos (6U) \r
+#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */\r
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP_Pos (7U) \r
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */\r
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E_Pos (8U) \r
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */\r
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P_Pos (9U) \r
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */\r
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE_Pos (10U) \r
+#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP_Pos (11U) \r
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */\r
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E_Pos (12U) \r
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */\r
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P_Pos (13U) \r
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */\r
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP_Pos (15U) \r
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */\r
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */\r
+#define TIM_CCER_CC5E_Pos (16U) \r
+#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */\r
+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */\r
+#define TIM_CCER_CC5P_Pos (17U) \r
+#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */\r
+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */\r
+#define TIM_CCER_CC6E_Pos (20U) \r
+#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */\r
+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */\r
+#define TIM_CCER_CC6P_Pos (21U) \r
+#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */\r
+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */\r
+\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT_Pos (0U) \r
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */\r
+#define TIM_CNT_UIFCPY_Pos (31U) \r
+#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */\r
+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC_Pos (0U) \r
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */\r
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR_Pos (0U) \r
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP_Pos (0U) \r
+#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */\r
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1_Pos (0U) \r
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2_Pos (0U) \r
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3_Pos (0U) \r
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4_Pos (0U) \r
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG_Pos (0U) \r
+#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */\r
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */\r
+#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */\r
+#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */\r
+#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */\r
+#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */\r
+#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */\r
+#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */\r
+#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */\r
+\r
+#define TIM_BDTR_LOCK_Pos (8U) \r
+#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */\r
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */\r
+#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_BDTR_OSSI_Pos (10U) \r
+#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */\r
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR_Pos (11U) \r
+#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */\r
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE_Pos (12U) \r
+#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */\r
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */\r
+#define TIM_BDTR_BKP_Pos (13U) \r
+#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */\r
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */\r
+#define TIM_BDTR_AOE_Pos (14U) \r
+#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */\r
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE_Pos (15U) \r
+#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */\r
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */\r
+#define TIM_BDTR_BKF_Pos (16U) \r
+#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */\r
+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */\r
+#define TIM_BDTR_BK2F_Pos (20U) \r
+#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */\r
+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */\r
+#define TIM_BDTR_BK2E_Pos (24U) \r
+#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */\r
+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */\r
+#define TIM_BDTR_BK2P_Pos (25U) \r
+#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */\r
+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA_Pos (0U) \r
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */\r
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */\r
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */\r
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */\r
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */\r
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */\r
+\r
+#define TIM_DCR_DBL_Pos (8U) \r
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */\r
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */\r
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */\r
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */\r
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */\r
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB_Pos (0U) \r
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */\r
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR regiter *********************/\r
+#define TIM_OR_TI4_RMP_Pos (6U) \r
+#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */\r
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
+#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */\r
+#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */\r
+#define TIM_OR_ITR1_RMP_Pos (10U) \r
+#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */\r
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */\r
+#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */\r
+\r
+/******************* Bit definition for TIM2_OR register *******************/\r
+#define TIM2_OR_ITR1_RMP_Pos (10U) \r
+#define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */\r
+#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */\r
+#define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000400 */\r
+#define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000800 */\r
+\r
+/******************* Bit definition for TIM5_OR register *******************/\r
+#define TIM5_OR_TI4_RMP_Pos (6U) \r
+#define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x000000C0 */\r
+#define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */\r
+#define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000040 */\r
+#define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000080 */\r
+\r
+/******************* Bit definition for TIM11_OR register *******************/\r
+#define TIM11_OR_TI1_RMP_Pos (0U) \r
+#define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000003 */\r
+#define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\r
+#define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000001 */\r
+#define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000002 */\r
+\r
+/****************** Bit definition for TIM_CCMR3 register *******************/\r
+#define TIM_CCMR3_OC5FE_Pos (2U) \r
+#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */\r
+#define TIM_CCMR3_OC5PE_Pos (3U) \r
+#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */\r
+\r
+#define TIM_CCMR3_OC5M_Pos (4U) \r
+#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */\r
+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r
+#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR3_OC5CE_Pos (7U) \r
+#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */\r
+\r
+#define TIM_CCMR3_OC6FE_Pos (10U) \r
+#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR3_OC6PE_Pos (11U) \r
+#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR3_OC6M_Pos (12U) \r
+#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */\r
+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR3_OC6CE_Pos (15U) \r
+#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */\r
+\r
+/******************* Bit definition for TIM_CCR5 register *******************/\r
+#define TIM_CCR5_CCR5_Pos (0U) \r
+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */\r
+#define TIM_CCR5_GC5C1_Pos (29U) \r
+#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */\r
+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */\r
+#define TIM_CCR5_GC5C2_Pos (30U) \r
+#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */\r
+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */\r
+#define TIM_CCR5_GC5C3_Pos (31U) \r
+#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */\r
+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */\r
+\r
+/******************* Bit definition for TIM_CCR6 register *******************/\r
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */\r
+\r
+/******************* Bit definition for TIM1_AF1 register *******************/\r
+#define TIM1_AF1_BKINE_Pos (0U) \r
+#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */\r
+#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */\r
+#define TIM1_AF1_BKDF1BKE_Pos (8U) \r
+#define TIM1_AF1_BKDF1BKE_Msk (0x1UL << TIM1_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */\r
+#define TIM1_AF1_BKDF1BKE TIM1_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */\r
+#define TIM1_AF1_BKINP_Pos (9U) \r
+#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */\r
+#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */\r
+\r
+/******************* Bit definition for TIM1_AF2 register *******************/\r
+#define TIM1_AF2_BK2INE_Pos (0U) \r
+#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */\r
+#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */\r
+#define TIM1_AF2_BK2DF1BKE_Pos (8U) \r
+#define TIM1_AF2_BK2DF1BKE_Msk (0x1UL << TIM1_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */\r
+#define TIM1_AF2_BK2DF1BKE TIM1_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */\r
+#define TIM1_AF2_BK2INP_Pos (9U) \r
+#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */\r
+#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */\r
+\r
+/******************* Bit definition for TIM8_AF1 register *******************/\r
+#define TIM8_AF1_BKINE_Pos (0U) \r
+#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */\r
+#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BRK BKIN input enable */\r
+#define TIM8_AF1_BKDF1BKE_Pos (8U) \r
+#define TIM8_AF1_BKDF1BKE_Msk (0x1UL << TIM8_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */\r
+#define TIM8_AF1_BKDF1BKE TIM8_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */\r
+#define TIM8_AF1_BKINP_Pos (9U) \r
+#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */\r
+#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRK BKIN input polarity */\r
+\r
+/******************* Bit definition for TIM8_AF2 register *******************/\r
+#define TIM8_AF2_BK2INE_Pos (0U) \r
+#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */\r
+#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */\r
+#define TIM8_AF2_BK2DF1BKE_Pos (8U) \r
+#define TIM8_AF2_BK2DF1BKE_Msk (0x1UL << TIM8_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */\r
+#define TIM8_AF2_BK2DF1BKE TIM8_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */\r
+#define TIM8_AF2_BK2INP_Pos (9U) \r
+#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */\r
+#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Low Power Timer (LPTIM) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for LPTIM_ISR register *******************/\r
+#define LPTIM_ISR_CMPM_Pos (0U) \r
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */\r
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */\r
+#define LPTIM_ISR_ARRM_Pos (1U) \r
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */\r
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */\r
+#define LPTIM_ISR_EXTTRIG_Pos (2U) \r
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */\r
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */\r
+#define LPTIM_ISR_CMPOK_Pos (3U) \r
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */\r
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */\r
+#define LPTIM_ISR_ARROK_Pos (4U) \r
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */\r
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */\r
+#define LPTIM_ISR_UP_Pos (5U) \r
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */\r
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */\r
+#define LPTIM_ISR_DOWN_Pos (6U) \r
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */\r
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */\r
+\r
+/****************** Bit definition for LPTIM_ICR register *******************/\r
+#define LPTIM_ICR_CMPMCF_Pos (0U) \r
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */\r
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */\r
+#define LPTIM_ICR_ARRMCF_Pos (1U) \r
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */\r
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */\r
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U) \r
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */\r
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */\r
+#define LPTIM_ICR_CMPOKCF_Pos (3U) \r
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */\r
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */\r
+#define LPTIM_ICR_ARROKCF_Pos (4U) \r
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */\r
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */\r
+#define LPTIM_ICR_UPCF_Pos (5U) \r
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */\r
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */\r
+#define LPTIM_ICR_DOWNCF_Pos (6U) \r
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */\r
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */\r
+\r
+/****************** Bit definition for LPTIM_IER register *******************/\r
+#define LPTIM_IER_CMPMIE_Pos (0U) \r
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */\r
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */\r
+#define LPTIM_IER_ARRMIE_Pos (1U) \r
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */\r
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */\r
+#define LPTIM_IER_EXTTRIGIE_Pos (2U) \r
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */\r
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */\r
+#define LPTIM_IER_CMPOKIE_Pos (3U) \r
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */\r
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */\r
+#define LPTIM_IER_ARROKIE_Pos (4U) \r
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */\r
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */\r
+#define LPTIM_IER_UPIE_Pos (5U) \r
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */\r
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */\r
+#define LPTIM_IER_DOWNIE_Pos (6U) \r
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */\r
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */\r
+\r
+/****************** Bit definition for LPTIM_CFGR register*******************/\r
+#define LPTIM_CFGR_CKSEL_Pos (0U) \r
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */\r
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */\r
+\r
+#define LPTIM_CFGR_CKPOL_Pos (1U) \r
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */\r
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */\r
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */\r
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */\r
+\r
+#define LPTIM_CFGR_CKFLT_Pos (3U) \r
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */\r
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */\r
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */\r
+\r
+#define LPTIM_CFGR_TRGFLT_Pos (6U) \r
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */\r
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */\r
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */\r
+\r
+#define LPTIM_CFGR_PRESC_Pos (9U) \r
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */\r
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */\r
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */\r
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */\r
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */\r
+\r
+#define LPTIM_CFGR_TRIGSEL_Pos (13U) \r
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */\r
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */\r
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */\r
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */\r
+\r
+#define LPTIM_CFGR_TRIGEN_Pos (17U) \r
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */\r
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */\r
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */\r
+\r
+#define LPTIM_CFGR_TIMOUT_Pos (19U) \r
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */\r
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */\r
+#define LPTIM_CFGR_WAVE_Pos (20U) \r
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */\r
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */\r
+#define LPTIM_CFGR_WAVPOL_Pos (21U) \r
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */\r
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */\r
+#define LPTIM_CFGR_PRELOAD_Pos (22U) \r
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */\r
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */\r
+#define LPTIM_CFGR_COUNTMODE_Pos (23U) \r
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */\r
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */\r
+#define LPTIM_CFGR_ENC_Pos (24U) \r
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */\r
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */\r
+\r
+/****************** Bit definition for LPTIM_CR register ********************/\r
+#define LPTIM_CR_ENABLE_Pos (0U) \r
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */\r
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */\r
+#define LPTIM_CR_SNGSTRT_Pos (1U) \r
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */\r
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */\r
+#define LPTIM_CR_CNTSTRT_Pos (2U) \r
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */\r
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */\r
+\r
+/****************** Bit definition for LPTIM_CMP register *******************/\r
+#define LPTIM_CMP_CMP_Pos (0U) \r
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */\r
+\r
+/****************** Bit definition for LPTIM_ARR register *******************/\r
+#define LPTIM_ARR_ARR_Pos (0U) \r
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */\r
+\r
+/****************** Bit definition for LPTIM_CNT register *******************/\r
+#define LPTIM_CNT_CNT_Pos (0U) \r
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_UE_Pos (0U) \r
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */\r
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */\r
+#define USART_CR1_RE_Pos (2U) \r
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */\r
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */\r
+#define USART_CR1_TE_Pos (3U) \r
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */\r
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE_Pos (4U) \r
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */\r
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE_Pos (5U) \r
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */\r
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE_Pos (6U) \r
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE_Pos (7U) \r
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */\r
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */\r
+#define USART_CR1_PEIE_Pos (8U) \r
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */\r
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS_Pos (9U) \r
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */\r
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */\r
+#define USART_CR1_PCE_Pos (10U) \r
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */\r
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE_Pos (11U) \r
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */\r
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */\r
+#define USART_CR1_M_Pos (12U) \r
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */\r
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */\r
+#define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos) /*!< 0x00001000 */\r
+#define USART_CR1_MME_Pos (13U) \r
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */\r
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE_Pos (14U) \r
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */\r
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8_Pos (15U) \r
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */\r
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT_Pos (16U) \r
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */\r
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */\r
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */\r
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */\r
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */\r
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */\r
+#define USART_CR1_DEAT_Pos (21U) \r
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */\r
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */\r
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */\r
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */\r
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */\r
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */\r
+#define USART_CR1_RTOIE_Pos (26U) \r
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */\r
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE_Pos (27U) \r
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */\r
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */\r
+#define USART_CR1_M1 0x10000000U /*!< Word length - Bit 1 */\r
+\r
+/* Legacy defines */\r
+#define USART_CR1_M_0 USART_CR1_M0 /*!< Word length - Bit 0 */\r
+#define USART_CR1_M_1 USART_CR1_M1 /*!< Word length - Bit 1 */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADDM7_Pos (4U) \r
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */\r
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL_Pos (5U) \r
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */\r
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE_Pos (6U) \r
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL_Pos (8U) \r
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */\r
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA_Pos (9U) \r
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */\r
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */\r
+#define USART_CR2_CPOL_Pos (10U) \r
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */\r
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN_Pos (11U) \r
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */\r
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */\r
+#define USART_CR2_STOP_Pos (12U) \r
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */\r
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */\r
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */\r
+#define USART_CR2_LINEN_Pos (14U) \r
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */\r
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */\r
+#define USART_CR2_SWAP_Pos (15U) \r
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */\r
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV_Pos (16U) \r
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */\r
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV_Pos (17U) \r
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */\r
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV_Pos (18U) \r
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */\r
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST_Pos (19U) \r
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */\r
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN_Pos (20U) \r
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */\r
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable */\r
+#define USART_CR2_ABRMODE_Pos (21U) \r
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */\r
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */\r
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */\r
+#define USART_CR2_RTOEN_Pos (23U) \r
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */\r
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD_Pos (24U) \r
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */\r
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE_Pos (0U) \r
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */\r
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN_Pos (1U) \r
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */\r
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP_Pos (2U) \r
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */\r
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL_Pos (3U) \r
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */\r
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK_Pos (4U) \r
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */\r
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN_Pos (5U) \r
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */\r
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR_Pos (6U) \r
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */\r
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT_Pos (7U) \r
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */\r
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE_Pos (8U) \r
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */\r
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */\r
+#define USART_CR3_CTSE_Pos (9U) \r
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */\r
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */\r
+#define USART_CR3_CTSIE_Pos (10U) \r
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */\r
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT_Pos (11U) \r
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */\r
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS_Pos (12U) \r
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */\r
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */\r
+#define USART_CR3_DDRE_Pos (13U) \r
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */\r
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM_Pos (14U) \r
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */\r
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP_Pos (15U) \r
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */\r
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT_Pos (17U) \r
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */\r
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */\r
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */\r
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION_Pos (0U) \r
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */\r
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA_Pos (4U) \r
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */\r
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC_Pos (0U) \r
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */\r
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT_Pos (8U) \r
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */\r
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */\r
+\r
+\r
+/******************* Bit definition for USART_RTOR register *****************/\r
+#define USART_RTOR_RTO_Pos (0U) \r
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */\r
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN_Pos (24U) \r
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */\r
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */\r
+\r
+/******************* Bit definition for USART_RQR register ******************/\r
+#define USART_RQR_ABRRQ_Pos (0U) \r
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */\r
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ_Pos (1U) \r
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */\r
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */\r
+#define USART_RQR_MMRQ_Pos (2U) \r
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */\r
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ_Pos (3U) \r
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */\r
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ_Pos (4U) \r
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */\r
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */\r
+\r
+/******************* Bit definition for USART_ISR register ******************/\r
+#define USART_ISR_PE_Pos (0U) \r
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */\r
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */\r
+#define USART_ISR_FE_Pos (1U) \r
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */\r
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */\r
+#define USART_ISR_NE_Pos (2U) \r
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */\r
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */\r
+#define USART_ISR_ORE_Pos (3U) \r
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */\r
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */\r
+#define USART_ISR_IDLE_Pos (4U) \r
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */\r
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */\r
+#define USART_ISR_RXNE_Pos (5U) \r
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */\r
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */\r
+#define USART_ISR_TC_Pos (6U) \r
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */\r
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */\r
+#define USART_ISR_TXE_Pos (7U) \r
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */\r
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */\r
+#define USART_ISR_LBDF_Pos (8U) \r
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */\r
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF_Pos (9U) \r
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */\r
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS_Pos (10U) \r
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */\r
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */\r
+#define USART_ISR_RTOF_Pos (11U) \r
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */\r
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF_Pos (12U) \r
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */\r
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */\r
+#define USART_ISR_ABRE_Pos (14U) \r
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */\r
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF_Pos (15U) \r
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */\r
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY_Pos (16U) \r
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */\r
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */\r
+#define USART_ISR_CMF_Pos (17U) \r
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */\r
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */\r
+#define USART_ISR_SBKF_Pos (18U) \r
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */\r
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */\r
+#define USART_ISR_RWU_Pos (19U) \r
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */\r
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_TEACK_Pos (21U) \r
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */\r
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */\r
+\r
+/******************* Bit definition for USART_ICR register ******************/\r
+#define USART_ICR_PECF_Pos (0U) \r
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */\r
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF_Pos (1U) \r
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */\r
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NCF_Pos (2U) \r
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */\r
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */\r
+#define USART_ICR_ORECF_Pos (3U) \r
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */\r
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF_Pos (4U) \r
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */\r
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TCCF_Pos (6U) \r
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */\r
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_LBDCF_Pos (8U) \r
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */\r
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF_Pos (9U) \r
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */\r
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF_Pos (11U) \r
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */\r
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF_Pos (12U) \r
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */\r
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */\r
+#define USART_ICR_CMCF_Pos (17U) \r
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */\r
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */\r
+\r
+/******************* Bit definition for USART_RDR register ******************/\r
+#define USART_RDR_RDR_Pos (0U) \r
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */\r
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/******************* Bit definition for USART_TDR register ******************/\r
+#define USART_TDR_TDR_Pos (0U) \r
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */\r
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T_Pos (0U) \r
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */\r
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */\r
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */\r
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */\r
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */\r
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */\r
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */\r
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */\r
+\r
+\r
+#define WWDG_CR_WDGA_Pos (7U) \r
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */\r
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W_Pos (0U) \r
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */\r
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */\r
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */\r
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */\r
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */\r
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */\r
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */\r
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */\r
+\r
+\r
+#define WWDG_CFR_WDGTB_Pos (7U) \r
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */\r
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */\r
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */\r
+\r
+\r
+#define WWDG_CFR_EWI_Pos (9U) \r
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */\r
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF_Pos (0U) \r
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */\r
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U) \r
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk \r
+#define DBGMCU_IDCODE_REV_ID_Pos (16U) \r
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk \r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U) \r
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk \r
+#define DBGMCU_CR_DBG_STOP_Pos (1U) \r
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk \r
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U) \r
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk \r
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U) \r
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk \r
+\r
+#define DBGMCU_CR_TRACE_MODE_Pos (6U) \r
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\r
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk \r
+#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\r
+\r
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) \r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U) \r
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */\r
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) \r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) \r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) \r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (13U) \r
+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x00002000 */\r
+#define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) \r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk \r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) \r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk \r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U) \r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk \r
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U) \r
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk \r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U) \r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk \r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U) \r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk \r
+\r
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk \r
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk \r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk \r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk \r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) \r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk \r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Ethernet MAC Registers bits definitions */\r
+/* */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD_Pos (23U) \r
+#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */\r
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */\r
+#define ETH_MACCR_JD_Pos (22U) \r
+#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */\r
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */\r
+#define ETH_MACCR_IFG_Pos (17U) \r
+#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */\r
+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */\r
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */\r
+#define ETH_MACCR_CSD_Pos (16U) \r
+#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */\r
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES_Pos (14U) \r
+#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\r
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD_Pos (13U) \r
+#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */\r
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */\r
+#define ETH_MACCR_LM_Pos (12U) \r
+#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\r
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */\r
+#define ETH_MACCR_DM_Pos (11U) \r
+#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */\r
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */\r
+#define ETH_MACCR_IPCO_Pos (10U) \r
+#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */\r
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */\r
+#define ETH_MACCR_RD_Pos (9U) \r
+#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */\r
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */\r
+#define ETH_MACCR_APCS_Pos (7U) \r
+#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */\r
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL_Pos (5U) \r
+#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */\r
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */\r
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */\r
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */\r
+#define ETH_MACCR_DC_Pos (4U) \r
+#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\r
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */\r
+#define ETH_MACCR_TE_Pos (3U) \r
+#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */\r
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */\r
+#define ETH_MACCR_RE_Pos (2U) \r
+#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */\r
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA_Pos (31U) \r
+#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */\r
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */\r
+#define ETH_MACFFR_HPF_Pos (10U) \r
+#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */\r
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */\r
+#define ETH_MACFFR_SAF_Pos (9U) \r
+#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */\r
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */\r
+#define ETH_MACFFR_SAIF_Pos (8U) \r
+#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */\r
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */\r
+#define ETH_MACFFR_PCF_Pos (6U) \r
+#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */\r
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */\r
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U) \r
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */\r
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */\r
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U) \r
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */\r
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) \r
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */\r
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */\r
+#define ETH_MACFFR_BFD_Pos (5U) \r
+#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */\r
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */\r
+#define ETH_MACFFR_PAM_Pos (4U) \r
+#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */\r
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */\r
+#define ETH_MACFFR_DAIF_Pos (3U) \r
+#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */\r
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */\r
+#define ETH_MACFFR_HM_Pos (2U) \r
+#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */\r
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */\r
+#define ETH_MACFFR_HU_Pos (1U) \r
+#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */\r
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */\r
+#define ETH_MACFFR_PM_Pos (0U) \r
+#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */\r
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH_Pos (0U) \r
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL_Pos (0U) \r
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA_Pos (11U) \r
+#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */\r
+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */\r
+#define ETH_MACMIIAR_MR_Pos (6U) \r
+#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */\r
+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */\r
+#define ETH_MACMIIAR_CR_Pos (2U) \r
+#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */\r
+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */\r
+#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
+#define ETH_MACMIIAR_CR_Div62_Pos (2U) \r
+#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */\r
+#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
+#define ETH_MACMIIAR_CR_Div16_Pos (3U) \r
+#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */\r
+#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+#define ETH_MACMIIAR_CR_Div26_Pos (2U) \r
+#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */\r
+#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+#define ETH_MACMIIAR_CR_Div102_Pos (4U) \r
+#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */\r
+#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */\r
+#define ETH_MACMIIAR_MW_Pos (1U) \r
+#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */\r
+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */\r
+#define ETH_MACMIIAR_MB_Pos (0U) \r
+#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */\r
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */\r
+\r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD_Pos (0U) \r
+#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT_Pos (16U) \r
+#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */\r
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */\r
+#define ETH_MACFCR_ZQPD_Pos (7U) \r
+#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */\r
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT_Pos (4U) \r
+#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */\r
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */\r
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */\r
+#define ETH_MACFCR_PLT_Minus28_Pos (4U) \r
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */\r
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */\r
+#define ETH_MACFCR_PLT_Minus144_Pos (5U) \r
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */\r
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */\r
+#define ETH_MACFCR_PLT_Minus256_Pos (4U) \r
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */\r
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */\r
+#define ETH_MACFCR_UPFD_Pos (3U) \r
+#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */\r
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE_Pos (2U) \r
+#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */\r
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE_Pos (1U) \r
+#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */\r
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA_Pos (0U) \r
+#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */\r
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC_Pos (16U) \r
+#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */\r
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI_Pos (0U) \r
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */\r
+#define ETH_MACRWUFFR_D_Pos (0U) \r
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -\r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */\r
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U) \r
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */\r
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU_Pos (9U) \r
+#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */\r
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR_Pos (6U) \r
+#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */\r
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR_Pos (5U) \r
+#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */\r
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE_Pos (2U) \r
+#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */\r
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE_Pos (1U) \r
+#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */\r
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD_Pos (0U) \r
+#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */\r
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC debug Register */\r
+#define ETH_MACDBGR_TFF_Pos (25U) \r
+#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */\r
+#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */\r
+#define ETH_MACDBGR_TFNE_Pos (24U) \r
+#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */\r
+#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */\r
+#define ETH_MACDBGR_TPWA_Pos (22U) \r
+#define ETH_MACDBGR_TPWA_Msk (0x1UL << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */\r
+#define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */\r
+#define ETH_MACDBGR_TFRS_Pos (20U) \r
+#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */\r
+#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */\r
+#define ETH_MACDBGR_TFRS_WRITING_Pos (20U) \r
+#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */\r
+#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MACDBGR_TFRS_WAITING_Pos (21U) \r
+#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */\r
+#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MACDBGR_TFRS_READ_Pos (20U) \r
+#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */\r
+#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */\r
+#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */\r
+#define ETH_MACDBGR_MTP_Pos (19U) \r
+#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */\r
+#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */\r
+#define ETH_MACDBGR_MTFCS_Pos (17U) \r
+#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */\r
+#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */\r
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U) \r
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */\r
+#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */\r
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U) \r
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */\r
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U) \r
+#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */\r
+#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */\r
+#define ETH_MACDBGR_MMTEA_Pos (16U) \r
+#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */\r
+#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */\r
+#define ETH_MACDBGR_RFFL_Pos (8U) \r
+#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */\r
+#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */\r
+#define ETH_MACDBGR_RFFL_FULL_Pos (8U) \r
+#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */\r
+#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */\r
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U) \r
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */\r
+#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */\r
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U) \r
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */\r
+#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */\r
+#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */\r
+#define ETH_MACDBGR_RFRCS_Pos (5U) \r
+#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */\r
+#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */\r
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U) \r
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */\r
+#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */\r
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U) \r
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */\r
+#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */\r
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U) \r
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */\r
+#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */\r
+#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */\r
+#define ETH_MACDBGR_RFWRA_Pos (4U) \r
+#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */\r
+#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */\r
+#define ETH_MACDBGR_MSFRWCS_Pos (1U) \r
+#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */\r
+#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */\r
+#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */\r
+#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */\r
+#define ETH_MACDBGR_MMRPEA_Pos (0U) \r
+#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */\r
+#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS_Pos (9U) \r
+#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */\r
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS_Pos (6U) \r
+#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */\r
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS_Pos (5U) \r
+#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */\r
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */\r
+#define ETH_MACSR_MMCS_Pos (4U) \r
+#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */\r
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */\r
+#define ETH_MACSR_PMTS_Pos (3U) \r
+#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */\r
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM_Pos (9U) \r
+#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */\r
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM_Pos (3U) \r
+#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */\r
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H_Pos (0U) \r
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L_Pos (0U) \r
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE_Pos (31U) \r
+#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */\r
+#define ETH_MACA1HR_SA_Pos (30U) \r
+#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\r
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */\r
+#define ETH_MACA1HR_MBC_Pos (24U) \r
+#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\r
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */\r
+#define ETH_MACA1HR_MACA1H_Pos (0U) \r
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L_Pos (0U) \r
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE_Pos (31U) \r
+#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */\r
+#define ETH_MACA2HR_SA_Pos (30U) \r
+#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\r
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */\r
+#define ETH_MACA2HR_MBC_Pos (24U) \r
+#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\r
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */\r
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H_Pos (0U) \r
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L_Pos (0U) \r
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE_Pos (31U) \r
+#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\r
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */\r
+#define ETH_MACA3HR_SA_Pos (30U) \r
+#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\r
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */\r
+#define ETH_MACA3HR_MBC_Pos (24U) \r
+#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\r
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */\r
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H_Pos (0U) \r
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */\r
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L_Pos (0U) \r
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCFHP_Pos (5U) \r
+#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */\r
+#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */\r
+#define ETH_MMCCR_MCP_Pos (4U) \r
+#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */\r
+#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */\r
+#define ETH_MMCCR_MCF_Pos (3U) \r
+#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */\r
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR_Pos (2U) \r
+#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */\r
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */\r
+#define ETH_MMCCR_CSR_Pos (1U) \r
+#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */\r
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR_Pos (0U) \r
+#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */\r
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS_Pos (17U) \r
+#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */\r
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES_Pos (6U) \r
+#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */\r
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES_Pos (5U) \r
+#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */\r
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS_Pos (21U) \r
+#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */\r
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS_Pos (15U) \r
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */\r
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS_Pos (14U) \r
+#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */\r
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM_Pos (17U) \r
+#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */\r
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM_Pos (6U) \r
+#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */\r
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM_Pos (5U) \r
+#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */\r
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM_Pos (21U) \r
+#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */\r
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U) \r
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */\r
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM_Pos (14U) \r
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */\r
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) \r
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) \r
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC_Pos (0U) \r
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC_Pos (0U) \r
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC_Pos (0U) \r
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U) \r
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSCNT_Pos (16U) \r
+#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */\r
+#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */\r
+#define ETH_PTPTSSR_TSSMRME_Pos (15U) \r
+#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */\r
+#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */\r
+#define ETH_PTPTSSR_TSSEME_Pos (14U) \r
+#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */\r
+#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */\r
+#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) \r
+#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */\r
+#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */\r
+#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) \r
+#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */\r
+#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */\r
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) \r
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */\r
+#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */\r
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) \r
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */\r
+#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */\r
+#define ETH_PTPTSSR_TSSSR_Pos (9U) \r
+#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */\r
+#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */\r
+#define ETH_PTPTSSR_TSSARFE_Pos (8U) \r
+#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */\r
+#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */\r
+\r
+#define ETH_PTPTSCR_TSARU_Pos (5U) \r
+#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */\r
+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE_Pos (4U) \r
+#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */\r
+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU_Pos (3U) \r
+#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */\r
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI_Pos (2U) \r
+#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */\r
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU_Pos (1U) \r
+#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */\r
+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE_Pos (0U) \r
+#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */\r
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI_Pos (0U) \r
+#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */\r
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS_Pos (0U) \r
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS_Pos (31U) \r
+#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */\r
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS_Pos (0U) \r
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */\r
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS_Pos (0U) \r
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U) \r
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */\r
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS_Pos (0U) \r
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */\r
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA_Pos (0U) \r
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH_Pos (0U) \r
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL_Pos (0U) \r
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
+#define ETH_PTPTSSR_TSTTR_Pos (5U) \r
+#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */\r
+#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */\r
+#define ETH_PTPTSSR_TSSO_Pos (4U) \r
+#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */\r
+#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB_Pos (25U) \r
+#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */\r
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM_Pos (24U) \r
+#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */\r
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */\r
+#define ETH_DMABMR_USP_Pos (23U) \r
+#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */\r
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */\r
+#define ETH_DMABMR_RDP_Pos (17U) \r
+#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */\r
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */\r
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+#define ETH_DMABMR_FB_Pos (16U) \r
+#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */\r
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR_Pos (14U) \r
+#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */\r
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */\r
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */\r
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */\r
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */\r
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */\r
+#define ETH_DMABMR_PBL_Pos (8U) \r
+#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */\r
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */\r
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_EDE_Pos (7U) \r
+#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */\r
+#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */\r
+#define ETH_DMABMR_DSL_Pos (2U) \r
+#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */\r
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA_Pos (1U) \r
+#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */\r
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR_Pos (0U) \r
+#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */\r
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD_Pos (0U) \r
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD_Pos (0U) \r
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL_Pos (0U) \r
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL_Pos (0U) \r
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS_Pos (29U) \r
+#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */\r
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS_Pos (28U) \r
+#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */\r
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */\r
+#define ETH_DMASR_MMCS_Pos (27U) \r
+#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */\r
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */\r
+#define ETH_DMASR_EBS_Pos (23U) \r
+#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */\r
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+#define ETH_DMASR_EBS_DescAccess_Pos (25U) \r
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */\r
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U) \r
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */\r
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */\r
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U) \r
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */\r
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS_Pos (20U) \r
+#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */\r
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */\r
+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMASR_TPS_Fetching_Pos (20U) \r
+#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */\r
+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */\r
+#define ETH_DMASR_TPS_Waiting_Pos (21U) \r
+#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */\r
+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */\r
+#define ETH_DMASR_TPS_Reading_Pos (20U) \r
+#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */\r
+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */\r
+#define ETH_DMASR_TPS_Suspended_Pos (21U) \r
+#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */\r
+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */\r
+#define ETH_DMASR_TPS_Closing_Pos (20U) \r
+#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */\r
+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS_Pos (17U) \r
+#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */\r
+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */\r
+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMASR_RPS_Fetching_Pos (17U) \r
+#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */\r
+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */\r
+#define ETH_DMASR_RPS_Waiting_Pos (17U) \r
+#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */\r
+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */\r
+#define ETH_DMASR_RPS_Suspended_Pos (19U) \r
+#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */\r
+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */\r
+#define ETH_DMASR_RPS_Closing_Pos (17U) \r
+#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */\r
+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */\r
+#define ETH_DMASR_RPS_Queuing_Pos (17U) \r
+#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */\r
+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS_Pos (16U) \r
+#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */\r
+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS_Pos (15U) \r
+#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */\r
+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS_Pos (14U) \r
+#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */\r
+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */\r
+#define ETH_DMASR_FBES_Pos (13U) \r
+#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */\r
+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */\r
+#define ETH_DMASR_ETS_Pos (10U) \r
+#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */\r
+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */\r
+#define ETH_DMASR_RWTS_Pos (9U) \r
+#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */\r
+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS_Pos (8U) \r
+#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */\r
+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS_Pos (7U) \r
+#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */\r
+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS_Pos (6U) \r
+#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */\r
+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */\r
+#define ETH_DMASR_TUS_Pos (5U) \r
+#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */\r
+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */\r
+#define ETH_DMASR_ROS_Pos (4U) \r
+#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */\r
+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */\r
+#define ETH_DMASR_TJTS_Pos (3U) \r
+#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */\r
+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS_Pos (2U) \r
+#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */\r
+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS_Pos (1U) \r
+#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */\r
+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */\r
+#define ETH_DMASR_TS_Pos (0U) \r
+#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */\r
+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD_Pos (26U) \r
+#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */\r
+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF_Pos (25U) \r
+#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */\r
+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF_Pos (24U) \r
+#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */\r
+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF_Pos (21U) \r
+#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */\r
+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF_Pos (20U) \r
+#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */\r
+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC_Pos (14U) \r
+#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */\r
+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */\r
+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST_Pos (13U) \r
+#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */\r
+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF_Pos (7U) \r
+#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */\r
+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF_Pos (6U) \r
+#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */\r
+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC_Pos (3U) \r
+#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */\r
+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */\r
+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF_Pos (2U) \r
+#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */\r
+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */\r
+#define ETH_DMAOMR_SR_Pos (1U) \r
+#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */\r
+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE_Pos (16U) \r
+#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */\r
+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE_Pos (15U) \r
+#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */\r
+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE_Pos (14U) \r
+#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */\r
+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE_Pos (13U) \r
+#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */\r
+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE_Pos (10U) \r
+#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */\r
+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE_Pos (9U) \r
+#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */\r
+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE_Pos (8U) \r
+#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */\r
+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE_Pos (7U) \r
+#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */\r
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE_Pos (6U) \r
+#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */\r
+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE_Pos (5U) \r
+#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */\r
+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE_Pos (4U) \r
+#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */\r
+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE_Pos (3U) \r
+#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */\r
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE_Pos (2U) \r
+#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */\r
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE_Pos (1U) \r
+#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */\r
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE_Pos (0U) \r
+#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */\r
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC_Pos (28U) \r
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */\r
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA_Pos (17U) \r
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */\r
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC_Pos (16U) \r
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */\r
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC_Pos (0U) \r
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */\r
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP_Pos (0U) \r
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP_Pos (0U) \r
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP_Pos (0U) \r
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP_Pos (0U) \r
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */\r
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* USB_OTG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/\r
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) \r
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */\r
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U) \r
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */\r
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) \r
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) \r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) \r
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) \r
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) \r
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) \r
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) \r
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) \r
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */\r
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) \r
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) \r
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */\r
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U) \r
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */\r
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) \r
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */\r
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U) \r
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */\r
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) \r
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */\r
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) \r
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */\r
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) \r
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */\r
+\r
+/******************** Bit definition for USB_OTG_HCFG register ********************/\r
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U) \r
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */\r
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCFG_FSLSS_Pos (2U) \r
+#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */\r
+\r
+/******************** Bit definition for USB_OTG_DCFG register ********************/\r
+#define USB_OTG_DCFG_DSPD_Pos (0U) \r
+#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */\r
+#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) \r
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */\r
+\r
+#define USB_OTG_DCFG_DAD_Pos (4U) \r
+#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */\r
+#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_OTG_DCFG_PFIVL_Pos (11U) \r
+#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */\r
+#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r
+\r
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) \r
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */\r
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r
+\r
+/******************** Bit definition for USB_OTG_PCGCR register ********************/\r
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U) \r
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */\r
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) \r
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */\r
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) \r
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */\r
+\r
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/\r
+#define USB_OTG_GOTGINT_SEDET_Pos (2U) \r
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */\r
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) \r
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */\r
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) \r
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */\r
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U) \r
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */\r
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) \r
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */\r
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) \r
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */\r
+#define USB_OTG_GOTGINT_IDCHNG_Pos (20U) \r
+#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */\r
+\r
+/******************** Bit definition for USB_OTG_DCTL register ********************/\r
+#define USB_OTG_DCTL_RWUSIG_Pos (0U) \r
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */\r
+#define USB_OTG_DCTL_SDIS_Pos (1U) \r
+#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */\r
+#define USB_OTG_DCTL_GINSTS_Pos (2U) \r
+#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */\r
+#define USB_OTG_DCTL_GONSTS_Pos (3U) \r
+#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */\r
+\r
+#define USB_OTG_DCTL_TCTL_Pos (4U) \r
+#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */\r
+#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCTL_SGINAK_Pos (7U) \r
+#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */\r
+#define USB_OTG_DCTL_CGINAK_Pos (8U) \r
+#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */\r
+#define USB_OTG_DCTL_SGONAK_Pos (9U) \r
+#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */\r
+#define USB_OTG_DCTL_CGONAK_Pos (10U) \r
+#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */\r
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U) \r
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */\r
+\r
+/******************** Bit definition for USB_OTG_HFIR register ********************/\r
+#define USB_OTG_HFIR_FRIVL_Pos (0U) \r
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */\r
+\r
+/******************** Bit definition for USB_OTG_HFNUM register ********************/\r
+#define USB_OTG_HFNUM_FRNUM_Pos (0U) \r
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */\r
+#define USB_OTG_HFNUM_FTREM_Pos (16U) \r
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */\r
+\r
+/******************** Bit definition for USB_OTG_DSTS register ********************/\r
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U) \r
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */\r
+\r
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U) \r
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */\r
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DSTS_EERR_Pos (3U) \r
+#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */\r
+#define USB_OTG_DSTS_FNSOF_Pos (8U) \r
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */\r
+\r
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/\r
+#define USB_OTG_GAHBCFG_GINT_Pos (0U) \r
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) \r
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\r
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) \r
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */\r
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) \r
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */\r
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) \r
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */\r
+\r
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/\r
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) \r
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */\r
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) \r
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) \r
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */\r
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) \r
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */\r
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U) \r
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */\r
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) \r
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) \r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */\r
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) \r
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */\r
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) \r
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) \r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) \r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */\r
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) \r
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */\r
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U) \r
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */\r
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U) \r
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */\r
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) \r
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */\r
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) \r
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */\r
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) \r
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */\r
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) \r
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */\r
+\r
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/\r
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U) \r
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */\r
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U) \r
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */\r
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U) \r
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */\r
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) \r
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) \r
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) \r
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */\r
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) \r
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */\r
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) \r
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/\r
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) \r
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U) \r
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPMSK_TOM_Pos (3U) \r
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) \r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) \r
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) \r
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) \r
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPMSK_BIM_Pos (9U) \r
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/\r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) \r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) \r
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) \r
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for USB_OTG_HAINT register ********************/\r
+#define USB_OTG_HAINT_HAINT_Pos (0U) \r
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/\r
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) \r
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U) \r
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)\r
+#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */\r
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U) \r
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */\r
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) \r
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */\r
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) \r
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */\r
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) \r
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */\r
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U) \r
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U) \r
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPMSK_BERRM_Pos (12U)\r
+#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */\r
+#define USB_OTG_DOEPMSK_NAKM_Pos (13U)\r
+#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */\r
+#define USB_OTG_DOEPMSK_NYETM_Pos (14U)\r
+#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/\r
+#define USB_OTG_GINTSTS_CMOD_Pos (0U) \r
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */\r
+#define USB_OTG_GINTSTS_MMIS_Pos (1U) \r
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */\r
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U) \r
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */\r
+#define USB_OTG_GINTSTS_SOF_Pos (3U) \r
+#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */\r
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) \r
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */\r
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) \r
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) \r
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) \r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */\r
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U) \r
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */\r
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) \r
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */\r
+#define USB_OTG_GINTSTS_USBRST_Pos (12U) \r
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */\r
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) \r
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */\r
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) \r
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */\r
+#define USB_OTG_GINTSTS_EOPF_Pos (15U) \r
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */\r
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U) \r
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */\r
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U) \r
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */\r
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) \r
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) \r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */\r
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) \r
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */\r
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U) \r
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */\r
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) \r
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */\r
+#define USB_OTG_GINTSTS_HCINT_Pos (25U) \r
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */\r
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U) \r
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U) \r
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */\r
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) \r
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */\r
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U) \r
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */\r
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U) \r
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */\r
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U) \r
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */\r
+\r
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/\r
+#define USB_OTG_GINTMSK_MMISM_Pos (1U) \r
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U) \r
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */\r
+#define USB_OTG_GINTMSK_SOFM_Pos (3U) \r
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */\r
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) \r
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */\r
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) \r
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) \r
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */\r
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) \r
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */\r
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) \r
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */\r
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) \r
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */\r
+#define USB_OTG_GINTMSK_USBRST_Pos (12U) \r
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */\r
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) \r
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */\r
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) \r
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */\r
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U) \r
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */\r
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U) \r
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U) \r
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U) \r
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) \r
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) \r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */\r
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) \r
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */\r
+#define USB_OTG_GINTMSK_RSTDEM_Pos (23U) \r
+#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */\r
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U) \r
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */\r
+#define USB_OTG_GINTMSK_HCIM_Pos (25U) \r
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */\r
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) \r
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U) \r
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */\r
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) \r
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */\r
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U) \r
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */\r
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U) \r
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */\r
+#define USB_OTG_GINTMSK_WUIM_Pos (31U) \r
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_DAINT register ********************/\r
+#define USB_OTG_DAINT_IEPINT_Pos (0U) \r
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */\r
+#define USB_OTG_DAINT_OEPINT_Pos (16U) \r
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */\r
+\r
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/\r
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) \r
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) \r
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U) \r
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_DPID_Pos (15U) \r
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) \r
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/\r
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U) \r
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U) \r
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM_Pos (0U) \r
+#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_BCNT_Pos (4U) \r
+#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */\r
+\r
+#define USB_OTG_DPID_Pos (15U) \r
+#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */\r
+#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_PKTSTS_Pos (17U) \r
+#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */\r
+\r
+#define USB_OTG_EPNUM_Pos (0U) \r
+#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */\r
+\r
+#define USB_OTG_FRMNUM_Pos (21U) \r
+#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM_Pos (0U) \r
+#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_BCNT_Pos (4U) \r
+#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */\r
+\r
+#define USB_OTG_DPID_Pos (15U) \r
+#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */\r
+#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_PKTSTS_Pos (17U) \r
+#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */\r
+\r
+#define USB_OTG_EPNUM_Pos (0U) \r
+#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */\r
+\r
+#define USB_OTG_FRMNUM_Pos (21U) \r
+#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */\r
+\r
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/\r
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) \r
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/\r
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) \r
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+#define USB_OTG_NPTXFSA_Pos (0U) \r
+#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */\r
+#define USB_OTG_NPTXFD_Pos (16U) \r
+#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */\r
+#define USB_OTG_TX0FSA_Pos (0U) \r
+#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */\r
+#define USB_OTG_TX0FD_Pos (16U) \r
+#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/\r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) \r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r
+\r
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) \r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) \r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) \r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/\r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) \r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) \r
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) \r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) \r
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) \r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) \r
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) \r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r
+\r
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/\r
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) \r
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */\r
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) \r
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */\r
+\r
+/******************** Bit definition for USB_OTG_GCCFG register ********************/\r
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U) \r
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */\r
+#define USB_OTG_GCCFG_VBDEN_Pos (21U) \r
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */\r
+\r
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) \r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) \r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r
+\r
+/******************** Bit definition for USB_OTG_CID register ********************/\r
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U) \r
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */\r
+\r
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U) \r
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */\r
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) \r
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */\r
+#define USB_OTG_GLPMCFG_BESL_Pos (2U) \r
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) \r
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) \r
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */\r
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) \r
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */\r
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) \r
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */\r
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) \r
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */\r
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) \r
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */\r
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) \r
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) \r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */\r
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) \r
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */\r
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) \r
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) \r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */\r
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) \r
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) \r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) \r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) \r
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) \r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) \r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) \r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) \r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) \r
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) \r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPRT register ********************/\r
+#define USB_OTG_HPRT_PCSTS_Pos (0U) \r
+#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */\r
+#define USB_OTG_HPRT_PCDET_Pos (1U) \r
+#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */\r
+#define USB_OTG_HPRT_PENA_Pos (2U) \r
+#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */\r
+#define USB_OTG_HPRT_PENCHNG_Pos (3U) \r
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */\r
+#define USB_OTG_HPRT_POCA_Pos (4U) \r
+#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */\r
+#define USB_OTG_HPRT_POCCHNG_Pos (5U) \r
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */\r
+#define USB_OTG_HPRT_PRES_Pos (6U) \r
+#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */\r
+#define USB_OTG_HPRT_PSUSP_Pos (7U) \r
+#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */\r
+#define USB_OTG_HPRT_PRST_Pos (8U) \r
+#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */\r
+\r
+#define USB_OTG_HPRT_PLSTS_Pos (10U) \r
+#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */\r
+#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HPRT_PPWR_Pos (12U) \r
+#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */\r
+\r
+#define USB_OTG_HPRT_PTCTL_Pos (13U) \r
+#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */\r
+#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_HPRT_PSPD_Pos (17U) \r
+#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */\r
+#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) \r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) \r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) \r
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) \r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) \r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) \r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) \r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) \r
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) \r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) \r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) \r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/\r
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) \r
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */\r
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) \r
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/\r
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) \r
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */\r
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) \r
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) \r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\r
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) \r
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */\r
+\r
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) \r
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DIEPCTL_STALL_Pos (21U) \r
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */\r
+\r
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) \r
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */\r
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U) \r
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */\r
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U) \r
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) \r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) \r
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */\r
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) \r
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */\r
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U) \r
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/\r
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) \r
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */\r
+\r
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U) \r
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */\r
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U) \r
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */\r
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U) \r
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */\r
+\r
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U) \r
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r
+\r
+#define USB_OTG_HCCHAR_MC_Pos (20U) \r
+#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */\r
+#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r
+\r
+#define USB_OTG_HCCHAR_DAD_Pos (22U) \r
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */\r
+#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) \r
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */\r
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U) \r
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */\r
+#define USB_OTG_HCCHAR_CHENA_Pos (31U) \r
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/\r
+\r
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) \r
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */\r
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r
+\r
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) \r
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */\r
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) \r
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */\r
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) \r
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */\r
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) \r
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCINT register ********************/\r
+#define USB_OTG_HCINT_XFRC_Pos (0U) \r
+#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */\r
+#define USB_OTG_HCINT_CHH_Pos (1U) \r
+#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */\r
+#define USB_OTG_HCINT_AHBERR_Pos (2U) \r
+#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */\r
+#define USB_OTG_HCINT_STALL_Pos (3U) \r
+#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */\r
+#define USB_OTG_HCINT_NAK_Pos (4U) \r
+#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */\r
+#define USB_OTG_HCINT_ACK_Pos (5U) \r
+#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */\r
+#define USB_OTG_HCINT_NYET_Pos (6U) \r
+#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */\r
+#define USB_OTG_HCINT_TXERR_Pos (7U) \r
+#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */\r
+#define USB_OTG_HCINT_BBERR_Pos (8U) \r
+#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */\r
+#define USB_OTG_HCINT_FRMOR_Pos (9U) \r
+#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */\r
+#define USB_OTG_HCINT_DTERR_Pos (10U) \r
+#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/\r
+#define USB_OTG_DIEPINT_XFRC_Pos (0U) \r
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */\r
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U) \r
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DIEPINT_AHBERR_Pos (2U)\r
+#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */\r
+#define USB_OTG_DIEPINT_TOC_Pos (3U) \r
+#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */\r
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) \r
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */\r
+#define USB_OTG_DIEPINT_INEPNM_Pos (5U)\r
+#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */\r
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U) \r
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */\r
+#define USB_OTG_DIEPINT_TXFE_Pos (7U) \r
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) \r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r
+#define USB_OTG_DIEPINT_BNA_Pos (9U) \r
+#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) \r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r
+#define USB_OTG_DIEPINT_BERR_Pos (12U) \r
+#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */\r
+#define USB_OTG_DIEPINT_NAK_Pos (13U) \r
+#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */\r
+\r
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/\r
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) \r
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */\r
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U) \r
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */\r
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) \r
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */\r
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U) \r
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U) \r
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U) \r
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */\r
+#define USB_OTG_HCINTMSK_NYET_Pos (6U) \r
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) \r
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */\r
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) \r
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */\r
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) \r
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */\r
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) \r
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) \r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) \r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */\r
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) \r
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */\r
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/\r
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) \r
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) \r
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */\r
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U) \r
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */\r
+#define USB_OTG_HCTSIZ_DPID_Pos (29U) \r
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */\r
+#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/\r
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) \r
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */\r
+\r
+/******************** Bit definition for USB_OTG_HCDMA register ********************/\r
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U) \r
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */\r
+\r
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/\r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) \r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/\r
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) \r
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */\r
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) \r
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/\r
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) \r
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U) \r
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */\r
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) \r
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) \r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) \r
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */\r
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U) \r
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U) \r
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */\r
+#define USB_OTG_DOEPCTL_STALL_Pos (21U) \r
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */\r
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U) \r
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */\r
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U) \r
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */\r
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U) \r
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */\r
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U) \r
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/\r
+#define USB_OTG_DOEPINT_XFRC_Pos (0U) \r
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */\r
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U) \r
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DOEPINT_AHBERR_Pos (2U)\r
+#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */\r
+#define USB_OTG_DOEPINT_STUP_Pos (3U) \r
+#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */\r
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) \r
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */\r
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) \r
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */\r
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) \r
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */\r
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)\r
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */\r
+#define USB_OTG_DOEPINT_NAK_Pos (13U)\r
+#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */\r
+#define USB_OTG_DOEPINT_NYET_Pos (14U) \r
+#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */\r
+#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)\r
+#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) \r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) \r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */\r
+\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) \r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for PCGCCTL register ********************/\r
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) \r
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */\r
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) \r
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) \r
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* JPEG Encoder/Decoder */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for CONFR0 register ********************/\r
+#define JPEG_CONFR0_START_Pos (0U) \r
+#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */\r
+\r
+/******************** Bit definition for CONFR1 register *******************/\r
+#define JPEG_CONFR1_NF_Pos (0U) \r
+#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */\r
+#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */\r
+#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR1_RE_Pos (2U) \r
+#define JPEG_CONFR1_RE_Msk (0x1UL << JPEG_CONFR1_RE_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR1_RE JPEG_CONFR1_RE_Msk /*!<Restart maker Enable */\r
+#define JPEG_CONFR1_DE_Pos (3U) \r
+#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */\r
+#define JPEG_CONFR1_COLORSPACE_Pos (4U) \r
+#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */\r
+#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */\r
+#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR1_NS_Pos (6U) \r
+#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */\r
+#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */\r
+#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR1_HDR_Pos (8U) \r
+#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */\r
+#define JPEG_CONFR1_YSIZE_Pos (16U) \r
+#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */\r
+#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */\r
+\r
+/******************** Bit definition for CONFR2 register *******************/\r
+#define JPEG_CONFR2_NMCU_Pos (0U) \r
+#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */\r
+#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */\r
+\r
+/******************** Bit definition for CONFR3 register *******************/\r
+#define JPEG_CONFR3_NRST_Pos (0U) \r
+#define JPEG_CONFR3_NRST_Msk (0xFFFFUL << JPEG_CONFR3_NRST_Pos) /*!< 0x0000FFFF */\r
+#define JPEG_CONFR3_NRST JPEG_CONFR3_NRST_Msk /*!<Number of MCU between two restart makers minus 1 */\r
+#define JPEG_CONFR3_XSIZE_Pos (16U) \r
+#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */\r
+#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */\r
+\r
+/******************** Bit definition for CONFR4 register *******************/\r
+#define JPEG_CONFR4_HD_Pos (0U) \r
+#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR4_HA_Pos (1U) \r
+#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR4_QT_Pos (2U) \r
+#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR4_NB_Pos (4U) \r
+#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR4_VSF_Pos (8U) \r
+#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */\r
+#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR4_HSF_Pos (12U) \r
+#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */\r
+#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CONFR5 register *******************/\r
+#define JPEG_CONFR5_HD_Pos (0U) \r
+#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR5_HA_Pos (1U) \r
+#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR5_QT_Pos (2U) \r
+#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR5_NB_Pos (4U) \r
+#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR5_VSF_Pos (8U) \r
+#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR5_HSF_Pos (12U) \r
+#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CONFR6 register *******************/\r
+#define JPEG_CONFR6_HD_Pos (0U) \r
+#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR6_HA_Pos (1U) \r
+#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR6_QT_Pos (2U) \r
+#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR6_NB_Pos (4U) \r
+#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR6_VSF_Pos (8U) \r
+#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR6_HSF_Pos (12U) \r
+#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CONFR7 register *******************/\r
+#define JPEG_CONFR7_HD_Pos (0U) \r
+#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */\r
+#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */\r
+#define JPEG_CONFR7_HA_Pos (1U) \r
+#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */\r
+#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */\r
+#define JPEG_CONFR7_QT_Pos (2U) \r
+#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */\r
+#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */\r
+#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */\r
+#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */\r
+#define JPEG_CONFR7_NB_Pos (4U) \r
+#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */\r
+#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */\r
+#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */\r
+#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */\r
+#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */\r
+#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */\r
+#define JPEG_CONFR7_VSF_Pos (8U) \r
+#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */\r
+#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */\r
+#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */\r
+#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */\r
+#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */\r
+#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */\r
+#define JPEG_CONFR7_HSF_Pos (12U) \r
+#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */\r
+#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */\r
+#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */\r
+#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bit definition for CR register *******************/\r
+#define JPEG_CR_JCEN_Pos (0U) \r
+#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */\r
+#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */\r
+#define JPEG_CR_IFTIE_Pos (1U) \r
+#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */\r
+#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */\r
+#define JPEG_CR_IFNFIE_Pos (2U) \r
+#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */\r
+#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */\r
+#define JPEG_CR_OFTIE_Pos (3U) \r
+#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */\r
+#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */\r
+#define JPEG_CR_OFNEIE_Pos (4U) \r
+#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */\r
+#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */\r
+#define JPEG_CR_EOCIE_Pos (5U) \r
+#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */\r
+#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */\r
+#define JPEG_CR_HPDIE_Pos (6U) \r
+#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */\r
+#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */\r
+#define JPEG_CR_IDMAEN_Pos (11U) \r
+#define JPEG_CR_IDMAEN_Msk (0x1UL << JPEG_CR_IDMAEN_Pos) /*!< 0x00000800 */\r
+#define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk /*!<Enable the DMA request generation for the input FIFO */\r
+#define JPEG_CR_ODMAEN_Pos (12U) \r
+#define JPEG_CR_ODMAEN_Msk (0x1UL << JPEG_CR_ODMAEN_Pos) /*!< 0x00001000 */\r
+#define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk /*!<Enable the DMA request generation for the output FIFO */\r
+#define JPEG_CR_IFF_Pos (13U) \r
+#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */\r
+#define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */\r
+#define JPEG_CR_OFF_Pos (14U) \r
+#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */\r
+#define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */\r
+\r
+/******************** Bit definition for SR register *******************/\r
+#define JPEG_SR_IFTF_Pos (1U) \r
+#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */\r
+#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */\r
+#define JPEG_SR_IFNFF_Pos (2U) \r
+#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */\r
+#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */\r
+#define JPEG_SR_OFTF_Pos (3U) \r
+#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */\r
+#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */\r
+#define JPEG_SR_OFNEF_Pos (4U) \r
+#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000001 */\r
+#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */\r
+#define JPEG_SR_EOCF_Pos (5U) \r
+#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000002 */\r
+#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */\r
+#define JPEG_SR_HPDF_Pos (6U) \r
+#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000004 */\r
+#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */\r
+#define JPEG_SR_COF_Pos (7U) \r
+#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000008 */\r
+#define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */\r
+\r
+/******************** Bit definition for CFR register *******************/\r
+#define JPEG_CFR_CEOCF_Pos (5U) \r
+#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000020 */\r
+#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */\r
+#define JPEG_CFR_CHPDF_Pos (6U) \r
+#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000040 */\r
+#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */\r
+\r
+/******************** Bit definition for DIR register ********************/\r
+#define JPEG_DIR_DATAIN_Pos (0U) \r
+#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */\r
+#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */\r
+\r
+/******************** Bit definition for DOR register ********************/\r
+#define JPEG_DOR_DATAOUT_Pos (0U) \r
+#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */\r
+#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* MDIOS */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for MDIOS_CR register *******************/\r
+#define MDIOS_CR_EN_Pos (0U) \r
+#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */\r
+#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!<Peripheral enable */\r
+#define MDIOS_CR_WRIE_Pos (1U) \r
+#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */\r
+#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!<Register write interrupt enable */\r
+#define MDIOS_CR_RDIE_Pos (2U) \r
+#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */\r
+#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!<Register Read Interrupt Enable */\r
+#define MDIOS_CR_EIE_Pos (3U) \r
+#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */\r
+#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!<Error interrupt enable */\r
+#define MDIOS_CR_DPC_Pos (7U) \r
+#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */\r
+#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!<Disable Preamble Check */\r
+#define MDIOS_CR_PORT_ADDRESS_Pos (8U) \r
+#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */\r
+#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!<PORT_ADDRESS[4:0] bits */\r
+#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */\r
+#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */\r
+#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */\r
+#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */\r
+#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */\r
+\r
+/******************** Bit definition for MDIOS_WRFR register *******************/\r
+#define MDIOS_WRFR_WRF_Pos (0U) \r
+#define MDIOS_WRFR_WRF_Msk (0xFFFFFFFFUL << MDIOS_WRFR_WRF_Pos) /*!< 0xFFFFFFFF */\r
+#define MDIOS_WRFR_WRF MDIOS_WRFR_WRF_Msk /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_CWRFR register *******************/\r
+#define MDIOS_CWRFR_CWRF_Pos (0U) \r
+#define MDIOS_CWRFR_CWRF_Msk (0xFFFFFFFFUL << MDIOS_CWRFR_CWRF_Pos) /*!< 0xFFFFFFFF */\r
+#define MDIOS_CWRFR_CWRF MDIOS_CWRFR_CWRF_Msk /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_RDFR register *******************/\r
+#define MDIOS_RDFR_RDF_Pos (0U) \r
+#define MDIOS_RDFR_RDF_Msk (0xFFFFFFFFUL << MDIOS_RDFR_RDF_Pos) /*!< 0xFFFFFFFF */\r
+#define MDIOS_RDFR_RDF MDIOS_RDFR_RDF_Msk /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_CRDFR register *******************/\r
+#define MDIOS_CRDFR_CRDF_Pos (0U) \r
+#define MDIOS_CRDFR_CRDF_Msk (0xFFFFFFFFUL << MDIOS_CRDFR_CRDF_Pos) /*!< 0xFFFFFFFF */\r
+#define MDIOS_CRDFR_CRDF MDIOS_CRDFR_CRDF_Msk /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */\r
+\r
+/******************** Bit definition for MDIOS_SR register *******************/\r
+#define MDIOS_SR_PERF_Pos (0U) \r
+#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */\r
+#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< Preamble error flag */\r
+#define MDIOS_SR_SERF_Pos (1U) \r
+#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */\r
+#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< Start error flag */\r
+#define MDIOS_SR_TERF_Pos (2U) \r
+#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */\r
+#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< Turnaround error flag */\r
+\r
+/******************** Bit definition for MDIOS_CLRFR register *******************/\r
+#define MDIOS_CLRFR_CPERF_Pos (0U) \r
+#define MDIOS_CLRFR_CPERF_Msk (0x1UL << MDIOS_CLRFR_CPERF_Pos) /*!< 0x00000001 */\r
+#define MDIOS_CLRFR_CPERF MDIOS_CLRFR_CPERF_Msk /*!< Clear the preamble error flag */\r
+#define MDIOS_CLRFR_CSERF_Pos (1U) \r
+#define MDIOS_CLRFR_CSERF_Msk (0x1UL << MDIOS_CLRFR_CSERF_Pos) /*!< 0x00000002 */\r
+#define MDIOS_CLRFR_CSERF MDIOS_CLRFR_CSERF_Msk /*!< Clear the start error flag */\r
+#define MDIOS_CLRFR_CTERF_Pos (2U) \r
+#define MDIOS_CLRFR_CTERF_Msk (0x1UL << MDIOS_CLRFR_CTERF_Pos) /*!< 0x00000004 */\r
+#define MDIOS_CLRFR_CTERF MDIOS_CLRFR_CTERF_Msk /*!< Clear the turnaround error flag */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+\r
+/******************************* ADC Instances ********************************/\r
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \\r
+ ((__INSTANCE__) == ADC2) || \\r
+ ((__INSTANCE__) == ADC3))\r
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r
+\r
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\r
+\r
+/******************************* CAN Instances ********************************/\r
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \\r
+ ((__INSTANCE__) == CAN2) || \\r
+ ((__INSTANCE__) == CAN3))\r
+/******************************* CRC Instances ********************************/\r
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)\r
+\r
+/******************************* DAC Instances ********************************/\r
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)\r
+\r
+/******************************* DCMI Instances *******************************/\r
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r
+\r
+/****************************** DFSDM Instances *******************************/\r
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\r
+ ((INSTANCE) == DFSDM1_Filter1) || \\r
+ ((INSTANCE) == DFSDM1_Filter2) || \\r
+ ((INSTANCE) == DFSDM1_Filter3))\r
+\r
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\r
+ ((INSTANCE) == DFSDM1_Channel1) || \\r
+ ((INSTANCE) == DFSDM1_Channel2) || \\r
+ ((INSTANCE) == DFSDM1_Channel3) || \\r
+ ((INSTANCE) == DFSDM1_Channel4) || \\r
+ ((INSTANCE) == DFSDM1_Channel5) || \\r
+ ((INSTANCE) == DFSDM1_Channel6) || \\r
+ ((INSTANCE) == DFSDM1_Channel7))\r
+\r
+/******************************* DMA2D Instances *******************************/\r
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r
+\r
+/******************************** DMA Instances *******************************/\r
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \\r
+ ((__INSTANCE__) == DMA1_Stream1) || \\r
+ ((__INSTANCE__) == DMA1_Stream2) || \\r
+ ((__INSTANCE__) == DMA1_Stream3) || \\r
+ ((__INSTANCE__) == DMA1_Stream4) || \\r
+ ((__INSTANCE__) == DMA1_Stream5) || \\r
+ ((__INSTANCE__) == DMA1_Stream6) || \\r
+ ((__INSTANCE__) == DMA1_Stream7) || \\r
+ ((__INSTANCE__) == DMA2_Stream0) || \\r
+ ((__INSTANCE__) == DMA2_Stream1) || \\r
+ ((__INSTANCE__) == DMA2_Stream2) || \\r
+ ((__INSTANCE__) == DMA2_Stream3) || \\r
+ ((__INSTANCE__) == DMA2_Stream4) || \\r
+ ((__INSTANCE__) == DMA2_Stream5) || \\r
+ ((__INSTANCE__) == DMA2_Stream6) || \\r
+ ((__INSTANCE__) == DMA2_Stream7))\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+\r
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI) || \\r
+ ((__INSTANCE__) == GPIOJ) || \\r
+ ((__INSTANCE__) == GPIOK))\r
+\r
+/****************************** CEC Instances *********************************/\r
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r
+\r
+/****************************** QSPI Instances *********************************/\r
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r
+\r
+\r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\r
+ ((__INSTANCE__) == I2C2) || \\r
+ ((__INSTANCE__) == I2C3) || \\r
+ ((__INSTANCE__) == I2C4))\r
+\r
+/****************************** SMBUS Instances *******************************/\r
+#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\r
+ ((__INSTANCE__) == I2C2) || \\r
+ ((__INSTANCE__) == I2C3) || \\r
+ ((__INSTANCE__) == I2C4))\r
+\r
+\r
+/******************************** I2S Instances *******************************/\r
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3))\r
+\r
+/******************************* LPTIM Instances ********************************/\r
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\r
+\r
+/****************************** LTDC Instances ********************************/\r
+#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)\r
+\r
+/****************************** MDIOS Instances ********************************/\r
+#define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)\r
+\r
+/****************************** MDIOS Instances ********************************/\r
+#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)\r
+\r
+\r
+/******************************* RNG Instances ********************************/\r
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)\r
+\r
+/******************************* SAI Instances ********************************/\r
+#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \\r
+ ((__PERIPH__) == SAI1_Block_B) || \\r
+ ((__PERIPH__) == SAI2_Block_A) || \\r
+ ((__PERIPH__) == SAI2_Block_B))\r
+/* Legacy define */\r
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\r
+\r
+/******************************** SDMMC Instances *******************************/\r
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \\r
+ ((__INSTANCE__) == SDMMC2))\r
+\r
+/****************************** SPDIFRX Instances *********************************/\r
+#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)\r
+\r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3) || \\r
+ ((__INSTANCE__) == SPI4) || \\r
+ ((__INSTANCE__) == SPI5) || \\r
+ ((__INSTANCE__) == SPI6))\r
+\r
+/****************** TIM Instances : All supported instances *******************/\r
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/****************** TIM Instances : supporting 32 bits counter ****************/\r
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5))\r
+\r
+/****************** TIM Instances : supporting the break function *************/\r
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/************** TIM Instances : supporting Break source selection *************/\r
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting 2 break inputs *****************/\r
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/************* TIM Instances : at least 1 capture/compare channel *************/\r
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************ TIM Instances : at least 2 capture/compare channels *************/\r
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/************ TIM Instances : at least 3 capture/compare channels *************/\r
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : at least 4 capture/compare channels *************/\r
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : at least 5 capture/compare channels *******/\r
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : at least 6 capture/compare channels *******/\r
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/\r
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/\r
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7))\r
+\r
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************** TIM Instances : DMA burst feature ***********************/\r
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting counting mode selection ********/\r
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting encoder interface **************/\r
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting OCxREF clear *******************/\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5))\r
+\r
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************** TIM Instances : Advanced-control timers *****************/\r
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************* TIM Instances : Timer input XOR function *****************/\r
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/***************** TIM Instances : external trigger input available ************/\r
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : remapping capability **********************/\r
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM11))\r
+\r
+/******************* TIM Instances : output(s) available **********************/\r
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_6))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM2) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM3) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM4) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM5) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_6))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM9) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM10) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM11) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM12) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM13) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM14) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))))\r
+\r
+/************ TIM Instances : complementary output(s) available ***************/\r
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))))\r
+\r
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : supporting synchronization ****************/\r
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting clock division *****************/\r
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+ \r
+/****************** TIM Instances : supporting repetition counter *************/\r
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+ \r
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting Hall sensor interface **********/\r
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+ \r
+/****************** TIM Instances : supporting commutation event generation ***/\r
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8)) \r
+\r
+/******************** USART Instances : Synchronous mode **********************/\r
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Auto Baud Rate detection ****************/\r
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/****************** UART Instances : Driver Enable *****************/\r
+#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/******************** UART Instances : Half-Duplex mode **********************/\r
+#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Hardware Flow control ********************/\r
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/******************** UART Instances : LIN mode **********************/\r
+#define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/********************* UART Instances : Smart card mode ***********************/\r
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/*********************** UART Instances : IRDA mode ***************************/\r
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)\r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)\r
+\r
+/*********************** PCD Instances ****************************************/\r
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+\r
+/*********************** HCD Instances ****************************************/\r
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+\r
+/******************************************************************************/\r
+/* For a painless codes migration between the STM32F7xx device product */\r
+/* lines, the aliases defined below are put in place to overcome the */\r
+/* differences in the interrupt handlers and IRQn definitions. */\r
+/* No need to update developed interrupt code when moving across */\r
+/* product lines within the same STM32F7 Family */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+#define HASH_RNG_IRQn RNG_IRQn\r
+\r
+/* Aliases for __IRQHandler */\r
+#define HASH_RNG_IRQHandler RNG_IRQHandler\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F767xx_H */\r
+\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.\r
+ *\r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The STM32F7xx device used in the target application\r
+ * - To use or not the peripheral\92s drivers in application code(i.e.\r
+ * code will be based on direct access to peripheral\92s registers\r
+ * rather than drivers API), this option is controlled by\r
+ * "#define USE_HAL_DRIVER"\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx\r
+ * @{\r
+ */\r
+\r
+#ifndef __STM32F7xx_H\r
+#define __STM32F7xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32 Family\r
+ */\r
+#if !defined (STM32F7)\r
+#define STM32F7\r
+#endif /* STM32F7 */\r
+\r
+/* Uncomment the line below according to the target STM32 device used in your\r
+ application\r
+ */\r
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \\r
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \\r
+ !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && !defined (STM32F730xx) && \\r
+ !defined (STM32F750xx)\r
+\r
+ /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,\r
+ STM32F756NG Devices */\r
+ /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,\r
+ STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */\r
+ /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */\r
+ /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,\r
+ STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */\r
+ /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,\r
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */\r
+ /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,\r
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */\r
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */\r
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */\r
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,\r
+ STM32F722VC, STM32F722RC Devices */\r
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */\r
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */\r
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */\r
+ /* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */\r
+ /* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */\r
+#endif\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+\r
+#if !defined (USE_HAL_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will\r
+ be based on direct access to peripherals registers\r
+ */\r
+ /*#define USE_HAL_DRIVER */\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+/**\r
+ * @brief CMSIS Device version number V1.2.4\r
+ */\r
+#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\r
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */\r
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */\r
+#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\\r
+ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\\r
+ |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\\r
+ |(__STM32F7_CMSIS_VERSION_RC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Device_Included\r
+ * @{\r
+ */\r
+#if defined(STM32F722xx)\r
+ #include "stm32f722xx.h"\r
+#elif defined(STM32F723xx)\r
+ #include "stm32f723xx.h"\r
+#elif defined(STM32F732xx)\r
+ #include "stm32f732xx.h"\r
+#elif defined(STM32F733xx)\r
+ #include "stm32f733xx.h"\r
+#elif defined(STM32F756xx)\r
+ #include "stm32f756xx.h"\r
+#elif defined(STM32F746xx)\r
+ #include "stm32f746xx.h"\r
+#elif defined(STM32F745xx)\r
+ #include "stm32f745xx.h"\r
+#elif defined(STM32F765xx)\r
+ #include "stm32f765xx.h"\r
+#elif defined(STM32F767xx)\r
+ #include "stm32f767xx.h"\r
+#elif defined(STM32F769xx)\r
+ #include "stm32f769xx.h"\r
+#elif defined(STM32F777xx)\r
+ #include "stm32f777xx.h"\r
+#elif defined(STM32F779xx)\r
+ #include "stm32f779xx.h"\r
+#elif defined(STM32F730xx)\r
+ #include "stm32f730xx.h"\r
+#elif defined(STM32F750xx)\r
+ #include "stm32f750xx.h"\r
+#else\r
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ RESET = 0U,\r
+ SET = !RESET\r
+} FlagStatus, ITStatus;\r
+\r
+typedef enum\r
+{\r
+ DISABLE = 0U,\r
+ ENABLE = !DISABLE\r
+} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum\r
+{\r
+ SUCCESS = 0U,\r
+ ERROR = !SUCCESS\r
+} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef USE_HAL_DRIVER\r
+ #include "stm32f7xx_hal.h"\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F7xx_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f7xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. \r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F7XX_H\r
+#define __SYSTEM_STM32F7XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F7xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Variables\r
+ * @{\r
+ */\r
+ /* The SystemCoreClock variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */\r
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F7XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armcc.h\r
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* CMSIS compiler control architecture macros */\r
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \\r
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )\r
+ #define __ARM_ARCH_6M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))\r
+ #define __ARM_ARCH_7M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\r
+ #define __ARM_ARCH_7EM__ 1\r
+#endif\r
+\r
+ /* __ARM_ARCH_8M_BASE__ not applicable */\r
+ /* __ARM_ARCH_8M_MAIN__ not applicable */\r
+\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE static __forceinline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __declspec(noreturn)\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT __packed struct\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION __packed union\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1U);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+ \r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+ return result;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+#else\r
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXB(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXH(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXW(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32U) ) >> 32U))\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armclang.h\r
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\r
+\r
+#ifndef __CMSIS_ARMCLANG_H\r
+#define __CMSIS_ARMCLANG_H\r
+\r
+#pragma clang system_header /* treat file as system include file */\r
+\r
+#ifndef __ARM_COMPAT_H\r
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr\r
+#else\r
+#define __get_FPSCR() ((uint32_t)0U)\r
+#endif\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __set_FPSCR __builtin_arm_set_fpscr\r
+#else\r
+#define __set_FPSCR(x) ((void)(x))\r
+#endif\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __builtin_arm_nop\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __builtin_arm_wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __builtin_arm_wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __builtin_arm_sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() __builtin_arm_isb(0xF);\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __builtin_arm_dsb(0xF);\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __builtin_arm_dmb(0xF);\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV(value) __builtin_bswap32(value)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV16(value) __ROR(__REV(value), 16)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __builtin_arm_rbit\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB (uint8_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH (uint16_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW (uint32_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __builtin_arm_clrex\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __builtin_arm_ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __builtin_arm_usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDAEX (uint32_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXB (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXH (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEX (uint32_t)__builtin_arm_stlex\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCLANG_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_compiler.h\r
+ * @brief CMSIS compiler generic header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_COMPILER_H\r
+#define __CMSIS_COMPILER_H\r
+\r
+#include <stdint.h>\r
+\r
+/*\r
+ * Arm Compiler 4/5\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+\r
+/*\r
+ * Arm Compiler 6 (armclang)\r
+ */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armclang.h"\r
+\r
+\r
+/*\r
+ * GNU Compiler\r
+ */\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+\r
+/*\r
+ * IAR Compiler\r
+ */\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iccarm.h>\r
+\r
+\r
+/*\r
+ * TI Arm Compiler\r
+ */\r
+#elif defined ( __TI_ARM__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+/*\r
+ * TASKING Compiler\r
+ */\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __packed__\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __packed__\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __packed__\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __packed__ T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __align(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+/*\r
+ * COSMIC Compiler\r
+ */\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM _asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ // NO RETURN is automatically detected hence no warning here\r
+ #define __NO_RETURN\r
+ #endif\r
+ #ifndef __USED\r
+ #warning No compiler specific solution for __USED. __USED is ignored.\r
+ #define __USED\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __weak\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED @packed\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT @packed struct\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION @packed union\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ @packed struct T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+#else\r
+ #error Unknown compiler.\r
+#endif\r
+\r
+\r
+#endif /* __CMSIS_COMPILER_H */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS compiler GCC header file\r
+ * @version V5.0.4\r
+ * @date 09. April 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+/* Fallback for __has_builtin */\r
+#ifndef __has_builtin\r
+ #define __has_builtin(x) (0)\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_get_fpscr) \r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ return __builtin_arm_get_fpscr();\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#endif\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_set_fpscr)\r
+// Re-enable using built-in when GCC has been fixed\r
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ __builtin_arm_set_fpscr(fpscr);\r
+#else\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");\r
+#endif\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP() __ASM volatile ("nop")\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI() __ASM volatile ("wfi")\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE() __ASM volatile ("wfe")\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV() __ASM volatile ("sev")\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__STATIC_FORCEINLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__STATIC_FORCEINLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__STATIC_FORCEINLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (int16_t)__builtin_bswap16(value);\r
+#else\r
+ int16_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__STATIC_FORCEINLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+__extension__ \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+ __extension__ \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#pragma GCC diagnostic pop\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_iccarm.h\r
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
+ * @version V5.0.7\r
+ * @date 19. June 2018\r
+ ******************************************************************************/\r
+\r
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2017-2018 IAR Systems\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License")\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef __CMSIS_ICCARM_H__\r
+#define __CMSIS_ICCARM_H__\r
+\r
+#ifndef __ICCARM__\r
+ #error This file should only be compiled by ICCARM\r
+#endif\r
+\r
+#pragma system_include\r
+\r
+#define __IAR_FT _Pragma("inline=forced") __intrinsic\r
+\r
+#if (__VER__ >= 8000000)\r
+ #define __ICCARM_V8 1\r
+#else\r
+ #define __ICCARM_V8 0\r
+#endif\r
+\r
+#ifndef __ALIGNED\r
+ #if __ICCARM_V8\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #elif (__VER__ >= 7080000)\r
+ /* Needs IAR language extensions */\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #else\r
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+#endif\r
+\r
+\r
+/* Define compiler macros for CPU architecture, used in CMSIS 5.\r
+ */\r
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\r
+/* Macros already defined */\r
+#else\r
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\r
+ #if __ARM_ARCH == 6\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif __ARM_ARCH == 7\r
+ #if __ARM_FEATURE_DSP\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #else\r
+ #define __ARM_ARCH_7M__ 1\r
+ #endif\r
+ #endif /* __ARM_ARCH */\r
+ #endif /* __ARM_ARCH_PROFILE == 'M' */\r
+#endif\r
+\r
+/* Alternativ core deduction for older ICCARM's */\r
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\r
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\r
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\r
+ #define __ARM_ARCH_7M__ 1\r
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #else\r
+ #error "Unknown target."\r
+ #endif\r
+#endif\r
+\r
+\r
+\r
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#else\r
+ #define __IAR_M0_FAMILY 0\r
+#endif\r
+\r
+\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+\r
+#ifndef __NO_RETURN\r
+ #if __ICCARM_V8\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+ #else\r
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED\r
+ #if __ICCARM_V8\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED __packed\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_STRUCT\r
+ #if __ICCARM_V8\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_STRUCT __packed struct\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_UNION\r
+ #if __ICCARM_V8\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_UNION __packed union\r
+ #endif\r
+#endif\r
+\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+\r
+#ifndef __FORCEINLINE\r
+ #define __FORCEINLINE _Pragma("inline=forced")\r
+#endif\r
+\r
+#ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT16_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\r
+{\r
+ return *(__packed uint16_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\r
+#endif\r
+\r
+\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\r
+{\r
+ *(__packed uint16_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\r
+{\r
+ return *(__packed uint32_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\r
+{\r
+ *(__packed uint32_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+#pragma language=save\r
+#pragma language=extended\r
+__packed struct __iar_u32 { uint32_t v; };\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\r
+#endif\r
+\r
+#ifndef __USED\r
+ #if __ICCARM_V8\r
+ #define __USED __attribute__((used))\r
+ #else\r
+ #define __USED _Pragma("__root")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __WEAK\r
+ #if __ICCARM_V8\r
+ #define __WEAK __attribute__((weak))\r
+ #else\r
+ #define __WEAK _Pragma("__weak")\r
+ #endif\r
+#endif\r
+\r
+\r
+#ifndef __ICCARM_INTRINSICS_VERSION__\r
+ #define __ICCARM_INTRINSICS_VERSION__ 0\r
+#endif\r
+\r
+#if __ICCARM_INTRINSICS_VERSION__ == 2\r
+\r
+ #if defined(__CLZ)\r
+ #undef __CLZ\r
+ #endif\r
+ #if defined(__REVSH)\r
+ #undef __REVSH\r
+ #endif\r
+ #if defined(__RBIT)\r
+ #undef __RBIT\r
+ #endif\r
+ #if defined(__SSAT)\r
+ #undef __SSAT\r
+ #endif\r
+ #if defined(__USAT)\r
+ #undef __USAT\r
+ #endif\r
+\r
+ #include "iccarm_builtin.h"\r
+\r
+ #define __disable_fault_irq __iar_builtin_disable_fiq\r
+ #define __disable_irq __iar_builtin_disable_interrupt\r
+ #define __enable_fault_irq __iar_builtin_enable_fiq\r
+ #define __enable_irq __iar_builtin_enable_interrupt\r
+ #define __arm_rsr __iar_builtin_rsr\r
+ #define __arm_wsr __iar_builtin_wsr\r
+\r
+\r
+ #define __get_APSR() (__arm_rsr("APSR"))\r
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))\r
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))\r
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))\r
+\r
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))\r
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))\r
+ #else\r
+ #define __get_FPSCR() ( 0 )\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #define __get_IPSR() (__arm_rsr("IPSR"))\r
+ #define __get_MSP() (__arm_rsr("MSP"))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __get_MSPLIM() (0U)\r
+ #else\r
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))\r
+ #endif\r
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))\r
+ #define __get_PSP() (__arm_rsr("PSP"))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __get_PSPLIM() (0U)\r
+ #else\r
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))\r
+ #endif\r
+\r
+ #define __get_xPSR() (__arm_rsr("xPSR"))\r
+\r
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))\r
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))\r
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))\r
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))\r
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))\r
+ #endif\r
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))\r
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))\r
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))\r
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))\r
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))\r
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))\r
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))\r
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))\r
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))\r
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))\r
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))\r
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))\r
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))\r
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))\r
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __TZ_get_PSPLIM_NS() (0U)\r
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))\r
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))\r
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))\r
+\r
+ #define __NOP __iar_builtin_no_operation\r
+\r
+ #define __CLZ __iar_builtin_CLZ\r
+ #define __CLREX __iar_builtin_CLREX\r
+\r
+ #define __DMB __iar_builtin_DMB\r
+ #define __DSB __iar_builtin_DSB\r
+ #define __ISB __iar_builtin_ISB\r
+\r
+ #define __LDREXB __iar_builtin_LDREXB\r
+ #define __LDREXH __iar_builtin_LDREXH\r
+ #define __LDREXW __iar_builtin_LDREX\r
+\r
+ #define __RBIT __iar_builtin_RBIT\r
+ #define __REV __iar_builtin_REV\r
+ #define __REV16 __iar_builtin_REV16\r
+\r
+ __IAR_FT int16_t __REVSH(int16_t val)\r
+ {\r
+ return (int16_t) __iar_builtin_REVSH(val);\r
+ }\r
+\r
+ #define __ROR __iar_builtin_ROR\r
+ #define __RRX __iar_builtin_RRX\r
+\r
+ #define __SEV __iar_builtin_SEV\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __SSAT __iar_builtin_SSAT\r
+ #endif\r
+\r
+ #define __STREXB __iar_builtin_STREXB\r
+ #define __STREXH __iar_builtin_STREXH\r
+ #define __STREXW __iar_builtin_STREX\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __USAT __iar_builtin_USAT\r
+ #endif\r
+\r
+ #define __WFE __iar_builtin_WFE\r
+ #define __WFI __iar_builtin_WFI\r
+\r
+ #if __ARM_MEDIA__\r
+ #define __SADD8 __iar_builtin_SADD8\r
+ #define __QADD8 __iar_builtin_QADD8\r
+ #define __SHADD8 __iar_builtin_SHADD8\r
+ #define __UADD8 __iar_builtin_UADD8\r
+ #define __UQADD8 __iar_builtin_UQADD8\r
+ #define __UHADD8 __iar_builtin_UHADD8\r
+ #define __SSUB8 __iar_builtin_SSUB8\r
+ #define __QSUB8 __iar_builtin_QSUB8\r
+ #define __SHSUB8 __iar_builtin_SHSUB8\r
+ #define __USUB8 __iar_builtin_USUB8\r
+ #define __UQSUB8 __iar_builtin_UQSUB8\r
+ #define __UHSUB8 __iar_builtin_UHSUB8\r
+ #define __SADD16 __iar_builtin_SADD16\r
+ #define __QADD16 __iar_builtin_QADD16\r
+ #define __SHADD16 __iar_builtin_SHADD16\r
+ #define __UADD16 __iar_builtin_UADD16\r
+ #define __UQADD16 __iar_builtin_UQADD16\r
+ #define __UHADD16 __iar_builtin_UHADD16\r
+ #define __SSUB16 __iar_builtin_SSUB16\r
+ #define __QSUB16 __iar_builtin_QSUB16\r
+ #define __SHSUB16 __iar_builtin_SHSUB16\r
+ #define __USUB16 __iar_builtin_USUB16\r
+ #define __UQSUB16 __iar_builtin_UQSUB16\r
+ #define __UHSUB16 __iar_builtin_UHSUB16\r
+ #define __SASX __iar_builtin_SASX\r
+ #define __QASX __iar_builtin_QASX\r
+ #define __SHASX __iar_builtin_SHASX\r
+ #define __UASX __iar_builtin_UASX\r
+ #define __UQASX __iar_builtin_UQASX\r
+ #define __UHASX __iar_builtin_UHASX\r
+ #define __SSAX __iar_builtin_SSAX\r
+ #define __QSAX __iar_builtin_QSAX\r
+ #define __SHSAX __iar_builtin_SHSAX\r
+ #define __USAX __iar_builtin_USAX\r
+ #define __UQSAX __iar_builtin_UQSAX\r
+ #define __UHSAX __iar_builtin_UHSAX\r
+ #define __USAD8 __iar_builtin_USAD8\r
+ #define __USADA8 __iar_builtin_USADA8\r
+ #define __SSAT16 __iar_builtin_SSAT16\r
+ #define __USAT16 __iar_builtin_USAT16\r
+ #define __UXTB16 __iar_builtin_UXTB16\r
+ #define __UXTAB16 __iar_builtin_UXTAB16\r
+ #define __SXTB16 __iar_builtin_SXTB16\r
+ #define __SXTAB16 __iar_builtin_SXTAB16\r
+ #define __SMUAD __iar_builtin_SMUAD\r
+ #define __SMUADX __iar_builtin_SMUADX\r
+ #define __SMMLA __iar_builtin_SMMLA\r
+ #define __SMLAD __iar_builtin_SMLAD\r
+ #define __SMLADX __iar_builtin_SMLADX\r
+ #define __SMLALD __iar_builtin_SMLALD\r
+ #define __SMLALDX __iar_builtin_SMLALDX\r
+ #define __SMUSD __iar_builtin_SMUSD\r
+ #define __SMUSDX __iar_builtin_SMUSDX\r
+ #define __SMLSD __iar_builtin_SMLSD\r
+ #define __SMLSDX __iar_builtin_SMLSDX\r
+ #define __SMLSLD __iar_builtin_SMLSLD\r
+ #define __SMLSLDX __iar_builtin_SMLSLDX\r
+ #define __SEL __iar_builtin_SEL\r
+ #define __QADD __iar_builtin_QADD\r
+ #define __QSUB __iar_builtin_QSUB\r
+ #define __PKHBT __iar_builtin_PKHBT\r
+ #define __PKHTB __iar_builtin_PKHTB\r
+ #endif\r
+\r
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #define __CLZ __cmsis_iar_clz_not_active\r
+ #define __SSAT __cmsis_iar_ssat_not_active\r
+ #define __USAT __cmsis_iar_usat_not_active\r
+ #define __RBIT __cmsis_iar_rbit_not_active\r
+ #define __get_APSR __cmsis_iar_get_APSR_not_active\r
+ #endif\r
+\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\r
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\r
+ #endif\r
+\r
+ #ifdef __INTRINSICS_INCLUDED\r
+ #error intrinsics.h is already included previously!\r
+ #endif\r
+\r
+ #include <intrinsics.h>\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #undef __CLZ\r
+ #undef __SSAT\r
+ #undef __USAT\r
+ #undef __RBIT\r
+ #undef __get_APSR\r
+\r
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)\r
+ {\r
+ if (data == 0U) { return 32U; }\r
+\r
+ uint32_t count = 0U;\r
+ uint32_t mask = 0x80000000U;\r
+\r
+ while ((data & mask) == 0U)\r
+ {\r
+ count += 1U;\r
+ mask = mask >> 1U;\r
+ }\r
+ return count;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)\r
+ {\r
+ uint8_t sc = 31U;\r
+ uint32_t r = v;\r
+ for (v >>= 1U; v; v >>= 1U)\r
+ {\r
+ r <<= 1U;\r
+ r |= v & 1U;\r
+ sc--;\r
+ }\r
+ return (r << sc);\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __get_APSR(void)\r
+ {\r
+ uint32_t res;\r
+ __asm("MRS %0,APSR" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ #endif\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #undef __get_FPSCR\r
+ #undef __set_FPSCR\r
+ #define __get_FPSCR() (0)\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #pragma diag_suppress=Pe940\r
+ #pragma diag_suppress=Pe177\r
+\r
+ #define __enable_irq __enable_interrupt\r
+ #define __disable_irq __disable_interrupt\r
+ #define __NOP __no_operation\r
+\r
+ #define __get_xPSR __get_PSR\r
+\r
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\r
+\r
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\r
+ {\r
+ return __LDREX((unsigned long *)ptr);\r
+ }\r
+\r
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\r
+ {\r
+ return __STREX(value, (unsigned long *)ptr);\r
+ }\r
+ #endif\r
+\r
+\r
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+ #if (__CORTEX_M >= 0x03)\r
+\r
+ __IAR_FT uint32_t __RRX(uint32_t value)\r
+ {\r
+ uint32_t result;\r
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");\r
+ return(result);\r
+ }\r
+\r
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));\r
+ }\r
+\r
+\r
+ #define __enable_fault_irq __enable_fiq\r
+ #define __disable_fault_irq __disable_fiq\r
+\r
+\r
+ #endif /* (__CORTEX_M >= 0x03) */\r
+\r
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+ {\r
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\r
+ }\r
+\r
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+ __IAR_FT uint32_t __get_MSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_MSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __get_PSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_PSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))\r
+\r
+#if __IAR_M0_FAMILY\r
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+ {\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+ {\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+ }\r
+#endif\r
+\r
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+\r
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+ {\r
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+ {\r
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\r
+ {\r
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");\r
+ }\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+\r
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#undef __IAR_FT\r
+#undef __IAR_M0_FAMILY\r
+#undef __ICCARM_V8\r
+\r
+#pragma diag_default=Pe940\r
+#pragma diag_default=Pe177\r
+\r
+#endif /* __CMSIS_ICCARM_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_version.h\r
+ * @brief CMSIS Core(M) Version definitions\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CMSIS_VERSION_H\r
+#define __CMSIS_VERSION_H\r
+\r
+/* CMSIS Version definitions */\r
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */\r
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */\r
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mbl.h\r
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\r
+ * @version V5.0.7\r
+ * @date 22. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MBL_H_GENERIC\r
+#define __CORE_ARMV8MBL_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MBL\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS definitions */\r
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT\r
+#define __CORE_ARMV8MBL_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MBL_REV\r
+ #define __ARMv8MBL_REV 0x0000U\r
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ETM_PRESENT\r
+ #define __ETM_PRESENT 0U\r
+ #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MTB_PRESENT\r
+ #define __MTB_PRESENT 0U\r
+ #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MBL */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ uint32_t RESERVED0[6U];\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[809U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */\r
+ uint32_t RESERVED4[4U];\r
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ uint32_t RESERVED0[7U];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */\r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mml.h\r
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\r
+ * @version V5.0.7\r
+ * @date 06. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MML_H_GENERIC\r
+#define __CORE_ARMV8MML_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MML\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS Armv8MML definitions */\r
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (81U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MML_H_DEPENDANT\r
+#define __CORE_ARMV8MML_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MML_REV\r
+ #define __ARMv8MML_REV 0x0000U\r
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MML */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[809U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */\r
+ uint32_t RESERVED4[4U];\r
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI Periodic Synchronization Control Register Definitions */\r
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */\r
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */\r
+\r
+/* TPI Software Lock Status Register Definitions */\r
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */\r
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */\r
+\r
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */\r
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */\r
+\r
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */\r
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */\r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V5.0.5\r
+ * @date 28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000U\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ Address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0plus.h\r
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r
+ * @version V5.0.6\r
+ * @date 28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM0PLUS_H_GENERIC\r
+#define __CORE_CM0PLUS_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex-M0+\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM0+ definitions */\r
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0PLUS_H_DEPENDANT\r
+#define __CORE_CM0PLUS_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0PLUS_REV\r
+ #define __CM0PLUS_REV 0x0000U\r
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex-M0+ */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M0+ header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm1.h\r
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File\r
+ * @version V1.0.0\r
+ * @date 23. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM1_H_GENERIC\r
+#define __CORE_CM1_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M1\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM1 definitions */\r
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (1U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM1_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM1_H_DEPENDANT\r
+#define __CORE_CM1_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM1_REV\r
+ #define __CM1_REV 0x0100U\r
+ #warning "__CM1_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M1 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\r
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\r
+\r
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\r
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the Cortex-M1 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ Address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM1_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm23.h\r
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File\r
+ * @version V5.0.7\r
+ * @date 22. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM23_H_GENERIC\r
+#define __CORE_CM23_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M23\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS definitions */\r
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (23U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM23_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM23_H_DEPENDANT\r
+#define __CORE_CM23_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM23_REV\r
+ #define __CM23_REV 0x0000U\r
+ #warning "__CM23_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ETM_PRESENT\r
+ #define __ETM_PRESENT 0U\r
+ #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MTB_PRESENT\r
+ #define __MTB_PRESENT 0U\r
+ #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M23 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ uint32_t RESERVED0[6U];\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */\r
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */\r
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */\r
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */\r
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */\r
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */\r
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 0 Definitions */\r
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */\r
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */\r
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */\r
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */\r
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ uint32_t RESERVED0[7U];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ \r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else \r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+ \r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+#define __NVIC_SetPriorityGrouping(X) (void)(X)\r
+#define __NVIC_GetPriorityGrouping() (0U)\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM23_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V5.0.8\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M3\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (3U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200U\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1U];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm33.h\r
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File\r
+ * @version V5.0.9\r
+ * @date 06. July 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM33_H_GENERIC\r
+#define __CORE_CM33_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M33\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM33 definitions */\r
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (33U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined (__TARGET_FPU_VFP)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined (__ARM_PCS_VFP)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined (__ARMVFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined (__TI_VFP_SUPPORT__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined (__FPU_VFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM33_H_DEPENDANT\r
+#define __CORE_CM33_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM33_REV\r
+ #define __CM33_REV 0x0000U\r
+ #warning "__CM33_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M33 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\r
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */\r
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */\r
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */\r
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\r
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\r
+\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\r
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 2 Register Definitions */\r
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */\r
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */\r
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */\r
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */\r
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */\r
+\r
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\r
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\r
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\r
+\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\r
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\r
+\r
+/* TPI Integration Test ATB Control Register 0 Definitions */\r
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */\r
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */\r
+\r
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */\r
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */\r
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */\r
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */\r
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Special LR values for Secure/Non-Secure call handling and exception handling */\r
+\r
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ \r
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */\r
+\r
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\r
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */\r
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */\r
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */\r
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */\r
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */\r
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */\r
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\r
+\r
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */\r
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */\r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */\r
+#else \r
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V5.0.8\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (4U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000U\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V5.0.8\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (7U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000U\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0U\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0U\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DTCM_PRESENT\r
+ #define __DTCM_PRESENT 0U\r
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */\r
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv7.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = SCB->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+\r
+\r
+/**\r
+ \brief Enable I-Cache\r
+ \details Turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable I-Cache\r
+ \details Turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate I-Cache\r
+ \details Invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
+{\r
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable D-Cache\r
+ \details Turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+ __DSB();\r
+\r
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable D-Cache\r
+ \details Turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate D-Cache\r
+ \details Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean D-Cache\r
+ \details Cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean & Invalidate D-Cache\r
+ \details Cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways-- != 0U);\r
+ } while(sets-- != 0U);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Invalidate by address\r
+ \details Invalidates D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t)addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean by address\r
+ \details Cleans D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean and Invalidate by address\r
+ \details Cleans and invalidates D_Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCIMVAC = op_addr;\r
+ op_addr += (uint32_t)linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc000.h\r
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File\r
+ * @version V5.0.5\r
+ * @date 28. May 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC000_H_GENERIC\r
+#define __CORE_SC000_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup SC000\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS SC000 definitions */\r
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\r
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (000U) /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC000_H_DEPENDANT\r
+#define __CORE_SC000_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC000_REV\r
+ #define __SC000_REV 0x0000U\r
+ #warning "__SC000_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC000 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31U];\r
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31U];\r
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31U];\r
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31U];\r
+ uint32_t RESERVED4[64U];\r
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ uint32_t RESERVED1[154U];\r
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r
+ Therefore they are not covered by the SC000 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC000_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_sc300.h\r
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File\r
+ * @version V5.0.6\r
+ * @date 04. June 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_SC300_H_GENERIC\r
+#define __CORE_SC300_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup SC3000\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS SC300 definitions */\r
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\r
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_SC (300U) /*!< Cortex secure core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_SC300_H_DEPENDANT\r
+#define __CORE_SC300_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __SC300_REV\r
+ #define __SC300_REV 0x0000U\r
+ #warning "__SC300_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group SC300 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */\r
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */\r
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit */\r
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */\r
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */\r
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED1[129U];\r
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ uint32_t RESERVED1[1U];\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */\r
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */\r
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */\r
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */\r
+\r
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */\r
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* The following EXC_RETURN values are saved the LR on exception entry */\r
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */\r
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_SC300_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv7.h\r
+ * @brief CMSIS MPU API for Armv7-M MPU\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+ \r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+ \r
+#ifndef ARM_MPU_ARMV7_H\r
+#define ARM_MPU_ARMV7_H\r
+\r
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\r
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\r
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\r
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\r
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\r
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\r
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\r
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\r
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\r
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\r
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\r
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\r
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\r
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\r
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\r
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\r
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\r
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\r
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\r
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\r
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\r
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\r
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\r
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\r
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\r
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\r
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\r
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\r
+\r
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\r
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\r
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only\r
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\r
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only\r
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access\r
+\r
+/** MPU Region Base Address Register Value\r
+*\r
+* \param Region The region to be configured, number 0 to 15.\r
+* \param BaseAddress The base address for the region.\r
+*/\r
+#define ARM_MPU_RBAR(Region, BaseAddress) \\r
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \\r
+ ((Region) & MPU_RBAR_REGION_Msk) | \\r
+ (MPU_RBAR_VALID_Msk))\r
+\r
+/**\r
+* MPU Memory Access Attributes\r
+* \r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+*/ \r
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \\r
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \\r
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \\r
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \\r
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\r
+\r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/\r
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \\r
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \\r
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \\r
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))\r
+ \r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/ \r
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\r
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\r
+\r
+/**\r
+* MPU Memory Access Attribute for strongly ordered memory.\r
+* - TEX: 000b\r
+* - Shareable\r
+* - Non-cacheable\r
+* - Non-bufferable\r
+*/ \r
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\r
+\r
+/**\r
+* MPU Memory Access Attribute for device memory.\r
+* - TEX: 000b (if non-shareable) or 010b (if shareable)\r
+* - Shareable or non-shareable\r
+* - Non-cacheable\r
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)\r
+*\r
+* \param IsShareable Configures the device memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\r
+\r
+/**\r
+* MPU Memory Access Attribute for normal memory.\r
+* - TEX: 1BBb (reflecting outer cacheability rules)\r
+* - Shareable or non-shareable\r
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)\r
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)\r
+*\r
+* \param OuterCp Configures the outer cache policy.\r
+* \param InnerCp Configures the inner cache policy.\r
+* \param IsShareable Configures the memory as shareable or non-shareable.\r
+*/ \r
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\r
+\r
+/**\r
+* MPU Memory Access Attribute non-cacheable policy.\r
+*/\r
+#define ARM_MPU_CACHEP_NOCACHE 0U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, write and read allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_WRA 1U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-through, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WT_NWA 2U\r
+\r
+/**\r
+* MPU Memory Access Attribute write-back, no write allocate policy.\r
+*/\r
+#define ARM_MPU_CACHEP_WB_NWA 3U\r
+\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; //!< The region base address register value (RBAR)\r
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RASR = 0U;\r
+}\r
+\r
+/** Configure an MPU region.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ while (cnt > MPU_TYPE_RALIASES) {\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\r
+ table += MPU_TYPE_RALIASES;\r
+ cnt -= MPU_TYPE_RALIASES;\r
+ }\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\r
+}\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv8.h\r
+ * @brief CMSIS MPU API for Armv8-M MPU\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef ARM_MPU_ARMV8_H\r
+#define ARM_MPU_ARMV8_H\r
+\r
+/** \brief Attribute for device memory (outer only) */\r
+#define ARM_MPU_ATTR_DEVICE ( 0U )\r
+\r
+/** \brief Attribute for non-cacheable, normal memory */\r
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )\r
+\r
+/** \brief Attribute for normal memory (outer and inner)\r
+* \param NT Non-Transient: Set to 1 for non-transient data.\r
+* \param WB Write-Back: Set to 1 to use write-back update policy.\r
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.\r
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.\r
+*/\r
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\r
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)\r
+\r
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)\r
+\r
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)\r
+\r
+/** \brief Memory Attribute\r
+* \param O Outer memory attributes\r
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\r
+*/\r
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\r
+\r
+/** \brief Normal memory non-shareable */\r
+#define ARM_MPU_SH_NON (0U)\r
+\r
+/** \brief Normal memory outer shareable */\r
+#define ARM_MPU_SH_OUTER (2U)\r
+\r
+/** \brief Normal memory inner shareable */\r
+#define ARM_MPU_SH_INNER (3U)\r
+\r
+/** \brief Memory access permissions\r
+* \param RO Read-Only: Set to 1 for read-only memory.\r
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.\r
+*/\r
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\r
+\r
+/** \brief Region Base Address Register value\r
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\r
+* \param SH Defines the Shareability domain for this memory region.\r
+* \param RO Read-Only: Set to 1 for a read-only memory region.\r
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.\r
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r
+*/\r
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\r
+ ((BASE & MPU_RBAR_BASE_Msk) | \\r
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\r
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\r
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r
+\r
+/** \brief Region Limit Address Register value\r
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
+* \param IDX The attribute index to be associated with this memory region.\r
+*/\r
+#define ARM_MPU_RLAR(LIMIT, IDX) \\r
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
+ (MPU_RLAR_EN_Msk))\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; /*!< Region Base Address Register value */\r
+ uint32_t RLAR; /*!< Region Limit Address Register value */\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Enable the Non-secure MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the Non-secure MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+#endif\r
+\r
+/** Set the memory attribute encoding to the given MPU.\r
+* \param mpu Pointer to the MPU to be configured.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\r
+{\r
+ const uint8_t reg = idx / 4U;\r
+ const uint32_t pos = ((idx % 4U) * 8U);\r
+ const uint32_t mask = 0xFFU << pos;\r
+ \r
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\r
+ return; // invalid index\r
+ }\r
+ \r
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\r
+}\r
+\r
+/** Set the memory attribute encoding.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Set the memory attribute encoding to the Non-secure MPU.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\r
+}\r
+#endif\r
+\r
+/** Clear and disable the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RLAR = 0U;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ ARM_MPU_ClrRegionEx(MPU, rnr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Clear and disable the given Non-secure MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\r
+{ \r
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);\r
+}\r
+#endif\r
+\r
+/** Configure the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RBAR = rbar;\r
+ mpu->RLAR = rlar;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Configure the given Non-secure MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); \r
+}\r
+#endif\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table to the given MPU.\r
+* \param mpu Pointer to the MPU registers to be used.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ if (cnt == 1U) {\r
+ mpu->RNR = rnr;\r
+ orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
+ } else {\r
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);\r
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r
+ \r
+ mpu->RNR = rnrBase;\r
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
+ table += c;\r
+ cnt -= c;\r
+ rnrOffset = 0U;\r
+ rnrBase += MPU_TYPE_RALIASES;\r
+ mpu->RNR = rnrBase;\r
+ }\r
+ \r
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Load the given number of MPU regions from a table to the Non-secure MPU.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file tz_context.h\r
+ * @brief Context Management for Armv8-M TrustZone\r
+ * @version V1.0.1\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef TZ_CONTEXT_H\r
+#define TZ_CONTEXT_H\r
+ \r
+#include <stdint.h>\r
+ \r
+#ifndef TZ_MODULEID_T\r
+#define TZ_MODULEID_T\r
+/// \details Data type that identifies secure software modules called by a process.\r
+typedef uint32_t TZ_ModuleId_t;\r
+#endif\r
+ \r
+/// \details TZ Memory ID identifies an allocated memory slot.\r
+typedef uint32_t TZ_MemoryId_t;\r
+ \r
+/// Initialize secure context memory system\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_InitContextSystem_S (void);\r
+ \r
+/// Allocate context memory for calling secure software modules in TrustZone\r
+/// \param[in] module identifies software modules called from non-secure mode\r
+/// \return value != 0 id TrustZone memory slot identifier\r
+/// \return value 0 no memory available or internal error\r
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\r
+ \r
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\r
+ \r
+/// Load secure context (called on RTOS thread context switch)\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\r
+ \r
+/// Store secure context (called on RTOS thread context switch)\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\r
+ \r
+#endif // TZ_CONTEXT_H\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_hal_legacy.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains aliases definition for the STM32Cube HAL constants\r
+ * macros and functions maintained for legacy purpose.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2018 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32_HAL_LEGACY\r
+#define STM32_HAL_LEGACY\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR\r
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR\r
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF\r
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR\r
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B\r
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B\r
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B\r
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B\r
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN\r
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED\r
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV\r
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV\r
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV\r
+#define REGULAR_GROUP ADC_REGULAR_GROUP\r
+#define INJECTED_GROUP ADC_INJECTED_GROUP\r
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP\r
+#define AWD_EVENT ADC_AWD_EVENT\r
+#define AWD1_EVENT ADC_AWD1_EVENT\r
+#define AWD2_EVENT ADC_AWD2_EVENT\r
+#define AWD3_EVENT ADC_AWD3_EVENT\r
+#define OVR_EVENT ADC_OVR_EVENT\r
+#define JQOVF_EVENT ADC_JQOVF_EVENT\r
+#define ALL_CHANNELS ADC_ALL_CHANNELS\r
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS\r
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS\r
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR\r
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6\r
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8\r
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO\r
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2\r
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO\r
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4\r
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO\r
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11\r
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1\r
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE\r
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING\r
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING\r
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5\r
+\r
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY\r
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY\r
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC\r
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC\r
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL\r
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL\r
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1\r
+\r
+#if defined(STM32H7)\r
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT\r
+#endif /* STM32H7 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE\r
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE\r
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1\r
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2\r
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3\r
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4\r
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5\r
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6\r
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7\r
+#if defined(STM32L0)\r
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */\r
+#endif\r
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR\r
+#if defined(STM32F373xC) || defined(STM32F378xx)\r
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1\r
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR\r
+#endif /* STM32F373xC || STM32F378xx */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r
+\r
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1\r
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2\r
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3\r
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4\r
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5\r
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6\r
+\r
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT\r
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT\r
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT\r
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT\r
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1\r
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1\r
+#if defined(STM32L0)\r
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */\r
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */\r
+/* to the second dedicated IO (only for COMP2). */\r
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2\r
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2\r
+#else\r
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2\r
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3\r
+#endif\r
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4\r
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5\r
+\r
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW\r
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH\r
+\r
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */\r
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */\r
+#if defined(COMP_CSR_LOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_LOCK\r
+#elif defined(COMP_CSR_COMP1LOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK\r
+#elif defined(COMP_CSR_COMPxLOCK)\r
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1\r
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1\r
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2\r
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2\r
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2\r
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE\r
+#endif\r
+\r
+#if defined(STM32L0)\r
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER\r
+#else\r
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED\r
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED\r
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER\r
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER\r
+#endif\r
+\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE\r
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2\r
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1\r
+#define DAC_WAVE_NONE 0x00000000U\r
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0\r
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1\r
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE\r
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE\r
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2\r
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4\r
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5\r
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4\r
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2\r
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32\r
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6\r
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7\r
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67\r
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67\r
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76\r
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6\r
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7\r
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6\r
+\r
+#define IS_HAL_REMAPDMA IS_DMA_REMAP\r
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE\r
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE\r
+\r
+#if defined(STM32L4)\r
+\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE\r
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT\r
+\r
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING\r
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
+\r
+#endif /* STM32L4 */\r
+\r
+#if defined(STM32H7)\r
+\r
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1\r
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2\r
+\r
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX\r
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX\r
+\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT\r
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO\r
+\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP\r
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0\r
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2\r
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT\r
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT\r
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT\r
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT\r
+\r
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING\r
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING\r
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING\r
+\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT\r
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT\r
+\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD\r
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD\r
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS\r
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES\r
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE\r
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE\r
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE\r
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE\r
+#define OBEX_PCROP OPTIONBYTE_PCROP\r
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG\r
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE\r
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE\r
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE\r
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD\r
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD\r
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE\r
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD\r
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD\r
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE\r
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD\r
+#define PAGESIZE FLASH_PAGE_SIZE\r
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE\r
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD\r
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD\r
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1\r
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2\r
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3\r
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4\r
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST\r
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST\r
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA\r
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB\r
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA\r
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB\r
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE\r
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN\r
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE\r
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN\r
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE\r
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD\r
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP\r
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV\r
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR\r
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG\r
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA\r
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE\r
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS\r
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS\r
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST\r
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR\r
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO\r
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION\r
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS\r
+#define OB_WDG_SW OB_IWDG_SW\r
+#define OB_WDG_HW OB_IWDG_HW\r
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET\r
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET\r
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET\r
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET\r
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR\r
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0\r
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1\r
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2\r
+#if defined(STM32G0)\r
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE\r
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH\r
+#else\r
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE\r
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE\r
+#endif\r
+#if defined(STM32H7)\r
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1\r
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1\r
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1\r
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2\r
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2\r
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE\r
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE\r
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET\r
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2\r
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r
+ * @{\r
+ */\r
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)\r
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16\r
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)\r
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8\r
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef\r
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define GET_GPIO_SOURCE GPIO_GET_INDEX\r
+#define GET_GPIO_INDEX GPIO_GET_INDEX\r
+\r
+#if defined(STM32F4)\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO\r
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#if defined(STM32L4)\r
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1\r
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1\r
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1\r
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1\r
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2\r
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2\r
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2\r
+#endif\r
+\r
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1\r
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1\r
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1\r
+\r
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)\r
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW\r
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH\r
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH\r
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/\r
+\r
+#if defined(STM32L1)\r
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW\r
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM\r
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH\r
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH\r
+#endif /* STM32L1 */\r
+\r
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW\r
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH\r
+#endif /* STM32F0 || STM32F3 || STM32F1 */\r
+\r
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r
+\r
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER\r
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER\r
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD\r
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD\r
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE\r
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE\r
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE\r
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE\r
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE\r
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE\r
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE\r
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE\r
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE\r
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX\r
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE\r
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD\r
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE\r
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE\r
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r
+\r
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING\r
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING\r
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING\r
+\r
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
+\r
+/* The following 3 definition have also been present in a temporary version of lptim.h */\r
+/* They need to be renamed also to the right name, just in case */\r
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b\r
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b\r
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b\r
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b\r
+\r
+#define NAND_AddressTypedef NAND_AddressTypeDef\r
+\r
+#define __ARRAY_ADDRESS ARRAY_ADDRESS\r
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE\r
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE\r
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE\r
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef\r
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS\r
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING\r
+#define NOR_ERROR HAL_NOR_STATUS_ERROR\r
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT\r
+\r
+#define __NOR_WRITE NOR_WRITE\r
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0\r
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1\r
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2\r
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3\r
+\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2\r
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3\r
+\r
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0\r
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0\r
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1\r
+\r
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO\r
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0\r
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS\r
+\r
+#if defined(STM32H7)\r
+ #define I2S_IT_TXE I2S_IT_TXP\r
+ #define I2S_IT_RXNE I2S_IT_RXP\r
+\r
+ #define I2S_FLAG_TXE I2S_FLAG_TXP\r
+ #define I2S_FLAG_RXNE I2S_FLAG_RXP\r
+ #define I2S_FLAG_FRE I2S_FLAG_TIFRE\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+ #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/* Compact Flash-ATA registers description */\r
+#define CF_DATA ATA_DATA\r
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT\r
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER\r
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW\r
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH\r
+#define CF_CARD_HEAD ATA_CARD_HEAD\r
+#define CF_STATUS_CMD ATA_STATUS_CMD\r
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE\r
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA\r
+\r
+/* Compact Flash-ATA commands */\r
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD\r
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD\r
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD\r
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD\r
+\r
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef\r
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS\r
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING\r
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR\r
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define FORMAT_BIN RTC_FORMAT_BIN\r
+#define FORMAT_BCD RTC_FORMAT_BCD\r
+\r
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE\r
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+\r
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE\r
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE\r
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE\r
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT\r
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT\r
+\r
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT\r
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1\r
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2\r
+\r
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE\r
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1\r
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1\r
+\r
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT\r
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1\r
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE\r
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE\r
+\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE\r
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE\r
+\r
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE\r
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE\r
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE\r
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE\r
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE\r
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE\r
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE\r
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE\r
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE\r
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE\r
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE\r
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE\r
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE\r
+\r
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE\r
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE\r
+\r
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE\r
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE\r
+\r
+#if defined(STM32H7)\r
+\r
+ #define SPI_FLAG_TXE SPI_FLAG_TXP\r
+ #define SPI_FLAG_RXNE SPI_FLAG_RXP\r
+\r
+ #define SPI_IT_TXE SPI_IT_TXP\r
+ #define SPI_IT_RXNE SPI_IT_RXP\r
+\r
+ #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET\r
+ #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET\r
+ #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET\r
+ #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET\r
+\r
+#endif /* STM32H7 */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK\r
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK\r
+\r
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1\r
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2\r
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR\r
+#define TIM_DMABase_DIER TIM_DMABASE_DIER\r
+#define TIM_DMABase_SR TIM_DMABASE_SR\r
+#define TIM_DMABase_EGR TIM_DMABASE_EGR\r
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1\r
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2\r
+#define TIM_DMABase_CCER TIM_DMABASE_CCER\r
+#define TIM_DMABase_CNT TIM_DMABASE_CNT\r
+#define TIM_DMABase_PSC TIM_DMABASE_PSC\r
+#define TIM_DMABase_ARR TIM_DMABASE_ARR\r
+#define TIM_DMABase_RCR TIM_DMABASE_RCR\r
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1\r
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2\r
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3\r
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4\r
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR\r
+#define TIM_DMABase_DCR TIM_DMABASE_DCR\r
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR\r
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1\r
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3\r
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5\r
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6\r
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2\r
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3\r
+#define TIM_DMABase_OR TIM_DMABASE_OR\r
+\r
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE\r
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1\r
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2\r
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3\r
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4\r
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM\r
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER\r
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK\r
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2\r
+\r
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER\r
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS\r
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS\r
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS\r
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS\r
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS\r
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS\r
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS\r
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS\r
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS\r
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS\r
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS\r
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS\r
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS\r
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS\r
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS\r
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS\r
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS\r
+\r
+#if defined(STM32L0)\r
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO\r
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO\r
+#endif\r
+\r
+#if defined(STM32F3)\r
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING\r
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE\r
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE\r
+\r
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r
+\r
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16\r
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16\r
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16\r
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16\r
+\r
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8\r
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8\r
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8\r
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8\r
+\r
+#define __DIV_LPUART UART_DIV_LPUART\r
+\r
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE\r
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE\r
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE\r
+\r
+#define USARTNACK_ENABLED USART_NACK_ENABLE\r
+#define USARTNACK_DISABLED USART_NACK_DISABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CFR_BASE WWDG_CFR_BASE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0\r
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE\r
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)\r
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)\r
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define VLAN_TAG ETH_VLAN_TAG\r
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD\r
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD\r
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD\r
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK\r
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK\r
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK\r
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK\r
+\r
+#define ETH_MMCCR 0x00000100U\r
+#define ETH_MMCRIR 0x00000104U\r
+#define ETH_MMCTIR 0x00000108U\r
+#define ETH_MMCRIMR 0x0000010CU\r
+#define ETH_MMCTIMR 0x00000110U\r
+#define ETH_MMCTGFSCCR 0x0000014CU\r
+#define ETH_MMCTGFMSCCR 0x00000150U\r
+#define ETH_MMCTGFCR 0x00000168U\r
+#define ETH_MMCRFCECR 0x00000194U\r
+#define ETH_MMCRFAECR 0x00000198U\r
+#define ETH_MMCRGUFCR 0x000001C4U\r
+\r
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */\r
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */\r
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */\r
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */\r
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */\r
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */\r
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */\r
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */\r
+#if defined(STM32F1)\r
+#else\r
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */\r
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */\r
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */\r
+#endif\r
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */\r
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */\r
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */\r
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */\r
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */\r
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR\r
+#define DCMI_IT_OVF DCMI_IT_OVR\r
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI\r
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI\r
+\r
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop\r
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop\r
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \\r
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \\r
+ || defined(STM32H7)\r
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888\r
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888\r
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565\r
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555\r
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444\r
+\r
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888\r
+#define CM_RGB888 DMA2D_INPUT_RGB888\r
+#define CM_RGB565 DMA2D_INPUT_RGB565\r
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555\r
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444\r
+#define CM_L8 DMA2D_INPUT_L8\r
+#define CM_AL44 DMA2D_INPUT_AL44\r
+#define CM_AL88 DMA2D_INPUT_AL88\r
+#define CM_L4 DMA2D_INPUT_L4\r
+#define CM_A8 DMA2D_INPUT_A8\r
+#define CM_A4 DMA2D_INPUT_A4\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */\r
+\r
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef\r
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef\r
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish\r
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish\r
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish\r
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish\r
+\r
+/*HASH Algorithm Selection*/\r
+\r
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1\r
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224\r
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256\r
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5\r
+\r
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH\r
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC\r
+\r
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY\r
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect\r
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r
+#if defined(STM32L0)\r
+#else\r
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r
+#endif\r
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram\r
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown\r
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown\r
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock\r
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock\r
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase\r
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter\r
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter\r
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter\r
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter\r
+\r
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r
+\r
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)\r
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT\r
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT\r
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT\r
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT\r
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA\r
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA\r
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA\r
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA\r
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */\r
+\r
+#if defined(STM32F4)\r
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT\r
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT\r
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT\r
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT\r
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA\r
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA\r
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA\r
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA\r
+#endif /* STM32F4 */\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg\r
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown\r
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor\r
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg\r
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown\r
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor\r
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler\r
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD\r
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler\r
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback\r
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive\r
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive\r
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC\r
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC\r
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM\r
+\r
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL\r
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING\r
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING\r
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING\r
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING\r
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING\r
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING\r
+\r
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB\r
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB\r
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER\r
+#define CR_PMODE_BB CR_VOS_BB\r
+\r
+#define DBP_BitNumber DBP_BIT_NUMBER\r
+#define PVDE_BitNumber PVDE_BIT_NUMBER\r
+#define PMODE_BitNumber PMODE_BIT_NUMBER\r
+#define EWUP_BitNumber EWUP_BIT_NUMBER\r
+#define FPDS_BitNumber FPDS_BIT_NUMBER\r
+#define ODEN_BitNumber ODEN_BIT_NUMBER\r
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER\r
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER\r
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER\r
+#define BRE_BitNumber BRE_BIT_NUMBER\r
+\r
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT\r
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback\r
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt\r
+#define HAL_TIM_DMAError TIM_DMAError\r
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt\r
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt\r
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)\r
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro\r
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT\r
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback\r
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent\r
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT\r
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA\r
+#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r
+#define HAL_LTDC_Relaod HAL_LTDC_Reload\r
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig\r
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define AES_IT_CC CRYP_IT_CC\r
+#define AES_IT_ERR CRYP_IT_ERR\r
+#define AES_FLAG_CCF CRYP_FLAG_CCF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE\r
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH\r
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM\r
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC\r
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM\r
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC\r
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK\r
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG\r
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG\r
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE\r
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE\r
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE\r
+\r
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY\r
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48\r
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS\r
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER\r
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __ADC_ENABLE __HAL_ADC_ENABLE\r
+#define __ADC_DISABLE __HAL_ADC_DISABLE\r
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS\r
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS\r
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __ADC_IS_ENABLED ADC_IS_ENABLE\r
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR\r
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED\r
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING\r
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE\r
+\r
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION\r
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK\r
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT\r
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR\r
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION\r
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE\r
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT\r
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS\r
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN\r
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ\r
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET\r
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET\r
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL\r
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL\r
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET\r
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET\r
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD\r
+\r
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER\r
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI\r
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE\r
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER\r
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE\r
+\r
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT\r
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT\r
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL\r
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM\r
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET\r
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE\r
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE\r
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER\r
+\r
+#define __HAL_ADC_SQR1 ADC_SQR1\r
+#define __HAL_ADC_SMPR1 ADC_SMPR1\r
+#define __HAL_ADC_SMPR2 ADC_SMPR2\r
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK\r
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK\r
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK\r
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS\r
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS\r
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV\r
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection\r
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq\r
+#define __HAL_ADC_JSQR ADC_JSQR\r
+\r
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL\r
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS\r
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF\r
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT\r
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS\r
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN\r
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR\r
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT\r
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT\r
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT\r
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r
+\r
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r
+\r
+\r
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r
+#if defined(STM32H7)\r
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1\r
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1\r
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1\r
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1\r
+#else\r
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r
+#endif /* STM32H7 */\r
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined(STM32F3)\r
+#define COMP_START __HAL_COMP_ENABLE\r
+#define COMP_STOP __HAL_COMP_DISABLE\r
+#define COMP_LOCK __HAL_COMP_LOCK\r
+\r
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F302xE) || defined(STM32F302xC)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\r
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\r
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r
+# endif\r
+# if defined(STM32F373xC) ||defined(STM32F378xx)\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+# endif\r
+#else\r
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\r
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())\r
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\r
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r
+#endif\r
+\r
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/* Note: On these STM32 families, the only argument of this macro */\r
+/* is COMP_FLAG_LOCK. */\r
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */\r
+/* argument. */\r
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined(STM32L0) || defined(STM32L4)\r
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\r
+ ((WAVE) == DAC_WAVE_NOISE)|| \\r
+ ((WAVE) == DAC_WAVE_TRIANGLE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_WRPAREA IS_OB_WRPAREA\r
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r
+#define IS_TYPEERASE IS_FLASH_TYPEERASE\r
+#define IS_NBSECTORS IS_FLASH_NBSECTORS\r
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2\r
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START\r
+#if defined(STM32F1)\r
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE\r
+#else\r
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE\r
+#endif /* STM32F1 */\r
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME\r
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD\r
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST\r
+#define __HAL_I2C_SPEED I2C_SPEED\r
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE\r
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ\r
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS\r
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE\r
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ\r
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB\r
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB\r
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE\r
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT\r
+\r
+#if defined(STM32H7)\r
+ #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE\r
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE\r
+\r
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE\r
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION\r
+\r
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS\r
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT\r
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT\r
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD\r
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX\r
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX\r
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX\r
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX\r
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L\r
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H\r
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM\r
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES\r
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX\r
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT\r
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION\r
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE\r
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine\r
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig\r
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention\r
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention\r
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2\r
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2\r
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB\r
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB\r
+\r
+#if defined (STM32F4)\r
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()\r
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()\r
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT\r
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT\r
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG\r
+#endif /* STM32F4 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI\r
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI\r
+\r
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r
+\r
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE\r
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE\r
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET\r
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET\r
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE\r
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE\r
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET\r
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET\r
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE\r
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE\r
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE\r
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE\r
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE\r
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE\r
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET\r
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET\r
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE\r
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE\r
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET\r
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET\r
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE\r
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE\r
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET\r
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET\r
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE\r
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE\r
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET\r
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET\r
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r
+\r
+#if defined(STM32WB)\r
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE\r
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET\r
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED\r
+#define QSPI_IRQHandler QUADSPI_IRQHandler\r
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */\r
+\r
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE\r
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE\r
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET\r
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE\r
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE\r
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE\r
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET\r
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET\r
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE\r
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE\r
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET\r
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET\r
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r
+\r
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE\r
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE\r
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE\r
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE\r
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE\r
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE\r
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET\r
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET\r
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE\r
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE\r
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE\r
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET\r
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET\r
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE\r
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE\r
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE\r
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET\r
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET\r
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE\r
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE\r
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE\r
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET\r
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET\r
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE\r
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE\r
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE\r
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE\r
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE\r
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE\r
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE\r
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE\r
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE\r
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE\r
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE\r
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE\r
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET\r
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET\r
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE\r
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE\r
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE\r
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET\r
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET\r
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE\r
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE\r
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE\r
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET\r
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET\r
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE\r
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE\r
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE\r
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET\r
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET\r
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE\r
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE\r
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE\r
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET\r
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE\r
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE\r
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE\r
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE\r
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE\r
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET\r
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET\r
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE\r
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE\r
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE\r
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET\r
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET\r
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE\r
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE\r
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE\r
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET\r
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET\r
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE\r
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET\r
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED\r
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE\r
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE\r
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE\r
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE\r
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET\r
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET\r
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE\r
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE\r
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE\r
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET\r
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET\r
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r
+\r
+/* alias define maintained for legacy */\r
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET\r
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r
+\r
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE\r
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE\r
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE\r
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE\r
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE\r
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE\r
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE\r
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE\r
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE\r
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE\r
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE\r
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE\r
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE\r
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE\r
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE\r
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE\r
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE\r
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE\r
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE\r
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE\r
+\r
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET\r
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET\r
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET\r
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET\r
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET\r
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET\r
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET\r
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET\r
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET\r
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET\r
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET\r
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET\r
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET\r
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET\r
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET\r
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET\r
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET\r
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET\r
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET\r
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET\r
+\r
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED\r
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED\r
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED\r
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED\r
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED\r
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED\r
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED\r
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED\r
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED\r
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED\r
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED\r
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED\r
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED\r
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED\r
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED\r
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED\r
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED\r
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED\r
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED\r
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED\r
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED\r
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED\r
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED\r
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED\r
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED\r
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED\r
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED\r
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED\r
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED\r
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED\r
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED\r
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED\r
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED\r
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED\r
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED\r
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED\r
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED\r
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED\r
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED\r
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED\r
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED\r
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED\r
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED\r
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED\r
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED\r
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED\r
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED\r
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED\r
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED\r
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED\r
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED\r
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED\r
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED\r
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED\r
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED\r
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED\r
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED\r
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED\r
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED\r
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED\r
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED\r
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED\r
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED\r
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED\r
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED\r
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED\r
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED\r
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED\r
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED\r
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED\r
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED\r
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED\r
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED\r
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED\r
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED\r
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED\r
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED\r
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED\r
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED\r
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED\r
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED\r
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED\r
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED\r
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED\r
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED\r
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED\r
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED\r
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED\r
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED\r
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED\r
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED\r
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED\r
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED\r
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED\r
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED\r
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED\r
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED\r
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED\r
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED\r
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED\r
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED\r
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED\r
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED\r
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED\r
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED\r
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED\r
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED\r
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED\r
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED\r
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED\r
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED\r
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED\r
+\r
+#if defined(STM32F4)\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED\r
+#define Sdmmc1ClockSelection SdioClockSelection\r
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO\r
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48\r
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK\r
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET\r
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE\r
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE\r
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r
+#define SdioClockSelection Sdmmc1ClockSelection\r
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1\r
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG\r
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE\r
+#endif\r
+\r
+#if defined(STM32F7)\r
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48\r
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()\r
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()\r
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()\r
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()\r
+#endif\r
+\r
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG\r
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG\r
+\r
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE\r
+\r
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE\r
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE\r
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK\r
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK\r
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK\r
+\r
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY\r
+\r
+#define RCC_IT_CSSLSE RCC_IT_LSECSS\r
+#define RCC_IT_CSSHSE RCC_IT_CSS\r
+\r
+#define RCC_PLLMUL_3 RCC_PLL_MUL3\r
+#define RCC_PLLMUL_4 RCC_PLL_MUL4\r
+#define RCC_PLLMUL_6 RCC_PLL_MUL6\r
+#define RCC_PLLMUL_8 RCC_PLL_MUL8\r
+#define RCC_PLLMUL_12 RCC_PLL_MUL12\r
+#define RCC_PLLMUL_16 RCC_PLL_MUL16\r
+#define RCC_PLLMUL_24 RCC_PLL_MUL24\r
+#define RCC_PLLMUL_32 RCC_PLL_MUL32\r
+#define RCC_PLLMUL_48 RCC_PLL_MUL48\r
+\r
+#define RCC_PLLDIV_2 RCC_PLL_DIV2\r
+#define RCC_PLLDIV_3 RCC_PLL_DIV3\r
+#define RCC_PLLDIV_4 RCC_PLL_DIV4\r
+\r
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE\r
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG\r
+#define RCC_MCO_NODIV RCC_MCODIV_1\r
+#define RCC_MCO_DIV1 RCC_MCODIV_1\r
+#define RCC_MCO_DIV2 RCC_MCODIV_2\r
+#define RCC_MCO_DIV4 RCC_MCODIV_4\r
+#define RCC_MCO_DIV8 RCC_MCODIV_8\r
+#define RCC_MCO_DIV16 RCC_MCODIV_16\r
+#define RCC_MCO_DIV32 RCC_MCODIV_32\r
+#define RCC_MCO_DIV64 RCC_MCODIV_64\r
+#define RCC_MCO_DIV128 RCC_MCODIV_128\r
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK\r
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI\r
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE\r
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK\r
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI\r
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14\r
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48\r
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE\r
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK\r
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2\r
+\r
+#if defined(STM32L4)\r
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE\r
+#elif defined(STM32WB) || defined(STM32G0)\r
+#else\r
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK\r
+#endif\r
+\r
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1\r
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI\r
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL\r
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5\r
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2\r
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3\r
+\r
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER\r
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER\r
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER\r
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER\r
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER\r
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER\r
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER\r
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER\r
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER\r
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER\r
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER\r
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER\r
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER\r
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER\r
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER\r
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER\r
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER\r
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER\r
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER\r
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER\r
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER\r
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER\r
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER\r
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER\r
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER\r
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS\r
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS\r
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS\r
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS\r
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE\r
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE\r
+\r
+#define CR_HSION_BB RCC_CR_HSION_BB\r
+#define CR_CSSON_BB RCC_CR_CSSON_BB\r
+#define CR_PLLON_BB RCC_CR_PLLON_BB\r
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB\r
+#define CR_MSION_BB RCC_CR_MSION_BB\r
+#define CSR_LSION_BB RCC_CSR_LSION_BB\r
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB\r
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB\r
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB\r
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB\r
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB\r
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB\r
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB\r
+#define CR_HSEON_BB RCC_CR_HSEON_BB\r
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB\r
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB\r
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB\r
+\r
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r
+\r
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT\r
+\r
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN\r
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF\r
+\r
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48\r
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ\r
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP\r
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ\r
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE\r
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48\r
+\r
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET\r
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r
+#define DfsdmClockSelection Dfsdm1ClockSelection\r
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1\r
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK\r
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG\r
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE\r
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1\r
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1\r
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1\r
+\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2\r
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1\r
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2\r
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2\r
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2\r
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)\r
+#else\r
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG\r
+#endif\r
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT\r
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT\r
+\r
+#if defined (STM32F1)\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r
+\r
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()\r
+\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r
+#else\r
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\r
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \\r
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r
+#endif /* STM32F1 */\r
+\r
+#define IS_ALARM IS_RTC_ALARM\r
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK\r
+#define IS_TAMPER IS_RTC_TAMPER\r
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE\r
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER\r
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT\r
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE\r
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION\r
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE\r
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ\r
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER\r
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK\r
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER\r
+\r
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE\r
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE\r
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS\r
+\r
+#if defined(STM32F4) || defined(STM32F2)\r
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED\r
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY\r
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED\r
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION\r
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND\r
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT\r
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED\r
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE\r
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE\r
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE\r
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL\r
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT\r
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT\r
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG\r
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG\r
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT\r
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT\r
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS\r
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT\r
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND\r
+/* alias CMSIS */\r
+#define SDMMC1_IRQn SDIO_IRQn\r
+#define SDMMC1_IRQHandler SDIO_IRQHandler\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32L4)\r
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED\r
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY\r
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED\r
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION\r
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND\r
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT\r
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED\r
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE\r
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE\r
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE\r
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE\r
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT\r
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT\r
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG\r
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG\r
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT\r
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT\r
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS\r
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT\r
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND\r
+/* alias CMSIS for compatibilities */\r
+#define SDIO_IRQn SDMMC1_IRQn\r
+#define SDIO_IRQHandler SDMMC1_IRQHandler\r
+#endif\r
+\r
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)\r
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef\r
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef\r
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef\r
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef\r
+#endif\r
+\r
+#if defined(STM32H7)\r
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback\r
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback\r
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback\r
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback\r
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback\r
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback\r
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback\r
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback\r
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT\r
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT\r
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE\r
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE\r
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r
+\r
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE\r
+\r
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1\r
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2\r
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START\r
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH\r
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR\r
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE\r
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE\r
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX\r
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX\r
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE\r
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION\r
+\r
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD\r
+\r
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE\r
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT\r
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT\r
+#define __USART_ENABLE __HAL_USART_ENABLE\r
+#define __USART_DISABLE __HAL_USART_DISABLE\r
+\r
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE\r
+\r
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE\r
+\r
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE\r
+\r
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+\r
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r
+\r
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup\r
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup\r
+\r
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo\r
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE\r
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r
+\r
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT\r
+\r
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE\r
+\r
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN\r
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER\r
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER\r
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER\r
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD\r
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD\r
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION\r
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION\r
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER\r
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER\r
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE\r
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE\r
+\r
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r
+\r
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE\r
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE\r
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define __HAL_LTDC_LAYER LTDC_LAYER\r
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE\r
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE\r
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE\r
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE\r
+#define SAI_STREOMODE SAI_STEREOMODE\r
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY\r
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL\r
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL\r
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL\r
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL\r
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL\r
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE\r
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1\r
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined(STM32H7)\r
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow\r
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT\r
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose\r
+ * @{\r
+ */\r
+#if defined (STM32H7) || defined (STM32F3)\r
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT\r
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA\r
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart\r
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT\r
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA\r
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32_HAL_LEGACY */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains all the functions prototypes for the HAL \r
+ * module driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_H\r
+#define __STM32F7xx_HAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_conf.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup HAL\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Constants HAL Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_TICK_FREQ Tick Frequency\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TICK_FREQ_10HZ = 100U,\r
+ HAL_TICK_FREQ_100HZ = 10U,\r
+ HAL_TICK_FREQ_1KHZ = 1U,\r
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ\r
+} HAL_TickFreqTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SYSCFG_BootMode Boot Mode\r
+ * @{\r
+ */\r
+#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U)\r
+#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup HAL_Exported_Macros HAL Exported Macros\r
+ * @{\r
+ */\r
+ \r
+/** @brief Freeze/Unfreeze Peripherals in Debug mode \r
+ */\r
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r
+#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))\r
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r
+#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r
+\r
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r
+#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r
+#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r
+\r
+\r
+/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))\r
+ \r
+\r
+/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000\r
+ */\r
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\\r
+ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\\r
+ }while(0);\r
+/**\r
+ * @brief Return the memory boot mapping as configured by user.\r
+ * @retval The boot mode as configured by user. The returned value can be one\r
+ * of the following values:\r
+ * @arg @ref SYSCFG_MEM_BOOT_ADD0\r
+ * @arg @ref SYSCFG_MEM_BOOT_ADD1\r
+ */\r
+#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @brief SYSCFG Break Cortex-M7 Lockup lock.\r
+ * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)\r
+\r
+/** @brief SYSCFG Break PVD lock.\r
+ * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.\r
+ * @note The selected configuration is locked and can be unlocked only by system reset.\r
+ */\r
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup HAL_Private_Macros HAL Private Macros\r
+ * @{\r
+ */\r
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \\r
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \\r
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup HAL_Exported_Functions\r
+ * @{\r
+ */\r
+/** @addtogroup HAL_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and Configuration functions ******************************/\r
+HAL_StatusTypeDef HAL_Init(void);\r
+HAL_StatusTypeDef HAL_DeInit(void);\r
+void HAL_MspInit(void);\r
+void HAL_MspDeInit(void);\r
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /* Exported variables ---------------------------------------------------------*/\r
+/** @addtogroup HAL_Exported_Variables\r
+ * @{\r
+ */\r
+extern __IO uint32_t uwTick;\r
+extern uint32_t uwTickPrio;\r
+extern HAL_TickFreqTypeDef uwTickFreq;\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup HAL_Exported_Functions_Group2\r
+ * @{\r
+ */ \r
+/* Peripheral Control functions ************************************************/\r
+void HAL_IncTick(void);\r
+void HAL_Delay(uint32_t Delay);\r
+uint32_t HAL_GetTick(void);\r
+uint32_t HAL_GetTickPrio(void);\r
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);\r
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);\r
+void HAL_SuspendTick(void);\r
+void HAL_ResumeTick(void);\r
+uint32_t HAL_GetHalVersion(void);\r
+uint32_t HAL_GetREVID(void);\r
+uint32_t HAL_GetDEVID(void);\r
+uint32_t HAL_GetUIDw0(void);\r
+uint32_t HAL_GetUIDw1(void);\r
+uint32_t HAL_GetUIDw2(void);\r
+void HAL_DBGMCU_EnableDBGSleepMode(void);\r
+void HAL_DBGMCU_DisableDBGSleepMode(void);\r
+void HAL_DBGMCU_EnableDBGStopMode(void);\r
+void HAL_DBGMCU_DisableDBGStopMode(void);\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void);\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void);\r
+void HAL_EnableCompensationCell(void);\r
+void HAL_DisableCompensationCell(void);\r
+void HAL_EnableFMCMemorySwapping(void);\r
+void HAL_DisableFMCMemorySwapping(void);\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+void HAL_EnableMemorySwappingBank(void);\r
+void HAL_DisableMemorySwappingBank(void);\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup HAL_Private_Variables HAL Private Variables\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup HAL_Private_Constants HAL Private Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cortex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of CORTEX HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CORTEX_H\r
+#define __STM32F7xx_HAL_CORTEX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CORTEX\r
+ * @{\r
+ */ \r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r
+ * @brief MPU Region initialization structure \r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint8_t Enable; /*!< Specifies the status of the region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */\r
+ uint8_t Number; /*!< Specifies the number of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */\r
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */\r
+ uint8_t Size; /*!< Specifies the size of the region to protect. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */\r
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. \r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ \r
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.\r
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ \r
+ uint8_t AccessPermission; /*!< Specifies the region access permission type. \r
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */\r
+ uint8_t DisableExec; /*!< Specifies the instruction access status. \r
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */\r
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */\r
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */\r
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. \r
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */\r
+}MPU_Region_InitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r
+ * @{\r
+ */\r
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source \r
+ * @{\r
+ */\r
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)\r
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r
+ * @{\r
+ */\r
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) \r
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)\r
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)\r
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r
+ * @{\r
+ */\r
+#define MPU_REGION_ENABLE ((uint8_t)0x01U)\r
+#define MPU_REGION_DISABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r
+ * @{\r
+ */\r
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)\r
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)\r
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)\r
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r
+ * @{\r
+ */\r
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)\r
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r
+ * @{\r
+ */\r
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)\r
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)\r
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r
+ * @{\r
+ */\r
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)\r
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)\r
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) \r
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) \r
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) \r
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) \r
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)\r
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) \r
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) \r
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) \r
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) \r
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) \r
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)\r
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)\r
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)\r
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) \r
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) \r
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) \r
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) \r
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)\r
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)\r
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)\r
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)\r
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)\r
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)\r
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) \r
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) \r
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)\r
+/** \r
+ * @}\r
+ */\r
+ \r
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \r
+ * @{\r
+ */\r
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) \r
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) \r
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) \r
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) \r
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) \r
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r
+ * @{\r
+ */\r
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) \r
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) \r
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) \r
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) \r
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) \r
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)\r
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)\r
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported Macros -----------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup CORTEX_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup CORTEX_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SystemReset(void);\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CORTEX_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ***********************************************/\r
+#if (__MPU_PRESENT == 1)\r
+void HAL_MPU_Enable(uint32_t MPU_Control);\r
+void HAL_MPU_Disable(void);\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r
+#endif /* __MPU_PRESENT */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void);\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r
+void HAL_SYSTICK_IRQHandler(void);\r
+void HAL_SYSTICK_Callback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/ \r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r
+ * @{\r
+ */\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \\r
+ ((GROUP) == NVIC_PRIORITYGROUP_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)\r
+\r
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)\r
+\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\r
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r
+\r
+#if (__MPU_PRESENT == 1)\r
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\r
+ ((STATE) == MPU_REGION_DISABLE))\r
+\r
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\r
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r
+\r
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r
+\r
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r
+\r
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \\r
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r
+\r
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \\r
+ ((TYPE) == MPU_TEX_LEVEL1) || \\r
+ ((TYPE) == MPU_TEX_LEVEL2))\r
+\r
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\r
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO) || \\r
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))\r
+\r
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER1) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER2) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER3) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER4) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER5) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER6) || \\r
+ ((NUMBER) == MPU_REGION_NUMBER7))\r
+\r
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512B) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \\r
+ ((SIZE) == MPU_REGION_SIZE_4GB))\r
+\r
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)\r
+#endif /* __MPU_PRESENT */\r
+\r
+/** \r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CORTEX_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_def.h\r
+ * @author MCD Application Team\r
+ * @brief This file contains HAL common defines, enumeration, macros and \r
+ * structures definitions. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DEF\r
+#define __STM32F7xx_HAL_DEF\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx.h"\r
+#include "Legacy/stm32_hal_legacy.h"\r
+#include <stddef.h>\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** \r
+ * @brief HAL Status structures definition \r
+ */ \r
+typedef enum \r
+{\r
+ HAL_OK = 0x00U,\r
+ HAL_ERROR = 0x01U,\r
+ HAL_BUSY = 0x02U,\r
+ HAL_TIMEOUT = 0x03U\r
+} HAL_StatusTypeDef;\r
+\r
+/** \r
+ * @brief HAL Lock structures definition \r
+ */\r
+typedef enum \r
+{\r
+ HAL_UNLOCKED = 0x00U,\r
+ HAL_LOCKED = 0x01U \r
+} HAL_LockTypeDef;\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */\r
+\r
+#define HAL_MAX_DELAY 0xFFFFFFFFU\r
+\r
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))\r
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)\r
+\r
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\r
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \\r
+ } while(0)\r
+\r
+/** @brief Reset the Handle's State field.\r
+ * @param __HANDLE__ specifies the Peripheral Handle.\r
+ * @note This macro can be used for the following purpose: \r
+ * - When the Handle is declared as local variable; before passing it as parameter\r
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro \r
+ * to set to 0 the Handle's "State" field.\r
+ * Otherwise, "State" field may have any random value and the first time the function \r
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed\r
+ * (i.e. HAL_PPP_MspInit() will not be executed).\r
+ * - When there is a need to reconfigure the low level hardware: instead of calling\r
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function\r
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.\r
+ * @retval None\r
+ */\r
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\r
+\r
+#if (USE_RTOS == 1U)\r
+ /* Reserved for future use */\r
+ #error "USE_RTOS should be 0 in the current HAL release"\r
+#else\r
+ #define __HAL_LOCK(__HANDLE__) \\r
+ do{ \\r
+ if((__HANDLE__)->Lock == HAL_LOCKED) \\r
+ { \\r
+ return HAL_BUSY; \\r
+ } \\r
+ else \\r
+ { \\r
+ (__HANDLE__)->Lock = HAL_LOCKED; \\r
+ } \\r
+ }while (0U)\r
+\r
+ #define __HAL_UNLOCK(__HANDLE__) \\r
+ do{ \\r
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \\r
+ }while (0U)\r
+#endif /* USE_RTOS */\r
+\r
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
+ #ifndef __weak\r
+ #define __weak __attribute__((weak))\r
+ #endif /* __weak */\r
+ #ifndef __packed\r
+ #define __packed __attribute__((__packed__))\r
+ #endif /* __packed */\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */\r
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END __attribute__ ((aligned (4)))\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN \r
+ #define __ALIGN_BEGIN\r
+ #endif /* __ALIGN_BEGIN */\r
+#else\r
+ #ifndef __ALIGN_END\r
+ #define __ALIGN_END\r
+ #endif /* __ALIGN_END */\r
+ #ifndef __ALIGN_BEGIN \r
+ #if defined (__CC_ARM) /* ARM Compiler */\r
+ #define __ALIGN_BEGIN __align(4)\r
+ #elif defined (__ICCARM__) /* IAR Compiler */\r
+ #define __ALIGN_BEGIN \r
+ #endif /* __CC_ARM */\r
+ #endif /* __ALIGN_BEGIN */\r
+#endif /* __GNUC__ */\r
+\r
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */\r
+#if defined (__GNUC__) /* GNU Compiler */\r
+ #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))\r
+#elif defined (__ICCARM__) /* IAR Compiler */\r
+ #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf\r
+#elif defined (__CC_ARM) /* ARM Compiler */\r
+ #define ALIGN_32BYTES(buf) __align(32) buf\r
+#endif\r
+\r
+/**\r
+ * @brief __RAM_FUNC definition\r
+ */ \r
+#if defined ( __CC_ARM )\r
+/* ARM Compiler\r
+ ------------\r
+ RAM functions are defined using the toolchain options. \r
+ Functions that are executed in RAM should reside in a separate source module.\r
+ Using the 'Options for File' dialog you can simply change the 'Code / Const' \r
+ area of a module to a memory space in physical RAM.\r
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r
+ dialog. \r
+*/\r
+#define __RAM_FUNC \r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+ RAM functions are defined using a specific toolchain keyword "__ramfunc". \r
+*/\r
+#define __RAM_FUNC __ramfunc\r
+\r
+#elif defined ( __GNUC__ )\r
+/* GNU Compiler\r
+ ------------\r
+ RAM functions are defined using a specific toolchain attribute \r
+ "__attribute__((section(".RamFunc")))".\r
+*/\r
+#define __RAM_FUNC __attribute__((section(".RamFunc")))\r
+\r
+#endif\r
+\r
+/** \r
+ * @brief __NOINLINE definition\r
+ */ \r
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )\r
+/* ARM & GNUCompiler \r
+ ---------------- \r
+*/\r
+#define __NOINLINE __attribute__ ( (noinline) )\r
+\r
+#elif defined ( __ICCARM__ )\r
+/* ICCARM Compiler\r
+ ---------------\r
+*/\r
+#define __NOINLINE _Pragma("optimize = no_inline")\r
+\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ___STM32F7xx_HAL_DEF */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of DMA HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA_H\r
+#define __STM32F7xx_HAL_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Types DMA Exported Types\r
+ * @brief DMA Exported Types \r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief DMA Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Channel; /*!< Specifies the channel used for the specified stream. \r
+ This parameter can be a value of @ref DMAEx_Channel_selection */\r
+\r
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, \r
+ from memory to memory or from peripheral to memory.\r
+ This parameter can be a value of @ref DMA_Data_transfer_direction */\r
+\r
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */\r
+\r
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.\r
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */\r
+\r
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_Peripheral_data_size */\r
+\r
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_Memory_data_size */\r
+\r
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_mode\r
+ @note The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Stream */\r
+\r
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.\r
+ This parameter can be a value of @ref DMA_Priority_level */\r
+\r
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\r
+ This parameter can be a value of @ref DMA_FIFO_direct_mode\r
+ @note The Direct mode (FIFO mode disabled) cannot be used if the \r
+ memory-to-memory data transfer is configured on the selected stream */\r
+\r
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.\r
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */\r
+\r
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction.\r
+ This parameter can be a value of @ref DMA_Memory_burst \r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+\r
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r
+ It specifies the amount of data to be transferred in a single non interruptible \r
+ transaction. \r
+ This parameter can be a value of @ref DMA_Peripheral_burst\r
+ @note The burst mode is possible only if the address Increment mode is enabled. */\r
+}DMA_InitTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */\r
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */\r
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */\r
+ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */\r
+ HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */\r
+ HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */\r
+}HAL_DMA_StateTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */\r
+}HAL_DMA_LevelCompleteTypeDef;\r
+\r
+/** \r
+ * @brief HAL DMA Error Code structure definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */\r
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */\r
+ HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */\r
+ HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */\r
+ HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */\r
+ HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */\r
+ HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */\r
+}HAL_DMA_CallbackIDTypeDef;\r
+\r
+/** \r
+ * @brief DMA handle Structure definition\r
+ */\r
+typedef struct __DMA_HandleTypeDef\r
+{\r
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */\r
+\r
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */ \r
+\r
+ HAL_LockTypeDef Lock; /*!< DMA locking object */ \r
+\r
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */\r
+\r
+ void *Parent; /*!< Parent object state */ \r
+\r
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */\r
+\r
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */\r
+\r
+ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */\r
+ \r
+ void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */\r
+ \r
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */\r
+ \r
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ \r
+\r
+ __IO uint32_t ErrorCode; /*!< DMA Error code */\r
+ \r
+ uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */\r
+\r
+ uint32_t StreamIndex; /*!< DMA Stream Index */\r
+ \r
+}DMA_HandleTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @brief DMA Exported constants \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Error_Code DMA Error Code\r
+ * @brief DMA Error Code \r
+ * @{\r
+ */ \r
+#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */\r
+#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */\r
+#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */\r
+#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */\r
+#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */\r
+#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */\r
+#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */\r
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r
+ * @brief DMA data transfer direction \r
+ * @{\r
+ */ \r
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */\r
+#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */\r
+#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r
+ * @brief DMA peripheral incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */\r
+#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r
+ * @brief DMA memory incremented mode \r
+ * @{\r
+ */ \r
+#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */\r
+#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r
+ * @brief DMA peripheral data size \r
+ * @{\r
+ */ \r
+#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */\r
+#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */\r
+#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_data_size DMA Memory data size\r
+ * @brief DMA memory data size \r
+ * @{ \r
+ */\r
+#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */\r
+#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */\r
+#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_mode DMA mode\r
+ * @brief DMA mode \r
+ * @{\r
+ */ \r
+#define DMA_NORMAL 0x00000000U /*!< Normal mode */\r
+#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */\r
+#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Priority_level DMA Priority level\r
+ * @brief DMA priority levels \r
+ * @{\r
+ */\r
+#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */\r
+#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */\r
+#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */\r
+#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\r
+ * @brief DMA FIFO direct mode\r
+ * @{\r
+ */\r
+#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */\r
+#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\r
+ * @brief DMA FIFO level \r
+ * @{\r
+ */\r
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */\r
+#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */\r
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */\r
+#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Memory_burst DMA Memory burst\r
+ * @brief DMA memory burst \r
+ * @{\r
+ */ \r
+#define DMA_MBURST_SINGLE 0x00000000U\r
+#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0\r
+#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1\r
+#define DMA_MBURST_INC16 DMA_SxCR_MBURST\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\r
+ * @brief DMA peripheral burst \r
+ * @{\r
+ */ \r
+#define DMA_PBURST_SINGLE 0x00000000U\r
+#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0\r
+#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1\r
+#define DMA_PBURST_INC16 DMA_SxCR_PBURST\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r
+ * @brief DMA interrupts definition \r
+ * @{\r
+ */\r
+#define DMA_IT_TC DMA_SxCR_TCIE\r
+#define DMA_IT_HT DMA_SxCR_HTIE\r
+#define DMA_IT_TE DMA_SxCR_TEIE\r
+#define DMA_IT_DME DMA_SxCR_DMEIE\r
+#define DMA_IT_FE 0x00000080U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flag_definitions DMA flag definitions\r
+ * @brief DMA flag definitions \r
+ * @{\r
+ */ \r
+#define DMA_FLAG_FEIF0_4 0x00000001U\r
+#define DMA_FLAG_DMEIF0_4 0x00000004U\r
+#define DMA_FLAG_TEIF0_4 0x00000008U\r
+#define DMA_FLAG_HTIF0_4 0x00000010U\r
+#define DMA_FLAG_TCIF0_4 0x00000020U\r
+#define DMA_FLAG_FEIF1_5 0x00000040U\r
+#define DMA_FLAG_DMEIF1_5 0x00000100U\r
+#define DMA_FLAG_TEIF1_5 0x00000200U\r
+#define DMA_FLAG_HTIF1_5 0x00000400U\r
+#define DMA_FLAG_TCIF1_5 0x00000800U\r
+#define DMA_FLAG_FEIF2_6 0x00010000U\r
+#define DMA_FLAG_DMEIF2_6 0x00040000U\r
+#define DMA_FLAG_TEIF2_6 0x00080000U\r
+#define DMA_FLAG_HTIF2_6 0x00100000U\r
+#define DMA_FLAG_TCIF2_6 0x00200000U\r
+#define DMA_FLAG_FEIF3_7 0x00400000U\r
+#define DMA_FLAG_DMEIF3_7 0x01000000U\r
+#define DMA_FLAG_TEIF3_7 0x02000000U\r
+#define DMA_FLAG_HTIF3_7 0x04000000U\r
+#define DMA_FLAG_TCIF3_7 0x08000000U\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/** @brief Reset DMA handle state\r
+ * @param __HANDLE__ specifies the DMA handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO filled level.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The FIFO filling state.\r
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \r
+ * and not empty.\r
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r
+ * - DMA_FIFOStatus_Empty: when FIFO is empty\r
+ * - DMA_FIFOStatus_Full: when FIFO is full\r
+ */\r
+#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)\r
+\r
+/* Interrupt & Flag management */\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer complete flag index.\r
+ */\r
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\r
+ DMA_FLAG_TCIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream half transfer complete flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified half transfer complete flag index.\r
+ */ \r
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\r
+ DMA_FLAG_HTIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream transfer error flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified transfer error flag index.\r
+ */\r
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\r
+ DMA_FLAG_TEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream FIFO error flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified FIFO error flag index.\r
+ */\r
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\r
+ DMA_FLAG_FEIF3_7)\r
+\r
+/**\r
+ * @brief Return the current DMA Stream direct mode error flag.\r
+ * @param __HANDLE__ DMA handle\r
+ * @retval The specified direct mode error flag index.\r
+ */\r
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\r
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\r
+ DMA_FLAG_DMEIF3_7)\r
+\r
+/**\r
+ * @brief Get the DMA Stream pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ Get the specified flag.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval The state of FLAG (SET or RESET).\r
+ */\r
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the DMA Stream pending flags.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.\r
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.\r
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.\r
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. \r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\r
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\r
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\r
+\r
+/**\r
+ * @brief Enable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Disable the specified DMA Stream interrupts.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval None\r
+ */\r
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Check whether the specified DMA Stream interrupt is enabled or not.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.\r
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask.\r
+ * @arg DMA_IT_FE: FIFO error interrupt mask.\r
+ * @arg DMA_IT_DME: Direct mode error interrupt.\r
+ * @retval The state of DMA_IT.\r
+ */\r
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \\r
+ ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \\r
+ ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))\r
+\r
+/**\r
+ * @brief Writes the number of data units to be transferred on the DMA Stream.\r
+ * @param __HANDLE__ DMA handle\r
+ * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) \r
+ * Number of data items depends only on the Peripheral data format.\r
+ * \r
+ * @note If Peripheral data format is Bytes: number of data units is equal \r
+ * to total number of bytes to be transferred.\r
+ * \r
+ * @note If Peripheral data format is Half-Word: number of data units is \r
+ * equal to total number of bytes to be transferred / 2.\r
+ * \r
+ * @note If Peripheral data format is Word: number of data units is equal \r
+ * to total number of bytes to be transferred / 4.\r
+ * \r
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.\r
+ */\r
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.\r
+ * @param __HANDLE__ DMA handle\r
+ * \r
+ * @retval The number of remaining data units in the current DMA Stream transfer.\r
+ */\r
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)\r
+\r
+\r
+/* Include DMA HAL Extension module */\r
+#include "stm32f7xx_hal_dma_ex.h" \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Functions DMA Exported Functions\r
+ * @brief DMA Exported functions \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); \r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\r
+ * @brief I/O operation functions \r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));\r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\r
+ * @brief Peripheral State functions \r
+ * @{\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+/* Private Constants -------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Constants DMA Private Constants\r
+ * @brief DMA private defines and constants \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Macros DMA Private Macros\r
+ * @brief DMA private macros \r
+ * @{\r
+ */\r
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \\r
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) \r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\r
+ ((STATE) == DMA_PINC_DISABLE))\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \\r
+ ((STATE) == DMA_MINC_DISABLE))\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_PDATAALIGN_WORD))\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \\r
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\r
+ ((SIZE) == DMA_MDATAALIGN_WORD ))\r
+\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \\r
+ ((MODE) == DMA_CIRCULAR) || \\r
+ ((MODE) == DMA_PFCTRL)) \r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \\r
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\r
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \\r
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) \r
+\r
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\r
+ ((STATE) == DMA_FIFOMODE_ENABLE))\r
+\r
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\r
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\r
+\r
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\r
+ ((BURST) == DMA_MBURST_INC4) || \\r
+ ((BURST) == DMA_MBURST_INC8) || \\r
+ ((BURST) == DMA_MBURST_INC16))\r
+\r
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\r
+ ((BURST) == DMA_PBURST_INC4) || \\r
+ ((BURST) == DMA_PBURST_INC8) || \\r
+ ((BURST) == DMA_PBURST_INC16))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMA_Private_Functions DMA Private Functions\r
+ * @brief DMA private functions \r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of DMA HAL extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_DMA_EX_H\r
+#define __STM32F7xx_HAL_DMA_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMAEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r
+ * @brief DMAEx Exported types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief HAL DMA Memory definition \r
+ */ \r
+typedef enum\r
+{\r
+ MEMORY0 = 0x00U, /*!< Memory 0 */\r
+ MEMORY1 = 0x01U, /*!< Memory 1 */\r
+\r
+}HAL_DMA_MemoryTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup DMA_Exported_Constants DMA Exported Constants\r
+ * @brief DMA Exported constants \r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx_Channel_selection DMA Channel selection\r
+ * @brief DMAEx channel selection \r
+ * @{\r
+ */ \r
+#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */\r
+#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */\r
+#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */\r
+#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */\r
+#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */\r
+#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */\r
+#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */\r
+#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */\r
+#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */\r
+#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/\r
+#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/\r
+#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/\r
+#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/\r
+#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/\r
+#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r
+ * @brief DMAEx Exported functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ * @{\r
+ */\r
+\r
+/* IO operation functions *******************************************************/\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);\r
+\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Macros DMA Private Macros\r
+ * @brief DMAEx private macros \r
+ * @{\r
+ */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\r
+ ((CHANNEL) == DMA_CHANNEL_1) || \\r
+ ((CHANNEL) == DMA_CHANNEL_2) || \\r
+ ((CHANNEL) == DMA_CHANNEL_3) || \\r
+ ((CHANNEL) == DMA_CHANNEL_4) || \\r
+ ((CHANNEL) == DMA_CHANNEL_5) || \\r
+ ((CHANNEL) == DMA_CHANNEL_6) || \\r
+ ((CHANNEL) == DMA_CHANNEL_7) || \\r
+ ((CHANNEL) == DMA_CHANNEL_8) || \\r
+ ((CHANNEL) == DMA_CHANNEL_9) || \\r
+ ((CHANNEL) == DMA_CHANNEL_10) || \\r
+ ((CHANNEL) == DMA_CHANNEL_11) || \\r
+ ((CHANNEL) == DMA_CHANNEL_12) || \\r
+ ((CHANNEL) == DMA_CHANNEL_13) || \\r
+ ((CHANNEL) == DMA_CHANNEL_14) || \\r
+ ((CHANNEL) == DMA_CHANNEL_15)) \r
+#else\r
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\r
+ ((CHANNEL) == DMA_CHANNEL_1) || \\r
+ ((CHANNEL) == DMA_CHANNEL_2) || \\r
+ ((CHANNEL) == DMA_CHANNEL_3) || \\r
+ ((CHANNEL) == DMA_CHANNEL_4) || \\r
+ ((CHANNEL) == DMA_CHANNEL_5) || \\r
+ ((CHANNEL) == DMA_CHANNEL_6) || \\r
+ ((CHANNEL) == DMA_CHANNEL_7))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions\r
+ * @brief DMAEx Private functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_DMA_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_exti.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of EXTI HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2018 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_EXTI_H\r
+#define __STM32F7xx_HAL_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI EXTI\r
+ * @brief EXTI HAL module driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup EXTI_Exported_Types EXTI Exported Types\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_EXTI_COMMON_CB_ID = 0x00U,\r
+ HAL_EXTI_RISING_CB_ID = 0x01U,\r
+ HAL_EXTI_FALLING_CB_ID = 0x02U,\r
+} EXTI_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief EXTI Handle structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Line; /*!< Exti line number */\r
+ void (* PendingCallback)(void); /*!< Exti pending callback */\r
+} EXTI_HandleTypeDef;\r
+\r
+/**\r
+ * @brief EXTI Configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Line; /*!< The Exti line to be configured. This parameter\r
+ can be a value of @ref EXTI_Line */\r
+ uint32_t Mode; /*!< The Exit Mode to be configured for a core.\r
+ This parameter can be a combination of @ref EXTI_Mode */\r
+ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter\r
+ can be a value of @ref EXTI_Trigger */\r
+} EXTI_ConfigTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Line EXTI Line\r
+ * @{\r
+ */\r
+#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */\r
+#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */\r
+#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */\r
+#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */\r
+#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */\r
+#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */\r
+#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */\r
+#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */\r
+#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */\r
+#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */\r
+#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */\r
+#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */\r
+#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */\r
+#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */\r
+#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */\r
+#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */\r
+#if defined(EXTI_IMR_IM16)\r
+#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */\r
+#endif /* EXTI_IMR_IM16 */\r
+#if defined(EXTI_IMR_IM17)\r
+#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
+#endif /* EXTI_IMR_IM17 */\r
+#if defined(EXTI_IMR_IM18)\r
+#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */\r
+#endif /* EXTI_IMR_IM18 */\r
+#if defined(EXTI_IMR_IM19)\r
+#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */\r
+#endif /* EXTI_IMR_IM19 */\r
+#if defined(EXTI_IMR_IM20)\r
+#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */\r
+#endif /* EXTI_IMR_IM20 */\r
+#if defined(EXTI_IMR_IM21)\r
+#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ \r
+#endif /* EXTI_IMR_IM21 */\r
+#if defined(EXTI_IMR_IM22)\r
+#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */\r
+#endif /* EXTI_IMR_IM22 */\r
+#if defined(EXTI_IMR_IM23)\r
+#define EXTI_LINE_23 EXTI_IMR_IM23 /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */\r
+#endif /* EXTI_IMR_IM23 */\r
+#if defined(EXTI_IMR_IM24)\r
+#define EXTI_LINE_24 EXTI_IMR_IM24 /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */\r
+#endif /* EXTI_IMR_IM24 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Mode EXTI Mode\r
+ * @{\r
+ */\r
+#define EXTI_MODE_NONE 0x00000000u\r
+#define EXTI_MODE_INTERRUPT 0x00000001u\r
+#define EXTI_MODE_EVENT 0x00000002u\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Trigger EXTI Trigger\r
+ * @{\r
+ */\r
+#define EXTI_TRIGGER_NONE 0x00000000u\r
+#define EXTI_TRIGGER_RISING 0x00000001u\r
+#define EXTI_TRIGGER_FALLING 0x00000002u\r
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private constants --------------------------------------------------------*/\r
+/** @defgroup EXTI_Private_Constants EXTI Private Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @brief EXTI Mask for interrupt & event mode\r
+ */\r
+#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)\r
+\r
+/**\r
+ * @brief EXTI Mask for trigger possibilities\r
+ */\r
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)\r
+\r
+/**\r
+ * @brief EXTI Line number\r
+ */\r
+#define EXTI_LINE_NB 25u\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup EXTI_Private_Macros EXTI Private Macros\r
+ * @{\r
+ */\r
+#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~EXTI_IMR_IM) == 0x00U) && (__LINE__))\r
+\r
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))\r
+\r
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)\r
+\r
+#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \\r
+ ((__LINE__) == EXTI_TRIGGER_RISING) || \\r
+ ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))\r
+\r
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions\r
+ * @brief EXTI Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions\r
+ * @brief Configuration functions\r
+ * @{\r
+ */\r
+/* Configuration functions ****************************************************/\r
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\r
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\r
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);\r
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));\r
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions\r
+ * @brief IO operation functions\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);\r
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\r
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\r
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_EXTI_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of FLASH HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_FLASH_H\r
+#define __STM32F7xx_HAL_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief FLASH Procedure structure definition\r
+ */\r
+typedef enum\r
+{\r
+ FLASH_PROC_NONE = 0U,\r
+ FLASH_PROC_SECTERASE,\r
+ FLASH_PROC_MASSERASE,\r
+ FLASH_PROC_PROGRAM\r
+} FLASH_ProcedureTypeDef;\r
+\r
+\r
+/**\r
+ * @brief FLASH handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */\r
+\r
+ __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */\r
+\r
+ __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */\r
+\r
+ __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */\r
+\r
+ __IO uint32_t Address; /* Internal variable to save address selected for program */\r
+\r
+ HAL_LockTypeDef Lock; /* FLASH locking object */\r
+\r
+ __IO uint32_t ErrorCode; /* FLASH error code */\r
+\r
+}FLASH_ProcessTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_Error_Code FLASH Error Code\r
+ * @brief FLASH Error Code\r
+ * @{\r
+ */\r
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */\r
+#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */\r
+#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */\r
+#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */\r
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */\r
+#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */\r
+#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Type_Program FLASH Type Program\r
+ * @{\r
+ */\r
+#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */\r
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Flag_definition FLASH Flag definition\r
+ * @brief Flag definition\r
+ * @{\r
+ */\r
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */\r
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */\r
+#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */\r
+#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */\r
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */\r
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\r
+ FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR)\r
+#else\r
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\r
+ FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR)\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition\r
+ * @brief FLASH Interrupt definition\r
+ * @{\r
+ */\r
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */\r
+#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism\r
+ * @{\r
+ */\r
+#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)\r
+#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)\r
+#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)\r
+#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)\r
+#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Keys FLASH Keys\r
+ * @{\r
+ */\r
+#define FLASH_KEY1 ((uint32_t)0x45670123U)\r
+#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)\r
+#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)\r
+#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Sectors FLASH Sectors\r
+ * @{\r
+ */\r
+#if (FLASH_SECTOR_TOTAL == 2)\r
+#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */\r
+#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */\r
+#elif (FLASH_SECTOR_TOTAL == 4)\r
+#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */\r
+#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */\r
+#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */\r
+#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */\r
+#else\r
+#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */\r
+#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */\r
+#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */\r
+#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */\r
+#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */\r
+#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */\r
+#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */\r
+#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */\r
+#endif /* FLASH_SECTOR_TOTAL */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Set the FLASH Latency.\r
+ * @param __LATENCY__ FLASH Latency\r
+ * The value of this parameter depend on device used within the same series\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \\r
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))\r
+\r
+/**\r
+ * @brief Get the FLASH Latency.\r
+ * @retval FLASH Latency\r
+ * The value of this parameter depend on device used within the same series\r
+ */\r
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\r
+\r
+/**\r
+ * @brief Enable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)\r
+\r
+/**\r
+ * @brief Disable the FLASH prefetch buffer.\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))\r
+\r
+/**\r
+ * @brief Enable the FLASH Adaptive Real-Time memory accelerator.\r
+ * @note The ART accelerator is available only for flash access on ITCM interface.\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r
+\r
+/**\r
+ * @brief Disable the FLASH Adaptive Real-Time memory accelerator.\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r
+\r
+/**\r
+ * @brief Resets the FLASH Adaptive Real-Time memory accelerator.\r
+ * @note This function must be used only when the Adaptive Real-Time memory accelerator\r
+ * is disabled.\r
+ * @retval None\r
+ */\r
+#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST)\r
+\r
+/**\r
+ * @brief Enable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ FLASH interrupt\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+ * @arg FLASH_IT_ERR: Error Interrupt\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Disable the specified FLASH interrupt.\r
+ * @param __INTERRUPT__ FLASH interrupt\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r
+ * @arg FLASH_IT_ERR: Error Interrupt\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Get the specified FLASH flag status.\r
+ * @param __FLAG__ specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag\r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r
+ * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag\r
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag\r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))\r
+\r
+/**\r
+ * @brief Clear the specified FLASH flag.\r
+ * @param __FLAG__ specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag\r
+ * @arg FLASH_FLAG_OPERR : FLASH operation Error flag\r
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag\r
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r
+ * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r
+ * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag\r
+ * @retval none\r
+ */\r
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include FLASH HAL Extension module */\r
+#include "stm32f7xx_hal_flash_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+/** @addtogroup FLASH_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Program operation functions ***********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r
+/* FLASH IRQ handler method */\r
+void HAL_FLASH_IRQHandler(void);\r
+/* Callbacks in non blocking modes */\r
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r
+/* Option bytes control */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Exported_Functions_Group3\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+uint32_t HAL_FLASH_GetError(void);\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Variables FLASH Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Constants FLASH Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief OPTCR register byte 1 (Bits[15:8]) base address\r
+ */\r
+#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \\r
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASH_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_FLASH_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of FLASH HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_FLASH_EX_H\r
+#define __STM32F7xx_HAL_FLASH_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief FLASH Erase structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.\r
+ This parameter can be a value of @ref FLASHEx_Type_Erase */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.\r
+ This parameter must be a value of @ref FLASHEx_Banks */\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled\r
+ This parameter must be a value of @ref FLASHEx_Sectors */\r
+\r
+ uint32_t NbSectors; /*!< Number of sectors to be erased.\r
+ This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\r
+\r
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism\r
+ This parameter must be a value of @ref FLASHEx_Voltage_Range */\r
+\r
+} FLASH_EraseInitTypeDef;\r
+\r
+/**\r
+ * @brief FLASH Option Bytes Program structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OptionType; /*!< Option byte to be configured.\r
+ This parameter can be a value of @ref FLASHEx_Option_Type */\r
+\r
+ uint32_t WRPState; /*!< Write protection activation or deactivation.\r
+ This parameter can be a value of @ref FLASHEx_WRP_State */\r
+\r
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.\r
+ The value of this parameter depend on device used within the same series */\r
+\r
+ uint32_t RDPLevel; /*!< Set the read protection level.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\r
+\r
+ uint32_t BORLevel; /*!< Set the BOR Level.\r
+ This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */\r
+\r
+ uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /\r
+ IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.\r
+ nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */\r
+\r
+ uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.\r
+ This parameter can be a value of @ref FLASHEx_Boot_Address */\r
+\r
+ uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.\r
+ This parameter can be a value of @ref FLASHEx_Boot_Address */\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+ uint32_t PCROPSector; /*!< Set the PCROP sector.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */\r
+\r
+ uint32_t PCROPRdp; /*!< Set the PCROP_RDP option.\r
+ This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+\r
+} FLASH_OBProgramInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase\r
+ * @{\r
+ */\r
+#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */\r
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range\r
+ * @{\r
+ */\r
+#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */\r
+#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */\r
+#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */\r
+#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_WRP_State FLASH WRP State\r
+ * @{\r
+ */\r
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */\r
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Type FLASH Option Type\r
+ * @{\r
+ */\r
+#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */\r
+#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */\r
+#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */\r
+#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */\r
+#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */\r
+#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */\r
+#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection\r
+ * @{\r
+ */\r
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)\r
+#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)\r
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2\r
+ it s no more possible to go back to level 1 or 0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog\r
+ * @{\r
+ */\r
+#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */\r
+#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog\r
+ * @{\r
+ */\r
+#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */\r
+#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP\r
+ * @{\r
+ */\r
+#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY\r
+ * @{\r
+ */\r
+#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP\r
+ * @{\r
+ */\r
+#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */\r
+#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY\r
+ * @{\r
+ */\r
+#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */\r
+#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level\r
+ * @{\r
+ */\r
+#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */\r
+#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */\r
+#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */\r
+#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (FLASH_OPTCR_nDBOOT)\r
+/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT\r
+ * @{\r
+ */\r
+#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */\r
+#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash\r
+ (Dual bank Boot mode), or RAM if Boot address option in RAM */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OPTCR_nDBOOT */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank\r
+ * @{\r
+ */\r
+#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */\r
+#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address\r
+ * @{\r
+ */\r
+#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */\r
+#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */\r
+#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */\r
+#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */\r
+#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */\r
+#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */\r
+#if (SRAM2_BASE == 0x2003C000U)\r
+#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */\r
+#else\r
+#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */\r
+#endif /* SRAM2_BASE == 0x2003C000U */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Latency FLASH Latency\r
+ * @{\r
+ */\r
+#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */\r
+#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */\r
+#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */\r
+#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */\r
+#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */\r
+#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */\r
+#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */\r
+#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */\r
+#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */\r
+#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */\r
+#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */\r
+#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */\r
+#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */\r
+#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */\r
+#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */\r
+#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+/** @defgroup FLASHEx_Banks FLASH Banks\r
+ * @{\r
+ */\r
+#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */\r
+#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */\r
+#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit\r
+ * @{\r
+ */\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */\r
+#else\r
+#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASHEx_Sectors FLASH Sectors\r
+ * @{\r
+ */\r
+#if (FLASH_SECTOR_TOTAL == 24)\r
+#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */\r
+#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */\r
+#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */\r
+#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */\r
+#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */\r
+#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */\r
+#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */\r
+#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */\r
+#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */\r
+#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */\r
+#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */\r
+#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */\r
+#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */\r
+#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */\r
+#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */\r
+#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */\r
+#endif /* FLASH_SECTOR_TOTAL == 24 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 24)\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r
+ * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.\r
+ * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r
+ * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and\r
+ * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).\r
+ * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.\r
+ * @{\r
+ */\r
+/* Single Bank Sectors */\r
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */\r
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */\r
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */\r
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */\r
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */\r
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */\r
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */\r
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */\r
+#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */\r
+#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */\r
+#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */\r
+#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */\r
+#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */\r
+\r
+/* Dual Bank Sectors */\r
+#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */\r
+#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */\r
+#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */\r
+#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */\r
+#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */\r
+#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */\r
+#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */\r
+#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */\r
+#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */\r
+#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */\r
+#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */\r
+#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */\r
+#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */\r
+#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */\r
+#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */\r
+#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */\r
+#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */\r
+#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */\r
+#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */\r
+#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */\r
+#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */\r
+#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */\r
+#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */\r
+#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */\r
+#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 24 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 8)\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @{\r
+ */\r
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */\r
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */\r
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */\r
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */\r
+#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */\r
+#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */\r
+#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */\r
+#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */\r
+#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 8 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 4)\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @{\r
+ */\r
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */\r
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */\r
+#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */\r
+#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */\r
+#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 4 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 2)\r
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r
+ * @{\r
+ */\r
+#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */\r
+#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */\r
+#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 2 */\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+#if (FLASH_SECTOR_TOTAL == 8)\r
+/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors\r
+ * @{\r
+ */\r
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */\r
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */\r
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */\r
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */\r
+#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */\r
+#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */\r
+#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */\r
+#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */\r
+#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 8 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 4)\r
+/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors\r
+ * @{\r
+ */\r
+#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */\r
+#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */\r
+#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */\r
+#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */\r
+#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_SECTOR_TOTAL == 4 */\r
+\r
+/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit\r
+ * @{\r
+ */\r
+#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */\r
+#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)\r
+ * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].\r
+ * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)\r
+ * @retval The FLASH Boot Base Adress\r
+ */\r
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASHEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Extension Program operation functions *************************************/\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters\r
+ * @{\r
+ */\r
+\r
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \\r
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))\r
+\r
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \\r
+ ((RANGE) == FLASH_VOLTAGE_RANGE_4))\r
+\r
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \\r
+ ((VALUE) == OB_WRPSTATE_ENABLE))\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\r
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\\r
+ OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP)))\r
+#else\r
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\r
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+\r
+#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)\r
+\r
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\\r
+ ((LEVEL) == OB_RDP_LEVEL_1) ||\\r
+ ((LEVEL) == OB_RDP_LEVEL_2))\r
+\r
+#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))\r
+\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))\r
+\r
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))\r
+\r
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\r
+ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\r
+\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \\r
+ ((LATENCY) == FLASH_LATENCY_1) || \\r
+ ((LATENCY) == FLASH_LATENCY_2) || \\r
+ ((LATENCY) == FLASH_LATENCY_3) || \\r
+ ((LATENCY) == FLASH_LATENCY_4) || \\r
+ ((LATENCY) == FLASH_LATENCY_5) || \\r
+ ((LATENCY) == FLASH_LATENCY_6) || \\r
+ ((LATENCY) == FLASH_LATENCY_7) || \\r
+ ((LATENCY) == FLASH_LATENCY_8) || \\r
+ ((LATENCY) == FLASH_LATENCY_9) || \\r
+ ((LATENCY) == FLASH_LATENCY_10) || \\r
+ ((LATENCY) == FLASH_LATENCY_11) || \\r
+ ((LATENCY) == FLASH_LATENCY_12) || \\r
+ ((LATENCY) == FLASH_LATENCY_13) || \\r
+ ((LATENCY) == FLASH_LATENCY_14) || \\r
+ ((LATENCY) == FLASH_LATENCY_15))\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \\r
+ (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))\r
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))\r
+\r
+#if (FLASH_SECTOR_TOTAL == 8)\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\\r
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\\r
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\\r
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r
+#endif /* FLASH_SECTOR_TOTAL == 8 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 24)\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\\r
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\\r
+ ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\\r
+ ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\\r
+ ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\\r
+ ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\\r
+ ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\\r
+ ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\\r
+ ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\\r
+ ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\\r
+ ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\\r
+ ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r
+#endif /* FLASH_SECTOR_TOTAL == 24 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 4)\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\\r
+ ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r
+#endif /* FLASH_SECTOR_TOTAL == 4 */\r
+\r
+#if (FLASH_SECTOR_TOTAL == 2)\r
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1))\r
+\r
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r
+#endif /* FLASH_SECTOR_TOTAL == 2 */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \\r
+ ((VALUE) == OB_NDBANK_DUAL_BANK))\r
+\r
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \\r
+ ((BANK) == FLASH_BANK_2) || \\r
+ ((BANK) == FLASH_BANK_BOTH))\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+#if defined (FLASH_OPTCR_nDBOOT)\r
+#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \\r
+ ((VALUE) == OB_DUAL_BOOT_ENABLE))\r
+#endif /* FLASH_OPTCR_nDBOOT */\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U)\r
+#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \\r
+ ((VALUE) == OB_PCROP_RDP_ENABLE))\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions\r
+ * @{\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_FLASH_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of GPIO HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_GPIO_H\r
+#define __STM32F7xx_HAL_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Types GPIO Exported Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief GPIO Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIO_mode_define */\r
+\r
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r
+ This parameter can be a value of @ref GPIO_pull_define */\r
+\r
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIO_speed_define */\r
+\r
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. \r
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */\r
+}GPIO_InitTypeDef;\r
+\r
+/** \r
+ * @brief GPIO Bit SET and Bit RESET enumeration \r
+ */\r
+typedef enum\r
+{\r
+ GPIO_PIN_RESET = 0,\r
+ GPIO_PIN_SET\r
+}GPIO_PinState;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_pins_define GPIO pins define\r
+ * @{\r
+ */\r
+#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */\r
+#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */\r
+#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */\r
+#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */\r
+#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */\r
+#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */\r
+#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */\r
+#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */\r
+#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */\r
+#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */\r
+#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */\r
+#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */\r
+#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */\r
+#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */\r
+#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */\r
+#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */\r
+#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */\r
+\r
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_mode_define GPIO mode define\r
+ * @brief GPIO Configuration Mode \r
+ * Elements values convention: 0xX0yz00YZ\r
+ * - X : GPIO mode or EXTI Mode\r
+ * - y : External IT or Event trigger detection \r
+ * - z : IO configuration on External IT or Event\r
+ * - Y : Output type (Push Pull or Open Drain)\r
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)\r
+ * @{\r
+ */ \r
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */\r
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */\r
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */\r
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */\r
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */\r
+\r
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */\r
+ \r
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+ \r
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */\r
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */\r
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_speed_define GPIO speed define\r
+ * @brief GPIO Output Maximum frequency\r
+ * @{\r
+ */ \r
+#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */\r
+#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */\r
+#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */\r
+#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /** @defgroup GPIO_pull_define GPIO pull define\r
+ * @brief GPIO Pull-Up or Pull-Down Activation\r
+ * @{\r
+ */ \r
+#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */\r
+#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */\r
+#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param __EXTI_LINE__ specifies the EXTI line flag to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending flags.\r
+ * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param __EXTI_LINE__ specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).\r
+ */\r
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Clears the EXTI's line pending bits.\r
+ * @param __EXTI_LINE__ specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on selected EXTI line.\r
+ * @param __EXTI_LINE__ specifies the EXTI line to check.\r
+ * This parameter can be GPIO_PIN_x where x can be(0..15)\r
+ * @retval None\r
+ */\r
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include GPIO HAL Extension module */\r
+#include "stm32f7xx_hal_gpio_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup GPIO_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* IO operation functions *****************************************************/\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r
+#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00))\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\\r
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\\r
+ ((MODE) == GPIO_MODE_AF_PP) ||\\r
+ ((MODE) == GPIO_MODE_AF_OD) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\r
+ ((MODE) == GPIO_MODE_ANALOG))\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \\r
+ ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))\r
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\r
+ ((PULL) == GPIO_PULLDOWN))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup GPIO_Private_Functions GPIO Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_GPIO_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of GPIO HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_GPIO_EX_H\r
+#define __STM32F7xx_HAL_GPIO_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIOEx GPIOEx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\r
+ * @{\r
+ */ \r
+/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\\r
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) \r
+/** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */\r
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */\r
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */\r
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */\r
+#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */\r
+#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */\r
+#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */\r
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */\r
+#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */\r
+#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */\r
+#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */\r
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */\r
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */\r
+#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */\r
+#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 6 selection \r
+ */ \r
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ \r
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */\r
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */\r
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */\r
+#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */\r
+#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */\r
+#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 8 selection \r
+ */ \r
+#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */\r
+#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */\r
+#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */\r
+#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */\r
+#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */\r
+#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+\r
+/** \r
+ * @brief AF 9 selection \r
+ */ \r
+#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */\r
+#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */\r
+#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */\r
+#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */\r
+#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */\r
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)\r
+#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)\r
+#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */\r
+#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */\r
+#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */\r
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r
+#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */\r
+#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ \r
+#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */\r
+#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */\r
+#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */\r
+#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+/** \r
+ * @brief AF 12 selection \r
+ */ \r
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */\r
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */\r
+#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */\r
+#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r
+#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */\r
+#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ \r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ \r
+/** \r
+ * @brief AF 13 selection \r
+ */ \r
+#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */\r
+#if defined (STM32F769xx) || defined (STM32F779xx) \r
+#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)\r
+#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ \r
+ \r
+/** \r
+ * @brief AF 14 selection \r
+ */\r
+#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ \r
+#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx)\r
+ /** \r
+ * @brief AF 0 selection \r
+ */ \r
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */\r
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */\r
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */\r
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 1 selection \r
+ */ \r
+#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */\r
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 2 selection \r
+ */ \r
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */\r
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */\r
+#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 3 selection \r
+ */ \r
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */\r
+#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */\r
+#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */\r
+#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */\r
+#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 4 selection \r
+ */ \r
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */\r
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */\r
+#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ \r
+\r
+/** \r
+ * @brief AF 5 selection \r
+ */ \r
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */\r
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */\r
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */\r
+#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 6 selection \r
+ */ \r
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */\r
+#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 7 selection \r
+ */ \r
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */\r
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */\r
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */\r
+#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */\r
+#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ \r
+\r
+/** \r
+ * @brief AF 8 selection \r
+ */ \r
+#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */\r
+#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */\r
+#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */\r
+#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */\r
+#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */\r
+#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 9 selection \r
+ */ \r
+#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */\r
+#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */\r
+#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */\r
+#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */\r
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */\r
+\r
+/** \r
+ * @brief AF 10 selection \r
+ */ \r
+#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */\r
+#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */\r
+#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */\r
+#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */\r
+#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ \r
+\r
+/** \r
+ * @brief AF 11 selection \r
+ */ \r
+#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */\r
+ \r
+/** \r
+ * @brief AF 12 selection \r
+ */ \r
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */\r
+#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */\r
+#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */\r
+ \r
+/** \r
+ * @brief AF 13 selection \r
+ */ \r
+#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */ \r
+ \r
+/** \r
+ * @brief AF 15 selection \r
+ */ \r
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ \r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/ \r
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO pin available on the platform\r
+ */\r
+/* Defines the available pins per GPIOs */\r
+#define GPIOA_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOB_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOC_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOD_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOE_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOF_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOG_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOI_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOH_PIN_AVAILABLE GPIO_PIN_All\r
+#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \\r
+ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\r
+ * @{\r
+ */\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\r
+ ((__GPIOx__) == (GPIOB))? 1U :\\r
+ ((__GPIOx__) == (GPIOC))? 2U :\\r
+ ((__GPIOx__) == (GPIOD))? 3U :\\r
+ ((__GPIOx__) == (GPIOE))? 4U :\\r
+ ((__GPIOx__) == (GPIOF))? 5U :\\r
+ ((__GPIOx__) == (GPIOG))? 6U :\\r
+ ((__GPIOx__) == (GPIOH))? 7U :\\r
+ ((__GPIOx__) == (GPIOI))? 8U :\\r
+ ((__GPIOx__) == (GPIOJ))? 9U : 10U)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\r
+ ((__GPIOx__) == (GPIOB))? 1U :\\r
+ ((__GPIOx__) == (GPIOC))? 2U :\\r
+ ((__GPIOx__) == (GPIOD))? 3U :\\r
+ ((__GPIOx__) == (GPIOE))? 4U :\\r
+ ((__GPIOx__) == (GPIOF))? 5U :\\r
+ ((__GPIOx__) == (GPIOG))? 6U :\\r
+ ((__GPIOx__) == (GPIOH))? 7U : 8U)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \\r
+ ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \\r
+ (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))\r
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \\r
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \\r
+ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))\r
+#elif defined(STM32F745xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \\r
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))\r
+#elif defined(STM32F767xx) || defined(STM32F777xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \\r
+ ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \\r
+ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \\r
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \\r
+ ((AF) == GPIO_AF14_LTDC))\r
+#elif defined(STM32F769xx) || defined(STM32F779xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \\r
+ ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \\r
+ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \\r
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \\r
+ ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI))\r
+#elif defined(STM32F765xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \\r
+ ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \\r
+ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \\r
+ ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \\r
+ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \\r
+ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \\r
+ ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \\r
+ ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \\r
+ ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \\r
+ ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \\r
+ ((AF) == GPIO_AF10_OTG_FS))\r
+#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \\r
+ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \\r
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \\r
+ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \\r
+ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \\r
+ ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \\r
+ ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \\r
+ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \\r
+ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \\r
+ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \\r
+ ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \\r
+ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \\r
+ ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \\r
+ ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \\r
+ ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \\r
+ ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \\r
+ ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \\r
+ ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \\r
+ ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \\r
+ ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \\r
+ ((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \\r
+ ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \\r
+ ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \\r
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \\r
+ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \\r
+ ((AF) == GPIO_AF10_OTG_FS))\r
+#endif /* STM32F756xx || STM32F746xx || STM32F750xx */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_GPIO_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of I2C HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32F7xx_HAL_I2C_H\r
+#define STM32F7xx_HAL_I2C_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup I2C_Exported_Types I2C Exported Types\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r
+ * @brief I2C Configuration Structure definition\r
+ * @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.\r
+ This parameter calculated by referring to I2C initialization\r
+ section in Reference manual */\r
+\r
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_ADDRESSING_MODE */\r
+\r
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.\r
+ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */\r
+\r
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected\r
+ This parameter can be a 7-bit address. */\r
+\r
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected\r
+ This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */\r
+\r
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.\r
+ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */\r
+\r
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.\r
+ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */\r
+\r
+} I2C_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_state_structure_definition HAL state structure definition\r
+ * @brief HAL State structure definition\r
+ * @note HAL I2C State value coding follow below described bitmap :\n\r
+ * b7-b6 Error information\n\r
+ * 00 : No Error\n\r
+ * 01 : Abort (Abort user request on going)\n\r
+ * 10 : Timeout\n\r
+ * 11 : Error\n\r
+ * b5 Peripheral initialization status\n\r
+ * 0 : Reset (peripheral not initialized)\n\r
+ * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n\r
+ * b4 (not used)\n\r
+ * x : Should be set to 0\n\r
+ * b3\n\r
+ * 0 : Ready or Busy (No Listen mode ongoing)\n\r
+ * 1 : Listen (peripheral in Address Listen Mode)\n\r
+ * b2 Intrinsic process state\n\r
+ * 0 : Ready\n\r
+ * 1 : Busy (peripheral busy with some configuration or internal operations)\n\r
+ * b1 Rx state\n\r
+ * 0 : Ready (no Rx operation ongoing)\n\r
+ * 1 : Busy (Rx operation ongoing)\n\r
+ * b0 Tx state\n\r
+ * 0 : Ready (no Tx operation ongoing)\n\r
+ * 1 : Busy (Tx operation ongoing)\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */\r
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */\r
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */\r
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */\r
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */\r
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission\r
+ process is ongoing */\r
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception\r
+ process is ongoing */\r
+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */\r
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */\r
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */\r
+\r
+} HAL_I2C_StateTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition\r
+ * @brief HAL Mode structure definition\r
+ * @note HAL I2C Mode value coding follow below described bitmap :\n\r
+ * b7 (not used)\n\r
+ * x : Should be set to 0\n\r
+ * b6\n\r
+ * 0 : None\n\r
+ * 1 : Memory (HAL I2C communication is in Memory Mode)\n\r
+ * b5\n\r
+ * 0 : None\n\r
+ * 1 : Slave (HAL I2C communication is in Slave Mode)\n\r
+ * b4\n\r
+ * 0 : None\n\r
+ * 1 : Master (HAL I2C communication is in Master Mode)\n\r
+ * b3-b2-b1-b0 (not used)\n\r
+ * xxxx : Should be set to 0000\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */\r
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */\r
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */\r
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */\r
+\r
+} HAL_I2C_ModeTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r
+ * @brief I2C Error Code definition\r
+ * @{\r
+ */\r
+#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */\r
+#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */\r
+#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */\r
+#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */\r
+#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */\r
+#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */\r
+#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */\r
+#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */\r
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\r
+ * @brief I2C handle Structure definition\r
+ * @{\r
+ */\r
+typedef struct __I2C_HandleTypeDef\r
+{\r
+ I2C_TypeDef *Instance; /*!< I2C registers base address */\r
+\r
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */\r
+\r
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */\r
+\r
+ uint16_t XferSize; /*!< I2C transfer size */\r
+\r
+ __IO uint16_t XferCount; /*!< I2C transfer counter */\r
+\r
+ __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can\r
+ be a value of @ref I2C_XFEROPTIONS */\r
+\r
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state */\r
+\r
+ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */\r
+\r
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */\r
+\r
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */\r
+\r
+ HAL_LockTypeDef Lock; /*!< I2C locking object */\r
+\r
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */\r
+\r
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */\r
+\r
+ __IO uint32_t ErrorCode; /*!< I2C Error code */\r
+\r
+ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */\r
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */\r
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */\r
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */\r
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */\r
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */\r
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */\r
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */\r
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */\r
+\r
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */\r
+\r
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */\r
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */\r
+\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+} I2C_HandleTypeDef;\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL I2C Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */\r
+ HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */\r
+ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */\r
+ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */\r
+ HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */\r
+ HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */\r
+ HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */\r
+ HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */\r
+ HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */\r
+\r
+ HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */\r
+ HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */\r
+\r
+} HAL_I2C_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL I2C Callback pointer definition\r
+ */\r
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */\r
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */\r
+\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Constants I2C Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options\r
+ * @{\r
+ */\r
+#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)\r
+#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
+#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r
+#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)\r
+#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)\r
+#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)\r
+\r
+/* List of XferOptions in usage of :\r
+ * 1- Restart condition in all use cases (direction change or not)\r
+ */\r
+#define I2C_OTHER_FRAME (0x000000AAU)\r
+#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)\r
+#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_DUALADDRESS_DISABLE (0x00000000U)\r
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks\r
+ * @{\r
+ */\r
+#define I2C_OA2_NOMASK ((uint8_t)0x00U)\r
+#define I2C_OA2_MASK01 ((uint8_t)0x01U)\r
+#define I2C_OA2_MASK02 ((uint8_t)0x02U)\r
+#define I2C_OA2_MASK03 ((uint8_t)0x03U)\r
+#define I2C_OA2_MASK04 ((uint8_t)0x04U)\r
+#define I2C_OA2_MASK05 ((uint8_t)0x05U)\r
+#define I2C_OA2_MASK06 ((uint8_t)0x06U)\r
+#define I2C_OA2_MASK07 ((uint8_t)0x07U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode\r
+ * @{\r
+ */\r
+#define I2C_GENERALCALL_DISABLE (0x00000000U)\r
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode\r
+ * @{\r
+ */\r
+#define I2C_NOSTRETCH_DISABLE (0x00000000U)\r
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size\r
+ * @{\r
+ */\r
+#define I2C_MEMADD_SIZE_8BIT (0x00000001U)\r
+#define I2C_MEMADD_SIZE_16BIT (0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View\r
+ * @{\r
+ */\r
+#define I2C_DIRECTION_TRANSMIT (0x00000000U)\r
+#define I2C_DIRECTION_RECEIVE (0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode\r
+ * @{\r
+ */\r
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD\r
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND\r
+#define I2C_SOFTEND_MODE (0x00000000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode\r
+ * @{\r
+ */\r
+#define I2C_NO_STARTSTOP (0x00000000U)\r
+#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)\r
+#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)\r
+#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r
+ * @brief I2C Interrupt definition\r
+ * Elements values convention: 0xXXXXXXXX\r
+ * - XXXXXXXX : Interrupt control mask\r
+ * @{\r
+ */\r
+#define I2C_IT_ERRI I2C_CR1_ERRIE\r
+#define I2C_IT_TCI I2C_CR1_TCIE\r
+#define I2C_IT_STOPI I2C_CR1_STOPIE\r
+#define I2C_IT_NACKI I2C_CR1_NACKIE\r
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE\r
+#define I2C_IT_RXI I2C_CR1_RXIE\r
+#define I2C_IT_TXI I2C_CR1_TXIE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Flag_definition I2C Flag definition\r
+ * @{\r
+ */\r
+#define I2C_FLAG_TXE I2C_ISR_TXE\r
+#define I2C_FLAG_TXIS I2C_ISR_TXIS\r
+#define I2C_FLAG_RXNE I2C_ISR_RXNE\r
+#define I2C_FLAG_ADDR I2C_ISR_ADDR\r
+#define I2C_FLAG_AF I2C_ISR_NACKF\r
+#define I2C_FLAG_STOPF I2C_ISR_STOPF\r
+#define I2C_FLAG_TC I2C_ISR_TC\r
+#define I2C_FLAG_TCR I2C_ISR_TCR\r
+#define I2C_FLAG_BERR I2C_ISR_BERR\r
+#define I2C_FLAG_ARLO I2C_ISR_ARLO\r
+#define I2C_FLAG_OVR I2C_ISR_OVR\r
+#define I2C_FLAG_PECERR I2C_ISR_PECERR\r
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT\r
+#define I2C_FLAG_ALERT I2C_ISR_ALERT\r
+#define I2C_FLAG_BUSY I2C_ISR_BUSY\r
+#define I2C_FLAG_DIR I2C_ISR_DIR\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Macros I2C Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset I2C handle state.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \\r
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \\r
+ (__HANDLE__)->MspInitCallback = NULL; \\r
+ (__HANDLE__)->MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r
+#endif\r
+\r
+/** @brief Enable the specified I2C interrupt.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified I2C interrupt.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r
+\r
+/** @brief Check whether the specified I2C interrupt source is enabled or not.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __INTERRUPT__ specifies the I2C interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable\r
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable\r
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable\r
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable\r
+ * @arg @ref I2C_IT_RXI RX interrupt enable\r
+ * @arg @ref I2C_IT_TXI TX interrupt enable\r
+ *\r
+ * @retval The new state of __INTERRUPT__ (SET or RESET).\r
+ */\r
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Check whether the specified I2C flag is set or not.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty\r
+ * @arg @ref I2C_FLAG_TXIS Transmit interrupt status\r
+ * @arg @ref I2C_FLAG_RXNE Receive data register not empty\r
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)\r
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag\r
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag\r
+ * @arg @ref I2C_FLAG_TC Transfer complete (master mode)\r
+ * @arg @ref I2C_FLAG_TCR Transfer complete reload\r
+ * @arg @ref I2C_FLAG_BERR Bus error\r
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost\r
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun\r
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception\r
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
+ * @arg @ref I2C_FLAG_ALERT SMBus alert\r
+ * @arg @ref I2C_FLAG_BUSY Bus busy\r
+ * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)\r
+ *\r
+ * @retval The new state of __FLAG__ (SET or RESET).\r
+ */\r
+#define I2C_FLAG_MASK (0x0001FFFFU)\r
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)\r
+\r
+/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty\r
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)\r
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag\r
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag\r
+ * @arg @ref I2C_FLAG_BERR Bus error\r
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost\r
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun\r
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception\r
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r
+ * @arg @ref I2C_FLAG_ALERT SMBus alert\r
+ *\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \\r
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))\r
+\r
+/** @brief Enable the specified I2C peripheral.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief Disable the specified I2C peripheral.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r
+\r
+/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.\r
+ * @param __HANDLE__ specifies the I2C Handle.\r
+ * @retval None\r
+ */\r
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include I2C HAL Extended module */\r
+#include "stm32f7xx_hal_i2c_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup I2C_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions******************************/\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);\r
+\r
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ * @{\r
+ */\r
+/* IO operation functions ****************************************************/\r
+/******* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r
+\r
+/******* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\r
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\r
+\r
+/******* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r
+\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */\r
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\r
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
+ * @{\r
+ */\r
+/* Peripheral State, Mode and Error functions *********************************/\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Constants I2C Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Macro I2C Private Macros\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\r
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r
+\r
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\r
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r
+\r
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \\r
+ ((MASK) == I2C_OA2_MASK01) || \\r
+ ((MASK) == I2C_OA2_MASK02) || \\r
+ ((MASK) == I2C_OA2_MASK03) || \\r
+ ((MASK) == I2C_OA2_MASK04) || \\r
+ ((MASK) == I2C_OA2_MASK05) || \\r
+ ((MASK) == I2C_OA2_MASK06) || \\r
+ ((MASK) == I2C_OA2_MASK07))\r
+\r
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \\r
+ ((CALL) == I2C_GENERALCALL_ENABLE))\r
+\r
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\r
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r
+\r
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\r
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r
+\r
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \\r
+ ((MODE) == I2C_AUTOEND_MODE) || \\r
+ ((MODE) == I2C_SOFTEND_MODE))\r
+\r
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \\r
+ ((REQUEST) == I2C_GENERATE_START_READ) || \\r
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \\r
+ ((REQUEST) == I2C_NO_STARTSTOP))\r
+\r
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \\r
+ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \\r
+ ((REQUEST) == I2C_NEXT_FRAME) || \\r
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \\r
+ ((REQUEST) == I2C_LAST_FRAME) || \\r
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \\r
+ IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))\r
+\r
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \\r
+ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))\r
+\r
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r
+\r
+#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))\r
+#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))\r
+#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)\r
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))\r
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)\r
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)\r
+\r
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))\r
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))\r
+\r
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\r
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r
+\r
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)\r
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32f7xx_hal_i2c.c file */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32F7xx_HAL_I2C_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of I2C HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32F7xx_HAL_I2C_EX_H\r
+#define STM32F7xx_HAL_I2C_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2CEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter\r
+ * @{\r
+ */\r
+#define I2C_ANALOGFILTER_ENABLE 0x00000000U\r
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus\r
+ * @{\r
+ */\r
+#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */\r
+#if defined(SYSCFG_PMC_I2C_PB6_FMP)\r
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */\r
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */\r
+#else\r
+#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */\r
+#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */\r
+#endif\r
+#if defined(SYSCFG_PMC_I2C_PB8_FMP)\r
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */\r
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */\r
+#else\r
+#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */\r
+#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */\r
+#endif\r
+#if defined(SYSCFG_PMC_I2C1_FMP)\r
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */\r
+#else\r
+#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */\r
+#endif\r
+#if defined(SYSCFG_PMC_I2C2_FMP)\r
+#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */\r
+#else\r
+#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */\r
+#endif\r
+#if defined(SYSCFG_PMC_I2C3_FMP)\r
+#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */\r
+#else\r
+#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */\r
+#endif\r
+#if defined(SYSCFG_PMC_I2C4_FMP)\r
+#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */\r
+#else\r
+#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ * @{\r
+ */\r
+\r
+/* Peripheral Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r
+#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)\r
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);\r
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);\r
+#endif\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros\r
+ * @{\r
+ */\r
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\r
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r
+\r
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)\r
+\r
+#if (defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP))\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))\r
+#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))\r
+#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))\r
+#elif defined(SYSCFG_PMC_I2C1_FMP)\r
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \\r
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))\r
+#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private Functions ---------------------------------------------------------*/\r
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions\r
+ * @{\r
+ */\r
+/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32F7xx_HAL_I2C_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of PWR HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PWR_H\r
+#define __STM32F7xx_HAL_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Types PWR Exported Types\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief PWR PVD configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.\r
+ This parameter can be a value of @ref PWR_PVD_detection_level */\r
+\r
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref PWR_PVD_Mode */\r
+}PWR_PVDTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Constants PWR Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r
+ * @{\r
+ */ \r
+#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0\r
+#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1\r
+#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2\r
+#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3\r
+#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4\r
+#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5\r
+#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6\r
+#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage \r
+ (Compare internally to VREFINT) */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PWR_PVD_Mode PWR PVD Mode\r
+ * @{\r
+ */\r
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */\r
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */\r
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)\r
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r
+ * @{\r
+ */\r
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)\r
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r
+ * @{\r
+ */\r
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)\r
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale\r
+ * @{\r
+ */\r
+#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS\r
+#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1\r
+#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag PWR Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_WU PWR_CSR1_WUIF\r
+#define PWR_FLAG_SB PWR_CSR1_SBF\r
+#define PWR_FLAG_PVDO PWR_CSR1_PVDO\r
+#define PWR_FLAG_BRR PWR_CSR1_BRR\r
+#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWR_Exported_Macro PWR Exported Macro\r
+ * @{\r
+ */\r
+\r
+/** @brief macros configure the main internal regulator output voltage.\r
+ * @param __REGULATOR__ specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption when the device does\r
+ * not operate at the maximum frequency (refer to the datasheets for more details).\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \\r
+ __IO uint32_t tmpreg; \\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+/** @brief Check PWR flag is set or not.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r
+ * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),\r
+ * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).\r
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r
+ * resumed from StandBy mode. \r
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode \r
+ * For this reason, this bit is equal to 0 after Standby or reset\r
+ * until the PVDE bit is set.\r
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset \r
+ * when the device wakes up from Standby mode or by a system reset \r
+ * or power reset. \r
+ * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage \r
+ * scaling output selection is ready.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the PWR's pending flags.\r
+ * @param __FLAG__ specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ */\r
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2)\r
+\r
+/**\r
+ * @brief Enable the PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Disable the PVD EXTI Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Enable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Disable event on PVD Exti Line 16.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r
+\r
+/**\r
+ * @brief Enable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r
+\r
+\r
+/**\r
+ * @brief PVD EXTI line configuration: set rising & falling edge trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r
+\r
+/**\r
+ * @brief checks whether the specified PVD Exti interrupt flag is set or not.\r
+ * @retval EXTI PVD Line Status.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Clear the PVD Exti flag.\r
+ * @retval None.\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @brief Generates a Software interrupt on PVD EXTI line.\r
+ * @retval None\r
+ */\r
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include PWR HAL Extension module */\r
+#include "stm32f7xx_hal_pwr_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @{\r
+ */\r
+/* Initialization and de-initialization functions *****************************/\r
+void HAL_PWR_DeInit(void);\r
+void HAL_PWR_EnableBkUpAccess(void);\r
+void HAL_PWR_DisableBkUpAccess(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
+ * @{\r
+ */\r
+/* Peripheral Control functions **********************************************/\r
+/* PVD configuration */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r
+void HAL_PWR_EnablePVD(void);\r
+void HAL_PWR_DisablePVD(void);\r
+\r
+/* WakeUp pins configuration */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r
+\r
+/* Low Power modes entry */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r
+void HAL_PWR_EnterSTANDBYMode(void);\r
+\r
+/* Power PVD IRQ Handler */\r
+void HAL_PWR_PVD_IRQHandler(void);\r
+void HAL_PWR_PVDCallback(void);\r
+\r
+/* Cortex System Control functions *******************************************/\r
+void HAL_PWR_EnableSleepOnExit(void);\r
+void HAL_PWR_DisableSleepOnExit(void);\r
+void HAL_PWR_EnableSEVOnPend(void);\r
+void HAL_PWR_DisableSEVOnPend(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Constants PWR Private Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\r
+ * @{\r
+ */\r
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWR_Private_Macros PWR Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\r
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\r
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\r
+ ((MODE) == PWR_PVD_MODE_NORMAL))\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\r
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\r
+ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PWR_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of PWR HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_PWR_EX_H\r
+#define __STM32F7xx_HAL_PWR_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWREx\r
+ * @{\r
+ */ \r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\r
+ * @{\r
+ */\r
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1\r
+#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2\r
+#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3\r
+#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4\r
+#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5\r
+#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6\r
+#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1\r
+#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2\r
+#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3\r
+#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4\r
+#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5\r
+#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6\r
+#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)\r
+#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)\r
+#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)\r
+#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)\r
+#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)\r
+#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode\r
+ * @{\r
+ */\r
+#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS\r
+#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag\r
+ * @{\r
+ */\r
+#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY\r
+#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY\r
+#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags\r
+ * @{\r
+ */\r
+#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1\r
+#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2\r
+#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3\r
+#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4\r
+#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5\r
+#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro\r
+ * @{\r
+ */\r
+/** @brief Macros to enable or disable the Over drive mode.\r
+ */\r
+#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)\r
+#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))\r
+\r
+/** @brief Macros to enable or disable the Over drive switching.\r
+ */\r
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)\r
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))\r
+\r
+/** @brief Macros to enable or disable the Under drive mode.\r
+ * @note This mode is enabled only with STOP low power mode.\r
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r
+ * mode is only available when the main regulator or the low power regulator \r
+ * is in low voltage mode. \r
+ * @note If the Under-drive mode was enabled, it is automatically disabled after \r
+ * exiting Stop mode. \r
+ * When the voltage regulator operates in Under-drive mode, an additional \r
+ * startup delay is induced when waking up from Stop mode.\r
+ */\r
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)\r
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))\r
+\r
+/** @brief Check PWR flag is set or not.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode\r
+ * is ready \r
+ * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode\r
+ * switching is ready \r
+ * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode\r
+ * is enabled in Stop mode\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the Under-Drive Ready flag.\r
+ */\r
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)\r
+\r
+/** @brief Check Wake Up flag is set or not.\r
+ * @param __WUFLAG__ specifies the Wake Up flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 \r
+ */\r
+#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))\r
+\r
+/** @brief Clear the WakeUp pins flags.\r
+ * @param __WUFLAG__ specifies the Wake Up pin flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 \r
+ */\r
+#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup PWREx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+uint32_t HAL_PWREx_GetVoltageRange(void);\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r
+\r
+void HAL_PWREx_EnableFlashPowerDown(void);\r
+void HAL_PWREx_DisableFlashPowerDown(void); \r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); \r
+\r
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void);\r
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void);\r
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void);\r
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void);\r
+\r
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);\r
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);\r
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup PWREx_Private_Macros PWREx Private Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters\r
+ * @{\r
+ */\r
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \\r
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))\r
+#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \\r
+ ((__PIN__) == PWR_WAKEUP_PIN6_LOW))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32F7xx_HAL_PWR_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of RCC HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RCC_H\r
+#define __STM32F7xx_HAL_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+ \r
+/* Include RCC HAL Extended module */\r
+/* (include on top of file since RCC structures are defined in extended file) */\r
+#include "stm32f7xx_hal_rcc_ex.h" \r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/ \r
+\r
+/** @defgroup RCC_Exported_Types RCC Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OscillatorType; /*!< The oscillators to be configured.\r
+ This parameter can be a value of @ref RCC_Oscillator_Type */\r
+\r
+ uint32_t HSEState; /*!< The new state of the HSE.\r
+ This parameter can be a value of @ref RCC_HSE_Config */\r
+\r
+ uint32_t LSEState; /*!< The new state of the LSE.\r
+ This parameter can be a value of @ref RCC_LSE_Config */\r
+ \r
+ uint32_t HSIState; /*!< The new state of the HSI.\r
+ This parameter can be a value of @ref RCC_HSI_Config */\r
+\r
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r
+ \r
+ uint32_t LSIState; /*!< The new state of the LSI.\r
+ This parameter can be a value of @ref RCC_LSI_Config */\r
+\r
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ \r
+\r
+}RCC_OscInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC System, AHB and APB busses clock configuration structure definition \r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockType; /*!< The clock to be configured.\r
+ This parameter can be a value of @ref RCC_System_Clock_Type */\r
+ \r
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.\r
+ This parameter can be a value of @ref RCC_System_Clock_Source */\r
+\r
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */\r
+\r
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r
+\r
+}RCC_ClkInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Constants RCC Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Oscillator_Type Oscillator Type\r
+ * @{\r
+ */\r
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)\r
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)\r
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)\r
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)\r
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Config RCC HSE Config\r
+ * @{\r
+ */\r
+#define RCC_HSE_OFF ((uint32_t)0x00000000U)\r
+#define RCC_HSE_ON RCC_CR_HSEON\r
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Config RCC LSE Config\r
+ * @{\r
+ */\r
+#define RCC_LSE_OFF ((uint32_t)0x00000000U)\r
+#define RCC_LSE_ON RCC_BDCR_LSEON\r
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSI_Config RCC HSI Config\r
+ * @{\r
+ */\r
+#define RCC_HSI_OFF ((uint32_t)0x00000000U)\r
+#define RCC_HSI_ON RCC_CR_HSION\r
+\r
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Config RCC LSI Config\r
+ * @{\r
+ */\r
+#define RCC_LSI_OFF ((uint32_t)0x00000000U)\r
+#define RCC_LSI_ON RCC_CSR_LSION\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Config RCC PLL Config\r
+ * @{\r
+ */\r
+#define RCC_PLL_NONE ((uint32_t)0x00000000U)\r
+#define RCC_PLL_OFF ((uint32_t)0x00000001U)\r
+#define RCC_PLL_ON ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)\r
+#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)\r
+#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)\r
+#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r
+ * @{\r
+ */\r
+#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI\r
+#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_System_Clock_Type RCC System Clock Type\r
+ * @{\r
+ */\r
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)\r
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)\r
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)\r
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_System_Clock_Source RCC System Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r
+ * @{\r
+ */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */\r
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)\r
+#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)\r
+#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)\r
+#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/** @defgroup RCC_MCO_Index RCC MCO Index\r
+ * @{\r
+ */\r
+#define RCC_MCO1 ((uint32_t)0x00000000U)\r
+#define RCC_MCO2 ((uint32_t)0x00000001U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)\r
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0\r
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1\r
+#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)\r
+#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0\r
+#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1\r
+#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler\r
+ * @{\r
+ */\r
+#define RCC_MCODIV_1 ((uint32_t)0x00000000U)\r
+#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2\r
+#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\r
+#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Interrupt RCC Interrupt \r
+ * @{\r
+ */\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01U)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02U)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04U)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08U)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10U)\r
+#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)\r
+#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)\r
+#define RCC_IT_CSS ((uint8_t)0x80U)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_Flag RCC Flags\r
+ * Elements values convention: 0XXYYYYYb\r
+ * - YYYYY : Flag position in the register\r
+ * - 0XX : Register index\r
+ * - 01: CR register\r
+ * - 10: BDCR register\r
+ * - 11: CSR register\r
+ * @{\r
+ */\r
+/* Flags in the CR register */\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31U)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)\r
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)\r
+#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)\r
+\r
+/* Flags in the BDCR register */\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x41U)\r
+\r
+/* Flags in the CSR register */\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)\r
+#define RCC_FLAG_BORRST ((uint8_t)0x79U)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x7AU)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x7BU)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations\r
+ * @{\r
+ */\r
+#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)\r
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1\r
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0\r
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCC_Exported_Macros RCC Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r
+ * @brief Enable or disable the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it. \r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\r
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0) \r
+\r
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\r
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable \r
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before \r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+ \r
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) \r
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r
+ * @brief EGet the enable or disable status of the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release\r
+ * @brief Force or release AHB peripheral reset.\r
+ * @{\r
+ */ \r
+#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\r
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))\r
+\r
+#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)\r
+#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\r
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset \r
+ * @brief Force or release APB1 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) \r
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\r
+\r
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) \r
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\r
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset \r
+ * @brief Force or release APB2 peripheral reset.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) \r
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))\r
+\r
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)\r
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r
+\r
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\r
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))\r
+\r
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))\r
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))\r
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)\r
+\r
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)\r
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)\r
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)\r
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_HSI_Configuration HSI Configuration\r
+ * @{ \r
+ */ \r
+ \r
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).\r
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.\r
+ * It is used (enabled by hardware) as system clock source after startup\r
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r
+ * of the HSE used directly or indirectly as system clock (if the Clock\r
+ * Security System CSS is enabled). \r
+ * @note HSI can not be stopped if it is used as system clock source. In this case,\r
+ * you have to select another source of the system clock then stop the HSI. \r
+ * @note After enabling the HSI, the application software should wait on HSIRDY\r
+ * flag to be set indicating that HSI clock is stable and can be used as\r
+ * system clock source. \r
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r
+ * clock cycles. \r
+ */\r
+#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))\r
+#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))\r
+\r
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r
+ * @note The calibration is used to compensate for the variations in voltage\r
+ * and temperature that influence the frequency of the internal HSI RC.\r
+ * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value.\r
+ * (default is RCC_HSICALIBRATION_DEFAULT).\r
+ */\r
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\\r
+ RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSI_Configuration LSI Configuration\r
+ * @{ \r
+ */ \r
+\r
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).\r
+ * @note After enabling the LSI, the application software should wait on \r
+ * LSIRDY flag to be set indicating that LSI clock is stable and can\r
+ * be used to clock the IWDG and/or the RTC.\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r
+ * clock cycles. \r
+ */\r
+#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))\r
+#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_HSE_Configuration HSE Configuration\r
+ * @{ \r
+ */ \r
+/**\r
+ * @brief Macro to configure the External High Speed oscillator (HSE).\r
+ * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this macro. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r
+ * software should wait on HSERDY flag to be set indicating that HSE clock\r
+ * is stable and can be used to clock the PLL and/or system clock.\r
+ * @note HSE state can not be changed if it is used directly or through the\r
+ * PLL as system clock. In this case, you have to select another source\r
+ * of the system clock then change the HSE state (ex. disable it).\r
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.\r
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)\r
+ * was previously enabled you have to enable it again after calling this\r
+ * function.\r
+ * @param __STATE__ specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r
+ * 6 HSE oscillator clock cycles.\r
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator.\r
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \\r
+ do { \\r
+ if ((__STATE__) == RCC_HSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ else if ((__STATE__) == RCC_HSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_LSE_Configuration LSE Configuration\r
+ * @{ \r
+ */\r
+\r
+/**\r
+ * @brief Macro to configure the External Low Speed oscillator (LSE).\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. \r
+ * User should request a transition to LSE Off first and then LSE On or LSE Bypass. \r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using \r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset). \r
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r
+ * software should wait on LSERDY flag to be set indicating that LSE clock\r
+ * is stable and can be used to clock the RTC.\r
+ * @param __STATE__ specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r
+ * 6 LSE oscillator clock cycles.\r
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.\r
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.\r
+ */\r
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \\r
+ do { \\r
+ if((__STATE__) == RCC_LSE_ON) \\r
+ { \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else if((__STATE__) == RCC_LSE_OFF) \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ } \\r
+ else if((__STATE__) == RCC_LSE_BYPASS) \\r
+ { \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ } \\r
+ else \\r
+ { \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \\r
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\r
+ } \\r
+ } while(0)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macros to enable or disable the RTC clock.\r
+ * @note These macros must be used only after the RTC clock source was selected.\r
+ */\r
+#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))\r
+#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))\r
+\r
+/** @brief Macros to configure the RTC clock (RTCCLK).\r
+ * @note As the RTC clock configuration bits are in the Backup domain and write\r
+ * access is denied to this domain after reset, you have to enable write\r
+ * access using the Power Backup Access macro before to configure\r
+ * the RTC clock source (to be done once after reset). \r
+ * @note Once the RTC clock is configured it can't be changed unless the \r
+ * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by\r
+ * a Power On Reset (POR).\r
+ * @param __RTCCLKSource__ specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected\r
+ * as RTC clock, where x:[2,31]\r
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to\r
+ * work in STOP and STANDBY modes, and can be used as wakeup source.\r
+ * However, when the HSE clock is used as RTC clock source, the RTC\r
+ * cannot be used in STOP and STANDBY modes. \r
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as\r
+ * RTC clock source).\r
+ */\r
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)\r
+ \r
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \\r
+ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \\r
+ } while (0)\r
+\r
+/** @brief Macro to get the RTC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()\r
+ */\r
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))\r
+\r
+/**\r
+ * @brief Get the RTC and HSE clock divider (RTCPRE).\r
+ * @retval Returned value can be one of the following values:\r
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected\r
+ * as RTC clock, where x:[2,31]\r
+ */\r
+#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)\r
+\r
+/** @brief Macros to force or release the Backup domain reset.\r
+ * @note This function resets the RTC peripheral (including the backup registers)\r
+ * and the RTC clock source selection in RCC_CSR register.\r
+ * @note The BKPSRAM is not affected by this reset. \r
+ */\r
+#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))\r
+#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_Configuration PLL Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macros to enable or disable the main PLL.\r
+ * @note After enabling the main PLL, the application software should wait on \r
+ * PLLRDY flag to be set indicating that PLL clock is stable and can\r
+ * be used as system clock source.\r
+ * @note The main PLL can not be disabled if it is used as system clock source\r
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)\r
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r
+ \r
+/** @brief Macro to configure the PLL clock source.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __PLLSOURCE__ specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * \r
+ */\r
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r
+\r
+/** @brief Macro to configure the PLL multiplication factor.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * \r
+ */\r
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration\r
+ * @{ \r
+ */\r
+\r
+/** @brief Macro to configure the I2S clock source (I2SCLK).\r
+ * @note This function must be called before enabling the I2S APB clock.\r
+ * @param __SOURCE__ specifies the I2S clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.\r
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin\r
+ * used as I2S clock source.\r
+ */\r
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \\r
+ RCC->CFGR |= (__SOURCE__); \\r
+ }while(0)\r
+\r
+/** @brief Macros to enable or disable the PLLI2S. \r
+ * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))\r
+#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Get_Clock_source Get Clock source\r
+ * @{ \r
+ */\r
+/**\r
+ * @brief Macro to configure the system clock source.\r
+ * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.\r
+ * This parameter can be one of the following values:\r
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r
+ */\r
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))\r
+\r
+/** @brief Macro to get the clock source used as system clock.\r
+ * @retval The clock source used as system clock. The returned value can be one\r
+ * of the following:\r
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r
+ */\r
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)\r
+\r
+/**\r
+ * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.\r
+ * @note As the LSE is in the Backup domain and write access is denied to\r
+ * this domain after reset, you have to enable write access using\r
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r
+ * (to be done once after reset).\r
+ * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.\r
+ * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.\r
+ * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.\r
+ * @retval None\r
+ */\r
+#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \\r
+ (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))\r
+\r
+/** @brief Macro to get the oscillator used as PLL clock source.\r
+ * @retval The oscillator used as PLL clock source. The returned value can be one\r
+ * of the following:\r
+ * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r
+ * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r
+ */\r
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\r
+ * @{ \r
+ */ \r
+ \r
+/** @brief Macro to configure the MCO1 clock.\r
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r
+ * @param __MCODIV__ specifies the MCO clock prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock\r
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r
+ */\r
+\r
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r
+ \r
+/** @brief Macro to configure the MCO2 clock.\r
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source \r
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r
+ * @param __MCODIV__ specifies the MCO clock prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock\r
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r
+ */\r
+\r
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r
+ * @brief macros to manage the specified RCC Flags and interrupts.\r
+ * @{\r
+ */\r
+\r
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable\r
+ * the selected interrupts).\r
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ */\r
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\r
+\r
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable \r
+ * the selected interrupts).\r
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ */\r
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))\r
+\r
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]\r
+ * bits to clear the selected interrupt pending bits.\r
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ */\r
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\r
+\r
+/** @brief Check the RCC's interrupt has occurred or not.\r
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.\r
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\r
+\r
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+ * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r
+ */\r
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)\r
+\r
+/** @brief Check RCC flag is set or not.\r
+ * @param __FLAG__ specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.\r
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.\r
+ * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.\r
+ * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.\r
+ * @arg RCC_FLAG_PINRST: Pin reset.\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.\r
+ * @arg RCC_FLAG_SFTRST: Software reset.\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define RCC_FLAG_MASK ((uint8_t)0x1F)\r
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Include RCC HAL Extension module */\r
+#include "stm32f7xx_hal_rcc_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+ /** @addtogroup RCC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group1\r
+ * @{\r
+ */ \r
+/* Initialization and de-initialization functions ******************************/\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void);\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RCC_Exported_Functions_Group2\r
+ * @{\r
+ */\r
+/* Peripheral Control functions ************************************************/\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r
+void HAL_RCC_EnableCSS(void);\r
+void HAL_RCC_DisableCSS(void);\r
+uint32_t HAL_RCC_GetSysClockFreq(void);\r
+uint32_t HAL_RCC_GetHCLKFreq(void);\r
+uint32_t HAL_RCC_GetPCLK1Freq(void);\r
+uint32_t HAL_RCC_GetPCLK2Freq(void);\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r
+\r
+/* CSS NMI IRQ handler */\r
+void HAL_RCC_NMI_IRQHandler(void);\r
+\r
+/* User Callbacks in non blocking mode (IT mode) */ \r
+void HAL_RCC_CSSCallback(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Constants RCC Private Constants\r
+ * @{\r
+ */\r
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT\r
+#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */\r
+#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */\r
+#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */\r
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */\r
+#define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */\r
+#define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */\r
+\r
+/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias\r
+ * @brief RCC registers bit address alias\r
+ * @{\r
+ */\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))\r
+\r
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)\r
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */ \r
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)\r
+\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_BYPASS))\r
+\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_BYPASS))\r
+\r
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))\r
+\r
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))\r
+\r
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))\r
+\r
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_PLLSOURCE_HSE))\r
+\r
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))\r
+#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))\r
+\r
+#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r
+\r
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \\r
+ ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))\r
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \\r
+ ((HCLK) == RCC_SYSCLK_DIV512))\r
+\r
+#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))\r
+\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \\r
+ ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \\r
+ ((PCLK) == RCC_HCLK_DIV16))\r
+\r
+#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))\r
+\r
+\r
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \\r
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))\r
+\r
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \\r
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))\r
+\r
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \\r
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \\r
+ ((DIV) == RCC_MCODIV_5)) \r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+\r
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \\r
+ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))\r
+\r
+\r
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \\r
+ ((DRIVE) == RCC_LSEDRIVE_HIGH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RCC_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of RCC HAL Extension module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_RCC_EX_H\r
+#define __STM32F7xx_HAL_RCC_EX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCCEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief RCC PLL configuration structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLState; /*!< The new state of the PLL.\r
+ This parameter can be a value of @ref RCC_PLL_Config */\r
+\r
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.\r
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */\r
+\r
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */\r
+\r
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.\r
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432 */\r
+\r
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).\r
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */\r
+\r
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15 */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7 */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+}RCC_PLLInitTypeDef;\r
+\r
+/**\r
+ * @brief PLLI2S Clock structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\r
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+ uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.\r
+ This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+}RCC_PLLI2SInitTypeDef;\r
+\r
+/**\r
+ * @brief PLLSAI Clock structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r
+ This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\r
+\r
+ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\r
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+ uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock\r
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ This parameter will be used only when PLLSAI is selected as Clock Source LTDC */\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+ uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.\r
+ This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider\r
+ This parameter will be used only when PLLSAI is disabled */\r
+}RCC_PLLSAIInitTypeDef;\r
+\r
+/**\r
+ * @brief RCC extended clocks structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r
+\r
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r
+\r
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.\r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */\r
+\r
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32\r
+ This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.\r
+ This parameter must be a number between Min_Data = 1 and Max_Data = 32\r
+ This parameter will be used only when PLLSAI is selected as Clock Source SAI */\r
+\r
+ uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.\r
+ This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */\r
+\r
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.\r
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */\r
+\r
+ uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.\r
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */\r
+\r
+ uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.\r
+ This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */\r
+\r
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection\r
+ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r
+\r
+ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection\r
+ This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\r
+\r
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source\r
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */\r
+\r
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source\r
+ This parameter can be a value of @ref RCCEx_USART2_Clock_Source */\r
+\r
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source\r
+ This parameter can be a value of @ref RCCEx_USART3_Clock_Source */\r
+\r
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source\r
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */\r
+\r
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source\r
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */\r
+\r
+ uint32_t Usart6ClockSelection; /*!< USART6 clock source\r
+ This parameter can be a value of @ref RCCEx_USART6_Clock_Source */\r
+\r
+ uint32_t Uart7ClockSelection; /*!< UART7 clock source\r
+ This parameter can be a value of @ref RCCEx_UART7_Clock_Source */\r
+\r
+ uint32_t Uart8ClockSelection; /*!< UART8 clock source\r
+ This parameter can be a value of @ref RCCEx_UART8_Clock_Source */\r
+\r
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source\r
+ This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */\r
+\r
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source\r
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */\r
+\r
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source\r
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */\r
+\r
+ uint32_t I2c4ClockSelection; /*!< I2C4 clock source\r
+ This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r
+\r
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source\r
+ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r
+\r
+ uint32_t CecClockSelection; /*!< CEC clock source\r
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */\r
+\r
+ uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC\r
+ This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\r
+\r
+ uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source\r
+ This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+ uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source\r
+ This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source\r
+ This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */\r
+\r
+ uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source\r
+ This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+}RCC_PeriphCLKInitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection\r
+ * @{\r
+ */\r
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)\r
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)\r
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)\r
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)\r
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)\r
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)\r
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)\r
+#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)\r
+#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)\r
+#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)\r
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)\r
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)\r
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)\r
+#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)\r
+#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)\r
+#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)\r
+#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)\r
+#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)\r
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)\r
+#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)\r
+#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)\r
+#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)\r
+#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\r
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)\r
+#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)\r
+#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)\r
+#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider\r
+ * @{\r
+ */\r
+#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)\r
+#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)\r
+#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)\r
+#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR\r
+ * @{\r
+ */\r
+#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)\r
+#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0\r
+#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1\r
+#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)\r
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)\r
+#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0\r
+#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)\r
+#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0\r
+#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL\r
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)\r
+#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)\r
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0\r
+#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1\r
+#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0\r
+#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1\r
+#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0\r
+#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1\r
+#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0\r
+#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1\r
+#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0\r
+#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1\r
+#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)\r
+#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0\r
+#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1\r
+#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0\r
+#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1\r
+#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0\r
+#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1\r
+#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0\r
+#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0\r
+#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0\r
+#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0\r
+#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)\r
+#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0\r
+#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1\r
+#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)\r
+#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection\r
+ * @{\r
+ */\r
+#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)\r
+#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)\r
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source\r
+ * @{\r
+ */\r
+#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)\r
+#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)\r
+#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)\r
+#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source\r
+ * @{\r
+ */\r
+#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)\r
+#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F769xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r
+ * @{\r
+ */\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable\r
+ * @brief Enables or disables the AHB/APB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+\r
+/** @brief Enables or disables the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\r
+#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))\r
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\r
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))\r
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))\r
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))\r
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\r
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\r
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\r
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\r
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))\r
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))\r
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))\r
+#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+/**\r
+ * @brief Enable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ETH_CLK_ENABLE() do { \\r
+ __HAL_RCC_ETHMAC_CLK_ENABLE(); \\r
+ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \\r
+ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \\r
+ } while(0)\r
+/**\r
+ * @brief Disable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))\r
+#define __HAL_RCC_ETH_CLK_DISABLE() do { \\r
+ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \\r
+ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \\r
+ __HAL_RCC_ETHMAC_CLK_DISABLE(); \\r
+ } while(0)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Enable or disable the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DCMI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_RNG_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\r
+ UNUSED(tmpreg); \\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\\r
+ } while(0)\r
+\r
+#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_CRYP_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_HASH_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))\r
+#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))\r
+#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_AES_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))\r
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+/** @brief Enables or disables the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_QSPI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))\r
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\r
+\r
+/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_RTC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_DAC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART7_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_UART8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_I2C4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CAN2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\r
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\r
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\r
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\r
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\r
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\r
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\r
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\r
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\r
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\r
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\r
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\r
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\r
+#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))\r
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))\r
+#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))\r
+#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\r
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */\r
+\r
+/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */\r
+\r
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_ADC3_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM9_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM10_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_TIM11_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI5_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SPI6_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_SAI2_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+\r
+#define __HAL_RCC_MDIO_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \\r
+ __IO uint32_t tmpreg; \\r
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\\r
+ /* Delay after an RCC peripheral clock enabling */ \\r
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\\r
+ UNUSED(tmpreg); \\r
+ } while(0)\r
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r
+\r
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\r
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\r
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\r
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\r
+#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\r
+#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\r
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))\r
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\r
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\r
+#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\r
+#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\r
+#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\r
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\r
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))\r
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\r
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))\r
+#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN))\r
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB/APB peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ * @{\r
+ */\r
+\r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)\r
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)\r
+#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)\r
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+/**\r
+ * @brief Enable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)\r
+#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \\r
+ __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \\r
+ __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())\r
+\r
+/**\r
+ * @brief Disable ETHERNET clock.\r
+ */\r
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)\r
+#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \\r
+ __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \\r
+ __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\r
+\r
+#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)\r
+#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)\r
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)\r
+#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)\r
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)\r
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)\r
+#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)\r
+\r
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)\r
+\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)\r
+#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock.\r
+ * @note After reset, the peripheral clock (used for registers read/write access)\r
+ * is disabled and the application software has to enable this clock before\r
+ * using it.\r
+ */\r
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET)\r
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET)\r
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset\r
+ * @brief Forces or releases AHB/APB peripheral reset.\r
+ * @{\r
+ */\r
+\r
+/** @brief Force or release AHB1 peripheral reset.\r
+ */\r
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\r
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\r
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\r
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))\r
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))\r
+\r
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))\r
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\r
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))\r
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))\r
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))\r
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\r
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\r
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\r
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\r
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))\r
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))\r
+#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))\r
+#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))\r
+#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))\r
+\r
+#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))\r
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))\r
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))\r
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Force or release AHB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\r
+\r
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)\r
+#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\r
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))\r
+#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\r
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))\r
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))\r
+#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))\r
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\r
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Force or release AHB3 peripheral reset\r
+ */\r
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\r
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\r
+\r
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)\r
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))\r
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))\r
+\r
+/** @brief Force or release APB1 peripheral reset.\r
+ */\r
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\r
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\r
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\r
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\r
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\r
+#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))\r
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))\r
+\r
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\r
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\r
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\r
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\r
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\r
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\r
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\r
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\r
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\r
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\r
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\r
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\r
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\r
+#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))\r
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))\r
+#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))\r
+#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\r
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))\r
+\r
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))\r
+#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))\r
+#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\r
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Force or release APB2 peripheral reset.\r
+ */\r
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))\r
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\r
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\r
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))\r
+#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))\r
+#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))\r
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\r
+#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\r
+#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))\r
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\r
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST))\r
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r
+\r
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\r
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\r
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\r
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))\r
+#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))\r
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))\r
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\r
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\r
+#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\r
+#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\r
+#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\r
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\r
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))\r
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\r
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST))\r
+#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))\r
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))\r
+#endif /* STM32F769xx || STM32F779xx */\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))\r
+#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))\r
+#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))\r
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))\r
+#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable\r
+ * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+\r
+/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ */\r
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\r
+#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\r
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\r
+#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))\r
+\r
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\r
+#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))\r
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\r
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\r
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\r
+#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))\r
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))\r
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\r
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))\r
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))\r
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))\r
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\r
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\r
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\r
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\r
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))\r
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))\r
+\r
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))\r
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))\r
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))\r
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))\r
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))\r
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))\r
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))\r
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\r
+\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\r
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r
+\r
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))\r
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))\r
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))\r
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))\r
+\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\r
+\r
+/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))\r
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))\r
+\r
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\r
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\r
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\r
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))\r
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\r
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\r
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\r
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\r
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\r
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))\r
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\r
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))\r
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\r
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\r
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\r
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))\r
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))\r
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\r
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\r
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\r
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))\r
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))\r
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\r
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))\r
+\r
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))\r
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))\r
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\r
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))\r
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))\r
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\r
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))\r
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))\r
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))\r
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\r
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\r
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))\r
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))\r
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\r
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))\r
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\r
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))\r
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\r
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\r
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))\r
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))\r
+#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))\r
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))\r
+#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))\r
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))\r
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status\r
+ * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ * @{\r
+ */\r
+\r
+/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)\r
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)\r
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)\r
+\r
+#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)\r
+#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)\r
+#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)\r
+#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)\r
+#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)\r
+#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)\r
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)\r
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)\r
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)\r
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)\r
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)\r
+#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)\r
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)\r
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)\r
+#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)\r
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)\r
+\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)\r
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)\r
+\r
+#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)\r
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)\r
+#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET)\r
+#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET)\r
+#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)\r
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)\r
+\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)\r
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)\r
+\r
+/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)\r
+\r
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)\r
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)\r
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)\r
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)\r
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)\r
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)\r
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)\r
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)\r
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)\r
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\r
+ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\r
+ defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r
+ STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)\r
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)\r
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)\r
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)\r
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)\r
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)\r
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)\r
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)\r
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)\r
+#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)\r
+#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)\r
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)\r
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)\r
+\r
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)\r
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)\r
+#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)\r
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce\r
+ * power consumption.\r
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.\r
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.\r
+ */\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)\r
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)\r
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)\r
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)\r
+#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)\r
+#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)\r
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)\r
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)\r
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)\r
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)\r
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)\r
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)\r
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)\r
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)\r
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)\r
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)\r
+#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)\r
+#endif /* STM32F769xx || STM32F779xx */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)\r
+#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)\r
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*------------------------------- PLL Configuration --------------------------*/\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.\r
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
+ * output frequency is between 100 and 432 MHz.\r
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)\r
+ * This parameter must be a number in the range {2, 4, 6, or 8}.\r
+ * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on\r
+ * the System clock frequency.\r
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @note If the USB OTG FS is used in your application, you have to set the\r
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
+ * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r
+ * correctly.\r
+ * @param __PLLR__ specifies the division factor for DSI clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ */\r
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \\r
+ (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \\r
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
+ ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \\r
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \\r
+ ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))\r
+#else\r
+/** @brief Macro to configure the main PLL clock source, multiplication and division factors.\r
+ * @note This function must be used only when the main PLL is disabled.\r
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.\r
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input\r
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r
+ * of 2 MHz to limit PLL jitter.\r
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO\r
+ * output frequency is between 100 and 432 MHz.\r
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)\r
+ * This parameter must be a number in the range {2, 4, 6, or 8}.\r
+ * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on\r
+ * the System clock frequency.\r
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @note If the USB OTG FS is used in your application, you have to set the\r
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r
+ * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r
+ * correctly.\r
+ */\r
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \\r
+ (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \\r
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \\r
+ ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \\r
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+/*---------------------------------------------------------------------------------------------*/\r
+\r
+/** @brief Macro to configure the Timers clocks prescalers\r
+ * @param __PRESC__ specifies the Timers clocks prescalers selection\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is\r
+ * equal to HPRE if PPREx is corresponding to division by 1 or 2,\r
+ * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to\r
+ * division by 4 or more.\r
+ * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is\r
+ * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,\r
+ * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding\r
+ * to division by 8 or more.\r
+ */\r
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\\r
+ RCC->DCKCFGR1 |= (__PRESC__); \\r
+ }while(0)\r
+\r
+/** @brief Macros to Enable or Disable the PLLISAI.\r
+ * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.\r
+ */\r
+#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))\r
+#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.\r
+ * @note This function must be used only when the PLLSAI is disabled.\r
+ * @note PLLSAI clock source is common with the main PLL (configured in\r
+ * RCC_PLLConfig function )\r
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO\r
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r
+ * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks\r
+ * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.\r
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ */\r
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \\r
+ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\\r
+ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\\r
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))\r
+\r
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors.\r
+ * @note This macro must be used only when the PLLI2S is disabled.\r
+ * @note PLLI2S clock source is common with the main PLL (configured in\r
+ * HAL_RCC_ClockConfig() API)\r
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO\r
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock.\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @param __PLLI2SR__ specifies the division factor for I2S clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r
+ * on the I2S clock frequency.\r
+ */\r
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \\r
+ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\\r
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\\r
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))\r
+#else\r
+/** @brief Macro to configure the PLLSAI clock multiplication and division factors.\r
+ * @note This function must be used only when the PLLSAI is disabled.\r
+ * @note PLLSAI clock source is common with the main PLL (configured in\r
+ * RCC_PLLConfig function )\r
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO\r
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r
+ * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks\r
+ * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.\r
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ */\r
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \\r
+ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\\r
+ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\\r
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\\r
+ ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))\r
+\r
+/** @brief Macro to configure the PLLI2S clock multiplication and division factors.\r
+ * @note This macro must be used only when the PLLI2S is disabled.\r
+ * @note PLLI2S clock source is common with the main PLL (configured in\r
+ * HAL_RCC_ClockConfig() API)\r
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.\r
+ * This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO\r
+ * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r
+ * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock.\r
+ * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.\r
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock.\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r
+ * @param __PLLI2SR__ specifies the division factor for I2S clock\r
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r
+ * on the I2S clock frequency.\r
+ */\r
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \\r
+ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\\r
+ ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\\r
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\\r
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.\r
+ * @note This function must be called before enabling the PLLI2S.\r
+ * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock .\r
+ * This parameter must be a number between 1 and 32.\r
+ * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__\r
+ */\r
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))\r
+\r
+/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.\r
+ * @note This function must be called before enabling the PLLSAI.\r
+ * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .\r
+ * This parameter must be a number between Min_Data = 1 and Max_Data = 32.\r
+ * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__\r
+ */\r
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))\r
+\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\r
+ defined (STM32F750xx)\r
+/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.\r
+ * @note This function must be called before enabling the PLLSAI.\r
+ * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .\r
+ * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.\r
+ * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__\r
+ */\r
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+/** @brief Macro to configure SAI1 clock source selection.\r
+ * @note This function must be called before enabling PLLSAI, PLLI2S and\r
+ * the SAI clock.\r
+ * @param __SOURCE__ specifies the SAI1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r
+ * used as SAI1 clock.\r
+ * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r
+ */\r
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))\r
+\r
+/** @brief Macro to get the SAI1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r
+ * as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI1 clock.\r
+ * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r
+ * used as SAI1 clock.\r
+ * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r
+ */\r
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))\r
+\r
+/** @brief Macro to configure SAI2 clock source selection.\r
+ * @note This function must be called before enabling PLLSAI, PLLI2S and\r
+ * the SAI clock.\r
+ * @param __SOURCE__ specifies the SAI2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r
+ * as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r
+ * as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r
+ * used as SAI2 clock.\r
+ * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r
+ */\r
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))\r
+\r
+\r
+/** @brief Macro to get the SAI2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r
+ * as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r
+ * as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r
+ * used as SAI2 clock.\r
+ * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r
+ * used as SAI2 clock.\r
+ * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r
+ */\r
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))\r
+\r
+\r
+/** @brief Enable PLLSAI_RDY interrupt.\r
+ */\r
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Disable PLLSAI_RDY interrupt.\r
+ */\r
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Clear the PLLSAI RDY interrupt pending bits.\r
+ */\r
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))\r
+\r
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.\r
+ * @retval The new state (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))\r
+\r
+/** @brief Check PLLSAI RDY flag is set or not.\r
+ * @retval The new state (TRUE or FALSE).\r
+ */\r
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))\r
+\r
+/** @brief Macro to Get I2S clock source selection.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.\r
+ * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source\r
+ */\r
+#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))\r
+\r
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).\r
+ *\r
+ * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the I2C1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r
+ * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))\r
+\r
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).\r
+ *\r
+ * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the I2C2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r
+ * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))\r
+\r
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).\r
+ *\r
+ * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))\r
+\r
+/** @brief macro to get the I2C3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))\r
+\r
+/** @brief Macro to configure the I2C4 clock (I2C4CLK).\r
+ *\r
+ * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))\r
+\r
+/** @brief macro to get the I2C4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r
+ * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r
+ */\r
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))\r
+\r
+/** @brief Macro to configure the USART1 clock (USART1CLK).\r
+ *\r
+ * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r
+ * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r
+ */\r
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))\r
+\r
+/** @brief Macro to configure the USART2 clock (USART2CLK).\r
+ *\r
+ * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r
+ * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r
+ */\r
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))\r
+\r
+/** @brief Macro to configure the USART3 clock (USART3CLK).\r
+ *\r
+ * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART3 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r
+ */\r
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))\r
+\r
+ /** @brief Macro to configure the UART4 clock (UART4CLK).\r
+ *\r
+ * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART4 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r
+ * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r
+ */\r
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))\r
+\r
+ /** @brief Macro to configure the UART5 clock (UART5CLK).\r
+ *\r
+ * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART5 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r
+ * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r
+ */\r
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))\r
+\r
+ /** @brief Macro to configure the USART6 clock (USART6CLK).\r
+ *\r
+ * @param __USART6_CLKSOURCE__ specifies the USART6 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))\r
+\r
+/** @brief macro to get the USART6 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r
+ * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r
+ */\r
+#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))\r
+\r
+ /** @brief Macro to configure the UART7 clock (UART7CLK).\r
+ *\r
+ * @param __UART7_CLKSOURCE__ specifies the UART7 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART7 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r
+ * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r
+ */\r
+#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))\r
+\r
+/** @brief Macro to configure the UART8 clock (UART8CLK).\r
+ *\r
+ * @param __UART8_CLKSOURCE__ specifies the UART8 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))\r
+\r
+/** @brief macro to get the UART8 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r
+ * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r
+ */\r
+#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))\r
+\r
+/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).\r
+ *\r
+ * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the LPTIM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r
+ */\r
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))\r
+\r
+/** @brief Macro to configure the CEC clock (CECCLK).\r
+ *\r
+ * @param __CEC_CLKSOURCE__ specifies the CEC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock\r
+ */\r
+#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))\r
+\r
+/** @brief macro to get the CEC clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r
+ * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock\r
+ */\r
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))\r
+\r
+/** @brief Macro to configure the CLK48 source (CLK48CLK).\r
+ *\r
+ * @param __CLK48_SOURCE__ specifies the CLK48 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source\r
+ * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source\r
+ */\r
+#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))\r
+\r
+/** @brief macro to get the CLK48 source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source\r
+ * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source\r
+ */\r
+#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))\r
+\r
+/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).\r
+ *\r
+ * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock\r
+ * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock\r
+ */\r
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))\r
+\r
+/** @brief macro to get the SDMMC1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock\r
+ * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock\r
+ */\r
+#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).\r
+ * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r
+ * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r
+ */\r
+#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))\r
+\r
+/** @brief macro to get the SDMMC2 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r
+ * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r
+ */\r
+#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/** @brief Macro to configure the DFSDM1 clock\r
+ * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock\r
+ * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock\r
+ */\r
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the DFSDM1 clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock\r
+ * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock\r
+ */\r
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))\r
+\r
+/** @brief Macro to configure the DFSDM1 Audio clock\r
+ * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock\r
+ */\r
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \\r
+ MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))\r
+\r
+/** @brief Macro to get the DFSDM1 Audio clock source.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock\r
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock\r
+ */\r
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F769xx) || defined (STM32F779xx)\r
+/** @brief Macro to configure the DSI clock.\r
+ * @param __DSI_CLKSOURCE__ specifies the DSI clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.\r
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.\r
+ */\r
+#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))\r
+\r
+/** @brief Macro to Get the DSI clock.\r
+ * @retval The clock source can be one of the following values:\r
+ * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.\r
+ * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.\r
+ */\r
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))\r
+#endif /* STM32F769xx || STM32F779xx */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Exported_Functions_Group1\r
+ * @{\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\r
+ * @{\r
+ */\r
+#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#elif defined(STM32F745xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#elif defined (STM32F765xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+#define IS_RCC_PERIPHCLOCK(SELECTION) \\r
+ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \\r
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))\r
+#endif /* STM32F746xx || STM32F756xx || STM32F750xx */\r
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\r
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\\r
+ ((VALUE) == RCC_PLLI2SP_DIV4) ||\\r
+ ((VALUE) == RCC_PLLI2SP_DIV6) ||\\r
+ ((VALUE) == RCC_PLLI2SP_DIV8))\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r
+\r
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\\r
+ ((VALUE) == RCC_PLLSAIP_DIV4) ||\\r
+ ((VALUE) == RCC_PLLSAIP_DIV6) ||\\r
+ ((VALUE) == RCC_PLLSAIP_DIV8))\r
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r
+\r
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r
+\r
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r
+\r
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_4) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_8) ||\\r
+ ((VALUE) == RCC_PLLSAIDIVR_16))\r
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))\r
+\r
+#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))\r
+\r
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))\r
+#define IS_RCC_USART1CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART2CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART2CLKSOURCE_HSI))\r
+#define IS_RCC_USART3CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART4CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART5CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_USART6CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_USART6CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART7CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART7CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_UART8CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \\r
+ ((SOURCE) == RCC_UART8CLKSOURCE_HSI))\r
+#define IS_RCC_I2C1CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))\r
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))\r
+\r
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))\r
+#define IS_RCC_I2C4CLKSOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \\r
+ ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))\r
+#define IS_RCC_LPTIM1CLK(SOURCE) \\r
+ (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \\r
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))\r
+#define IS_RCC_CLK48SOURCE(SOURCE) \\r
+ (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \\r
+ ((SOURCE) == RCC_CLK48SOURCE_PLL))\r
+#define IS_RCC_TIMPRES(VALUE) \\r
+ (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \\r
+ ((VALUE) == RCC_TIMPRES_ACTIVATED))\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\\r
+ defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx)\r
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))\r
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r
+\r
+#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \\r
+ ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))\r
+\r
+#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \\r
+ ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))\r
+\r
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \\r
+ ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))\r
+\r
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \\r
+ ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r
+#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \\r
+ ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r
+\r
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\\r
+ ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_RCC_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of TIM HAL module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32F7xx_HAL_TIM_H\r
+#define STM32F7xx_HAL_TIM_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Types TIM Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM Time base Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+ uint32_t ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_ClockDivision */\r
+\r
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.\r
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r
+\r
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.\r
+ This parameter can be a value of @ref TIM_AutoReloadPreload */\r
+} TIM_Base_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Output Compare Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.\r
+ This parameter can be a value of @ref TIM_Output_Fast_State\r
+ @note This parameter is valid only in PWM1 and PWM2 mode. */\r
+\r
+\r
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+} TIM_OC_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM One Pulse Mode Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+\r
+ uint32_t OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for timer instances supporting break feature. */\r
+\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_OnePulse_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Input Capture Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_IC_InitTypeDef;\r
+\r
+/**\r
+ * @brief TIM Encoder Configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Encoder_Mode */\r
+\r
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC1Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC2Selection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_Encoder_InitTypeDef;\r
+\r
+/**\r
+ * @brief Clock Configuration Handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClockSource; /*!< TIM clock sources\r
+ This parameter can be a value of @ref TIM_Clock_Source */\r
+ uint32_t ClockPolarity; /*!< TIM clock polarity\r
+ This parameter can be a value of @ref TIM_Clock_Polarity */\r
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler\r
+ This parameter can be a value of @ref TIM_Clock_Prescaler */\r
+ uint32_t ClockFilter; /*!< TIM clock filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClockConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Clear Input Configuration Handle Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t ClearInputState; /*!< TIM clear Input state\r
+ This parameter can be ENABLE or DISABLE */\r
+ uint32_t ClearInputSource; /*!< TIM clear Input sources\r
+ This parameter can be a value of @ref TIM_ClearInput_Source */\r
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity\r
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */\r
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler\r
+ This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+} TIM_ClearInputConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Master configuration Structure definition\r
+ * @note Advanced timers provide TRGO2 internal line which is redirected\r
+ * to the ADC\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection\r
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */\r
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection\r
+ This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */\r
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection\r
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */\r
+} TIM_MasterConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Slave configuration Structure definition\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t SlaveMode; /*!< Slave mode selection\r
+ This parameter can be a value of @ref TIM_Slave_Mode */\r
+ uint32_t InputTrigger; /*!< Input Trigger source\r
+ This parameter can be a value of @ref TIM_Trigger_Selection */\r
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity\r
+ This parameter can be a value of @ref TIM_Trigger_Polarity */\r
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler\r
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */\r
+ uint32_t TriggerFilter; /*!< Input trigger filter\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+} TIM_SlaveConfigTypeDef;\r
+\r
+/**\r
+ * @brief TIM Break input(s) and Dead time configuration Structure definition\r
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable\r
+ * filter and polarity.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode\r
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode\r
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r
+ uint32_t LockLevel; /*!< TIM Lock level\r
+ This parameter can be a value of @ref TIM_Lock_level */\r
+ uint32_t DeadTime; /*!< TIM dead Time\r
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r
+ uint32_t BreakState; /*!< TIM Break State\r
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r
+ uint32_t BreakPolarity; /*!< TIM Break input polarity\r
+ This parameter can be a value of @ref TIM_Break_Polarity */\r
+ uint32_t BreakFilter; /*!< Specifies the break input filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+ uint32_t Break2State; /*!< TIM Break2 State\r
+ This parameter can be a value of @ref TIM_Break2_Input_enable_disable */\r
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity\r
+ This parameter can be a value of @ref TIM_Break2_Polarity */\r
+ uint32_t Break2Filter; /*!< TIM break2 input filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state\r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BreakDeadTimeConfigTypeDef;\r
+\r
+/**\r
+ * @brief HAL State structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */\r
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */\r
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */\r
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */\r
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */\r
+} HAL_TIM_StateTypeDef;\r
+\r
+/**\r
+ * @brief HAL Active channel structures definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */\r
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */\r
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */\r
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */\r
+ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */\r
+ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */\r
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */\r
+} HAL_TIM_ActiveChannel;\r
+\r
+/**\r
+ * @brief TIM Time Base Handle Structure definition\r
+ */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+typedef struct __TIM_HandleTypeDef\r
+#else\r
+typedef struct\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+{\r
+ TIM_TypeDef *Instance; /*!< Register base address */\r
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */\r
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */\r
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array\r
+ This array is accessed by a @ref DMA_Handle_index */\r
+ HAL_LockTypeDef Lock; /*!< Locking object */\r
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */\r
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */\r
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */\r
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */\r
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */\r
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */\r
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */\r
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */\r
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */\r
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */\r
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */\r
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */\r
+ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */\r
+ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */\r
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */\r
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */\r
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */\r
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */\r
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */\r
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */\r
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */\r
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */\r
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */\r
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */\r
+ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */\r
+ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */\r
+ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */\r
+ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+} TIM_HandleTypeDef;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief HAL TIM Callback ID enumeration definition\r
+ */\r
+typedef enum\r
+{\r
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */\r
+ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */\r
+ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */\r
+ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */\r
+ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */\r
+ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */\r
+ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */\r
+ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */\r
+ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */\r
+ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */\r
+ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */\r
+ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */\r
+ ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */\r
+ ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */\r
+ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */\r
+ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */\r
+ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */\r
+ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */\r
+\r
+ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */\r
+ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */\r
+ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */\r
+ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */\r
+ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */\r
+ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */\r
+ ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */\r
+ ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */\r
+ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */\r
+ ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */\r
+} HAL_TIM_CallbackIDTypeDef;\r
+\r
+/**\r
+ * @brief HAL TIM Callback pointer definition\r
+ */\r
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */\r
+\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Constants TIM Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */\r
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address\r
+ * @{\r
+ */\r
+#define TIM_DMABASE_CR1 0x00000000U\r
+#define TIM_DMABASE_CR2 0x00000001U\r
+#define TIM_DMABASE_SMCR 0x00000002U\r
+#define TIM_DMABASE_DIER 0x00000003U\r
+#define TIM_DMABASE_SR 0x00000004U\r
+#define TIM_DMABASE_EGR 0x00000005U\r
+#define TIM_DMABASE_CCMR1 0x00000006U\r
+#define TIM_DMABASE_CCMR2 0x00000007U\r
+#define TIM_DMABASE_CCER 0x00000008U\r
+#define TIM_DMABASE_CNT 0x00000009U\r
+#define TIM_DMABASE_PSC 0x0000000AU\r
+#define TIM_DMABASE_ARR 0x0000000BU\r
+#define TIM_DMABASE_RCR 0x0000000CU\r
+#define TIM_DMABASE_CCR1 0x0000000DU\r
+#define TIM_DMABASE_CCR2 0x0000000EU\r
+#define TIM_DMABASE_CCR3 0x0000000FU\r
+#define TIM_DMABASE_CCR4 0x00000010U\r
+#define TIM_DMABASE_BDTR 0x00000011U\r
+#define TIM_DMABASE_DCR 0x00000012U\r
+#define TIM_DMABASE_DMAR 0x00000013U\r
+#define TIM_DMABASE_OR 0x00000014U\r
+#define TIM_DMABASE_CCMR3 0x00000015U\r
+#define TIM_DMABASE_CCR5 0x00000016U\r
+#define TIM_DMABASE_CCR6 0x00000017U\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+#define TIM_DMABASE_AF1 0x00000018U\r
+#define TIM_DMABASE_AF2 0x00000019U\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Event_Source TIM Event Source\r
+ * @{\r
+ */\r
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */\r
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */\r
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */\r
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */\r
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */\r
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */\r
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */\r
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */\r
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity\r
+ * @{\r
+ */\r
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */\r
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\r
+ * @{\r
+ */\r
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */\r
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */\r
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */\r
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */\r
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode TIM Counter Mode\r
+ * @{\r
+ */\r
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */\r
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */\r
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */\r
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */\r
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClockDivision TIM Clock Division\r
+ * @{\r
+ */\r
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */\r
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */\r
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */\r
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\r
+ * @{\r
+ */\r
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */\r
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State\r
+ * @{\r
+ */\r
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */\r
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r
+ * @{\r
+ */\r
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */\r
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity\r
+ * @{\r
+ */\r
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */\r
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r
+ * @{\r
+ */\r
+#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */\r
+#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State\r
+ * @{\r
+ */\r
+#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */\r
+#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State\r
+ * @{\r
+ */\r
+#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */\r
+#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity\r
+ * @{\r
+ */\r
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */\r
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */\r
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\r
+ * @{\r
+ */\r
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively */\r
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\r
+ * @{\r
+ */\r
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */\r
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */\r
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */\r
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r
+ * @{\r
+ */\r
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */\r
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r
+ * @{\r
+ */\r
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */\r
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */\r
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition\r
+ * @{\r
+ */\r
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */\r
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */\r
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */\r
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */\r
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */\r
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */\r
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */\r
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Commutation_Source TIM Commutation Source\r
+ * @{\r
+ */\r
+#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */\r
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_sources TIM DMA Sources\r
+ * @{\r
+ */\r
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */\r
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */\r
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */\r
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */\r
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */\r
+#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */\r
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Flag_definition TIM Flag Definition\r
+ * @{\r
+ */\r
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */\r
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */\r
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */\r
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */\r
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */\r
+#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */\r
+#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */\r
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */\r
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */\r
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */\r
+#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */\r
+#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */\r
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */\r
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */\r
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */\r
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Channel TIM Channel\r
+ * @{\r
+ */\r
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */\r
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */\r
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */\r
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */\r
+#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */\r
+#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */\r
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Source TIM Clock Source\r
+ * @{\r
+ */\r
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */\r
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */\r
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */\r
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */\r
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */\r
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */\r
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */\r
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */\r
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */\r
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */\r
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */\r
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */\r
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r
+ * @{\r
+ */\r
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\r
+ * @{\r
+ */\r
+#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */\r
+#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\r
+ * @{\r
+ */\r
+#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */\r
+#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Lock_level TIM Lock level\r
+ * @{\r
+ */\r
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */\r
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */\r
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */\r
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable\r
+ * @{\r
+ */\r
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */\r
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity\r
+ * @{\r
+ */\r
+#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */\r
+#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable\r
+ * @{\r
+ */\r
+#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */\r
+#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity\r
+ * @{\r
+ */\r
+#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */\r
+#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable\r
+ * @{\r
+ */\r
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */\r
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event \r
+ (if none of the break inputs BRK and BRK2 is active) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3\r
+ * @{\r
+ */\r
+#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r
+#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */\r
+#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */\r
+#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r
+ * @{\r
+ */\r
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */\r
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */\r
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */\r
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */\r
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */\r
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)\r
+ * @{\r
+ */\r
+#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */\r
+#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */\r
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode\r
+ * @{\r
+ */\r
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */\r
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Slave_Mode TIM Slave mode\r
+ * @{\r
+ */\r
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */\r
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */\r
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */\r
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */\r
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */\r
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes\r
+ * @{\r
+ */\r
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */\r
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */\r
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */\r
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */\r
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */\r
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */\r
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */\r
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */\r
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */\r
+#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */\r
+#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */\r
+#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */\r
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\r
+ * @{\r
+ */\r
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */\r
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */\r
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */\r
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */\r
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */\r
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */\r
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */\r
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */\r
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */\r
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */\r
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r
+ * @{\r
+ */\r
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */\r
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection\r
+ * @{\r
+ */\r
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */\r
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length\r
+ * @{\r
+ */\r
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Handle_index TIM DMA Handle Index\r
+ * @{\r
+ */\r
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */\r
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */\r
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State\r
+ * @{\r
+ */\r
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */\r
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */\r
+#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */\r
+#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Break_System TIM Break System\r
+ * @{\r
+ */\r
+#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */\r
+#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */\r
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */\r
+#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/** @defgroup TIM_Exported_Macros TIM Exported Macros\r
+ * @{\r
+ */\r
+\r
+/** @brief Reset TIM handle state.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval None\r
+ */\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \\r
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \\r
+ (__HANDLE__)->Base_MspInitCallback = NULL; \\r
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->IC_MspInitCallback = NULL; \\r
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->OC_MspInitCallback = NULL; \\r
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \\r
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \\r
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \\r
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \\r
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \\r
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \\r
+ } while(0)\r
+#else\r
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @brief Enable the TIM peripheral.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r
+\r
+/**\r
+ * @brief Enable the TIM main Output.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r
+\r
+/**\r
+ * @brief Disable the TIM peripheral.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE(__HANDLE__) \\r
+ do { \\r
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
+ { \\r
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
+ { \\r
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Disable the TIM main Output.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled\r
+ */\r
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\r
+ do { \\r
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\r
+ { \\r
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\r
+ { \\r
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\r
+ } \\r
+ } \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Disable the TIM main Output.\r
+ * @param __HANDLE__ TIM handle\r
+ * @retval None\r
+ * @note The Main Output Enable of a timer instance is disabled unconditionally\r
+ */\r
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)\r
+\r
+/** @brief Enable the specified TIM interrupt.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r
+\r
+/** @brief Disable the specified TIM interrupt.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r
+\r
+/** @brief Enable the specified DMA request.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __DMA__ specifies the TIM DMA request to enable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: Update DMA request\r
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
+ * @arg TIM_DMA_COM: Commutation DMA request\r
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))\r
+\r
+/** @brief Disable the specified DMA request.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __DMA__ specifies the TIM DMA request to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: Update DMA request\r
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request\r
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request\r
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request\r
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request\r
+ * @arg TIM_DMA_COM: Commutation DMA request\r
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r
+\r
+/** @brief Check whether the specified TIM interrupt flag is set or not.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __FLAG__ specifies the TIM interrupt flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
+ * @arg TIM_FLAG_COM: Commutation interrupt flag\r
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+ * @arg TIM_FLAG_BREAK: Break interrupt flag\r
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r
+\r
+/** @brief Clear the specified TIM interrupt flag.\r
+ * @param __HANDLE__ specifies the TIM Handle.\r
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag\r
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag\r
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag\r
+ * @arg TIM_FLAG_COM: Commutation interrupt flag\r
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r
+ * @arg TIM_FLAG_BREAK: Break interrupt flag\r
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag\r
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r
+ * @retval The new state of __FLAG__ (TRUE or FALSE).\r
+ */\r
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r
+\r
+/**\r
+ * @brief Check whether the specified TIM interrupt source is enabled or not.\r
+ * @param __HANDLE__ TIM handle\r
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval The state of TIM_IT (SET or RESET).\r
+ */\r
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r
+\r
+/** @brief Clear the TIM interrupt pending bits.\r
+ * @param __HANDLE__ TIM handle\r
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_UPDATE: Update interrupt\r
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt\r
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt\r
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt\r
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt\r
+ * @arg TIM_IT_COM: Commutation interrupt\r
+ * @arg TIM_IT_TRIGGER: Trigger interrupt\r
+ * @arg TIM_IT_BREAK: Break interrupt\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r
+\r
+/**\r
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\r
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder\r
+mode.\r
+ */\r
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r
+\r
+/**\r
+ * @brief Set the TIM Prescaler on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __PRESC__ specifies the Prescaler new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))\r
+\r
+/**\r
+ * @brief Set the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __COUNTER__ specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r
+\r
+/**\r
+ * @brief Get the TIM Counter Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)\r
+ */\r
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CNT)\r
+\r
+/**\r
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __AUTORELOAD__ specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \\r
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Autoreload Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)\r
+ */\r
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->ARR)\r
+\r
+/**\r
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CKD__ specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\r
+ do{ \\r
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \\r
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \\r
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Clock Division value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @retval The clock division can be one of the following values:\r
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r
+ */\r
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r
+\r
+/**\r
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+ do{ \\r
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\r
+ } while(0)\r
+\r
+/**\r
+ * @brief Get the TIM Input Capture prescaler on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r
+ * @retval The input capture prescaler can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ */\r
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\r
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)\r
+\r
+/**\r
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @param __COMPARE__ specifies the Capture Compare register new value.\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\r
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))\r
+\r
+/**\r
+ * @brief Get the TIM Capture Compare Register value on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value\r
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value\r
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value\r
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value\r
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value\r
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value\r
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)\r
+ */\r
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\r
+ ((__HANDLE__)->Instance->CCR6))\r
+\r
+/**\r
+ * @brief Set the TIM Output compare preload.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\\r
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))\r
+\r
+/**\r
+ * @brief Reset the TIM Output compare preload.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\\r
+ ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))\r
+\r
+/**\r
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter\r
+ * overflow/underflow generates an update interrupt or DMA request (if\r
+ * enabled)\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)\r
+\r
+/**\r
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the\r
+ * following events generate an update interrupt or DMA request (if\r
+ * enabled):\r
+ * _ Counter overflow underflow\r
+ * _ Setting the UG bit\r
+ * _ Update generation through the slave mode controller\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \\r
+ ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)\r
+\r
+/**\r
+ * @brief Set the TIM Capture x input polarity on runtime.\r
+ * @param __HANDLE__ TIM handle.\r
+ * @param __CHANNEL__ TIM Channels to be configured.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param __POLARITY__ Polarity for TIx source\r
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r
+ * @retval None\r
+ */\r
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+ do{ \\r
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \\r
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\r
+ }while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported macros ----------------------------------------------------*/\r
+\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Constants TIM Private Constants\r
+ * @{\r
+ */\r
+/* The counter of a timer instance is disabled only if all the CCx and CCxN\r
+ channels have been disabled */\r
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r
+/**\r
+ * @}\r
+ */\r
+/* End of private constants --------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Macros TIM Private Macros\r
+ * @{\r
+ */\r
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \\r
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))\r
+\r
+#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)\r
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CR2) || \\r
+ ((__BASE__) == TIM_DMABASE_SMCR) || \\r
+ ((__BASE__) == TIM_DMABASE_DIER) || \\r
+ ((__BASE__) == TIM_DMABASE_SR) || \\r
+ ((__BASE__) == TIM_DMABASE_EGR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCER) || \\r
+ ((__BASE__) == TIM_DMABASE_CNT) || \\r
+ ((__BASE__) == TIM_DMABASE_PSC) || \\r
+ ((__BASE__) == TIM_DMABASE_ARR) || \\r
+ ((__BASE__) == TIM_DMABASE_RCR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR4) || \\r
+ ((__BASE__) == TIM_DMABASE_BDTR) || \\r
+ ((__BASE__) == TIM_DMABASE_OR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR5) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR6) || \\r
+ ((__BASE__) == TIM_DMABASE_AF1) || \\r
+ ((__BASE__) == TIM_DMABASE_AF2))\r
+#else\r
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CR2) || \\r
+ ((__BASE__) == TIM_DMABASE_SMCR) || \\r
+ ((__BASE__) == TIM_DMABASE_DIER) || \\r
+ ((__BASE__) == TIM_DMABASE_SR) || \\r
+ ((__BASE__) == TIM_DMABASE_EGR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCER) || \\r
+ ((__BASE__) == TIM_DMABASE_CNT) || \\r
+ ((__BASE__) == TIM_DMABASE_PSC) || \\r
+ ((__BASE__) == TIM_DMABASE_ARR) || \\r
+ ((__BASE__) == TIM_DMABASE_RCR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR1) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR2) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR4) || \\r
+ ((__BASE__) == TIM_DMABASE_BDTR) || \\r
+ ((__BASE__) == TIM_DMABASE_OR) || \\r
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR5) || \\r
+ ((__BASE__) == TIM_DMABASE_CCR6))\r
+#endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */\r
+\r
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \\r
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r
+\r
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\r
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r
+\r
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\r
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\r
+\r
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \\r
+ ((__STATE__) == TIM_OCFAST_ENABLE))\r
+\r
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\r
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\r
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\r
+\r
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \\r
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))\r
+\r
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\r
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))\r
+\r
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\r
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))\r
+\r
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\r
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))\r
+\r
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \\r
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))\r
+\r
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \\r
+ ((__MODE__) == TIM_ENCODERMODE_TI12))\r
+\r
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r
+\r
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_6) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))\r
+\r
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))\r
+\r
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))\r
+\r
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \\r
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r
+\r
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \\r
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r
+\r
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\r
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r
+\r
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r
+\r
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \\r
+ ((__STATE__) == TIM_OSSR_DISABLE))\r
+\r
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \\r
+ ((__STATE__) == TIM_OSSI_DISABLE))\r
+\r
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \\r
+ ((__LEVEL__) == TIM_LOCKLEVEL_3))\r
+\r
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)\r
+\r
+\r
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \\r
+ ((__STATE__) == TIM_BREAK_DISABLE))\r
+\r
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\r
+\r
+#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \\r
+ ((__STATE__) == TIM_BREAK2_DISABLE))\r
+\r
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r
+\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\r
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\r
+\r
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))\r
+\r
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \\r
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \\r
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO_OC4REF))\r
+\r
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \\r
+ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \\r
+ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC1) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \\r
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r
+\r
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\r
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r
+\r
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \\r
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
+\r
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \\r
+ ((__MODE__) == TIM_OCMODE_PWM2) || \\r
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \\r
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \\r
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \\r
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))\r
+\r
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \\r
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \\r
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \\r
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\r
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r
+\r
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \\r
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \\r
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \\r
+ ((__SELECTION__) == TIM_TS_ETRF))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\r
+ ((__SELECTION__) == TIM_TS_ITR1) || \\r
+ ((__SELECTION__) == TIM_TS_ITR2) || \\r
+ ((__SELECTION__) == TIM_TS_ITR3) || \\r
+ ((__SELECTION__) == TIM_TS_NONE))\r
+\r
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \\r
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))\r
+\r
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\r
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))\r
+\r
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\r
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r
+\r
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\r
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r
+\r
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\r
+\r
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)\r
+\r
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \\r
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \\r
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \\r
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))\r
+\r
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \\r
+ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r
+\r
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\r
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))\r
+\r
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\r
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r
+\r
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\\r
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))\r
+\r
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\r
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\r
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private macros -----------------------------------------------------*/\r
+\r
+/* Include TIM HAL Extended module */\r
+#include "stm32f7xx_hal_tim_ex.h"\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+ * @brief Time Base functions\r
+ * @{\r
+ */\r
+/* Time Base functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+ * @brief TIM Output Compare functions\r
+ * @{\r
+ */\r
+/* Timer Output Compare functions *********************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+ * @brief TIM PWM functions\r
+ * @{\r
+ */\r
+/* Timer PWM functions ********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+ * @brief TIM Input Capture functions\r
+ * @{\r
+ */\r
+/* Timer Input Capture functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+ * @brief TIM One Pulse functions\r
+ * @{\r
+ */\r
+/* Timer One Pulse functions **************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+ * @brief TIM Encoder functions\r
+ * @{\r
+ */\r
+/* Timer Encoder functions ****************************************************/\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+ * @brief IRQ handler management\r
+ * @{\r
+ */\r
+/* Interrupt Handler functions ***********************************************/\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Control functions *********************************************************/\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
+ uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\r
+ uint32_t *BurstBuffer, uint32_t BurstLength);\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions\r
+ * @{\r
+ */\r
+/* Callback in non blocking modes (Interrupt and DMA) *************************/\r
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r
+\r
+/* Callbacks Register/UnRegister functions ***********************************/\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+ * @brief Peripheral State functions\r
+ * @{\r
+ */\r
+/* Peripheral State functions ************************************************/\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions----------------------------------------------------------*/\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+* @{\r
+*/\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r
+\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);\r
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+* @}\r
+*/\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* STM32F7xx_HAL_TIM_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim_ex.h\r
+ * @author MCD Application Team\r
+ * @brief Header file of TIM HAL Extended module.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef STM32F7xx_HAL_TIM_EX_H\r
+#define STM32F7xx_HAL_TIM_EX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal_def.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM Hall sensor Configuration Structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r
+\r
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\r
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r
+} TIM_HallSensor_InitTypeDef;\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+\r
+/**\r
+ * @brief TIM Break/Break2 input configuration\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t Source; /*!< Specifies the source of the timer break input.\r
+ This parameter can be a value of @ref TIMEx_Break_Input_Source */\r
+ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.\r
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */\r
+ uint32_t Polarity; /*!< Specifies the break input source polarity.\r
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity\r
+ Not relevant when analog watchdog output of the DFSDM1 used as break input source */\r
+}\r
+TIMEx_BreakInputConfigTypeDef;\r
+\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported types -----------------------------------------------------*/\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx_Remap TIM Extended Remapping\r
+ * @{\r
+ */\r
+#define TIM_TIM2_TIM8_TRGO (0x00000000U)\r
+#define TIM_TIM2_ETH_PTP (0x00000400U)\r
+#define TIM_TIM2_USBFS_SOF (0x00000800U)\r
+#define TIM_TIM2_USBHS_SOF (0x00000C00U)\r
+#define TIM_TIM5_GPIO (0x00000000U)\r
+#define TIM_TIM5_LSI (0x00000040U)\r
+#define TIM_TIM5_LSE (0x00000080U)\r
+#define TIM_TIM5_RTC (0x000000C0U)\r
+#define TIM_TIM11_GPIO (0x00000000U)\r
+#define TIM_TIM11_SPDIFRX (0x00000001U)\r
+#define TIM_TIM11_HSE (0x00000002U)\r
+#define TIM_TIM11_MCO1 (0x00000003U)\r
+/**\r
+ * @}\r
+ */\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+\r
+/** @defgroup TIMEx_Break_Input TIM Extended Break input\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */\r
+#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */\r
+#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */\r
+#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity\r
+ * @{\r
+ */\r
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */\r
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */\r
+/**\r
+ * @}\r
+ */\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported constants -------------------------------------------------*/\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported macro -----------------------------------------------------*/\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros\r
+ * @{\r
+ */\r
+#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\\r
+ ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\\r
+ ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_GPIO) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_LSI) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_LSE) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM5_RTC) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_GPIO) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_HSE) ||\\r
+ ((__TIM_REMAP__) == TIM_TIM11_MCO1))\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+\r
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \\r
+ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \\r
+ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \\r
+ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))\r
+\r
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \\r
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of private macro ------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+ * @brief Timer Hall Sensor functions\r
+ * @{\r
+ */\r
+/* Timer Hall Sensor functions **********************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);\r
+\r
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);\r
+\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+ * @brief Timer Complementary Output Compare functions\r
+ * @{\r
+ */\r
+/* Timer Complementary Output Compare functions *****************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+ * @brief Timer Complementary PWM functions\r
+ * @{\r
+ */\r
+/* Timer Complementary PWM functions ****************************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/* Non-Blocking mode: DMA */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+ * @brief Timer Complementary One Pulse functions\r
+ * @{\r
+ */\r
+/* Timer Complementary One Pulse functions **********************************/\r
+/* Blocking mode: Polling */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+\r
+/* Non-Blocking mode: Interrupt */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ * @{\r
+ */\r
+/* Extended Control functions ************************************************/\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);\r
+#endif /* TIM_BREAK_INPUT_SUPPORT */\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
+ * @brief Extended Callbacks functions\r
+ * @{\r
+ */\r
+/* Extended Callback **********************************************************/\r
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);\r
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
+ * @brief Extended Peripheral State functions\r
+ * @{\r
+ */\r
+/* Extended Peripheral State functions ***************************************/\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* End of exported functions -------------------------------------------------*/\r
+\r
+/* Private functions----------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions\r
+ * @{\r
+ */\r
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);\r
+/**\r
+ * @}\r
+ */\r
+/* End of private functions --------------------------------------------------*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* STM32F7xx_HAL_TIM_EX_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal.c\r
+ * @author MCD Application Team\r
+ * @brief HAL module driver.\r
+ * This is the common part of the HAL initialization\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The common HAL driver contains a set of generic and common APIs that can be\r
+ used by the PPP peripheral drivers and the user to start using the HAL. \r
+ [..]\r
+ The HAL contains two APIs' categories: \r
+ (+) Common HAL APIs\r
+ (+) Services HAL APIs\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL HAL\r
+ * @brief HAL module driver.\r
+ * @{\r
+ */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup HAL_Private_Constants\r
+ * @{\r
+ */\r
+/**\r
+ * @brief STM32F7xx HAL Driver version number V1.2.7\r
+ */\r
+#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\r
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */\r
+#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ \r
+#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\\r
+ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\\r
+ |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\\r
+ |(__STM32F7xx_HAL_VERSION_RC))\r
+ \r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Exported variables ---------------------------------------------------------*/\r
+/** @addtogroup HAL_Exported_Variables\r
+ * @{\r
+ */\r
+__IO uint32_t uwTick;\r
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */\r
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup HAL_Exported_Functions HAL Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions \r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Initialization and Configuration functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Initializes the Flash interface the NVIC allocation and initial clock \r
+ configuration. It initializes the systick also when timeout is needed \r
+ and the backup domain when enabled.\r
+ (+) De-Initializes common part of the HAL.\r
+ (+) Configure the time base source to have 1ms time base with a dedicated \r
+ Tick interrupt priority. \r
+ (++) SysTick timer is used by default as source of time base, but user\r
+ can eventually implement his proper time base source (a general purpose \r
+ timer for example or other time source), keeping in mind that Time base \r
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and \r
+ handled in milliseconds basis.\r
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically \r
+ at the beginning of the program after reset by HAL_Init() or at any time \r
+ when clock is configured, by HAL_RCC_ClockConfig(). \r
+ (++) Source of time base is configured to generate interrupts at regular \r
+ time intervals. Care must be taken if HAL_Delay() is called from a \r
+ peripheral ISR process, the Tick interrupt line must have higher priority \r
+ (numerically lower) than the peripheral interrupt. Otherwise the caller \r
+ ISR process will be blocked. \r
+ (++) functions affecting time base configurations are declared as __weak \r
+ to make override possible in case of other implementations in user file.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is used to initialize the HAL Library; it must be the first \r
+ * instruction to be executed in the main program (before to call any other\r
+ * HAL function), it performs the following:\r
+ * Configure the Flash prefetch, and instruction cache through ART accelerator.\r
+ * Configures the SysTick to generate an interrupt each 1 millisecond,\r
+ * which is clocked by the HSI (at this stage, the clock is not yet\r
+ * configured and thus the system is running from the internal HSI at 16 MHz).\r
+ * Set NVIC Group Priority to 4.\r
+ * Calls the HAL_MspInit() callback function defined in user file \r
+ * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization \r
+ * \r
+ * @note SysTick is used as time base for the HAL_Delay() function, the application\r
+ * need to ensure that the SysTick time base is always set to 1 millisecond\r
+ * to have correct HAL operation.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_Init(void)\r
+{\r
+ /* Configure Instruction cache through ART accelerator */ \r
+#if (ART_ACCLERATOR_ENABLE != 0)\r
+ __HAL_FLASH_ART_ENABLE();\r
+#endif /* ART_ACCLERATOR_ENABLE */\r
+\r
+ /* Configure Flash prefetch */\r
+#if (PREFETCH_ENABLE != 0U)\r
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\r
+#endif /* PREFETCH_ENABLE */\r
+\r
+ /* Set Interrupt Group Priority */\r
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r
+\r
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\r
+ HAL_InitTick(TICK_INT_PRIORITY);\r
+ \r
+ /* Init the low level hardware */\r
+ HAL_MspInit();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function de-Initializes common part of the HAL and stops the systick.\r
+ * This function is optional. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DeInit(void)\r
+{\r
+ /* Reset of all peripherals */\r
+ __HAL_RCC_APB1_FORCE_RESET();\r
+ __HAL_RCC_APB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_APB2_FORCE_RESET();\r
+ __HAL_RCC_APB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB1_FORCE_RESET();\r
+ __HAL_RCC_AHB1_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB2_FORCE_RESET();\r
+ __HAL_RCC_AHB2_RELEASE_RESET();\r
+\r
+ __HAL_RCC_AHB3_FORCE_RESET();\r
+ __HAL_RCC_AHB3_RELEASE_RESET();\r
+\r
+ /* De-Init the low level hardware */\r
+ HAL_MspDeInit();\r
+ \r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspInit(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the MSP.\r
+ * @retval None\r
+ */\r
+__weak void HAL_MspDeInit(void)\r
+{\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_MspDeInit could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief This function configures the source of the time base.\r
+ * The time source is configured to have 1ms time base with a dedicated \r
+ * Tick interrupt priority.\r
+ * @note This function is called automatically at the beginning of program after\r
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().\r
+ * @note In the default implementation, SysTick timer is the source of time base. \r
+ * It is used to generate interrupts at regular time intervals. \r
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process, \r
+ * The SysTick interrupt must have higher priority (numerically lower)\r
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r
+ * The function is declared as __weak to be overwritten in case of other\r
+ * implementation in user file.\r
+ * @param TickPriority Tick interrupt priority.\r
+ * @retval HAL status\r
+ */\r
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r
+{\r
+ /* Configure the SysTick to have interrupt in 1ms time basis*/\r
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Configure the SysTick IRQ priority */\r
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))\r
+ {\r
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\r
+ uwTickPrio = TickPriority;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions \r
+ * @brief HAL Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### HAL Control functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Provide a tick value in millisecond\r
+ (+) Provide a blocking delay in millisecond\r
+ (+) Suspend the time base source interrupt\r
+ (+) Resume the time base source interrupt\r
+ (+) Get the HAL API driver version\r
+ (+) Get the device identifier\r
+ (+) Get the device revision identifier\r
+ (+) Enable/Disable Debug module during SLEEP mode\r
+ (+) Enable/Disable Debug module during STOP mode\r
+ (+) Enable/Disable Debug module during STANDBY mode\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function is called to increment a global variable "uwTick"\r
+ * used as application time base.\r
+ * @note In the default implementation, this variable is incremented each 1ms\r
+ * in SysTick ISR.\r
+ * @note This function is declared as __weak to be overwritten in case of other \r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_IncTick(void)\r
+{\r
+ uwTick += uwTickFreq;\r
+}\r
+\r
+/**\r
+ * @brief Provides a tick value in millisecond.\r
+ * @note This function is declared as __weak to be overwritten in case of other \r
+ * implementations in user file.\r
+ * @retval tick value\r
+ */\r
+__weak uint32_t HAL_GetTick(void)\r
+{\r
+ return uwTick;\r
+}\r
+\r
+/**\r
+ * @brief This function returns a tick priority.\r
+ * @retval tick priority\r
+ */\r
+uint32_t HAL_GetTickPrio(void)\r
+{\r
+ return uwTickPrio;\r
+}\r
+\r
+/**\r
+ * @brief Set new tick Freq.\r
+ * @retval Status\r
+ */\r
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ assert_param(IS_TICKFREQ(Freq));\r
+\r
+ if (uwTickFreq != Freq)\r
+ {\r
+ uwTickFreq = Freq;\r
+\r
+ /* Apply the new tick Freq */\r
+ status = HAL_InitTick(uwTickPrio);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Return tick frequency.\r
+ * @retval tick period in Hz\r
+ */\r
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)\r
+{\r
+ return uwTickFreq;\r
+}\r
+\r
+/**\r
+ * @brief This function provides minimum delay (in milliseconds) based\r
+ * on variable incremented.\r
+ * @note In the default implementation , SysTick timer is the source of time base.\r
+ * It is used to generate interrupts at regular time intervals where uwTick\r
+ * is incremented.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @param Delay specifies the delay time length, in milliseconds.\r
+ * @retval None\r
+ */\r
+__weak void HAL_Delay(uint32_t Delay)\r
+{\r
+ uint32_t tickstart = HAL_GetTick();\r
+ uint32_t wait = Delay;\r
+\r
+ /* Add a freq to guarantee minimum wait */\r
+ if (wait < HAL_MAX_DELAY)\r
+ {\r
+ wait += (uint32_t)(uwTickFreq);\r
+ }\r
+\r
+ while ((HAL_GetTick() - tickstart) < wait)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Suspend Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r
+ * is called, the SysTick interrupt will be disabled and so Tick increment \r
+ * is suspended.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SuspendTick(void)\r
+{\r
+ /* Disable SysTick Interrupt */\r
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Resume Tick increment.\r
+ * @note In the default implementation , SysTick timer is the source of time base. It is\r
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r
+ * is called, the SysTick interrupt will be enabled and so Tick increment \r
+ * is resumed.\r
+ * @note This function is declared as __weak to be overwritten in case of other\r
+ * implementations in user file.\r
+ * @retval None\r
+ */\r
+__weak void HAL_ResumeTick(void)\r
+{\r
+ /* Enable SysTick Interrupt */\r
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HAL revision\r
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r
+ */\r
+uint32_t HAL_GetHalVersion(void)\r
+{\r
+ return __STM32F7xx_HAL_VERSION;\r
+}\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t HAL_GetREVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) >> 16U);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetDEVID(void)\r
+{\r
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Returns first word of the unique device identifier (UID based on 96 bits)\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetUIDw0(void)\r
+{\r
+ return(READ_REG(*((uint32_t *)UID_BASE)));\r
+}\r
+\r
+/**\r
+ * @brief Returns second word of the unique device identifier (UID based on 96 bits)\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetUIDw1(void)\r
+{\r
+ return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));\r
+}\r
+\r
+/**\r
+ * @brief Returns third word of the unique device identifier (UID based on 96 bits)\r
+ * @retval Device identifier\r
+ */\r
+uint32_t HAL_GetUIDw2(void)\r
+{\r
+ return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGSleepMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during SLEEP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGSleepMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGStopMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STOP mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGStopMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r
+}\r
+\r
+/**\r
+ * @brief Enable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_EnableDBGStandbyMode(void)\r
+{\r
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @brief Disable the Debug Module during STANDBY mode\r
+ * @retval None\r
+ */\r
+void HAL_DBGMCU_DisableDBGStandbyMode(void)\r
+{\r
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r
+}\r
+\r
+/**\r
+ * @brief Enables the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V. \r
+ * @retval None\r
+ */\r
+void HAL_EnableCompensationCell(void)\r
+{\r
+ SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;\r
+}\r
+\r
+/**\r
+ * @brief Power-down the I/O Compensation Cell.\r
+ * @note The I/O compensation cell can be used only when the device supply\r
+ * voltage ranges from 2.4 to 3.6 V. \r
+ * @retval None\r
+ */\r
+void HAL_DisableCompensationCell(void)\r
+{\r
+ SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);\r
+}\r
+\r
+/**\r
+ * @brief Enables the FMC Memory Mapping Swapping.\r
+ * \r
+ * @note SDRAM is accessible at 0x60000000 \r
+ * and NOR/RAM is accessible at 0xC0000000 \r
+ *\r
+ * @retval None\r
+ */\r
+void HAL_EnableFMCMemorySwapping(void)\r
+{\r
+ SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;\r
+}\r
+\r
+/**\r
+ * @brief Disables the FMC Memory Mapping Swapping\r
+ * \r
+ * @note SDRAM is accessible at 0xC0000000 (default mapping) \r
+ * and NOR/RAM is accessible at 0x60000000 (default mapping) \r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_DisableFMCMemorySwapping(void)\r
+{\r
+\r
+ SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);\r
+}\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+/**\r
+* @brief Enable the Internal FLASH Bank Swapping.\r
+* \r
+* @note This function can be used only for STM32F77xx/STM32F76xx devices. \r
+*\r
+* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r
+* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) \r
+*\r
+* @retval None\r
+*/\r
+void HAL_EnableMemorySwappingBank(void)\r
+{\r
+ SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r
+}\r
+\r
+/**\r
+* @brief Disable the Internal FLASH Bank Swapping.\r
+* \r
+* @note This function can be used only for STM32F77xx/STM32F76xx devices. \r
+*\r
+* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r
+* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) \r
+* \r
+* @retval None\r
+*/\r
+void HAL_DisableMemorySwappingBank(void)\r
+{\r
+ CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r
+}\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_cortex.c\r
+ * @author MCD Application Team\r
+ * @brief CORTEX HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the CORTEX:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ *\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+\r
+ [..] \r
+ *** How to configure Interrupts using CORTEX HAL driver ***\r
+ ===========================================================\r
+ [..] \r
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).\r
+ The Cortex-M4 exceptions are managed by CMSIS functions.\r
+ \r
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\r
+ function according to the following table.\r
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). \r
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r
+ (#) please refer to programming manual for details in how to configure priority. \r
+ \r
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. \r
+ The pending IRQ priority will be managed only by the sub priority.\r
+ \r
+ -@- IRQ priority order (sorted by highest to lowest priority):\r
+ (+@) Lowest preemption priority\r
+ (+@) Lowest sub priority\r
+ (+@) Lowest hardware priority (IRQ number)\r
+ \r
+ [..] \r
+ *** How to configure Systick using CORTEX HAL driver ***\r
+ ========================================================\r
+ [..]\r
+ Setup SysTick Timer for time base.\r
+ \r
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r
+ is a CMSIS function that:\r
+ (++) Configures the SysTick Reload register with value passed as function parameter.\r
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r
+ (++) Resets the SysTick Counter register.\r
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r
+ (++) Enables the SysTick Interrupt.\r
+ (++) Starts the SysTick Counter.\r
+ \r
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r
+ inside the stm32f7xx_hal_cortex.h file.\r
+\r
+ (+) You can change the SysTick IRQ priority by calling the\r
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \r
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r
+\r
+ (+) To adjust the SysTick time base, use the following formula:\r
+ \r
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)\r
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r
+ (++) Reload Value should not exceed 0xFFFFFF\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CORTEX CORTEX\r
+ * @brief CORTEX HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r
+ Systick functionalities \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Sets the priority grouping field (preemption priority and subpriority)\r
+ * using the required unlock sequence.\r
+ * @param PriorityGroup The priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. \r
+ * The pending IRQ priority will be managed only by the subpriority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r
+ NVIC_SetPriorityGrouping(PriorityGroup);\r
+}\r
+\r
+/**\r
+ * @brief Sets the priority of an interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @param PreemptPriority The preemption priority for the IRQn channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority \r
+ * @param SubPriority the subpriority level for the IRQ channel.\r
+ * This parameter can be a value between 0 and 15\r
+ * A lower priority value indicates a higher priority. \r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{ \r
+ uint32_t prioritygroup = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r
+ \r
+ prioritygroup = NVIC_GetPriorityGrouping();\r
+ \r
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r
+}\r
+\r
+/**\r
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.\r
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r
+ * function should be called before. \r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Enable interrupt */\r
+ NVIC_EnableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Disable interrupt */\r
+ NVIC_DisableIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Initiates a system reset request to reset the MCU.\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SystemReset(void)\r
+{\r
+ /* System Reset */\r
+ NVIC_SystemReset();\r
+}\r
+\r
+/**\r
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ * Counter is in free running mode to generate periodic interrupts.\r
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.\r
+ * @retval status: - 0 Function succeeded.\r
+ * - 1 Function failed.\r
+ */\r
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r
+{\r
+ return SysTick_Config(TicksNumb);\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief Cortex control functions \r
+ *\r
+@verbatim \r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the CORTEX\r
+ (NVIC, SYSTICK, MPU) functionalities. \r
+ \r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/**\r
+ * @brief Disables the MPU\r
+ * @retval None\r
+ */\r
+void HAL_MPU_Disable(void)\r
+{\r
+ /* Make sure outstanding transfers are done */\r
+ __DMB();\r
+\r
+ /* Disable fault exceptions */\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+ \r
+ /* Disable the MPU and clear the control register*/\r
+ MPU->CTRL = 0;\r
+}\r
+\r
+/**\r
+ * @brief Enables the MPU\r
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault, \r
+ * NMI, FAULTMASK and privileged access to the default memory \r
+ * This parameter can be one of the following values:\r
+ * @arg MPU_HFNMI_PRIVDEF_NONE\r
+ * @arg MPU_HARDFAULT_NMI\r
+ * @arg MPU_PRIVILEGED_DEFAULT\r
+ * @arg MPU_HFNMI_PRIVDEF\r
+ * @retval None\r
+ */\r
+void HAL_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ /* Enable the MPU */\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+ \r
+ /* Enable fault exceptions */\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+ \r
+ /* Ensure MPU setting take effects */\r
+ __DSB();\r
+ __ISB();\r
+}\r
+\r
+/**\r
+ * @brief Initializes and configures the Region and the memory to be protected.\r
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains\r
+ * the initialization and configuration information.\r
+ * @retval None\r
+ */\r
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r
+\r
+ /* Set the Region number */\r
+ MPU->RNR = MPU_Init->Number;\r
+\r
+ if ((MPU_Init->Enable) != RESET)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r
+ \r
+ MPU->RBAR = MPU_Init->BaseAddress;\r
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |\r
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |\r
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |\r
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |\r
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |\r
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |\r
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |\r
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |\r
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);\r
+ }\r
+ else\r
+ {\r
+ MPU->RBAR = 0x00;\r
+ MPU->RASR = 0x00;\r
+ }\r
+}\r
+#endif /* __MPU_PRESENT */\r
+\r
+/**\r
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.\r
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r
+ */\r
+uint32_t HAL_NVIC_GetPriorityGrouping(void)\r
+{\r
+ /* Get the PRIGROUP[10:8] field value */\r
+ return NVIC_GetPriorityGrouping();\r
+}\r
+\r
+/**\r
+ * @brief Gets the priority of an interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @param PriorityGroup the priority grouping bits length.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r
+ * 0 bits for subpriority\r
+ * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).\r
+ * @param pSubPriority Pointer on the Subpriority value (starting from 0).\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r
+ /* Get priority for Cortex-M system or device specific interrupts */\r
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r
+}\r
+\r
+/**\r
+ * @brief Sets Pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Set interrupt pending */\r
+ NVIC_SetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC \r
+ * and returns the pending bit for the specified interrupt).\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Return 1 if pending else 0 */\r
+ return NVIC_GetPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Clears the pending bit of an external interrupt.\r
+ * @param IRQn External interrupt number.\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval None\r
+ */\r
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Clear pending interrupt */\r
+ NVIC_ClearPendingIRQ(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r
+ * @param IRQn External interrupt number\r
+ * This parameter can be an enumerator of IRQn_Type enumeration\r
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r
+ * @retval status: - 0 Interrupt status is not pending.\r
+ * - 1 Interrupt status is pending.\r
+ */\r
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r
+ \r
+ /* Return 1 if active else 0 */\r
+ return NVIC_GetActive(IRQn);\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param CLKSource specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r
+ {\r
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles SYSTICK interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_SYSTICK_IRQHandler(void)\r
+{\r
+ HAL_SYSTICK_Callback();\r
+}\r
+\r
+/**\r
+ * @brief SYSTICK callback.\r
+ * @retval None\r
+ */\r
+__weak void HAL_SYSTICK_Callback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_SYSTICK_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma.c\r
+ * @author MCD Application Team\r
+ * @brief DMA HAL module driver.\r
+ * \r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Direct Memory Access (DMA) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and errors functions\r
+ @verbatim \r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Enable and configure the peripheral to be connected to the DMA Stream\r
+ (except for internal SRAM/FLASH memories: no initialization is \r
+ necessary) please refer to Reference manual for connection between peripherals\r
+ and DMA requests.\r
+\r
+ (#) For a given Stream, program the required configuration through the following parameters:\r
+ Transfer Direction, Source and Destination data formats, \r
+ Circular, Normal or peripheral flow control mode, Stream Priority level, \r
+ Source and Destination Increment mode, FIFO mode and its Threshold (if needed), \r
+ Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.\r
+\r
+ -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:\r
+ __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source \r
+ address and destination address and the Length of data to be transferred.\r
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this \r
+ case a fixed Timeout can be configured by User depending from his application.\r
+ (+) Use HAL_DMA_Abort() function to abort the current transfer.\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()\r
+ (+) Select Callbacks functions using HAL_DMA_RegisterCallback()\r
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of \r
+ Source address and destination address and the Length of data to be transferred. In this \r
+ case the DMA interrupt is configured \r
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can \r
+ add his own function by customization of function pointer XferCpltCallback and \r
+ XferErrorCallback (i.e a member of DMA handle structure).\r
+ [..]\r
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error \r
+ detection.\r
+\r
+ (#) Use HAL_DMA_Abort_IT() function to abort the current transfer\r
+\r
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.\r
+\r
+ -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\r
+ possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\r
+ Half-Word data size for the peripheral to access its data register and set Word data size\r
+ for the Memory to gain in access time. Each two half words will be packed and written in\r
+ a single access to a Word in the Memory).\r
+\r
+ -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\r
+ and Destination. In this case the Peripheral Data Size will be applied to both Source\r
+ and Destination.\r
+\r
+ *** DMA HAL driver macros list ***\r
+ =============================================\r
+ [..]\r
+ Below the list of most used macros in DMA HAL driver.\r
+ \r
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.\r
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.\r
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. \r
+\r
+ [..]\r
+ (@) You can refer to the DMA HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA DMA\r
+ * @brief DMA HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< DMA interrupt status register */\r
+ __IO uint32_t Reserved0;\r
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */\r
+} DMA_Base_Registers;\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private constants ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Constants\r
+ * @{\r
+ */\r
+ #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+/** @addtogroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group1\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to initialize the DMA Stream source\r
+ and destination addresses, incrementation and data sizes, transfer direction, \r
+ circular/normal mode selection, memory-to-memory mode selection and Stream priority value.\r
+ [..]\r
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r
+ reference manual.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @brief Initialize the DMA according to the specified\r
+ * parameters in the DMA_InitTypeDef and create the associated handle.\r
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmp = 0U;\r
+ uint32_t tickstart = HAL_GetTick();\r
+ DMA_Base_Registers *regs;\r
+\r
+ /* Check the DMA peripheral state */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\r
+ assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));\r
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));\r
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r
+ assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));\r
+ /* Check the memory burst, peripheral burst and FIFO threshold parameters only\r
+ when FIFO mode is enabled */\r
+ if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)\r
+ {\r
+ assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));\r
+ assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));\r
+ assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));\r
+ }\r
+ \r
+ /* Allocate lock resource */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Disable the peripheral */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ \r
+ /* Check if the DMA Stream is effectively disabled */\r
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Get the CR register value */\r
+ tmp = hdma->Instance->CR;\r
+\r
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */\r
+ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\r
+ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \\r
+ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \\r
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));\r
+\r
+ /* Prepare the DMA Stream configuration */\r
+ tmp |= hdma->Init.Channel | hdma->Init.Direction |\r
+ hdma->Init.PeriphInc | hdma->Init.MemInc |\r
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r
+ hdma->Init.Mode | hdma->Init.Priority;\r
+\r
+ /* the Memory burst and peripheral burst are not used when the FIFO is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get memory burst and peripheral burst */\r
+ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;\r
+ }\r
+ \r
+ /* Write to DMA Stream CR register */\r
+ hdma->Instance->CR = tmp; \r
+\r
+ /* Get the FCR register value */\r
+ tmp = hdma->Instance->FCR;\r
+\r
+ /* Clear Direct mode and FIFO threshold bits */\r
+ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\r
+\r
+ /* Prepare the DMA Stream FIFO configuration */\r
+ tmp |= hdma->Init.FIFOMode;\r
+\r
+ /* The FIFO threshold is not used when the FIFO mode is disabled */\r
+ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r
+ {\r
+ /* Get the FIFO threshold */\r
+ tmp |= hdma->Init.FIFOThreshold;\r
+ \r
+ /* Check compatibility between FIFO threshold level and size of the memory burst */\r
+ /* for INCR4, INCR8, INCR16 bursts */\r
+ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)\r
+ {\r
+ if (DMA_CheckFifoParam(hdma) != HAL_OK)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ \r
+ return HAL_ERROR; \r
+ }\r
+ }\r
+ }\r
+ \r
+ /* Write to DMA Stream FCR */\r
+ hdma->Instance->FCR = tmp;\r
+\r
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate\r
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */\r
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+ \r
+ /* Clear all interrupt flags */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+\r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+ \r
+ /* Initialize the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the DMA peripheral \r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r
+{\r
+ DMA_Base_Registers *regs;\r
+\r
+ /* Check the DMA peripheral state */\r
+ if(hdma == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check the DMA peripheral state */\r
+ if(hdma->State == HAL_DMA_STATE_BUSY)\r
+ {\r
+ /* Return error status */\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\r
+\r
+ /* Disable the selected DMA Streamx */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ /* Reset DMA Streamx control register */\r
+ hdma->Instance->CR = 0U;\r
+\r
+ /* Reset DMA Streamx number of data to transfer register */\r
+ hdma->Instance->NDTR = 0U;\r
+\r
+ /* Reset DMA Streamx peripheral address register */\r
+ hdma->Instance->PAR = 0U;\r
+\r
+ /* Reset DMA Streamx memory 0 address register */\r
+ hdma->Instance->M0AR = 0U;\r
+ \r
+ /* Reset DMA Streamx memory 1 address register */\r
+ hdma->Instance->M1AR = 0U;\r
+ \r
+ /* Reset DMA Streamx FIFO control register */\r
+ hdma->Instance->FCR = (uint32_t)0x00000021U;\r
+ \r
+ /* Get DMA steam Base Address */ \r
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r
+ \r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+ \r
+ /* Clean all callbacks */\r
+ hdma->XferCpltCallback = NULL;\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ hdma->XferM1CpltCallback = NULL;\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ hdma->XferErrorCallback = NULL;\r
+ hdma->XferAbortCallback = NULL; \r
+\r
+ /* Reset the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+\r
+ /* Reset the DMA state */\r
+ hdma->State = HAL_DMA_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group2\r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and Start DMA transfer\r
+ (+) Configure the source, destination address and data length and \r
+ Start DMA transfer with interrupt\r
+ (+) Abort DMA transfer\r
+ (+) Poll for transfer complete\r
+ (+) Handle DMA interrupt request \r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the DMA Transfer.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ } \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Start the DMA Transfer with interrupt enabled.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+ \r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+ \r
+ /* Enable Common interrupts*/\r
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r
+ hdma->Instance->FCR |= DMA_IT_FE;\r
+ \r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ hdma->Instance->CR |= DMA_IT_HT;\r
+ }\r
+ \r
+ /* Enable the Peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma); \r
+ \r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * \r
+ * @note After disabling a DMA Stream, a check for wait until the DMA Stream is \r
+ * effectively disabled is added. If a Stream is disabled \r
+ * while a data transfer is ongoing, the current data will be transferred\r
+ * and the Stream will be effectively disabled only after the transfer of\r
+ * this single data is finished. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r
+{\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ \r
+ uint32_t tickstart = HAL_GetTick();\r
+ \r
+ if(hdma->State != HAL_DMA_STATE_BUSY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Disable all the transfer interrupts */\r
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r
+ hdma->Instance->FCR &= ~(DMA_IT_FE);\r
+ \r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ hdma->Instance->CR &= ~(DMA_IT_HT);\r
+ }\r
+ \r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ \r
+ /* Check if the DMA Stream is effectively disabled */\r
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_TIMEOUT;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state*/\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Aborts the DMA Transfer in Interrupt mode.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r
+{\r
+ if(hdma->State != HAL_DMA_STATE_BUSY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Set Abort State */\r
+ hdma->State = HAL_DMA_STATE_ABORT;\r
+ \r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Polling for transfer complete.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CompleteLevel Specifies the DMA level complete.\r
+ * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.\r
+ * This model could be used for debug purpose.\r
+ * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). \r
+ * @param Timeout Timeout duration.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK; \r
+ uint32_t mask_cpltlevel;\r
+ uint32_t tickstart = HAL_GetTick(); \r
+ uint32_t tmpisr;\r
+ \r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs;\r
+\r
+ if(HAL_DMA_STATE_BUSY != hdma->State)\r
+ {\r
+ /* No transfer ongoing */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r
+ __HAL_UNLOCK(hdma);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Polling mode not supported in circular mode and double buffering mode */\r
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Transfer Complete flag */\r
+ mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r
+ }\r
+ else\r
+ {\r
+ /* Half Transfer Complete flag */\r
+ mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r
+ }\r
+ \r
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+ tmpisr = regs->ISR;\r
+ \r
+ while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))\r
+ {\r
+ /* Check for the Timeout (Not applicable in circular mode)*/\r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ \r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get the ISR register value */\r
+ tmpisr = regs->ISR;\r
+\r
+ if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+ \r
+ /* Clear the transfer error flag */\r
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r
+ }\r
+ \r
+ if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+ \r
+ /* Clear the FIFO error flag */\r
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r
+ }\r
+ \r
+ if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+ \r
+ /* Clear the Direct Mode error flag */\r
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r
+ }\r
+ }\r
+ \r
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r
+ {\r
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r
+ {\r
+ HAL_DMA_Abort(hdma);\r
+ \r
+ /* Clear the half transfer and transfer complete flags */\r
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State= HAL_DMA_STATE_READY;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ \r
+ /* Get the level transfer complete flag */\r
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r
+ {\r
+ /* Clear the half transfer and transfer complete flags */\r
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r
+ \r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the half transfer flag */\r
+ regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Handles DMA interrupt request.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval None\r
+ */\r
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t tmpisr;\r
+ __IO uint32_t count = 0;\r
+ uint32_t timeout = SystemCoreClock / 9600;\r
+\r
+ /* calculate DMA base and stream number */\r
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r
+\r
+ tmpisr = regs->ISR;\r
+\r
+ /* Transfer Error Interrupt management ***************************************/\r
+ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)\r
+ {\r
+ /* Disable the transfer error interrupt */\r
+ hdma->Instance->CR &= ~(DMA_IT_TE);\r
+ \r
+ /* Clear the transfer error flag */\r
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r
+ \r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r
+ }\r
+ }\r
+ /* FIFO Error Interrupt management ******************************************/\r
+ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)\r
+ {\r
+ /* Clear the FIFO error flag */\r
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r
+ }\r
+ }\r
+ /* Direct Mode Error Interrupt management ***********************************/\r
+ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)\r
+ {\r
+ /* Clear the direct mode error flag */\r
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r
+\r
+ /* Update error code */\r
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r
+ }\r
+ }\r
+ /* Half Transfer Complete Interrupt management ******************************/\r
+ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)\r
+ {\r
+ /* Clear the half transfer complete flag */\r
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r
+ \r
+ /* Multi_Buffering mode enabled */\r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r
+ {\r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferM1HalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferM1HalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r
+ {\r
+ /* Disable the half transfer interrupt */\r
+ hdma->Instance->CR &= ~(DMA_IT_HT);\r
+ }\r
+ \r
+ if(hdma->XferHalfCpltCallback != NULL)\r
+ {\r
+ /* Half transfer callback */\r
+ hdma->XferHalfCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Transfer Complete Interrupt management ***********************************/\r
+ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)\r
+ {\r
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)\r
+ {\r
+ /* Clear the transfer complete flag */\r
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r
+ \r
+ if(HAL_DMA_STATE_ABORT == hdma->State)\r
+ {\r
+ /* Disable all the transfer interrupts */\r
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r
+ hdma->Instance->FCR &= ~(DMA_IT_FE);\r
+ \r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ hdma->Instance->CR &= ~(DMA_IT_HT);\r
+ }\r
+\r
+ /* Clear all interrupt flags at correct offset within the register */\r
+ regs->IFCR = 0x3FU << hdma->StreamIndex;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+\r
+ if(hdma->XferAbortCallback != NULL)\r
+ {\r
+ hdma->XferAbortCallback(hdma);\r
+ }\r
+ return;\r
+ }\r
+\r
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r
+ {\r
+ /* Current memory buffer used is Memory 0 */\r
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r
+ {\r
+ if(hdma->XferM1CpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory1 */\r
+ hdma->XferM1CpltCallback(hdma);\r
+ }\r
+ }\r
+ /* Current memory buffer used is Memory 1 */\r
+ else\r
+ {\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete Callback for memory0 */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r
+ else\r
+ {\r
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r
+ {\r
+ /* Disable the transfer complete interrupt */\r
+ hdma->Instance->CR &= ~(DMA_IT_TC);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+\r
+ if(hdma->XferCpltCallback != NULL)\r
+ {\r
+ /* Transfer complete callback */\r
+ hdma->XferCpltCallback(hdma);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ \r
+ /* manage error case */\r
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r
+ {\r
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r
+ {\r
+ hdma->State = HAL_DMA_STATE_ABORT;\r
+\r
+ /* Disable the stream */\r
+ __HAL_DMA_DISABLE(hdma);\r
+\r
+ do\r
+ {\r
+ if (++count > timeout)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hdma);\r
+\r
+ /* Change the DMA state */\r
+ hdma->State = HAL_DMA_STATE_READY;\r
+ }\r
+\r
+ if(hdma->XferErrorCallback != NULL)\r
+ {\r
+ /* Transfer error callback */\r
+ hdma->XferErrorCallback(hdma);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Register callbacks\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CallbackID User Callback identifer\r
+ * a DMA_HandleTypeDef structure as parameter.\r
+ * @param pCallback pointer to private callbacsk function which has pointer to \r
+ * a DMA_HandleTypeDef structure as parameter.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))\r
+{\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+\r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_M1CPLT_CB_ID:\r
+ hdma->XferM1CpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r
+ hdma->XferM1HalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = pCallback;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief UnRegister callbacks\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param CallbackID User Callback identifer\r
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r
+ * @retval HAL status\r
+ */ \r
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_DMA_XFER_CPLT_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_M1CPLT_CB_ID:\r
+ hdma->XferM1CpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_ERROR_CB_ID:\r
+ hdma->XferErrorCallback = NULL;\r
+ break;\r
+ \r
+ case HAL_DMA_XFER_ABORT_CB_ID:\r
+ hdma->XferAbortCallback = NULL;\r
+ break; \r
+ \r
+ case HAL_DMA_XFER_ALL_CB_ID:\r
+ hdma->XferCpltCallback = NULL;\r
+ hdma->XferHalfCpltCallback = NULL;\r
+ hdma->XferM1CpltCallback = NULL;\r
+ hdma->XferM1HalfCpltCallback = NULL;\r
+ hdma->XferErrorCallback = NULL;\r
+ hdma->XferAbortCallback = NULL;\r
+ break; \r
+ \r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ \r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hdma);\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Exported_Functions_Group3\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### State and Errors functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides functions allowing to\r
+ (+) Check the DMA state\r
+ (+) Get error code\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the DMA state.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval HAL state\r
+ */\r
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the DMA error code\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @retval DMA Error Code\r
+ */\r
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r
+{\r
+ return hdma->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Sets the DMA Transfer parameter.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream.\r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Clear DBM bit */\r
+ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);\r
+\r
+ /* Configure DMA Stream data length */\r
+ hdma->Instance->NDTR = DataLength;\r
+\r
+ /* Memory to Peripheral */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->PAR = DstAddress;\r
+\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->M0AR = SrcAddress;\r
+ }\r
+ /* Peripheral to Memory */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->PAR = SrcAddress;\r
+\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M0AR = DstAddress;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the DMA Stream base address depending on stream number\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval Stream base address\r
+ */\r
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;\r
+ \r
+ /* lookup table for necessary bitshift of flags within status registers */\r
+ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};\r
+ hdma->StreamIndex = flagBitshiftOffset[stream_number];\r
+ \r
+ if (stream_number > 3U)\r
+ {\r
+ /* return pointer to HISR and HIFCR */\r
+ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);\r
+ }\r
+ else\r
+ {\r
+ /* return pointer to LISR and LIFCR */\r
+ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));\r
+ }\r
+ \r
+ return hdma->StreamBaseAddress;\r
+}\r
+\r
+/**\r
+ * @brief Check compatibility between FIFO threshold level and size of the memory burst\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ uint32_t tmp = hdma->Init.FIFOThreshold;\r
+ \r
+ /* Memory Data size equal to Byte */\r
+ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)\r
+ {\r
+ switch (tmp)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Memory Data size equal to Half-Word */\r
+ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r
+ {\r
+ switch (tmp)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ status = HAL_ERROR;\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break; \r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Memory Data size equal to Word */\r
+ else\r
+ {\r
+ switch (tmp)\r
+ {\r
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r
+ case DMA_FIFO_THRESHOLD_HALFFULL:\r
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r
+ status = HAL_ERROR;\r
+ break;\r
+ case DMA_FIFO_THRESHOLD_FULL:\r
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ } \r
+ \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_dma_ex.c\r
+ * @author MCD Application Team\r
+ * @brief DMA Extension HAL module driver\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the DMA Extension peripheral:\r
+ * + Extended features functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The DMA Extension HAL driver can be used as follows:\r
+ (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\r
+ for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\r
+\r
+ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r
+ -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r
+ -@- In Multi (Double) buffer mode, it is possible to update the base address for \r
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMAEx DMAEx\r
+ * @brief DMA Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+\r
+/* Private types -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup DMAEx_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/** @addtogroup DMAEx_Exported_Functions_Group1\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ =============================================================================== \r
+ [..] This section provides functions allowing to:\r
+ (+) Configure the source, destination address and data length and \r
+ Start MultiBuffer DMA transfer\r
+ (+) Configure the source, destination address and data length and \r
+ Start MultiBuffer DMA transfer with interrupt\r
+ (+) Change on the fly the memory0 or memory1 address.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer \r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ \r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ status = HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY; \r
+ \r
+ /* Enable the double buffer mode */\r
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M1AR = SecondMemAddress;\r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r
+ \r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma);\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer \r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r
+ \r
+ /* Memory-to-memory transfer not supported in double buffering mode */\r
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r
+ {\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Process locked */\r
+ __HAL_LOCK(hdma);\r
+ \r
+ if(HAL_DMA_STATE_READY == hdma->State)\r
+ {\r
+ /* Change DMA peripheral state */\r
+ hdma->State = HAL_DMA_STATE_BUSY;\r
+ \r
+ /* Initialize the error code */\r
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r
+ \r
+ /* Enable the Double buffer mode */\r
+ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M1AR = SecondMemAddress;\r
+ \r
+ /* Configure the source, destination address and the data length */\r
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); \r
+ \r
+ /* Clear all flags */\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r
+ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r
+ \r
+ /* Enable Common interrupts*/\r
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r
+ hdma->Instance->FCR |= DMA_IT_FE;\r
+ \r
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r
+ {\r
+ hdma->Instance->CR |= DMA_IT_HT;\r
+ }\r
+ \r
+ /* Enable the peripheral */\r
+ __HAL_DMA_ENABLE(hdma); \r
+ }\r
+ else\r
+ { \r
+ /* Process unlocked */\r
+ __HAL_UNLOCK(hdma); \r
+ \r
+ /* Return error status */\r
+ status = HAL_BUSY;\r
+ } \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Change the memory0 or memory1 address on the fly.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param Address The new address\r
+ * @param memory the memory to be changed, This parameter can be one of \r
+ * the following values:\r
+ * MEMORY0 /\r
+ * MEMORY1\r
+ * @note The MEMORY0 address can be changed only when the current transfer use\r
+ * MEMORY1 and the MEMORY1 address can be changed only when the current \r
+ * transfer use MEMORY0.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\r
+{\r
+ if(memory == MEMORY0)\r
+ {\r
+ /* change the memory0 address */\r
+ hdma->Instance->M0AR = Address;\r
+ }\r
+ else\r
+ {\r
+ /* change the memory1 address */\r
+ hdma->Instance->M1AR = Address;\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup DMAEx_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set the DMA Transfer parameter.\r
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains\r
+ * the configuration information for the specified DMA Stream. \r
+ * @param SrcAddress The source memory Buffer address\r
+ * @param DstAddress The destination memory Buffer address\r
+ * @param DataLength The length of data to be transferred from source to destination\r
+ * @retval HAL status\r
+ */\r
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r
+{\r
+ /* Configure DMA Stream data length */\r
+ hdma->Instance->NDTR = DataLength;\r
+ \r
+ /* Peripheral to Memory */\r
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r
+ {\r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->PAR = DstAddress;\r
+ \r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->M0AR = SrcAddress;\r
+ }\r
+ /* Memory to Peripheral */\r
+ else\r
+ {\r
+ /* Configure DMA Stream source address */\r
+ hdma->Instance->PAR = SrcAddress;\r
+ \r
+ /* Configure DMA Stream destination address */\r
+ hdma->Instance->M0AR = DstAddress;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32F7xx_hal_exti.c\r
+ * @author MCD Application Team\r
+ * @brief EXTI HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Extended Interrupts and events controller (EXTI) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### EXTI Peripheral features #####\r
+ ==============================================================================\r
+ [..]\r
+ (+) Each Exti line can be configured within this driver.\r
+\r
+ (+) Exti line can be configured in 3 different modes\r
+ (++) Interrupt\r
+ (++) Event\r
+ (++) Both of them\r
+\r
+ (+) Configurable Exti lines can be configured with 3 different triggers\r
+ (++) Rising\r
+ (++) Falling\r
+ (++) Both of them\r
+\r
+ (+) When set in interrupt mode, configurable Exti lines have two different\r
+ interrupts pending registers which allow to distinguish which transition\r
+ occurs:\r
+ (++) Rising edge pending interrupt\r
+ (++) Falling\r
+\r
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can\r
+ be selected through multiplexer.\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+\r
+ (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().\r
+ (++) Choose the interrupt line number by setting "Line" member from\r
+ EXTI_ConfigTypeDef structure.\r
+ (++) Configure the interrupt and/or event mode using "Mode" member from\r
+ EXTI_ConfigTypeDef structure.\r
+ (++) For configurable lines, configure rising and/or falling trigger\r
+ "Trigger" member from EXTI_ConfigTypeDef structure.\r
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"\r
+ member from GPIO_InitTypeDef structure.\r
+\r
+ (#) Get current Exti configuration of a dedicated line using\r
+ HAL_EXTI_GetConfigLine().\r
+ (++) Provide exiting handle as parameter.\r
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.\r
+\r
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().\r
+ (++) Provide exiting handle as parameter.\r
+\r
+ (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().\r
+ (++) Provide exiting handle as first parameter.\r
+ (++) Provide which callback will be registered using one value from\r
+ EXTI_CallbackIDTypeDef.\r
+ (++) Provide callback function pointer.\r
+\r
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().\r
+\r
+ (#) Clear interrupt pending bit using HAL_EXTI_GetPending().\r
+\r
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2018 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+#include "stm32f7xx_hal_exti.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+/** MISRA C:2012 deviation rule has been granted for following rule:\r
+ * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out\r
+ * of bounds [0,3] in following API :\r
+ * HAL_EXTI_SetConfigLine\r
+ * HAL_EXTI_GetConfigLine\r
+ * HAL_EXTI_ClearConfigLine\r
+ */\r
+\r
+#ifdef HAL_EXTI_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private defines ------------------------------------------------------------*/\r
+/** @defgroup EXTI_Private_Constants EXTI Private Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup EXTI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI_Exported_Functions_Group1\r
+ * @brief Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Configuration functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Set configuration of a dedicated Exti line.\r
+ * @param hexti Exti handle.\r
+ * @param pExtiConfig Pointer on EXTI configuration to be set.\r
+ * @retval HAL Status.\r
+ */\r
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\r
+{\r
+ uint32_t regval;\r
+\r
+ /* Check null pointer */\r
+ if ((hexti == NULL) || (pExtiConfig == NULL))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));\r
+ assert_param(IS_EXTI_MODE(pExtiConfig->Mode));\r
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); \r
+ \r
+ /* Assign line number to handle */\r
+ hexti->Line = pExtiConfig->Line;\r
+ \r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~pExtiConfig->Line;\r
+ EXTI->EMR &= ~pExtiConfig->Line;\r
+ \r
+ /* Select the Mode for the selected external interrupts */\r
+ regval = (uint32_t)EXTI_BASE;\r
+ regval += pExtiConfig->Mode;\r
+ *(__IO uint32_t *) regval |= pExtiConfig->Line;\r
+ \r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~pExtiConfig->Line;\r
+ EXTI->FTSR &= ~pExtiConfig->Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= pExtiConfig->Line;\r
+ EXTI->FTSR |= pExtiConfig->Line;\r
+ }\r
+ else\r
+ {\r
+ regval = (uint32_t)EXTI_BASE;\r
+ regval += pExtiConfig->Trigger;\r
+ *(__IO uint32_t *) regval |= pExtiConfig->Line;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get configuration of a dedicated Exti line.\r
+ * @param hexti Exti handle.\r
+ * @param pExtiConfig Pointer on structure to store Exti configuration.\r
+ * @retval HAL Status.\r
+ */\r
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\r
+{\r
+ /* Check null pointer */\r
+ if ((hexti == NULL) || (pExtiConfig == NULL))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_EXTI_LINE(hexti->Line));\r
+\r
+ /* Store handle line number to configuration structure */\r
+ pExtiConfig->Line = hexti->Line;\r
+\r
+ /* Get EXTI mode to configiguration structure */\r
+ if ((EXTI->IMR & hexti->Line) == hexti->Line)\r
+ {\r
+ pExtiConfig->Mode = EXTI_MODE_INTERRUPT;\r
+ }\r
+ else if ((EXTI->EMR & hexti->Line) == hexti->Line)\r
+ {\r
+ pExtiConfig->Mode = EXTI_MODE_EVENT;\r
+ }\r
+ else\r
+ {\r
+ /* No MODE selected */\r
+ pExtiConfig->Mode = 0x0Bu;\r
+ }\r
+\r
+ /* Get EXTI Trigger to configiguration structure */\r
+ if ((EXTI->RTSR & hexti->Line) == hexti->Line)\r
+ {\r
+ if ((EXTI->FTSR & hexti->Line) == hexti->Line)\r
+ {\r
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;\r
+ }\r
+ else\r
+ {\r
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;\r
+ }\r
+ }\r
+ else if ((EXTI->FTSR & hexti->Line) == hexti->Line)\r
+ {\r
+ pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;\r
+ }\r
+ else\r
+ {\r
+ /* No Trigger selected */\r
+ pExtiConfig->Trigger = 0x00u;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Clear whole configuration of a dedicated Exti line.\r
+ * @param hexti Exti handle.\r
+ * @retval HAL Status.\r
+ */\r
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)\r
+{\r
+ /* Check null pointer */\r
+ if (hexti == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_EXTI_LINE(hexti->Line));\r
+\r
+ /* 1] Clear interrupt mode */\r
+ EXTI->IMR = (EXTI->IMR & ~hexti->Line);\r
+\r
+ /* 2] Clear event mode */\r
+ EXTI->EMR = (EXTI->EMR & ~hexti->Line);\r
+\r
+ /* 3] Clear triggers */\r
+ EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);\r
+ EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Register callback for a dedicated Exti line.\r
+ * @param hexti Exti handle.\r
+ * @param CallbackID User callback identifier.\r
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.\r
+ * @param pPendingCbfn function pointer to be stored as callback.\r
+ * @retval HAL Status.\r
+ */\r
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_EXTI_COMMON_CB_ID:\r
+ hexti->PendingCallback = pPendingCbfn;\r
+ break;\r
+\r
+ default:\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Store line number as handle private field.\r
+ * @param hexti Exti handle.\r
+ * @param ExtiLine Exti line number.\r
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.\r
+ * @retval HAL Status.\r
+ */\r
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(ExtiLine));\r
+\r
+ /* Check null pointer */\r
+ if (hexti == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* Store line number as handle private field */\r
+ hexti->Line = ExtiLine;\r
+\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup EXTI_Exported_Functions_Group2\r
+ * @brief EXTI IO functions.\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Handle EXTI interrupt request.\r
+ * @param hexti Exti handle.\r
+ * @retval none.\r
+ */\r
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)\r
+{\r
+ __IO uint32_t *regaddr;\r
+ uint32_t regval;\r
+\r
+ /* Get pending bit */\r
+ regaddr = (&EXTI->PR);\r
+ regval = (*regaddr & hexti->Line);\r
+\r
+ if (regval != 0x00u)\r
+ {\r
+ /* Clear pending bit */\r
+ *regaddr = hexti->Line;\r
+\r
+ /* Call callback */\r
+ if (hexti->PendingCallback != NULL)\r
+ {\r
+ hexti->PendingCallback();\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Get interrupt pending bit of a dedicated line.\r
+ * @param hexti Exti handle.\r
+ * @param Edge Specify which pending edge as to be checked.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING\r
+ * This parameter is kept for compatibility with other series.\r
+ * @retval 1 if interrupt is pending else 0.\r
+ */\r
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\r
+{\r
+ __IO uint32_t *regaddr;\r
+ uint32_t regval;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_EXTI_LINE(hexti->Line));\r
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));\r
+\r
+ /* Get pending bit */\r
+ regaddr = &EXTI->PR;\r
+\r
+ /* return 1 if bit is set else 0 */\r
+ regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));\r
+\r
+ return regval;\r
+}\r
+\r
+/**\r
+ * @brief Clear interrupt pending bit of a dedicated line.\r
+ * @param hexti Exti handle.\r
+ * @param Edge Specify which pending edge as to be clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING\r
+ * This parameter is kept for compatibility with other series.\r
+ * @retval None.\r
+ */\r
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_EXTI_LINE(hexti->Line));\r
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));\r
+ \r
+ /* Clear Pending bit */\r
+ EXTI->PR = hexti->Line;\r
+}\r
+\r
+/**\r
+ * @brief Generate a software interrupt for a dedicated line.\r
+ * @param hexti Exti handle.\r
+ * @retval None.\r
+ */\r
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_EXTI_LINE(hexti->Line));\r
+\r
+ EXTI->SWIER = hexti->Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_EXTI_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash.c\r
+ * @author MCD Application Team\r
+ * @brief FLASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the internal FLASH memory:\r
+ * + Program operations functions\r
+ * + Memory Control functions \r
+ * + Peripheral Errors functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### FLASH peripheral features #####\r
+ ==============================================================================\r
+ \r
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \r
+ to the Flash memory. It implements the erase and program Flash memory operations \r
+ and the read and write protection mechanisms.\r
+ \r
+ [..] The Flash memory interface accelerates code execution with a system of instruction\r
+ prefetch and cache lines. \r
+\r
+ [..] The FLASH main features are:\r
+ (+) Flash memory read operations\r
+ (+) Flash memory program/erase operations\r
+ (+) Read / write protections\r
+ (+) Prefetch on I-Code\r
+ (+) 64 cache lines of 128 bits on I-Code\r
+ (+) 8 cache lines of 128 bits on D-Code\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] \r
+ This driver provides functions and macros to configure and program the FLASH \r
+ memory of all STM32F7xx devices.\r
+ \r
+ (#) FLASH Memory IO Programming functions: \r
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r
+ HAL_FLASH_Lock() functions\r
+ (++) Program functions: byte, half word, word and double word\r
+ (++) There Two modes of programming :\r
+ (+++) Polling mode using HAL_FLASH_Program() function\r
+ (+++) Interrupt mode using HAL_FLASH_Program_IT() function\r
+ \r
+ (#) Interrupts and flags management functions : \r
+ (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\r
+ (++) Wait for last FLASH operation according to its status\r
+ (++) Get error flag status by calling HAL_SetErrorCode() \r
+ [..] \r
+ In addition to these functions, this driver includes a set of macros allowing\r
+ to handle the following operations:\r
+ (+) Set the latency\r
+ (+) Enable/Disable the prefetch buffer\r
+ (+) Enable/Disable the Instruction cache and the Data cache\r
+ (+) Reset the Instruction cache and the Data cache\r
+ (+) Enable/Disable the FLASH interrupts\r
+ (+) Monitor the FLASH flags status\r
+ [..] \r
+ (@) For any Flash memory program operation (erase or program), the CPU clock frequency\r
+ (HCLK) must be at least 1MHz. \r
+ (@) The contents of the Flash memory are not guaranteed if a device reset occurs during \r
+ a Flash memory operation.\r
+ (@) Any attempt to read the Flash memory while it is being written or erased, causes the \r
+ bus to stall. Read operations are processed correctly once the program operation has \r
+ completed. This means that code or data fetches cannot be performed while a write/erase \r
+ operation is ongoing.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH FLASH\r
+ * @brief FLASH HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Constants\r
+ * @{\r
+ */\r
+#define SECTOR_MASK ((uint32_t)0xFFFFFF07U)\r
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */\r
+/**\r
+ * @}\r
+ */ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+/* Variable used for Erase sectors under interruption */\r
+FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+/* Program operations */\r
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\r
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data);\r
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);\r
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);\r
+static void FLASH_SetErrorCode(void);\r
+\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \r
+ * @brief Programming operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Programming operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the FLASH \r
+ program operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Program byte, halfword, word or double word at a specified address\r
+ * @param TypeProgram Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address specifies the address to be programmed.\r
+ * @param Data specifies the data to be programmed\r
+ * \r
+ * @retval HAL_StatusTypeDef HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ switch(TypeProgram)\r
+ {\r
+ case FLASH_TYPEPROGRAM_BYTE :\r
+ {\r
+ /*Program byte (8-bit) at a specified address.*/\r
+ FLASH_Program_Byte(Address, (uint8_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_HALFWORD :\r
+ {\r
+ /*Program halfword (16-bit) at a specified address.*/\r
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_WORD :\r
+ {\r
+ /*Program word (32-bit) at a specified address.*/\r
+ FLASH_Program_Word(Address, (uint32_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_DOUBLEWORD :\r
+ {\r
+ /*Program double word (64-bit) at a specified address.*/\r
+ FLASH_Program_DoubleWord(Address, Data);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the program operation is completed, disable the PG Bit */\r
+ FLASH->CR &= (~FLASH_CR_PG);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.\r
+ * @param TypeProgram Indicate the way to program at a specified address.\r
+ * This parameter can be a value of @ref FLASH_Type_Program\r
+ * @param Address specifies the address to be programmed.\r
+ * @param Data specifies the data to be programmed\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r
+\r
+ /* Enable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r
+ \r
+ /* Enable Error source interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r
+ \r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\r
+ FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); \r
+\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r
+ pFlash.Address = Address;\r
+ \r
+ switch(TypeProgram)\r
+ {\r
+ case FLASH_TYPEPROGRAM_BYTE :\r
+ {\r
+ /*Program byte (8-bit) at a specified address.*/\r
+ FLASH_Program_Byte(Address, (uint8_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_HALFWORD :\r
+ {\r
+ /*Program halfword (16-bit) at a specified address.*/\r
+ FLASH_Program_HalfWord(Address, (uint16_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_WORD :\r
+ {\r
+ /*Program word (32-bit) at a specified address.*/\r
+ FLASH_Program_Word(Address, (uint32_t) Data);\r
+ break;\r
+ }\r
+ \r
+ case FLASH_TYPEPROGRAM_DOUBLEWORD :\r
+ {\r
+ /*Program double word (64-bit) at a specified address.*/\r
+ FLASH_Program_DoubleWord(Address, Data);\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief This function handles FLASH interrupt request.\r
+ * @retval None\r
+ */\r
+void HAL_FLASH_IRQHandler(void)\r
+{\r
+ uint32_t temp = 0;\r
+ \r
+ /* If the program operation is completed, disable the PG Bit */\r
+ FLASH->CR &= (~FLASH_CR_PG);\r
+\r
+ /* If the erase operation is completed, disable the SER Bit */\r
+ FLASH->CR &= (~FLASH_CR_SER);\r
+ FLASH->CR &= SECTOR_MASK; \r
+\r
+ /* if the erase operation is completed, disable the MER Bit */\r
+ FLASH->CR &= (~FLASH_MER_BIT);\r
+\r
+ /* Check FLASH End of Operation flag */\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\r
+ {\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ \r
+ switch (pFlash.ProcedureOnGoing)\r
+ {\r
+ case FLASH_PROC_SECTERASE :\r
+ {\r
+ /* Nb of sector to erased can be decreased */\r
+ pFlash.NbSectorsToErase--;\r
+\r
+ /* Check if there are still sectors to erase */\r
+ if(pFlash.NbSectorsToErase != 0)\r
+ {\r
+ temp = pFlash.Sector;\r
+ /* Indicate user which sector has been erased */\r
+ HAL_FLASH_EndOfOperationCallback(temp);\r
+\r
+ /* Increment sector number */\r
+ temp = ++pFlash.Sector;\r
+ FLASH_Erase_Sector(temp, pFlash.VoltageForErase);\r
+ }\r
+ else\r
+ {\r
+ /* No more sectors to Erase, user callback can be called.*/\r
+ /* Reset Sector and stop Erase sectors procedure */\r
+ pFlash.Sector = temp = 0xFFFFFFFFU;\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(temp);\r
+ /* Sector Erase procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ }\r
+ break;\r
+ }\r
+ \r
+ case FLASH_PROC_MASSERASE :\r
+ {\r
+ /* MassErase ended. Return the selected bank : in this product we don't have Banks */\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(0);\r
+ /* MAss Erase procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ break;\r
+ }\r
+\r
+ case FLASH_PROC_PROGRAM :\r
+ {\r
+ /*Program ended. Return the selected address*/\r
+ /* FLASH EOP interrupt user callback */\r
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r
+ /* Programming procedure is completed */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ }\r
+ \r
+ /* Check FLASH operation error flags */\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)\r
+ {\r
+ switch (pFlash.ProcedureOnGoing)\r
+ {\r
+ case FLASH_PROC_SECTERASE :\r
+ {\r
+ /* return the faulty sector */\r
+ temp = pFlash.Sector;\r
+ pFlash.Sector = 0xFFFFFFFFU;\r
+ break;\r
+ }\r
+ case FLASH_PROC_MASSERASE :\r
+ {\r
+ /* No return in case of Mass Erase */\r
+ temp = 0;\r
+ break;\r
+ }\r
+ case FLASH_PROC_PROGRAM :\r
+ {\r
+ /*return the faulty address*/\r
+ temp = pFlash.Address;\r
+ break;\r
+ }\r
+ default :\r
+ break;\r
+ }\r
+ /*Save the Error code*/\r
+ FLASH_SetErrorCode();\r
+\r
+ /* FLASH error interrupt user callback */\r
+ HAL_FLASH_OperationErrorCallback(temp);\r
+\r
+ /*Stop the procedure ongoing */\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r
+ }\r
+ \r
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r
+ {\r
+ /* Disable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);\r
+\r
+ /* Disable Error source interrupt */\r
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+ }\r
+ \r
+}\r
+\r
+/**\r
+ * @brief FLASH end of operation interrupt callback\r
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure\r
+ * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r
+ * all the selected sectors have been erased)\r
+ * - Program : Address which was selected for data program\r
+ * - Mass Erase : No return value expected\r
+ * @retval None\r
+ */\r
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(ReturnValue);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief FLASH operation error interrupt callback\r
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure\r
+ * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r
+ * all the selected sectors have been erased)\r
+ * - Program : Address which was selected for data program\r
+ * - Mass Erase : No return value expected\r
+ * @retval None\r
+ */\r
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(ReturnValue);\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief management functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to control the FLASH \r
+ memory operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlock the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\r
+ {\r
+ /* Authorize the FLASH Registers access */\r
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);\r
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);\r
+\r
+ /* Verify Flash is unlocked */\r
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\r
+ {\r
+ status = HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Locks the FLASH control register access\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_Lock(void)\r
+{\r
+ /* Set the LOCK Bit to lock the FLASH Registers access */\r
+ FLASH->CR |= FLASH_CR_LOCK;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Unlock the FLASH Option Control Registers access.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r
+{\r
+ if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)\r
+ {\r
+ /* Authorizes the Option Byte register programming */\r
+ FLASH->OPTKEYR = FLASH_OPT_KEY1;\r
+ FLASH->OPTKEYR = FLASH_OPT_KEY2;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ } \r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Lock the FLASH Option Control Registers access.\r
+ * @retval HAL Status \r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r
+{\r
+ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r
+ FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;\r
+ \r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Launch the option byte loading.\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r
+{\r
+ /* Set the OPTSTRT bit in OPTCR register */\r
+ FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;\r
+\r
+ /* Wait for last operation to be completed */\r
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); \r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions \r
+ * @brief Peripheral Errors functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Peripheral Errors functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection permits to get in run-time Errors of the FLASH peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Get the specific FLASH error flag.\r
+ * @retval FLASH_ErrorCode: The returned value can be:\r
+ * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag \r
+ * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag \r
+ * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag\r
+ * @arg FLASH_ERROR_WRP: FLASH Write protected error flag\r
+ * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag \r
+ */\r
+uint32_t HAL_FLASH_GetError(void)\r
+{ \r
+ return pFlash.ErrorCode;\r
+} \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @brief Wait for a FLASH operation to complete.\r
+ * @param Timeout maximum flash operationtimeout\r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Clear Error Code */\r
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r
+ \r
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error\r
+ flag will be set */\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) \r
+ { \r
+ if(Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)\r
+ {\r
+ /*Save the error code*/\r
+ FLASH_SetErrorCode();\r
+ return HAL_ERROR;\r
+ }\r
+ \r
+ /* Check FLASH End of Operation flag */\r
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\r
+ {\r
+ /* Clear FLASH End of Operation pending bit */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r
+ }\r
+\r
+ /* If there is an error flag set */\r
+ return HAL_OK;\r
+ \r
+} \r
+\r
+/**\r
+ * @brief Program a double word (64-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V and an External Vpp is present.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address specifies the address to be programmed.\r
+ * @param Data specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ /* Program the double-word */\r
+ *(__IO uint32_t*)Address = (uint32_t)Data;\r
+ *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);\r
+\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+\r
+/**\r
+ * @brief Program word (32-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address specifies the address to be programmed.\r
+ * @param Data specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint32_t*)Address = Data;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Program a half-word (16-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address specifies the address to be programmed.\r
+ * @param Data specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_HALF_WORD;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint16_t*)Address = Data;\r
+\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Program byte (8-bit) at a specified address.\r
+ * @note This function must be used when the device voltage range is from\r
+ * 2.7V to 3.6V.\r
+ *\r
+ * @note If an erase and a program operations are requested simultaneously, \r
+ * the erase operation is performed before the program one.\r
+ * \r
+ * @param Address specifies the address to be programmed.\r
+ * @param Data specifies the data to be programmed.\r
+ * @retval None\r
+ */\r
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+ \r
+ /* If the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_PSIZE_BYTE;\r
+ FLASH->CR |= FLASH_CR_PG;\r
+\r
+ *(__IO uint8_t*)Address = Data;\r
+\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Set the specific FLASH error flag.\r
+ * @retval None\r
+ */\r
+static void FLASH_SetErrorCode(void)\r
+{\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;\r
+ }\r
+ \r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)\r
+ {\r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;\r
+ }\r
+ \r
+#if defined (FLASH_OPTCR2_PCROP)\r
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)\r
+ { \r
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;\r
+ } \r
+#endif /* FLASH_OPTCR2_PCROP */\r
+ \r
+ /* Clear error programming flags */\r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_flash_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended FLASH HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the FLASH extension peripheral:\r
+ * + Extended programming operations functions\r
+ * \r
+ @verbatim\r
+ ==============================================================================\r
+ ##### Flash Extension features #####\r
+ ==============================================================================\r
+ \r
+ [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx \r
+ devices contains the following additional features \r
+ \r
+ (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\r
+ capability (RWW)\r
+ (+) Dual bank memory organization \r
+ (+) Dual boot mode\r
+ \r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to configure and program the FLASH memory \r
+ of all STM32F7xx devices. It includes\r
+ (#) FLASH Memory Erase functions: \r
+ (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r
+ HAL_FLASH_Lock() functions\r
+ (++) Erase function: Erase sector, erase all sectors\r
+ (++) There are two modes of erase :\r
+ (+++) Polling Mode using HAL_FLASHEx_Erase()\r
+ (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\r
+ \r
+ (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :\r
+ (++) Set/Reset the write protection\r
+ (++) Set the Read protection Level\r
+ (++) Set the BOR level\r
+ (++) Program the user Option Bytes\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx FLASHEx\r
+ * @brief FLASH HAL Extension module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Constants\r
+ * @{\r
+ */ \r
+#define SECTOR_MASK 0xFFFFFF07U\r
+#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Variables\r
+ * @{\r
+ */ \r
+extern FLASH_ProcessTypeDef pFlash;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup FLASHEx_Private_Functions\r
+ * @{\r
+ */\r
+/* Option bytes control */\r
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);\r
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);\r
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);\r
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);\r
+static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);\r
+static uint32_t FLASH_OB_GetUser(void);\r
+static uint32_t FLASH_OB_GetWRP(void);\r
+static uint8_t FLASH_OB_GetRDP(void);\r
+static uint32_t FLASH_OB_GetBOR(void);\r
+static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\r
+ uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);\r
+#else\r
+static void FLASH_MassErase(uint8_t VoltageRange);\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector);\r
+static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp);\r
+static uint32_t FLASH_OB_GetPCROP(void);\r
+static uint32_t FLASH_OB_GetPCROPRDP(void);\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+\r
+extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\r
+ * @brief Extended IO operation functions \r
+ *\r
+@verbatim \r
+ ===============================================================================\r
+ ##### Extended programming operation functions #####\r
+ =============================================================================== \r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the Extension FLASH \r
+ programming operations Operations.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors \r
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @param[out] SectorError pointer to variable that\r
+ * contains the configuration information on faulty sector in case of error \r
+ * (0xFFFFFFFF means that all the sectors have been correctly erased)\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ uint32_t index = 0;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /*Initialization of SectorError variable*/\r
+ *SectorError = 0xFFFFFFFFU;\r
+ \r
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+ {\r
+ /*Mass erase to be done*/\r
+#if defined (FLASH_OPTCR_nDBANK) \r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r
+#else\r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); \r
+#endif /* FLASH_OPTCR_nDBANK */\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* if the erase operation is completed, disable the MER Bit */\r
+ FLASH->CR &= (~FLASH_MER_BIT);\r
+ }\r
+ else\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r
+\r
+ /* Erase by sector by sector to be done*/\r
+ for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)\r
+ {\r
+ FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ /* If the erase operation is completed, disable the SER Bit and SNB Bits */\r
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); \r
+\r
+ if(status != HAL_OK) \r
+ {\r
+ /* In case of error, stop erase procedure and return the faulty sector*/\r
+ *SectorError = index;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled\r
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r
+ * contains the configuration information for the erasing.\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r
+\r
+ /* Enable End of FLASH Operation interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r
+ \r
+ /* Enable Error source interrupt */\r
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r
+ \r
+ /* Clear pending flags (if any) */ \r
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\r
+ FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); \r
+ \r
+ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r
+ {\r
+ /*Mass erase to be done*/\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;\r
+#if defined (FLASH_OPTCR_nDBANK) \r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r
+#else\r
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); \r
+#endif /* FLASH_OPTCR_nDBANK */ \r
+ }\r
+ else\r
+ {\r
+ /* Erase by sector to be done*/\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r
+\r
+ pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;\r
+ pFlash.NbSectorsToErase = pEraseInit->NbSectors;\r
+ pFlash.Sector = pEraseInit->Sector;\r
+ pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;\r
+\r
+ /*Erase 1st sector and wait for IT*/\r
+ FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Program option bytes\r
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ HAL_StatusTypeDef status = HAL_ERROR;\r
+ \r
+ /* Process Locked */\r
+ __HAL_LOCK(&pFlash);\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r
+\r
+ /* Write protection configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\r
+ {\r
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));\r
+ if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)\r
+ {\r
+ /*Enable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_EnableWRP(pOBInit->WRPSector);\r
+ }\r
+ else\r
+ {\r
+ /*Disable of Write protection on the selected Sector*/\r
+ status = FLASH_OB_DisableWRP(pOBInit->WRPSector);\r
+ }\r
+ }\r
+\r
+ /* Read protection configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\r
+ {\r
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);\r
+ }\r
+\r
+ /* USER configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\r
+ {\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r
+ pOBInit->USERConfig & OB_IWDG_SW,\r
+ pOBInit->USERConfig & OB_STOP_NO_RST,\r
+ pOBInit->USERConfig & OB_STDBY_NO_RST, \r
+ pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r
+ pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,\r
+ pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,\r
+ pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);\r
+#else\r
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r
+ pOBInit->USERConfig & OB_IWDG_SW,\r
+ pOBInit->USERConfig & OB_STOP_NO_RST,\r
+ pOBInit->USERConfig & OB_STDBY_NO_RST, \r
+ pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r
+ pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); \r
+#endif /* FLASH_OPTCR_nDBANK */\r
+ }\r
+ \r
+ /* BOR Level configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)\r
+ {\r
+ status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);\r
+ }\r
+ \r
+ /* Boot 0 Address configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)\r
+ {\r
+ status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);\r
+ }\r
+ \r
+ /* Boot 1 Address configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)\r
+ {\r
+ status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);\r
+ }\r
+ \r
+#if defined (FLASH_OPTCR2_PCROP)\r
+ /* PCROP configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)\r
+ {\r
+ status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector);\r
+ }\r
+ \r
+ /* PCROP_RDP configuration */\r
+ if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP)\r
+ {\r
+ status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp);\r
+ }\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(&pFlash);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Get the Option byte configuration\r
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that\r
+ * contains the configuration information for the programming.\r
+ * \r
+ * @retval None\r
+ */\r
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r
+{\r
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\r
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;\r
+\r
+ /*Get WRP*/\r
+ pOBInit->WRPSector = FLASH_OB_GetWRP();\r
+\r
+ /*Get RDP Level*/\r
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();\r
+\r
+ /*Get USER*/\r
+ pOBInit->USERConfig = FLASH_OB_GetUser();\r
+\r
+ /*Get BOR Level*/\r
+ pOBInit->BORLevel = FLASH_OB_GetBOR();\r
+ \r
+ /*Get Boot Address when Boot pin = 0 */\r
+ pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);\r
+ \r
+ /*Get Boot Address when Boot pin = 1 */\r
+ pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+ /*Get PCROP Sectors */\r
+ pOBInit->PCROPSector = FLASH_OB_GetPCROP();\r
+ \r
+ /*Get PCROP_RDP Value */\r
+ pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP();\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#if defined (FLASH_OPTCR_nDBANK)\r
+/**\r
+ * @brief Full erase of FLASH memory sectors \r
+ * @param VoltageRange The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ * @param Banks Banks to be erased\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_BANK_1: Bank1 to be erased\r
+ * @arg FLASH_BANK_2: Bank2 to be erased\r
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\r
+ *\r
+ * @retval HAL Status\r
+ */\r
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+ assert_param(IS_FLASH_BANK(Banks));\r
+\r
+ /* if the previous operation is completed, proceed to erase all sectors */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ if(Banks == FLASH_BANK_BOTH)\r
+ {\r
+ /* bank1 & bank2 will be erased*/\r
+ FLASH->CR |= FLASH_MER_BIT;\r
+ }\r
+ else if(Banks == FLASH_BANK_2)\r
+ {\r
+ /*Only bank2 will be erased*/\r
+ FLASH->CR |= FLASH_CR_MER2;\r
+ }\r
+ else\r
+ {\r
+ /*Only bank1 will be erased*/\r
+ FLASH->CR |= FLASH_CR_MER1; \r
+ }\r
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Erase the specified FLASH memory sector\r
+ * @param Sector FLASH sector to erase\r
+ * The value of this parameter depend on device used within the same series \r
+ * @param VoltageRange The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ * \r
+ * @retval None\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r
+{\r
+ uint32_t tmp_psize = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_SECTOR(Sector));\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+ \r
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_BYTE;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_HALF_WORD;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_WORD;\r
+ }\r
+ else\r
+ {\r
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r
+ }\r
+ \r
+ /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */\r
+ if(Sector > FLASH_SECTOR_11) \r
+ {\r
+ Sector += 4;\r
+ } \r
+\r
+ /* If the previous operation is completed, proceed to erase the sector */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= tmp_psize;\r
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);\r
+ FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH Write Protection Option Bytes value.\r
+ * @retval uint32_t FLASH Write Protection Option Bytes value\r
+ */\r
+static uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));\r
+}\r
+\r
+/**\r
+ * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. \r
+ * @param Wwdg Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_WWDG_SW: Software WWDG selected\r
+ * @arg OB_WWDG_HW: Hardware WWDG selected\r
+ * @param Iwdg Selects the WWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param Stop Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param Stdby Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @param Iwdgstop Independent watchdog counter freeze in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r
+ * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r
+ * @param Iwdgstdby Independent watchdog counter freeze in standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r
+ * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY\r
+ * @param NDBank Flash Single Bank mode enabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)\r
+ * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) \r
+ * @param NDBoot Flash Dual boot mode disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot\r
+ * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot\r
+\r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\r
+ uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)\r
+{\r
+ uint32_t useroptionmask = 0x00;\r
+ uint32_t useroptionvalue = 0x00;\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r
+ assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r
+ assert_param(IS_OB_STOP_SOURCE(Stop));\r
+ assert_param(IS_OB_STDBY_SOURCE(Stdby));\r
+ assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r
+ assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r
+ assert_param(IS_OB_NDBANK(NDBank));\r
+ assert_param(IS_OB_NDBOOT(NDBoot));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\r
+ FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \\r
+ FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);\r
+ \r
+ useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);\r
+ \r
+ /* Update User Option Byte */ \r
+ MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r
+ }\r
+ \r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH User Option Byte value.\r
+ * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r
+ * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r
+ */\r
+static uint32_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));\r
+}\r
+#else\r
+\r
+/**\r
+ * @brief Full erase of FLASH memory sectors \r
+ * @param VoltageRange The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ *\r
+ * @retval HAL Status\r
+ */\r
+static void FLASH_MassErase(uint8_t VoltageRange)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+\r
+ /* if the previous operation is completed, proceed to erase all sectors */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= FLASH_CR_MER;\r
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Erase the specified FLASH memory sector\r
+ * @param Sector FLASH sector to erase\r
+ * The value of this parameter depend on device used within the same series \r
+ * @param VoltageRange The device voltage range which defines the erase parallelism. \r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r
+ * the operation will be done by byte (8-bit) \r
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r
+ * the operation will be done by half word (16-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r
+ * the operation will be done by word (32-bit)\r
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r
+ * the operation will be done by double word (64-bit)\r
+ * \r
+ * @retval None\r
+ */\r
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r
+{\r
+ uint32_t tmp_psize = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_SECTOR(Sector));\r
+ assert_param(IS_VOLTAGERANGE(VoltageRange));\r
+ \r
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_BYTE;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_HALF_WORD;\r
+ }\r
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r
+ {\r
+ tmp_psize = FLASH_PSIZE_WORD;\r
+ }\r
+ else\r
+ {\r
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r
+ }\r
+\r
+ /* If the previous operation is completed, proceed to erase the sector */\r
+ FLASH->CR &= CR_PSIZE_MASK;\r
+ FLASH->CR |= tmp_psize;\r
+ FLASH->CR &= SECTOR_MASK;\r
+ FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);\r
+ FLASH->CR |= FLASH_CR_STRT;\r
+ \r
+ /* Data synchronous Barrier (DSB) Just after the write operation\r
+ This will force the CPU to respect the sequence of instruction (no optimization).*/\r
+ __DSB();\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH Write Protection Option Bytes value.\r
+ * @retval uint32_t FLASH Write Protection Option Bytes value\r
+ */\r
+static uint32_t FLASH_OB_GetWRP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));\r
+}\r
+\r
+/**\r
+ * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. \r
+ * @param Wwdg Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_WWDG_SW: Software WWDG selected\r
+ * @arg OB_WWDG_HW: Hardware WWDG selected\r
+ * @param Iwdg Selects the WWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param Stop Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param Stdby Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @param Iwdgstop Independent watchdog counter freeze in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r
+ * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r
+ * @param Iwdgstdby Independent watchdog counter freeze in standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r
+ * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)\r
+{\r
+ uint32_t useroptionmask = 0x00;\r
+ uint32_t useroptionvalue = 0x00;\r
+\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r
+ assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r
+ assert_param(IS_OB_STOP_SOURCE(Stop));\r
+ assert_param(IS_OB_STDBY_SOURCE(Stdby));\r
+ assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r
+ assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\r
+ FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);\r
+ \r
+ useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);\r
+ \r
+ /* Update User Option Byte */ \r
+ MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r
+ }\r
+ \r
+ return status; \r
+\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH User Option Byte value.\r
+ * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r
+ * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r
+ */\r
+static uint32_t FLASH_OB_GetUser(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));\r
+}\r
+#endif /* FLASH_OPTCR_nDBANK */\r
+\r
+/**\r
+ * @brief Enable the write protection of the desired bank1 or bank2 sectors\r
+ *\r
+ * @note When the memory read protection level is selected (RDP level = 1), \r
+ * it is not possible to program or erase the flash sector i if CortexM7 \r
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
+ * \r
+ * @param WRPSector specifies the sector(s) to be write protected.\r
+ * This parameter can be one of the following values:\r
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r
+ * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r
+ * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)\r
+ * @arg OB_WRP_SECTOR_All\r
+ *\r
+ * @retval HAL FLASH State \r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /*Write protection enabled on sectors */\r
+ FLASH->OPTCR &= (~WRPSector); \r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Disable the write protection of the desired bank1 or bank 2 sectors\r
+ *\r
+ * @note When the memory read protection level is selected (RDP level = 1), \r
+ * it is not possible to program or erase the flash sector i if CortexM4 \r
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \r
+ * \r
+ * @param WRPSector specifies the sector(s) to be write protected.\r
+ * This parameter can be one of the following values:\r
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r
+ * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r
+ * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) \r
+ * @arg OB_WRP_Sector_All\r
+ *\r
+ *\r
+ * @retval HAL Status \r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ {\r
+ /* Write protection disabled on sectors */\r
+ FLASH->OPTCR |= (WRPSector); \r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Set the read protection level.\r
+ * @param Level specifies the read protection level.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_RDP_LEVEL_0: No protection\r
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory\r
+ * @arg OB_RDP_LEVEL_2: Full chip protection\r
+ * \r
+ * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_RDP_LEVEL(Level));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ { \r
+ *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Set the BOR Level. \r
+ * @param Level specifies the Option Bytes BOR Reset Level.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r
+ * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r
+ * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r
+ * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V\r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOR_LEVEL(Level));\r
+\r
+ /* Set the BOR Level */\r
+ MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);\r
+ \r
+ return HAL_OK;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Configure Boot base address.\r
+ * \r
+ * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1\r
+ * This parameter can be one of the following values:\r
+ * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 \r
+ * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 \r
+ * @param Address specifies Boot base address\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) \r
+ * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r
+ * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) \r
+ * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) \r
+ * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) \r
+ * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) \r
+ * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_BOOT_ADDRESS(Address));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+ \r
+ if(status == HAL_OK)\r
+ {\r
+ if(BootOption == OPTIONBYTE_BOOTADDR_0)\r
+ { \r
+ MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);\r
+ }\r
+ else\r
+ {\r
+ MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));\r
+ }\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Read Protection level.\r
+ * @retval FlagStatus FLASH ReadOut Protection Status:\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_RDP_LEVEL_0: No protection\r
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory\r
+ * @arg OB_RDP_LEVEL_2: Full chip protection\r
+ */\r
+static uint8_t FLASH_OB_GetRDP(void)\r
+{\r
+ uint8_t readstatus = OB_RDP_LEVEL_0;\r
+ \r
+ if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)\r
+ {\r
+ readstatus = OB_RDP_LEVEL_0;\r
+ }\r
+ else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)\r
+ {\r
+ readstatus = OB_RDP_LEVEL_2;\r
+ }\r
+ else \r
+ {\r
+ readstatus = OB_RDP_LEVEL_1;\r
+ }\r
+\r
+ return readstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH BOR level.\r
+ * @retval uint32_t The FLASH BOR level:\r
+ * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r
+ * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r
+ * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r
+ * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V \r
+ */\r
+static uint32_t FLASH_OB_GetBOR(void)\r
+{\r
+ /* Return the FLASH BOR level */\r
+ return ((uint32_t)(FLASH->OPTCR & 0x0C));\r
+}\r
+\r
+/**\r
+ * @brief Configure Boot base address.\r
+ * \r
+ * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1\r
+ * This parameter can be one of the following values:\r
+ * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 \r
+ * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 \r
+ * \r
+ * @retval uint32_t Boot Base Address:\r
+ * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) \r
+ * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r
+ * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) \r
+ * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) \r
+ * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) \r
+ * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) \r
+ * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r
+ */\r
+static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)\r
+{ \r
+ uint32_t Address = 0;\r
+ \r
+ /* Return the Boot base Address */\r
+ if(BootOption == OPTIONBYTE_BOOTADDR_0)\r
+ { \r
+ Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;\r
+ }\r
+ else\r
+ {\r
+ Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);\r
+ }\r
+\r
+ return Address;\r
+}\r
+\r
+#if defined (FLASH_OPTCR2_PCROP)\r
+/**\r
+ * @brief Set the PCROP protection for sectors.\r
+ * @param PCROPSector specifies the sector(s) to be PCROP protected.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7\r
+ * @arg OB_PCROP_SECTOR_ALL\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_PCROP_SECTOR(PCROPSector));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ { \r
+ MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector);\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Set the PCROP_RDP value\r
+ * @param Pcrop_Rdp specifies the PCROP_RDP bit value.\r
+ * \r
+ * @retval HAL Status\r
+ */\r
+static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp));\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r
+\r
+ if(status == HAL_OK)\r
+ { \r
+ MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp);\r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH PCROP Protection Option Bytes value.\r
+ * @retval uint32_t FLASH PCROP Protection Option Bytes value\r
+ */\r
+static uint32_t FLASH_OB_GetPCROP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP));\r
+}\r
+\r
+/**\r
+ * @brief Return the FLASH PCROP_RDP option byte value.\r
+ * @retval uint32_t FLASH PCROP_RDP option byte value\r
+ */\r
+static uint32_t FLASH_OB_GetPCROPRDP(void)\r
+{\r
+ /* Return the FLASH write protection Register value */\r
+ return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP));\r
+}\r
+#endif /* FLASH_OPTCR2_PCROP */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_gpio.c\r
+ * @author MCD Application Team\r
+ * @brief GPIO HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### GPIO Peripheral features #####\r
+ ==============================================================================\r
+ [..] \r
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each\r
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\r
+ in several modes:\r
+ (+) Input mode \r
+ (+) Analog mode\r
+ (+) Output mode\r
+ (+) Alternate function mode\r
+ (+) External interrupt/event lines\r
+\r
+ [..] \r
+ During and just after reset, the alternate functions and external interrupt \r
+ lines are not active and the I/O ports are configured in input floating mode.\r
+ \r
+ [..] \r
+ All GPIO pins have weak internal pull-up and pull-down resistors, which can be \r
+ activated or not.\r
+\r
+ [..]\r
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r
+ type and the IO speed can be selected depending on the VDD value.\r
+\r
+ [..] \r
+ All ports have external interrupt/event capability. To use external interrupt \r
+ lines, the port must be configured in input mode. All available GPIO pins are \r
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r
+ \r
+ [..]\r
+ The external interrupt/event controller consists of up to 23 edge detectors \r
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each \r
+ input line can be independently configured to select the type (interrupt or event) \r
+ and the corresponding trigger event (rising or falling or both). Each line can \r
+ also be masked independently. \r
+\r
+ ##### How to use this driver #####\r
+ ============================================================================== \r
+ [..]\r
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). \r
+\r
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure\r
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef \r
+ structure.\r
+ (++) In case of Output or alternate function mode selection: the speed is \r
+ configured through "Speed" member from GPIO_InitTypeDef structure.\r
+ (++) In alternate mode is selection, the alternate function connected to the IO\r
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.\r
+ (++) Analog mode is required when a pin is to be used as ADC channel \r
+ or DAC output.\r
+ (++) In case of external interrupt/event selection the "Mode" member from \r
+ GPIO_InitTypeDef structure select the type (interrupt or event) and \r
+ the corresponding trigger event (rising or falling or both).\r
+\r
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority \r
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r
+ HAL_NVIC_EnableIRQ().\r
+ \r
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r
+ \r
+ (#) To set/reset the level of a pin configured in output mode use \r
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r
+ \r
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r
+\r
+ \r
+ (#) During and just after reset, the alternate functions are not \r
+ active and the GPIO pins are configured in input floating mode (except JTAG\r
+ pins).\r
+ \r
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose \r
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has \r
+ priority over the GPIO function.\r
+ \r
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off. \r
+ The HSE has priority over the GPIO function.\r
+ \r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO GPIO\r
+ * @brief GPIO HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants\r
+ * @{\r
+ */\r
+#define GPIO_MODE ((uint32_t)0x00000003U)\r
+#define EXTI_MODE ((uint32_t)0x10000000U)\r
+#define GPIO_MODE_IT ((uint32_t)0x00010000U)\r
+#define GPIO_MODE_EVT ((uint32_t)0x00020000U)\r
+#define RISING_EDGE ((uint32_t)0x00100000U)\r
+#define FALLING_EDGE ((uint32_t)0x00200000U)\r
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)\r
+\r
+#define GPIO_NUMBER ((uint32_t)16U)\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to initialize and de-initialize the GPIOs\r
+ to be ready for use.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains\r
+ * the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r
+{\r
+ uint32_t position = 0x00;\r
+ uint32_t ioposition = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t temp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r
+\r
+ /* Configure the port pins */\r
+ for(position = 0; position < GPIO_NUMBER; position++)\r
+ {\r
+ /* Get the IO position */\r
+ ioposition = ((uint32_t)0x01) << position;\r
+ /* Get the current IO position */\r
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;\r
+\r
+ if(iocurrent == ioposition)\r
+ {\r
+ /*--------------------- GPIO Mode Configuration ------------------------*/\r
+ /* In case of Alternate function mode selection */\r
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Alternate function parameter */\r
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r
+ \r
+ /* Configure Alternate function mapped with the current IO */\r
+ temp = GPIOx->AFR[position >> 3];\r
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));\r
+ GPIOx->AFR[position >> 3] = temp;\r
+ }\r
+\r
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r
+ temp = GPIOx->MODER;\r
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));\r
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));\r
+ GPIOx->MODER = temp;\r
+\r
+ /* In case of Output or Alternate function mode selection */\r
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r
+ {\r
+ /* Check the Speed parameter */\r
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r
+ /* Configure the IO Speed */\r
+ temp = GPIOx->OSPEEDR; \r
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+ temp |= (GPIO_Init->Speed << (position * 2));\r
+ GPIOx->OSPEEDR = temp;\r
+\r
+ /* Configure the IO Output Type */\r
+ temp = GPIOx->OTYPER;\r
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;\r
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);\r
+ GPIOx->OTYPER = temp;\r
+ }\r
+\r
+ /* Activate the Pull-up or Pull down resistor for the current IO */\r
+ temp = GPIOx->PUPDR;\r
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r
+ temp |= ((GPIO_Init->Pull) << (position * 2));\r
+ GPIOx->PUPDR = temp;\r
+\r
+ /*--------------------- EXTI Mode Configuration ------------------------*/\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r
+ {\r
+ /* Enable SYSCFG Clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ temp = SYSCFG->EXTICR[position >> 2];\r
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));\r
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));\r
+ SYSCFG->EXTICR[position >> 2] = temp;\r
+\r
+ /* Clear EXTI line configuration */\r
+ temp = EXTI->IMR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->IMR = temp;\r
+\r
+ temp = EXTI->EMR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->EMR = temp;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ temp = EXTI->RTSR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->RTSR = temp;\r
+\r
+ temp = EXTI->FTSR;\r
+ temp &= ~((uint32_t)iocurrent);\r
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r
+ {\r
+ temp |= iocurrent;\r
+ }\r
+ EXTI->FTSR = temp;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)\r
+{\r
+ uint32_t position;\r
+ uint32_t ioposition = 0x00;\r
+ uint32_t iocurrent = 0x00;\r
+ uint32_t tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r
+ \r
+ /* Configure the port pins */\r
+ for(position = 0; position < GPIO_NUMBER; position++)\r
+ {\r
+ /* Get the IO position */\r
+ ioposition = ((uint32_t)0x01) << position;\r
+ /* Get the current IO position */\r
+ iocurrent = (GPIO_Pin) & ioposition;\r
+\r
+ if(iocurrent == ioposition)\r
+ {\r
+ /*------------------------- EXTI Mode Configuration --------------------*/\r
+ tmp = SYSCFG->EXTICR[position >> 2];\r
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));\r
+ if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))\r
+ {\r
+ /* Configure the External Interrupt or event for the current IO */\r
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));\r
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;\r
+\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~((uint32_t)iocurrent);\r
+ EXTI->EMR &= ~((uint32_t)iocurrent);\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~((uint32_t)iocurrent);\r
+ EXTI->FTSR &= ~((uint32_t)iocurrent);\r
+ }\r
+ /*------------------------- GPIO Mode Configuration --------------------*/\r
+ /* Configure IO Direction in Input Floating Mode */\r
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));\r
+\r
+ /* Configure the default Alternate Function in current IO */\r
+ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r
+\r
+ /* Configure the default value for IO Speed */\r
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r
+\r
+ /* Configure the default value IO Output Type */\r
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;\r
+\r
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions \r
+ * @brief GPIO Read and Write\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin specifies the port bit to read.\r
+ * This parameter can be GPIO_PIN_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ GPIO_PinState bitstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\r
+ {\r
+ bitstatus = GPIO_PIN_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = GPIO_PIN_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ *\r
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify\r
+ * accesses. In this way, there is no risk of an IRQ occurring between\r
+ * the read and the modify access.\r
+ *\r
+ * @param GPIOx where x can be (A..K) to select the GPIO peripheral.\r
+ * @param GPIO_Pin specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).\r
+ * @param PinState specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the GPIO_PinState enum values:\r
+ * @arg GPIO_PIN_RESET: to clear the port pin\r
+ * @arg GPIO_PIN_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_PIN_ACTION(PinState));\r
+\r
+ if(PinState != GPIO_PIN_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Toggles the specified GPIO pins.\r
+ * @param GPIOx Where x can be (A..I) to select the GPIO peripheral.\r
+ * @param GPIO_Pin Specifies the pins to be toggled.\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)\r
+ {\r
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r
+ * @note The configuration of the locked GPIO pins can no longer be modified\r
+ * until the next reset.\r
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family\r
+ * @param GPIO_Pin specifies the port bit to be locked.\r
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+\r
+ /* Apply lock key write sequence */\r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+\r
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)\r
+ {\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles EXTI interrupt request.\r
+ * @param GPIO_Pin Specifies the pins connected EXTI line\r
+ * @retval None\r
+ */\r
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r
+{\r
+ /* EXTI line interrupt detected */\r
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)\r
+ {\r
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief EXTI line detection callbacks.\r
+ * @param GPIO_Pin Specifies the pins connected EXTI line\r
+ * @retval None\r
+ */\r
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(GPIO_Pin);\r
+ \r
+ /* NOTE: This function Should not be modified, when the callback is needed,\r
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c.c\r
+ * @author MCD Application Team\r
+ * @brief I2C HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + IO operation functions\r
+ * + Peripheral State and Errors functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ The I2C HAL driver can be used as follows:\r
+\r
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:\r
+ I2C_HandleTypeDef hi2c;\r
+\r
+ (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:\r
+ (##) Enable the I2Cx interface clock\r
+ (##) I2C pins configuration\r
+ (+++) Enable the clock for the I2C GPIOs\r
+ (+++) Configure I2C pins as alternate function open-drain\r
+ (##) NVIC configuration if you need to use interrupt process\r
+ (+++) Configure the I2Cx interrupt priority\r
+ (+++) Enable the NVIC I2C IRQ Channel\r
+ (##) DMA Configuration if you need to use DMA process\r
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream\r
+ (+++) Enable the DMAx interface clock using\r
+ (+++) Configure the DMA handle parameters\r
+ (+++) Configure the DMA Tx or Rx stream\r
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\r
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on\r
+ the DMA Tx or Rx stream\r
+\r
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,\r
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.\r
+\r
+ (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware\r
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.\r
+\r
+ (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()\r
+\r
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\r
+\r
+ *** Polling mode IO operation ***\r
+ =================================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()\r
+ (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()\r
+ (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()\r
+ (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()\r
+\r
+ *** Polling mode IO MEM operation ***\r
+ =====================================\r
+ [..]\r
+ (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()\r
+ (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()\r
+\r
+\r
+ *** Interrupt mode IO operation ***\r
+ ===================================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()\r
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
+ (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()\r
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
+ (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()\r
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
+ (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()\r
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
+ This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+\r
+ *** Interrupt mode or DMA mode IO sequential operation ***\r
+ ==========================================================\r
+ [..]\r
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition\r
+ when a direction change during transfer\r
+ [..]\r
+ (+) A specific option field manage the different steps of a sequential transfer\r
+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:\r
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode\r
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address\r
+ and data to transfer without a final stop condition\r
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address\r
+ and data to transfer without a final stop condition, an then permit a call the same master sequential interface\r
+ several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()\r
+ or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())\r
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address\r
+ and with new data to transfer if the direction change or manage only the new data to transfer\r
+ if no direction change and without a final stop condition in both cases\r
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address\r
+ and with new data to transfer if the direction change or manage only the new data to transfer\r
+ if no direction change and with a final stop condition in both cases\r
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential\r
+ interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).\r
+ Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).\r
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit\r
+ without stopping the communication and so generate a restart condition.\r
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential\r
+ interface.\r
+ Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\r
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).\r
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.\r
+\r
+ (+) Differents sequential I2C interfaces are listed below:\r
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()\r
+ or using @ref HAL_I2C_Master_Seq_Transmit_DMA()\r
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()\r
+ or using @ref HAL_I2C_Master_Seq_Receive_DMA()\r
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
+ (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
+ (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()\r
+ (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can\r
+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).\r
+ (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()\r
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()\r
+ or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()\r
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()\r
+ or using @ref HAL_I2C_Slave_Seq_Receive_DMA()\r
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
+ (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+ (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
+ This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+ *** Interrupt mode IO MEM operation ***\r
+ =======================================\r
+ [..]\r
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using\r
+ @ref HAL_I2C_Mem_Write_IT()\r
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\r
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using\r
+ @ref HAL_I2C_Mem_Read_IT()\r
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\r
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+\r
+ *** DMA mode IO operation ***\r
+ ==============================\r
+ [..]\r
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using\r
+ @ref HAL_I2C_Master_Transmit_DMA()\r
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\r
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using\r
+ @ref HAL_I2C_Master_Receive_DMA()\r
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\r
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using\r
+ @ref HAL_I2C_Slave_Transmit_DMA()\r
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\r
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using\r
+ @ref HAL_I2C_Slave_Receive_DMA()\r
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\r
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\r
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\r
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.\r
+ This action will inform Master to generate a Stop condition to discard the communication.\r
+\r
+ *** DMA mode IO MEM operation ***\r
+ =================================\r
+ [..]\r
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using\r
+ @ref HAL_I2C_Mem_Write_DMA()\r
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\r
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using\r
+ @ref HAL_I2C_Mem_Read_DMA()\r
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\r
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\r
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\r
+\r
+\r
+ *** I2C HAL driver macros list ***\r
+ ==================================\r
+ [..]\r
+ Below the list of most used macros in I2C HAL driver.\r
+\r
+ (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral\r
+ (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral\r
+ (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode\r
+ (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not\r
+ (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag\r
+ (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt\r
+ (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\r
+\r
+ *** Callback registration ***\r
+ =============================================\r
+\r
+ The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1\r
+ allows the user to configure dynamically the driver callbacks.\r
+ Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()\r
+ to register an interrupt callback.\r
+\r
+ Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:\r
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\r
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.\r
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.\r
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.\r
+ (+) ListenCpltCallback : callback for end of listen mode.\r
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.\r
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.\r
+ (+) ErrorCallback : callback for error detection.\r
+ (+) AbortCpltCallback : callback for abort completion process.\r
+ (+) MspInitCallback : callback for Msp Init.\r
+ (+) MspDeInitCallback : callback for Msp DeInit.\r
+ This function takes as parameters the HAL peripheral handle, the Callback ID\r
+ and a pointer to the user callback function.\r
+\r
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().\r
+\r
+ Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default\r
+ weak function.\r
+ @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
+ and the Callback ID.\r
+ This function allows to reset following callbacks:\r
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\r
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.\r
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.\r
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.\r
+ (+) ListenCpltCallback : callback for end of listen mode.\r
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.\r
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.\r
+ (+) ErrorCallback : callback for error detection.\r
+ (+) AbortCpltCallback : callback for abort completion process.\r
+ (+) MspInitCallback : callback for Msp Init.\r
+ (+) MspDeInitCallback : callback for Msp DeInit.\r
+\r
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().\r
+\r
+ By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET\r
+ all callbacks are set to the corresponding weak functions:\r
+ examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().\r
+ Exception done for MspInit and MspDeInit functions that are\r
+ reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when\r
+ these callbacks are null (not registered beforehand).\r
+ If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()\r
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\r
+\r
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.\r
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered\r
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,\r
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\r
+ Then, the user first registers the MspInit/MspDeInit user callbacks\r
+ using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()\r
+ or @ref HAL_I2C_Init() function.\r
+\r
+ When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or\r
+ not defined, the callback registration feature is not available and all callbacks\r
+ are set to the corresponding weak functions.\r
+\r
+ [..]\r
+ (@) You can refer to the I2C HAL driver header file for more useful macros\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C I2C\r
+ * @brief I2C HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Define I2C Private Define\r
+ * @{\r
+ */\r
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */\r
+#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */\r
+#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */\r
+#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */\r
+\r
+#define MAX_NBYTE_SIZE 255U\r
+#define SlaveAddr_SHIFT 7U\r
+#define SlaveAddr_MSK 0x06U\r
+\r
+/* Private define for @ref PreviousState usage */\r
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */\r
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */\r
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */\r
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */\r
+\r
+\r
+/* Private define to centralize the enable/disable of Interrupts */\r
+#define I2C_XFER_TX_IT (0x00000001U)\r
+#define I2C_XFER_RX_IT (0x00000002U)\r
+#define I2C_XFER_LISTEN_IT (0x00000004U)\r
+\r
+#define I2C_XFER_ERROR_IT (0x00000011U)\r
+#define I2C_XFER_CPLT_IT (0x00000012U)\r
+#define I2C_XFER_RELOAD_IT (0x00000012U)\r
+\r
+/* Private define Sequential Transfer Options default/reset value */\r
+#define I2C_NO_OPTION_FRAME (0xFFFF0000U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Functions I2C Private Functions\r
+ * @{\r
+ */\r
+/* Private functions to handle DMA transfer */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);\r
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);\r
+\r
+/* Private functions to handle IT transfer */\r
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);\r
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);\r
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);\r
+\r
+/* Private functions to handle IT transfer */\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r
+\r
+/* Private functions for I2C transfer IRQ handler */\r
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r
+\r
+/* Private functions to handle flags during polling transfer */\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r
+\r
+/* Private functions to centralize the enable/disable of Interrupts */\r
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r
+\r
+/* Private function to flush TXDR register */\r
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);\r
+\r
+/* Private function to handle start, restart or stop a transfer */\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\r
+\r
+/* Private function to Convert Specific options */\r
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Exported_Functions I2C Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..] This subsection provides a set of functions allowing to initialize and\r
+ deinitialize the I2Cx peripheral:\r
+\r
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures\r
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r
+\r
+ (+) Call the function HAL_I2C_Init() to configure the selected device with\r
+ the selected configuration:\r
+ (++) Clock Timing\r
+ (++) Own Address 1\r
+ (++) Addressing mode (Master, Slave)\r
+ (++) Dual Addressing mode\r
+ (++) Own Address 2\r
+ (++) Own Address 2 Mask\r
+ (++) General call mode\r
+ (++) Nostretch mode\r
+\r
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration\r
+ of the selected I2Cx peripheral.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the I2C according to the specified parameters\r
+ * in the I2C_InitTypeDef and initialize the associated handle.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Check the I2C handle allocation */\r
+ if (hi2c == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\r
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\r
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\r
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\r
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));\r
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\r
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ hi2c->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ /* Init the I2C Callback settings */\r
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\r
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\r
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */\r
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */\r
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */\r
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */\r
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */\r
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */\r
+\r
+ if (hi2c->MspInitCallback == NULL)\r
+ {\r
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */\r
+ }\r
+\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ hi2c->MspInitCallback(hi2c);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r
+ HAL_I2C_MspInit(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+\r
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/\r
+ /* Configure I2Cx: Frequency range */\r
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;\r
+\r
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r
+ /* Disable Own Address1 before set the Own Address1 configuration */\r
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;\r
+\r
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */\r
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\r
+ {\r
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);\r
+ }\r
+ else /* I2C_ADDRESSINGMODE_10BIT */\r
+ {\r
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);\r
+ }\r
+\r
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/\r
+ /* Configure I2Cx: Addressing Master mode */\r
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);\r
+ }\r
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */\r
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);\r
+\r
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\r
+ /* Disable Own Address2 before set the Own Address2 configuration */\r
+ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;\r
+\r
+ /* Configure I2Cx: Dual mode and Own Address2 */\r
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));\r
+\r
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/\r
+ /* Configure I2Cx: Generalcall and NoStretch mode */\r
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);\r
+\r
+ /* Enable the selected I2C peripheral */\r
+ __HAL_I2C_ENABLE(hi2c);\r
+\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the I2C peripheral.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Check the I2C handle allocation */\r
+ if (hi2c == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+ /* Disable the I2C Peripheral Clock */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ if (hi2c->MspDeInitCallback == NULL)\r
+ {\r
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */\r
+ }\r
+\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ hi2c->MspDeInitCallback(hi2c);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_I2C_MspDeInit(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State = HAL_I2C_STATE_RESET;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initialize the I2C MSP.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitialize the I2C MSP.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Register a User I2C Callback\r
+ * To be used instead of the weak predefined callback\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param CallbackID ID of the callback to be registered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\r
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\r
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\r
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\r
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\r
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\r
+ * @param pCallback pointer to the Callback function\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if (HAL_I2C_STATE_READY == hi2c->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\r
+ hi2c->MasterTxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\r
+ hi2c->MasterRxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\r
+ hi2c->SlaveTxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\r
+ hi2c->SlaveRxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :\r
+ hi2c->ListenCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\r
+ hi2c->MemTxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\r
+ hi2c->MemRxCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_ERROR_CB_ID :\r
+ hi2c->ErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_ABORT_CB_ID :\r
+ hi2c->AbortCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_MSPINIT_CB_ID :\r
+ hi2c->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_MSPDEINIT_CB_ID :\r
+ hi2c->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (HAL_I2C_STATE_RESET == hi2c->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_I2C_MSPINIT_CB_ID :\r
+ hi2c->MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_I2C_MSPDEINIT_CB_ID :\r
+ hi2c->MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2c);\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Unregister an I2C Callback\r
+ * I2C callback is redirected to the weak predefined callback\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param CallbackID ID of the callback to be unregistered\r
+ * This parameter can be one of the following values:\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\r
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\r
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\r
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\r
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\r
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\r
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if (HAL_I2C_STATE_READY == hi2c->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\r
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\r
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\r
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\r
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :\r
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\r
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\r
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_ERROR_CB_ID :\r
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ break;\r
+\r
+ case HAL_I2C_ABORT_CB_ID :\r
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */\r
+ break;\r
+\r
+ case HAL_I2C_MSPINIT_CB_ID :\r
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */\r
+ break;\r
+\r
+ case HAL_I2C_MSPDEINIT_CB_ID :\r
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (HAL_I2C_STATE_RESET == hi2c->State)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_I2C_MSPINIT_CB_ID :\r
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */\r
+ break;\r
+\r
+ case HAL_I2C_MSPDEINIT_CB_ID :\r
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */\r
+ break;\r
+\r
+ default :\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2c);\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Register the Slave Address Match I2C Callback\r
+ * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pCallback pointer to the Address Match Callback function\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if (HAL_I2C_STATE_READY == hi2c->State)\r
+ {\r
+ hi2c->AddrCallback = pCallback;\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2c);\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief UnRegister the Slave Address Match I2C Callback\r
+ * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if (HAL_I2C_STATE_READY == hi2c->State)\r
+ {\r
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */\r
+ }\r
+ else\r
+ {\r
+ /* Update the error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\r
+\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(hi2c);\r
+ return status;\r
+}\r
+\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\r
+ * @brief Data transfers functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### IO operation functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to manage the I2C data\r
+ transfers.\r
+\r
+ (#) There are two modes of transfer:\r
+ (++) Blocking mode : The communication is performed in the polling mode.\r
+ The status of all data processing is returned by the same function\r
+ after finishing transfer.\r
+ (++) No-Blocking mode : The communication is performed using Interrupts\r
+ or DMA. These functions return the status of the transfer startup.\r
+ The end of the data processing will be indicated through the\r
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when\r
+ using DMA mode.\r
+\r
+ (#) Blocking mode functions are :\r
+ (++) HAL_I2C_Master_Transmit()\r
+ (++) HAL_I2C_Master_Receive()\r
+ (++) HAL_I2C_Slave_Transmit()\r
+ (++) HAL_I2C_Slave_Receive()\r
+ (++) HAL_I2C_Mem_Write()\r
+ (++) HAL_I2C_Mem_Read()\r
+ (++) HAL_I2C_IsDeviceReady()\r
+\r
+ (#) No-Blocking mode functions with Interrupt are :\r
+ (++) HAL_I2C_Master_Transmit_IT()\r
+ (++) HAL_I2C_Master_Receive_IT()\r
+ (++) HAL_I2C_Slave_Transmit_IT()\r
+ (++) HAL_I2C_Slave_Receive_IT()\r
+ (++) HAL_I2C_Mem_Write_IT()\r
+ (++) HAL_I2C_Mem_Read_IT()\r
+ (++) HAL_I2C_Master_Seq_Transmit_IT()\r
+ (++) HAL_I2C_Master_Seq_Receive_IT()\r
+ (++) HAL_I2C_Slave_Seq_Transmit_IT()\r
+ (++) HAL_I2C_Slave_Seq_Receive_IT()\r
+ (++) HAL_I2C_EnableListen_IT()\r
+ (++) HAL_I2C_DisableListen_IT()\r
+ (++) HAL_I2C_Master_Abort_IT()\r
+\r
+ (#) No-Blocking mode functions with DMA are :\r
+ (++) HAL_I2C_Master_Transmit_DMA()\r
+ (++) HAL_I2C_Master_Receive_DMA()\r
+ (++) HAL_I2C_Slave_Transmit_DMA()\r
+ (++) HAL_I2C_Slave_Receive_DMA()\r
+ (++) HAL_I2C_Mem_Write_DMA()\r
+ (++) HAL_I2C_Mem_Read_DMA()\r
+ (++) HAL_I2C_Master_Seq_Transmit_DMA()\r
+ (++) HAL_I2C_Master_Seq_Receive_DMA()\r
+ (++) HAL_I2C_Slave_Seq_Transmit_DMA()\r
+ (++) HAL_I2C_Slave_Seq_Receive_DMA()\r
+\r
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r
+ (++) HAL_I2C_MasterTxCpltCallback()\r
+ (++) HAL_I2C_MasterRxCpltCallback()\r
+ (++) HAL_I2C_SlaveTxCpltCallback()\r
+ (++) HAL_I2C_SlaveRxCpltCallback()\r
+ (++) HAL_I2C_MemTxCpltCallback()\r
+ (++) HAL_I2C_MemRxCpltCallback()\r
+ (++) HAL_I2C_AddrCallback()\r
+ (++) HAL_I2C_ListenCpltCallback()\r
+ (++) HAL_I2C_ErrorCallback()\r
+ (++) HAL_I2C_AbortCpltCallback()\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Transmits in master mode an amount of data in blocking mode.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+ }\r
+\r
+ while (hi2c->XferCount > 0U)\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferCount--;\r
+ hi2c->XferSize--;\r
+\r
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }\r
+\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set */\r
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receives in master mode an amount of data in blocking mode.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+\r
+ while (hi2c->XferCount > 0U)\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+\r
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }\r
+\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set */\r
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits in slave mode an amount of data in blocking mode.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Wait until ADDR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+ /* If 10bit addressing mode is selected */\r
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ /* Wait until ADDR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+\r
+ /* Wait until DIR flag is set Transmitter mode */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ while (hi2c->XferCount > 0U)\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferCount--;\r
+ }\r
+\r
+ /* Wait until STOP flag is set */\r
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r
+ {\r
+ /* Normal use case for Transmitter mode */\r
+ /* A NACK is generated to confirm the end of transfer */\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Clear STOP flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Wait until BUSY flag is reset */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in blocking mode\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Wait until ADDR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+ /* Wait until DIR flag is reset Receiver mode */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ while (hi2c->XferCount > 0U)\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ /* Store Last receive data if any */\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r
+ {\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferCount--;\r
+ }\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferCount--;\r
+ }\r
+\r
+ /* Wait until STOP flag is set */\r
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear STOP flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Wait until BUSY flag is reset */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+\r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+\r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode;\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ if (hi2c->XferSize > 0U)\r
+ {\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r
+\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update Transfer ISR function pointer */\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and generate START condition */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t xfermode;\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ if (hi2c->XferSize > 0U)\r
+ {\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update Transfer ISR function pointer */\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to read and generate START condition */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_DMA;\r
+\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r
+{\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Slave_ISR_DMA;\r
+\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Write an amount of data in blocking mode to a specific memory address\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Send Slave Address and Memory Address */\r
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+\r
+ do\r
+ {\r
+ /* Wait until TXIS flag is set */\r
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferCount--;\r
+ hi2c->XferSize--;\r
+\r
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+\r
+ }\r
+ while (hi2c->XferCount > 0U);\r
+\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */\r
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read an amount of data in blocking mode from a specific memory address\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Send Slave Address and Memory Address */\r
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+ }\r
+\r
+ do\r
+ {\r
+ /* Wait until RXNE flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+\r
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+ {\r
+ /* Wait until TCR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }\r
+ while (hi2c->XferCount > 0U);\r
+\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is reset */\r
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart;\r
+ uint32_t xfermode;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ /* Send Slave Address and Memory Address */\r
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart;\r
+ uint32_t xfermode;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ /* Send Slave Address and Memory Address */\r
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+\r
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+/**\r
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart;\r
+ uint32_t xfermode;\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ /* Send Slave Address and Memory Address */\r
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be read\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r
+{\r
+ uint32_t tickstart;\r
+ uint32_t xfermode;\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Init tickstart for timeout management*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MEM;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+\r
+ /* Send Slave Address and Memory Address */\r
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r
+\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks if target device is ready for communication.\r
+ * @note This function is used with Memory devices\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param Trials Number of trials\r
+ * @param Timeout Timeout duration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ __IO uint32_t I2C_Trials = 0UL;\r
+\r
+ FlagStatus tmp1;\r
+ FlagStatus tmp2;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ do\r
+ {\r
+ /* Generate Start */\r
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);\r
+\r
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r
+ /* Wait until STOPF flag is set or a NACK flag is set*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ while ((tmp1 == RESET) && (tmp2 == RESET))\r
+ {\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\r
+ }\r
+\r
+ /* Check if the NACKF flag has not been set */\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)\r
+ {\r
+ /* Wait until STOPF flag is reset */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Device is ready */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Wait until STOPF flag is reset */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Clear STOP Flag, auto generated with autoend*/\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ }\r
+\r
+ /* Check if the maximum allowed number of trials has been reached */\r
+ if (I2C_Trials == Trials)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+\r
+ /* Wait until STOPF flag is reset */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+ }\r
+\r
+ /* Increment Trials */\r
+ I2C_Trials++;\r
+ }\r
+ while (I2C_Trials < Trials);\r
+\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ uint32_t xfermode;\r
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+\r
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+ /* Mean Previous state is same as current state */\r
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+ {\r
+ xferrequest = I2C_NO_STARTSTOP;\r
+ }\r
+ else\r
+ {\r
+ /* Convert OTHER_xxx XferOptions if any */\r
+ I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+ /* Update xfermode accordingly if no reload is necessary */\r
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+ {\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+ }\r
+\r
+ /* Send Slave Address and set NBYTES to write */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ uint32_t xfermode;\r
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+\r
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+\r
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+ /* Mean Previous state is same as current state */\r
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+ {\r
+ xferrequest = I2C_NO_STARTSTOP;\r
+ }\r
+ else\r
+ {\r
+ /* Convert OTHER_xxx XferOptions if any */\r
+ I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+ /* Update xfermode accordingly if no reload is necessary */\r
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+ {\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+ }\r
+\r
+ if (hi2c->XferSize > 0U)\r
+ {\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Send Slave Address and set NBYTES to write */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update Transfer ISR function pointer */\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to write and generate START condition */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ uint32_t xfermode;\r
+ uint32_t xferrequest = I2C_GENERATE_START_READ;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+\r
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+ /* Mean Previous state is same as current state */\r
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+ {\r
+ xferrequest = I2C_NO_STARTSTOP;\r
+ }\r
+ else\r
+ {\r
+ /* Convert OTHER_xxx XferOptions if any */\r
+ I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+ /* Update xfermode accordingly if no reload is necessary */\r
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+ {\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+ }\r
+\r
+ /* Send Slave Address and set NBYTES to read */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ uint32_t xfermode;\r
+ uint32_t xferrequest = I2C_GENERATE_START_READ;\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;\r
+ hi2c->Mode = HAL_I2C_MODE_MASTER;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Master_ISR_DMA;\r
+\r
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+\r
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\r
+ /* Mean Previous state is same as current state */\r
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))\r
+ {\r
+ xferrequest = I2C_NO_STARTSTOP;\r
+ }\r
+ else\r
+ {\r
+ /* Convert OTHER_xxx XferOptions if any */\r
+ I2C_ConvertOtherXferOptions(hi2c);\r
+\r
+ /* Update xfermode accordingly if no reload is necessary */\r
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)\r
+ {\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+ }\r
+\r
+ if (hi2c->XferSize > 0U)\r
+ {\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Send Slave Address and set NBYTES to read */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);\r
+\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR and NACK interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Update Transfer ISR function pointer */\r
+ hi2c->XferISR = I2C_Master_ISR_IT;\r
+\r
+ /* Send Slave Address */\r
+ /* Set NBYTES to read and generate START condition */\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r
+ /* possible to enable all of these */\r
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+ }\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+ /* and then toggle the HAL slave RX state to TX state */\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+ {\r
+ /* Disable associated Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+ /* Abort DMA Xfer if any */\r
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+\r
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r
+ {\r
+ /* Clear ADDR flag after prepare the transfer parameters */\r
+ /* This action will generate an acknowledge to the Master */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* REnable ADDR interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r
+\r
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+ /* and then toggle the HAL slave RX state to TX state */\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+ {\r
+ /* Disable associated Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+ {\r
+ /* Abort DMA Xfer if any */\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+ {\r
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+ /* Abort DMA Xfer if any */\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Slave_ISR_DMA;\r
+\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Reset XferSize */\r
+ hi2c->XferSize = 0;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r
+ {\r
+ /* Clear ADDR flag after prepare the transfer parameters */\r
+ /* This action will generate an acknowledge to the Master */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* Enable ERR, STOP, NACK, ADDR interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+ /* and then toggle the HAL slave TX state to RX state */\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+ {\r
+ /* Disable associated Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+ /* Abort DMA Xfer if any */\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+\r
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r
+ {\r
+ /* Clear ADDR flag after prepare the transfer parameters */\r
+ /* This action will generate an acknowledge to the Master */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* REnable ADDR interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA\r
+ * @note This interface allow to manage repeated start condition when a direction change during transfer\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param pData Pointer to data buffer\r
+ * @param Size Amount of data to be sent\r
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r
+{\r
+ HAL_StatusTypeDef dmaxferstatus;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r
+\r
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+ {\r
+ if ((pData == NULL) || (Size == 0U))\r
+ {\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r
+ /* and then toggle the HAL slave TX state to RX state */\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+ {\r
+ /* Disable associated Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+ {\r
+ /* Abort DMA Xfer if any */\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+ {\r
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+ /* Abort DMA Xfer if any */\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+\r
+ /* Enable Address Acknowledge */\r
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r
+\r
+ /* Prepare transfer parameters */\r
+ hi2c->pBuffPtr = pData;\r
+ hi2c->XferCount = Size;\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ hi2c->XferOptions = XferOptions;\r
+ hi2c->XferISR = I2C_Slave_ISR_DMA;\r
+\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA transfer complete callback */\r
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r
+\r
+ /* Set the unused DMA callbacks to NULL */\r
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Enable the DMA stream */\r
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (dmaxferstatus == HAL_OK)\r
+ {\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Reset XferSize */\r
+ hi2c->XferSize = 0;\r
+ }\r
+ else\r
+ {\r
+ /* Update I2C state */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Update I2C error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r
+ {\r
+ /* Clear ADDR flag after prepare the transfer parameters */\r
+ /* This action will generate an acknowledge to the Master */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ /* REnable ADDR interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r
+\r
+ /* Enable DMA Request */\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the Address listen mode with Interrupt.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)\r
+{\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+\r
+ /* Enable the Address Match interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Disable the Address listen mode with Interrupt.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */\r
+ uint32_t tmp;\r
+\r
+ /* Disable Address listen mode only if a transfer is not ongoing */\r
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)\r
+ {\r
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;\r
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Disable the Address Match interrupt */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Abort a master I2C IT or DMA process communication with Interrupt.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)\r
+{\r
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ /* Set State at HAL_I2C_STATE_ABORT */\r
+ hi2c->State = HAL_I2C_STATE_ABORT;\r
+\r
+ /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */\r
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */\r
+ I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Note : The I2C interrupts must be enabled after unlocking current process\r
+ to avoid the risk of I2C interrupt handle execution before current\r
+ process unlock */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Wrong usage of abort function */\r
+ /* This function should be used only in case of abort monitored by master device */\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief This function handles I2C event interrupt request.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Get current IT Flags and IT sources value */\r
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);\r
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
+\r
+ /* I2C events treatment -------------------------------------*/\r
+ if (hi2c->XferISR != NULL)\r
+ {\r
+ hi2c->XferISR(hi2c, itflags, itsources);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C error interrupt request.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\r
+{\r
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);\r
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r
+ uint32_t tmperror;\r
+\r
+ /* I2C Bus error interrupt occurred ------------------------------------*/\r
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;\r
+\r
+ /* Clear BERR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\r
+ }\r
+\r
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/\r
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;\r
+\r
+ /* Clear OVR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\r
+ }\r
+\r
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/\r
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;\r
+\r
+ /* Clear ARLO flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\r
+ }\r
+\r
+ /* Store current volatile hi2c->ErrorCode, misra rule */\r
+ tmperror = hi2c->ErrorCode;\r
+\r
+ /* Call the Error Callback in case of Error detected */\r
+ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)\r
+ {\r
+ I2C_ITError(hi2c, tmperror);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Master Tx Transfer completed callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MasterTxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Master Rx Transfer completed callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MasterRxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/** @brief Slave Tx Transfer completed callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Slave Rx Transfer completed callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Slave Address Match callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION\r
+ * @param AddrMatchCode Address Match Code\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+ UNUSED(TransferDirection);\r
+ UNUSED(AddrMatchCode);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_AddrCallback() could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Listen Complete callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_ListenCpltCallback() could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Memory Tx Transfer completed callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MemTxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Memory Rx Transfer completed callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_MemRxCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief I2C error callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief I2C abort callback.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval None\r
+ */\r
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(hi2c);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r
+ * @brief Peripheral State, Mode and Error functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Peripheral State, Mode and Error functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection permit to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the I2C handle state.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @retval HAL state\r
+ */\r
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Return I2C handle state */\r
+ return hi2c->State;\r
+}\r
+\r
+/**\r
+ * @brief Returns the I2C Master, Slave, Memory or no mode.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for I2C module\r
+ * @retval HAL mode\r
+ */\r
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)\r
+{\r
+ return hi2c->Mode;\r
+}\r
+\r
+/**\r
+* @brief Return the I2C error code.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+* @retval I2C Error Code\r
+*/\r
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\r
+{\r
+ return hi2c->ErrorCode;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @param ITSources Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+ uint16_t devaddress;\r
+ uint32_t tmpITFlags = ITFlags;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Set corresponding Error Code */\r
+ /* No need to generate STOP, it is automatically done */\r
+ /* Error callback will be send during stop flag treatment */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ }\r
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))\r
+ {\r
+ /* Remove RXNE flag on temporary variable as read done */\r
+ tmpITFlags &= ~I2C_FLAG_RXNE;\r
+\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))\r
+ {\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+ {\r
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))\r
+ {\r
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+ {\r
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);\r
+ }\r
+ else\r
+ {\r
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call TxCpltCallback() if no stop mode is set */\r
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+ {\r
+ /* Call I2C Master Sequential complete process */\r
+ I2C_ITMasterSeqCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Wrong size Status regarding TCR flag event */\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+ }\r
+ }\r
+ }\r
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+ {\r
+ if (hi2c->XferCount == 0U)\r
+ {\r
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+ {\r
+ /* Generate a stop condition in case of no transfer option */\r
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Call I2C Master Sequential complete process */\r
+ I2C_ITMasterSeqCplt(hi2c);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wrong size Status regarding TC flag event */\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Master complete process */\r
+ I2C_ITMasterCplt(hi2c, tmpITFlags);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @param ITSources Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+ uint32_t tmpoptions = hi2c->XferOptions;\r
+ uint32_t tmpITFlags = ITFlags;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Check that I2C transfer finished */\r
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
+ /* Mean XferCount == 0*/\r
+ /* So clear Flag NACKF only */\r
+ if (hi2c->XferCount == 0U)\r
+ {\r
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */\r
+ {\r
+ /* Call I2C Listen complete process */\r
+ I2C_ITListenCplt(hi2c, tmpITFlags);\r
+ }\r
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+\r
+ /* Last Byte is Transmitted */\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSeqCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, hi2c->ErrorCode);\r
+ }\r
+ }\r
+ }\r
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))\r
+ {\r
+ if (hi2c->XferCount > 0U)\r
+ {\r
+ /* Remove RXNE flag on temporary variable as read done */\r
+ tmpITFlags &= ~I2C_FLAG_RXNE;\r
+\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+\r
+ if ((hi2c->XferCount == 0U) && \\r
+ (tmpoptions != I2C_NO_OPTION_FRAME))\r
+ {\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSeqCplt(hi2c);\r
+ }\r
+ }\r
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))\r
+ {\r
+ I2C_ITAddrCplt(hi2c, tmpITFlags);\r
+ }\r
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))\r
+ {\r
+ /* Write data to TXDR only if XferCount not reach "0" */\r
+ /* A TXIS flag can be set, during STOP treatment */\r
+ /* Check if all Datas have already been sent */\r
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */\r
+ if (hi2c->XferCount > 0U)\r
+ {\r
+ /* Write data to TXDR */\r
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ hi2c->XferCount--;\r
+ hi2c->XferSize--;\r
+ }\r
+ else\r
+ {\r
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))\r
+ {\r
+ /* Last Byte is Transmitted */\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSeqCplt(hi2c);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ /* Check if STOPF is set */\r
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Slave complete process */\r
+ I2C_ITSlaveCplt(hi2c, tmpITFlags);\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @param ITSources Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+ uint16_t devaddress;\r
+ uint32_t xfermode;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Set corresponding Error Code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+ /* No need to generate STOP, it is automatically done */\r
+ /* But enable STOP interrupt, to treat it */\r
+ /* Error callback will be send during stop flag treatment */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+\r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+ }\r
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+ {\r
+ /* Disable TC interrupt */\r
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);\r
+\r
+ if (hi2c->XferCount != 0U)\r
+ {\r
+ /* Recover Slave address */\r
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);\r
+\r
+ /* Prepare the new XferSize to transfer */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ xfermode = I2C_RELOAD_MODE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+ {\r
+ xfermode = hi2c->XferOptions;\r
+ }\r
+ else\r
+ {\r
+ xfermode = I2C_AUTOEND_MODE;\r
+ }\r
+ }\r
+\r
+ /* Set the new XferSize in Nbytes register */\r
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r
+\r
+ /* Update XferCount value */\r
+ hi2c->XferCount -= hi2c->XferSize;\r
+\r
+ /* Enable DMA Request */\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+ {\r
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r
+ }\r
+ else\r
+ {\r
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Call TxCpltCallback() if no stop mode is set */\r
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+ {\r
+ /* Call I2C Master Sequential complete process */\r
+ I2C_ITMasterSeqCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Wrong size Status regarding TCR flag event */\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+ }\r
+ }\r
+ }\r
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))\r
+ {\r
+ if (hi2c->XferCount == 0U)\r
+ {\r
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r
+ {\r
+ /* Generate a stop condition in case of no transfer option */\r
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)\r
+ {\r
+ /* Generate Stop */\r
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;\r
+ }\r
+ else\r
+ {\r
+ /* Call I2C Master Sequential complete process */\r
+ I2C_ITMasterSeqCplt(hi2c);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wrong size Status regarding TC flag event */\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r
+ }\r
+ }\r
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Master complete process */\r
+ I2C_ITMasterCplt(hi2c, ITFlags);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @param ITSources Interrupt sources enabled.\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r
+{\r
+ uint32_t tmpoptions = hi2c->XferOptions;\r
+ uint32_t treatdmanack = 0U;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))\r
+ {\r
+ /* Check that I2C transfer finished */\r
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r
+ /* Mean XferCount == 0 */\r
+ /* So clear Flag NACKF only */\r
+ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||\r
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))\r
+ {\r
+ /* Split check of hdmarx, for MISRA compliance */\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)\r
+ {\r
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)\r
+ {\r
+ treatdmanack = 1U;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Split check of hdmatx, for MISRA compliance */\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)\r
+ {\r
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)\r
+ {\r
+ treatdmanack = 1U;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (treatdmanack == 1U)\r
+ {\r
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */\r
+ {\r
+ /* Call I2C Listen complete process */\r
+ I2C_ITListenCplt(hi2c, ITFlags);\r
+ }\r
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+\r
+ /* Last Byte is Transmitted */\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSeqCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+\r
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, hi2c->ErrorCode);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Only Clear NACK Flag, no DMA treatment is pending */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+ }\r
+ }\r
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))\r
+ {\r
+ I2C_ITAddrCplt(hi2c, ITFlags);\r
+ }\r
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))\r
+ {\r
+ /* Call I2C Slave complete process */\r
+ I2C_ITSlaveCplt(hi2c, ITFlags);\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Master sends target device address followed by internal memory address for write request.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param Timeout Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+ /* Wait until TXIS flag is set */\r
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* If Memory address size is 8Bit */\r
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+ {\r
+ /* Send Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+ /* If Memory address size is 16Bit */\r
+ else\r
+ {\r
+ /* Send MSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
+\r
+ /* Wait until TXIS flag is set */\r
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Send LSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+\r
+ /* Wait until TCR flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Master sends target device address followed by internal memory address for read request.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param DevAddress Target device address: The device 7 bits address value\r
+ * in datasheet must be shifted to the left before calling the interface\r
+ * @param MemAddress Internal memory address\r
+ * @param MemAddSize Size of internal memory address\r
+ * @param Timeout Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);\r
+\r
+ /* Wait until TXIS flag is set */\r
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* If Memory address size is 8Bit */\r
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r
+ {\r
+ /* Send Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+ /* If Memory address size is 16Bit */\r
+ else\r
+ {\r
+ /* Send MSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r
+\r
+ /* Wait until TXIS flag is set */\r
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Send LSB of Memory Address */\r
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r
+ }\r
+\r
+ /* Wait until TC flag is set */\r
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief I2C Address complete process callback.\r
+ * @param hi2c I2C handle.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ uint8_t transferdirection;\r
+ uint16_t slaveaddrcode;\r
+ uint16_t ownadd1code;\r
+ uint16_t ownadd2code;\r
+\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(ITFlags);\r
+\r
+ /* In case of Listen state, need to inform upper layer of address match code event */\r
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\r
+ {\r
+ transferdirection = I2C_GET_DIR(hi2c);\r
+ slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);\r
+ ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);\r
+ ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);\r
+\r
+ /* If 10bits addressing mode is selected */\r
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r
+ {\r
+ if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))\r
+ {\r
+ slaveaddrcode = ownadd1code;\r
+ hi2c->AddrEventCount++;\r
+ if (hi2c->AddrEventCount == 2U)\r
+ {\r
+ /* Reset Address Event counter */\r
+ hi2c->AddrEventCount = 0U;\r
+\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call Slave Addr callback */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#else\r
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ slaveaddrcode = ownadd2code;\r
+\r
+ /* Disable ADDR Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call Slave Addr callback */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#else\r
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* else 7 bits addressing mode is selected */\r
+ else\r
+ {\r
+ /* Disable ADDR Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call Slave Addr callback */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#else\r
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* Else clear address flag only */\r
+ else\r
+ {\r
+ /* Clear ADDR flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Master sequential complete process.\r
+ * @param hi2c I2C handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Reset I2C handle mode */\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* No Generate Stop, to permit restart mode */\r
+ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->MasterTxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_MasterTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
+ else\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->MasterRxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_MasterRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Slave sequential complete process.\r
+ * @param hi2c I2C handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* Reset I2C handle mode */\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r
+ {\r
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\r
+\r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->SlaveTxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r
+ {\r
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\r
+\r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->SlaveRxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Master complete process.\r
+ * @param hi2c I2C handle.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ uint32_t tmperror;\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ /* Reset handle parameters */\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->XferISR = NULL;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+\r
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)\r
+ {\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Set acknowledge error code */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+\r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+\r
+ /* Disable Interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r
+\r
+ /* Store current volatile hi2c->ErrorCode, misra rule */\r
+ tmperror = hi2c->ErrorCode;\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, hi2c->ErrorCode);\r
+ }\r
+ /* hi2c->State == HAL_I2C_STATE_BUSY_TX */\r
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->MemTxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_MemTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->MasterTxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_MasterTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->MemRxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_MemRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->MasterRxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_MasterRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Slave complete process.\r
+ * @param hi2c I2C handle.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);\r
+ uint32_t tmpITFlags = ITFlags;\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Disable all interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r
+\r
+ /* Disable Address Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+\r
+ /* If a DMA is ongoing, Update handle size context */\r
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)\r
+ {\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);\r
+ }\r
+ }\r
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)\r
+ {\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Do nothing */\r
+ }\r
+\r
+ /* Store Last receive data if any */\r
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)\r
+ {\r
+ /* Remove RXNE flag on temporary variable as read done */\r
+ tmpITFlags &= ~I2C_FLAG_RXNE;\r
+\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ if ((hi2c->XferSize > 0U))\r
+ {\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+ }\r
+ }\r
+\r
+ /* All data are not transferred, so set error code accordingly */\r
+ if (hi2c->XferCount != 0U)\r
+ {\r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferISR = NULL;\r
+\r
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, hi2c->ErrorCode);\r
+\r
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)\r
+ {\r
+ /* Call I2C Listen complete process */\r
+ I2C_ITListenCplt(hi2c, tmpITFlags);\r
+ }\r
+ }\r
+ else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r
+ {\r
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */\r
+ I2C_ITSlaveSeqCplt(hi2c);\r
+\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->ListenCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_ListenCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->SlaveRxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_SlaveRxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->SlaveTxCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_SlaveTxCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Listen complete process.\r
+ * @param hi2c I2C handle.\r
+ * @param ITFlags Interrupt flags to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r
+{\r
+ /* Reset handle parameters */\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferISR = NULL;\r
+\r
+ /* Store Last receive data if any */\r
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)\r
+ {\r
+ /* Read data from RXDR */\r
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;\r
+\r
+ /* Increment Buffer pointer */\r
+ hi2c->pBuffPtr++;\r
+\r
+ if ((hi2c->XferSize > 0U))\r
+ {\r
+ hi2c->XferSize--;\r
+ hi2c->XferCount--;\r
+\r
+ /* Set ErrorCode corresponding to a Non-Acknowledge */\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ }\r
+ }\r
+\r
+ /* Disable all Interrupts*/\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+\r
+ /* Clear NACK Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->ListenCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_ListenCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief I2C interrupts error process.\r
+ * @param hi2c I2C handle.\r
+ * @param ErrorCode Error code to handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)\r
+{\r
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;\r
+\r
+ /* Reset handle parameters */\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r
+ hi2c->XferCount = 0U;\r
+\r
+ /* Set new error code */\r
+ hi2c->ErrorCode |= ErrorCode;\r
+\r
+ /* Disable Interrupts */\r
+ if ((tmpstate == HAL_I2C_STATE_LISTEN) ||\r
+ (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||\r
+ (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))\r
+ {\r
+ /* Disable all interrupts, except interrupts related to LISTEN state */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+\r
+ /* keep HAL_I2C_STATE_LISTEN if set */\r
+ hi2c->State = HAL_I2C_STATE_LISTEN;\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->XferISR = I2C_Slave_ISR_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable all interrupts */\r
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r
+\r
+ /* If state is an abort treatment on goind, don't change state */\r
+ /* This change will be do later */\r
+ if (hi2c->State != HAL_I2C_STATE_ABORT)\r
+ {\r
+ /* Set HAL_I2C_STATE_READY */\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ }\r
+ hi2c->PreviousState = I2C_STATE_NONE;\r
+ hi2c->XferISR = NULL;\r
+ }\r
+\r
+ /* Abort DMA TX transfer if any */\r
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Abort DMA TX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r
+ {\r
+ /* Call Directly XferAbortCallback function in case of error */\r
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r
+ }\r
+ }\r
+ }\r
+ /* Abort DMA RX transfer if any */\r
+ else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r
+ {\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ /* Set the I2C DMA Abort callback :\r
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Abort DMA RX */\r
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r
+ {\r
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */\r
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r
+ }\r
+ }\r
+ }\r
+ else if (hi2c->State == HAL_I2C_STATE_ABORT)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->AbortCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_AbortCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->ErrorCallback(hi2c);\r
+#else\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief I2C Tx data register flush process.\r
+ * @param hi2c I2C handle.\r
+ * @retval None\r
+ */\r
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* If a pending TXIS flag is set */\r
+ /* Write a dummy data in TXDR to clear it */\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)\r
+ {\r
+ hi2c->Instance->TXDR = 0x00U;\r
+ }\r
+\r
+ /* Flush TX register if not empty */\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)\r
+ {\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C master transmit process complete callback.\r
+ * @param hdma DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+ /* If last transfer, enable STOP interrupt */\r
+ if (hi2c->XferCount == 0U)\r
+ {\r
+ /* Enable STOP interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+ }\r
+ /* else prepare a new DMA transfer and enable TCReload interrupt */\r
+ else\r
+ {\r
+ /* Update Buffer pointer */\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+\r
+ /* Set the XferSize to transfer */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
+ }\r
+ else\r
+ {\r
+ /* Enable TC interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C slave transmit process complete callback.\r
+ * @param hdma DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+ uint32_t tmpoptions = hi2c->XferOptions;\r
+\r
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))\r
+ {\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r
+\r
+ /* Last Byte is Transmitted */\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSeqCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* No specific action, Master fully manage the generation of STOP condition */\r
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
+ /* So STOP condition should be manage through Interrupt treatment */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C master receive process complete callback.\r
+ * @param hdma DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+ /* If last transfer, enable STOP interrupt */\r
+ if (hi2c->XferCount == 0U)\r
+ {\r
+ /* Enable STOP interrupt */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r
+ }\r
+ /* else prepare a new DMA transfer and enable TCReload interrupt */\r
+ else\r
+ {\r
+ /* Update Buffer pointer */\r
+ hi2c->pBuffPtr += hi2c->XferSize;\r
+\r
+ /* Set the XferSize to transfer */\r
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)\r
+ {\r
+ hi2c->XferSize = MAX_NBYTE_SIZE;\r
+ }\r
+ else\r
+ {\r
+ hi2c->XferSize = hi2c->XferCount;\r
+ }\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
+ }\r
+ else\r
+ {\r
+ /* Enable TC interrupts */\r
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C slave receive process complete callback.\r
+ * @param hdma DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+ uint32_t tmpoptions = hi2c->XferOptions;\r
+\r
+ if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \\r
+ (tmpoptions != I2C_NO_OPTION_FRAME))\r
+ {\r
+ /* Disable DMA Request */\r
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r
+\r
+ /* Call I2C Slave Sequential complete process */\r
+ I2C_ITSlaveSeqCplt(hi2c);\r
+ }\r
+ else\r
+ {\r
+ /* No specific action, Master fully manage the generation of STOP condition */\r
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */\r
+ /* So STOP condition should be manage through Interrupt treatment */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C communication error callback.\r
+ * @param hdma DMA handle\r
+ * @retval None\r
+ */\r
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ uint32_t treatdmaerror = 0U;\r
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+ if (hi2c->hdmatx != NULL)\r
+ {\r
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)\r
+ {\r
+ treatdmaerror = 1U;\r
+ }\r
+ }\r
+\r
+ if (hi2c->hdmarx != NULL)\r
+ {\r
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)\r
+ {\r
+ treatdmaerror = 1U;\r
+ }\r
+ }\r
+\r
+ /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */\r
+ if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))\r
+ {\r
+ /* Disable Acknowledge */\r
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief DMA I2C communication abort callback\r
+ * (To be called at end of DMA Abort procedure).\r
+ * @param hdma DMA handle.\r
+ * @retval None\r
+ */\r
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)\r
+{\r
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\r
+\r
+ /* Reset AbortCpltCallback */\r
+ hi2c->hdmatx->XferAbortCallback = NULL;\r
+ hi2c->hdmarx->XferAbortCallback = NULL;\r
+\r
+ /* Check if come from abort from user */\r
+ if (hi2c->State == HAL_I2C_STATE_ABORT)\r
+ {\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->AbortCpltCallback(hi2c);\r
+#else\r
+ HAL_I2C_AbortCpltCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+ else\r
+ {\r
+ /* Call the corresponding callback to inform upper layer of End of Transfer */\r
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\r
+ hi2c->ErrorCallback(hi2c);\r
+#else\r
+ HAL_I2C_ErrorCallback(hi2c);\r
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Flag Specifies the I2C flag to check.\r
+ * @param Status The new Flag status (SET or RESET).\r
+ * @param Timeout Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)\r
+ {\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check for the Timeout */\r
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\r
+ {\r
+ /* Check if a NACK is detected */\r
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check if a STOPF is detected */\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r
+ {\r
+ /* Check if an RXNE is pending */\r
+ /* Store Last receive data if any */\r
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))\r
+ {\r
+ /* Return HAL_OK */\r
+ /* The Reading of data from RXDR will be done in caller function */\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /* Check for the Timeout */\r
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief This function handles Acknowledge failed detection during an I2C Communication.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param Timeout Timeout duration\r
+ * @param Tickstart Tick start value\r
+ * @retval HAL status\r
+ */\r
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r
+{\r
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r
+ {\r
+ /* Wait until STOP Flag is reset */\r
+ /* AutoEnd should be initiate after AF */\r
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r
+ {\r
+ /* Check for the Timeout */\r
+ if (Timeout != HAL_MAX_DELAY)\r
+ {\r
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\r
+ {\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Clear NACKF Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r
+\r
+ /* Clear STOP Flag */\r
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r
+\r
+ /* Flush TX register */\r
+ I2C_Flush_TXDR(hi2c);\r
+\r
+ /* Clear Configuration Register 2 */\r
+ I2C_RESET_CR2(hi2c);\r
+\r
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+ hi2c->Mode = HAL_I2C_MODE_NONE;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_ERROR;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).\r
+ * @param hi2c I2C handle.\r
+ * @param DevAddress Specifies the slave address to be programmed.\r
+ * @param Size Specifies the number of bytes to be programmed.\r
+ * This parameter must be a value between 0 and 255.\r
+ * @param Mode New state of the I2C START condition generation.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_RELOAD_MODE Enable Reload mode .\r
+ * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.\r
+ * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.\r
+ * @param Request New state of the I2C START condition generation.\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.\r
+ * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).\r
+ * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.\r
+ * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.\r
+ * @retval None\r
+ */\r
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_TRANSFER_MODE(Mode));\r
+ assert_param(IS_TRANSFER_REQUEST(Request));\r
+\r
+ /* update CR2 register */\r
+ MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \\r
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));\r
+}\r
+\r
+/**\r
+ * @brief Manage the enabling of Interrupts.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r
+ * @retval None\r
+ */\r
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
+{\r
+ uint32_t tmpisr = 0U;\r
+\r
+ if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \\r
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))\r
+ {\r
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+ {\r
+ /* Enable ERR, STOP, NACK and ADDR interrupts */\r
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
+ {\r
+ /* Enable ERR and NACK interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+ {\r
+ /* Enable STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
+ {\r
+ /* Enable TC interrupts */\r
+ tmpisr |= I2C_IT_TCI;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+ {\r
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */\r
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
+ {\r
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
+ {\r
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+ {\r
+ /* Enable STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI;\r
+ }\r
+ }\r
+\r
+ /* Enable interrupts only at the end */\r
+ /* to avoid the risk of I2C interrupt handle execution before */\r
+ /* all interrupts requested done */\r
+ __HAL_I2C_ENABLE_IT(hi2c, tmpisr);\r
+}\r
+\r
+/**\r
+ * @brief Manage the disabling of Interrupts.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2C.\r
+ * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r
+ * @retval None\r
+ */\r
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r
+{\r
+ uint32_t tmpisr = 0U;\r
+\r
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r
+ {\r
+ /* Disable TC and TXI interrupts */\r
+ tmpisr |= I2C_IT_TCI | I2C_IT_TXI;\r
+\r
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)\r
+ {\r
+ /* Disable NACK and STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r
+ {\r
+ /* Disable TC and RXI interrupts */\r
+ tmpisr |= I2C_IT_TCI | I2C_IT_RXI;\r
+\r
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)\r
+ {\r
+ /* Disable NACK and STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r
+ {\r
+ /* Disable ADDR, NACK and STOP interrupts */\r
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r
+ {\r
+ /* Enable ERR and NACK interrupts */\r
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r
+ {\r
+ /* Enable STOP interrupts */\r
+ tmpisr |= I2C_IT_STOPI;\r
+ }\r
+\r
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r
+ {\r
+ /* Enable TC interrupts */\r
+ tmpisr |= I2C_IT_TCI;\r
+ }\r
+\r
+ /* Disable interrupts only at the end */\r
+ /* to avoid a breaking situation like at "t" time */\r
+ /* all disable interrupts request are not done */\r
+ __HAL_I2C_DISABLE_IT(hi2c, tmpisr);\r
+}\r
+\r
+/**\r
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.\r
+ * @param hi2c I2C handle.\r
+ * @retval None\r
+ */\r
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)\r
+{\r
+ /* if user set XferOptions to I2C_OTHER_FRAME */\r
+ /* it request implicitly to generate a restart condition */\r
+ /* set XferOptions to I2C_FIRST_FRAME */\r
+ if (hi2c->XferOptions == I2C_OTHER_FRAME)\r
+ {\r
+ hi2c->XferOptions = I2C_FIRST_FRAME;\r
+ }\r
+ /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */\r
+ /* it request implicitly to generate a restart condition */\r
+ /* then generate a stop condition at the end of transfer */\r
+ /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */\r
+ else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)\r
+ {\r
+ hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;\r
+ }\r
+ else\r
+ {\r
+ /* Nothing to do */\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_i2c_ex.c\r
+ * @author MCD Application Team\r
+ * @brief I2C Extended HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of I2C Extended peripheral:\r
+ * + Extended features functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### I2C peripheral Extended features #####\r
+ ==============================================================================\r
+\r
+ [..] Comparing to other previous devices, the I2C interface for STM32F7xx\r
+ devices contains the following additional features\r
+\r
+ (+) Possibility to disable or enable Analog Noise Filter\r
+ (+) Use of a configured Digital Noise Filter\r
+ (+) Disable or enable Fast Mode Plus\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..] This driver provides functions to:\r
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()\r
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()\r
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :\r
+ (++) HAL_I2CEx_EnableFastModePlus()\r
+ (++) HAL_I2CEx_DisableFastModePlus()\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx I2CEx\r
+ * @brief I2C Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions\r
+ * @brief Extended features functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended features functions #####\r
+ ===============================================================================\r
+ [..] This section provides functions allowing to:\r
+ (+) Configure Noise Filters\r
+ (+) Configure Fast Mode Plus\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure I2C Analog noise filter.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2Cx peripheral.\r
+ * @param AnalogFilter New state of the Analog filter.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+\r
+ /* Reset I2Cx ANOFF bit */\r
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);\r
+\r
+ /* Set analog filter bit*/\r
+ hi2c->Instance->CR1 |= AnalogFilter;\r
+\r
+ __HAL_I2C_ENABLE(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure I2C Digital noise filter.\r
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains\r
+ * the configuration information for the specified I2Cx peripheral.\r
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\r
+{\r
+ uint32_t tmpreg;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\r
+\r
+ if (hi2c->State == HAL_I2C_STATE_READY)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_BUSY;\r
+\r
+ /* Disable the selected I2C peripheral */\r
+ __HAL_I2C_DISABLE(hi2c);\r
+\r
+ /* Get the old register value */\r
+ tmpreg = hi2c->Instance->CR1;\r
+\r
+ /* Reset I2Cx DNF bits [11:8] */\r
+ tmpreg &= ~(I2C_CR1_DNF);\r
+\r
+ /* Set I2Cx DNF coefficient */\r
+ tmpreg |= DigitalFilter << 8U;\r
+\r
+ /* Store the new register value */\r
+ hi2c->Instance->CR1 = tmpreg;\r
+\r
+ __HAL_I2C_ENABLE(hi2c);\r
+\r
+ hi2c->State = HAL_I2C_STATE_READY;\r
+\r
+ /* Process Unlocked */\r
+ __HAL_UNLOCK(hi2c);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+}\r
+\r
+#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)\r
+/**\r
+ * @brief Enable the I2C fast mode plus driving capability.\r
+ * @param ConfigFastModePlus Selects the pin.\r
+ * This parameter can be one of the @ref I2CEx_FastModePlus values\r
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected\r
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r
+ * on each one of the following pins PB6, PB7, PB8 and PB9.\r
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r
+ * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r
+ * @note For all I2C2 pins fast mode plus driving capability can be enabled\r
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.\r
+ * @note For all I2C3 pins fast mode plus driving capability can be enabled\r
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.\r
+ * @note For all I2C4 pins fast mode plus driving capability can be enabled\r
+ * only by using I2C_FASTMODEPLUS_I2C4 parameter.\r
+ * @retval None\r
+ */\r
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
+\r
+ /* Enable SYSCFG clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ /* Enable fast mode plus driving capability for selected pin */\r
+ SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r
+}\r
+\r
+/**\r
+ * @brief Disable the I2C fast mode plus driving capability.\r
+ * @param ConfigFastModePlus Selects the pin.\r
+ * This parameter can be one of the @ref I2CEx_FastModePlus values\r
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected\r
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r
+ * on each one of the following pins PB6, PB7, PB8 and PB9.\r
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r
+ * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r
+ * @note For all I2C2 pins fast mode plus driving capability can be disabled\r
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.\r
+ * @note For all I2C3 pins fast mode plus driving capability can be disabled\r
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.\r
+ * @note For all I2C4 pins fast mode plus driving capability can be disabled\r
+ * only by using I2C_FASTMODEPLUS_I2C4 parameter.\r
+ * @retval None\r
+ */\r
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r
+\r
+ /* Enable SYSCFG clock */\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ /* Disable fast mode plus driving capability for selected pin */\r
+ CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r
+}\r
+\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr.c\r
+ * @author MCD Application Team\r
+ * @brief PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of the Power Controller (PWR) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions \r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR PWR\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWR_Private_Constants\r
+ * @{\r
+ */\r
+ \r
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r
+ * @{\r
+ */ \r
+#define PVD_MODE_IT ((uint32_t)0x00010000U)\r
+#define PVD_MODE_EVT ((uint32_t)0x00020000U)\r
+#define PVD_RISING_EDGE ((uint32_t)0x00000001U)\r
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask\r
+ * @{\r
+ */ \r
+#define PWR_EWUP_MASK ((uint32_t)0x00003F00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup PWR_Exported_Functions PWR Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r
+ * @brief Initialization and de-initialization functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ After reset, the backup domain (RTC registers, RTC backup data \r
+ registers and backup SRAM) is protected against possible unwanted \r
+ write accesses. \r
+ To enable access to the RTC Domain and RTC registers, proceed as follows:\r
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the\r
+ __HAL_RCC_PWR_CLK_ENABLE() macro.\r
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r
+ \r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DeInit(void)\r
+{\r
+ __HAL_RCC_PWR_FORCE_RESET();\r
+ __HAL_RCC_PWR_RELEASE_RESET();\r
+}\r
+\r
+/**\r
+ * @brief Enables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableBkUpAccess(void)\r
+{\r
+ /* Enable access to RTC and backup registers */\r
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @brief Disables access to the backup domain (RTC registers, RTC \r
+ * backup data registers and backup SRAM).\r
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r
+ * Backup Domain Access should be kept enabled.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableBkUpAccess(void)\r
+{\r
+ /* Disable access to RTC and backup registers */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \r
+ * @brief Low Power modes configuration functions \r
+ *\r
+@verbatim\r
+\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ \r
+ *** PVD configuration ***\r
+ =========================\r
+ [..]\r
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a \r
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower \r
+ than the PVD threshold. This event is internally connected to the EXTI \r
+ line16 and can generate an interrupt if enabled. This is done through\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r
+ (+) The PVD is stopped in Standby mode.\r
+\r
+ *** Wake-up pin configuration ***\r
+ ================================\r
+ [..]\r
+ (+) Wake-up pin is used to wake up the system from Standby mode. This pin is \r
+ forced in input pull-down configuration and is active on rising edges.\r
+ (+) There are up to 6 Wake-up pin in the STM32F7 devices family\r
+\r
+ *** Low Power modes configuration ***\r
+ =====================================\r
+ [..]\r
+ The devices feature 3 low-power modes:\r
+ (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.\r
+ (+) Stop mode: all clocks are stopped, regulator running, regulator \r
+ in low power mode\r
+ (+) Standby mode: 1.2V domain powered off.\r
+ \r
+ *** Sleep mode ***\r
+ ==================\r
+ [..]\r
+ (+) Entry:\r
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)\r
+ functions with\r
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ \r
+ -@@- The Regulator parameter is not used for the STM32F7 family \r
+ and is kept as parameter just to maintain compatibility with the \r
+ lower power families (STM32L).\r
+ (+) Exit:\r
+ Any peripheral interrupt acknowledged by the nested vectored interrupt \r
+ controller (NVIC) can wake up the device from Sleep mode.\r
+\r
+ *** Stop mode ***\r
+ =================\r
+ [..]\r
+ In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents \r
+ are preserved.\r
+ The voltage regulator can be configured either in normal or low-power mode.\r
+ To minimize the consumption In Stop mode, FLASH can be powered off before \r
+ entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\r
+ It can be switched on again by software after exiting the Stop mode using\r
+ the HAL_PWREx_DisableFlashPowerDown() function. \r
+\r
+ (+) Entry:\r
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) \r
+ function with:\r
+ (++) Main regulator ON.\r
+ (++) Low Power regulator ON.\r
+ (+) Exit:\r
+ Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r
+\r
+ *** Standby mode ***\r
+ ====================\r
+ [..]\r
+ (+)\r
+ The Standby mode allows to achieve the lowest power consumption. It is based \r
+ on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. \r
+ The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \r
+ the HSE oscillator are also switched off. SRAM and register contents are lost \r
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby \r
+ circuitry.\r
+ \r
+ The voltage regulator is OFF.\r
+ \r
+ (++) Entry:\r
+ (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r
+ (++) Exit:\r
+ (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r
+ wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r
+\r
+ *** Auto-wakeup (AWU) from low-power mode ***\r
+ =============================================\r
+ [..]\r
+ \r
+ (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r
+ Wakeup event, a tamper event or a time-stamp event, without depending on \r
+ an external interrupt (Auto-wakeup mode).\r
+\r
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes\r
+ \r
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \r
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r
+\r
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r
+ is necessary to configure the RTC to detect the tamper or time stamp event using the\r
+ HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r
+ \r
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration\r
+ * information for the PVD.\r
+ * @note Refer to the electrical characteristics of your device datasheet for\r
+ * more details about the voltage threshold corresponding to each \r
+ * detection level.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r
+ \r
+ /* Set PLS[7:5] bits according to PVDLevel value */\r
+ MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);\r
+ \r
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \r
+\r
+ /* Configure interrupt mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();\r
+ }\r
+ \r
+ /* Configure event mode */\r
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r
+ }\r
+ \r
+ /* Configure the edge */\r
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r
+ }\r
+ \r
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r
+ {\r
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnablePVD(void)\r
+{\r
+ /* Enable the power voltage detector */\r
+ SET_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Power Voltage Detector(PVD).\r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisablePVD(void)\r
+{\r
+ /* Disable the power voltage detector */\r
+ CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);\r
+}\r
+\r
+/**\r
+ * @brief Enable the WakeUp PINx functionality.\r
+ * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.\r
+ * This parameter can be one of the following legacy values, which sets the default polarity: \r
+ * detection on high level (rising edge):\r
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 \r
+ * or one of the following value where the user can explicitly states the enabled pin and\r
+ * the chosen polarity \r
+ * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW \r
+ * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW \r
+ * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW \r
+ * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r
+ * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW \r
+ * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW \r
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r
+ \r
+ /* Enable wake-up pin */\r
+ SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));\r
+ \r
+ /* Specifies the Wake-Up pin polarity for the event detection\r
+ (rising or falling edge) */\r
+ MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));\r
+}\r
+\r
+/**\r
+ * @brief Disables the WakeUp PINx functionality.\r
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_WAKEUP_PIN1\r
+ * @arg PWR_WAKEUP_PIN2\r
+ * @arg PWR_WAKEUP_PIN3\r
+ * @arg PWR_WAKEUP_PIN4\r
+ * @arg PWR_WAKEUP_PIN5\r
+ * @arg PWR_WAKEUP_PIN6 \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r
+{\r
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r
+\r
+ CLEAR_BIT(PWR->CSR2, WakeUpPinx);\r
+}\r
+ \r
+/**\r
+ * @brief Enters Sleep mode.\r
+ * \r
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r
+ * \r
+ * @note In Sleep mode, the systick is stopped to avoid exit from this mode with\r
+ * systick interrupt when used as time base for Timeout \r
+ * \r
+ * @param Regulator Specifies the regulator state in SLEEP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r
+ * @note This parameter is not used for the STM32F7 family and is kept as parameter\r
+ * just to maintain compatibility with the lower power families.\r
+ * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r
+\r
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r
+\r
+ /* Ensure that all instructions done before entering SLEEP mode */\r
+ __DSB();\r
+ __ISB();\r
+\r
+ /* Select SLEEP mode entry -------------------------------------------------*/\r
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters Stop mode. \r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced. \r
+ * @param Regulator Specifies the regulator state in Stop mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r
+ * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r
+ * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+\r
+ /* Select the regulator state in Stop mode ---------------------------------*/\r
+ tmpreg = PWR->CR1;\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);\r
+\r
+ /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */\r
+ tmpreg |= Regulator;\r
+\r
+ /* Store the new value */\r
+ PWR->CR1 = tmpreg;\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+\r
+ /* Ensure that all instructions done before entering STOP mode */\r
+ __DSB();\r
+ __ISB();\r
+\r
+ /* Select Stop mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_STOPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __SEV();\r
+ __WFE();\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); \r
+}\r
+\r
+/**\r
+ * @brief Enters Standby mode.\r
+ * @note In Standby mode, all I/O pins are high impedance except for:\r
+ * - Reset pad (still available) \r
+ * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \r
+ * Alarm out, or RTC clock calibration out.\r
+ * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. \r
+ * - WKUP pins if enabled. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Select Standby mode */\r
+ PWR->CR1 |= PWR_CR1_PDDS;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM)\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief This function handles the PWR PVD interrupt request.\r
+ * @note This API should be called under the PVD_IRQHandler().\r
+ * @retval None\r
+ */\r
+void HAL_PWR_PVD_IRQHandler(void)\r
+{\r
+ /* Check PWR Exti flag */\r
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r
+ {\r
+ /* PWR PVD interrupt user callback */\r
+ HAL_PWR_PVDCallback();\r
+ \r
+ /* Clear PWR Exti pending bit */\r
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief PWR PVD interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_PWR_PVDCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_PWR_PVDCallback could be implemented in the user file\r
+ */ \r
+}\r
+\r
+/**\r
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \r
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over.\r
+ * Setting this bit is useful when the processor is expected to run only on\r
+ * interruptions handling. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSleepOnExit(void)\r
+{\r
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \r
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r
+ * re-enters SLEEP mode when an interruption handling is over. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSleepOnExit(void)\r
+{\r
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Enables CORTEX M4 SEVONPEND bit. \r
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended.\r
+ * @retval None\r
+ */\r
+void HAL_PWR_EnableSEVOnPend(void)\r
+{\r
+ /* Set SEVONPEND bit of Cortex System Control Register */\r
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @brief Disables CORTEX M4 SEVONPEND bit. \r
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \r
+ * WFE to wake up when an interrupt moves from inactive to pended. \r
+ * @retval None\r
+ */\r
+void HAL_PWR_DisableSEVOnPend(void)\r
+{\r
+ /* Clear SEVONPEND bit of Cortex System Control Register */\r
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_pwr_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extended PWR HAL module driver.\r
+ * This file provides firmware functions to manage the following \r
+ * functionalities of PWR extension peripheral: \r
+ * + Peripheral Extended features functions\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx PWREx\r
+ * @brief PWR HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @addtogroup PWREx_Private_Constants\r
+ * @{\r
+ */ \r
+#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000\r
+#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000\r
+#define PWR_BKPREG_TIMEOUT_VALUE 1000\r
+#define PWR_VOSRDY_TIMEOUT_VALUE 1000\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions \r
+ * @brief Peripheral Extended features functions \r
+ *\r
+@verbatim \r
+\r
+ ===============================================================================\r
+ ##### Peripheral extended features functions #####\r
+ ===============================================================================\r
+\r
+ *** Main and Backup Regulators configuration ***\r
+ ================================================\r
+ [..] \r
+ (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from \r
+ the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is \r
+ retained even in Standby or VBAT mode when the low power backup regulator\r
+ is enabled. It can be considered as an internal EEPROM when VBAT is \r
+ always present. You can use the HAL_PWREx_EnableBkUpReg() function to \r
+ enable the low power backup regulator. \r
+\r
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD) \r
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to \r
+ save battery life.\r
+\r
+ (+) The backup SRAM is not mass erased by a tamper event. It is read \r
+ protected to prevent confidential data, such as cryptographic private \r
+ key, from being accessed. The backup SRAM can be erased only through \r
+ the Flash interface when a protection level change from level 1 to \r
+ level 0 is requested. \r
+ -@- Refer to the description of Read protection (RDP) in the Flash \r
+ programming manual.\r
+\r
+ (+) The main internal regulator can be configured to have a tradeoff between \r
+ performance and power consumption when the device does not operate at \r
+ the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() \r
+ macro which configure VOS bit in PWR_CR register\r
+ \r
+ Refer to the product datasheets for more details.\r
+\r
+ *** FLASH Power Down configuration ****\r
+ =======================================\r
+ [..] \r
+ (+) By setting the FPDS bit in the PWR_CR register by using the \r
+ HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power \r
+ down mode when the device enters Stop mode. When the Flash memory \r
+ is in power down mode, an additional startup delay is incurred when \r
+ waking up from Stop mode.\r
+\r
+ *** Over-Drive and Under-Drive configuration ****\r
+ =================================================\r
+ [..] \r
+ (+) In Run mode: the main regulator has 2 operating modes available:\r
+ (++) Normal mode: The CPU and core logic operate at maximum frequency at a given \r
+ voltage scaling (scale 1, scale 2 or scale 3)\r
+ (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a \r
+ higher frequency than the normal mode for a given voltage scaling (scale 1, \r
+ scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and\r
+ disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow \r
+ the sequence described in Reference manual.\r
+ \r
+ (+) In Stop mode: the main regulator or low power regulator supplies a low power \r
+ voltage to the 1.2V domain, thus preserving the content of registers \r
+ and internal SRAM. 2 operating modes are available:\r
+ (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only \r
+ available when the main regulator or the low power regulator is used in Scale 3 or \r
+ low voltage mode.\r
+ (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only\r
+ available when the main regulator or the low power regulator is in low voltage mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Enable Backup regulator */\r
+ PWR->CSR1 |= PWR_CSR1_BRE;\r
+ \r
+ /* Workaround for the following hardware bug: */\r
+ /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r
+ PWR->CSR1 |= PWR_CSR1_EIWUP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is set */ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Backup Regulator.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Disable Backup regulator */\r
+ PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);\r
+ \r
+ /* Workaround for the following hardware bug: */\r
+ /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r
+ PWR->CSR1 |= PWR_CSR1_EIWUP;\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till Backup regulator ready flag is set */ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enables the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableFlashPowerDown(void)\r
+{\r
+ /* Enable the Flash Power Down */\r
+ PWR->CR1 |= PWR_CR1_FPDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables the Flash Power Down in Stop mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableFlashPowerDown(void)\r
+{\r
+ /* Disable the Flash Power Down */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);\r
+}\r
+\r
+/**\r
+ * @brief Enables Main Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void)\r
+{\r
+ /* Enable Main regulator low voltage */\r
+ PWR->CR1 |= PWR_CR1_MRUDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables Main Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void)\r
+{ \r
+ /* Disable Main regulator low voltage */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);\r
+}\r
+\r
+/**\r
+ * @brief Enables Low Power Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void)\r
+{\r
+ /* Enable low power regulator */\r
+ PWR->CR1 |= PWR_CR1_LPUDS;\r
+}\r
+\r
+/**\r
+ * @brief Disables Low Power Regulator low voltage mode.\r
+ * @retval None\r
+ */\r
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void)\r
+{\r
+ /* Disable low power regulator */\r
+ PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);\r
+}\r
+\r
+/**\r
+ * @brief Activates the Over-Drive mode.\r
+ * @note This mode allows the CPU and the core logic to operate at a higher frequency\r
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
+ * critical tasks and when the system clock source is either HSI or HSE. \r
+ * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
+ * The peripheral clocks must be enabled once the Over-drive mode is activated. \r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Enable the Over-drive to extend the clock frequency to 216 MHz */\r
+ __HAL_PWR_OVERDRIVE_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Enable the Over-drive switch */\r
+ __HAL_PWR_OVERDRIVESWITCHING_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Deactivates the Over-Drive mode.\r
+ * @note This mode allows the CPU and the core logic to operate at a higher frequency\r
+ * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). \r
+ * @note It is recommended to enter or exit Over-drive mode when the application is not running \r
+ * critical tasks and when the system clock source is either HSI or HSE. \r
+ * During the Over-drive switch activation, no peripheral clocks should be enabled. \r
+ * The peripheral clocks must be enabled once the Over-drive mode is activated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)\r
+{\r
+ uint32_t tickstart = 0;\r
+ \r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ \r
+ /* Disable the Over-drive switch */\r
+ __HAL_PWR_OVERDRIVESWITCHING_DISABLE();\r
+ \r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+ \r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ } \r
+ \r
+ /* Disable the Over-drive */\r
+ __HAL_PWR_OVERDRIVE_DISABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enters in Under-Drive STOP mode.\r
+ * \r
+ * @note This mode can be selected only when the Under-Drive is already active \r
+ * \r
+ * @note This mode is enabled only with STOP low power mode.\r
+ * In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r
+ * mode is only available when the main regulator or the low power regulator \r
+ * is in low voltage mode\r
+ * \r
+ * @note If the Under-drive mode was enabled, it is automatically disabled after \r
+ * exiting Stop mode. \r
+ * When the voltage regulator operates in Under-drive mode, an additional \r
+ * startup delay is induced when waking up from Stop mode.\r
+ * \r
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r
+ * \r
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r
+ * the HSI RC oscillator is selected as system clock.\r
+ * \r
+ * @note When the voltage regulator operates in low power mode, an additional \r
+ * startup delay is incurred when waking up from Stop mode. \r
+ * By keeping the internal regulator ON during Stop mode, the consumption \r
+ * is higher although the startup time is reduced.\r
+ * \r
+ * @param Regulator specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode \r
+ * and Flash memory in power-down when the device is in Stop under-drive mode\r
+ * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode \r
+ * and Flash memory in power-down when the device is in Stop under-drive mode\r
+ * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r
+{\r
+ uint32_t tempreg = 0;\r
+ uint32_t tickstart = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r
+ \r
+ /* Enable Power ctrl clock */\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ /* Enable the Under-drive Mode ---------------------------------------------*/\r
+ /* Clear Under-drive flag */\r
+ __HAL_PWR_CLEAR_ODRUDR_FLAG();\r
+ \r
+ /* Enable the Under-drive */ \r
+ __HAL_PWR_UNDERDRIVE_ENABLE();\r
+\r
+ /* Get tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for UnderDrive mode is ready */\r
+ while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tempreg = PWR->CR1;\r
+ /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */\r
+ tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);\r
+ \r
+ /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */\r
+ tempreg |= Regulator;\r
+ \r
+ /* Store the new value */\r
+ PWR->CR1 = tempreg;\r
+ \r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(STOPEntry == PWR_SLEEPENTRY_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r
+\r
+ return HAL_OK; \r
+}\r
+\r
+/**\r
+ * @brief Returns Voltage Scaling Range.\r
+ * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or \r
+ * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1\r
+ */ \r
+uint32_t HAL_PWREx_GetVoltageRange(void)\r
+{\r
+ return (PWR->CR1 & PWR_CR1_VOS);\r
+}\r
+\r
+/**\r
+ * @brief Configures the main internal regulator output voltage.\r
+ * @param VoltageScaling specifies the regulator output voltage to achieve\r
+ * a tradeoff between performance and power consumption.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\r
+ * typical output voltage at 1.4 V, \r
+ * system frequency up to 216 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\r
+ * typical output voltage at 1.2 V, \r
+ * system frequency up to 180 MHz.\r
+ * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,\r
+ * typical output voltage at 1.00 V, \r
+ * system frequency up to 151 MHz.\r
+ * @note To update the system clock frequency(SYSCLK):\r
+ * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().\r
+ * - Call the HAL_RCC_OscConfig() to configure the PLL.\r
+ * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.\r
+ * - Set the new system clock frequency using the HAL_RCC_ClockConfig().\r
+ * @note The scale can be modified only when the HSI or HSE clock source is selected \r
+ * as system clock source, otherwise the API returns HAL_ERROR. \r
+ * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits\r
+ * value in the PWR_CR1 register are not taken in account.\r
+ * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.\r
+ * @note The new voltage scale is active only when the PLL is ON. \r
+ * @retval HAL Status\r
+ */\r
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));\r
+\r
+ /* Enable Power ctrl clock */\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\r
+ {\r
+ /* Disable the main PLL */\r
+ __HAL_RCC_PLL_DISABLE();\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick(); \r
+ /* Wait till PLL is disabled */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ \r
+ /* Set Range */\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);\r
+ \r
+ /* Enable the main PLL */\r
+ __HAL_RCC_PLL_ENABLE();\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+ /* Wait till PLL is ready */ \r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ \r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+ while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ } \r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc.c\r
+ * @author MCD Application Team\r
+ * @brief RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Reset and Clock Control (RCC) peripheral:\r
+ * + Initialization and de-initialization functions\r
+ * + Peripheral Control functions\r
+ *\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### RCC specific features #####\r
+ ==============================================================================\r
+ [..]\r
+ After reset the device is running from Internal High Speed oscillator\r
+ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache\r
+ and I-Cache are disabled, and all peripherals are off except internal\r
+ SRAM, Flash and JTAG.\r
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r
+ all peripherals mapped on these busses are running at HSI speed.\r
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r
+ (+) All GPIOs are in input floating state, except the JTAG pins which\r
+ are assigned to be used for debug purpose.\r
+\r
+ [..]\r
+ Once the device started from reset, the user application has to:\r
+ (+) Configure the clock source to be used to drive the System clock\r
+ (if the application needs higher frequency/performance)\r
+ (+) Configure the System clock frequency and Flash settings\r
+ (+) Configure the AHB and APB busses prescalers\r
+ (+) Enable the clock for the peripheral(s) to be used\r
+ (+) Configure the clock source(s) for peripherals which clocks are not\r
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)\r
+\r
+ ##### RCC Limitations #####\r
+ ==============================================================================\r
+ [..]\r
+ A delay between an RCC peripheral clock enable and the effective peripheral\r
+ enabling should be taken into account in order to manage the peripheral read/write\r
+ from/to registers.\r
+ (+) This delay depends on the peripheral mapping.\r
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle\r
+ after the clock enable bit is set on the hardware register\r
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle\r
+ after the clock enable bit is set on the hardware register\r
+\r
+ [..]\r
+ Implemented Workaround:\r
+ (+) For AHB & APB peripherals, a dummy read to the peripheral register has been\r
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC RCC\r
+ * @brief RCC HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Macros RCC Private Macros\r
+ * @{\r
+ */\r
+\r
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()\r
+#define MCO1_GPIO_PORT GPIOA\r
+#define MCO1_PIN GPIO_PIN_8\r
+\r
+#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()\r
+#define MCO2_GPIO_PORT GPIOC\r
+#define MCO2_PIN GPIO_PIN_9\r
+\r
+/**\r
+ * @}\r
+ */\r
+/* Private variables ---------------------------------------------------------*/\r
+/** @defgroup RCC_Private_Variables RCC Private Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Exported functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCC_Exported_Functions RCC Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\r
+ * @brief Initialization and Configuration functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+##### Initialization and de-initialization functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This section provides functions allowing to configure the internal/external oscillators\r
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1\r
+ and APB2).\r
+\r
+ [..] Internal/external clock and PLL configuration\r
+ (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r
+ the PLL as System clock source.\r
+\r
+ (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r
+ clock source.\r
+\r
+ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\r
+ through the PLL as System clock source. Can be used also as RTC clock source.\r
+\r
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\r
+\r
+ (#) PLL (clocked by HSI or HSE), featuring two different output clocks:\r
+ (++) The first output is used to generate the high speed system clock (up to 216 MHz)\r
+ (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r
+ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r
+\r
+ (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()\r
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System\r
+ clock source), the System clock is automatically switched to HSI and an interrupt\r
+ is generated if enabled. The interrupt is linked to the Cortex-M7 NMI\r
+ (Non-Maskable Interrupt) exception vector.\r
+\r
+ (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\r
+ clock (through a configurable prescaler) on PA8 pin.\r
+\r
+ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\r
+ clock (through a configurable prescaler) on PC9 pin.\r
+\r
+ [..] System, AHB and APB busses clocks configuration\r
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r
+ HSE and PLL.\r
+ The AHB clock (HCLK) is derived from System clock through configurable\r
+ prescaler and used to clock the CPU, memory and peripherals mapped\r
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\r
+ from AHB clock through configurable prescalers and used to clock\r
+ the peripherals mapped on these busses. You can use\r
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.\r
+\r
+ -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r
+ (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or\r
+ from an external clock mapped on the I2S_CKIN pin.\r
+ You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.\r
+ (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or\r
+ from an external clock mapped on the I2S_CKIN pin.\r
+ You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.\r
+ (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r
+ divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()\r
+ macros to configure this clock.\r
+ (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz\r
+ to work correctly, while the SDIO require a frequency equal or lower than\r
+ to 48. This clock is derived of the main PLL through PLLQ divider.\r
+ (+@) IWDG clock which is always the LSI clock.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @note The default reset state of the clock configuration is given below:\r
+ * - HSI ON and used as system clock source\r
+ * - HSE, PLL, PLLI2S and PLLSAI OFF\r
+ * - AHB, APB1 and APB2 prescaler set to 1.\r
+ * - CSS, MCO1 and MCO2 OFF\r
+ * - All interrupts disabled\r
+ * @note This function doesn't modify the configuration of the\r
+ * - Peripheral clocks\r
+ * - LSI, LSE and RTC clocks\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_DeInit(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Set HSION bit to the reset value */\r
+ SET_BIT(RCC->CR, RCC_CR_HSION);\r
+\r
+ /* Wait till HSI is ready */\r
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Set HSITRIM[4:0] bits to the reset value */\r
+ SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Reset CFGR register */\r
+ CLEAR_REG(RCC->CFGR);\r
+\r
+ /* Wait till clock switch is ready */\r
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Clear HSEON, HSEBYP and CSSON bits */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);\r
+\r
+ /* Wait till HSE is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Clear PLLON bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);\r
+\r
+ /* Wait till PLL is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Reset PLLI2SON bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);\r
+\r
+ /* Wait till PLLI2S is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Get Start Tick */\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Reset PLLSAI bit */\r
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);\r
+\r
+ /* Wait till PLLSAI is disabled */\r
+ while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */\r
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U;\r
+\r
+ /* Reset PLLI2SCFGR register to default value */\r
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;\r
+\r
+ /* Reset PLLSAICFGR register to default value */\r
+ RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U;\r
+\r
+ /* Disable all interrupts */\r
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);\r
+\r
+ /* Clear all interrupt flags */\r
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);\r
+\r
+ /* Clear LSION bit */\r
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\r
+\r
+ /* Reset all CSR flags */\r
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HSI_VALUE;\r
+\r
+ /* Adapt Systick interrupt period */\r
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ return HAL_OK;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the\r
+ * RCC_OscInitTypeDef.\r
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC Oscillators.\r
+ * @note The PLL is not disabled when used as system clock.\r
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r
+ * supported by this function. User should request a transition to LSE Off\r
+ * first and then LSE On or LSE Bypass.\r
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r
+ * supported by this function. User should request a transition to HSE Off\r
+ * first and then HSE On or HSE Bypass.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ uint32_t tickstart;\r
+ FlagStatus pwrclkchanged = RESET;\r
+\r
+ /* Check Null pointer */\r
+ if(RCC_OscInitStruct == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r
+\r
+ /*------------------------------- HSE Configuration ------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r
+ /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */\r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)\r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\r
+ {\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set the new HSE configuration ---------------------------------------*/\r
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r
+\r
+ /* Check the HSE State */\r
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSE is bypassed or disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*----------------------------- HSI Configuration --------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r
+\r
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\r
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)\r
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\r
+ {\r
+ /* When HSI is used as system clock it will not disabled */\r
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Otherwise, just the calibration is allowed */\r
+ else\r
+ {\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check the HSI State */\r
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r
+ {\r
+ /* Enable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal High Speed oscillator (HSI). */\r
+ __HAL_RCC_HSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till HSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSI Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r
+\r
+ /* Check the LSI State */\r
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r
+ {\r
+ /* Enable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Internal Low Speed oscillator (LSI). */\r
+ __HAL_RCC_LSI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSI is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /*------------------------------ LSE Configuration -------------------------*/\r
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r
+\r
+ /* Update LSE configuration in Backup Domain control register */\r
+ /* Requires to enable write access to Backup Domain of necessary */\r
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r
+ {\r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ pwrclkchanged = SET;\r
+ }\r
+\r
+ if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
+ {\r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+\r
+ /* Wait for Backup domain Write protection disable */\r
+ tickstart = HAL_GetTick();\r
+\r
+ while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Set the new LSE configuration -----------------------------------------*/\r
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r
+ /* Check the LSE State */\r
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Restore clock configuration if changed */\r
+ if(pwrclkchanged == SET)\r
+ {\r
+ __HAL_RCC_PWR_CLK_DISABLE();\r
+ }\r
+ }\r
+ /*-------------------------------- PLL Configuration -----------------------*/\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r
+ {\r
+ /* Check if the PLL is used as system clock or not */\r
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r
+ {\r
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r
+#if defined (RCC_PLLCFGR_PLLR)\r
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r
+#endif\r
+\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Configure the main PLL clock source, multiplication and division factors. */\r
+#if defined (RCC_PLLCFGR_PLLR)\r
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
+ RCC_OscInitStruct->PLL.PLLM,\r
+ RCC_OscInitStruct->PLL.PLLN,\r
+ RCC_OscInitStruct->PLL.PLLP,\r
+ RCC_OscInitStruct->PLL.PLLQ,\r
+ RCC_OscInitStruct->PLL.PLLR);\r
+#else\r
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r
+ RCC_OscInitStruct->PLL.PLLM,\r
+ RCC_OscInitStruct->PLL.PLLN,\r
+ RCC_OscInitStruct->PLL.PLLP,\r
+ RCC_OscInitStruct->PLL.PLLQ);\r
+#endif\r
+\r
+ /* Enable the main PLL. */\r
+ __HAL_RCC_PLL_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the main PLL. */\r
+ __HAL_RCC_PLL_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLL is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified\r
+ * parameters in the RCC_ClkInitStruct.\r
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that\r
+ * contains the configuration information for the RCC peripheral.\r
+ * @param FLatency FLASH Latency, this parameter depend on device selected\r
+ *\r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function\r
+ *\r
+ * @note The HSI is used (enabled by hardware) as system clock source after\r
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case\r
+ * of failure of the HSE used directly or indirectly as system clock\r
+ * (if the Clock Security System CSS is enabled).\r
+ *\r
+ * @note A switch from one clock source to another occurs only if the target\r
+ * clock source is ready (clock stable after startup delay or PLL locked).\r
+ * If a clock source which is not yet ready is selected, the switch will\r
+ * occur when the clock source will be ready.\r
+ * You can use HAL_RCC_GetClockConfig() function to know which clock is\r
+ * currently used as system clock source.\r
+ * @note Depending on the device voltage range, the software has to set correctly\r
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r
+ * (for more details refer to section above "Initialization/de-initialization functions")\r
+ * @retval None\r
+ */\r
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)\r
+{\r
+ uint32_t tickstart = 0;\r
+\r
+ /* Check Null pointer */\r
+ if(RCC_ClkInitStruct == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r
+ assert_param(IS_FLASH_LATENCY(FLatency));\r
+\r
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r
+ must be correctly programmed according to the frequency of the CPU clock\r
+ (HCLK) and the supply voltage of the device. */\r
+\r
+ /* Increasing the CPU frequency */\r
+ if(FLatency > __HAL_FLASH_GET_LATENCY())\r
+ {\r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- HCLK Configuration --------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r
+ {\r
+ /* Set the highest APBx dividers in order to ensure that we do not go through\r
+ a non-spec phase whatever we decrease or increase HCLK. */\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+ {\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);\r
+ }\r
+\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+ {\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));\r
+ }\r
+\r
+ /* Set the new HCLK clock divider */\r
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r
+ }\r
+\r
+ /*------------------------- SYSCLK Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r
+ {\r
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r
+\r
+ /* HSE is selected as System Clock Source */\r
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r
+ {\r
+ /* Check the HSE ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* PLL is selected as System Clock Source */\r
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r
+ {\r
+ /* Check the PLL ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+ /* HSI is selected as System Clock Source */\r
+ else\r
+ {\r
+ /* Check the HSI ready flag */\r
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))\r
+ {\r
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Decreasing the number of wait states because of lower CPU frequency */\r
+ if(FLatency < __HAL_FLASH_GET_LATENCY())\r
+ {\r
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r
+ __HAL_FLASH_SET_LATENCY(FLatency);\r
+\r
+ /* Check that the new number of wait states is taken into account to access the Flash\r
+ memory by reading the FLASH_ACR register */\r
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ }\r
+\r
+ /*-------------------------- PCLK1 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r
+ }\r
+\r
+ /*-------------------------- PCLK2 Configuration ---------------------------*/\r
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r
+ {\r
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));\r
+ }\r
+\r
+ /* Update the SystemCoreClock global variable */\r
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];\r
+\r
+ /* Configure the source of time base considering new system clocks settings*/\r
+ HAL_InitTick (TICK_INT_PRIORITY);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\r
+ * @brief RCC clocks control functions\r
+ *\r
+ @verbatim\r
+ ===============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks\r
+ frequencies.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).\r
+ * @note PA8/PC9 should be configured in alternate function mode.\r
+ * @param RCC_MCOx specifies the output direction for the clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).\r
+ * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).\r
+ * @param RCC_MCOSource specifies the clock source to output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r
+ * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r
+ * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r
+ * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r
+ * @param RCC_MCODiv specifies the MCOx prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_MCODIV_1: no division applied to MCOx clock\r
+ * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r
+ * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r
+ * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r
+ * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r
+ * @retval None\r
+ */\r
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCOx));\r
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r
+ /* RCC_MCO1 */\r
+ if(RCC_MCOx == RCC_MCO1)\r
+ {\r
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r
+\r
+ /* MCO1 Clock Enable */\r
+ MCO1_CLK_ENABLE();\r
+\r
+ /* Configure the MCO1 pin in alternate function mode */\r
+ GPIO_InitStruct.Pin = MCO1_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+ /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));\r
+\r
+ /* MCO2 Clock Enable */\r
+ MCO2_CLK_ENABLE();\r
+\r
+ /* Configure the MCO2 pin in alternate function mode */\r
+ GPIO_InitStruct.Pin = MCO2_PIN;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r
+ HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);\r
+\r
+ /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */\r
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the Clock Security System.\r
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator\r
+ * is automatically disabled and an interrupt is generated to inform the\r
+ * software about the failure (Clock Security System Interrupt, CSSI),\r
+ * allowing the MCU to perform rescue operations. The CSSI is linked to\r
+ * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_EnableCSS(void)\r
+{\r
+ SET_BIT(RCC->CR, RCC_CR_CSSON);\r
+}\r
+\r
+/**\r
+ * @brief Disables the Clock Security System.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_DisableCSS(void)\r
+{\r
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON);\r
+}\r
+\r
+/**\r
+ * @brief Returns the SYSCLK frequency\r
+ *\r
+ * @note The system frequency computed by this function is not the real\r
+ * frequency in the chip. It is calculated based on the predefined\r
+ * constant and the selected clock source:\r
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)\r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature.\r
+ * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ *\r
+ * @note The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ *\r
+ * @note This function can be used by the user application to compute the\r
+ * baudrate for the communication peripherals or configure other parameters.\r
+ *\r
+ * @note Each time SYSCLK changes, this function must be called to update the\r
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ *\r
+ *\r
+ * @retval SYSCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetSysClockFreq(void)\r
+{\r
+ uint32_t pllm = 0, pllvco = 0, pllp = 0;\r
+ uint32_t sysclockfreq = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ switch (RCC->CFGR & RCC_CFGR_SWS)\r
+ {\r
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */\r
+ {\r
+ sysclockfreq = HSI_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */\r
+ {\r
+ sysclockfreq = HSE_VALUE;\r
+ break;\r
+ }\r
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */\r
+ {\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\r
+ SYSCLK = PLL_VCO / PLLP */\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\r
+ }\r
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);\r
+\r
+ sysclockfreq = pllvco/pllp;\r
+ break;\r
+ }\r
+ default:\r
+ {\r
+ sysclockfreq = HSI_VALUE;\r
+ break;\r
+ }\r
+ }\r
+ return sysclockfreq;\r
+}\r
+\r
+/**\r
+ * @brief Returns the HCLK frequency\r
+ * @note Each time HCLK changes, this function must be called to update the\r
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.\r
+ * @retval HCLK frequency\r
+ */\r
+uint32_t HAL_RCC_GetHCLKFreq(void)\r
+{\r
+ return SystemCoreClock;\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK1 frequency\r
+ * @note Each time PCLK1 changes, this function must be called to update the\r
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK1 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK1Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);\r
+}\r
+\r
+/**\r
+ * @brief Returns the PCLK2 frequency\r
+ * @note Each time PCLK2 changes, this function must be called to update the\r
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r
+ * @retval PCLK2 frequency\r
+ */\r
+uint32_t HAL_RCC_GetPCLK2Freq(void)\r
+{\r
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);\r
+}\r
+\r
+/**\r
+ * @brief Configures the RCC_OscInitStruct according to the internal\r
+ * RCC configuration registers.\r
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r
+ * will be configured.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)\r
+{\r
+ /* Set all possible values for the Oscillator type parameter ---------------*/\r
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r
+\r
+ /* Get the HSE configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r
+ }\r
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r
+ }\r
+\r
+ /* Get the HSI configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r
+ }\r
+\r
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);\r
+\r
+ /* Get the LSE configuration -----------------------------------------------*/\r
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r
+ }\r
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r
+ }\r
+\r
+ /* Get the LSI configuration -----------------------------------------------*/\r
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r
+ }\r
+\r
+ /* Get the PLL configuration -----------------------------------------------*/\r
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r
+ }\r
+ else\r
+ {\r
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r
+ }\r
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);\r
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);\r
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos);\r
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);\r
+#if defined (RCC_PLLCFGR_PLLR)\r
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Configures the RCC_ClkInitStruct according to the internal\r
+ * RCC configuration registers.\r
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that\r
+ * will be configured.\r
+ * @param pFLatency Pointer on the Flash Latency.\r
+ * @retval None\r
+ */\r
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)\r
+{\r
+ /* Set all possible values for the Clock type parameter --------------------*/\r
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r
+\r
+ /* Get the SYSCLK configuration --------------------------------------------*/\r
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r
+\r
+ /* Get the HCLK configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);\r
+\r
+ /* Get the APB1 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);\r
+\r
+ /* Get the APB2 configuration ----------------------------------------------*/\r
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);\r
+\r
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/\r
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);\r
+}\r
+\r
+/**\r
+ * @brief This function handles the RCC CSS interrupt request.\r
+ * @note This API should be called under the NMI_Handler().\r
+ * @retval None\r
+ */\r
+void HAL_RCC_NMI_IRQHandler(void)\r
+{\r
+ /* Check RCC CSSF flag */\r
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r
+ {\r
+ /* RCC Clock Security System interrupt user callback */\r
+ HAL_RCC_CSSCallback();\r
+\r
+ /* Clear RCC CSS pending bit */\r
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief RCC Clock Security System interrupt callback\r
+ * @retval None\r
+ */\r
+__weak void HAL_RCC_CSSCallback(void)\r
+{\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_RCC_CSSCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_rcc_ex.c\r
+ * @author MCD Application Team\r
+ * @brief Extension RCC HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities RCC extension peripheral:\r
+ * + Extended Peripheral Control functions\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx RCCEx\r
+ * @brief RCCEx HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Defines RCCEx Private Defines\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+/* Private macro -------------------------------------------------------------*/\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions\r
+ * @brief Extended Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended Peripheral Control functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the RCC Clocks\r
+ frequencies.\r
+ [..]\r
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r
+ select the RTC clock source; in this case the Backup domain will be reset in\r
+ order to modify the RTC Clock source, as consequence RTC registers (including\r
+ the backup registers) and RCC_BDCR register will be set to their reset values.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \\r
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \\r
+ defined (STM32F750xx)\r
+/**\r
+ * @brief Initializes the RCC extended peripherals clocks according to the specified\r
+ * parameters in the RCC_PeriphCLKInitTypeDef.\r
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+ * contains the configuration information for the Extended Peripherals\r
+ * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).\r
+ *\r
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\r
+ * the RTC clock source; in this case the Backup domain will be reset in\r
+ * order to modify the RTC Clock source, as consequence RTC registers (including\r
+ * the backup registers) are set to their reset values.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg0 = 0;\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t plli2sused = 0;\r
+ uint32_t pllsaiused = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
+\r
+ /*----------------------------------- I2S configuration ----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));\r
+\r
+ /* Configure I2S Clock source */\r
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);\r
+\r
+ /* Enable the PLLI2S when it's used as clock source for I2S */\r
+ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1;\r
+ }\r
+ }\r
+\r
+ /*------------------------------------ SAI1 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\r
+\r
+ /* Configure SAI1 Clock source */\r
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1;\r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1;\r
+ }\r
+ }\r
+\r
+ /*------------------------------------ SAI2 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\r
+\r
+ /* Configure SAI2 Clock source */\r
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r
+\r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1;\r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1;\r
+ }\r
+ }\r
+\r
+ /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r
+ {\r
+ plli2sused = 1;\r
+ }\r
+\r
+ /*------------------------------------ RTC configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\r
+ {\r
+ /* Check for RTC Parameters used to output RTCCLK */\r
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
+\r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+\r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for Backup domain Write protection disable */\r
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */\r
+ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);\r
+\r
+ if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\r
+ {\r
+ /* Store the content of BDCR register before the reset of Backup Domain */\r
+ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r
+\r
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
+ __HAL_RCC_BACKUPRESET_FORCE();\r
+ __HAL_RCC_BACKUPRESET_RELEASE();\r
+\r
+ /* Restore the Content of BDCR register */\r
+ RCC->BDCR = tmpreg0;\r
+\r
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r
+ }\r
+\r
+ /*------------------------------------ TIM configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r
+\r
+ /* Configure Timer Prescaler */\r
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r
+ }\r
+\r
+ /*-------------------------------------- I2C1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r
+\r
+ /* Configure the I2C1 clock source */\r
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- I2C2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r
+\r
+ /* Configure the I2C2 clock source */\r
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- I2C3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r
+\r
+ /* Configure the I2C3 clock source */\r
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- I2C4 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r
+\r
+ /* Configure the I2C4 clock source */\r
+ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r
+\r
+ /* Configure the USART1 clock source */\r
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r
+\r
+ /* Configure the USART2 clock source */\r
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r
+\r
+ /* Configure the USART3 clock source */\r
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART4 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r
+\r
+ /* Configure the UART4 clock source */\r
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART5 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r
+\r
+ /* Configure the UART5 clock source */\r
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART6 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));\r
+\r
+ /* Configure the USART6 clock source */\r
+ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART7 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));\r
+\r
+ /* Configure the UART7 clock source */\r
+ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART8 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));\r
+\r
+ /* Configure the UART8 clock source */\r
+ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);\r
+ }\r
+\r
+ /*--------------------------------------- CEC Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));\r
+\r
+ /* Configure the CEC clock source */\r
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- CK48 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));\r
+\r
+ /* Configure the CLK48 source */\r
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\r
+\r
+ /* Enable the PLLSAI when it's used as clock source for CK48 */\r
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)\r
+ {\r
+ pllsaiused = 1;\r
+ }\r
+ }\r
+\r
+ /*-------------------------------------- LTDC Configuration -----------------------------------*/\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r
+ {\r
+ pllsaiused = 1;\r
+ }\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r
+\r
+ /* Configure the LTPIM1 clock source */\r
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r
+ }\r
+\r
+ /*------------------------------------- SDMMC1 Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r
+\r
+ /* Configure the SDMMC1 clock source */\r
+ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r
+ }\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ /*------------------------------------- SDMMC2 Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));\r
+\r
+ /* Configure the SDMMC2 clock source */\r
+ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);\r
+ }\r
+\r
+ /*------------------------------------- DFSDM1 Configuration -------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\r
+\r
+ /* Configure the DFSDM1 interface clock source */\r
+ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\r
+ }\r
+\r
+ /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));\r
+\r
+ /* Configure the DFSDM interface clock source */\r
+ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);\r
+ }\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */\r
+ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\r
+ {\r
+ /* Disable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLI2S is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* check for common PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r
+\r
+ /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/\r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+\r
+ /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ }\r
+\r
+ /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/\r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))\r
+ {\r
+ /* Check for PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+ /* Check for PLLI2S/DIVQ parameters */\r
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\r
+\r
+ /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);\r
+ }\r
+\r
+ /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r
+\r
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r
+ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);\r
+ }\r
+\r
+ /*----------------- In Case of PLLI2S is just selected -----------------*/\r
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\r
+ {\r
+ /* Check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */\r
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ }\r
+\r
+ /* Enable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLI2S is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /*-------------------------------------- PLLSAI Configuration ---------------------------------*/\r
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */\r
+ if(pllsaiused == 1)\r
+ {\r
+ /* Disable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is disabled */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check the PLLSAI division factors */\r
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\r
+\r
+ /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/\r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\r
+ {\r
+ /* check for PLLSAIQ Parameter */\r
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\r
+ /* check for PLLSAI/DIVQ Parameter */\r
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\r
+\r
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\r
+ }\r
+\r
+ /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/\r
+ /* In Case of PLLI2S is selected as source clock for CK48 */\r
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\r
+ /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\r
+\r
+ /* Configure the PLLSAI division factors */\r
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */\r
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);\r
+ }\r
+\r
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r
+ /*---------------------------- LTDC configuration -------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\r
+ {\r
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));\r
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));\r
+\r
+ /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r
+\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);\r
+\r
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */\r
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\r
+ }\r
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+ /* Enable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is ready */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal\r
+ * RCC configuration registers.\r
+ * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tempreg = 0;\r
+\r
+ /* Set all possible values for the extended clock type parameter------------*/\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\\r
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\\r
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\\r
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\\r
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\\r
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\\r
+ RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\\r
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\\r
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\\r
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\\r
+ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\\r
+ RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO;\r
+#else\r
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\\r
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\\r
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\\r
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\\r
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\\r
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\\r
+ RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\\r
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\\r
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\\r
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\\r
+ RCC_PERIPHCLK_CLK48;\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+ /* Get the PLLI2S Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\r
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);\r
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r
+\r
+ /* Get the PLLSAI Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\r
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\r
+\r
+ /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/\r
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);\r
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);\r
+ PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos);\r
+\r
+ /* Get the SAI1 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r
+\r
+ /* Get the SAI2 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\r
+\r
+ /* Get the I2S clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();\r
+\r
+ /* Get the I2C1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r
+\r
+ /* Get the I2C2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();\r
+\r
+ /* Get the I2C3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();\r
+\r
+ /* Get the I2C4 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();\r
+\r
+ /* Get the USART1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();\r
+\r
+ /* Get the USART2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();\r
+\r
+ /* Get the USART3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();\r
+\r
+ /* Get the UART4 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();\r
+\r
+ /* Get the UART5 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();\r
+\r
+ /* Get the USART6 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();\r
+\r
+ /* Get the UART7 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();\r
+\r
+ /* Get the UART8 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();\r
+\r
+ /* Get the LPTIM1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r
+\r
+ /* Get the CEC clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();\r
+\r
+ /* Get the CK48 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\r
+\r
+ /* Get the SDMMC1 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();\r
+\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ /* Get the SDMMC2 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();\r
+\r
+ /* Get the DFSDM clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();\r
+\r
+ /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+\r
+ /* Get the RTC Clock configuration -----------------------------------------------*/\r
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\r
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\r
+\r
+ /* Get the TIM Prescaler configuration --------------------------------------------*/\r
+ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r
+ }\r
+ else\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r
+ }\r
+}\r
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r
+\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+/**\r
+ * @brief Initializes the RCC extended peripherals clocks according to the specified\r
+ * parameters in the RCC_PeriphCLKInitTypeDef.\r
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\r
+ * contains the configuration information for the Extended Peripherals\r
+ * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).\r
+ *\r
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\r
+ * the RTC clock source; in this case the Backup domain will be reset in\r
+ * order to modify the RTC Clock source, as consequence RTC registers (including\r
+ * the backup registers) are set to their reset values.\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tickstart = 0;\r
+ uint32_t tmpreg0 = 0;\r
+ uint32_t plli2sused = 0;\r
+ uint32_t pllsaiused = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r
+\r
+ /*----------------------------------- I2S configuration ----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));\r
+\r
+ /* Configure I2S Clock source */\r
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);\r
+\r
+ /* Enable the PLLI2S when it's used as clock source for I2S */\r
+ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1;\r
+ }\r
+ }\r
+\r
+ /*------------------------------------ SAI1 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\r
+\r
+ /* Configure SAI1 Clock source */\r
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1;\r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1;\r
+ }\r
+ }\r
+\r
+ /*------------------------------------ SAI2 configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\r
+\r
+ /* Configure SAI2 Clock source */\r
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r
+\r
+ /* Enable the PLLI2S when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\r
+ {\r
+ plli2sused = 1;\r
+ }\r
+ /* Enable the PLLSAI when it's used as clock source for SAI */\r
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\r
+ {\r
+ pllsaiused = 1;\r
+ }\r
+ }\r
+\r
+ /*------------------------------------ RTC configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\r
+ {\r
+ /* Check for RTC Parameters used to output RTCCLK */\r
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r
+\r
+ /* Enable Power Clock*/\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+\r
+ /* Enable write access to Backup domain */\r
+ PWR->CR1 |= PWR_CR1_DBP;\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait for Backup domain Write protection disable */\r
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */\r
+ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);\r
+\r
+ if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\r
+ {\r
+ /* Store the content of BDCR register before the reset of Backup Domain */\r
+ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r
+\r
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */\r
+ __HAL_RCC_BACKUPRESET_FORCE();\r
+ __HAL_RCC_BACKUPRESET_RELEASE();\r
+\r
+ /* Restore the Content of BDCR register */\r
+ RCC->BDCR = tmpreg0;\r
+\r
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\r
+ {\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till LSE is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r
+ {\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r
+ }\r
+\r
+ /*------------------------------------ TIM configuration --------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r
+\r
+ /* Configure Timer Prescaler */\r
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r
+ }\r
+\r
+ /*-------------------------------------- I2C1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r
+\r
+ /* Configure the I2C1 clock source */\r
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- I2C2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r
+\r
+ /* Configure the I2C2 clock source */\r
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- I2C3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r
+\r
+ /* Configure the I2C3 clock source */\r
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r
+\r
+ /* Configure the USART1 clock source */\r
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART2 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r
+\r
+ /* Configure the USART2 clock source */\r
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART3 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r
+\r
+ /* Configure the USART3 clock source */\r
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART4 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r
+\r
+ /* Configure the UART4 clock source */\r
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART5 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r
+\r
+ /* Configure the UART5 clock source */\r
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- USART6 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));\r
+\r
+ /* Configure the USART6 clock source */\r
+ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART7 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));\r
+\r
+ /* Configure the UART7 clock source */\r
+ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- UART8 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));\r
+\r
+ /* Configure the UART8 clock source */\r
+ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- CK48 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));\r
+\r
+ /* Configure the CLK48 source */\r
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\r
+\r
+ /* Enable the PLLSAI when it's used as clock source for CK48 */\r
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)\r
+ {\r
+ pllsaiused = 1;\r
+ }\r
+ }\r
+\r
+ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r
+\r
+ /* Configure the LTPIM1 clock source */\r
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r
+ }\r
+\r
+ /*------------------------------------- SDMMC1 Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r
+\r
+ /* Configure the SDMMC1 clock source */\r
+ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r
+ }\r
+\r
+ /*------------------------------------- SDMMC2 Configuration ------------------------------------*/\r
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));\r
+\r
+ /* Configure the SDMMC2 clock source */\r
+ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);\r
+ }\r
+\r
+ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */\r
+ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\r
+ {\r
+ /* Disable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLI2S is disabled */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* check for common PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r
+\r
+ /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/\r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+\r
+ /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ }\r
+\r
+ /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/\r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))\r
+ {\r
+ /* Check for PLLI2S Parameters */\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+ /* Check for PLLI2S/DIVQ parameters */\r
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\r
+\r
+ /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);\r
+ }\r
+\r
+ /*----------------- In Case of PLLI2S is just selected -----------------*/\r
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\r
+ {\r
+ /* Check for Parameters */\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r
+\r
+ /* Configure the PLLI2S division factors */\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */\r
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\r
+ }\r
+\r
+ /* Enable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLI2S is ready */\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+\r
+ /*-------------------------------------- PLLSAI Configuration ---------------------------------*/\r
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */\r
+ if(pllsaiused == 1)\r
+ {\r
+ /* Disable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_DISABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is disabled */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Check the PLLSAI division factors */\r
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\r
+\r
+ /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/\r
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\\r
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\r
+ {\r
+ /* check for PLLSAIQ Parameter */\r
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\r
+ /* check for PLLSAI/DIVQ Parameter */\r
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\r
+\r
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\r
+ }\r
+\r
+ /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/\r
+ /* In Case of PLLI2S is selected as source clock for CK48 */\r
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))\r
+ {\r
+ /* check for Parameters */\r
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\r
+ /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */\r
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r
+\r
+ /* Configure the PLLSAI division factors */\r
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */\r
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\r
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);\r
+ }\r
+\r
+ /* Enable PLLSAI Clock */\r
+ __HAL_RCC_PLLSAI_ENABLE();\r
+\r
+ /* Get Start Tick*/\r
+ tickstart = HAL_GetTick();\r
+\r
+ /* Wait till PLLSAI is ready */\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal\r
+ * RCC configuration registers.\r
+ * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure\r
+ * @retval None\r
+ */\r
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)\r
+{\r
+ uint32_t tempreg = 0;\r
+\r
+ /* Set all possible values for the extended clock type parameter------------*/\r
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\\r
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\\r
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\\r
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\\r
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\\r
+ RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\\r
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\\r
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\\r
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\\r
+ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2;\r
+\r
+ /* Get the PLLI2S Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\r
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r
+\r
+ /* Get the PLLSAI Clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\r
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r
+\r
+ /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/\r
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);\r
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);\r
+\r
+ /* Get the SAI1 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r
+\r
+ /* Get the SAI2 clock configuration ----------------------------------------------*/\r
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\r
+\r
+ /* Get the I2S clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();\r
+\r
+ /* Get the I2C1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r
+\r
+ /* Get the I2C2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();\r
+\r
+ /* Get the I2C3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();\r
+\r
+ /* Get the USART1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();\r
+\r
+ /* Get the USART2 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();\r
+\r
+ /* Get the USART3 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();\r
+\r
+ /* Get the UART4 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();\r
+\r
+ /* Get the UART5 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();\r
+\r
+ /* Get the USART6 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();\r
+\r
+ /* Get the UART7 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();\r
+\r
+ /* Get the UART8 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();\r
+\r
+ /* Get the LPTIM1 clock configuration ------------------------------------------*/\r
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r
+\r
+ /* Get the CK48 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\r
+\r
+ /* Get the SDMMC1 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();\r
+\r
+ /* Get the SDMMC2 clock configuration -----------------------------------------------*/\r
+ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();\r
+\r
+ /* Get the RTC Clock configuration -----------------------------------------------*/\r
+ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\r
+ PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\r
+\r
+ /* Get the TIM Prescaler configuration --------------------------------------------*/\r
+ if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r
+ }\r
+ else\r
+ {\r
+ PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r
+ }\r
+}\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+/**\r
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)\r
+ * @note Return 0 if peripheral clock identifier not managed by this API\r
+ * @param PeriphClk Peripheral clock identifier\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock\r
+ * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock\r
+ * @retval Frequency in KHz\r
+ */\r
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* This variable is used to store the SAI clock frequency (value in Hz) */\r
+ uint32_t frequency = 0;\r
+ /* This variable is used to store the VCO Input (value in Hz) */\r
+ uint32_t vcoinput = 0;\r
+ /* This variable is used to store the SAI clock source */\r
+ uint32_t saiclocksource = 0;\r
+\r
+ if (PeriphClk == RCC_PERIPHCLK_SAI1)\r
+ {\r
+ saiclocksource = RCC->DCKCFGR1;\r
+ saiclocksource &= RCC_DCKCFGR1_SAI1SEL;\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLLSAI is the clock source for SAI1 */\r
+ {\r
+ /* Configure the PLLSAI division factor */\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r
+ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r
+ frequency = frequency/(tmpreg);\r
+ break;\r
+ }\r
+ case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */\r
+ {\r
+ /* Configure the PLLI2S division factor */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r
+ tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);\r
+ frequency = frequency/(tmpreg);\r
+ break;\r
+ }\r
+ case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/\r
+ {\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the main PLL Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* In Case the main PLL Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+ break;\r
+ }\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ default :\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (PeriphClk == RCC_PERIPHCLK_SAI2)\r
+ {\r
+ saiclocksource = RCC->DCKCFGR1;\r
+ saiclocksource &= RCC_DCKCFGR1_SAI2SEL;\r
+ switch (saiclocksource)\r
+ {\r
+ case 0: /* PLLSAI is the clock source for SAI*/\r
+ {\r
+ /* Configure the PLLSAI division factor */\r
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r
+ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r
+ frequency = frequency/(tmpreg);\r
+ break;\r
+ }\r
+ case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */\r
+ {\r
+ /* Configure the PLLI2S division factor */\r
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the PLL Source is HSI (Internal Clock) */\r
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r
+ }\r
+ else\r
+ {\r
+ /* In Case the PLL Source is HSE (External Clock) */\r
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r
+ }\r
+\r
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r
+\r
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r
+ tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);\r
+ frequency = frequency/(tmpreg);\r
+ break;\r
+ }\r
+ case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */\r
+ {\r
+ frequency = EXTERNAL_CLOCK_VALUE;\r
+ break;\r
+ }\r
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r
+ case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */\r
+ {\r
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r
+ {\r
+ /* In Case the main PLL Source is HSI */\r
+ frequency = HSI_VALUE;\r
+ }\r
+ else\r
+ {\r
+ /* In Case the main PLL Source is HSE */\r
+ frequency = HSE_VALUE;\r
+ }\r
+ break;\r
+ }\r
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r
+ default :\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ return frequency;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions\r
+ * @brief Extended Clock management functions\r
+ *\r
+@verbatim\r
+ ===============================================================================\r
+ ##### Extended clock management functions #####\r
+ ===============================================================================\r
+ [..]\r
+ This subsection provides a set of functions allowing to control the\r
+ activation or deactivation of PLLI2S, PLLSAI.\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enable PLLI2S.\r
+ * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that\r
+ * contains the configuration information for the PLLI2S\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check for parameters */\r
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));\r
+ assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));\r
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));\r
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)\r
+ assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));\r
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */\r
+\r
+ /* Disable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_DISABLE();\r
+\r
+ /* Wait till PLLI2S is disabled */\r
+ tickstart = HAL_GetTick();\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Configure the PLLI2S division factors */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */\r
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */\r
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\r
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);\r
+#else\r
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */\r
+ /* I2SPCLK = PLLI2S_VCO / PLLI2SP */\r
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */\r
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\r
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+ /* Enable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_ENABLE();\r
+\r
+ /* Wait till PLLI2S is ready */\r
+ tickstart = HAL_GetTick();\r
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable PLLI2S.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Disable the PLLI2S */\r
+ __HAL_RCC_PLLI2S_DISABLE();\r
+\r
+ /* Wait till PLLI2S is disabled */\r
+ tickstart = HAL_GetTick();\r
+ while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Enable PLLSAI.\r
+ * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that\r
+ * contains the configuration information for the PLLSAI\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Check for parameters */\r
+ assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));\r
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));\r
+ assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));\r
+#if defined(RCC_PLLSAICFGR_PLLSAIR)\r
+ assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));\r
+#endif /* RCC_PLLSAICFGR_PLLSAIR */\r
+\r
+ /* Disable the PLLSAI */\r
+ __HAL_RCC_PLLSAI_DISABLE();\r
+\r
+ /* Wait till PLLSAI is disabled */\r
+ tickstart = HAL_GetTick();\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ /* Configure the PLLSAI division factors */\r
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */\r
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */\r
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */\r
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ);\r
+#else\r
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */\r
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */\r
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */\r
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */\r
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \\r
+ PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);\r
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r
+\r
+ /* Enable the PLLSAI */\r
+ __HAL_RCC_PLLSAI_ENABLE();\r
+\r
+ /* Wait till PLLSAI is ready */\r
+ tickstart = HAL_GetTick();\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Disable PLLSAI.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)\r
+{\r
+ uint32_t tickstart;\r
+\r
+ /* Disable the PLLSAI */\r
+ __HAL_RCC_PLLSAI_DISABLE();\r
+\r
+ /* Wait till PLLSAI is disabled */\r
+ tickstart = HAL_GetTick();\r
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r
+ {\r
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r
+ {\r
+ /* return in case of Timeout detected */\r
+ return HAL_TIMEOUT;\r
+ }\r
+ }\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim.c\r
+ * @author MCD Application Team\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Timer (TIM) peripheral:\r
+ * + TIM Time Base Initialization\r
+ * + TIM Time Base Start\r
+ * + TIM Time Base Start Interruption\r
+ * + TIM Time Base Start DMA\r
+ * + TIM Output Compare/PWM Initialization\r
+ * + TIM Output Compare/PWM Channel Configuration\r
+ * + TIM Output Compare/PWM Start\r
+ * + TIM Output Compare/PWM Start Interruption\r
+ * + TIM Output Compare/PWM Start DMA\r
+ * + TIM Input Capture Initialization\r
+ * + TIM Input Capture Channel Configuration\r
+ * + TIM Input Capture Start\r
+ * + TIM Input Capture Start Interruption\r
+ * + TIM Input Capture Start DMA\r
+ * + TIM One Pulse Initialization\r
+ * + TIM One Pulse Channel Configuration\r
+ * + TIM One Pulse Start\r
+ * + TIM Encoder Interface Initialization\r
+ * + TIM Encoder Interface Start\r
+ * + TIM Encoder Interface Start Interruption\r
+ * + TIM Encoder Interface Start DMA\r
+ * + Commutation Event configuration with Interruption and DMA\r
+ * + TIM OCRef clear configuration\r
+ * + TIM External Clock configuration\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### TIMER Generic features #####\r
+ ==============================================================================\r
+ [..] The Timer features include:\r
+ (#) 16-bit up, down, up/down auto-reload counter.\r
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the\r
+ counter clock frequency either by any factor between 1 and 65536.\r
+ (#) Up to 4 independent channels for:\r
+ (++) Input Capture\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output\r
+ (#) Synchronization circuit to control the timer with external signals and to interconnect\r
+ several timers together.\r
+ (#) Supports incremental encoder for positioning purposes\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions\r
+ depending on the selected feature:\r
+ (++) Time Base : HAL_TIM_Base_MspInit()\r
+ (++) Input Capture : HAL_TIM_IC_MspInit()\r
+ (++) Output Compare : HAL_TIM_OC_MspInit()\r
+ (++) PWM generation : HAL_TIM_PWM_MspInit()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r
+\r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE();\r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the\r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
+ any start function.\r
+\r
+ (#) Configure the TIM in the desired functioning mode using one of the\r
+ Initialization function of this driver:\r
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an\r
+ Output Compare signal.\r
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a\r
+ PWM signal.\r
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an\r
+ external signal.\r
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer\r
+ in One Pulse Mode.\r
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r
+\r
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:\r
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r
+\r
+ (#) The DMA Burst is managed with the two following functions:\r
+ HAL_TIM_DMABurst_WriteStart()\r
+ HAL_TIM_DMABurst_ReadStart()\r
+\r
+ *** Callback registration ***\r
+ =============================================\r
+\r
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1\r
+ allows the user to configure dynamically the driver callbacks.\r
+\r
+ Use Function @ref HAL_TIM_RegisterCallback() to register a callback.\r
+ @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,\r
+ the Callback ID and a pointer to the user callback function.\r
+\r
+ Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default\r
+ weak function.\r
+ @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\r
+ and the Callback ID.\r
+\r
+ These functions allow to register/unregister following callbacks:\r
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.\r
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.\r
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.\r
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.\r
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.\r
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.\r
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.\r
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.\r
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.\r
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.\r
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.\r
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.\r
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.\r
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.\r
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.\r
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.\r
+ (+) TriggerCallback : TIM Trigger Callback.\r
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.\r
+ (+) IC_CaptureCallback : TIM Input Capture Callback.\r
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.\r
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.\r
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.\r
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.\r
+ (+) ErrorCallback : TIM Error Callback.\r
+ (+) CommutationCallback : TIM Commutation Callback.\r
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.\r
+ (+) BreakCallback : TIM Break Callback.\r
+ (+) Break2Callback : TIM Break2 Callback.\r
+\r
+By default, after the Init and when the state is HAL_TIM_STATE_RESET\r
+all interrupt callbacks are set to the corresponding weak functions:\r
+ examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().\r
+\r
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\r
+ functionalities in the Init / DeInit only when these callbacks are null\r
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit\r
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)\r
+\r
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.\r
+ Exception done MspInit / MspDeInit that can be registered / unregistered\r
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,\r
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.\r
+ In that case first register the MspInit/MspDeInit user callbacks\r
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.\r
+\r
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or\r
+ not defined, the callback registration feature is not available and all callbacks\r
+ are set to the corresponding weak functions.\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM TIM\r
+ * @brief TIM HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/** @addtogroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter);\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig);\r
+/**\r
+ * @}\r
+ */\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @defgroup TIM_Exported_Functions TIM Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions\r
+ * @brief Time Base functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Time Base functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM base.\r
+ (+) De-initialize the TIM base.\r
+ (+) Start the Time Base.\r
+ (+) Stop the Time Base.\r
+ (+) Start the Time Base and enable interrupt.\r
+ (+) Stop the Time Base and disable interrupt.\r
+ (+) Start the Time Base and enable DMA transfer.\r
+ (+) Stop the Time Base and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Time base Unit according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->Base_MspInitCallback == NULL)\r
+ {\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->Base_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the Time Base configuration */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Base peripheral\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->Base_MspDeInitCallback == NULL)\r
+ {\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->Base_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Base_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Base MSP.\r
+ * @param htim TIM Base handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Base MSP.\r
+ * @param htim TIM Base handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Change the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in interrupt mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the TIM Update interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in interrupt mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ /* Disable the TIM Update interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Base generation in DMA mode.\r
+ * @param htim TIM Base handle\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Update DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Base generation in DMA mode.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r
+\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions\r
+ * @brief TIM Output Compare functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Output Compare functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Output Compare.\r
+ (+) De-initialize the TIM Output Compare.\r
+ (+) Start the TIM Output Compare.\r
+ (+) Stop the TIM Output Compare.\r
+ (+) Start the TIM Output Compare and enable interrupt.\r
+ (+) Stop the TIM Output Compare and disable interrupt.\r
+ (+) Start the TIM Output Compare and enable DMA transfer.\r
+ (+) Stop the TIM Output Compare and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Output Compare according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->OC_MspInitCallback == NULL)\r
+ {\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->OC_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the Output Compare */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->OC_MspDeInitCallback == NULL)\r
+ {\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->OC_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare MSP.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Output Compare MSP.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Output compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions\r
+ * @brief TIM PWM functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM PWM functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM PWM.\r
+ (+) De-initialize the TIM PWM.\r
+ (+) Start the TIM PWM.\r
+ (+) Stop the TIM PWM.\r
+ (+) Start the TIM PWM and enable interrupt.\r
+ (+) Stop the TIM PWM and disable interrupt.\r
+ (+) Start the TIM PWM and enable DMA transfer.\r
+ (+) Stop the TIM PWM and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM PWM Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()\r
+ * @param htim TIM PWM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->PWM_MspInitCallback == NULL)\r
+ {\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->PWM_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the PWM */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM PWM handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->PWM_MspDeInitCallback == NULL)\r
+ {\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->PWM_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_PWM_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM MSP.\r
+ * @param htim TIM PWM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM PWM MSP.\r
+ * @param htim TIM PWM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Capture/Compare 3 request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode.\r
+ * @param htim TIM PWM handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions\r
+ * @brief TIM Input Capture functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Input Capture functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Input Capture.\r
+ (+) De-initialize the TIM Input Capture.\r
+ (+) Start the TIM Input Capture.\r
+ (+) Stop the TIM Input Capture.\r
+ (+) Start the TIM Input Capture and enable interrupt.\r
+ (+) Stop the TIM Input Capture and disable interrupt.\r
+ (+) Start the TIM Input Capture and enable DMA transfer.\r
+ (+) Stop the TIM Input Capture and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Input Capture Time base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()\r
+ * @param htim TIM Input Capture handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->IC_MspInitCallback == NULL)\r
+ {\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->IC_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Init the base time for the input capture */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM peripheral\r
+ * @param htim TIM Input Capture handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->IC_MspDeInitCallback == NULL)\r
+ {\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->IC_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_IC_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture MSP.\r
+ * @param htim TIM Input Capture handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Input Capture MSP.\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Enable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Input Capture measurement in DMA mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @param pData The destination Buffer address.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((pData == NULL) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Input Capture measurement in DMA mode.\r
+ * @param htim TIM Input Capture handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Disable the TIM Capture/Compare 4 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Input Capture channel */\r
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions\r
+ * @brief TIM One Pulse functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM One Pulse functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM One Pulse.\r
+ (+) De-initialize the TIM One Pulse.\r
+ (+) Start the TIM One Pulse.\r
+ (+) Stop the TIM One Pulse.\r
+ (+) Start the TIM One Pulse and enable interrupt.\r
+ (+) Stop the TIM One Pulse and disable interrupt.\r
+ (+) Start the TIM One Pulse and enable DMA transfer.\r
+ (+) Stop the TIM One Pulse and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM One Pulse Time Base according to the specified\r
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()\r
+ * @param htim TIM One Pulse handle\r
+ * @param OnePulseMode Select the One pulse mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r
+{\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->OnePulse_MspInitCallback == NULL)\r
+ {\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->OnePulse_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_OnePulse_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Configure the Time base in the One Pulse Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Reset the OPM Bit */\r
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;\r
+\r
+ /* Configure the OPM Mode */\r
+ htim->Instance->CR1 |= OnePulseMode;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM One Pulse\r
+ * @param htim TIM One Pulse handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->OnePulse_MspDeInitCallback == NULL)\r
+ {\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->OnePulse_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_OnePulse_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse MSP.\r
+ * @param htim TIM One Pulse handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM One Pulse MSP.\r
+ * @param htim TIM One Pulse handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Enable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+ No need to enable the counter, it's enabled automatically by hardware\r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be disable\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Disable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Enable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\r
+\r
+ No need to enable the counter, it's enabled automatically by hardware\r
+ (the counter starts in response to a stimulus and generate a pulse */\r
+\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Enable the main output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(OutputChannel);\r
+\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ /* Disable the Capture compare and the Input Capture channels\r
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\r
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\r
+ {\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions\r
+ * @brief TIM Encoder functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Encoder functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure the TIM Encoder.\r
+ (+) De-initialize the TIM Encoder.\r
+ (+) Start the TIM Encoder.\r
+ (+) Stop the TIM Encoder.\r
+ (+) Start the TIM Encoder and enable interrupt.\r
+ (+) Stop the TIM Encoder and disable interrupt.\r
+ (+) Start the TIM Encoder and enable DMA transfer.\r
+ (+) Stop the TIM Encoder and disable DMA transfer.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.\r
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)\r
+ * requires a timer reset to avoid unexpected direction\r
+ * due to DIR bit readonly in center aligned mode.\r
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()\r
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together\r
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource\r
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param sConfig TIM Encoder Interface configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy weak callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->Encoder_MspInitCallback == NULL)\r
+ {\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->Encoder_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIM_Encoder_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Reset the SMS and ECE bits */\r
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);\r
+\r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = htim->Instance->CCER;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr |= sConfig->EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));\r
+\r
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);\r
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+\r
+ /* Write to TIMx CCER */\r
+ htim->Instance->CCER = tmpccer;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Encoder interface\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->Encoder_MspDeInitCallback == NULL)\r
+ {\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->Encoder_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIM_Encoder_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Encoder Interface MSP.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Encoder Interface MSP.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the encoder interface channels */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+ }\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in interrupt mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the encoder interface channels */\r
+ /* Enable the capture compare Interrupts 1 and/or 2 */\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ default :\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in interrupt mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 1 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts 1 and 2 */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Encoder Interface in DMA mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @param pData1 The destination Buffer address for IC1.\r
+ * @param pData2 The destination Buffer address for IC2.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_ALL:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the Peripheral */\r
+ __HAL_TIM_ENABLE(htim);\r
+\r
+ /* Enable the Capture compare channel */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ /* Enable the TIM Input Capture DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Encoder Interface in DMA mode.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1 and 2\r
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 1 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+ else\r
+ {\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare DMA Request 1 and 2 */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ }\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management\r
+ * @brief TIM IRQ handler management\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### IRQ handler management #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides Timer IRQ handler function.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief This function handles TIM interrupts requests.\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Capture compare 1 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)\r
+ {\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ }\r
+ /* Capture compare 2 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 3 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* Capture compare 4 event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ /* Input capture event */\r
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ /* Output compare event */\r
+ else\r
+ {\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->OC_DelayElapsedCallback(htim);\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_OC_DelayElapsedCallback(htim);\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+ }\r
+ }\r
+ /* TIM Update event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM Break input event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->BreakCallback(htim);\r
+#else\r
+ HAL_TIMEx_BreakCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM Break2 input event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->Break2Callback(htim);\r
+#else\r
+ HAL_TIMEx_Break2Callback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM Trigger detection event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+ /* TIM commutation event */\r
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r
+ {\r
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)\r
+ {\r
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->CommutationCallback(htim);\r
+#else\r
+ HAL_TIMEx_CommutCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\r
+ * @brief TIM Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.\r
+ (+) Configure External Clock source.\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master and the Slave synchronization.\r
+ (+) Configure the DMA Burst Mode.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the TIM Output Compare Channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim TIM Output Compare handle\r
+ * @param sConfig TIM Output Compare configuration structure\r
+ * @param Channel TIM Channels to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,\r
+ TIM_OC_InitTypeDef *sConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 1 in Output Compare */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 2 in Output Compare */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 3 in Output Compare */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 4 in Output Compare */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 5 in Output Compare */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the TIM Channel 6 in Output Compare */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Input Capture Channels according to the specified\r
+ * parameters in the TIM_IC_InitTypeDef.\r
+ * @param htim TIM IC handle\r
+ * @param sConfig TIM Input Capture configuration structure\r
+ * @param Channel TIM Channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if (Channel == TIM_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TIM_TI1_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r
+ }\r
+ else if (Channel == TIM_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI2_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Set the IC2PSC value */\r
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);\r
+ }\r
+ else if (Channel == TIM_CHANNEL_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI3_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC3PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r
+\r
+ /* Set the IC3PSC value */\r
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI4_SetConfig(htim->Instance,\r
+ sConfig->ICPolarity,\r
+ sConfig->ICSelection,\r
+ sConfig->ICFilter);\r
+\r
+ /* Reset the IC4PSC Bits */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r
+\r
+ /* Set the IC4PSC value */\r
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM PWM channels according to the specified\r
+ * parameters in the TIM_OC_InitTypeDef.\r
+ * @param htim TIM PWM handle\r
+ * @param sConfig TIM PWM configuration structure\r
+ * @param Channel TIM Channels to be configured\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,\r
+ TIM_OC_InitTypeDef *sConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 1 in PWM mode */\r
+ TIM_OC1_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel1 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 2 in PWM mode */\r
+ TIM_OC2_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel2 */\r
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 3 in PWM mode */\r
+ TIM_OC3_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel3 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 4 in PWM mode */\r
+ TIM_OC4_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel4 */\r
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_5:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 5 in PWM mode */\r
+ TIM_OC5_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel5*/\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_6:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));\r
+\r
+ /* Configure the Channel 6 in PWM mode */\r
+ TIM_OC6_SetConfig(htim->Instance, sConfig);\r
+\r
+ /* Set the Preload enable bit for channel6 */\r
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;\r
+\r
+ /* Configure the Output Fast mode */\r
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;\r
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM One Pulse Channels according to the specified\r
+ * parameters in the TIM_OnePulse_InitTypeDef.\r
+ * @param htim TIM One Pulse handle\r
+ * @param sConfig TIM One Pulse configuration structure\r
+ * @param OutputChannel TIM output channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @param InputChannel TIM input Channel to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)\r
+{\r
+ TIM_OC_InitTypeDef temp1;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r
+\r
+ if (OutputChannel != InputChannel)\r
+ {\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Extract the Output compare configuration from sConfig structure */\r
+ temp1.OCMode = sConfig->OCMode;\r
+ temp1.Pulse = sConfig->Pulse;\r
+ temp1.OCPolarity = sConfig->OCPolarity;\r
+ temp1.OCNPolarity = sConfig->OCNPolarity;\r
+ temp1.OCIdleState = sConfig->OCIdleState;\r
+ temp1.OCNIdleState = sConfig->OCNIdleState;\r
+\r
+ switch (OutputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ TIM_OC1_SetConfig(htim->Instance, &temp1);\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_OC2_SetConfig(htim->Instance, &temp1);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (InputChannel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;\r
+\r
+ /* Select the Slave Mode */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r
+ sConfig->ICSelection, sConfig->ICFilter);\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r
+\r
+ /* Select the Trigger source */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;\r
+\r
+ /* Select the Slave Mode */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+ }\r
+ else\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_OR\r
+ * @arg TIM_DMABASE_CCMR3 \r
+ * @arg TIM_DMABASE_CCR5 \r
+ * @arg TIM_DMABASE_CCR6 \r
+ * @arg TIM_DMABASE_AF1 (*)\r
+ * @arg TIM_DMABASE_AF2 (*)\r
+ * (*) value not defined in all devices\r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ /* Set the DMA commutation callbacks */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ /* Set the DMA trigger callbacks */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+\r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM DMA Burst mode\r
+ * @param htim TIM handle\r
+ * @param BurstRequestSrc TIM DMA Request sources to disable\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+ /* Abort the DMA transfer (at least disable the DMA stream) */\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (HAL_OK == status)\r
+ {\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\r
+ * @param htim TIM handle\r
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABASE_CR1\r
+ * @arg TIM_DMABASE_CR2\r
+ * @arg TIM_DMABASE_SMCR\r
+ * @arg TIM_DMABASE_DIER\r
+ * @arg TIM_DMABASE_SR\r
+ * @arg TIM_DMABASE_EGR\r
+ * @arg TIM_DMABASE_CCMR1\r
+ * @arg TIM_DMABASE_CCMR2\r
+ * @arg TIM_DMABASE_CCER\r
+ * @arg TIM_DMABASE_CNT\r
+ * @arg TIM_DMABASE_PSC\r
+ * @arg TIM_DMABASE_ARR\r
+ * @arg TIM_DMABASE_RCR\r
+ * @arg TIM_DMABASE_CCR1\r
+ * @arg TIM_DMABASE_CCR2\r
+ * @arg TIM_DMABASE_CCR3\r
+ * @arg TIM_DMABASE_CCR4\r
+ * @arg TIM_DMABASE_BDTR\r
+ * @arg TIM_DMABASE_OR\r
+ * @arg TIM_DMABASE_CCMR3 \r
+ * @arg TIM_DMABASE_CCR5 \r
+ * @arg TIM_DMABASE_CCR6 \r
+ * @arg TIM_DMABASE_AF1 (*)\r
+ * @arg TIM_DMABASE_AF2 (*)\r
+ * (*) value not defined in all devices\r
+ * @param BurstRequestSrc TIM DMA Request sources\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r
+ * @param BurstBuffer The Buffer address.\r
+ * @param BurstLength DMA Burst length. This parameter can be one value\r
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r
+ uint32_t *BurstBuffer, uint32_t BurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ /* Set the DMA Period elapsed callbacks */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ /* Set the DMA capture/compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ /* Set the DMA capture callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ /* Set the DMA commutation callbacks */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ /* Set the DMA trigger callbacks */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* configure the DMA Burst Mode */\r
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);\r
+\r
+ /* Enable the TIM DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stop the DMA burst reading\r
+ * @param htim TIM handle\r
+ * @param BurstRequestSrc TIM DMA Request sources to disable.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r
+\r
+ /* Abort the DMA transfer (at least disable the DMA stream) */\r
+ switch (BurstRequestSrc)\r
+ {\r
+ case TIM_DMA_UPDATE:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC1:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC2:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC3:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+ case TIM_DMA_CC4:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\r
+ break;\r
+ }\r
+ case TIM_DMA_COM:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r
+ break;\r
+ }\r
+ case TIM_DMA_TRIGGER:\r
+ {\r
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (HAL_OK == status)\r
+ {\r
+ /* Disable the TIM Update DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r
+ }\r
+\r
+ /* Return function status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Generate a software event\r
+ * @param htim TIM handle\r
+ * @param EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source\r
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source\r
+ * @note Basic timers can only generate an update event.\r
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.\r
+ * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant\r
+ * only for timer instances supporting break input(s).\r
+ * @retval HAL status\r
+ */\r
+\r
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Set the event sources */\r
+ htim->Instance->EGR = EventSource;\r
+\r
+ /* Change the TIM state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the OCRef clear feature\r
+ * @param htim TIM handle\r
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that\r
+ * contains the OCREF clear feature and parameters for the TIM peripheral.\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,\r
+ uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ switch (sClearInputConfig->ClearInputSource)\r
+ {\r
+ case TIM_CLEARINPUTSOURCE_NONE:\r
+ {\r
+ /* Clear the OCREF clear selection bit and the the ETR Bits */\r
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));\r
+ break;\r
+ }\r
+\r
+ case TIM_CLEARINPUTSOURCE_ETR:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r
+\r
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */\r
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClearInputConfig->ClearInputPrescaler,\r
+ sClearInputConfig->ClearInputPolarity,\r
+ sClearInputConfig->ClearInputFilter);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 1 */\r
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 1 */\r
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 2 */\r
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 2 */\r
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 3 */\r
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 3 */\r
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 4 */\r
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 4 */\r
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_5:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 5 */\r
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 5 */\r
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);\r
+ }\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_6:\r
+ {\r
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\r
+ {\r
+ /* Enable the OCREF clear feature for Channel 6 */\r
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the OCREF clear feature for Channel 6 */\r
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);\r
+ }\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the clock source to be used\r
+ * @param htim TIM handle\r
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that\r
+ * contains the clock source information for the TIM peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r
+\r
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ switch (sClockSourceConfig->ClockSource)\r
+ {\r
+ case TIM_CLOCKSOURCE_INTERNAL:\r
+ {\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ETRMODE1:\r
+ {\r
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+\r
+ /* Check ETR input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClockSourceConfig->ClockPrescaler,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+\r
+ /* Select the External clock mode1 and the ETRF trigger */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ETRMODE2:\r
+ {\r
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));\r
+\r
+ /* Check ETR input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sClockSourceConfig->ClockPrescaler,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ /* Enable the External clock mode2 */\r
+ htim->Instance->SMCR |= TIM_SMCR_ECE;\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI1:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 */\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI2:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI2 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_TI1ED:\r
+ {\r
+ /* Check whether or not the timer instance supports external clock mode 1 */\r
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r
+\r
+ /* Check TI1 input conditioning related parameters */\r
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r
+\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sClockSourceConfig->ClockPolarity,\r
+ sClockSourceConfig->ClockFilter);\r
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r
+ break;\r
+ }\r
+\r
+ case TIM_CLOCKSOURCE_ITR0:\r
+ case TIM_CLOCKSOURCE_ITR1:\r
+ case TIM_CLOCKSOURCE_ITR2:\r
+ case TIM_CLOCKSOURCE_ITR3:\r
+ {\r
+ /* Check whether or not the timer instance supports internal trigger input */\r
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r
+\r
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input\r
+ * or a XOR combination between CH1_input, CH2_input & CH3_input\r
+ * @param htim TIM handle.\r
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the\r
+ * output of a XOR gate.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r
+ * pins are connected to the TI1 input (XOR combination)\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r
+{\r
+ uint32_t tmpcr2;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Reset the TI1 selection */\r
+ tmpcr2 &= ~TIM_CR2_TI1S;\r
+\r
+ /* Set the TI1 selection */\r
+ tmpcr2 |= TI1_Selection;\r
+\r
+ /* Write to TIMxCR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode\r
+ * @param htim TIM handle.\r
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the Slave mode\r
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable Trigger Interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in Slave mode in interrupt mode\r
+ * @param htim TIM handle.\r
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r
+ * contains the selected trigger (internal trigger input, filtered\r
+ * timer input or external trigger input) and the Slave mode\r
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\r
+ {\r
+ htim->State = HAL_TIM_STATE_READY;\r
+ __HAL_UNLOCK(htim);\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Enable Trigger Interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r
+\r
+ /* Disable Trigger DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Read the captured value from Capture Compare unit\r
+ * @param htim TIM handle.\r
+ * @param Channel TIM Channels to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected\r
+ * @retval Captured value\r
+ */\r
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpreg = 0U;\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 1 value */\r
+ tmpreg = htim->Instance->CCR1;\r
+\r
+ break;\r
+ }\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 2 value */\r
+ tmpreg = htim->Instance->CCR2;\r
+\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 3 value */\r
+ tmpreg = htim->Instance->CCR3;\r
+\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_4:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r
+\r
+ /* Return the capture 4 value */\r
+ tmpreg = htim->Instance->CCR4;\r
+\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return tmpreg;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r
+ * @brief TIM Callbacks functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### TIM Callbacks functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides TIM callback functions:\r
+ (+) TIM Period elapsed callback\r
+ (+) TIM Output Compare callback\r
+ (+) TIM Input capture callback\r
+ (+) TIM Trigger callback\r
+ (+) TIM Error callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Period elapsed callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Period elapsed half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Output Compare callback in non-blocking mode\r
+ * @param htim TIM OC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input Capture callback in non-blocking mode\r
+ * @param htim TIM IC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Input Capture half complete callback in non-blocking mode\r
+ * @param htim TIM IC handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief PWM Pulse finished half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Trigger detection half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Timer error callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIM_ErrorCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback\r
+ * @param htim tim handle\r
+ * @param CallbackID ID of the callback to be registered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
+ * @param pCallback pointer to the callback function\r
+ * @retval status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ if (pCallback == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Process locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ if (htim->State == HAL_TIM_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+ htim->PeriodElapsedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+ htim->PeriodElapsedHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_CB_ID :\r
+ htim->TriggerCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+ htim->TriggerHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_CB_ID :\r
+ htim->IC_CaptureCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+ htim->IC_CaptureHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+ htim->OC_DelayElapsedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+ htim->PWM_PulseFinishedCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ERROR_CB_ID :\r
+ htim->ErrorCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_CB_ID :\r
+ htim->CommutationCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
+ htim->CommutationHalfCpltCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BREAK_CB_ID :\r
+ htim->BreakCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BREAK2_CB_ID :\r
+ htim->Break2Callback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = pCallback;\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = pCallback;\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Unregister a TIM callback\r
+ * TIM callback is redirected to the weak predefined callback\r
+ * @param htim tim handle\r
+ * @param CallbackID ID of the callback to be unregistered\r
+ * This parameter can be one of the following values:\r
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\r
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\r
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\r
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID\r
+ * @retval status\r
+ */\r
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)\r
+{\r
+ HAL_StatusTypeDef status = HAL_OK;\r
+\r
+ /* Process locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ if (htim->State == HAL_TIM_STATE_READY)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\r
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_CB_ID :\r
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */\r
+ break;\r
+\r
+ case HAL_TIM_TRIGGER_HALF_CB_ID :\r
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_CB_ID :\r
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\r
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\r
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ERROR_CB_ID :\r
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_CB_ID :\r
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */\r
+ break;\r
+\r
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :\r
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BREAK_CB_ID :\r
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BREAK2_CB_ID :\r
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ switch (CallbackID)\r
+ {\r
+ case HAL_TIM_BASE_MSPINIT_CB_ID :\r
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPINIT_CB_ID :\r
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :\r
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPINIT_CB_ID :\r
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :\r
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPINIT_CB_ID :\r
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */\r
+ break;\r
+\r
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */\r
+ break;\r
+\r
+ default :\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return error status */\r
+ status = HAL_ERROR;\r
+ }\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return status;\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\r
+ * @brief TIM Peripheral State functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral State functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Base handle state.\r
+ * @param htim TIM Base handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM OC handle state.\r
+ * @param htim TIM Output Compare handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM PWM handle state.\r
+ * @param htim TIM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Input Capture handle state.\r
+ * @param htim TIM IC handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM One Pulse Mode handle state.\r
+ * @param htim TIM OPM handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @brief Return the TIM Encoder Mode handle state.\r
+ * @param htim TIM Encoder Interface handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Functions TIM Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA error callback\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMAError(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->ErrorCallback(htim);\r
+#else\r
+ HAL_TIM_ErrorCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PWM_PulseFinishedCallback(htim);\r
+#else\r
+ HAL_TIM_PWM_PulseFinishedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Delay Pulse half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Capture complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Capture half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r
+ }\r
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r
+ {\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->IC_CaptureHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Period Elapse half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->PeriodElapsedHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Trigger half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->TriggerHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIM_TriggerHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief Time Base configuration\r
+ * @param TIMx TIM peripheral\r
+ * @param Structure TIM Base configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r
+{\r
+ uint32_t tmpcr1;\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/\r
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))\r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r
+ tmpcr1 |= Structure->CounterMode;\r
+ }\r
+\r
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= ~TIM_CR1_CKD;\r
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;\r
+ }\r
+\r
+ /* Set the auto-reload preload */\r
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = (uint32_t)Structure->Period ;\r
+\r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Structure->Prescaler;\r
+\r
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))\r
+ {\r
+ /* Set the Repetition Counter value */\r
+ TIMx->RCR = Structure->RepetitionCounter;\r
+ }\r
+\r
+ /* Generate an update event to reload the Prescaler\r
+ and the repetition counter (only for advanced timer) value immediately */\r
+ TIMx->EGR = TIM_EGR_UG;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 1 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC1M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC1S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= OC_Config->OCPolarity;\r
+\r
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC1NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= OC_Config->OCNPolarity;\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC1NE;\r
+ }\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS1;\r
+ tmpcr2 &= ~TIM_CR2_OIS1N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= OC_Config->OCIdleState;\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= OC_Config->OCNIdleState;\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 2 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR1_OC2M;\r
+ tmpccmrx &= ~TIM_CCMR1_CC2S;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 4U);\r
+\r
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC2NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 4U);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC2NE;\r
+\r
+ }\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS2;\r
+ tmpcr2 &= ~TIM_CR2_OIS2N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 3 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 3: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC3M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC3S;\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 8U);\r
+\r
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))\r
+ {\r
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r
+\r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC3NP;\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (OC_Config->OCNPolarity << 8U);\r
+ /* Reset the Output N State */\r
+ tmpccer &= ~TIM_CCER_CC3NE;\r
+ }\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS3;\r
+ tmpcr2 &= ~TIM_CR2_OIS3N;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 4 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+\r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= ~TIM_CCMR2_OC4M;\r
+ tmpccmrx &= ~TIM_CCMR2_CC4S;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC4P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 12U);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r
+\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS4;\r
+\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 5 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,\r
+ TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC5E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= OC_Config->OCMode;\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= ~TIM_CCER_CC5P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 16U);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS5;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR5 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Timer Output Compare 6 configuration\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param OC_Config The ouput configuration structure\r
+ * @retval None\r
+ */\r
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,\r
+ TIM_OC_InitTypeDef *OC_Config)\r
+{\r
+ uint32_t tmpccmrx;\r
+ uint32_t tmpccer;\r
+ uint32_t tmpcr2;\r
+\r
+ /* Disable the output: Reset the CCxE Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC6E;\r
+\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR3;\r
+\r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (OC_Config->OCMode << 8U);\r
+\r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (OC_Config->OCPolarity << 20U);\r
+\r
+ if (IS_TIM_BREAK_INSTANCE(TIMx))\r
+ {\r
+ /* Reset the Output Compare IDLE State */\r
+ tmpcr2 &= ~TIM_CR2_OIS6;\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);\r
+ }\r
+\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+\r
+ /* Write to TIMx CCMR3 */\r
+ TIMx->CCMR3 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR6 = OC_Config->Pulse;\r
+\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Slave Timer configuration function\r
+ * @param htim TIM handle\r
+ * @param sSlaveConfig Slave timer configuration\r
+ * @retval None\r
+ */\r
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r
+ TIM_SlaveConfigTypeDef *sSlaveConfig)\r
+{\r
+ uint32_t tmpsmcr;\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* Reset the Trigger Selection Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= sSlaveConfig->InputTrigger;\r
+\r
+ /* Reset the slave mode Bits */\r
+ tmpsmcr &= ~TIM_SMCR_SMS;\r
+ /* Set the slave mode */\r
+ tmpsmcr |= sSlaveConfig->SlaveMode;\r
+\r
+ /* Write to TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Configure the trigger prescaler, filter, and polarity */\r
+ switch (sSlaveConfig->InputTrigger)\r
+ {\r
+ case TIM_TS_ETRF:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+ /* Configure the ETR Trigger source */\r
+ TIM_ETR_SetConfig(htim->Instance,\r
+ sSlaveConfig->TriggerPrescaler,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI1F_ED:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = htim->Instance->CCER;\r
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = htim->Instance->CCMR1;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ htim->Instance->CCMR1 = tmpccmr1;\r
+ htim->Instance->CCER = tmpccer;\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI1FP1:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI1 Filter and Polarity */\r
+ TIM_TI1_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_TI2FP2:\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r
+\r
+ /* Configure TI2 Filter and Polarity */\r
+ TIM_TI2_ConfigInputStage(htim->Instance,\r
+ sSlaveConfig->TriggerPolarity,\r
+ sSlaveConfig->TriggerFilter);\r
+ break;\r
+ }\r
+\r
+ case TIM_TS_ITR0:\r
+ case TIM_TS_ITR1:\r
+ case TIM_TS_ITR2:\r
+ case TIM_TS_ITR3:\r
+ {\r
+ /* Check the parameter */\r
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1\r
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r
+ {\r
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;\r
+ tmpccmr1 |= TIM_ICSelection;\r
+ }\r
+ else\r
+ {\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;\r
+ }\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI1.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ tmpccer = TIMx->CCER;\r
+ TIMx->CCER &= ~TIM_CCER_CC1E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;\r
+ tmpccmr1 |= (TIM_ICFilter << 4U);\r
+\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_ICPolarity;\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;\r
+ tmpccmr1 |= (TIM_ICSelection << 8U);\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the Polarity and Filter for TI2.\r
+ * @param TIMx to select the TIM peripheral.\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr1;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC2E;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set the filter */\r
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;\r
+ tmpccmr1 |= (TIM_ICFilter << 12U);\r
+\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r
+ tmpccer |= (TIM_ICPolarity << 4U);\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ */\r
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC3E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;\r
+ tmpccmr2 |= TIM_ICSelection;\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);\r
+\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPOLARITY_RISING\r
+ * @arg TIM_ICPOLARITY_FALLING\r
+ * @arg TIM_ICPOLARITY_BOTHEDGE\r
+ * @param TIM_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3\r
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be\r
+ * protected against un-initialized filter and polarity values.\r
+ * @retval None\r
+ */\r
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r
+ uint32_t TIM_ICFilter)\r
+{\r
+ uint32_t tmpccmr2;\r
+ uint32_t tmpccer;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= ~TIM_CCER_CC4E;\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Select the Input */\r
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;\r
+ tmpccmr2 |= (TIM_ICSelection << 8U);\r
+\r
+ /* Set the filter */\r
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;\r
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);\r
+\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r
+\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer ;\r
+}\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param InputTriggerSource The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= ~TIM_SMCR_TS;\r
+ /* Set the Input Trigger source and the slave mode*/\r
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.\r
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.\r
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.\r
+ * @param ExtTRGFilter External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\r
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r
+\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));\r
+\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @arg TIM_CHANNEL_4: TIM Channel 4\r
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected\r
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected\r
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)\r
+{\r
+ uint32_t tmp;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));\r
+ assert_param(IS_TIM_CHANNELS(Channel));\r
+\r
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxE Bit */\r
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
+}\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+/**\r
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.\r
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains\r
+ * the configuration information for TIM module.\r
+ * @retval None\r
+ */\r
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Reset the TIM callback to the legacy weak callbacks */\r
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */\r
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */\r
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */\r
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */\r
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */\r
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */\r
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */\r
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */\r
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */\r
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */\r
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */\r
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */\r
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */\r
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */\r
+}\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_tim_ex.c\r
+ * @author MCD Application Team\r
+ * @brief TIM HAL module driver.\r
+ * This file provides firmware functions to manage the following\r
+ * functionalities of the Timer Extended peripheral:\r
+ * + Time Hall Sensor Interface Initialization\r
+ * + Time Hall Sensor Interface Start\r
+ * + Time Complementary signal break and dead time configuration\r
+ * + Time Master and Slave synchronization configuration\r
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)\r
+ * + Timer remapping capabilities configuration\r
+ @verbatim\r
+ ==============================================================================\r
+ ##### TIMER Extended features #####\r
+ ==============================================================================\r
+ [..]\r
+ The Timer Extended features include:\r
+ (#) Complementary outputs with programmable dead-time for :\r
+ (++) Output Compare\r
+ (++) PWM generation (Edge and Center-aligned Mode)\r
+ (++) One-pulse mode output\r
+ (#) Synchronization circuit to control the timer with external signals and to\r
+ interconnect several timers together.\r
+ (#) Break input to put the timer output signals in reset state or in a known state.\r
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for\r
+ positioning purposes\r
+\r
+ ##### How to use this driver #####\r
+ ==============================================================================\r
+ [..]\r
+ (#) Initialize the TIM low level resources by implementing the following functions\r
+ depending on the selected feature:\r
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()\r
+\r
+ (#) Initialize the TIM low level resources :\r
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\r
+ (##) TIM pins configuration\r
+ (+++) Enable the clock for the TIM GPIOs using the following function:\r
+ __HAL_RCC_GPIOx_CLK_ENABLE();\r
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\r
+\r
+ (#) The external Clock can be configured, if needed (the default clock is the\r
+ internal clock from the APBx), using the following function:\r
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before\r
+ any start function.\r
+\r
+ (#) Configure the TIM in the desired functioning mode using one of the\r
+ initialization function of this driver:\r
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the\r
+ Timer Hall Sensor Interface and the commutation event with the corresponding\r
+ Interrupt and DMA request if needed (Note that One Timer is used to interface\r
+ with the Hall sensor Interface and another Timer should be used to use\r
+ the commutation event).\r
+\r
+ (#) Activate the TIM peripheral using one of the start functions:\r
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()\r
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r
+\r
+ @endverbatim\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+*/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/** @addtogroup STM32F7xx_HAL_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx TIMEx\r
+ * @brief TIM Extended HAL module driver\r
+ * @{\r
+ */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r
+ * @brief Timer Hall Sensor functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Hall Sensor functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Initialize and configure TIM HAL Sensor.\r
+ (+) De-initialize TIM HAL Sensor.\r
+ (+) Start the Hall Sensor Interface.\r
+ (+) Stop the Hall Sensor Interface.\r
+ (+) Start the Hall Sensor Interface and enable interrupts.\r
+ (+) Stop the Hall Sensor Interface and disable interrupts.\r
+ (+) Start the Hall Sensor Interface and enable DMA transfers.\r
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @param sConfig TIM Hall Sensor configuration structure\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)\r
+{\r
+ TIM_OC_InitTypeDef OC_Config;\r
+\r
+ /* Check the TIM handle allocation */\r
+ if (htim == NULL)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r
+\r
+ if (htim->State == HAL_TIM_STATE_RESET)\r
+ {\r
+ /* Allocate lock resource and initialize it */\r
+ htim->Lock = HAL_UNLOCKED;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ /* Reset interrupt callbacks to legacy week callbacks */\r
+ TIM_ResetCallback(htim);\r
+\r
+ if (htim->HallSensor_MspInitCallback == NULL)\r
+ {\r
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;\r
+ }\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */\r
+ htim->HallSensor_MspInitCallback(htim);\r
+#else\r
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r
+ HAL_TIMEx_HallSensor_MspInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+ }\r
+\r
+ /* Set the TIM state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Configure the Time base in the Encoder Mode */\r
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);\r
+\r
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */\r
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r
+ /* Set the IC1PSC value */\r
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r
+\r
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */\r
+ htim->Instance->CR2 |= TIM_CR2_TI1S;\r
+\r
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r
+\r
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r
+\r
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r
+ OC_Config.OCMode = TIM_OCMODE_PWM2;\r
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r
+ OC_Config.Pulse = sConfig->Commutation_Delay;\r
+\r
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r
+\r
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r
+ register to 101 */\r
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;\r
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;\r
+\r
+ /* Initialize the TIM state*/\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes the TIM Hall Sensor interface\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_INSTANCE(htim->Instance));\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Disable the TIM Peripheral Clock */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ if (htim->HallSensor_MspDeInitCallback == NULL)\r
+ {\r
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;\r
+ }\r
+ /* DeInit the low level hardware */\r
+ htim->HallSensor_MspDeInitCallback(htim);\r
+#else\r
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r
+ HAL_TIMEx_HallSensor_MspDeInit(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+\r
+ /* Change TIM state */\r
+ htim->State = HAL_TIM_STATE_RESET;\r
+\r
+ /* Release Lock */\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM Hall Sensor MSP.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief DeInitializes TIM Hall Sensor MSP.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall sensor Interface.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channels 1, 2 and 3\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Enable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Enable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+ /* Disable the capture compare Interrupts event */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @param pData The destination Buffer address.\r
+ * @param Length The length of data to be transferred from TIM peripheral to memory.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if (((uint32_t)pData == 0U) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ /* Enable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r
+\r
+ /* Set the DMA Input Capture 1 Callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream for Capture 1*/\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the capture compare 1 Interrupt */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.\r
+ * @param htim TIM Hall Sensor Interface handle\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\r
+\r
+ /* Disable the Input Capture channel 1\r
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\r
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r
+\r
+\r
+ /* Disable the capture compare Interrupts 1 event */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r
+ * @brief Timer Complementary Output Compare functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Complementary Output Compare functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary Output Compare/PWM.\r
+ (+) Stop the Complementary Output Compare/PWM.\r
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.\r
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode\r
+ * on the complementary output.\r
+ * @param htim TIM OC handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Output Compare interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode\r
+ * on the complementary output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM Output Compare signal generation in DMA mode\r
+ * on the complementary output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if (((uint32_t)pData == 0U) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Output Compare DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM Output Compare signal generation in DMA mode\r
+ * on the complementary output.\r
+ * @param htim TIM Output Compare handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Output Compare DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the Capture compare channel N */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r
+ * @brief Timer Complementary PWM functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Complementary PWM functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary PWM.\r
+ (+) Stop the Complementary PWM.\r
+ (+) Start the Complementary PWM and enable interrupts.\r
+ (+) Stop the Complementary PWM and disable interrupts.\r
+ (+) Start the Complementary PWM and enable DMA transfers.\r
+ (+) Stop the Complementary PWM and disable DMA transfers.\r
+ (+) Start the Complementary Input Capture measurement.\r
+ (+) Stop the Complementary Input Capture.\r
+ (+) Start the Complementary Input Capture and enable interrupts.\r
+ (+) Stop the Complementary Input Capture and disable interrupts.\r
+ (+) Start the Complementary Input Capture and enable DMA transfers.\r
+ (+) Stop the Complementary Input Capture and disable DMA transfers.\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation on the complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation on the complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the PWM signal generation in interrupt mode on the\r
+ * complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Enable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the TIM Break interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the PWM signal generation in interrupt mode on the\r
+ * complementary output.\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ uint32_t tmpccer;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the TIM Break interrupt (only if no more channel is active) */\r
+ tmpccer = htim->Instance->CCER;\r
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\r
+ {\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r
+ }\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM PWM signal generation in DMA mode on the\r
+ * complementary output\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @param pData The source Buffer address.\r
+ * @param Length The length of data to be transferred from memory to TIM peripheral\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r
+{\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ if ((htim->State == HAL_TIM_STATE_BUSY))\r
+ {\r
+ return HAL_BUSY;\r
+ }\r
+ else if ((htim->State == HAL_TIM_STATE_READY))\r
+ {\r
+ if (((uint32_t)pData == 0U) && (Length > 0U))\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ else\r
+ {\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* nothing to do */\r
+ }\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Set the DMA compare callbacks */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\r
+\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\r
+\r
+ /* Enable the DMA stream */\r
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\r
+ {\r
+ return HAL_ERROR;\r
+ }\r
+ /* Enable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Enable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\r
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\r
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\r
+ {\r
+ __HAL_TIM_ENABLE(htim);\r
+ }\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary\r
+ * output\r
+ * @param htim TIM handle\r
+ * @param Channel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\r
+\r
+ switch (Channel)\r
+ {\r
+ case TIM_CHANNEL_1:\r
+ {\r
+ /* Disable the TIM Capture/Compare 1 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_2:\r
+ {\r
+ /* Disable the TIM Capture/Compare 2 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\r
+ break;\r
+ }\r
+\r
+ case TIM_CHANNEL_3:\r
+ {\r
+ /* Disable the TIM Capture/Compare 3 DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Disable the complementary PWM output */\r
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r
+ * @brief Timer Complementary One Pulse functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Timer Complementary One Pulse functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Start the Complementary One Pulse generation.\r
+ (+) Stop the Complementary One Pulse.\r
+ (+) Start the Complementary One Pulse and enable interrupts.\r
+ (+) Stop the Complementary One Pulse and disable interrupts.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation on the complementary\r
+ * output.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be enabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Enable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Enable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ /* Enable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\r
+\r
+ /* Enable the Main Output */\r
+ __HAL_TIM_MOE_ENABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the\r
+ * complementary channel.\r
+ * @param htim TIM One Pulse handle\r
+ * @param OutputChannel TIM Channel to be disabled\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\r
+\r
+ /* Disable the TIM Capture/Compare 1 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r
+\r
+ /* Disable the TIM Capture/Compare 2 interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r
+\r
+ /* Disable the complementary One Pulse output */\r
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r
+\r
+ /* Disable the Main Output */\r
+ __HAL_TIM_MOE_DISABLE(htim);\r
+\r
+ /* Disable the Peripheral */\r
+ __HAL_TIM_DISABLE(htim);\r
+\r
+ /* Return function status */\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r
+ * @brief Peripheral Control functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Peripheral Control functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides functions allowing to:\r
+ (+) Configure the commutation event in case of use of the Hall sensor interface.\r
+ (+) Configure Output channels for OC and PWM mode.\r
+\r
+ (+) Configure Complementary channels, break features and dead time.\r
+ (+) Configure Master synchronization.\r
+ (+) Configure timer remapping capabilities.\r
+ (+) Enable or disable channel grouping.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence.\r
+ * @note This function is mandatory to use the commutation event in order to\r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer)\r
+ * configured in Hall sensor interface, this interface Timer will generate the\r
+ * commutation at its TRGO output (connected to Timer used in this function) each time\r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim TIM handle\r
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource the Commutation Event source\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ {\r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+\r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+\r
+ /* Disable Commutation Interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
+\r
+ /* Disable Commutation DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with interrupt.\r
+ * @note This function is mandatory to use the commutation event in order to\r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer)\r
+ * configured in Hall sensor interface, this interface Timer will generate the\r
+ * commutation at its TRGO output (connected to Timer used in this function) each time\r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @param htim TIM handle\r
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource the Commutation Event source\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ {\r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+\r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+\r
+ /* Disable Commutation DMA request */\r
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ /* Enable the Commutation Interrupt */\r
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TIM commutation event sequence with DMA.\r
+ * @note This function is mandatory to use the commutation event in order to\r
+ * update the configuration at each commutation detection on the TRGI input of the Timer,\r
+ * the typical use of this feature is with the use of another Timer(interface Timer)\r
+ * configured in Hall sensor interface, this interface Timer will generate the\r
+ * commutation at its TRGO output (connected to Timer used in this function) each time\r
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.\r
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set\r
+ * @param htim TIM handle\r
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected\r
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected\r
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected\r
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected\r
+ * @arg TIM_TS_NONE: No trigger is needed\r
+ * @param CommutationSource the Commutation Event source\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r
+\r
+ __HAL_LOCK(htim);\r
+\r
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r
+ {\r
+ /* Select the Input trigger */\r
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;\r
+ htim->Instance->SMCR |= InputTrigger;\r
+ }\r
+\r
+ /* Select the Capture Compare preload feature */\r
+ htim->Instance->CR2 |= TIM_CR2_CCPC;\r
+ /* Select the Commutation event source */\r
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r
+ htim->Instance->CR2 |= CommutationSource;\r
+\r
+ /* Enable the Commutation DMA Request */\r
+ /* Set the DMA Commutation Callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\r
+ /* Set the DMA error callback */\r
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;\r
+\r
+ /* Disable Commutation Interrupt */\r
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\r
+\r
+ /* Enable the Commutation DMA Request */\r
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM in master mode.\r
+ * @param htim TIM handle.\r
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that\r
+ * contains the selected trigger output (TRGO) and the Master/Slave\r
+ * mode.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\r
+ TIM_MasterConfigTypeDef *sMasterConfig)\r
+{\r
+ uint32_t tmpcr2;\r
+ uint32_t tmpsmcr;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Change the handler state */\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = htim->Instance->CR2;\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = htim->Instance->SMCR;\r
+\r
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */\r
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));\r
+\r
+ /* Clear the MMS2 bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS2;\r
+ /* Select the TRGO2 source*/\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;\r
+ }\r
+\r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= ~TIM_CR2_MMS;\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;\r
+\r
+ /* Reset the MSM Bit */\r
+ tmpsmcr &= ~TIM_SMCR_MSM;\r
+ /* Set master mode */\r
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;\r
+\r
+ /* Update TIMx CR2 */\r
+ htim->Instance->CR2 = tmpcr2;\r
+\r
+ /* Update TIMx SMCR */\r
+ htim->Instance->SMCR = tmpsmcr;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r
+ * and the AOE(automatic output enable).\r
+ * @param htim TIM handle\r
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that\r
+ * contains the BDTR Register configuration information for the TIM peripheral.\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\r
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)\r
+{\r
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */\r
+ uint32_t tmpbdtr = 0U;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));\r
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+\r
+ /* Set the BDTR bits */\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));\r
+\r
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance))\r
+ {\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));\r
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));\r
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));\r
+\r
+ /* Set the BREAK2 input related BDTR bits */\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);\r
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);\r
+ }\r
+\r
+ /* Set TIMx_BDTR */\r
+ htim->Instance->BDTR = tmpbdtr;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+#if defined(TIM_BREAK_INPUT_SUPPORT)\r
+\r
+/**\r
+ * @brief Configures the break input source.\r
+ * @param htim TIM handle.\r
+ * @param BreakInput Break input to configure\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_BREAKINPUT_BRK: Timer break input\r
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input\r
+ * @param sBreakInputConfig Break input source configuration\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,\r
+ uint32_t BreakInput,\r
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)\r
+\r
+{\r
+ uint32_t tmporx;\r
+ uint32_t bkin_enable_mask = 0U;\r
+ uint32_t bkin_polarity_mask = 0U;\r
+ uint32_t bkin_enable_bitpos = 0U;\r
+ uint32_t bkin_polarity_bitpos = 0U;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));\r
+#if defined(DFSDM1_Channel0)\r
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+ {\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));\r
+ }\r
+#else\r
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));\r
+#endif /* DFSDM1_Channel0 */\r
+\r
+ /* Check input state */\r
+ __HAL_LOCK(htim);\r
+\r
+ switch (sBreakInputConfig->Source)\r
+ {\r
+ case TIM_BREAKINPUTSOURCE_BKIN:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKINE;\r
+ bkin_enable_bitpos = 0;\r
+ bkin_polarity_mask = TIM1_AF1_BKINP;\r
+ bkin_polarity_bitpos = 9;\r
+ break;\r
+ }\r
+\r
+ case TIM_BREAKINPUTSOURCE_DFSDM1:\r
+ {\r
+ bkin_enable_mask = TIM1_AF1_BKDF1BKE;\r
+ bkin_enable_bitpos = 8;\r
+ break;\r
+ }\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ switch (BreakInput)\r
+ {\r
+ case TIM_BREAKINPUT_BRK:\r
+ {\r
+ /* Get the TIMx_AF1 register value */\r
+ tmporx = htim->Instance->AF1;\r
+\r
+ /* Enable the break input */\r
+ tmporx &= ~bkin_enable_mask;\r
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+\r
+ /* Set the break input polarity */\r
+#if defined(DFSDM1_Channel0)\r
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+#endif /* DFSDM1_Channel0 */\r
+ {\r
+ tmporx &= ~bkin_polarity_mask;\r
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
+ }\r
+\r
+ /* Set TIMx_AF1 */\r
+ htim->Instance->AF1 = tmporx;\r
+ break;\r
+ }\r
+ case TIM_BREAKINPUT_BRK2:\r
+ {\r
+ /* Get the TIMx_AF2 register value */\r
+ tmporx = htim->Instance->AF2;\r
+\r
+ /* Enable the break input */\r
+ tmporx &= ~bkin_enable_mask;\r
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r
+\r
+ /* Set the break input polarity */\r
+#if defined(DFSDM1_Channel0)\r
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)\r
+#endif /* DFSDM1_Channel0 */\r
+ {\r
+ tmporx &= ~bkin_polarity_mask;\r
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;\r
+ }\r
+\r
+ /* Set TIMx_AF2 */\r
+ htim->Instance->AF2 = tmporx;\r
+ break;\r
+ }\r
+ default:\r
+ break;\r
+ }\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+#endif /*TIM_BREAK_INPUT_SUPPORT */\r
+\r
+/**\r
+ * @brief Configures the TIMx Remapping input capabilities.\r
+ * @param htim TIM handle.\r
+ * @param Remap specifies the TIM remapping source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)\r
+ * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.\r
+ * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.\r
+ * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.\r
+ * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)\r
+ * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.\r
+ * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.\r
+ * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.\r
+ * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)\r
+ * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous\r
+ * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock\r
+ * (HSE divided by a programmable prescaler)\r
+ * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1\r
+ *\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r
+{\r
+ __HAL_LOCK(htim);\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_REMAP(Remap));\r
+\r
+ /* Set the Timer remapping configuration */\r
+ htim->Instance->OR = Remap;\r
+\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @brief Group channel 5 and channel 1, 2 or 3\r
+ * @param htim TIM handle.\r
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.\r
+ * This parameter can be any combination of the following values:\r
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC\r
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF\r
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF\r
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF\r
+ * @retval HAL status\r
+ */\r
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));\r
+ assert_param(IS_TIM_GROUPCH5(Channels));\r
+\r
+ /* Process Locked */\r
+ __HAL_LOCK(htim);\r
+\r
+ htim->State = HAL_TIM_STATE_BUSY;\r
+\r
+ /* Clear GC5Cx bit fields */\r
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);\r
+\r
+ /* Set GC5Cx bit fields */\r
+ htim->Instance->CCR5 |= Channels;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+ __HAL_UNLOCK(htim);\r
+\r
+ return HAL_OK;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\r
+ * @brief Extended Callbacks functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Extended Callbacks functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This section provides Extended TIM callback functions:\r
+ (+) Timer Commutation callback\r
+ (+) Timer Break callback\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Hall commutation changed callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_CommutCallback could be implemented in the user file\r
+ */\r
+}\r
+/**\r
+ * @brief Hall commutation changed half complete callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Break detection callback in non-blocking mode\r
+ * @param htim TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_BreakCallback could be implemented in the user file\r
+ */\r
+}\r
+\r
+/**\r
+ * @brief Hall Break2 detection callback in non blocking mode\r
+ * @param htim: TIM handle\r
+ * @retval None\r
+ */\r
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)\r
+{\r
+ /* Prevent unused argument(s) compilation warning */\r
+ UNUSED(htim);\r
+\r
+ /* NOTE : This function Should not be modified, when the callback is needed,\r
+ the HAL_TIMEx_Break2Callback could be implemented in the user file\r
+ */\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\r
+ * @brief Extended Peripheral State functions\r
+ *\r
+@verbatim\r
+ ==============================================================================\r
+ ##### Extended Peripheral State functions #####\r
+ ==============================================================================\r
+ [..]\r
+ This subsection permits to get in run-time the status of the peripheral\r
+ and the data flow.\r
+\r
+@endverbatim\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Return the TIM Hall Sensor interface handle state.\r
+ * @param htim TIM Hall Sensor handle\r
+ * @retval HAL state\r
+ */\r
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r
+{\r
+ return htim->State;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief TIM DMA Commutation callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->CommutationCallback(htim);\r
+#else\r
+ HAL_TIMEx_CommutCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+/**\r
+ * @brief TIM DMA Commutation half complete callback.\r
+ * @param hdma pointer to DMA handle.\r
+ * @retval None\r
+ */\r
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)\r
+{\r
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r
+\r
+ /* Change the htim state */\r
+ htim->State = HAL_TIM_STATE_READY;\r
+\r
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r
+ htim->CommutationHalfCpltCallback(htim);\r
+#else\r
+ HAL_TIMEx_CommutHalfCpltCallback(htim);\r
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel xN.\r
+ * @param TIMx to select the TIM peripheral\r
+ * @param Channel specifies the TIM Channel\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CHANNEL_1: TIM Channel 1\r
+ * @arg TIM_CHANNEL_2: TIM Channel 2\r
+ * @arg TIM_CHANNEL_3: TIM Channel 3\r
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.\r
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.\r
+ * @retval None\r
+ */\r
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)\r
+{\r
+ uint32_t tmp;\r
+\r
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\r
+\r
+ /* Reset the CCxNE Bit */\r
+ TIMx->CCER &= ~tmp;\r
+\r
+ /* Set or reset the CCxNE Bit */\r
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file : main.h\r
+ * @brief : Header for main.c file.\r
+ * This file contains the common defines of the application.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MAIN_H\r
+#define __MAIN_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f7xx_hal.h"\r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* USER CODE BEGIN ET */\r
+\r
+/* USER CODE END ET */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* USER CODE BEGIN EC */\r
+\r
+/* USER CODE END EC */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* USER CODE BEGIN EM */\r
+\r
+/* USER CODE END EM */\r
+\r
+/* Exported functions prototypes ---------------------------------------------*/\r
+void Error_Handler(void);\r
+\r
+/* USER CODE BEGIN EFP */\r
+\r
+/* USER CODE END EFP */\r
+\r
+/* Private defines -----------------------------------------------------------*/\r
+/* USER CODE BEGIN Private defines */\r
+\r
+/* USER CODE END Private defines */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MAIN_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_hal_conf_template.h\r
+ * @author MCD Application Team\r
+ * @brief HAL configuration template file. \r
+ * This file should be copied to the application folder and renamed\r
+ * to stm32f7xx_hal_conf.h.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2017 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_HAL_CONF_H\r
+#define __STM32F7xx_HAL_CONF_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* ########################## Module Selection ############################## */\r
+/**\r
+ * @brief This is the list of modules to be used in the HAL driver \r
+ */\r
+#define HAL_MODULE_ENABLED \r
+\r
+ /* #define HAL_ADC_MODULE_ENABLED */\r
+/* #define HAL_CRYP_MODULE_ENABLED */\r
+/* #define HAL_CAN_MODULE_ENABLED */\r
+/* #define HAL_CEC_MODULE_ENABLED */\r
+/* #define HAL_CRC_MODULE_ENABLED */\r
+/* #define HAL_CRYP_MODULE_ENABLED */\r
+/* #define HAL_DAC_MODULE_ENABLED */\r
+/* #define HAL_DCMI_MODULE_ENABLED */\r
+/* #define HAL_DMA2D_MODULE_ENABLED */\r
+/* #define HAL_ETH_MODULE_ENABLED */\r
+/* #define HAL_NAND_MODULE_ENABLED */\r
+/* #define HAL_NOR_MODULE_ENABLED */\r
+/* #define HAL_SRAM_MODULE_ENABLED */\r
+/* #define HAL_SDRAM_MODULE_ENABLED */\r
+/* #define HAL_HASH_MODULE_ENABLED */\r
+/* #define HAL_I2S_MODULE_ENABLED */\r
+/* #define HAL_IWDG_MODULE_ENABLED */\r
+/* #define HAL_LPTIM_MODULE_ENABLED */\r
+/* #define HAL_LTDC_MODULE_ENABLED */\r
+/* #define HAL_QSPI_MODULE_ENABLED */\r
+/* #define HAL_RNG_MODULE_ENABLED */\r
+/* #define HAL_RTC_MODULE_ENABLED */\r
+/* #define HAL_SAI_MODULE_ENABLED */\r
+/* #define HAL_SD_MODULE_ENABLED */\r
+/* #define HAL_MMC_MODULE_ENABLED */\r
+/* #define HAL_SPDIFRX_MODULE_ENABLED */\r
+/* #define HAL_SPI_MODULE_ENABLED */\r
+#define HAL_TIM_MODULE_ENABLED\r
+/* #define HAL_UART_MODULE_ENABLED */\r
+/* #define HAL_USART_MODULE_ENABLED */\r
+/* #define HAL_IRDA_MODULE_ENABLED */\r
+/* #define HAL_SMARTCARD_MODULE_ENABLED */\r
+/* #define HAL_WWDG_MODULE_ENABLED */\r
+/* #define HAL_PCD_MODULE_ENABLED */\r
+/* #define HAL_HCD_MODULE_ENABLED */\r
+/* #define HAL_DFSDM_MODULE_ENABLED */\r
+/* #define HAL_DSI_MODULE_ENABLED */\r
+/* #define HAL_JPEG_MODULE_ENABLED */\r
+/* #define HAL_MDIOS_MODULE_ENABLED */\r
+/* #define HAL_SMBUS_MODULE_ENABLED */\r
+/* #define HAL_EXTI_MODULE_ENABLED */\r
+#define HAL_GPIO_MODULE_ENABLED\r
+#define HAL_EXTI_MODULE_ENABLED \r
+#define HAL_DMA_MODULE_ENABLED\r
+#define HAL_RCC_MODULE_ENABLED\r
+#define HAL_FLASH_MODULE_ENABLED\r
+#define HAL_PWR_MODULE_ENABLED\r
+#define HAL_I2C_MODULE_ENABLED\r
+#define HAL_CORTEX_MODULE_ENABLED\r
+\r
+/* ########################## HSE/HSI Values adaptation ##################### */\r
+/**\r
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSE is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSE_STARTUP_TIMEOUT)\r
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */\r
+#endif /* HSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+ * @brief Internal High Speed oscillator (HSI) value.\r
+ * This value is used by the RCC HAL module to compute the system frequency\r
+ * (when HSI is used as system clock source, directly or through the PLL). \r
+ */\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @brief Internal Low Speed oscillator (LSI) value.\r
+ */\r
+#if !defined (LSI_VALUE) \r
+ #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/\r
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz\r
+ The real value may vary depending on the variations\r
+ in voltage and temperature. */\r
+/**\r
+ * @brief External Low Speed oscillator (LSE) value.\r
+ */\r
+#if !defined (LSE_VALUE)\r
+ #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */\r
+#endif /* LSE_VALUE */\r
+\r
+#if !defined (LSE_STARTUP_TIMEOUT)\r
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */\r
+#endif /* LSE_STARTUP_TIMEOUT */\r
+\r
+/**\r
+ * @brief External clock source for I2S peripheral\r
+ * This value is used by the I2S HAL module to compute the I2S clock source \r
+ * frequency, this source is inserted directly through I2S_CKIN pad. \r
+ */\r
+#if !defined (EXTERNAL_CLOCK_VALUE)\r
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* EXTERNAL_CLOCK_VALUE */\r
+\r
+/* Tip: To avoid modifying this file each time you need to use different HSE,\r
+ === you can define the HSE value in your toolchain compiler preprocessor. */\r
+\r
+/* ########################### System Configuration ######################### */\r
+/**\r
+ * @brief This is the HAL system configuration section\r
+ */ \r
+#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */\r
+#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */\r
+#define USE_RTOS 0U\r
+#define PREFETCH_ENABLE 0U\r
+#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */\r
+\r
+/* ########################## Assert Selection ############################## */\r
+/**\r
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
+ * HAL drivers code\r
+ */\r
+/* #define USE_FULL_ASSERT 1U */\r
+\r
+/* ################## Ethernet peripheral configuration ##################### */\r
+\r
+/* Section 1 : Ethernet peripheral configuration */\r
+\r
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\r
+#define MAC_ADDR0 2U\r
+#define MAC_ADDR1 0U\r
+#define MAC_ADDR2 0U\r
+#define MAC_ADDR3 0U\r
+#define MAC_ADDR4 0U\r
+#define MAC_ADDR5 0U\r
+\r
+/* Definition of the Ethernet driver buffers size and count */ \r
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */\r
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */\r
+#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */\r
+#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */\r
+\r
+/* Section 2: PHY configuration section */\r
+\r
+/* DP83848_PHY_ADDRESS Address*/ \r
+#define DP83848_PHY_ADDRESS 0x01U\r
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \r
+#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)\r
+/* PHY Configuration delay */\r
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)\r
+\r
+#define PHY_READ_TO ((uint32_t)0x0000FFFFU)\r
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)\r
+\r
+/* Section 3: Common PHY Registers */\r
+\r
+#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */\r
+#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */\r
+ \r
+#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */\r
+#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */\r
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */\r
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */\r
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */\r
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */\r
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */\r
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */\r
+#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */\r
+#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */\r
+\r
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */\r
+#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */\r
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */\r
+ \r
+/* Section 4: Extended PHY Registers */\r
+#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */\r
+\r
+#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */\r
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */\r
+\r
+/* ################## SPI peripheral configuration ########################## */\r
+\r
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\r
+* Activated: CRC code is present inside driver\r
+* Deactivated: CRC code cleaned from driver\r
+*/\r
+\r
+#define USE_SPI_CRC 0U\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/**\r
+ * @brief Include module's header file \r
+ */\r
+\r
+#ifdef HAL_RCC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rcc.h"\r
+#endif /* HAL_RCC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_EXTI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_exti.h"\r
+#endif /* HAL_EXTI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_GPIO_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_gpio.h"\r
+#endif /* HAL_GPIO_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dma.h"\r
+#endif /* HAL_DMA_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_CORTEX_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cortex.h"\r
+#endif /* HAL_CORTEX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ADC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_adc.h"\r
+#endif /* HAL_ADC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CAN_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_can.h"\r
+#endif /* HAL_CAN_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CEC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cec.h"\r
+#endif /* HAL_CEC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_crc.h"\r
+#endif /* HAL_CRC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_CRYP_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_cryp.h" \r
+#endif /* HAL_CRYP_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DMA2D_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dma2d.h"\r
+#endif /* HAL_DMA2D_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DAC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dac.h"\r
+#endif /* HAL_DAC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DCMI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dcmi.h"\r
+#endif /* HAL_DCMI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_ETH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_eth.h"\r
+#endif /* HAL_ETH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_FLASH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_flash.h"\r
+#endif /* HAL_FLASH_MODULE_ENABLED */\r
+ \r
+#ifdef HAL_SRAM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sram.h"\r
+#endif /* HAL_SRAM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NOR_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_nor.h"\r
+#endif /* HAL_NOR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_NAND_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_nand.h"\r
+#endif /* HAL_NAND_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SDRAM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sdram.h"\r
+#endif /* HAL_SDRAM_MODULE_ENABLED */ \r
+\r
+#ifdef HAL_HASH_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_hash.h"\r
+#endif /* HAL_HASH_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2C_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_i2c.h"\r
+#endif /* HAL_I2C_MODULE_ENABLED */\r
+\r
+#ifdef HAL_I2S_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_i2s.h"\r
+#endif /* HAL_I2S_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IWDG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_iwdg.h"\r
+#endif /* HAL_IWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LPTIM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_lptim.h"\r
+#endif /* HAL_LPTIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_LTDC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_ltdc.h"\r
+#endif /* HAL_LTDC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PWR_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_pwr.h"\r
+#endif /* HAL_PWR_MODULE_ENABLED */\r
+\r
+#ifdef HAL_QSPI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_qspi.h"\r
+#endif /* HAL_QSPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RNG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rng.h"\r
+#endif /* HAL_RNG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_RTC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_rtc.h"\r
+#endif /* HAL_RTC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SAI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sai.h"\r
+#endif /* HAL_SAI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_sd.h"\r
+#endif /* HAL_SD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_MMC_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_mmc.h"\r
+#endif /* HAL_MMC_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPDIFRX_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_spdifrx.h"\r
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SPI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_spi.h"\r
+#endif /* HAL_SPI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_TIM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_tim.h"\r
+#endif /* HAL_TIM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_UART_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_uart.h"\r
+#endif /* HAL_UART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_USART_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_usart.h"\r
+#endif /* HAL_USART_MODULE_ENABLED */\r
+\r
+#ifdef HAL_IRDA_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_irda.h"\r
+#endif /* HAL_IRDA_MODULE_ENABLED */\r
+\r
+#ifdef HAL_SMARTCARD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_smartcard.h"\r
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_WWDG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_wwdg.h"\r
+#endif /* HAL_WWDG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_PCD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_pcd.h"\r
+#endif /* HAL_PCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_HCD_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_hcd.h"\r
+#endif /* HAL_HCD_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DFSDM_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dfsdm.h"\r
+#endif /* HAL_DFSDM_MODULE_ENABLED */\r
+\r
+#ifdef HAL_DSI_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_dsi.h"\r
+#endif /* HAL_DSI_MODULE_ENABLED */\r
+\r
+#ifdef HAL_JPEG_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_jpeg.h"\r
+#endif /* HAL_JPEG_MODULE_ENABLED */\r
+\r
+#ifdef HAL_MDIOS_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_mdios.h"\r
+#endif /* HAL_MDIOS_MODULE_ENABLED */ \r
+\r
+#ifdef HAL_SMBUS_MODULE_ENABLED\r
+ #include "stm32f7xx_hal_smbus.h"\r
+#endif /* HAL_SMBUS_MODULE_ENABLED */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief The assert_param macro is used for function's parameters check.\r
+ * @param expr: If expr is false, it calls assert_failed function\r
+ * which reports the name of the source file and the source\r
+ * line number of the call that failed. \r
+ * If expr is true, it returns no value.\r
+ * @retval None\r
+ */\r
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+ void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+ #define assert_param(expr) ((void)0U)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_HAL_CONF_H */\r
+ \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_it.h\r
+ * @brief This file contains the headers of the interrupt handlers.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F7xx_IT_H\r
+#define __STM32F7xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* USER CODE BEGIN ET */\r
+\r
+/* USER CODE END ET */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* USER CODE BEGIN EC */\r
+\r
+/* USER CODE END EC */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* USER CODE BEGIN EM */\r
+\r
+/* USER CODE END EM */\r
+\r
+/* Exported functions prototypes ---------------------------------------------*/\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+/* USER CODE BEGIN EFP */\r
+\r
+/* USER CODE END EFP */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F7xx_IT_H */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : Linker script for STM32F767ZITx Device from STM32F7 series
+** 2048Kbytes FLASH
+** 512Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20080000; /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
--- /dev/null
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld (debug in RAM dedicated)
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : Linker script for STM32F767ZITx Device from STM32F7 series
+** 2048Kbytes FLASH
+** 512Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20080000; /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "RAM" Ram type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >RAM
+
+ /* The program code and other data into "RAM" Ram type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >RAM
+
+ /* Constant data into "RAM" Ram type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >RAM
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >RAM
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >RAM
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >RAM
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >RAM
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >RAM
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file : main.c\r
+ * @brief : Main program body\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN PTD */\r
+\r
+/* USER CODE END PTD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN PD */\r
+\r
+/* USER CODE END PD */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN PM */\r
+\r
+/* USER CODE END PM */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+\r
+TIM_HandleTypeDef htim2;\r
+TIM_HandleTypeDef htim5;\r
+\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+void SystemClock_Config(void);\r
+static void MX_GPIO_Init(void);\r
+static void MX_TIM2_Init(void);\r
+static void MX_TIM5_Init(void);\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* Private user code ---------------------------------------------------------*/\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+\r
+/**\r
+ * @brief The application entry point.\r
+ * @retval int\r
+ */\r
+int main(void)\r
+{\r
+ /* USER CODE BEGIN 1 */\r
+ /* USER CODE END 1 */\r
+ \r
+\r
+ /* MCU Configuration--------------------------------------------------------*/\r
+\r
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\r
+ HAL_Init();\r
+\r
+ /* USER CODE BEGIN Init */\r
+\r
+ /* USER CODE END Init */\r
+\r
+ /* Configure the system clock */\r
+ SystemClock_Config();\r
+\r
+ /* USER CODE BEGIN SysInit */\r
+\r
+ /* USER CODE END SysInit */\r
+\r
+ /* Initialize all configured peripherals */\r
+ MX_GPIO_Init();\r
+ MX_TIM2_Init();\r
+ MX_TIM5_Init();\r
+ /* USER CODE BEGIN 2 */\r
+ HAL_TIM_Encoder_Start(&htim2, TIM_CHANNEL_ALL);\r
+ HAL_TIM_Encoder_Start(&htim5, TIM_CHANNEL_ALL);\r
+ /* USER CODE END 2 */\r
+\r
+ /* Infinite loop */\r
+ /* USER CODE BEGIN WHILE */\r
+ uint32_t i = 0;\r
+ while (1) {\r
+ /* USER CODE END WHILE */\r
+\r
+ /* USER CODE BEGIN 3 */\r
+ /*\r
+ * un giro completo usando risoluzione 4x (encoder mode TI1 and TI2) è 148000\r
+ * un giro completo usando risoluzine 2x è 74000\r
+ */\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+ i = TIM2->CNT;\r
+\r
+ TIM2->CNT=0;\r
+ }\r
+ /* USER CODE END 3 */\r
+}\r
+\r
+/**\r
+ * @brief System Clock Configuration\r
+ * @retval None\r
+ */\r
+void SystemClock_Config(void)\r
+{\r
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};\r
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};\r
+\r
+ /** Configure the main internal regulator output voltage \r
+ */\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);\r
+ /** Initializes the CPU, AHB and APB busses clocks \r
+ */\r
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;\r
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;\r
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;\r
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;\r
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+ /** Initializes the CPU, AHB and APB busses clocks \r
+ */\r
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\r
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;\r
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;\r
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;\r
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;\r
+\r
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief TIM2 Initialization Function\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void MX_TIM2_Init(void)\r
+{\r
+\r
+ /* USER CODE BEGIN TIM2_Init 0 */\r
+\r
+ /* USER CODE END TIM2_Init 0 */\r
+\r
+ TIM_Encoder_InitTypeDef sConfig = {0};\r
+ TIM_MasterConfigTypeDef sMasterConfig = {0};\r
+\r
+ /* USER CODE BEGIN TIM2_Init 1 */\r
+\r
+ /* USER CODE END TIM2_Init 1 */\r
+ htim2.Instance = TIM2;\r
+ htim2.Init.Prescaler = 0;\r
+ htim2.Init.CounterMode = TIM_COUNTERMODE_UP;\r
+ htim2.Init.Period = 148000;\r
+ htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\r
+ htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\r
+ sConfig.EncoderMode = TIM_ENCODERMODE_TI12;\r
+ sConfig.IC1Polarity = TIM_ICPOLARITY_FALLING;\r
+ sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;\r
+ sConfig.IC1Prescaler = TIM_ICPSC_DIV1;\r
+ sConfig.IC1Filter = 0;\r
+ sConfig.IC2Polarity = TIM_ICPOLARITY_FALLING;\r
+ sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;\r
+ sConfig.IC2Prescaler = TIM_ICPSC_DIV1;\r
+ sConfig.IC2Filter = 0;\r
+ if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\r
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\r
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+ /* USER CODE BEGIN TIM2_Init 2 */\r
+\r
+ /* USER CODE END TIM2_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+ * @brief TIM5 Initialization Function\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void MX_TIM5_Init(void)\r
+{\r
+\r
+ /* USER CODE BEGIN TIM5_Init 0 */\r
+\r
+ /* USER CODE END TIM5_Init 0 */\r
+\r
+ TIM_Encoder_InitTypeDef sConfig = {0};\r
+ TIM_MasterConfigTypeDef sMasterConfig = {0};\r
+\r
+ /* USER CODE BEGIN TIM5_Init 1 */\r
+\r
+ /* USER CODE END TIM5_Init 1 */\r
+ htim5.Instance = TIM5;\r
+ htim5.Init.Prescaler = 0;\r
+ htim5.Init.CounterMode = TIM_COUNTERMODE_UP;\r
+ htim5.Init.Period = 4294967295;\r
+ htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\r
+ htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\r
+ sConfig.EncoderMode = TIM_ENCODERMODE_TI1;\r
+ sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;\r
+ sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;\r
+ sConfig.IC1Prescaler = TIM_ICPSC_DIV1;\r
+ sConfig.IC1Filter = 0;\r
+ sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;\r
+ sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;\r
+ sConfig.IC2Prescaler = TIM_ICPSC_DIV1;\r
+ sConfig.IC2Filter = 0;\r
+ if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\r
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\r
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)\r
+ {\r
+ Error_Handler();\r
+ }\r
+ /* USER CODE BEGIN TIM5_Init 2 */\r
+\r
+ /* USER CODE END TIM5_Init 2 */\r
+\r
+}\r
+\r
+/**\r
+ * @brief GPIO Initialization Function\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void MX_GPIO_Init(void)\r
+{\r
+\r
+ /* GPIO Ports Clock Enable */\r
+ __HAL_RCC_GPIOA_CLK_ENABLE();\r
+ __HAL_RCC_GPIOB_CLK_ENABLE();\r
+\r
+}\r
+\r
+/* USER CODE BEGIN 4 */\r
+\r
+/* USER CODE END 4 */\r
+\r
+/**\r
+ * @brief This function is executed in case of error occurrence.\r
+ * @retval None\r
+ */\r
+void Error_Handler(void)\r
+{\r
+ /* USER CODE BEGIN Error_Handler_Debug */\r
+ /* User can add his own implementation to report the HAL error return state */\r
+\r
+ /* USER CODE END Error_Handler_Debug */\r
+}\r
+\r
+#ifdef USE_FULL_ASSERT\r
+/**\r
+ * @brief Reports the name of the source file and the source line number\r
+ * where the assert_param error has occurred.\r
+ * @param file: pointer to the source file name\r
+ * @param line: assert_param error line source number\r
+ * @retval None\r
+ */\r
+void assert_failed(uint8_t *file, uint32_t line)\r
+{ \r
+ /* USER CODE BEGIN 6 */\r
+ /* User can add his own implementation to report the file name and line number,\r
+ tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
+ /* USER CODE END 6 */\r
+}\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * File Name : stm32f7xx_hal_msp.c\r
+ * Description : This file provides code for the MSP Initialization \r
+ * and de-Initialization codes.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+/* USER CODE BEGIN Includes */\r
+\r
+/* USER CODE END Includes */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN TD */\r
+\r
+/* USER CODE END TD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN Define */\r
+ \r
+/* USER CODE END Define */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN Macro */\r
+\r
+/* USER CODE END Macro */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* External functions --------------------------------------------------------*/\r
+/* USER CODE BEGIN ExternalFunctions */\r
+\r
+/* USER CODE END ExternalFunctions */\r
+\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+/**\r
+ * Initializes the Global MSP.\r
+ */\r
+void HAL_MspInit(void)\r
+{\r
+ /* USER CODE BEGIN MspInit 0 */\r
+\r
+ /* USER CODE END MspInit 0 */\r
+\r
+ __HAL_RCC_PWR_CLK_ENABLE();\r
+ __HAL_RCC_SYSCFG_CLK_ENABLE();\r
+\r
+ /* System interrupt init*/\r
+\r
+ /* USER CODE BEGIN MspInit 1 */\r
+\r
+ /* USER CODE END MspInit 1 */\r
+}\r
+\r
+/**\r
+* @brief TIM_Encoder MSP Initialization\r
+* This function configures the hardware resources used in this example\r
+* @param htim_encoder: TIM_Encoder handle pointer\r
+* @retval None\r
+*/\r
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStruct = {0};\r
+ if(htim_encoder->Instance==TIM2)\r
+ {\r
+ /* USER CODE BEGIN TIM2_MspInit 0 */\r
+\r
+ /* USER CODE END TIM2_MspInit 0 */\r
+ /* Peripheral clock enable */\r
+ __HAL_RCC_TIM2_CLK_ENABLE();\r
+ \r
+ __HAL_RCC_GPIOA_CLK_ENABLE();\r
+ __HAL_RCC_GPIOB_CLK_ENABLE();\r
+ /**TIM2 GPIO Configuration \r
+ PA5 ------> TIM2_CH1\r
+ PB3 ------> TIM2_CH2 \r
+ */\r
+ GPIO_InitStruct.Pin = GPIO_PIN_5;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+ GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;\r
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
+\r
+ GPIO_InitStruct.Pin = GPIO_PIN_3;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Pull = GPIO_PULLUP;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+ GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;\r
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r
+\r
+ /* USER CODE BEGIN TIM2_MspInit 1 */\r
+\r
+ /* USER CODE END TIM2_MspInit 1 */\r
+ }\r
+ else if(htim_encoder->Instance==TIM5)\r
+ {\r
+ /* USER CODE BEGIN TIM5_MspInit 0 */\r
+\r
+ /* USER CODE END TIM5_MspInit 0 */\r
+ /* Peripheral clock enable */\r
+ __HAL_RCC_TIM5_CLK_ENABLE();\r
+ \r
+ __HAL_RCC_GPIOA_CLK_ENABLE();\r
+ /**TIM5 GPIO Configuration \r
+ PA0/WKUP ------> TIM5_CH1\r
+ PA1 ------> TIM5_CH2 \r
+ */\r
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;\r
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r
+ GPIO_InitStruct.Pull = GPIO_NOPULL;\r
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r
+ GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;\r
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r
+\r
+ /* USER CODE BEGIN TIM5_MspInit 1 */\r
+\r
+ /* USER CODE END TIM5_MspInit 1 */\r
+ }\r
+\r
+}\r
+\r
+/**\r
+* @brief TIM_Encoder MSP De-Initialization\r
+* This function freeze the hardware resources used in this example\r
+* @param htim_encoder: TIM_Encoder handle pointer\r
+* @retval None\r
+*/\r
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder)\r
+{\r
+ if(htim_encoder->Instance==TIM2)\r
+ {\r
+ /* USER CODE BEGIN TIM2_MspDeInit 0 */\r
+\r
+ /* USER CODE END TIM2_MspDeInit 0 */\r
+ /* Peripheral clock disable */\r
+ __HAL_RCC_TIM2_CLK_DISABLE();\r
+ \r
+ /**TIM2 GPIO Configuration \r
+ PA5 ------> TIM2_CH1\r
+ PB3 ------> TIM2_CH2 \r
+ */\r
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);\r
+\r
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3);\r
+\r
+ /* USER CODE BEGIN TIM2_MspDeInit 1 */\r
+\r
+ /* USER CODE END TIM2_MspDeInit 1 */\r
+ }\r
+ else if(htim_encoder->Instance==TIM5)\r
+ {\r
+ /* USER CODE BEGIN TIM5_MspDeInit 0 */\r
+\r
+ /* USER CODE END TIM5_MspDeInit 0 */\r
+ /* Peripheral clock disable */\r
+ __HAL_RCC_TIM5_CLK_DISABLE();\r
+ \r
+ /**TIM5 GPIO Configuration \r
+ PA0/WKUP ------> TIM5_CH1\r
+ PA1 ------> TIM5_CH2 \r
+ */\r
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);\r
+\r
+ /* USER CODE BEGIN TIM5_MspDeInit 1 */\r
+\r
+ /* USER CODE END TIM5_MspDeInit 1 */\r
+ }\r
+\r
+}\r
+\r
+/* USER CODE BEGIN 1 */\r
+\r
+/* USER CODE END 1 */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* USER CODE BEGIN Header */\r
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx_it.c\r
+ * @brief Interrupt Service Routines.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.\r
+ * All rights reserved.</center></h2>\r
+ *\r
+ * This software component is licensed by ST under BSD 3-Clause license,\r
+ * the "License"; You may not use this file except in compliance with the\r
+ * License. You may obtain a copy of the License at:\r
+ * opensource.org/licenses/BSD-3-Clause\r
+ *\r
+ ******************************************************************************\r
+ */\r
+/* USER CODE END Header */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "main.h"\r
+#include "stm32f7xx_it.h"\r
+/* Private includes ----------------------------------------------------------*/\r
+/* USER CODE BEGIN Includes */\r
+/* USER CODE END Includes */\r
+ \r
+/* Private typedef -----------------------------------------------------------*/\r
+/* USER CODE BEGIN TD */\r
+\r
+/* USER CODE END TD */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* USER CODE BEGIN PD */\r
+ \r
+/* USER CODE END PD */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* USER CODE BEGIN PM */\r
+\r
+/* USER CODE END PM */\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+/* USER CODE BEGIN PV */\r
+\r
+/* USER CODE END PV */\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* USER CODE BEGIN PFP */\r
+\r
+/* USER CODE END PFP */\r
+\r
+/* Private user code ---------------------------------------------------------*/\r
+/* USER CODE BEGIN 0 */\r
+\r
+/* USER CODE END 0 */\r
+\r
+/* External variables --------------------------------------------------------*/\r
+\r
+/* USER CODE BEGIN EV */\r
+\r
+/* USER CODE END EV */\r
+\r
+/******************************************************************************/\r
+/* Cortex-M7 Processor Interruption and Exception Handlers */ \r
+/******************************************************************************/\r
+/**\r
+ * @brief This function handles Non maskable interrupt.\r
+ */\r
+void NMI_Handler(void)\r
+{\r
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */\r
+\r
+ /* USER CODE END NonMaskableInt_IRQn 0 */\r
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */\r
+\r
+ /* USER CODE END NonMaskableInt_IRQn 1 */\r
+}\r
+\r
+/**\r
+ * @brief This function handles Hard fault interrupt.\r
+ */\r
+void HardFault_Handler(void)\r
+{\r
+ /* USER CODE BEGIN HardFault_IRQn 0 */\r
+\r
+ /* USER CODE END HardFault_IRQn 0 */\r
+ while (1)\r
+ {\r
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */\r
+ /* USER CODE END W1_HardFault_IRQn 0 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Memory management fault.\r
+ */\r
+void MemManage_Handler(void)\r
+{\r
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */\r
+\r
+ /* USER CODE END MemoryManagement_IRQn 0 */\r
+ while (1)\r
+ {\r
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */\r
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Pre-fetch fault, memory access fault.\r
+ */\r
+void BusFault_Handler(void)\r
+{\r
+ /* USER CODE BEGIN BusFault_IRQn 0 */\r
+\r
+ /* USER CODE END BusFault_IRQn 0 */\r
+ while (1)\r
+ {\r
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */\r
+ /* USER CODE END W1_BusFault_IRQn 0 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles Undefined instruction or illegal state.\r
+ */\r
+void UsageFault_Handler(void)\r
+{\r
+ /* USER CODE BEGIN UsageFault_IRQn 0 */\r
+\r
+ /* USER CODE END UsageFault_IRQn 0 */\r
+ while (1)\r
+ {\r
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */\r
+ /* USER CODE END W1_UsageFault_IRQn 0 */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief This function handles System service call via SWI instruction.\r
+ */\r
+void SVC_Handler(void)\r
+{\r
+ /* USER CODE BEGIN SVCall_IRQn 0 */\r
+\r
+ /* USER CODE END SVCall_IRQn 0 */\r
+ /* USER CODE BEGIN SVCall_IRQn 1 */\r
+\r
+ /* USER CODE END SVCall_IRQn 1 */\r
+}\r
+\r
+/**\r
+ * @brief This function handles Debug monitor.\r
+ */\r
+void DebugMon_Handler(void)\r
+{\r
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */\r
+\r
+ /* USER CODE END DebugMonitor_IRQn 0 */\r
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */\r
+\r
+ /* USER CODE END DebugMonitor_IRQn 1 */\r
+}\r
+\r
+/**\r
+ * @brief This function handles Pendable request for system service.\r
+ */\r
+void PendSV_Handler(void)\r
+{\r
+ /* USER CODE BEGIN PendSV_IRQn 0 */\r
+\r
+ /* USER CODE END PendSV_IRQn 0 */\r
+ /* USER CODE BEGIN PendSV_IRQn 1 */\r
+\r
+ /* USER CODE END PendSV_IRQn 1 */\r
+}\r
+\r
+/**\r
+ * @brief This function handles System tick timer.\r
+ */\r
+void SysTick_Handler(void)\r
+{\r
+ /* USER CODE BEGIN SysTick_IRQn 0 */\r
+\r
+ /* USER CODE END SysTick_IRQn 0 */\r
+ HAL_IncTick();\r
+ /* USER CODE BEGIN SysTick_IRQn 1 */\r
+\r
+ /* USER CODE END SysTick_IRQn 1 */\r
+}\r
+\r
+/******************************************************************************/\r
+/* STM32F7xx Peripheral Interrupt Handlers */\r
+/* Add here the Interrupt Handlers for the used peripherals. */\r
+/* For the available peripheral interrupt handler names, */\r
+/* please refer to the startup file (startup_stm32f7xx.s). */\r
+/******************************************************************************/\r
+\r
+/* USER CODE BEGIN 1 */\r
+\r
+/* USER CODE END 1 */\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**
+*****************************************************************************
+**
+** File : syscalls.c
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : STM32CubeIDE Minimal System calls file
+**
+** For more information about which c-functions
+** need which of these lowlevel functions
+** please consult the Newlib libc-manual
+**
+** Environment : STM32CubeIDE MCU
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+*****************************************************************************
+**
+** <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit (int status)
+{
+ _kill(status, -1);
+ while (1) {} /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ *ptr++ = __io_getchar();
+ }
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ __io_putchar(*ptr++);
+ }
+ return len;
+}
+
+int _close(int file)
+{
+ return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _isatty(int file)
+{
+ return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+ return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+ /* Pretend like we always fail */
+ return -1;
+}
+
+int _wait(int *status)
+{
+ errno = ECHILD;
+ return -1;
+}
+
+int _unlink(char *name)
+{
+ errno = ENOENT;
+ return -1;
+}
+
+int _times(struct tms *buf)
+{
+ return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _link(char *old, char *new)
+{
+ errno = EMLINK;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+ errno = ENOMEM;
+ return -1;
+}
--- /dev/null
+/**
+*****************************************************************************
+**
+** File : sysmem.c
+**
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : STM32CubeIDE Minimal System Memory calls file
+**
+** For more information about which c-functions
+** need which of these lowlevel functions
+** please consult the Newlib libc-manual
+**
+** Environment : STM32CubeIDE MCU
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+*****************************************************************************
+**
+** <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <errno.h>
+#include <stdio.h>
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+ extern char end asm("end");
+ static char *heap_end;
+ char *prev_heap_end;
+
+ if (heap_end == 0)
+ heap_end = &end;
+
+ prev_heap_end = heap_end;
+ if (heap_end + incr > stack_ptr)
+ {
+ errno = ENOMEM;
+ return (caddr_t) -1;
+ }
+
+ heap_end += incr;
+
+ return (caddr_t) prev_heap_end;
+}
+
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f7xx.c\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r
+ *\r
+ * This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f7xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F7xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f7xx.h"\r
+\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\r
+#endif /* HSE_VALUE */\r
+\r
+#if !defined (HSI_VALUE)\r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/************************* Miscellaneous Configuration ************************/\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+ /* This variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+ uint32_t SystemCoreClock = 16000000;\r
+ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* FPU settings ------------------------------------------------------------*/\r
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */\r
+ #endif\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f767xx.s\r
+ * @author MCD Application Team\r
+ * @brief STM32F767xx Devices vector table for GCC based toolchain. \r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M7 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors\r
+ * may be used to endorse or promote products derived from this software\r
+ * without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+ \r
+ .syntax unified\r
+ .cpu cortex-m7\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section. \r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */ \r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+ ldr sp, =_estack /* set stack pointer */\r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+\r
+/* Call the clock system initialization function.*/\r
+ bl SystemInit \r
+/* Call static constructors */\r
+ bl __libc_init_array\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ * @param None \r
+ * @retval None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M7. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+* \r
+*******************************************************************************/\r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+ \r
+ \r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ \r
+ /* External Interrupts */\r
+ .word WWDG_IRQHandler /* Window WatchDog */\r
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */\r
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */\r
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */\r
+ .word FLASH_IRQHandler /* FLASH */\r
+ .word RCC_IRQHandler /* RCC */\r
+ .word EXTI0_IRQHandler /* EXTI Line0 */\r
+ .word EXTI1_IRQHandler /* EXTI Line1 */\r
+ .word EXTI2_IRQHandler /* EXTI Line2 */\r
+ .word EXTI3_IRQHandler /* EXTI Line3 */\r
+ .word EXTI4_IRQHandler /* EXTI Line4 */\r
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */\r
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */\r
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */\r
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */\r
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */\r
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */\r
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */\r
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */\r
+ .word CAN1_TX_IRQHandler /* CAN1 TX */\r
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */\r
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */\r
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */\r
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */\r
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */\r
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */\r
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */\r
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */\r
+ .word TIM2_IRQHandler /* TIM2 */\r
+ .word TIM3_IRQHandler /* TIM3 */\r
+ .word TIM4_IRQHandler /* TIM4 */\r
+ .word I2C1_EV_IRQHandler /* I2C1 Event */\r
+ .word I2C1_ER_IRQHandler /* I2C1 Error */\r
+ .word I2C2_EV_IRQHandler /* I2C2 Event */\r
+ .word I2C2_ER_IRQHandler /* I2C2 Error */\r
+ .word SPI1_IRQHandler /* SPI1 */\r
+ .word SPI2_IRQHandler /* SPI2 */\r
+ .word USART1_IRQHandler /* USART1 */\r
+ .word USART2_IRQHandler /* USART2 */\r
+ .word USART3_IRQHandler /* USART3 */\r
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */\r
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */\r
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */\r
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */\r
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */\r
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */\r
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */\r
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */\r
+ .word FMC_IRQHandler /* FMC */\r
+ .word SDMMC1_IRQHandler /* SDMMC1 */\r
+ .word TIM5_IRQHandler /* TIM5 */\r
+ .word SPI3_IRQHandler /* SPI3 */\r
+ .word UART4_IRQHandler /* UART4 */\r
+ .word UART5_IRQHandler /* UART5 */\r
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */\r
+ .word TIM7_IRQHandler /* TIM7 */\r
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */\r
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */\r
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */\r
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */\r
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */\r
+ .word ETH_IRQHandler /* Ethernet */\r
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */\r
+ .word CAN2_TX_IRQHandler /* CAN2 TX */\r
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */\r
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */\r
+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */\r
+ .word OTG_FS_IRQHandler /* USB OTG FS */\r
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */\r
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */\r
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */\r
+ .word USART6_IRQHandler /* USART6 */\r
+ .word I2C3_EV_IRQHandler /* I2C3 event */\r
+ .word I2C3_ER_IRQHandler /* I2C3 error */\r
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */\r
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */\r
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */\r
+ .word OTG_HS_IRQHandler /* USB OTG HS */\r
+ .word DCMI_IRQHandler /* DCMI */\r
+ .word 0 /* Reserved */\r
+ .word RNG_IRQHandler /* RNG */\r
+ .word FPU_IRQHandler /* FPU */\r
+ .word UART7_IRQHandler /* UART7 */\r
+ .word UART8_IRQHandler /* UART8 */\r
+ .word SPI4_IRQHandler /* SPI4 */\r
+ .word SPI5_IRQHandler /* SPI5 */\r
+ .word SPI6_IRQHandler /* SPI6 */\r
+ .word SAI1_IRQHandler /* SAI1 */\r
+ .word LTDC_IRQHandler /* LTDC */\r
+ .word LTDC_ER_IRQHandler /* LTDC error */\r
+ .word DMA2D_IRQHandler /* DMA2D */\r
+ .word SAI2_IRQHandler /* SAI2 */\r
+ .word QUADSPI_IRQHandler /* QUADSPI */\r
+ .word LPTIM1_IRQHandler /* LPTIM1 */\r
+ .word CEC_IRQHandler /* HDMI_CEC */\r
+ .word I2C4_EV_IRQHandler /* I2C4 Event */\r
+ .word I2C4_ER_IRQHandler /* I2C4 Error */\r
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */\r
+ .word 0 /* Reserved */\r
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */\r
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */\r
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */\r
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */\r
+ .word SDMMC2_IRQHandler /* SDMMC2 */\r
+ .word CAN3_TX_IRQHandler /* CAN3 TX */\r
+ .word CAN3_RX0_IRQHandler /* CAN3 RX0 */\r
+ .word CAN3_RX1_IRQHandler /* CAN3 RX1 */\r
+ .word CAN3_SCE_IRQHandler /* CAN3 SCE */\r
+ .word JPEG_IRQHandler /* JPEG */\r
+ .word MDIOS_IRQHandler /* MDIOS */\r
+ \r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler. \r
+* As they are weak aliases, any function with the same name will override \r
+* this definition.\r
+* \r
+*******************************************************************************/\r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+ \r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+ \r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+ \r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler \r
+ \r
+ .weak WWDG_IRQHandler \r
+ .thumb_set WWDG_IRQHandler,Default_Handler \r
+ \r
+ .weak PVD_IRQHandler \r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+ \r
+ .weak TAMP_STAMP_IRQHandler \r
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r
+ \r
+ .weak RTC_WKUP_IRQHandler \r
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r
+ \r
+ .weak FLASH_IRQHandler \r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+ \r
+ .weak RCC_IRQHandler \r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI0_IRQHandler \r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI1_IRQHandler \r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI2_IRQHandler \r
+ .thumb_set EXTI2_IRQHandler,Default_Handler \r
+ \r
+ .weak EXTI3_IRQHandler \r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI4_IRQHandler \r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream0_IRQHandler \r
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream1_IRQHandler \r
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream2_IRQHandler \r
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream3_IRQHandler \r
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler \r
+ \r
+ .weak DMA1_Stream4_IRQHandler \r
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream5_IRQHandler \r
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream6_IRQHandler \r
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\r
+ \r
+ .weak ADC_IRQHandler \r
+ .thumb_set ADC_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_TX_IRQHandler \r
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_RX0_IRQHandler \r
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_RX1_IRQHandler \r
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN1_SCE_IRQHandler \r
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI9_5_IRQHandler \r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_BRK_TIM9_IRQHandler \r
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_UP_TIM10_IRQHandler \r
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_TRG_COM_TIM11_IRQHandler \r
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM1_CC_IRQHandler \r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM2_IRQHandler \r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM3_IRQHandler \r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM4_IRQHandler \r
+ .thumb_set TIM4_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C1_EV_IRQHandler \r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C1_ER_IRQHandler \r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C2_EV_IRQHandler \r
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C2_ER_IRQHandler \r
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI1_IRQHandler \r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI2_IRQHandler \r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+ \r
+ .weak USART1_IRQHandler \r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+ \r
+ .weak USART2_IRQHandler \r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+ \r
+ .weak USART3_IRQHandler \r
+ .thumb_set USART3_IRQHandler,Default_Handler\r
+ \r
+ .weak EXTI15_10_IRQHandler \r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+ \r
+ .weak RTC_Alarm_IRQHandler \r
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_FS_WKUP_IRQHandler \r
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_BRK_TIM12_IRQHandler \r
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_UP_TIM13_IRQHandler \r
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_TRG_COM_TIM14_IRQHandler \r
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM8_CC_IRQHandler \r
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA1_Stream7_IRQHandler \r
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\r
+ \r
+ .weak FMC_IRQHandler \r
+ .thumb_set FMC_IRQHandler,Default_Handler\r
+ \r
+ .weak SDMMC1_IRQHandler \r
+ .thumb_set SDMMC1_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM5_IRQHandler \r
+ .thumb_set TIM5_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI3_IRQHandler \r
+ .thumb_set SPI3_IRQHandler,Default_Handler\r
+ \r
+ .weak UART4_IRQHandler \r
+ .thumb_set UART4_IRQHandler,Default_Handler\r
+ \r
+ .weak UART5_IRQHandler \r
+ .thumb_set UART5_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM6_DAC_IRQHandler \r
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r
+ \r
+ .weak TIM7_IRQHandler \r
+ .thumb_set TIM7_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream0_IRQHandler \r
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream1_IRQHandler \r
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream2_IRQHandler \r
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream3_IRQHandler \r
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream4_IRQHandler \r
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream4_IRQHandler \r
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler \r
+\r
+ .weak ETH_IRQHandler \r
+ .thumb_set ETH_IRQHandler,Default_Handler\r
+ \r
+ .weak ETH_WKUP_IRQHandler \r
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_TX_IRQHandler \r
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler \r
+ \r
+ .weak CAN2_RX0_IRQHandler \r
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN2_RX1_IRQHandler \r
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r
+ \r
+ .weak CAN2_SCE_IRQHandler \r
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_FS_IRQHandler \r
+ .thumb_set OTG_FS_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream5_IRQHandler \r
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream6_IRQHandler \r
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\r
+ \r
+ .weak DMA2_Stream7_IRQHandler \r
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\r
+ \r
+ .weak USART6_IRQHandler \r
+ .thumb_set USART6_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C3_EV_IRQHandler \r
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C3_ER_IRQHandler \r
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_EP1_OUT_IRQHandler \r
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_EP1_IN_IRQHandler \r
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_WKUP_IRQHandler \r
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\r
+ \r
+ .weak OTG_HS_IRQHandler \r
+ .thumb_set OTG_HS_IRQHandler,Default_Handler\r
+ \r
+ .weak DCMI_IRQHandler \r
+ .thumb_set DCMI_IRQHandler,Default_Handler\r
+\r
+ .weak RNG_IRQHandler \r
+ .thumb_set RNG_IRQHandler,Default_Handler \r
+\r
+ .weak FPU_IRQHandler \r
+ .thumb_set FPU_IRQHandler,Default_Handler\r
+\r
+ .weak UART7_IRQHandler \r
+ .thumb_set UART7_IRQHandler,Default_Handler\r
+\r
+ .weak UART8_IRQHandler \r
+ .thumb_set UART8_IRQHandler,Default_Handler \r
+\r
+ .weak SPI4_IRQHandler \r
+ .thumb_set SPI4_IRQHandler,Default_Handler\r
+ \r
+ .weak SPI5_IRQHandler \r
+ .thumb_set SPI5_IRQHandler,Default_Handler\r
+\r
+ .weak SPI6_IRQHandler \r
+ .thumb_set SPI6_IRQHandler,Default_Handler \r
+\r
+ .weak SAI1_IRQHandler \r
+ .thumb_set SAI1_IRQHandler,Default_Handler\r
+ \r
+ .weak LTDC_IRQHandler \r
+ .thumb_set LTDC_IRQHandler,Default_Handler\r
+\r
+ .weak LTDC_ER_IRQHandler \r
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2D_IRQHandler \r
+ .thumb_set DMA2D_IRQHandler,Default_Handler \r
+\r
+ .weak SAI2_IRQHandler \r
+ .thumb_set SAI2_IRQHandler,Default_Handler\r
+ \r
+ .weak QUADSPI_IRQHandler \r
+ .thumb_set QUADSPI_IRQHandler,Default_Handler\r
+ \r
+ .weak LPTIM1_IRQHandler \r
+ .thumb_set LPTIM1_IRQHandler,Default_Handler\r
+\r
+ .weak CEC_IRQHandler \r
+ .thumb_set CEC_IRQHandler,Default_Handler\r
+ \r
+ .weak I2C4_EV_IRQHandler \r
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler \r
+ \r
+ .weak I2C4_ER_IRQHandler \r
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler\r
+ \r
+ .weak SPDIF_RX_IRQHandler \r
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT0_IRQHandler \r
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT1_IRQHandler \r
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT2_IRQHandler \r
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler\r
+\r
+ .weak DFSDM1_FLT3_IRQHandler \r
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler\r
+\r
+ .weak SDMMC2_IRQHandler \r
+ .thumb_set SDMMC2_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_TX_IRQHandler \r
+ .thumb_set CAN3_TX_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_RX0_IRQHandler \r
+ .thumb_set CAN3_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_RX1_IRQHandler \r
+ .thumb_set CAN3_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN3_SCE_IRQHandler \r
+ .thumb_set CAN3_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak JPEG_IRQHandler \r
+ .thumb_set JPEG_IRQHandler,Default_Handler\r
+\r
+ .weak MDIOS_IRQHandler \r
+ .thumb_set MDIOS_IRQHandler,Default_Handler \r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+ \r
--- /dev/null
+# This is an genericBoard board with a single STM32F767ZITx chip
+#
+# Generated by STM32CubeIDE
+# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
+
+source [find interface/stlink.cfg]
+
+set WORKAREASIZE 0x8000
+
+transport select "hla_swd"
+
+set CHIPNAME STM32F767ZITx
+set BOARDNAME genericBoard
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# STlink Debug clock frequency
+set CLOCK_FREQ 8000
+
+# use hardware reset, connect under reset
+# connect_assert_srst needed if low power mode application running (WFI...)
+reset_config srst_only srst_nogate connect_assert_srst
+set CONNECT_UNDER_RESET 1
+
+# BCTM CPU variables
+
+source [find target/stm32f7x.cfg]
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
+<intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_DEVICE_SHAREABLE_ALLOWED" value="false"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_INTERFACE" value="Swd"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_INTERFACE_FREQUENCY" value="8000000.0"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_LOW_POWER_MODE_ALLOWED" value="true"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_RESET_MODE" value="connect_under_reset"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.DBG_STOP_WATCHDOG_THEN_HALTED_ALLOWED" value="true"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_GENERATOR_OPTION" value="false"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_NAME" value=""${stm32cubeide_openocd_path}/openocd""/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_OTHER_OPTIONS" value=""/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_SCRIPT" value="${ProjDirPath}/encoder.elf.cfg"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.openocd.OPENOCD_SCRIPT_CHOICE" value="automated"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/home/fdila/Projects/stm32-tests/encoder/Debug/st-link_gdbserver_log.txt"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_ap_id" value="0"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="ST-LINK (OpenOCD)"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/encoder.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="encoder"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/encoder"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
--- /dev/null
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32F7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IP4=TIM2
+Mcu.IP5=TIM5
+Mcu.IPNb=6
+Mcu.Name=STM32F767ZITx
+Mcu.Package=LQFP144
+Mcu.Pin0=PA0/WKUP
+Mcu.Pin1=PA1
+Mcu.Pin2=PA5
+Mcu.Pin3=PB3
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.PinsNb=5
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F767ZITx
+MxCube.Version=5.3.0
+MxDb.Version=DB.5.0.30
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0/WKUP.Signal=S_TIM5_CH1
+PA1.Signal=S_TIM5_CH2
+PA5.GPIOParameters=GPIO_PuPd
+PA5.GPIO_PuPd=GPIO_PULLUP
+PA5.Signal=S_TIM2_CH1_ETR
+PB3.GPIOParameters=GPIO_PuPd
+PB3.GPIO_PuPd=GPIO_PULLUP
+PB3.Signal=S_TIM2_CH2
+PCC.Checker=false
+PCC.Line=STM32F7x7
+PCC.MCU=STM32F767ZITx
+PCC.PartNumber=STM32F767ZITx
+PCC.Seq0=0
+PCC.Series=STM32F7
+PCC.Temperature=25
+PCC.Vdd=3.3
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F767ZITx
+ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.15.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=encoder.ioc
+ProjectManager.ProjectName=encoder
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=2-SystemClock_Config-RCC-false-HAL-false
+RCC.CECFreq_Value=32786.88524590164
+RCC.DFSDMFreq_Value=16000000
+RCC.FamilyName=M
+RCC.HSE_VALUE=25000000
+RCC.HSI_VALUE=16000000
+RCC.I2SFreq_Value=96000000
+RCC.IPParameters=CECFreq_Value,DFSDMFreq_Value,FamilyName,HSE_VALUE,HSI_VALUE,I2SFreq_Value,LCDTFTFreq_Value,LSE_VALUE,LSI_VALUE,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLQCLKFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
+RCC.LCDTFTFreq_Value=48000000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.PLLCLKFreq_Value=96000000
+RCC.PLLI2SPCLKFreq_Value=96000000
+RCC.PLLI2SQCLKFreq_Value=96000000
+RCC.PLLI2SRCLKFreq_Value=96000000
+RCC.PLLQCLKFreq_Value=96000000
+RCC.PLLSAIPCLKFreq_Value=96000000
+RCC.PLLSAIQCLKFreq_Value=96000000
+RCC.PLLSAIRCLKFreq_Value=96000000
+RCC.PLLSAIoutputFreq_Value=96000000
+RCC.RNGFreq_Value=96000000
+RCC.SAI1Freq_Value=96000000
+RCC.SAI2Freq_Value=96000000
+RCC.SDMMC2Freq_Value=16000000
+RCC.SDMMCFreq_Value=16000000
+RCC.SPDIFRXFreq_Value=96000000
+RCC.USBFreq_Value=96000000
+RCC.VCOI2SOutputFreq_Value=192000000
+RCC.VCOInputFreq_Value=1000000
+RCC.VCOOutputFreq_Value=192000000
+RCC.VCOSAIOutputFreq_Value=192000000
+SH.S_TIM2_CH1_ETR.0=TIM2_CH1,Encoder_Interface
+SH.S_TIM2_CH1_ETR.ConfNb=1
+SH.S_TIM2_CH2.0=TIM2_CH2,Encoder_Interface
+SH.S_TIM2_CH2.ConfNb=1
+SH.S_TIM5_CH1.0=TIM5_CH1,Encoder_Interface
+SH.S_TIM5_CH1.ConfNb=1
+SH.S_TIM5_CH2.0=TIM5_CH2,Encoder_Interface
+SH.S_TIM5_CH2.ConfNb=1
+TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+TIM2.CounterMode=TIM_COUNTERMODE_UP
+TIM2.EncoderMode=TIM_ENCODERMODE_TI12
+TIM2.IC1Polarity=TIM_ICPOLARITY_FALLING
+TIM2.IC1Prescaler=TIM_ICPSC_DIV1
+TIM2.IC2Polarity=TIM_ICPOLARITY_FALLING
+TIM2.IPParameters=EncoderMode,Period,CounterMode,AutoReloadPreload,IC1Prescaler,IC1Polarity,IC2Polarity
+TIM2.Period=148000
+TIM5.IPParameters=Period
+TIM5.Period=4294967295
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
+isbadioc=false
projects / pioneer-stm32 / commitdiff