+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Core/Src/stm32f7xx_hal_msp.c \
-../Core/Src/stm32f7xx_it.c \
-../Core/Src/syscalls.c \
-../Core/Src/sysmem.c \
-../Core/Src/system_stm32f7xx.c
-
-CPP_SRCS += \
-../Core/Src/encoder.cpp \
-../Core/Src/main.cpp
-
-OBJS += \
-./Core/Src/encoder.o \
-./Core/Src/main.o \
-./Core/Src/stm32f7xx_hal_msp.o \
-./Core/Src/stm32f7xx_it.o \
-./Core/Src/syscalls.o \
-./Core/Src/sysmem.o \
-./Core/Src/system_stm32f7xx.o
-
-C_DEPS += \
-./Core/Src/stm32f7xx_hal_msp.d \
-./Core/Src/stm32f7xx_it.d \
-./Core/Src/syscalls.d \
-./Core/Src/sysmem.d \
-./Core/Src/system_stm32f7xx.d
-
-CPP_DEPS += \
-./Core/Src/encoder.d \
-./Core/Src/main.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Src/encoder.o: ../Core/Src/encoder.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/encoder.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/main.o: ../Core/Src/main.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/syscalls.o: ../Core/Src/syscalls.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/sysmem.o: ../Core/Src/sysmem.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-S_SRCS += \
-../Core/Startup/startup_stm32f767zitx.s
-
-OBJS += \
-./Core/Startup/startup_stm32f767zitx.o
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Startup/%.o: ../Core/Startup/%.s
- arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
-
-OBJS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o
-
-C_DEPS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
--include ../makefile.init
-
-RM := rm -rf
-
-# All of the sources participating in the build are defined here
--include sources.mk
--include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk
--include Core/Startup/subdir.mk
--include Core/Src/subdir.mk
--include subdir.mk
--include objects.mk
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(CC_DEPS)),)
--include $(CC_DEPS)
-endif
-ifneq ($(strip $(C++_DEPS)),)
--include $(C++_DEPS)
-endif
-ifneq ($(strip $(C_UPPER_DEPS)),)
--include $(C_UPPER_DEPS)
-endif
-ifneq ($(strip $(CXX_DEPS)),)
--include $(CXX_DEPS)
-endif
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-ifneq ($(strip $(CPP_DEPS)),)
--include $(CPP_DEPS)
-endif
-endif
-
--include ../makefile.defs
-
-# Add inputs and outputs from these tool invocations to the build variables
-EXECUTABLES += \
-otto_controller.elf \
-
-SIZE_OUTPUT += \
-default.size.stdout \
-
-OBJDUMP_LIST += \
-otto_controller.list \
-
-
-# All Target
-all: otto_controller.elf secondary-outputs
-
-# Tool invocations
-otto_controller.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/otto_controller/STM32F767ZITX_FLASH.ld
- arm-none-eabi-g++ -o "otto_controller.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/otto_controller/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_controller.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
- @echo 'Finished building target: $@'
- @echo ' '
-
-default.size.stdout: $(EXECUTABLES)
- arm-none-eabi-size $(EXECUTABLES)
- @echo 'Finished building: $@'
- @echo ' '
-
-otto_controller.list: $(EXECUTABLES)
- arm-none-eabi-objdump -h -S $(EXECUTABLES) > "otto_controller.list"
- @echo 'Finished building: $@'
- @echo ' '
-
-# Other Targets
-clean:
- -$(RM) *
- -@echo ' '
-
-secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
-
-.PHONY: all clean dependents
-.SECONDARY:
-
--include ../makefile.targets
+++ /dev/null
-"Core/Src/encoder.o"
-"Core/Src/main.o"
-"Core/Src/stm32f7xx_hal_msp.o"
-"Core/Src/stm32f7xx_it.o"
-"Core/Src/syscalls.o"
-"Core/Src/sysmem.o"
-"Core/Src/system_stm32f7xx.o"
-"Core/Startup/startup_stm32f767zitx.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o"
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-USER_OBJS :=
-
-LIBS :=
-
+++ /dev/null
-
-otto_controller.elf: file format elf32-littlearm
-
-Sections:
-Idx Name Size VMA LMA File off Algn
- 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 000051ac 080001f8 080001f8 000101f8 2**3
- CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000018 080053a4 080053a4 000153a4 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 080053bc 080053bc 0002000c 2**0
- CONTENTS
- 4 .ARM 00000008 080053bc 080053bc 000153bc 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 080053c4 080053c4 0002000c 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000008 080053c4 080053c4 000153c4 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 080053cc 080053cc 000153cc 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 8 .data 0000000c 20000000 080053d0 00020000 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 000002e4 2000000c 080053dc 0002000c 2**2
- ALLOC
- 10 ._user_heap_stack 00000600 200002f0 080053dc 000202f0 2**0
- ALLOC
- 11 .ARM.attributes 0000002e 00000000 00000000 0002000c 2**0
- CONTENTS, READONLY
- 12 .debug_info 0000db5b 00000000 00000000 0002003a 2**0
- CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00001e3b 00000000 00000000 0002db95 2**0
- CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000d68 00000000 00000000 0002f9d0 2**3
- CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000c80 00000000 00000000 00030738 2**3
- CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 0002823f 00000000 00000000 000313b8 2**0
- CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 00009a58 00000000 00000000 000595f7 2**0
- CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000f1de0 00000000 00000000 0006304f 2**0
- CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 00154e2f 2**0
- CONTENTS, READONLY
- 20 .debug_frame 0000385c 00000000 00000000 00154eac 2**2
- CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-080001f8 <__do_global_dtors_aux>:
- 80001f8: b510 push {r4, lr}
- 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
- 80001fc: 7823 ldrb r3, [r4, #0]
- 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
- 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
- 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
- 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
- 8000206: f3af 8000 nop.w
- 800020a: 2301 movs r3, #1
- 800020c: 7023 strb r3, [r4, #0]
- 800020e: bd10 pop {r4, pc}
- 8000210: 2000000c .word 0x2000000c
- 8000214: 00000000 .word 0x00000000
- 8000218: 0800538c .word 0x0800538c
-
-0800021c <frame_dummy>:
- 800021c: b508 push {r3, lr}
- 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
- 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
- 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
- 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
- 8000226: f3af 8000 nop.w
- 800022a: bd08 pop {r3, pc}
- 800022c: 00000000 .word 0x00000000
- 8000230: 20000010 .word 0x20000010
- 8000234: 0800538c .word 0x0800538c
-
-08000238 <__aeabi_uldivmod>:
- 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
- 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
- 800023c: 2900 cmp r1, #0
- 800023e: bf08 it eq
- 8000240: 2800 cmpeq r0, #0
- 8000242: bf1c itt ne
- 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
- 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
- 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0>
- 8000250: f1ad 0c08 sub.w ip, sp, #8
- 8000254: e96d ce04 strd ip, lr, [sp, #-16]!
- 8000258: f000 f806 bl 8000268 <__udivmoddi4>
- 800025c: f8dd e004 ldr.w lr, [sp, #4]
- 8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
- 8000264: b004 add sp, #16
- 8000266: 4770 bx lr
-
-08000268 <__udivmoddi4>:
- 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 800026c: 9e08 ldr r6, [sp, #32]
- 800026e: 4604 mov r4, r0
- 8000270: 4688 mov r8, r1
- 8000272: 2b00 cmp r3, #0
- 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6>
- 8000276: 428a cmp r2, r1
- 8000278: 4615 mov r5, r2
- 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4>
- 800027c: fab2 f282 clz r2, r2
- 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e>
- 8000282: f1c2 0720 rsb r7, r2, #32
- 8000286: fa01 f302 lsl.w r3, r1, r2
- 800028a: fa20 f707 lsr.w r7, r0, r7
- 800028e: 4095 lsls r5, r2
- 8000290: ea47 0803 orr.w r8, r7, r3
- 8000294: 4094 lsls r4, r2
- 8000296: ea4f 4e15 mov.w lr, r5, lsr #16
- 800029a: 0c23 lsrs r3, r4, #16
- 800029c: fbb8 f7fe udiv r7, r8, lr
- 80002a0: fa1f fc85 uxth.w ip, r5
- 80002a4: fb0e 8817 mls r8, lr, r7, r8
- 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16
- 80002ac: fb07 f10c mul.w r1, r7, ip
- 80002b0: 4299 cmp r1, r3
- 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60>
- 80002b4: 18eb adds r3, r5, r3
- 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
- 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c>
- 80002be: 4299 cmp r1, r3
- 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c>
- 80002c4: 3f02 subs r7, #2
- 80002c6: 442b add r3, r5
- 80002c8: 1a5b subs r3, r3, r1
- 80002ca: b2a4 uxth r4, r4
- 80002cc: fbb3 f0fe udiv r0, r3, lr
- 80002d0: fb0e 3310 mls r3, lr, r0, r3
- 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16
- 80002d8: fb00 fc0c mul.w ip, r0, ip
- 80002dc: 45a4 cmp ip, r4
- 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c>
- 80002e0: 192c adds r4, r5, r4
- 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290>
- 80002ea: 45a4 cmp ip, r4
- 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290>
- 80002f0: 3802 subs r0, #2
- 80002f2: 442c add r4, r5
- 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16
- 80002f8: eba4 040c sub.w r4, r4, ip
- 80002fc: 2700 movs r7, #0
- 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0>
- 8000300: 40d4 lsrs r4, r2
- 8000302: 2300 movs r3, #0
- 8000304: e9c6 4300 strd r4, r3, [r6]
- 8000308: 4639 mov r1, r7
- 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 800030e: 428b cmp r3, r1
- 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe>
- 8000312: 2e00 cmp r6, #0
- 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286>
- 8000318: 2700 movs r7, #0
- 800031a: e9c6 0100 strd r0, r1, [r6]
- 800031e: 4638 mov r0, r7
- 8000320: 4639 mov r1, r7
- 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000326: fab3 f783 clz r7, r3
- 800032a: 2f00 cmp r7, #0
- 800032c: d147 bne.n 80003be <__udivmoddi4+0x156>
- 800032e: 428b cmp r3, r1
- 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0>
- 8000332: 4282 cmp r2, r0
- 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4>
- 8000338: 1a84 subs r4, r0, r2
- 800033a: eb61 0303 sbc.w r3, r1, r3
- 800033e: 2001 movs r0, #1
- 8000340: 4698 mov r8, r3
- 8000342: 2e00 cmp r6, #0
- 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0>
- 8000346: e9c6 4800 strd r4, r8, [r6]
- 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0>
- 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8>
- 800034e: deff udf #255 ; 0xff
- 8000350: fab2 f282 clz r2, r2
- 8000354: 2a00 cmp r2, #0
- 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210>
- 800035a: 1b49 subs r1, r1, r5
- 800035c: ea4f 4e15 mov.w lr, r5, lsr #16
- 8000360: fa1f f885 uxth.w r8, r5
- 8000364: 2701 movs r7, #1
- 8000366: fbb1 fcfe udiv ip, r1, lr
- 800036a: 0c23 lsrs r3, r4, #16
- 800036c: fb0e 111c mls r1, lr, ip, r1
- 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16
- 8000374: fb08 f10c mul.w r1, r8, ip
- 8000378: 4299 cmp r1, r3
- 800037a: d907 bls.n 800038c <__udivmoddi4+0x124>
- 800037c: 18eb adds r3, r5, r3
- 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
- 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122>
- 8000384: 4299 cmp r1, r3
- 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc>
- 800038a: 4684 mov ip, r0
- 800038c: 1a59 subs r1, r3, r1
- 800038e: b2a3 uxth r3, r4
- 8000390: fbb1 f0fe udiv r0, r1, lr
- 8000394: fb0e 1410 mls r4, lr, r0, r1
- 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16
- 800039c: fb08 f800 mul.w r8, r8, r0
- 80003a0: 45a0 cmp r8, r4
- 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c>
- 80003a4: 192c adds r4, r5, r4
- 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a>
- 80003ac: 45a0 cmp r8, r4
- 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6>
- 80003b2: 4618 mov r0, r3
- 80003b4: eba4 0408 sub.w r4, r4, r8
- 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16
- 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96>
- 80003be: f1c7 0c20 rsb ip, r7, #32
- 80003c2: 40bb lsls r3, r7
- 80003c4: fa22 fe0c lsr.w lr, r2, ip
- 80003c8: ea4e 0e03 orr.w lr, lr, r3
- 80003cc: fa01 f407 lsl.w r4, r1, r7
- 80003d0: fa20 f50c lsr.w r5, r0, ip
- 80003d4: fa21 f30c lsr.w r3, r1, ip
- 80003d8: ea4f 481e mov.w r8, lr, lsr #16
- 80003dc: 4325 orrs r5, r4
- 80003de: fbb3 f9f8 udiv r9, r3, r8
- 80003e2: 0c2c lsrs r4, r5, #16
- 80003e4: fb08 3319 mls r3, r8, r9, r3
- 80003e8: fa1f fa8e uxth.w sl, lr
- 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16
- 80003f0: fb09 f40a mul.w r4, r9, sl
- 80003f4: 429c cmp r4, r3
- 80003f6: fa02 f207 lsl.w r2, r2, r7
- 80003fa: fa00 f107 lsl.w r1, r0, r7
- 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0>
- 8000400: eb1e 0303 adds.w r3, lr, r3
- 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
- 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2>
- 800040c: 429c cmp r4, r3
- 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2>
- 8000412: f1a9 0902 sub.w r9, r9, #2
- 8000416: 4473 add r3, lr
- 8000418: 1b1b subs r3, r3, r4
- 800041a: b2ad uxth r5, r5
- 800041c: fbb3 f0f8 udiv r0, r3, r8
- 8000420: fb08 3310 mls r3, r8, r0, r3
- 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16
- 8000428: fb00 fa0a mul.w sl, r0, sl
- 800042c: 45a2 cmp sl, r4
- 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da>
- 8000430: eb1e 0404 adds.w r4, lr, r4
- 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa>
- 800043a: 45a2 cmp sl, r4
- 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa>
- 800043e: 3802 subs r0, #2
- 8000440: 4474 add r4, lr
- 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16
- 8000446: fba0 8902 umull r8, r9, r0, r2
- 800044a: eba4 040a sub.w r4, r4, sl
- 800044e: 454c cmp r4, r9
- 8000450: 46c2 mov sl, r8
- 8000452: 464b mov r3, r9
- 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298>
- 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294>
- 8000458: 2e00 cmp r6, #0
- 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8>
- 800045c: ebb1 050a subs.w r5, r1, sl
- 8000460: eb64 0403 sbc.w r4, r4, r3
- 8000464: fa04 fc0c lsl.w ip, r4, ip
- 8000468: 40fd lsrs r5, r7
- 800046a: 40fc lsrs r4, r7
- 800046c: ea4c 0505 orr.w r5, ip, r5
- 8000470: e9c6 5400 strd r5, r4, [r6]
- 8000474: 2700 movs r7, #0
- 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0>
- 8000478: f1c2 0320 rsb r3, r2, #32
- 800047c: fa20 f703 lsr.w r7, r0, r3
- 8000480: 4095 lsls r5, r2
- 8000482: fa01 f002 lsl.w r0, r1, r2
- 8000486: fa21 f303 lsr.w r3, r1, r3
- 800048a: ea4f 4e15 mov.w lr, r5, lsr #16
- 800048e: 4338 orrs r0, r7
- 8000490: 0c01 lsrs r1, r0, #16
- 8000492: fbb3 f7fe udiv r7, r3, lr
- 8000496: fa1f f885 uxth.w r8, r5
- 800049a: fb0e 3317 mls r3, lr, r7, r3
- 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004a2: fb07 f308 mul.w r3, r7, r8
- 80004a6: 428b cmp r3, r1
- 80004a8: fa04 f402 lsl.w r4, r4, r2
- 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256>
- 80004ae: 1869 adds r1, r5, r1
- 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
- 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae>
- 80004b6: 428b cmp r3, r1
- 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae>
- 80004ba: 3f02 subs r7, #2
- 80004bc: 4429 add r1, r5
- 80004be: 1acb subs r3, r1, r3
- 80004c0: b281 uxth r1, r0
- 80004c2: fbb3 f0fe udiv r0, r3, lr
- 80004c6: fb0e 3310 mls r3, lr, r0, r3
- 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004ce: fb00 f308 mul.w r3, r0, r8
- 80004d2: 428b cmp r3, r1
- 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e>
- 80004d6: 1869 adds r1, r5, r1
- 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
- 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6>
- 80004de: 428b cmp r3, r1
- 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6>
- 80004e2: 3802 subs r0, #2
- 80004e4: 4429 add r1, r5
- 80004e6: 1ac9 subs r1, r1, r3
- 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16
- 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe>
- 80004ee: 4637 mov r7, r6
- 80004f0: 4630 mov r0, r6
- 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0>
- 80004f4: 4607 mov r7, r0
- 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60>
- 80004f8: 4618 mov r0, r3
- 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c>
- 80004fc: 4541 cmp r1, r8
- 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0>
- 8000500: ebb8 0a02 subs.w sl, r8, r2
- 8000504: eb69 020e sbc.w r2, r9, lr
- 8000508: 3801 subs r0, #1
- 800050a: 4613 mov r3, r2
- 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0>
- 800050e: 4660 mov r0, ip
- 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e>
- 8000512: 4618 mov r0, r3
- 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da>
- 8000516: 4667 mov r7, ip
- 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256>
- 800051a: 4681 mov r9, r0
- 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0>
- 800051e: 3802 subs r0, #2
- 8000520: 442c add r4, r5
- 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c>
- 8000524: f1ac 0c02 sub.w ip, ip, #2
- 8000528: 442b add r3, r5
- 800052a: e72f b.n 800038c <__udivmoddi4+0x124>
- 800052c: 4638 mov r0, r7
- 800052e: e708 b.n 8000342 <__udivmoddi4+0xda>
- 8000530: 4637 mov r7, r6
- 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0>
-
-08000534 <__aeabi_idiv0>:
- 8000534: 4770 bx lr
- 8000536: bf00 nop
-
-08000538 <_ZN7Encoder8GetCountEv>:
- Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters);
-
-
- void Setup();
-
- int GetCount() {
- 8000538: b480 push {r7}
- 800053a: b085 sub sp, #20
- 800053c: af00 add r7, sp, #0
- 800053e: 6078 str r0, [r7, #4]
- int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_)
- 8000540: 687b ldr r3, [r7, #4]
- 8000542: 681b ldr r3, [r3, #0]
- 8000544: 681b ldr r3, [r3, #0]
- 8000546: 6a5a ldr r2, [r3, #36] ; 0x24
- - ((this->timer_->Init.Period) / 2));
- 8000548: 687b ldr r3, [r7, #4]
- 800054a: 681b ldr r3, [r3, #0]
- 800054c: 68db ldr r3, [r3, #12]
- 800054e: 085b lsrs r3, r3, #1
- 8000550: 1ad3 subs r3, r2, r3
- 8000552: 60fb str r3, [r7, #12]
- return count;
- 8000554: 68fb ldr r3, [r7, #12]
- }
- 8000556: 4618 mov r0, r3
- 8000558: 3714 adds r7, #20
- 800055a: 46bd mov sp, r7
- 800055c: f85d 7b04 ldr.w r7, [sp], #4
- 8000560: 4770 bx lr
-
-08000562 <_ZN7Encoder10ResetCountEv>:
-
- void ResetCount() {
- 8000562: b480 push {r7}
- 8000564: b083 sub sp, #12
- 8000566: af00 add r7, sp, #0
- 8000568: 6078 str r0, [r7, #4]
- //set counter to half its maximum value
- __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period / 2));
- 800056a: 687b ldr r3, [r7, #4]
- 800056c: 681b ldr r3, [r3, #0]
- 800056e: 68da ldr r2, [r3, #12]
- 8000570: 687b ldr r3, [r7, #4]
- 8000572: 681b ldr r3, [r3, #0]
- 8000574: 681b ldr r3, [r3, #0]
- 8000576: 0852 lsrs r2, r2, #1
- 8000578: 625a str r2, [r3, #36] ; 0x24
- }
- 800057a: bf00 nop
- 800057c: 370c adds r7, #12
- 800057e: 46bd mov sp, r7
- 8000580: f85d 7b04 ldr.w r7, [sp], #4
- 8000584: 4770 bx lr
-
-08000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>:
-// timer_ = timer;
-// wheel_circumference_ = wheel_circ;
-//
-//}
-
-Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) {
- 8000586: b480 push {r7}
- 8000588: b085 sub sp, #20
- 800058a: af00 add r7, sp, #0
- 800058c: 60f8 str r0, [r7, #12]
- 800058e: 60b9 str r1, [r7, #8]
- 8000590: 607a str r2, [r7, #4]
- timer_ = timer;
- 8000592: 68fb ldr r3, [r7, #12]
- 8000594: 68ba ldr r2, [r7, #8]
- 8000596: 601a str r2, [r3, #0]
- ticks_per_meter_ = ticks_per_meter;
- 8000598: 68fb ldr r3, [r7, #12]
- 800059a: 687a ldr r2, [r7, #4]
- 800059c: 615a str r2, [r3, #20]
-
-}
- 800059e: 68fb ldr r3, [r7, #12]
- 80005a0: 4618 mov r0, r3
- 80005a2: 3714 adds r7, #20
- 80005a4: 46bd mov sp, r7
- 80005a6: f85d 7b04 ldr.w r7, [sp], #4
- 80005aa: 4770 bx lr
-
-080005ac <_ZN7Encoder5SetupEv>:
-
-void Encoder::Setup() {
- 80005ac: b580 push {r7, lr}
- 80005ae: b082 sub sp, #8
- 80005b0: af00 add r7, sp, #0
- 80005b2: 6078 str r0, [r7, #4]
- HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL);
- 80005b4: 687b ldr r3, [r7, #4]
- 80005b6: 681b ldr r3, [r3, #0]
- 80005b8: 213c movs r1, #60 ; 0x3c
- 80005ba: 4618 mov r0, r3
- 80005bc: f002 ffce bl 800355c <HAL_TIM_Encoder_Start>
- this->ResetCount();
- 80005c0: 6878 ldr r0, [r7, #4]
- 80005c2: f7ff ffce bl 8000562 <_ZN7Encoder10ResetCountEv>
- this->previous_millis_ = 0;
- 80005c6: 687b ldr r3, [r7, #4]
- 80005c8: 2200 movs r2, #0
- 80005ca: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005cc: f001 fae2 bl 8001b94 <HAL_GetTick>
- 80005d0: 4602 mov r2, r0
- 80005d2: 687b ldr r3, [r7, #4]
- 80005d4: 609a str r2, [r3, #8]
-}
- 80005d6: bf00 nop
- 80005d8: 3708 adds r7, #8
- 80005da: 46bd mov sp, r7
- 80005dc: bd80 pop {r7, pc}
-
-080005de <_ZN7Encoder12UpdateValuesEv>:
-
-void Encoder::UpdateValues() {
- 80005de: b580 push {r7, lr}
- 80005e0: b082 sub sp, #8
- 80005e2: af00 add r7, sp, #0
- 80005e4: 6078 str r0, [r7, #4]
- this->previous_millis_ = this->current_millis_;
- 80005e6: 687b ldr r3, [r7, #4]
- 80005e8: 689a ldr r2, [r3, #8]
- 80005ea: 687b ldr r3, [r7, #4]
- 80005ec: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005ee: f001 fad1 bl 8001b94 <HAL_GetTick>
- 80005f2: 4602 mov r2, r0
- 80005f4: 687b ldr r3, [r7, #4]
- 80005f6: 609a str r2, [r3, #8]
- this->ticks_ = this->GetCount();
- 80005f8: 6878 ldr r0, [r7, #4]
- 80005fa: f7ff ff9d bl 8000538 <_ZN7Encoder8GetCountEv>
- 80005fe: 4602 mov r2, r0
- 8000600: 687b ldr r3, [r7, #4]
- 8000602: 60da str r2, [r3, #12]
- this->ResetCount();
- 8000604: 6878 ldr r0, [r7, #4]
- 8000606: f7ff ffac bl 8000562 <_ZN7Encoder10ResetCountEv>
-}
- 800060a: bf00 nop
- 800060c: 3708 adds r7, #8
- 800060e: 46bd mov sp, r7
- 8000610: bd80 pop {r7, pc}
-
-08000612 <_ZN7Encoder9GetMetersEv>:
-// float meters = ((float) this->ticks_ * this->wheel_circumference_)
-// / TICKS_PER_REVOLUTION;
-// return meters;
-//}
-
-float Encoder::GetMeters() {
- 8000612: b480 push {r7}
- 8000614: b085 sub sp, #20
- 8000616: af00 add r7, sp, #0
- 8000618: 6078 str r0, [r7, #4]
- float meters = (((float) this->ticks_) / this->ticks_per_meter_);
- 800061a: 687b ldr r3, [r7, #4]
- 800061c: 68db ldr r3, [r3, #12]
- 800061e: ee07 3a90 vmov s15, r3
- 8000622: eef8 6ae7 vcvt.f32.s32 s13, s15
- 8000626: 687b ldr r3, [r7, #4]
- 8000628: 695b ldr r3, [r3, #20]
- 800062a: ee07 3a90 vmov s15, r3
- 800062e: eeb8 7ae7 vcvt.f32.s32 s14, s15
- 8000632: eec6 7a87 vdiv.f32 s15, s13, s14
- 8000636: edc7 7a03 vstr s15, [r7, #12]
- return meters;
- 800063a: 68fb ldr r3, [r7, #12]
- 800063c: ee07 3a90 vmov s15, r3
-}
- 8000640: eeb0 0a67 vmov.f32 s0, s15
- 8000644: 3714 adds r7, #20
- 8000646: 46bd mov sp, r7
- 8000648: f85d 7b04 ldr.w r7, [sp], #4
- 800064c: 4770 bx lr
- ...
-
-08000650 <_ZN7Encoder17GetLinearVelocityEv>:
-
-
-float Encoder::GetLinearVelocity() {
- 8000650: b580 push {r7, lr}
- 8000652: b086 sub sp, #24
- 8000654: af00 add r7, sp, #0
- 8000656: 6078 str r0, [r7, #4]
- this->UpdateValues();
- 8000658: 6878 ldr r0, [r7, #4]
- 800065a: f7ff ffc0 bl 80005de <_ZN7Encoder12UpdateValuesEv>
- float meters = this->GetMeters();
- 800065e: 6878 ldr r0, [r7, #4]
- 8000660: f7ff ffd7 bl 8000612 <_ZN7Encoder9GetMetersEv>
- 8000664: ed87 0a05 vstr s0, [r7, #20]
- float deltaTime = this->current_millis_ - this->previous_millis_;
- 8000668: 687b ldr r3, [r7, #4]
- 800066a: 689a ldr r2, [r3, #8]
- 800066c: 687b ldr r3, [r7, #4]
- 800066e: 685b ldr r3, [r3, #4]
- 8000670: 1ad3 subs r3, r2, r3
- 8000672: ee07 3a90 vmov s15, r3
- 8000676: eef8 7a67 vcvt.f32.u32 s15, s15
- 800067a: edc7 7a04 vstr s15, [r7, #16]
- if (deltaTime == 0)
- 800067e: edd7 7a04 vldr s15, [r7, #16]
- 8000682: eef5 7a40 vcmp.f32 s15, #0.0
- 8000686: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800068a: d102 bne.n 8000692 <_ZN7Encoder17GetLinearVelocityEv+0x42>
- return 0;
- 800068c: f04f 0300 mov.w r3, #0
- 8000690: e00c b.n 80006ac <_ZN7Encoder17GetLinearVelocityEv+0x5c>
- float linear_velocity = (meters / (deltaTime / 1000));
- 8000692: edd7 7a04 vldr s15, [r7, #16]
- 8000696: eddf 6a09 vldr s13, [pc, #36] ; 80006bc <_ZN7Encoder17GetLinearVelocityEv+0x6c>
- 800069a: ee87 7aa6 vdiv.f32 s14, s15, s13
- 800069e: edd7 6a05 vldr s13, [r7, #20]
- 80006a2: eec6 7a87 vdiv.f32 s15, s13, s14
- 80006a6: edc7 7a03 vstr s15, [r7, #12]
- return linear_velocity;
- 80006aa: 68fb ldr r3, [r7, #12]
- 80006ac: ee07 3a90 vmov s15, r3
-}
- 80006b0: eeb0 0a67 vmov.f32 s0, s15
- 80006b4: 3718 adds r7, #24
- 80006b6: 46bd mov sp, r7
- 80006b8: bd80 pop {r7, pc}
- 80006ba: bf00 nop
- 80006bc: 447a0000 .word 0x447a0000
-
-080006c0 <_ZN8OdometryC1Ev>:
- float left_velocity_;
- float right_velocity_;
-
-
- public:
- Odometry() {
- 80006c0: b480 push {r7}
- 80006c2: b083 sub sp, #12
- 80006c4: af00 add r7, sp, #0
- 80006c6: 6078 str r0, [r7, #4]
- left_velocity_ = 0;
- 80006c8: 687b ldr r3, [r7, #4]
- 80006ca: f04f 0200 mov.w r2, #0
- 80006ce: 601a str r2, [r3, #0]
- right_velocity_ = 0;
- 80006d0: 687b ldr r3, [r7, #4]
- 80006d2: f04f 0200 mov.w r2, #0
- 80006d6: 605a str r2, [r3, #4]
- }
- 80006d8: 687b ldr r3, [r7, #4]
- 80006da: 4618 mov r0, r3
- 80006dc: 370c adds r7, #12
- 80006de: 46bd mov sp, r7
- 80006e0: f85d 7b04 ldr.w r7, [sp], #4
- 80006e4: 4770 bx lr
- ...
-
-080006e8 <_ZN8Odometry12UpdateValuesEff>:
-
- void UpdateValues(float linear_vel, float angular_vel) {
- 80006e8: b480 push {r7}
- 80006ea: b085 sub sp, #20
- 80006ec: af00 add r7, sp, #0
- 80006ee: 60f8 str r0, [r7, #12]
- 80006f0: ed87 0a02 vstr s0, [r7, #8]
- 80006f4: edc7 0a01 vstr s1, [r7, #4]
- left_velocity_ = linear_vel - (BASELINE * angular_vel)/2;
- 80006f8: edd7 7a02 vldr s15, [r7, #8]
- 80006fc: eeb7 6ae7 vcvt.f64.f32 d6, s15
- 8000700: edd7 7a01 vldr s15, [r7, #4]
- 8000704: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 8000708: ed9f 5b15 vldr d5, [pc, #84] ; 8000760 <_ZN8Odometry12UpdateValuesEff+0x78>
- 800070c: ee27 5b05 vmul.f64 d5, d7, d5
- 8000710: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 8000714: ee85 7b04 vdiv.f64 d7, d5, d4
- 8000718: ee36 7b47 vsub.f64 d7, d6, d7
- 800071c: eef7 7bc7 vcvt.f32.f64 s15, d7
- 8000720: 68fb ldr r3, [r7, #12]
- 8000722: edc3 7a00 vstr s15, [r3]
- right_velocity_ = linear_vel + (BASELINE * angular_vel)/2;
- 8000726: edd7 7a02 vldr s15, [r7, #8]
- 800072a: eeb7 6ae7 vcvt.f64.f32 d6, s15
- 800072e: edd7 7a01 vldr s15, [r7, #4]
- 8000732: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 8000736: ed9f 5b0a vldr d5, [pc, #40] ; 8000760 <_ZN8Odometry12UpdateValuesEff+0x78>
- 800073a: ee27 5b05 vmul.f64 d5, d7, d5
- 800073e: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 8000742: ee85 7b04 vdiv.f64 d7, d5, d4
- 8000746: ee36 7b07 vadd.f64 d7, d6, d7
- 800074a: eef7 7bc7 vcvt.f32.f64 s15, d7
- 800074e: 68fb ldr r3, [r7, #12]
- 8000750: edc3 7a01 vstr s15, [r3, #4]
- }
- 8000754: bf00 nop
- 8000756: 3714 adds r7, #20
- 8000758: 46bd mov sp, r7
- 800075a: f85d 7b04 ldr.w r7, [sp], #4
- 800075e: 4770 bx lr
- 8000760: 33333333 .word 0x33333333
- 8000764: 3fd33333 .word 0x3fd33333
-
-08000768 <_ZN8Odometry15GetLeftVelocityEv>:
-
- float GetLeftVelocity(){
- 8000768: b480 push {r7}
- 800076a: b083 sub sp, #12
- 800076c: af00 add r7, sp, #0
- 800076e: 6078 str r0, [r7, #4]
- return left_velocity_;
- 8000770: 687b ldr r3, [r7, #4]
- 8000772: 681b ldr r3, [r3, #0]
- 8000774: ee07 3a90 vmov s15, r3
- }
- 8000778: eeb0 0a67 vmov.f32 s0, s15
- 800077c: 370c adds r7, #12
- 800077e: 46bd mov sp, r7
- 8000780: f85d 7b04 ldr.w r7, [sp], #4
- 8000784: 4770 bx lr
-
-08000786 <_ZN8Odometry16GetRightVelocityEv>:
- float GetRightVelocity(){
- 8000786: b480 push {r7}
- 8000788: b083 sub sp, #12
- 800078a: af00 add r7, sp, #0
- 800078c: 6078 str r0, [r7, #4]
- return right_velocity_;
- 800078e: 687b ldr r3, [r7, #4]
- 8000790: 685b ldr r3, [r3, #4]
- 8000792: ee07 3a90 vmov s15, r3
- }
- 8000796: eeb0 0a67 vmov.f32 s0, s15
- 800079a: 370c adds r7, #12
- 800079c: 46bd mov sp, r7
- 800079e: f85d 7b04 ldr.w r7, [sp], #4
- 80007a2: 4770 bx lr
-
-080007a4 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>:
- GPIO_TypeDef *dir_gpio_port_;
- uint16_t dir_pin_;
- TIM_HandleTypeDef *pwm_timer_;
- uint32_t pwm_channel_;
-
- MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin,
- 80007a4: b480 push {r7}
- 80007a6: b085 sub sp, #20
- 80007a8: af00 add r7, sp, #0
- 80007aa: 60f8 str r0, [r7, #12]
- 80007ac: 60b9 str r1, [r7, #8]
- 80007ae: 603b str r3, [r7, #0]
- 80007b0: 4613 mov r3, r2
- 80007b2: 80fb strh r3, [r7, #6]
- GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin,
- TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) {
- this->sleep_gpio_port_ = sleep_gpio_port;
- 80007b4: 68fb ldr r3, [r7, #12]
- 80007b6: 68ba ldr r2, [r7, #8]
- 80007b8: 601a str r2, [r3, #0]
- this->sleep_pin_ = sleep_pin;
- 80007ba: 68fb ldr r3, [r7, #12]
- 80007bc: 88fa ldrh r2, [r7, #6]
- 80007be: 809a strh r2, [r3, #4]
- this->dir_gpio_port_ = dir_gpio_port;
- 80007c0: 68fb ldr r3, [r7, #12]
- 80007c2: 683a ldr r2, [r7, #0]
- 80007c4: 609a str r2, [r3, #8]
- this->dir_pin_ = dir_pin;
- 80007c6: 68fb ldr r3, [r7, #12]
- 80007c8: 8b3a ldrh r2, [r7, #24]
- 80007ca: 819a strh r2, [r3, #12]
- this->pwm_timer_ = pwm_timer;
- 80007cc: 68fb ldr r3, [r7, #12]
- 80007ce: 69fa ldr r2, [r7, #28]
- 80007d0: 611a str r2, [r3, #16]
- this->pwm_channel_ = pwm_channel;
- 80007d2: 68fb ldr r3, [r7, #12]
- 80007d4: 6a3a ldr r2, [r7, #32]
- 80007d6: 615a str r2, [r3, #20]
- }
- 80007d8: 68fb ldr r3, [r7, #12]
- 80007da: 4618 mov r0, r3
- 80007dc: 3714 adds r7, #20
- 80007de: 46bd mov sp, r7
- 80007e0: f85d 7b04 ldr.w r7, [sp], #4
- 80007e4: 4770 bx lr
-
-080007e6 <_ZN15MotorController5setupEv>:
-
- void setup() {
- 80007e6: b580 push {r7, lr}
- 80007e8: b082 sub sp, #8
- 80007ea: af00 add r7, sp, #0
- 80007ec: 6078 str r0, [r7, #4]
- HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_);
- 80007ee: 687b ldr r3, [r7, #4]
- 80007f0: 691a ldr r2, [r3, #16]
- 80007f2: 687b ldr r3, [r7, #4]
- 80007f4: 695b ldr r3, [r3, #20]
- 80007f6: 4619 mov r1, r3
- 80007f8: 4610 mov r0, r2
- 80007fa: f002 fdd9 bl 80033b0 <HAL_TIM_PWM_Start>
- }
- 80007fe: bf00 nop
- 8000800: 3708 adds r7, #8
- 8000802: 46bd mov sp, r7
- 8000804: bd80 pop {r7, pc}
- ...
-
-08000808 <_ZN15MotorController9set_speedEi>:
-
- void set_speed(int duty_cycle) {
- 8000808: b580 push {r7, lr}
- 800080a: b082 sub sp, #8
- 800080c: af00 add r7, sp, #0
- 800080e: 6078 str r0, [r7, #4]
- 8000810: 6039 str r1, [r7, #0]
- if (duty_cycle >= 0) {
- 8000812: 683b ldr r3, [r7, #0]
- 8000814: 2b00 cmp r3, #0
- 8000816: f2c0 8083 blt.w 8000920 <_ZN15MotorController9set_speedEi+0x118>
- //set direction to forward
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
- 800081a: 687b ldr r3, [r7, #4]
- 800081c: 6898 ldr r0, [r3, #8]
- 800081e: 687b ldr r3, [r7, #4]
- 8000820: 899b ldrh r3, [r3, #12]
- 8000822: 2201 movs r2, #1
- 8000824: 4619 mov r1, r3
- 8000826: f001 fc9f bl 8002168 <HAL_GPIO_WritePin>
-
- //check if duty_cycle exceeds maximum
- if (duty_cycle > MAX_DUTY_CYCLE)
- 800082a: 683b ldr r3, [r7, #0]
- 800082c: f240 3216 movw r2, #790 ; 0x316
- 8000830: 4293 cmp r3, r2
- 8000832: dd3d ble.n 80008b0 <_ZN15MotorController9set_speedEi+0xa8>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 8000834: 687b ldr r3, [r7, #4]
- 8000836: 695b ldr r3, [r3, #20]
- 8000838: 2b00 cmp r3, #0
- 800083a: d106 bne.n 800084a <_ZN15MotorController9set_speedEi+0x42>
- 800083c: 687b ldr r3, [r7, #4]
- 800083e: 691b ldr r3, [r3, #16]
- 8000840: 681b ldr r3, [r3, #0]
- 8000842: f240 3216 movw r2, #790 ; 0x316
- 8000846: 635a str r2, [r3, #52] ; 0x34
- 8000848: e0f5 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 800084a: 687b ldr r3, [r7, #4]
- 800084c: 695b ldr r3, [r3, #20]
- 800084e: 2b04 cmp r3, #4
- 8000850: d106 bne.n 8000860 <_ZN15MotorController9set_speedEi+0x58>
- 8000852: 687b ldr r3, [r7, #4]
- 8000854: 691b ldr r3, [r3, #16]
- 8000856: 681b ldr r3, [r3, #0]
- 8000858: f240 3216 movw r2, #790 ; 0x316
- 800085c: 639a str r2, [r3, #56] ; 0x38
- 800085e: e0ea b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000860: 687b ldr r3, [r7, #4]
- 8000862: 695b ldr r3, [r3, #20]
- 8000864: 2b08 cmp r3, #8
- 8000866: d106 bne.n 8000876 <_ZN15MotorController9set_speedEi+0x6e>
- 8000868: 687b ldr r3, [r7, #4]
- 800086a: 691b ldr r3, [r3, #16]
- 800086c: 681b ldr r3, [r3, #0]
- 800086e: f240 3216 movw r2, #790 ; 0x316
- 8000872: 63da str r2, [r3, #60] ; 0x3c
- 8000874: e0df b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000876: 687b ldr r3, [r7, #4]
- 8000878: 695b ldr r3, [r3, #20]
- 800087a: 2b0c cmp r3, #12
- 800087c: d106 bne.n 800088c <_ZN15MotorController9set_speedEi+0x84>
- 800087e: 687b ldr r3, [r7, #4]
- 8000880: 691b ldr r3, [r3, #16]
- 8000882: 681b ldr r3, [r3, #0]
- 8000884: f240 3216 movw r2, #790 ; 0x316
- 8000888: 641a str r2, [r3, #64] ; 0x40
- 800088a: e0d4 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 800088c: 687b ldr r3, [r7, #4]
- 800088e: 695b ldr r3, [r3, #20]
- 8000890: 2b10 cmp r3, #16
- 8000892: d106 bne.n 80008a2 <_ZN15MotorController9set_speedEi+0x9a>
- 8000894: 687b ldr r3, [r7, #4]
- 8000896: 691b ldr r3, [r3, #16]
- 8000898: 681b ldr r3, [r3, #0]
- 800089a: f240 3216 movw r2, #790 ; 0x316
- 800089e: 659a str r2, [r3, #88] ; 0x58
- 80008a0: e0c9 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008a2: 687b ldr r3, [r7, #4]
- 80008a4: 691b ldr r3, [r3, #16]
- 80008a6: 681b ldr r3, [r3, #0]
- 80008a8: f240 3216 movw r2, #790 ; 0x316
- 80008ac: 65da str r2, [r3, #92] ; 0x5c
- 80008ae: e0c2 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- else
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 80008b0: 687b ldr r3, [r7, #4]
- 80008b2: 695b ldr r3, [r3, #20]
- 80008b4: 2b00 cmp r3, #0
- 80008b6: d105 bne.n 80008c4 <_ZN15MotorController9set_speedEi+0xbc>
- 80008b8: 683a ldr r2, [r7, #0]
- 80008ba: 687b ldr r3, [r7, #4]
- 80008bc: 691b ldr r3, [r3, #16]
- 80008be: 681b ldr r3, [r3, #0]
- 80008c0: 635a str r2, [r3, #52] ; 0x34
- 80008c2: e0b8 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008c4: 687b ldr r3, [r7, #4]
- 80008c6: 695b ldr r3, [r3, #20]
- 80008c8: 2b04 cmp r3, #4
- 80008ca: d105 bne.n 80008d8 <_ZN15MotorController9set_speedEi+0xd0>
- 80008cc: 683a ldr r2, [r7, #0]
- 80008ce: 687b ldr r3, [r7, #4]
- 80008d0: 691b ldr r3, [r3, #16]
- 80008d2: 681b ldr r3, [r3, #0]
- 80008d4: 639a str r2, [r3, #56] ; 0x38
- 80008d6: e0ae b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008d8: 687b ldr r3, [r7, #4]
- 80008da: 695b ldr r3, [r3, #20]
- 80008dc: 2b08 cmp r3, #8
- 80008de: d105 bne.n 80008ec <_ZN15MotorController9set_speedEi+0xe4>
- 80008e0: 683a ldr r2, [r7, #0]
- 80008e2: 687b ldr r3, [r7, #4]
- 80008e4: 691b ldr r3, [r3, #16]
- 80008e6: 681b ldr r3, [r3, #0]
- 80008e8: 63da str r2, [r3, #60] ; 0x3c
- 80008ea: e0a4 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008ec: 687b ldr r3, [r7, #4]
- 80008ee: 695b ldr r3, [r3, #20]
- 80008f0: 2b0c cmp r3, #12
- 80008f2: d105 bne.n 8000900 <_ZN15MotorController9set_speedEi+0xf8>
- 80008f4: 683a ldr r2, [r7, #0]
- 80008f6: 687b ldr r3, [r7, #4]
- 80008f8: 691b ldr r3, [r3, #16]
- 80008fa: 681b ldr r3, [r3, #0]
- 80008fc: 641a str r2, [r3, #64] ; 0x40
- 80008fe: e09a b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000900: 687b ldr r3, [r7, #4]
- 8000902: 695b ldr r3, [r3, #20]
- 8000904: 2b10 cmp r3, #16
- 8000906: d105 bne.n 8000914 <_ZN15MotorController9set_speedEi+0x10c>
- 8000908: 683a ldr r2, [r7, #0]
- 800090a: 687b ldr r3, [r7, #4]
- 800090c: 691b ldr r3, [r3, #16]
- 800090e: 681b ldr r3, [r3, #0]
- 8000910: 659a str r2, [r3, #88] ; 0x58
- 8000912: e090 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000914: 683a ldr r2, [r7, #0]
- 8000916: 687b ldr r3, [r7, #4]
- 8000918: 691b ldr r3, [r3, #16]
- 800091a: 681b ldr r3, [r3, #0]
- 800091c: 65da str r2, [r3, #92] ; 0x5c
- 800091e: e08a b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
-
- } else if (duty_cycle < 0){
- 8000920: 683b ldr r3, [r7, #0]
- 8000922: 2b00 cmp r3, #0
- 8000924: f280 8087 bge.w 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- //set direction to backwards
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET);
- 8000928: 687b ldr r3, [r7, #4]
- 800092a: 6898 ldr r0, [r3, #8]
- 800092c: 687b ldr r3, [r7, #4]
- 800092e: 899b ldrh r3, [r3, #12]
- 8000930: 2200 movs r2, #0
- 8000932: 4619 mov r1, r3
- 8000934: f001 fc18 bl 8002168 <HAL_GPIO_WritePin>
-
- //check if duty_cycle is lower than minimum
- if (duty_cycle < -MAX_DUTY_CYCLE)
- 8000938: 683b ldr r3, [r7, #0]
- 800093a: 4a45 ldr r2, [pc, #276] ; (8000a50 <_ZN15MotorController9set_speedEi+0x248>)
- 800093c: 4293 cmp r3, r2
- 800093e: da3d bge.n 80009bc <_ZN15MotorController9set_speedEi+0x1b4>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 8000940: 687b ldr r3, [r7, #4]
- 8000942: 695b ldr r3, [r3, #20]
- 8000944: 2b00 cmp r3, #0
- 8000946: d106 bne.n 8000956 <_ZN15MotorController9set_speedEi+0x14e>
- 8000948: 687b ldr r3, [r7, #4]
- 800094a: 691b ldr r3, [r3, #16]
- 800094c: 681b ldr r3, [r3, #0]
- 800094e: f240 3216 movw r2, #790 ; 0x316
- 8000952: 635a str r2, [r3, #52] ; 0x34
- 8000954: e06f b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000956: 687b ldr r3, [r7, #4]
- 8000958: 695b ldr r3, [r3, #20]
- 800095a: 2b04 cmp r3, #4
- 800095c: d106 bne.n 800096c <_ZN15MotorController9set_speedEi+0x164>
- 800095e: 687b ldr r3, [r7, #4]
- 8000960: 691b ldr r3, [r3, #16]
- 8000962: 681b ldr r3, [r3, #0]
- 8000964: f240 3216 movw r2, #790 ; 0x316
- 8000968: 639a str r2, [r3, #56] ; 0x38
- 800096a: e064 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 800096c: 687b ldr r3, [r7, #4]
- 800096e: 695b ldr r3, [r3, #20]
- 8000970: 2b08 cmp r3, #8
- 8000972: d106 bne.n 8000982 <_ZN15MotorController9set_speedEi+0x17a>
- 8000974: 687b ldr r3, [r7, #4]
- 8000976: 691b ldr r3, [r3, #16]
- 8000978: 681b ldr r3, [r3, #0]
- 800097a: f240 3216 movw r2, #790 ; 0x316
- 800097e: 63da str r2, [r3, #60] ; 0x3c
- 8000980: e059 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000982: 687b ldr r3, [r7, #4]
- 8000984: 695b ldr r3, [r3, #20]
- 8000986: 2b0c cmp r3, #12
- 8000988: d106 bne.n 8000998 <_ZN15MotorController9set_speedEi+0x190>
- 800098a: 687b ldr r3, [r7, #4]
- 800098c: 691b ldr r3, [r3, #16]
- 800098e: 681b ldr r3, [r3, #0]
- 8000990: f240 3216 movw r2, #790 ; 0x316
- 8000994: 641a str r2, [r3, #64] ; 0x40
- 8000996: e04e b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000998: 687b ldr r3, [r7, #4]
- 800099a: 695b ldr r3, [r3, #20]
- 800099c: 2b10 cmp r3, #16
- 800099e: d106 bne.n 80009ae <_ZN15MotorController9set_speedEi+0x1a6>
- 80009a0: 687b ldr r3, [r7, #4]
- 80009a2: 691b ldr r3, [r3, #16]
- 80009a4: 681b ldr r3, [r3, #0]
- 80009a6: f240 3216 movw r2, #790 ; 0x316
- 80009aa: 659a str r2, [r3, #88] ; 0x58
- 80009ac: e043 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009ae: 687b ldr r3, [r7, #4]
- 80009b0: 691b ldr r3, [r3, #16]
- 80009b2: 681b ldr r3, [r3, #0]
- 80009b4: f240 3216 movw r2, #790 ; 0x316
- 80009b8: 65da str r2, [r3, #92] ; 0x5c
- 80009ba: e03c b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- else
- //invert sign to make duty_cycle positive
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 80009bc: 687b ldr r3, [r7, #4]
- 80009be: 695b ldr r3, [r3, #20]
- 80009c0: 2b00 cmp r3, #0
- 80009c2: d106 bne.n 80009d2 <_ZN15MotorController9set_speedEi+0x1ca>
- 80009c4: 683b ldr r3, [r7, #0]
- 80009c6: 425a negs r2, r3
- 80009c8: 687b ldr r3, [r7, #4]
- 80009ca: 691b ldr r3, [r3, #16]
- 80009cc: 681b ldr r3, [r3, #0]
- 80009ce: 635a str r2, [r3, #52] ; 0x34
- 80009d0: e031 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009d2: 687b ldr r3, [r7, #4]
- 80009d4: 695b ldr r3, [r3, #20]
- 80009d6: 2b04 cmp r3, #4
- 80009d8: d106 bne.n 80009e8 <_ZN15MotorController9set_speedEi+0x1e0>
- 80009da: 683b ldr r3, [r7, #0]
- 80009dc: 425a negs r2, r3
- 80009de: 687b ldr r3, [r7, #4]
- 80009e0: 691b ldr r3, [r3, #16]
- 80009e2: 681b ldr r3, [r3, #0]
- 80009e4: 639a str r2, [r3, #56] ; 0x38
- 80009e6: e026 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009e8: 687b ldr r3, [r7, #4]
- 80009ea: 695b ldr r3, [r3, #20]
- 80009ec: 2b08 cmp r3, #8
- 80009ee: d106 bne.n 80009fe <_ZN15MotorController9set_speedEi+0x1f6>
- 80009f0: 683b ldr r3, [r7, #0]
- 80009f2: 425a negs r2, r3
- 80009f4: 687b ldr r3, [r7, #4]
- 80009f6: 691b ldr r3, [r3, #16]
- 80009f8: 681b ldr r3, [r3, #0]
- 80009fa: 63da str r2, [r3, #60] ; 0x3c
- 80009fc: e01b b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009fe: 687b ldr r3, [r7, #4]
- 8000a00: 695b ldr r3, [r3, #20]
- 8000a02: 2b0c cmp r3, #12
- 8000a04: d106 bne.n 8000a14 <_ZN15MotorController9set_speedEi+0x20c>
- 8000a06: 683b ldr r3, [r7, #0]
- 8000a08: 425a negs r2, r3
- 8000a0a: 687b ldr r3, [r7, #4]
- 8000a0c: 691b ldr r3, [r3, #16]
- 8000a0e: 681b ldr r3, [r3, #0]
- 8000a10: 641a str r2, [r3, #64] ; 0x40
- 8000a12: e010 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000a14: 687b ldr r3, [r7, #4]
- 8000a16: 695b ldr r3, [r3, #20]
- 8000a18: 2b10 cmp r3, #16
- 8000a1a: d106 bne.n 8000a2a <_ZN15MotorController9set_speedEi+0x222>
- 8000a1c: 683b ldr r3, [r7, #0]
- 8000a1e: 425a negs r2, r3
- 8000a20: 687b ldr r3, [r7, #4]
- 8000a22: 691b ldr r3, [r3, #16]
- 8000a24: 681b ldr r3, [r3, #0]
- 8000a26: 659a str r2, [r3, #88] ; 0x58
- 8000a28: e005 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000a2a: 683b ldr r3, [r7, #0]
- 8000a2c: 425a negs r2, r3
- 8000a2e: 687b ldr r3, [r7, #4]
- 8000a30: 691b ldr r3, [r3, #16]
- 8000a32: 681b ldr r3, [r3, #0]
- 8000a34: 65da str r2, [r3, #92] ; 0x5c
- }
-
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- 8000a36: 687b ldr r3, [r7, #4]
- 8000a38: 6818 ldr r0, [r3, #0]
- 8000a3a: 687b ldr r3, [r7, #4]
- 8000a3c: 889b ldrh r3, [r3, #4]
- 8000a3e: 2201 movs r2, #1
- 8000a40: 4619 mov r1, r3
- 8000a42: f001 fb91 bl 8002168 <HAL_GPIO_WritePin>
-
- }
- 8000a46: bf00 nop
- 8000a48: 3708 adds r7, #8
- 8000a4a: 46bd mov sp, r7
- 8000a4c: bd80 pop {r7, pc}
- 8000a4e: bf00 nop
- 8000a50: fffffcea .word 0xfffffcea
-
-08000a54 <_ZN15MotorController5coastEv>:
- void brake() {
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- }
-
- void coast() {
- 8000a54: b580 push {r7, lr}
- 8000a56: b082 sub sp, #8
- 8000a58: af00 add r7, sp, #0
- 8000a5a: 6078 str r0, [r7, #4]
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET);
- 8000a5c: 687b ldr r3, [r7, #4]
- 8000a5e: 6818 ldr r0, [r3, #0]
- 8000a60: 687b ldr r3, [r7, #4]
- 8000a62: 889b ldrh r3, [r3, #4]
- 8000a64: 2200 movs r2, #0
- 8000a66: 4619 mov r1, r3
- 8000a68: f001 fb7e bl 8002168 <HAL_GPIO_WritePin>
- }
- 8000a6c: bf00 nop
- 8000a6e: 3708 adds r7, #8
- 8000a70: 46bd mov sp, r7
- 8000a72: bd80 pop {r7, pc}
-
-08000a74 <_ZN3PidC1Efff>:
- float previous_error_;
-
- int min_;
- int max_;
-
- Pid(float kp, float ki, float kd) {
- 8000a74: b480 push {r7}
- 8000a76: b085 sub sp, #20
- 8000a78: af00 add r7, sp, #0
- 8000a7a: 60f8 str r0, [r7, #12]
- 8000a7c: ed87 0a02 vstr s0, [r7, #8]
- 8000a80: edc7 0a01 vstr s1, [r7, #4]
- 8000a84: ed87 1a00 vstr s2, [r7]
- this->kp_ = kp;
- 8000a88: 68fb ldr r3, [r7, #12]
- 8000a8a: 68ba ldr r2, [r7, #8]
- 8000a8c: 601a str r2, [r3, #0]
- this->ki_ = ki;
- 8000a8e: 68fb ldr r3, [r7, #12]
- 8000a90: 687a ldr r2, [r7, #4]
- 8000a92: 605a str r2, [r3, #4]
- this->kd_ = kd;
- 8000a94: 68fb ldr r3, [r7, #12]
- 8000a96: 683a ldr r2, [r7, #0]
- 8000a98: 609a str r2, [r3, #8]
-
- this->error_ = 0;
- 8000a9a: 68fb ldr r3, [r7, #12]
- 8000a9c: f04f 0200 mov.w r2, #0
- 8000aa0: 60da str r2, [r3, #12]
- this->setpoint_ = 0;
- 8000aa2: 68fb ldr r3, [r7, #12]
- 8000aa4: f04f 0200 mov.w r2, #0
- 8000aa8: 611a str r2, [r3, #16]
-
- this->previous_error_ = 0;
- 8000aaa: 68fb ldr r3, [r7, #12]
- 8000aac: f04f 0200 mov.w r2, #0
- 8000ab0: 619a str r2, [r3, #24]
- this->error_sum_ = 0;
- 8000ab2: 68fb ldr r3, [r7, #12]
- 8000ab4: f04f 0200 mov.w r2, #0
- 8000ab8: 615a str r2, [r3, #20]
-
- this->min_ = -MAX_DUTY_CYCLE;
- 8000aba: 68fb ldr r3, [r7, #12]
- 8000abc: 4a06 ldr r2, [pc, #24] ; (8000ad8 <_ZN3PidC1Efff+0x64>)
- 8000abe: 61da str r2, [r3, #28]
- this->max_ = MAX_DUTY_CYCLE;
- 8000ac0: 68fb ldr r3, [r7, #12]
- 8000ac2: f240 3216 movw r2, #790 ; 0x316
- 8000ac6: 621a str r2, [r3, #32]
-
- }
- 8000ac8: 68fb ldr r3, [r7, #12]
- 8000aca: 4618 mov r0, r3
- 8000acc: 3714 adds r7, #20
- 8000ace: 46bd mov sp, r7
- 8000ad0: f85d 7b04 ldr.w r7, [sp], #4
- 8000ad4: 4770 bx lr
- 8000ad6: bf00 nop
- 8000ad8: fffffcea .word 0xfffffcea
-
-08000adc <_ZN3Pid3setEf>:
- this->previous_error_ = 0;
- this->error_sum_ = 0;
-
- }
-
- void set(float setpoint) {
- 8000adc: b480 push {r7}
- 8000ade: b083 sub sp, #12
- 8000ae0: af00 add r7, sp, #0
- 8000ae2: 6078 str r0, [r7, #4]
- 8000ae4: ed87 0a00 vstr s0, [r7]
- this->setpoint_ = setpoint;
- 8000ae8: 687b ldr r3, [r7, #4]
- 8000aea: 683a ldr r2, [r7, #0]
- 8000aec: 611a str r2, [r3, #16]
- }
- 8000aee: bf00 nop
- 8000af0: 370c adds r7, #12
- 8000af2: 46bd mov sp, r7
- 8000af4: f85d 7b04 ldr.w r7, [sp], #4
- 8000af8: 4770 bx lr
-
-08000afa <_ZN3Pid6updateEf>:
-
- int update(float measure) {
- 8000afa: b480 push {r7}
- 8000afc: b085 sub sp, #20
- 8000afe: af00 add r7, sp, #0
- 8000b00: 6078 str r0, [r7, #4]
- 8000b02: ed87 0a00 vstr s0, [r7]
-
- this->error_ = this->setpoint_ - measure;
- 8000b06: 687b ldr r3, [r7, #4]
- 8000b08: ed93 7a04 vldr s14, [r3, #16]
- 8000b0c: edd7 7a00 vldr s15, [r7]
- 8000b10: ee77 7a67 vsub.f32 s15, s14, s15
- 8000b14: 687b ldr r3, [r7, #4]
- 8000b16: edc3 7a03 vstr s15, [r3, #12]
-
- //proportional term
- float output = this->error_ * this->kp_;
- 8000b1a: 687b ldr r3, [r7, #4]
- 8000b1c: ed93 7a03 vldr s14, [r3, #12]
- 8000b20: 687b ldr r3, [r7, #4]
- 8000b22: edd3 7a00 vldr s15, [r3]
- 8000b26: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b2a: edc7 7a03 vstr s15, [r7, #12]
-
- //integral term without windup
- error_sum_ += this->error_;
- 8000b2e: 687b ldr r3, [r7, #4]
- 8000b30: ed93 7a05 vldr s14, [r3, #20]
- 8000b34: 687b ldr r3, [r7, #4]
- 8000b36: edd3 7a03 vldr s15, [r3, #12]
- 8000b3a: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b3e: 687b ldr r3, [r7, #4]
- 8000b40: edc3 7a05 vstr s15, [r3, #20]
- output += error_sum_ * this->ki_;
- 8000b44: 687b ldr r3, [r7, #4]
- 8000b46: ed93 7a05 vldr s14, [r3, #20]
- 8000b4a: 687b ldr r3, [r7, #4]
- 8000b4c: edd3 7a01 vldr s15, [r3, #4]
- 8000b50: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b54: ed97 7a03 vldr s14, [r7, #12]
- 8000b58: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b5c: edc7 7a03 vstr s15, [r7, #12]
-
- //derivative term
- output += (this->error_ - this->previous_error_) * kd_;
- 8000b60: 687b ldr r3, [r7, #4]
- 8000b62: ed93 7a03 vldr s14, [r3, #12]
- 8000b66: 687b ldr r3, [r7, #4]
- 8000b68: edd3 7a06 vldr s15, [r3, #24]
- 8000b6c: ee37 7a67 vsub.f32 s14, s14, s15
- 8000b70: 687b ldr r3, [r7, #4]
- 8000b72: edd3 7a02 vldr s15, [r3, #8]
- 8000b76: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b7a: ed97 7a03 vldr s14, [r7, #12]
- 8000b7e: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b82: edc7 7a03 vstr s15, [r7, #12]
- this->previous_error_ = this->error_;
- 8000b86: 687b ldr r3, [r7, #4]
- 8000b88: 68da ldr r2, [r3, #12]
- 8000b8a: 687b ldr r3, [r7, #4]
- 8000b8c: 619a str r2, [r3, #24]
-
- int integer_output = static_cast<int> (output);
- 8000b8e: edd7 7a03 vldr s15, [r7, #12]
- 8000b92: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8000b96: ee17 3a90 vmov r3, s15
- 8000b9a: 60bb str r3, [r7, #8]
-// if(integer_output > this->max_)
-// integer_output = this->max_;
-// else if (integer_output < this->min_)
-// integer_output = this->min_;
-
- return integer_output;
- 8000b9c: 68bb ldr r3, [r7, #8]
-
- }
- 8000b9e: 4618 mov r0, r3
- 8000ba0: 3714 adds r7, #20
- 8000ba2: 46bd mov sp, r7
- 8000ba4: f85d 7b04 ldr.w r7, [sp], #4
- 8000ba8: 4770 bx lr
- ...
-
-08000bac <main>:
-
-/**
- * @brief The application entry point.
- * @retval int
- */
-int main(void) {
- 8000bac: b580 push {r7, lr}
- 8000bae: af00 add r7, sp, #0
- /* USER CODE END 1 */
-
- /* MCU Configuration--------------------------------------------------------*/
-
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
- 8000bb0: f000 ff9f bl 8001af2 <HAL_Init>
- /* USER CODE BEGIN Init */
-
- /* USER CODE END Init */
-
- /* Configure the system clock */
- SystemClock_Config();
- 8000bb4: f000 f848 bl 8000c48 <_Z18SystemClock_Configv>
- /* USER CODE BEGIN SysInit */
-
- /* USER CODE END SysInit */
-
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- 8000bb8: f000 fb20 bl 80011fc <_ZL12MX_GPIO_Initv>
- MX_TIM2_Init();
- 8000bbc: f000 f8ea bl 8000d94 <_ZL12MX_TIM2_Initv>
- MX_TIM3_Init();
- 8000bc0: f000 f946 bl 8000e50 <_ZL12MX_TIM3_Initv>
- MX_TIM4_Init();
- 8000bc4: f000 f9a2 bl 8000f0c <_ZL12MX_TIM4_Initv>
- MX_TIM5_Init();
- 8000bc8: f000 fa40 bl 800104c <_ZL12MX_TIM5_Initv>
- MX_USART6_UART_Init();
- 8000bcc: f000 fae0 bl 8001190 <_ZL19MX_USART6_UART_Initv>
- MX_TIM6_Init();
- 8000bd0: f000 fa9c bl 800110c <_ZL12MX_TIM6_Initv>
-
- /* Initialize interrupts */
- MX_NVIC_Init();
- 8000bd4: f000 f8c2 bl 8000d5c <_ZL12MX_NVIC_Initv>
- /* USER CODE BEGIN 2 */
-
- left_encoder.Setup();
- 8000bd8: 4811 ldr r0, [pc, #68] ; (8000c20 <main+0x74>)
- 8000bda: f7ff fce7 bl 80005ac <_ZN7Encoder5SetupEv>
- right_encoder.Setup();
- 8000bde: 4811 ldr r0, [pc, #68] ; (8000c24 <main+0x78>)
- 8000be0: f7ff fce4 bl 80005ac <_ZN7Encoder5SetupEv>
-
- left_motor.setup();
- 8000be4: 4810 ldr r0, [pc, #64] ; (8000c28 <main+0x7c>)
- 8000be6: f7ff fdfe bl 80007e6 <_ZN15MotorController5setupEv>
- right_motor.setup();
- 8000bea: 4810 ldr r0, [pc, #64] ; (8000c2c <main+0x80>)
- 8000bec: f7ff fdfb bl 80007e6 <_ZN15MotorController5setupEv>
- left_motor.coast();
- 8000bf0: 480d ldr r0, [pc, #52] ; (8000c28 <main+0x7c>)
- 8000bf2: f7ff ff2f bl 8000a54 <_ZN15MotorController5coastEv>
- right_motor.coast();
- 8000bf6: 480d ldr r0, [pc, #52] ; (8000c2c <main+0x80>)
- 8000bf8: f7ff ff2c bl 8000a54 <_ZN15MotorController5coastEv>
-
- tx_buffer = (uint8_t*) &odom_msg;
- 8000bfc: 4b0c ldr r3, [pc, #48] ; (8000c30 <main+0x84>)
- 8000bfe: 4a0d ldr r2, [pc, #52] ; (8000c34 <main+0x88>)
- 8000c00: 601a str r2, [r3, #0]
- rx_buffer = (uint8_t*) &vel_msg;
- 8000c02: 4b0d ldr r3, [pc, #52] ; (8000c38 <main+0x8c>)
- 8000c04: 4a0d ldr r2, [pc, #52] ; (8000c3c <main+0x90>)
- 8000c06: 601a str r2, [r3, #0]
-
- //Enables UART RX interrupt
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
- 8000c08: 4b0b ldr r3, [pc, #44] ; (8000c38 <main+0x8c>)
- 8000c0a: 681b ldr r3, [r3, #0]
- 8000c0c: 2208 movs r2, #8
- 8000c0e: 4619 mov r1, r3
- 8000c10: 480b ldr r0, [pc, #44] ; (8000c40 <main+0x94>)
- 8000c12: f003 fd0b bl 800462c <HAL_UART_Receive_IT>
-
- //Enables TIM6 interrupt (used for periodic transmission)
- HAL_TIM_Base_Start_IT(&htim6);
- 8000c16: 480b ldr r0, [pc, #44] ; (8000c44 <main+0x98>)
- 8000c18: f002 fb6a bl 80032f0 <HAL_TIM_Base_Start_IT>
-
- /* USER CODE END 2 */
-
- /* Infinite loop */
- /* USER CODE BEGIN WHILE */
- while (1) {
- 8000c1c: e7fe b.n 8000c1c <main+0x70>
- 8000c1e: bf00 nop
- 8000c20: 20000200 .word 0x20000200
- 8000c24: 200001e8 .word 0x200001e8
- 8000c28: 2000029c .word 0x2000029c
- 8000c2c: 200002b4 .word 0x200002b4
- 8000c30: 200002cc .word 0x200002cc
- 8000c34: 200002d4 .word 0x200002d4
- 8000c38: 200002d0 .word 0x200002d0
- 8000c3c: 200002e0 .word 0x200002e0
- 8000c40: 20000168 .word 0x20000168
- 8000c44: 20000128 .word 0x20000128
-
-08000c48 <_Z18SystemClock_Configv>:
-
-/**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void) {
- 8000c48: b580 push {r7, lr}
- 8000c4a: b0b8 sub sp, #224 ; 0xe0
- 8000c4c: af00 add r7, sp, #0
- RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
- 8000c4e: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000c52: 2234 movs r2, #52 ; 0x34
- 8000c54: 2100 movs r1, #0
- 8000c56: 4618 mov r0, r3
- 8000c58: f004 fb90 bl 800537c <memset>
- RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
- 8000c5c: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000c60: 2200 movs r2, #0
- 8000c62: 601a str r2, [r3, #0]
- 8000c64: 605a str r2, [r3, #4]
- 8000c66: 609a str r2, [r3, #8]
- 8000c68: 60da str r2, [r3, #12]
- 8000c6a: 611a str r2, [r3, #16]
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
- 8000c6c: f107 0308 add.w r3, r7, #8
- 8000c70: 2290 movs r2, #144 ; 0x90
- 8000c72: 2100 movs r1, #0
- 8000c74: 4618 mov r0, r3
- 8000c76: f004 fb81 bl 800537c <memset>
-
- /** Configure the main internal regulator output voltage
- */
- __HAL_RCC_PWR_CLK_ENABLE();
- 8000c7a: 4b36 ldr r3, [pc, #216] ; (8000d54 <_Z18SystemClock_Configv+0x10c>)
- 8000c7c: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000c7e: 4a35 ldr r2, [pc, #212] ; (8000d54 <_Z18SystemClock_Configv+0x10c>)
- 8000c80: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8000c84: 6413 str r3, [r2, #64] ; 0x40
- 8000c86: 4b33 ldr r3, [pc, #204] ; (8000d54 <_Z18SystemClock_Configv+0x10c>)
- 8000c88: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000c8a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000c8e: 607b str r3, [r7, #4]
- 8000c90: 687b ldr r3, [r7, #4]
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 8000c92: 4b31 ldr r3, [pc, #196] ; (8000d58 <_Z18SystemClock_Configv+0x110>)
- 8000c94: 681b ldr r3, [r3, #0]
- 8000c96: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 8000c9a: 4a2f ldr r2, [pc, #188] ; (8000d58 <_Z18SystemClock_Configv+0x110>)
- 8000c9c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000ca0: 6013 str r3, [r2, #0]
- 8000ca2: 4b2d ldr r3, [pc, #180] ; (8000d58 <_Z18SystemClock_Configv+0x110>)
- 8000ca4: 681b ldr r3, [r3, #0]
- 8000ca6: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8000caa: 603b str r3, [r7, #0]
- 8000cac: 683b ldr r3, [r7, #0]
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8000cae: 2302 movs r3, #2
- 8000cb0: f8c7 30ac str.w r3, [r7, #172] ; 0xac
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000cb4: 2301 movs r3, #1
- 8000cb6: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000cba: 2310 movs r3, #16
- 8000cbc: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8000cc0: 2300 movs r3, #0
- 8000cc2: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- 8000cc6: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000cca: 4618 mov r0, r3
- 8000ccc: f001 fa7e bl 80021cc <HAL_RCC_OscConfig>
- 8000cd0: 4603 mov r3, r0
- 8000cd2: 2b00 cmp r3, #0
- 8000cd4: bf14 ite ne
- 8000cd6: 2301 movne r3, #1
- 8000cd8: 2300 moveq r3, #0
- 8000cda: b2db uxtb r3, r3
- 8000cdc: 2b00 cmp r3, #0
- 8000cde: d001 beq.n 8000ce4 <_Z18SystemClock_Configv+0x9c>
- Error_Handler();
- 8000ce0: f000 fc4e bl 8001580 <Error_Handler>
- }
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
- 8000ce4: 230f movs r3, #15
- 8000ce6: f8c7 3098 str.w r3, [r7, #152] ; 0x98
- | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 8000cea: 2300 movs r3, #0
- 8000cec: f8c7 309c str.w r3, [r7, #156] ; 0x9c
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000cf0: 2300 movs r3, #0
- 8000cf2: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8000cf6: 2300 movs r3, #0
- 8000cf8: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8000cfc: 2300 movs r3, #0
- 8000cfe: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
-
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
- 8000d02: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000d06: 2100 movs r1, #0
- 8000d08: 4618 mov r0, r3
- 8000d0a: f001 fcd1 bl 80026b0 <HAL_RCC_ClockConfig>
- 8000d0e: 4603 mov r3, r0
- 8000d10: 2b00 cmp r3, #0
- 8000d12: bf14 ite ne
- 8000d14: 2301 movne r3, #1
- 8000d16: 2300 moveq r3, #0
- 8000d18: b2db uxtb r3, r3
- 8000d1a: 2b00 cmp r3, #0
- 8000d1c: d001 beq.n 8000d22 <_Z18SystemClock_Configv+0xda>
- Error_Handler();
- 8000d1e: f000 fc2f bl 8001580 <Error_Handler>
- }
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
- 8000d22: f44f 6300 mov.w r3, #2048 ; 0x800
- 8000d26: 60bb str r3, [r7, #8]
- PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
- 8000d28: 2300 movs r3, #0
- 8000d2a: 663b str r3, [r7, #96] ; 0x60
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
- 8000d2c: f107 0308 add.w r3, r7, #8
- 8000d30: 4618 mov r0, r3
- 8000d32: f001 fe8b bl 8002a4c <HAL_RCCEx_PeriphCLKConfig>
- 8000d36: 4603 mov r3, r0
- 8000d38: 2b00 cmp r3, #0
- 8000d3a: bf14 ite ne
- 8000d3c: 2301 movne r3, #1
- 8000d3e: 2300 moveq r3, #0
- 8000d40: b2db uxtb r3, r3
- 8000d42: 2b00 cmp r3, #0
- 8000d44: d001 beq.n 8000d4a <_Z18SystemClock_Configv+0x102>
- Error_Handler();
- 8000d46: f000 fc1b bl 8001580 <Error_Handler>
- }
-}
- 8000d4a: bf00 nop
- 8000d4c: 37e0 adds r7, #224 ; 0xe0
- 8000d4e: 46bd mov sp, r7
- 8000d50: bd80 pop {r7, pc}
- 8000d52: bf00 nop
- 8000d54: 40023800 .word 0x40023800
- 8000d58: 40007000 .word 0x40007000
-
-08000d5c <_ZL12MX_NVIC_Initv>:
-
-/**
- * @brief NVIC Configuration.
- * @retval None
- */
-static void MX_NVIC_Init(void) {
- 8000d5c: b580 push {r7, lr}
- 8000d5e: af00 add r7, sp, #0
- /* TIM3_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1);
- 8000d60: 2201 movs r2, #1
- 8000d62: 2102 movs r1, #2
- 8000d64: 201d movs r0, #29
- 8000d66: f000 fffc bl 8001d62 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM3_IRQn);
- 8000d6a: 201d movs r0, #29
- 8000d6c: f001 f815 bl 8001d9a <HAL_NVIC_EnableIRQ>
- /* TIM6_DAC_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2);
- 8000d70: 2202 movs r2, #2
- 8000d72: 2102 movs r1, #2
- 8000d74: 2036 movs r0, #54 ; 0x36
- 8000d76: f000 fff4 bl 8001d62 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
- 8000d7a: 2036 movs r0, #54 ; 0x36
- 8000d7c: f001 f80d bl 8001d9a <HAL_NVIC_EnableIRQ>
- /* USART6_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(USART6_IRQn, 2, 0);
- 8000d80: 2200 movs r2, #0
- 8000d82: 2102 movs r1, #2
- 8000d84: 2047 movs r0, #71 ; 0x47
- 8000d86: f000 ffec bl 8001d62 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(USART6_IRQn);
- 8000d8a: 2047 movs r0, #71 ; 0x47
- 8000d8c: f001 f805 bl 8001d9a <HAL_NVIC_EnableIRQ>
-}
- 8000d90: bf00 nop
- 8000d92: bd80 pop {r7, pc}
-
-08000d94 <_ZL12MX_TIM2_Initv>:
-/**
- * @brief TIM2 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM2_Init(void) {
- 8000d94: b580 push {r7, lr}
- 8000d96: b08c sub sp, #48 ; 0x30
- 8000d98: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM2_Init 0 */
-
- /* USER CODE END TIM2_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = { 0 };
- 8000d9a: f107 030c add.w r3, r7, #12
- 8000d9e: 2224 movs r2, #36 ; 0x24
- 8000da0: 2100 movs r1, #0
- 8000da2: 4618 mov r0, r3
- 8000da4: f004 faea bl 800537c <memset>
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000da8: 463b mov r3, r7
- 8000daa: 2200 movs r2, #0
- 8000dac: 601a str r2, [r3, #0]
- 8000dae: 605a str r2, [r3, #4]
- 8000db0: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM2_Init 1 */
-
- /* USER CODE END TIM2_Init 1 */
- htim2.Instance = TIM2;
- 8000db2: 4b26 ldr r3, [pc, #152] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000db4: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
- 8000db8: 601a str r2, [r3, #0]
- htim2.Init.Prescaler = 0;
- 8000dba: 4b24 ldr r3, [pc, #144] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dbc: 2200 movs r2, #0
- 8000dbe: 605a str r2, [r3, #4]
- htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000dc0: 4b22 ldr r3, [pc, #136] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dc2: 2200 movs r2, #0
- 8000dc4: 609a str r2, [r3, #8]
- htim2.Init.Period = 4294967295;
- 8000dc6: 4b21 ldr r3, [pc, #132] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dc8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000dcc: 60da str r2, [r3, #12]
- htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000dce: 4b1f ldr r3, [pc, #124] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dd0: 2200 movs r2, #0
- 8000dd2: 611a str r2, [r3, #16]
- htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000dd4: 4b1d ldr r3, [pc, #116] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dd6: 2200 movs r2, #0
- 8000dd8: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8000dda: 2303 movs r3, #3
- 8000ddc: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8000dde: 2300 movs r3, #0
- 8000de0: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8000de2: 2301 movs r3, #1
- 8000de4: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8000de6: 2300 movs r3, #0
- 8000de8: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 8000dea: 2300 movs r3, #0
- 8000dec: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8000dee: 2300 movs r3, #0
- 8000df0: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8000df2: 2301 movs r3, #1
- 8000df4: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8000df6: 2300 movs r3, #0
- 8000df8: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 8000dfa: 2300 movs r3, #0
- 8000dfc: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) {
- 8000dfe: f107 030c add.w r3, r7, #12
- 8000e02: 4619 mov r1, r3
- 8000e04: 4811 ldr r0, [pc, #68] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e06: f002 fb17 bl 8003438 <HAL_TIM_Encoder_Init>
- 8000e0a: 4603 mov r3, r0
- 8000e0c: 2b00 cmp r3, #0
- 8000e0e: bf14 ite ne
- 8000e10: 2301 movne r3, #1
- 8000e12: 2300 moveq r3, #0
- 8000e14: b2db uxtb r3, r3
- 8000e16: 2b00 cmp r3, #0
- 8000e18: d001 beq.n 8000e1e <_ZL12MX_TIM2_Initv+0x8a>
- Error_Handler();
- 8000e1a: f000 fbb1 bl 8001580 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000e1e: 2300 movs r3, #0
- 8000e20: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000e22: 2300 movs r3, #0
- 8000e24: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig)
- 8000e26: 463b mov r3, r7
- 8000e28: 4619 mov r1, r3
- 8000e2a: 4808 ldr r0, [pc, #32] ; (8000e4c <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e2c: f003 faa4 bl 8004378 <HAL_TIMEx_MasterConfigSynchronization>
- 8000e30: 4603 mov r3, r0
- != HAL_OK) {
- 8000e32: 2b00 cmp r3, #0
- 8000e34: bf14 ite ne
- 8000e36: 2301 movne r3, #1
- 8000e38: 2300 moveq r3, #0
- 8000e3a: b2db uxtb r3, r3
- if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig)
- 8000e3c: 2b00 cmp r3, #0
- 8000e3e: d001 beq.n 8000e44 <_ZL12MX_TIM2_Initv+0xb0>
- Error_Handler();
- 8000e40: f000 fb9e bl 8001580 <Error_Handler>
- }
- /* USER CODE BEGIN TIM2_Init 2 */
-
- /* USER CODE END TIM2_Init 2 */
-
-}
- 8000e44: bf00 nop
- 8000e46: 3730 adds r7, #48 ; 0x30
- 8000e48: 46bd mov sp, r7
- 8000e4a: bd80 pop {r7, pc}
- 8000e4c: 20000028 .word 0x20000028
-
-08000e50 <_ZL12MX_TIM3_Initv>:
-/**
- * @brief TIM3 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM3_Init(void) {
- 8000e50: b580 push {r7, lr}
- 8000e52: b088 sub sp, #32
- 8000e54: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM3_Init 0 */
-
- /* USER CODE END TIM3_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };
- 8000e56: f107 0310 add.w r3, r7, #16
- 8000e5a: 2200 movs r2, #0
- 8000e5c: 601a str r2, [r3, #0]
- 8000e5e: 605a str r2, [r3, #4]
- 8000e60: 609a str r2, [r3, #8]
- 8000e62: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000e64: 1d3b adds r3, r7, #4
- 8000e66: 2200 movs r2, #0
- 8000e68: 601a str r2, [r3, #0]
- 8000e6a: 605a str r2, [r3, #4]
- 8000e6c: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM3_Init 1 */
-
- /* USER CODE END TIM3_Init 1 */
- htim3.Instance = TIM3;
- 8000e6e: 4b25 ldr r3, [pc, #148] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e70: 4a25 ldr r2, [pc, #148] ; (8000f08 <_ZL12MX_TIM3_Initv+0xb8>)
- 8000e72: 601a str r2, [r3, #0]
- htim3.Init.Prescaler = 999;
- 8000e74: 4b23 ldr r3, [pc, #140] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e76: f240 32e7 movw r2, #999 ; 0x3e7
- 8000e7a: 605a str r2, [r3, #4]
- htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000e7c: 4b21 ldr r3, [pc, #132] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e7e: 2200 movs r2, #0
- 8000e80: 609a str r2, [r3, #8]
- htim3.Init.Period = 159;
- 8000e82: 4b20 ldr r3, [pc, #128] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e84: 229f movs r2, #159 ; 0x9f
- 8000e86: 60da str r2, [r3, #12]
- htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000e88: 4b1e ldr r3, [pc, #120] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e8a: 2200 movs r2, #0
- 8000e8c: 611a str r2, [r3, #16]
- htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000e8e: 4b1d ldr r3, [pc, #116] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e90: 2200 movs r2, #0
- 8000e92: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim3) != HAL_OK) {
- 8000e94: 481b ldr r0, [pc, #108] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e96: f002 f9ff bl 8003298 <HAL_TIM_Base_Init>
- 8000e9a: 4603 mov r3, r0
- 8000e9c: 2b00 cmp r3, #0
- 8000e9e: bf14 ite ne
- 8000ea0: 2301 movne r3, #1
- 8000ea2: 2300 moveq r3, #0
- 8000ea4: b2db uxtb r3, r3
- 8000ea6: 2b00 cmp r3, #0
- 8000ea8: d001 beq.n 8000eae <_ZL12MX_TIM3_Initv+0x5e>
- Error_Handler();
- 8000eaa: f000 fb69 bl 8001580 <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000eae: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000eb2: 613b str r3, [r7, #16]
- if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) {
- 8000eb4: f107 0310 add.w r3, r7, #16
- 8000eb8: 4619 mov r1, r3
- 8000eba: 4812 ldr r0, [pc, #72] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000ebc: f002 fdbc bl 8003a38 <HAL_TIM_ConfigClockSource>
- 8000ec0: 4603 mov r3, r0
- 8000ec2: 2b00 cmp r3, #0
- 8000ec4: bf14 ite ne
- 8000ec6: 2301 movne r3, #1
- 8000ec8: 2300 moveq r3, #0
- 8000eca: b2db uxtb r3, r3
- 8000ecc: 2b00 cmp r3, #0
- 8000ece: d001 beq.n 8000ed4 <_ZL12MX_TIM3_Initv+0x84>
- Error_Handler();
- 8000ed0: f000 fb56 bl 8001580 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000ed4: 2300 movs r3, #0
- 8000ed6: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000ed8: 2300 movs r3, #0
- 8000eda: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig)
- 8000edc: 1d3b adds r3, r7, #4
- 8000ede: 4619 mov r1, r3
- 8000ee0: 4808 ldr r0, [pc, #32] ; (8000f04 <_ZL12MX_TIM3_Initv+0xb4>)
- 8000ee2: f003 fa49 bl 8004378 <HAL_TIMEx_MasterConfigSynchronization>
- 8000ee6: 4603 mov r3, r0
- != HAL_OK) {
- 8000ee8: 2b00 cmp r3, #0
- 8000eea: bf14 ite ne
- 8000eec: 2301 movne r3, #1
- 8000eee: 2300 moveq r3, #0
- 8000ef0: b2db uxtb r3, r3
- if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig)
- 8000ef2: 2b00 cmp r3, #0
- 8000ef4: d001 beq.n 8000efa <_ZL12MX_TIM3_Initv+0xaa>
- Error_Handler();
- 8000ef6: f000 fb43 bl 8001580 <Error_Handler>
- }
- /* USER CODE BEGIN TIM3_Init 2 */
-
- /* USER CODE END TIM3_Init 2 */
-
-}
- 8000efa: bf00 nop
- 8000efc: 3720 adds r7, #32
- 8000efe: 46bd mov sp, r7
- 8000f00: bd80 pop {r7, pc}
- 8000f02: bf00 nop
- 8000f04: 20000068 .word 0x20000068
- 8000f08: 40000400 .word 0x40000400
-
-08000f0c <_ZL12MX_TIM4_Initv>:
-/**
- * @brief TIM4 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM4_Init(void) {
- 8000f0c: b580 push {r7, lr}
- 8000f0e: b08e sub sp, #56 ; 0x38
- 8000f10: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM4_Init 0 */
-
- /* USER CODE END TIM4_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };
- 8000f12: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000f16: 2200 movs r2, #0
- 8000f18: 601a str r2, [r3, #0]
- 8000f1a: 605a str r2, [r3, #4]
- 8000f1c: 609a str r2, [r3, #8]
- 8000f1e: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000f20: f107 031c add.w r3, r7, #28
- 8000f24: 2200 movs r2, #0
- 8000f26: 601a str r2, [r3, #0]
- 8000f28: 605a str r2, [r3, #4]
- 8000f2a: 609a str r2, [r3, #8]
- TIM_OC_InitTypeDef sConfigOC = { 0 };
- 8000f2c: 463b mov r3, r7
- 8000f2e: 2200 movs r2, #0
- 8000f30: 601a str r2, [r3, #0]
- 8000f32: 605a str r2, [r3, #4]
- 8000f34: 609a str r2, [r3, #8]
- 8000f36: 60da str r2, [r3, #12]
- 8000f38: 611a str r2, [r3, #16]
- 8000f3a: 615a str r2, [r3, #20]
- 8000f3c: 619a str r2, [r3, #24]
-
- /* USER CODE BEGIN TIM4_Init 1 */
-
- /* USER CODE END TIM4_Init 1 */
- htim4.Instance = TIM4;
- 8000f3e: 4b41 ldr r3, [pc, #260] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f40: 4a41 ldr r2, [pc, #260] ; (8001048 <_ZL12MX_TIM4_Initv+0x13c>)
- 8000f42: 601a str r2, [r3, #0]
- htim4.Init.Prescaler = 0;
- 8000f44: 4b3f ldr r3, [pc, #252] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f46: 2200 movs r2, #0
- 8000f48: 605a str r2, [r3, #4]
- htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000f4a: 4b3e ldr r3, [pc, #248] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f4c: 2200 movs r2, #0
- 8000f4e: 609a str r2, [r3, #8]
- htim4.Init.Period = 799;
- 8000f50: 4b3c ldr r3, [pc, #240] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f52: f240 321f movw r2, #799 ; 0x31f
- 8000f56: 60da str r2, [r3, #12]
- htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000f58: 4b3a ldr r3, [pc, #232] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f5a: 2200 movs r2, #0
- 8000f5c: 611a str r2, [r3, #16]
- htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000f5e: 4b39 ldr r3, [pc, #228] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f60: 2200 movs r2, #0
- 8000f62: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim4) != HAL_OK) {
- 8000f64: 4837 ldr r0, [pc, #220] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f66: f002 f997 bl 8003298 <HAL_TIM_Base_Init>
- 8000f6a: 4603 mov r3, r0
- 8000f6c: 2b00 cmp r3, #0
- 8000f6e: bf14 ite ne
- 8000f70: 2301 movne r3, #1
- 8000f72: 2300 moveq r3, #0
- 8000f74: b2db uxtb r3, r3
- 8000f76: 2b00 cmp r3, #0
- 8000f78: d001 beq.n 8000f7e <_ZL12MX_TIM4_Initv+0x72>
- Error_Handler();
- 8000f7a: f000 fb01 bl 8001580 <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000f7e: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000f82: 62bb str r3, [r7, #40] ; 0x28
- if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) {
- 8000f84: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000f88: 4619 mov r1, r3
- 8000f8a: 482e ldr r0, [pc, #184] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000f8c: f002 fd54 bl 8003a38 <HAL_TIM_ConfigClockSource>
- 8000f90: 4603 mov r3, r0
- 8000f92: 2b00 cmp r3, #0
- 8000f94: bf14 ite ne
- 8000f96: 2301 movne r3, #1
- 8000f98: 2300 moveq r3, #0
- 8000f9a: b2db uxtb r3, r3
- 8000f9c: 2b00 cmp r3, #0
- 8000f9e: d001 beq.n 8000fa4 <_ZL12MX_TIM4_Initv+0x98>
- Error_Handler();
- 8000fa0: f000 faee bl 8001580 <Error_Handler>
- }
- if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) {
- 8000fa4: 4827 ldr r0, [pc, #156] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000fa6: f002 f9cd bl 8003344 <HAL_TIM_PWM_Init>
- 8000faa: 4603 mov r3, r0
- 8000fac: 2b00 cmp r3, #0
- 8000fae: bf14 ite ne
- 8000fb0: 2301 movne r3, #1
- 8000fb2: 2300 moveq r3, #0
- 8000fb4: b2db uxtb r3, r3
- 8000fb6: 2b00 cmp r3, #0
- 8000fb8: d001 beq.n 8000fbe <_ZL12MX_TIM4_Initv+0xb2>
- Error_Handler();
- 8000fba: f000 fae1 bl 8001580 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000fbe: 2300 movs r3, #0
- 8000fc0: 61fb str r3, [r7, #28]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000fc2: 2300 movs r3, #0
- 8000fc4: 627b str r3, [r7, #36] ; 0x24
- if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig)
- 8000fc6: f107 031c add.w r3, r7, #28
- 8000fca: 4619 mov r1, r3
- 8000fcc: 481d ldr r0, [pc, #116] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000fce: f003 f9d3 bl 8004378 <HAL_TIMEx_MasterConfigSynchronization>
- 8000fd2: 4603 mov r3, r0
- != HAL_OK) {
- 8000fd4: 2b00 cmp r3, #0
- 8000fd6: bf14 ite ne
- 8000fd8: 2301 movne r3, #1
- 8000fda: 2300 moveq r3, #0
- 8000fdc: b2db uxtb r3, r3
- if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig)
- 8000fde: 2b00 cmp r3, #0
- 8000fe0: d001 beq.n 8000fe6 <_ZL12MX_TIM4_Initv+0xda>
- Error_Handler();
- 8000fe2: f000 facd bl 8001580 <Error_Handler>
- }
- sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8000fe6: 2360 movs r3, #96 ; 0x60
- 8000fe8: 603b str r3, [r7, #0]
- sConfigOC.Pulse = 0;
- 8000fea: 2300 movs r3, #0
- 8000fec: 607b str r3, [r7, #4]
- sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 8000fee: 2300 movs r3, #0
- 8000ff0: 60bb str r3, [r7, #8]
- sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 8000ff2: 2300 movs r3, #0
- 8000ff4: 613b str r3, [r7, #16]
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3)
- 8000ff6: 463b mov r3, r7
- 8000ff8: 2208 movs r2, #8
- 8000ffa: 4619 mov r1, r3
- 8000ffc: 4811 ldr r0, [pc, #68] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8000ffe: f002 fc03 bl 8003808 <HAL_TIM_PWM_ConfigChannel>
- 8001002: 4603 mov r3, r0
- != HAL_OK) {
- 8001004: 2b00 cmp r3, #0
- 8001006: bf14 ite ne
- 8001008: 2301 movne r3, #1
- 800100a: 2300 moveq r3, #0
- 800100c: b2db uxtb r3, r3
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3)
- 800100e: 2b00 cmp r3, #0
- 8001010: d001 beq.n 8001016 <_ZL12MX_TIM4_Initv+0x10a>
- Error_Handler();
- 8001012: f000 fab5 bl 8001580 <Error_Handler>
- }
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4)
- 8001016: 463b mov r3, r7
- 8001018: 220c movs r2, #12
- 800101a: 4619 mov r1, r3
- 800101c: 4809 ldr r0, [pc, #36] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 800101e: f002 fbf3 bl 8003808 <HAL_TIM_PWM_ConfigChannel>
- 8001022: 4603 mov r3, r0
- != HAL_OK) {
- 8001024: 2b00 cmp r3, #0
- 8001026: bf14 ite ne
- 8001028: 2301 movne r3, #1
- 800102a: 2300 moveq r3, #0
- 800102c: b2db uxtb r3, r3
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4)
- 800102e: 2b00 cmp r3, #0
- 8001030: d001 beq.n 8001036 <_ZL12MX_TIM4_Initv+0x12a>
- Error_Handler();
- 8001032: f000 faa5 bl 8001580 <Error_Handler>
- }
- /* USER CODE BEGIN TIM4_Init 2 */
-
- /* USER CODE END TIM4_Init 2 */
- HAL_TIM_MspPostInit(&htim4);
- 8001036: 4803 ldr r0, [pc, #12] ; (8001044 <_ZL12MX_TIM4_Initv+0x138>)
- 8001038: f000 fc2c bl 8001894 <HAL_TIM_MspPostInit>
-
-}
- 800103c: bf00 nop
- 800103e: 3738 adds r7, #56 ; 0x38
- 8001040: 46bd mov sp, r7
- 8001042: bd80 pop {r7, pc}
- 8001044: 200000a8 .word 0x200000a8
- 8001048: 40000800 .word 0x40000800
-
-0800104c <_ZL12MX_TIM5_Initv>:
-/**
- * @brief TIM5 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM5_Init(void) {
- 800104c: b580 push {r7, lr}
- 800104e: b08c sub sp, #48 ; 0x30
- 8001050: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM5_Init 0 */
-
- /* USER CODE END TIM5_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = { 0 };
- 8001052: f107 030c add.w r3, r7, #12
- 8001056: 2224 movs r2, #36 ; 0x24
- 8001058: 2100 movs r1, #0
- 800105a: 4618 mov r0, r3
- 800105c: f004 f98e bl 800537c <memset>
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8001060: 463b mov r3, r7
- 8001062: 2200 movs r2, #0
- 8001064: 601a str r2, [r3, #0]
- 8001066: 605a str r2, [r3, #4]
- 8001068: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM5_Init 1 */
-
- /* USER CODE END TIM5_Init 1 */
- htim5.Instance = TIM5;
- 800106a: 4b26 ldr r3, [pc, #152] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 800106c: 4a26 ldr r2, [pc, #152] ; (8001108 <_ZL12MX_TIM5_Initv+0xbc>)
- 800106e: 601a str r2, [r3, #0]
- htim5.Init.Prescaler = 0;
- 8001070: 4b24 ldr r3, [pc, #144] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 8001072: 2200 movs r2, #0
- 8001074: 605a str r2, [r3, #4]
- htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001076: 4b23 ldr r3, [pc, #140] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 8001078: 2200 movs r2, #0
- 800107a: 609a str r2, [r3, #8]
- htim5.Init.Period = 4294967295;
- 800107c: 4b21 ldr r3, [pc, #132] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 800107e: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8001082: 60da str r2, [r3, #12]
- htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8001084: 4b1f ldr r3, [pc, #124] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 8001086: 2200 movs r2, #0
- 8001088: 611a str r2, [r3, #16]
- htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 800108a: 4b1e ldr r3, [pc, #120] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 800108c: 2200 movs r2, #0
- 800108e: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8001090: 2303 movs r3, #3
- 8001092: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8001094: 2300 movs r3, #0
- 8001096: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8001098: 2301 movs r3, #1
- 800109a: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 800109c: 2300 movs r3, #0
- 800109e: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 80010a0: 2300 movs r3, #0
- 80010a2: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 80010a4: 2300 movs r3, #0
- 80010a6: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 80010a8: 2301 movs r3, #1
- 80010aa: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 80010ac: 2300 movs r3, #0
- 80010ae: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 80010b0: 2300 movs r3, #0
- 80010b2: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) {
- 80010b4: f107 030c add.w r3, r7, #12
- 80010b8: 4619 mov r1, r3
- 80010ba: 4812 ldr r0, [pc, #72] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 80010bc: f002 f9bc bl 8003438 <HAL_TIM_Encoder_Init>
- 80010c0: 4603 mov r3, r0
- 80010c2: 2b00 cmp r3, #0
- 80010c4: bf14 ite ne
- 80010c6: 2301 movne r3, #1
- 80010c8: 2300 moveq r3, #0
- 80010ca: b2db uxtb r3, r3
- 80010cc: 2b00 cmp r3, #0
- 80010ce: d001 beq.n 80010d4 <_ZL12MX_TIM5_Initv+0x88>
- Error_Handler();
- 80010d0: f000 fa56 bl 8001580 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 80010d4: 2300 movs r3, #0
- 80010d6: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 80010d8: 2300 movs r3, #0
- 80010da: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig)
- 80010dc: 463b mov r3, r7
- 80010de: 4619 mov r1, r3
- 80010e0: 4808 ldr r0, [pc, #32] ; (8001104 <_ZL12MX_TIM5_Initv+0xb8>)
- 80010e2: f003 f949 bl 8004378 <HAL_TIMEx_MasterConfigSynchronization>
- 80010e6: 4603 mov r3, r0
- != HAL_OK) {
- 80010e8: 2b00 cmp r3, #0
- 80010ea: bf14 ite ne
- 80010ec: 2301 movne r3, #1
- 80010ee: 2300 moveq r3, #0
- 80010f0: b2db uxtb r3, r3
- if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig)
- 80010f2: 2b00 cmp r3, #0
- 80010f4: d001 beq.n 80010fa <_ZL12MX_TIM5_Initv+0xae>
- Error_Handler();
- 80010f6: f000 fa43 bl 8001580 <Error_Handler>
- }
- /* USER CODE BEGIN TIM5_Init 2 */
-
- /* USER CODE END TIM5_Init 2 */
-
-}
- 80010fa: bf00 nop
- 80010fc: 3730 adds r7, #48 ; 0x30
- 80010fe: 46bd mov sp, r7
- 8001100: bd80 pop {r7, pc}
- 8001102: bf00 nop
- 8001104: 200000e8 .word 0x200000e8
- 8001108: 40000c00 .word 0x40000c00
-
-0800110c <_ZL12MX_TIM6_Initv>:
-/**
- * @brief TIM6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM6_Init(void) {
- 800110c: b580 push {r7, lr}
- 800110e: b084 sub sp, #16
- 8001110: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM6_Init 0 */
-
- /* USER CODE END TIM6_Init 0 */
-
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8001112: 1d3b adds r3, r7, #4
- 8001114: 2200 movs r2, #0
- 8001116: 601a str r2, [r3, #0]
- 8001118: 605a str r2, [r3, #4]
- 800111a: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM6_Init 1 */
-
- /* USER CODE END TIM6_Init 1 */
- htim6.Instance = TIM6;
- 800111c: 4b1a ldr r3, [pc, #104] ; (8001188 <_ZL12MX_TIM6_Initv+0x7c>)
- 800111e: 4a1b ldr r2, [pc, #108] ; (800118c <_ZL12MX_TIM6_Initv+0x80>)
- 8001120: 601a str r2, [r3, #0]
- htim6.Init.Prescaler = 9999;
- 8001122: 4b19 ldr r3, [pc, #100] ; (8001188 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001124: f242 720f movw r2, #9999 ; 0x270f
- 8001128: 605a str r2, [r3, #4]
- htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
- 800112a: 4b17 ldr r3, [pc, #92] ; (8001188 <_ZL12MX_TIM6_Initv+0x7c>)
- 800112c: 2200 movs r2, #0
- 800112e: 609a str r2, [r3, #8]
- htim6.Init.Period = 799;
- 8001130: 4b15 ldr r3, [pc, #84] ; (8001188 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001132: f240 321f movw r2, #799 ; 0x31f
- 8001136: 60da str r2, [r3, #12]
- htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001138: 4b13 ldr r3, [pc, #76] ; (8001188 <_ZL12MX_TIM6_Initv+0x7c>)
- 800113a: 2200 movs r2, #0
- 800113c: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim6) != HAL_OK) {
- 800113e: 4812 ldr r0, [pc, #72] ; (8001188 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001140: f002 f8aa bl 8003298 <HAL_TIM_Base_Init>
- 8001144: 4603 mov r3, r0
- 8001146: 2b00 cmp r3, #0
- 8001148: bf14 ite ne
- 800114a: 2301 movne r3, #1
- 800114c: 2300 moveq r3, #0
- 800114e: b2db uxtb r3, r3
- 8001150: 2b00 cmp r3, #0
- 8001152: d001 beq.n 8001158 <_ZL12MX_TIM6_Initv+0x4c>
- Error_Handler();
- 8001154: f000 fa14 bl 8001580 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001158: 2300 movs r3, #0
- 800115a: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 800115c: 2300 movs r3, #0
- 800115e: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig)
- 8001160: 1d3b adds r3, r7, #4
- 8001162: 4619 mov r1, r3
- 8001164: 4808 ldr r0, [pc, #32] ; (8001188 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001166: f003 f907 bl 8004378 <HAL_TIMEx_MasterConfigSynchronization>
- 800116a: 4603 mov r3, r0
- != HAL_OK) {
- 800116c: 2b00 cmp r3, #0
- 800116e: bf14 ite ne
- 8001170: 2301 movne r3, #1
- 8001172: 2300 moveq r3, #0
- 8001174: b2db uxtb r3, r3
- if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig)
- 8001176: 2b00 cmp r3, #0
- 8001178: d001 beq.n 800117e <_ZL12MX_TIM6_Initv+0x72>
- Error_Handler();
- 800117a: f000 fa01 bl 8001580 <Error_Handler>
- }
- /* USER CODE BEGIN TIM6_Init 2 */
-
- /* USER CODE END TIM6_Init 2 */
-
-}
- 800117e: bf00 nop
- 8001180: 3710 adds r7, #16
- 8001182: 46bd mov sp, r7
- 8001184: bd80 pop {r7, pc}
- 8001186: bf00 nop
- 8001188: 20000128 .word 0x20000128
- 800118c: 40001000 .word 0x40001000
-
-08001190 <_ZL19MX_USART6_UART_Initv>:
-/**
- * @brief USART6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_USART6_UART_Init(void) {
- 8001190: b580 push {r7, lr}
- 8001192: af00 add r7, sp, #0
- /* USER CODE END USART6_Init 0 */
-
- /* USER CODE BEGIN USART6_Init 1 */
-
- /* USER CODE END USART6_Init 1 */
- huart6.Instance = USART6;
- 8001194: 4b17 ldr r3, [pc, #92] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 8001196: 4a18 ldr r2, [pc, #96] ; (80011f8 <_ZL19MX_USART6_UART_Initv+0x68>)
- 8001198: 601a str r2, [r3, #0]
- huart6.Init.BaudRate = 115200;
- 800119a: 4b16 ldr r3, [pc, #88] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 800119c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
- 80011a0: 605a str r2, [r3, #4]
- huart6.Init.WordLength = UART_WORDLENGTH_9B;
- 80011a2: 4b14 ldr r3, [pc, #80] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011a4: f44f 5280 mov.w r2, #4096 ; 0x1000
- 80011a8: 609a str r2, [r3, #8]
- huart6.Init.StopBits = UART_STOPBITS_1;
- 80011aa: 4b12 ldr r3, [pc, #72] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011ac: 2200 movs r2, #0
- 80011ae: 60da str r2, [r3, #12]
- huart6.Init.Parity = UART_PARITY_ODD;
- 80011b0: 4b10 ldr r3, [pc, #64] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011b2: f44f 62c0 mov.w r2, #1536 ; 0x600
- 80011b6: 611a str r2, [r3, #16]
- huart6.Init.Mode = UART_MODE_TX_RX;
- 80011b8: 4b0e ldr r3, [pc, #56] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011ba: 220c movs r2, #12
- 80011bc: 615a str r2, [r3, #20]
- huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 80011be: 4b0d ldr r3, [pc, #52] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011c0: 2200 movs r2, #0
- 80011c2: 619a str r2, [r3, #24]
- huart6.Init.OverSampling = UART_OVERSAMPLING_16;
- 80011c4: 4b0b ldr r3, [pc, #44] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011c6: 2200 movs r2, #0
- 80011c8: 61da str r2, [r3, #28]
- huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 80011ca: 4b0a ldr r3, [pc, #40] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011cc: 2200 movs r2, #0
- 80011ce: 621a str r2, [r3, #32]
- huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 80011d0: 4b08 ldr r3, [pc, #32] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011d2: 2200 movs r2, #0
- 80011d4: 625a str r2, [r3, #36] ; 0x24
- if (HAL_UART_Init(&huart6) != HAL_OK) {
- 80011d6: 4807 ldr r0, [pc, #28] ; (80011f4 <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011d8: f003 f948 bl 800446c <HAL_UART_Init>
- 80011dc: 4603 mov r3, r0
- 80011de: 2b00 cmp r3, #0
- 80011e0: bf14 ite ne
- 80011e2: 2301 movne r3, #1
- 80011e4: 2300 moveq r3, #0
- 80011e6: b2db uxtb r3, r3
- 80011e8: 2b00 cmp r3, #0
- 80011ea: d001 beq.n 80011f0 <_ZL19MX_USART6_UART_Initv+0x60>
- Error_Handler();
- 80011ec: f000 f9c8 bl 8001580 <Error_Handler>
- }
- /* USER CODE BEGIN USART6_Init 2 */
-
- /* USER CODE END USART6_Init 2 */
-
-}
- 80011f0: bf00 nop
- 80011f2: bd80 pop {r7, pc}
- 80011f4: 20000168 .word 0x20000168
- 80011f8: 40011400 .word 0x40011400
-
-080011fc <_ZL12MX_GPIO_Initv>:
-/**
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void) {
- 80011fc: b580 push {r7, lr}
- 80011fe: b08c sub sp, #48 ; 0x30
- 8001200: af00 add r7, sp, #0
- GPIO_InitTypeDef GPIO_InitStruct = { 0 };
- 8001202: f107 031c add.w r3, r7, #28
- 8001206: 2200 movs r2, #0
- 8001208: 601a str r2, [r3, #0]
- 800120a: 605a str r2, [r3, #4]
- 800120c: 609a str r2, [r3, #8]
- 800120e: 60da str r2, [r3, #12]
- 8001210: 611a str r2, [r3, #16]
-
- /* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 8001212: 4b5e ldr r3, [pc, #376] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001214: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001216: 4a5d ldr r2, [pc, #372] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001218: f043 0304 orr.w r3, r3, #4
- 800121c: 6313 str r3, [r2, #48] ; 0x30
- 800121e: 4b5b ldr r3, [pc, #364] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001220: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001222: f003 0304 and.w r3, r3, #4
- 8001226: 61bb str r3, [r7, #24]
- 8001228: 69bb ldr r3, [r7, #24]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 800122a: 4b58 ldr r3, [pc, #352] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 800122c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800122e: 4a57 ldr r2, [pc, #348] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001230: f043 0301 orr.w r3, r3, #1
- 8001234: 6313 str r3, [r2, #48] ; 0x30
- 8001236: 4b55 ldr r3, [pc, #340] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001238: 6b1b ldr r3, [r3, #48] ; 0x30
- 800123a: f003 0301 and.w r3, r3, #1
- 800123e: 617b str r3, [r7, #20]
- 8001240: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOF_CLK_ENABLE();
- 8001242: 4b52 ldr r3, [pc, #328] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001244: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001246: 4a51 ldr r2, [pc, #324] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001248: f043 0320 orr.w r3, r3, #32
- 800124c: 6313 str r3, [r2, #48] ; 0x30
- 800124e: 4b4f ldr r3, [pc, #316] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001250: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001252: f003 0320 and.w r3, r3, #32
- 8001256: 613b str r3, [r7, #16]
- 8001258: 693b ldr r3, [r7, #16]
- __HAL_RCC_GPIOE_CLK_ENABLE();
- 800125a: 4b4c ldr r3, [pc, #304] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 800125c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800125e: 4a4b ldr r2, [pc, #300] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001260: f043 0310 orr.w r3, r3, #16
- 8001264: 6313 str r3, [r2, #48] ; 0x30
- 8001266: 4b49 ldr r3, [pc, #292] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001268: 6b1b ldr r3, [r3, #48] ; 0x30
- 800126a: f003 0310 and.w r3, r3, #16
- 800126e: 60fb str r3, [r7, #12]
- 8001270: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 8001272: 4b46 ldr r3, [pc, #280] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001274: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001276: 4a45 ldr r2, [pc, #276] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001278: f043 0308 orr.w r3, r3, #8
- 800127c: 6313 str r3, [r2, #48] ; 0x30
- 800127e: 4b43 ldr r3, [pc, #268] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001280: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001282: f003 0308 and.w r3, r3, #8
- 8001286: 60bb str r3, [r7, #8]
- 8001288: 68bb ldr r3, [r7, #8]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 800128a: 4b40 ldr r3, [pc, #256] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 800128c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800128e: 4a3f ldr r2, [pc, #252] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001290: f043 0302 orr.w r3, r3, #2
- 8001294: 6313 str r3, [r2, #48] ; 0x30
- 8001296: 4b3d ldr r3, [pc, #244] ; (800138c <_ZL12MX_GPIO_Initv+0x190>)
- 8001298: 6b1b ldr r3, [r3, #48] ; 0x30
- 800129a: f003 0302 and.w r3, r3, #2
- 800129e: 607b str r3, [r7, #4]
- 80012a0: 687b ldr r3, [r7, #4]
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET);
- 80012a2: 2200 movs r2, #0
- 80012a4: f44f 5140 mov.w r1, #12288 ; 0x3000
- 80012a8: 4839 ldr r0, [pc, #228] ; (8001390 <_ZL12MX_GPIO_Initv+0x194>)
- 80012aa: f000 ff5d bl 8002168 <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET);
- 80012ae: 2201 movs r2, #1
- 80012b0: f44f 4140 mov.w r1, #49152 ; 0xc000
- 80012b4: 4836 ldr r0, [pc, #216] ; (8001390 <_ZL12MX_GPIO_Initv+0x194>)
- 80012b6: f000 ff57 bl 8002168 <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin : user_button_Pin */
- GPIO_InitStruct.Pin = user_button_Pin;
- 80012ba: f44f 5300 mov.w r3, #8192 ; 0x2000
- 80012be: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
- 80012c0: 4b34 ldr r3, [pc, #208] ; (8001394 <_ZL12MX_GPIO_Initv+0x198>)
- 80012c2: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012c4: 2300 movs r3, #0
- 80012c6: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct);
- 80012c8: f107 031c add.w r3, r7, #28
- 80012cc: 4619 mov r1, r3
- 80012ce: 4832 ldr r0, [pc, #200] ; (8001398 <_ZL12MX_GPIO_Initv+0x19c>)
- 80012d0: f000 fda0 bl 8001e14 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current2_Pin */
- GPIO_InitStruct.Pin = current2_Pin;
- 80012d4: 2301 movs r3, #1
- 80012d6: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 80012d8: 2303 movs r3, #3
- 80012da: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012dc: 2300 movs r3, #0
- 80012de: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct);
- 80012e0: f107 031c add.w r3, r7, #28
- 80012e4: 4619 mov r1, r3
- 80012e6: 482c ldr r0, [pc, #176] ; (8001398 <_ZL12MX_GPIO_Initv+0x19c>)
- 80012e8: f000 fd94 bl 8001e14 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current1_Pin */
- GPIO_InitStruct.Pin = current1_Pin;
- 80012ec: 2308 movs r3, #8
- 80012ee: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 80012f0: 2303 movs r3, #3
- 80012f2: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012f4: 2300 movs r3, #0
- 80012f6: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct);
- 80012f8: f107 031c add.w r3, r7, #28
- 80012fc: 4619 mov r1, r3
- 80012fe: 4827 ldr r0, [pc, #156] ; (800139c <_ZL12MX_GPIO_Initv+0x1a0>)
- 8001300: f000 fd88 bl 8001e14 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault2_Pin */
- GPIO_InitStruct.Pin = fault2_Pin;
- 8001304: 2340 movs r3, #64 ; 0x40
- 8001306: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001308: 2300 movs r3, #0
- 800130a: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800130c: 2300 movs r3, #0
- 800130e: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct);
- 8001310: f107 031c add.w r3, r7, #28
- 8001314: 4619 mov r1, r3
- 8001316: 4821 ldr r0, [pc, #132] ; (800139c <_ZL12MX_GPIO_Initv+0x1a0>)
- 8001318: f000 fd7c bl 8001e14 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : dir2_Pin dir1_Pin */
- GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin;
- 800131c: f44f 5340 mov.w r3, #12288 ; 0x3000
- 8001320: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 8001322: 2301 movs r3, #1
- 8001324: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001326: 2300 movs r3, #0
- 8001328: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800132a: 2300 movs r3, #0
- 800132c: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 800132e: f107 031c add.w r3, r7, #28
- 8001332: 4619 mov r1, r3
- 8001334: 4816 ldr r0, [pc, #88] ; (8001390 <_ZL12MX_GPIO_Initv+0x194>)
- 8001336: f000 fd6d bl 8001e14 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : sleep2_Pin sleep1_Pin */
- GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin;
- 800133a: f44f 4340 mov.w r3, #49152 ; 0xc000
- 800133e: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 8001340: 2301 movs r3, #1
- 8001342: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- 8001344: 2301 movs r3, #1
- 8001346: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001348: 2300 movs r3, #0
- 800134a: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 800134c: f107 031c add.w r3, r7, #28
- 8001350: 4619 mov r1, r3
- 8001352: 480f ldr r0, [pc, #60] ; (8001390 <_ZL12MX_GPIO_Initv+0x194>)
- 8001354: f000 fd5e bl 8001e14 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault1_Pin */
- GPIO_InitStruct.Pin = fault1_Pin;
- 8001358: f44f 7300 mov.w r3, #512 ; 0x200
- 800135c: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 800135e: 2300 movs r3, #0
- 8001360: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001362: 2300 movs r3, #0
- 8001364: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct);
- 8001366: f107 031c add.w r3, r7, #28
- 800136a: 4619 mov r1, r3
- 800136c: 480c ldr r0, [pc, #48] ; (80013a0 <_ZL12MX_GPIO_Initv+0x1a4>)
- 800136e: f000 fd51 bl 8001e14 <HAL_GPIO_Init>
-
- /* EXTI interrupt init*/
- HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
- 8001372: 2200 movs r2, #0
- 8001374: 2100 movs r1, #0
- 8001376: 2028 movs r0, #40 ; 0x28
- 8001378: f000 fcf3 bl 8001d62 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
- 800137c: 2028 movs r0, #40 ; 0x28
- 800137e: f000 fd0c bl 8001d9a <HAL_NVIC_EnableIRQ>
-
-}
- 8001382: bf00 nop
- 8001384: 3730 adds r7, #48 ; 0x30
- 8001386: 46bd mov sp, r7
- 8001388: bd80 pop {r7, pc}
- 800138a: bf00 nop
- 800138c: 40023800 .word 0x40023800
- 8001390: 40021400 .word 0x40021400
- 8001394: 10110000 .word 0x10110000
- 8001398: 40020800 .word 0x40020800
- 800139c: 40020000 .word 0x40020000
- 80013a0: 40021000 .word 0x40021000
-
-080013a4 <HAL_TIM_PeriodElapsedCallback>:
-
-/* USER CODE BEGIN 4 */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
- 80013a4: b580 push {r7, lr}
- 80013a6: b084 sub sp, #16
- 80013a8: af00 add r7, sp, #0
- 80013aa: 6078 str r0, [r7, #4]
-
- //TIMER 100Hz PID control
- if (htim->Instance == TIM3) {
- 80013ac: 687b ldr r3, [r7, #4]
- 80013ae: 681b ldr r3, [r3, #0]
- 80013b0: 4a30 ldr r2, [pc, #192] ; (8001474 <HAL_TIM_PeriodElapsedCallback+0xd0>)
- 80013b2: 4293 cmp r3, r2
- 80013b4: d14d bne.n 8001452 <HAL_TIM_PeriodElapsedCallback+0xae>
-
- left_velocity = left_encoder.GetLinearVelocity();
- 80013b6: 4830 ldr r0, [pc, #192] ; (8001478 <HAL_TIM_PeriodElapsedCallback+0xd4>)
- 80013b8: f7ff f94a bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 80013bc: eef0 7a40 vmov.f32 s15, s0
- 80013c0: 4b2e ldr r3, [pc, #184] ; (800147c <HAL_TIM_PeriodElapsedCallback+0xd8>)
- 80013c2: edc3 7a00 vstr s15, [r3]
- left_dutycycle = left_pid.update(left_velocity);
- 80013c6: 4b2d ldr r3, [pc, #180] ; (800147c <HAL_TIM_PeriodElapsedCallback+0xd8>)
- 80013c8: edd3 7a00 vldr s15, [r3]
- 80013cc: eeb0 0a67 vmov.f32 s0, s15
- 80013d0: 482b ldr r0, [pc, #172] ; (8001480 <HAL_TIM_PeriodElapsedCallback+0xdc>)
- 80013d2: f7ff fb92 bl 8000afa <_ZN3Pid6updateEf>
- 80013d6: 4602 mov r2, r0
- 80013d8: 4b2a ldr r3, [pc, #168] ; (8001484 <HAL_TIM_PeriodElapsedCallback+0xe0>)
- 80013da: 601a str r2, [r3, #0]
- left_motor.set_speed(left_dutycycle);
- 80013dc: 4b29 ldr r3, [pc, #164] ; (8001484 <HAL_TIM_PeriodElapsedCallback+0xe0>)
- 80013de: 681b ldr r3, [r3, #0]
- 80013e0: 4619 mov r1, r3
- 80013e2: 4829 ldr r0, [pc, #164] ; (8001488 <HAL_TIM_PeriodElapsedCallback+0xe4>)
- 80013e4: f7ff fa10 bl 8000808 <_ZN15MotorController9set_speedEi>
-
- right_velocity = right_encoder.GetLinearVelocity();
- 80013e8: 4828 ldr r0, [pc, #160] ; (800148c <HAL_TIM_PeriodElapsedCallback+0xe8>)
- 80013ea: f7ff f931 bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 80013ee: eef0 7a40 vmov.f32 s15, s0
- 80013f2: 4b27 ldr r3, [pc, #156] ; (8001490 <HAL_TIM_PeriodElapsedCallback+0xec>)
- 80013f4: edc3 7a00 vstr s15, [r3]
- right_dutycycle = right_pid.update(right_velocity);
- 80013f8: 4b25 ldr r3, [pc, #148] ; (8001490 <HAL_TIM_PeriodElapsedCallback+0xec>)
- 80013fa: edd3 7a00 vldr s15, [r3]
- 80013fe: eeb0 0a67 vmov.f32 s0, s15
- 8001402: 4824 ldr r0, [pc, #144] ; (8001494 <HAL_TIM_PeriodElapsedCallback+0xf0>)
- 8001404: f7ff fb79 bl 8000afa <_ZN3Pid6updateEf>
- 8001408: 4602 mov r2, r0
- 800140a: 4b23 ldr r3, [pc, #140] ; (8001498 <HAL_TIM_PeriodElapsedCallback+0xf4>)
- 800140c: 601a str r2, [r3, #0]
- right_motor.set_speed(right_dutycycle);
- 800140e: 4b22 ldr r3, [pc, #136] ; (8001498 <HAL_TIM_PeriodElapsedCallback+0xf4>)
- 8001410: 681b ldr r3, [r3, #0]
- 8001412: 4619 mov r1, r3
- 8001414: 4821 ldr r0, [pc, #132] ; (800149c <HAL_TIM_PeriodElapsedCallback+0xf8>)
- 8001416: f7ff f9f7 bl 8000808 <_ZN15MotorController9set_speedEi>
-
- float difference = left_velocity - right_velocity;
- 800141a: 4b18 ldr r3, [pc, #96] ; (800147c <HAL_TIM_PeriodElapsedCallback+0xd8>)
- 800141c: ed93 7a00 vldr s14, [r3]
- 8001420: 4b1b ldr r3, [pc, #108] ; (8001490 <HAL_TIM_PeriodElapsedCallback+0xec>)
- 8001422: edd3 7a00 vldr s15, [r3]
- 8001426: ee77 7a67 vsub.f32 s15, s14, s15
- 800142a: edc7 7a03 vstr s15, [r7, #12]
-
- int cross_dutycycle = cross_pid.update(difference);
- 800142e: ed97 0a03 vldr s0, [r7, #12]
- 8001432: 481b ldr r0, [pc, #108] ; (80014a0 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 8001434: f7ff fb61 bl 8000afa <_ZN3Pid6updateEf>
- 8001438: 60b8 str r0, [r7, #8]
-
- left_dutycycle += cross_dutycycle;
- 800143a: 4b12 ldr r3, [pc, #72] ; (8001484 <HAL_TIM_PeriodElapsedCallback+0xe0>)
- 800143c: 681a ldr r2, [r3, #0]
- 800143e: 68bb ldr r3, [r7, #8]
- 8001440: 4413 add r3, r2
- 8001442: 4a10 ldr r2, [pc, #64] ; (8001484 <HAL_TIM_PeriodElapsedCallback+0xe0>)
- 8001444: 6013 str r3, [r2, #0]
- right_dutycycle -= cross_dutycycle;
- 8001446: 4b14 ldr r3, [pc, #80] ; (8001498 <HAL_TIM_PeriodElapsedCallback+0xf4>)
- 8001448: 681a ldr r2, [r3, #0]
- 800144a: 68bb ldr r3, [r7, #8]
- 800144c: 1ad3 subs r3, r2, r3
- 800144e: 4a12 ldr r2, [pc, #72] ; (8001498 <HAL_TIM_PeriodElapsedCallback+0xf4>)
- 8001450: 6013 str r3, [r2, #0]
-
- }
-
- //TIMER 2Hz Transmit
- if (htim->Instance == TIM6) {
- 8001452: 687b ldr r3, [r7, #4]
- 8001454: 681b ldr r3, [r3, #0]
- 8001456: 4a13 ldr r2, [pc, #76] ; (80014a4 <HAL_TIM_PeriodElapsedCallback+0x100>)
- 8001458: 4293 cmp r3, r2
- 800145a: d106 bne.n 800146a <HAL_TIM_PeriodElapsedCallback+0xc6>
-
- //TODO odometry
-
- HAL_UART_Transmit(&huart6, tx_buffer, 8, 100);
- 800145c: 4b12 ldr r3, [pc, #72] ; (80014a8 <HAL_TIM_PeriodElapsedCallback+0x104>)
- 800145e: 6819 ldr r1, [r3, #0]
- 8001460: 2364 movs r3, #100 ; 0x64
- 8001462: 2208 movs r2, #8
- 8001464: 4811 ldr r0, [pc, #68] ; (80014ac <HAL_TIM_PeriodElapsedCallback+0x108>)
- 8001466: f003 f84f bl 8004508 <HAL_UART_Transmit>
- }
-}
- 800146a: bf00 nop
- 800146c: 3710 adds r7, #16
- 800146e: 46bd mov sp, r7
- 8001470: bd80 pop {r7, pc}
- 8001472: bf00 nop
- 8001474: 40000400 .word 0x40000400
- 8001478: 20000200 .word 0x20000200
- 800147c: 20000220 .word 0x20000220
- 8001480: 20000228 .word 0x20000228
- 8001484: 20000294 .word 0x20000294
- 8001488: 2000029c .word 0x2000029c
- 800148c: 200001e8 .word 0x200001e8
- 8001490: 20000224 .word 0x20000224
- 8001494: 2000024c .word 0x2000024c
- 8001498: 20000298 .word 0x20000298
- 800149c: 200002b4 .word 0x200002b4
- 80014a0: 20000270 .word 0x20000270
- 80014a4: 40001000 .word 0x40001000
- 80014a8: 200002cc .word 0x200002cc
- 80014ac: 20000168 .word 0x20000168
-
-080014b0 <HAL_UART_RxCpltCallback>:
-
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {
- 80014b0: b580 push {r7, lr}
- 80014b2: b086 sub sp, #24
- 80014b4: af00 add r7, sp, #0
- 80014b6: 6078 str r0, [r7, #4]
- odom.UpdateValues(vel_msg.linear_velocity, vel_msg.angular_velocity);
- 80014b8: 4b1c ldr r3, [pc, #112] ; (800152c <HAL_UART_RxCpltCallback+0x7c>)
- 80014ba: edd3 7a00 vldr s15, [r3]
- 80014be: 4b1b ldr r3, [pc, #108] ; (800152c <HAL_UART_RxCpltCallback+0x7c>)
- 80014c0: ed93 7a01 vldr s14, [r3, #4]
- 80014c4: eef0 0a47 vmov.f32 s1, s14
- 80014c8: eeb0 0a67 vmov.f32 s0, s15
- 80014cc: 4818 ldr r0, [pc, #96] ; (8001530 <HAL_UART_RxCpltCallback+0x80>)
- 80014ce: f7ff f90b bl 80006e8 <_ZN8Odometry12UpdateValuesEff>
-
- float left_setpoint = odom.GetLeftVelocity();
- 80014d2: 4817 ldr r0, [pc, #92] ; (8001530 <HAL_UART_RxCpltCallback+0x80>)
- 80014d4: f7ff f948 bl 8000768 <_ZN8Odometry15GetLeftVelocityEv>
- 80014d8: ed87 0a05 vstr s0, [r7, #20]
- float right_setpoint = odom.GetRightVelocity();
- 80014dc: 4814 ldr r0, [pc, #80] ; (8001530 <HAL_UART_RxCpltCallback+0x80>)
- 80014de: f7ff f952 bl 8000786 <_ZN8Odometry16GetRightVelocityEv>
- 80014e2: ed87 0a04 vstr s0, [r7, #16]
-
- left_pid.set(left_setpoint);
- 80014e6: ed97 0a05 vldr s0, [r7, #20]
- 80014ea: 4812 ldr r0, [pc, #72] ; (8001534 <HAL_UART_RxCpltCallback+0x84>)
- 80014ec: f7ff faf6 bl 8000adc <_ZN3Pid3setEf>
- right_pid.set(right_setpoint);
- 80014f0: ed97 0a04 vldr s0, [r7, #16]
- 80014f4: 4810 ldr r0, [pc, #64] ; (8001538 <HAL_UART_RxCpltCallback+0x88>)
- 80014f6: f7ff faf1 bl 8000adc <_ZN3Pid3setEf>
-
- float cross_setpoint = left_setpoint - right_setpoint;
- 80014fa: ed97 7a05 vldr s14, [r7, #20]
- 80014fe: edd7 7a04 vldr s15, [r7, #16]
- 8001502: ee77 7a67 vsub.f32 s15, s14, s15
- 8001506: edc7 7a03 vstr s15, [r7, #12]
- cross_pid.set(cross_setpoint);
- 800150a: ed97 0a03 vldr s0, [r7, #12]
- 800150e: 480b ldr r0, [pc, #44] ; (800153c <HAL_UART_RxCpltCallback+0x8c>)
- 8001510: f7ff fae4 bl 8000adc <_ZN3Pid3setEf>
-
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
- 8001514: 4b0a ldr r3, [pc, #40] ; (8001540 <HAL_UART_RxCpltCallback+0x90>)
- 8001516: 681b ldr r3, [r3, #0]
- 8001518: 2208 movs r2, #8
- 800151a: 4619 mov r1, r3
- 800151c: 4809 ldr r0, [pc, #36] ; (8001544 <HAL_UART_RxCpltCallback+0x94>)
- 800151e: f003 f885 bl 800462c <HAL_UART_Receive_IT>
-
-}
- 8001522: bf00 nop
- 8001524: 3718 adds r7, #24
- 8001526: 46bd mov sp, r7
- 8001528: bd80 pop {r7, pc}
- 800152a: bf00 nop
- 800152c: 200002e0 .word 0x200002e0
- 8001530: 20000218 .word 0x20000218
- 8001534: 20000228 .word 0x20000228
- 8001538: 2000024c .word 0x2000024c
- 800153c: 20000270 .word 0x20000270
- 8001540: 200002d0 .word 0x200002d0
- 8001544: 20000168 .word 0x20000168
-
-08001548 <HAL_GPIO_EXTI_Callback>:
-
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
- 8001548: b580 push {r7, lr}
- 800154a: b082 sub sp, #8
- 800154c: af00 add r7, sp, #0
- 800154e: 4603 mov r3, r0
- 8001550: 80fb strh r3, [r7, #6]
- //Blue user button on the NUCLEO board
- if (GPIO_Pin == GPIO_PIN_13) {
- 8001552: 88fb ldrh r3, [r7, #6]
- 8001554: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8001558: d109 bne.n 800156e <HAL_GPIO_EXTI_Callback+0x26>
- if (mode == 0) {
- 800155a: 4b07 ldr r3, [pc, #28] ; (8001578 <HAL_GPIO_EXTI_Callback+0x30>)
- 800155c: 781b ldrb r3, [r3, #0]
- 800155e: 2b00 cmp r3, #0
- 8001560: d105 bne.n 800156e <HAL_GPIO_EXTI_Callback+0x26>
- mode = 1;
- 8001562: 4b05 ldr r3, [pc, #20] ; (8001578 <HAL_GPIO_EXTI_Callback+0x30>)
- 8001564: 2201 movs r2, #1
- 8001566: 701a strb r2, [r3, #0]
- //Enables TIM3 interrupt (used for PID control)
- HAL_TIM_Base_Start_IT(&htim3);
- 8001568: 4804 ldr r0, [pc, #16] ; (800157c <HAL_GPIO_EXTI_Callback+0x34>)
- 800156a: f001 fec1 bl 80032f0 <HAL_TIM_Base_Start_IT>
-
- }
-
- }
-}
- 800156e: bf00 nop
- 8001570: 3708 adds r7, #8
- 8001572: 46bd mov sp, r7
- 8001574: bd80 pop {r7, pc}
- 8001576: bf00 nop
- 8001578: 200002e8 .word 0x200002e8
- 800157c: 20000068 .word 0x20000068
-
-08001580 <Error_Handler>:
-
-/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void) {
- 8001580: b480 push {r7}
- 8001582: af00 add r7, sp, #0
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
-
- /* USER CODE END Error_Handler_Debug */
-}
- 8001584: bf00 nop
- 8001586: 46bd mov sp, r7
- 8001588: f85d 7b04 ldr.w r7, [sp], #4
- 800158c: 4770 bx lr
- ...
-
-08001590 <_Z41__static_initialization_and_destruction_0ii>:
- 8001590: b580 push {r7, lr}
- 8001592: b086 sub sp, #24
- 8001594: af04 add r7, sp, #16
- 8001596: 6078 str r0, [r7, #4]
- 8001598: 6039 str r1, [r7, #0]
- 800159a: 687b ldr r3, [r7, #4]
- 800159c: 2b01 cmp r3, #1
- 800159e: d148 bne.n 8001632 <_Z41__static_initialization_and_destruction_0ii+0xa2>
- 80015a0: 683b ldr r3, [r7, #0]
- 80015a2: f64f 72ff movw r2, #65535 ; 0xffff
- 80015a6: 4293 cmp r3, r2
- 80015a8: d143 bne.n 8001632 <_Z41__static_initialization_and_destruction_0ii+0xa2>
-Encoder right_encoder = Encoder(&htim5, RIGHT_TICKS_PER_METER);
- 80015aa: 4a24 ldr r2, [pc, #144] ; (800163c <_Z41__static_initialization_and_destruction_0ii+0xac>)
- 80015ac: 4924 ldr r1, [pc, #144] ; (8001640 <_Z41__static_initialization_and_destruction_0ii+0xb0>)
- 80015ae: 4825 ldr r0, [pc, #148] ; (8001644 <_Z41__static_initialization_and_destruction_0ii+0xb4>)
- 80015b0: f7fe ffe9 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>
-Encoder left_encoder = Encoder(&htim2, LEFT_TICKS_PER_METER);
- 80015b4: 4a24 ldr r2, [pc, #144] ; (8001648 <_Z41__static_initialization_and_destruction_0ii+0xb8>)
- 80015b6: 4925 ldr r1, [pc, #148] ; (800164c <_Z41__static_initialization_and_destruction_0ii+0xbc>)
- 80015b8: 4825 ldr r0, [pc, #148] ; (8001650 <_Z41__static_initialization_and_destruction_0ii+0xc0>)
- 80015ba: f7fe ffe4 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>
-Odometry odom = Odometry();
- 80015be: 4825 ldr r0, [pc, #148] ; (8001654 <_Z41__static_initialization_and_destruction_0ii+0xc4>)
- 80015c0: f7ff f87e bl 80006c0 <_ZN8OdometryC1Ev>
-Pid left_pid(180, 200, 0);
- 80015c4: ed9f 1a24 vldr s2, [pc, #144] ; 8001658 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 80015c8: eddf 0a24 vldr s1, [pc, #144] ; 800165c <_Z41__static_initialization_and_destruction_0ii+0xcc>
- 80015cc: ed9f 0a24 vldr s0, [pc, #144] ; 8001660 <_Z41__static_initialization_and_destruction_0ii+0xd0>
- 80015d0: 4824 ldr r0, [pc, #144] ; (8001664 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 80015d2: f7ff fa4f bl 8000a74 <_ZN3PidC1Efff>
-Pid right_pid(185, 195, 0);
- 80015d6: ed9f 1a20 vldr s2, [pc, #128] ; 8001658 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 80015da: eddf 0a23 vldr s1, [pc, #140] ; 8001668 <_Z41__static_initialization_and_destruction_0ii+0xd8>
- 80015de: ed9f 0a23 vldr s0, [pc, #140] ; 800166c <_Z41__static_initialization_and_destruction_0ii+0xdc>
- 80015e2: 4823 ldr r0, [pc, #140] ; (8001670 <_Z41__static_initialization_and_destruction_0ii+0xe0>)
- 80015e4: f7ff fa46 bl 8000a74 <_ZN3PidC1Efff>
-Pid cross_pid(50, 20, 0);
- 80015e8: ed9f 1a1b vldr s2, [pc, #108] ; 8001658 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 80015ec: eef3 0a04 vmov.f32 s1, #52 ; 0x41a00000 20.0
- 80015f0: ed9f 0a20 vldr s0, [pc, #128] ; 8001674 <_Z41__static_initialization_and_destruction_0ii+0xe4>
- 80015f4: 4820 ldr r0, [pc, #128] ; (8001678 <_Z41__static_initialization_and_destruction_0ii+0xe8>)
- 80015f6: f7ff fa3d bl 8000a74 <_ZN3PidC1Efff>
-TIM_CHANNEL_4);
- 80015fa: 230c movs r3, #12
- 80015fc: 9302 str r3, [sp, #8]
- 80015fe: 4b1f ldr r3, [pc, #124] ; (800167c <_Z41__static_initialization_and_destruction_0ii+0xec>)
- 8001600: 9301 str r3, [sp, #4]
- 8001602: f44f 5300 mov.w r3, #8192 ; 0x2000
- 8001606: 9300 str r3, [sp, #0]
- 8001608: 4b1d ldr r3, [pc, #116] ; (8001680 <_Z41__static_initialization_and_destruction_0ii+0xf0>)
- 800160a: f44f 4200 mov.w r2, #32768 ; 0x8000
- 800160e: 491c ldr r1, [pc, #112] ; (8001680 <_Z41__static_initialization_and_destruction_0ii+0xf0>)
- 8001610: 481c ldr r0, [pc, #112] ; (8001684 <_Z41__static_initialization_and_destruction_0ii+0xf4>)
- 8001612: f7ff f8c7 bl 80007a4 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
-TIM_CHANNEL_3);
- 8001616: 2308 movs r3, #8
- 8001618: 9302 str r3, [sp, #8]
- 800161a: 4b18 ldr r3, [pc, #96] ; (800167c <_Z41__static_initialization_and_destruction_0ii+0xec>)
- 800161c: 9301 str r3, [sp, #4]
- 800161e: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8001622: 9300 str r3, [sp, #0]
- 8001624: 4b16 ldr r3, [pc, #88] ; (8001680 <_Z41__static_initialization_and_destruction_0ii+0xf0>)
- 8001626: f44f 4280 mov.w r2, #16384 ; 0x4000
- 800162a: 4915 ldr r1, [pc, #84] ; (8001680 <_Z41__static_initialization_and_destruction_0ii+0xf0>)
- 800162c: 4816 ldr r0, [pc, #88] ; (8001688 <_Z41__static_initialization_and_destruction_0ii+0xf8>)
- 800162e: f7ff f8b9 bl 80007a4 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
-}
- 8001632: bf00 nop
- 8001634: 3708 adds r7, #8
- 8001636: 46bd mov sp, r7
- 8001638: bd80 pop {r7, pc}
- 800163a: bf00 nop
- 800163c: 000300dd .word 0x000300dd
- 8001640: 200000e8 .word 0x200000e8
- 8001644: 200001e8 .word 0x200001e8
- 8001648: 0002fccc .word 0x0002fccc
- 800164c: 20000028 .word 0x20000028
- 8001650: 20000200 .word 0x20000200
- 8001654: 20000218 .word 0x20000218
- 8001658: 00000000 .word 0x00000000
- 800165c: 43480000 .word 0x43480000
- 8001660: 43340000 .word 0x43340000
- 8001664: 20000228 .word 0x20000228
- 8001668: 43430000 .word 0x43430000
- 800166c: 43390000 .word 0x43390000
- 8001670: 2000024c .word 0x2000024c
- 8001674: 42480000 .word 0x42480000
- 8001678: 20000270 .word 0x20000270
- 800167c: 200000a8 .word 0x200000a8
- 8001680: 40021400 .word 0x40021400
- 8001684: 2000029c .word 0x2000029c
- 8001688: 200002b4 .word 0x200002b4
-
-0800168c <_GLOBAL__sub_I_htim2>:
- 800168c: b580 push {r7, lr}
- 800168e: af00 add r7, sp, #0
- 8001690: f64f 71ff movw r1, #65535 ; 0xffff
- 8001694: 2001 movs r0, #1
- 8001696: f7ff ff7b bl 8001590 <_Z41__static_initialization_and_destruction_0ii>
- 800169a: bd80 pop {r7, pc}
-
-0800169c <HAL_MspInit>:
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
- /**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- 800169c: b480 push {r7}
- 800169e: b083 sub sp, #12
- 80016a0: af00 add r7, sp, #0
- /* USER CODE BEGIN MspInit 0 */
-
- /* USER CODE END MspInit 0 */
-
- __HAL_RCC_PWR_CLK_ENABLE();
- 80016a2: 4b0f ldr r3, [pc, #60] ; (80016e0 <HAL_MspInit+0x44>)
- 80016a4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80016a6: 4a0e ldr r2, [pc, #56] ; (80016e0 <HAL_MspInit+0x44>)
- 80016a8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80016ac: 6413 str r3, [r2, #64] ; 0x40
- 80016ae: 4b0c ldr r3, [pc, #48] ; (80016e0 <HAL_MspInit+0x44>)
- 80016b0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80016b2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80016b6: 607b str r3, [r7, #4]
- 80016b8: 687b ldr r3, [r7, #4]
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80016ba: 4b09 ldr r3, [pc, #36] ; (80016e0 <HAL_MspInit+0x44>)
- 80016bc: 6c5b ldr r3, [r3, #68] ; 0x44
- 80016be: 4a08 ldr r2, [pc, #32] ; (80016e0 <HAL_MspInit+0x44>)
- 80016c0: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 80016c4: 6453 str r3, [r2, #68] ; 0x44
- 80016c6: 4b06 ldr r3, [pc, #24] ; (80016e0 <HAL_MspInit+0x44>)
- 80016c8: 6c5b ldr r3, [r3, #68] ; 0x44
- 80016ca: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 80016ce: 603b str r3, [r7, #0]
- 80016d0: 683b ldr r3, [r7, #0]
- /* System interrupt init*/
-
- /* USER CODE BEGIN MspInit 1 */
-
- /* USER CODE END MspInit 1 */
-}
- 80016d2: bf00 nop
- 80016d4: 370c adds r7, #12
- 80016d6: 46bd mov sp, r7
- 80016d8: f85d 7b04 ldr.w r7, [sp], #4
- 80016dc: 4770 bx lr
- 80016de: bf00 nop
- 80016e0: 40023800 .word 0x40023800
-
-080016e4 <HAL_TIM_Encoder_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_encoder: TIM_Encoder handle pointer
-* @retval None
-*/
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
-{
- 80016e4: b580 push {r7, lr}
- 80016e6: b08c sub sp, #48 ; 0x30
- 80016e8: af00 add r7, sp, #0
- 80016ea: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80016ec: f107 031c add.w r3, r7, #28
- 80016f0: 2200 movs r2, #0
- 80016f2: 601a str r2, [r3, #0]
- 80016f4: 605a str r2, [r3, #4]
- 80016f6: 609a str r2, [r3, #8]
- 80016f8: 60da str r2, [r3, #12]
- 80016fa: 611a str r2, [r3, #16]
- if(htim_encoder->Instance==TIM2)
- 80016fc: 687b ldr r3, [r7, #4]
- 80016fe: 681b ldr r3, [r3, #0]
- 8001700: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8001704: d144 bne.n 8001790 <HAL_TIM_Encoder_MspInit+0xac>
- {
- /* USER CODE BEGIN TIM2_MspInit 0 */
-
- /* USER CODE END TIM2_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM2_CLK_ENABLE();
- 8001706: 4b3b ldr r3, [pc, #236] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001708: 6c1b ldr r3, [r3, #64] ; 0x40
- 800170a: 4a3a ldr r2, [pc, #232] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 800170c: f043 0301 orr.w r3, r3, #1
- 8001710: 6413 str r3, [r2, #64] ; 0x40
- 8001712: 4b38 ldr r3, [pc, #224] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001714: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001716: f003 0301 and.w r3, r3, #1
- 800171a: 61bb str r3, [r7, #24]
- 800171c: 69bb ldr r3, [r7, #24]
-
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 800171e: 4b35 ldr r3, [pc, #212] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001720: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001722: 4a34 ldr r2, [pc, #208] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001724: f043 0301 orr.w r3, r3, #1
- 8001728: 6313 str r3, [r2, #48] ; 0x30
- 800172a: 4b32 ldr r3, [pc, #200] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 800172c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800172e: f003 0301 and.w r3, r3, #1
- 8001732: 617b str r3, [r7, #20]
- 8001734: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 8001736: 4b2f ldr r3, [pc, #188] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001738: 6b1b ldr r3, [r3, #48] ; 0x30
- 800173a: 4a2e ldr r2, [pc, #184] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 800173c: f043 0302 orr.w r3, r3, #2
- 8001740: 6313 str r3, [r2, #48] ; 0x30
- 8001742: 4b2c ldr r3, [pc, #176] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001744: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001746: f003 0302 and.w r3, r3, #2
- 800174a: 613b str r3, [r7, #16]
- 800174c: 693b ldr r3, [r7, #16]
- /**TIM2 GPIO Configuration
- PA5 ------> TIM2_CH1
- PB3 ------> TIM2_CH2
- */
- GPIO_InitStruct.Pin = encoder_sx1_Pin;
- 800174e: 2320 movs r3, #32
- 8001750: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001752: 2302 movs r3, #2
- 8001754: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001756: 2300 movs r3, #0
- 8001758: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800175a: 2300 movs r3, #0
- 800175c: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 800175e: 2301 movs r3, #1
- 8001760: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct);
- 8001762: f107 031c add.w r3, r7, #28
- 8001766: 4619 mov r1, r3
- 8001768: 4823 ldr r0, [pc, #140] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x114>)
- 800176a: f000 fb53 bl 8001e14 <HAL_GPIO_Init>
-
- GPIO_InitStruct.Pin = encoder_sx2_Pin;
- 800176e: 2308 movs r3, #8
- 8001770: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001772: 2302 movs r3, #2
- 8001774: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001776: 2300 movs r3, #0
- 8001778: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800177a: 2300 movs r3, #0
- 800177c: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 800177e: 2301 movs r3, #1
- 8001780: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct);
- 8001782: f107 031c add.w r3, r7, #28
- 8001786: 4619 mov r1, r3
- 8001788: 481c ldr r0, [pc, #112] ; (80017fc <HAL_TIM_Encoder_MspInit+0x118>)
- 800178a: f000 fb43 bl 8001e14 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM5_MspInit 1 */
-
- /* USER CODE END TIM5_MspInit 1 */
- }
-
-}
- 800178e: e02c b.n 80017ea <HAL_TIM_Encoder_MspInit+0x106>
- else if(htim_encoder->Instance==TIM5)
- 8001790: 687b ldr r3, [r7, #4]
- 8001792: 681b ldr r3, [r3, #0]
- 8001794: 4a1a ldr r2, [pc, #104] ; (8001800 <HAL_TIM_Encoder_MspInit+0x11c>)
- 8001796: 4293 cmp r3, r2
- 8001798: d127 bne.n 80017ea <HAL_TIM_Encoder_MspInit+0x106>
- __HAL_RCC_TIM5_CLK_ENABLE();
- 800179a: 4b16 ldr r3, [pc, #88] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 800179c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800179e: 4a15 ldr r2, [pc, #84] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 80017a0: f043 0308 orr.w r3, r3, #8
- 80017a4: 6413 str r3, [r2, #64] ; 0x40
- 80017a6: 4b13 ldr r3, [pc, #76] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 80017a8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80017aa: f003 0308 and.w r3, r3, #8
- 80017ae: 60fb str r3, [r7, #12]
- 80017b0: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 80017b2: 4b10 ldr r3, [pc, #64] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 80017b4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80017b6: 4a0f ldr r2, [pc, #60] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 80017b8: f043 0301 orr.w r3, r3, #1
- 80017bc: 6313 str r3, [r2, #48] ; 0x30
- 80017be: 4b0d ldr r3, [pc, #52] ; (80017f4 <HAL_TIM_Encoder_MspInit+0x110>)
- 80017c0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80017c2: f003 0301 and.w r3, r3, #1
- 80017c6: 60bb str r3, [r7, #8]
- 80017c8: 68bb ldr r3, [r7, #8]
- GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin;
- 80017ca: 2303 movs r3, #3
- 80017cc: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80017ce: 2302 movs r3, #2
- 80017d0: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80017d2: 2300 movs r3, #0
- 80017d4: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80017d6: 2300 movs r3, #0
- 80017d8: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
- 80017da: 2302 movs r3, #2
- 80017dc: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 80017de: f107 031c add.w r3, r7, #28
- 80017e2: 4619 mov r1, r3
- 80017e4: 4804 ldr r0, [pc, #16] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x114>)
- 80017e6: f000 fb15 bl 8001e14 <HAL_GPIO_Init>
-}
- 80017ea: bf00 nop
- 80017ec: 3730 adds r7, #48 ; 0x30
- 80017ee: 46bd mov sp, r7
- 80017f0: bd80 pop {r7, pc}
- 80017f2: bf00 nop
- 80017f4: 40023800 .word 0x40023800
- 80017f8: 40020000 .word 0x40020000
- 80017fc: 40020400 .word 0x40020400
- 8001800: 40000c00 .word 0x40000c00
-
-08001804 <HAL_TIM_Base_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
- 8001804: b480 push {r7}
- 8001806: b087 sub sp, #28
- 8001808: af00 add r7, sp, #0
- 800180a: 6078 str r0, [r7, #4]
- if(htim_base->Instance==TIM3)
- 800180c: 687b ldr r3, [r7, #4]
- 800180e: 681b ldr r3, [r3, #0]
- 8001810: 4a1c ldr r2, [pc, #112] ; (8001884 <HAL_TIM_Base_MspInit+0x80>)
- 8001812: 4293 cmp r3, r2
- 8001814: d10c bne.n 8001830 <HAL_TIM_Base_MspInit+0x2c>
- {
- /* USER CODE BEGIN TIM3_MspInit 0 */
-
- /* USER CODE END TIM3_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM3_CLK_ENABLE();
- 8001816: 4b1c ldr r3, [pc, #112] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 8001818: 6c1b ldr r3, [r3, #64] ; 0x40
- 800181a: 4a1b ldr r2, [pc, #108] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 800181c: f043 0302 orr.w r3, r3, #2
- 8001820: 6413 str r3, [r2, #64] ; 0x40
- 8001822: 4b19 ldr r3, [pc, #100] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 8001824: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001826: f003 0302 and.w r3, r3, #2
- 800182a: 617b str r3, [r7, #20]
- 800182c: 697b ldr r3, [r7, #20]
- /* USER CODE BEGIN TIM6_MspInit 1 */
-
- /* USER CODE END TIM6_MspInit 1 */
- }
-
-}
- 800182e: e022 b.n 8001876 <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM4)
- 8001830: 687b ldr r3, [r7, #4]
- 8001832: 681b ldr r3, [r3, #0]
- 8001834: 4a15 ldr r2, [pc, #84] ; (800188c <HAL_TIM_Base_MspInit+0x88>)
- 8001836: 4293 cmp r3, r2
- 8001838: d10c bne.n 8001854 <HAL_TIM_Base_MspInit+0x50>
- __HAL_RCC_TIM4_CLK_ENABLE();
- 800183a: 4b13 ldr r3, [pc, #76] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 800183c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800183e: 4a12 ldr r2, [pc, #72] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 8001840: f043 0304 orr.w r3, r3, #4
- 8001844: 6413 str r3, [r2, #64] ; 0x40
- 8001846: 4b10 ldr r3, [pc, #64] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 8001848: 6c1b ldr r3, [r3, #64] ; 0x40
- 800184a: f003 0304 and.w r3, r3, #4
- 800184e: 613b str r3, [r7, #16]
- 8001850: 693b ldr r3, [r7, #16]
-}
- 8001852: e010 b.n 8001876 <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM6)
- 8001854: 687b ldr r3, [r7, #4]
- 8001856: 681b ldr r3, [r3, #0]
- 8001858: 4a0d ldr r2, [pc, #52] ; (8001890 <HAL_TIM_Base_MspInit+0x8c>)
- 800185a: 4293 cmp r3, r2
- 800185c: d10b bne.n 8001876 <HAL_TIM_Base_MspInit+0x72>
- __HAL_RCC_TIM6_CLK_ENABLE();
- 800185e: 4b0a ldr r3, [pc, #40] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 8001860: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001862: 4a09 ldr r2, [pc, #36] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 8001864: f043 0310 orr.w r3, r3, #16
- 8001868: 6413 str r3, [r2, #64] ; 0x40
- 800186a: 4b07 ldr r3, [pc, #28] ; (8001888 <HAL_TIM_Base_MspInit+0x84>)
- 800186c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800186e: f003 0310 and.w r3, r3, #16
- 8001872: 60fb str r3, [r7, #12]
- 8001874: 68fb ldr r3, [r7, #12]
-}
- 8001876: bf00 nop
- 8001878: 371c adds r7, #28
- 800187a: 46bd mov sp, r7
- 800187c: f85d 7b04 ldr.w r7, [sp], #4
- 8001880: 4770 bx lr
- 8001882: bf00 nop
- 8001884: 40000400 .word 0x40000400
- 8001888: 40023800 .word 0x40023800
- 800188c: 40000800 .word 0x40000800
- 8001890: 40001000 .word 0x40001000
-
-08001894 <HAL_TIM_MspPostInit>:
-
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
-{
- 8001894: b580 push {r7, lr}
- 8001896: b088 sub sp, #32
- 8001898: af00 add r7, sp, #0
- 800189a: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800189c: f107 030c add.w r3, r7, #12
- 80018a0: 2200 movs r2, #0
- 80018a2: 601a str r2, [r3, #0]
- 80018a4: 605a str r2, [r3, #4]
- 80018a6: 609a str r2, [r3, #8]
- 80018a8: 60da str r2, [r3, #12]
- 80018aa: 611a str r2, [r3, #16]
- if(htim->Instance==TIM4)
- 80018ac: 687b ldr r3, [r7, #4]
- 80018ae: 681b ldr r3, [r3, #0]
- 80018b0: 4a11 ldr r2, [pc, #68] ; (80018f8 <HAL_TIM_MspPostInit+0x64>)
- 80018b2: 4293 cmp r3, r2
- 80018b4: d11c bne.n 80018f0 <HAL_TIM_MspPostInit+0x5c>
- {
- /* USER CODE BEGIN TIM4_MspPostInit 0 */
-
- /* USER CODE END TIM4_MspPostInit 0 */
-
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 80018b6: 4b11 ldr r3, [pc, #68] ; (80018fc <HAL_TIM_MspPostInit+0x68>)
- 80018b8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80018ba: 4a10 ldr r2, [pc, #64] ; (80018fc <HAL_TIM_MspPostInit+0x68>)
- 80018bc: f043 0308 orr.w r3, r3, #8
- 80018c0: 6313 str r3, [r2, #48] ; 0x30
- 80018c2: 4b0e ldr r3, [pc, #56] ; (80018fc <HAL_TIM_MspPostInit+0x68>)
- 80018c4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80018c6: f003 0308 and.w r3, r3, #8
- 80018ca: 60bb str r3, [r7, #8]
- 80018cc: 68bb ldr r3, [r7, #8]
- /**TIM4 GPIO Configuration
- PD14 ------> TIM4_CH3
- PD15 ------> TIM4_CH4
- */
- GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin;
- 80018ce: f44f 4340 mov.w r3, #49152 ; 0xc000
- 80018d2: 60fb str r3, [r7, #12]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80018d4: 2302 movs r3, #2
- 80018d6: 613b str r3, [r7, #16]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80018d8: 2300 movs r3, #0
- 80018da: 617b str r3, [r7, #20]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80018dc: 2300 movs r3, #0
- 80018de: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
- 80018e0: 2302 movs r3, #2
- 80018e2: 61fb str r3, [r7, #28]
- HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
- 80018e4: f107 030c add.w r3, r7, #12
- 80018e8: 4619 mov r1, r3
- 80018ea: 4805 ldr r0, [pc, #20] ; (8001900 <HAL_TIM_MspPostInit+0x6c>)
- 80018ec: f000 fa92 bl 8001e14 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM4_MspPostInit 1 */
-
- /* USER CODE END TIM4_MspPostInit 1 */
- }
-
-}
- 80018f0: bf00 nop
- 80018f2: 3720 adds r7, #32
- 80018f4: 46bd mov sp, r7
- 80018f6: bd80 pop {r7, pc}
- 80018f8: 40000800 .word 0x40000800
- 80018fc: 40023800 .word 0x40023800
- 8001900: 40020c00 .word 0x40020c00
-
-08001904 <HAL_UART_MspInit>:
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
- 8001904: b580 push {r7, lr}
- 8001906: b08a sub sp, #40 ; 0x28
- 8001908: af00 add r7, sp, #0
- 800190a: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800190c: f107 0314 add.w r3, r7, #20
- 8001910: 2200 movs r2, #0
- 8001912: 601a str r2, [r3, #0]
- 8001914: 605a str r2, [r3, #4]
- 8001916: 609a str r2, [r3, #8]
- 8001918: 60da str r2, [r3, #12]
- 800191a: 611a str r2, [r3, #16]
- if(huart->Instance==USART6)
- 800191c: 687b ldr r3, [r7, #4]
- 800191e: 681b ldr r3, [r3, #0]
- 8001920: 4a17 ldr r2, [pc, #92] ; (8001980 <HAL_UART_MspInit+0x7c>)
- 8001922: 4293 cmp r3, r2
- 8001924: d127 bne.n 8001976 <HAL_UART_MspInit+0x72>
- {
- /* USER CODE BEGIN USART6_MspInit 0 */
-
- /* USER CODE END USART6_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_USART6_CLK_ENABLE();
- 8001926: 4b17 ldr r3, [pc, #92] ; (8001984 <HAL_UART_MspInit+0x80>)
- 8001928: 6c5b ldr r3, [r3, #68] ; 0x44
- 800192a: 4a16 ldr r2, [pc, #88] ; (8001984 <HAL_UART_MspInit+0x80>)
- 800192c: f043 0320 orr.w r3, r3, #32
- 8001930: 6453 str r3, [r2, #68] ; 0x44
- 8001932: 4b14 ldr r3, [pc, #80] ; (8001984 <HAL_UART_MspInit+0x80>)
- 8001934: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001936: f003 0320 and.w r3, r3, #32
- 800193a: 613b str r3, [r7, #16]
- 800193c: 693b ldr r3, [r7, #16]
-
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 800193e: 4b11 ldr r3, [pc, #68] ; (8001984 <HAL_UART_MspInit+0x80>)
- 8001940: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001942: 4a10 ldr r2, [pc, #64] ; (8001984 <HAL_UART_MspInit+0x80>)
- 8001944: f043 0304 orr.w r3, r3, #4
- 8001948: 6313 str r3, [r2, #48] ; 0x30
- 800194a: 4b0e ldr r3, [pc, #56] ; (8001984 <HAL_UART_MspInit+0x80>)
- 800194c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800194e: f003 0304 and.w r3, r3, #4
- 8001952: 60fb str r3, [r7, #12]
- 8001954: 68fb ldr r3, [r7, #12]
- /**USART6 GPIO Configuration
- PC6 ------> USART6_TX
- PC7 ------> USART6_RX
- */
- GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 8001956: 23c0 movs r3, #192 ; 0xc0
- 8001958: 617b str r3, [r7, #20]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800195a: 2302 movs r3, #2
- 800195c: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800195e: 2300 movs r3, #0
- 8001960: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8001962: 2303 movs r3, #3
- 8001964: 623b str r3, [r7, #32]
- GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
- 8001966: 2308 movs r3, #8
- 8001968: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 800196a: f107 0314 add.w r3, r7, #20
- 800196e: 4619 mov r1, r3
- 8001970: 4805 ldr r0, [pc, #20] ; (8001988 <HAL_UART_MspInit+0x84>)
- 8001972: f000 fa4f bl 8001e14 <HAL_GPIO_Init>
- /* USER CODE BEGIN USART6_MspInit 1 */
-
- /* USER CODE END USART6_MspInit 1 */
- }
-
-}
- 8001976: bf00 nop
- 8001978: 3728 adds r7, #40 ; 0x28
- 800197a: 46bd mov sp, r7
- 800197c: bd80 pop {r7, pc}
- 800197e: bf00 nop
- 8001980: 40011400 .word 0x40011400
- 8001984: 40023800 .word 0x40023800
- 8001988: 40020800 .word 0x40020800
-
-0800198c <NMI_Handler>:
-/******************************************************************************/
-/**
- * @brief This function handles Non maskable interrupt.
- */
-void NMI_Handler(void)
-{
- 800198c: b480 push {r7}
- 800198e: af00 add r7, sp, #0
-
- /* USER CODE END NonMaskableInt_IRQn 0 */
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
- /* USER CODE END NonMaskableInt_IRQn 1 */
-}
- 8001990: bf00 nop
- 8001992: 46bd mov sp, r7
- 8001994: f85d 7b04 ldr.w r7, [sp], #4
- 8001998: 4770 bx lr
-
-0800199a <HardFault_Handler>:
-
-/**
- * @brief This function handles Hard fault interrupt.
- */
-void HardFault_Handler(void)
-{
- 800199a: b480 push {r7}
- 800199c: af00 add r7, sp, #0
- /* USER CODE BEGIN HardFault_IRQn 0 */
-
- /* USER CODE END HardFault_IRQn 0 */
- while (1)
- 800199e: e7fe b.n 800199e <HardFault_Handler+0x4>
-
-080019a0 <MemManage_Handler>:
-
-/**
- * @brief This function handles Memory management fault.
- */
-void MemManage_Handler(void)
-{
- 80019a0: b480 push {r7}
- 80019a2: af00 add r7, sp, #0
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
- /* USER CODE END MemoryManagement_IRQn 0 */
- while (1)
- 80019a4: e7fe b.n 80019a4 <MemManage_Handler+0x4>
-
-080019a6 <BusFault_Handler>:
-
-/**
- * @brief This function handles Pre-fetch fault, memory access fault.
- */
-void BusFault_Handler(void)
-{
- 80019a6: b480 push {r7}
- 80019a8: af00 add r7, sp, #0
- /* USER CODE BEGIN BusFault_IRQn 0 */
-
- /* USER CODE END BusFault_IRQn 0 */
- while (1)
- 80019aa: e7fe b.n 80019aa <BusFault_Handler+0x4>
-
-080019ac <UsageFault_Handler>:
-
-/**
- * @brief This function handles Undefined instruction or illegal state.
- */
-void UsageFault_Handler(void)
-{
- 80019ac: b480 push {r7}
- 80019ae: af00 add r7, sp, #0
- /* USER CODE BEGIN UsageFault_IRQn 0 */
-
- /* USER CODE END UsageFault_IRQn 0 */
- while (1)
- 80019b0: e7fe b.n 80019b0 <UsageFault_Handler+0x4>
-
-080019b2 <SVC_Handler>:
-
-/**
- * @brief This function handles System service call via SWI instruction.
- */
-void SVC_Handler(void)
-{
- 80019b2: b480 push {r7}
- 80019b4: af00 add r7, sp, #0
-
- /* USER CODE END SVCall_IRQn 0 */
- /* USER CODE BEGIN SVCall_IRQn 1 */
-
- /* USER CODE END SVCall_IRQn 1 */
-}
- 80019b6: bf00 nop
- 80019b8: 46bd mov sp, r7
- 80019ba: f85d 7b04 ldr.w r7, [sp], #4
- 80019be: 4770 bx lr
-
-080019c0 <DebugMon_Handler>:
-
-/**
- * @brief This function handles Debug monitor.
- */
-void DebugMon_Handler(void)
-{
- 80019c0: b480 push {r7}
- 80019c2: af00 add r7, sp, #0
-
- /* USER CODE END DebugMonitor_IRQn 0 */
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
- /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 80019c4: bf00 nop
- 80019c6: 46bd mov sp, r7
- 80019c8: f85d 7b04 ldr.w r7, [sp], #4
- 80019cc: 4770 bx lr
-
-080019ce <PendSV_Handler>:
-
-/**
- * @brief This function handles Pendable request for system service.
- */
-void PendSV_Handler(void)
-{
- 80019ce: b480 push {r7}
- 80019d0: af00 add r7, sp, #0
-
- /* USER CODE END PendSV_IRQn 0 */
- /* USER CODE BEGIN PendSV_IRQn 1 */
-
- /* USER CODE END PendSV_IRQn 1 */
-}
- 80019d2: bf00 nop
- 80019d4: 46bd mov sp, r7
- 80019d6: f85d 7b04 ldr.w r7, [sp], #4
- 80019da: 4770 bx lr
-
-080019dc <SysTick_Handler>:
-
-/**
- * @brief This function handles System tick timer.
- */
-void SysTick_Handler(void)
-{
- 80019dc: b580 push {r7, lr}
- 80019de: af00 add r7, sp, #0
- /* USER CODE BEGIN SysTick_IRQn 0 */
-
- /* USER CODE END SysTick_IRQn 0 */
- HAL_IncTick();
- 80019e0: f000 f8c4 bl 8001b6c <HAL_IncTick>
- /* USER CODE BEGIN SysTick_IRQn 1 */
-
- /* USER CODE END SysTick_IRQn 1 */
-}
- 80019e4: bf00 nop
- 80019e6: bd80 pop {r7, pc}
-
-080019e8 <TIM3_IRQHandler>:
-
-/**
- * @brief This function handles TIM3 global interrupt.
- */
-void TIM3_IRQHandler(void)
-{
- 80019e8: b580 push {r7, lr}
- 80019ea: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM3_IRQn 0 */
-
- /* USER CODE END TIM3_IRQn 0 */
- HAL_TIM_IRQHandler(&htim3);
- 80019ec: 4802 ldr r0, [pc, #8] ; (80019f8 <TIM3_IRQHandler+0x10>)
- 80019ee: f001 fdec bl 80035ca <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM3_IRQn 1 */
-
- /* USER CODE END TIM3_IRQn 1 */
-}
- 80019f2: bf00 nop
- 80019f4: bd80 pop {r7, pc}
- 80019f6: bf00 nop
- 80019f8: 20000068 .word 0x20000068
-
-080019fc <EXTI15_10_IRQHandler>:
-
-/**
- * @brief This function handles EXTI line[15:10] interrupts.
- */
-void EXTI15_10_IRQHandler(void)
-{
- 80019fc: b580 push {r7, lr}
- 80019fe: af00 add r7, sp, #0
- /* USER CODE BEGIN EXTI15_10_IRQn 0 */
-
- /* USER CODE END EXTI15_10_IRQn 0 */
- HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
- 8001a00: f44f 5000 mov.w r0, #8192 ; 0x2000
- 8001a04: f000 fbca bl 800219c <HAL_GPIO_EXTI_IRQHandler>
- /* USER CODE BEGIN EXTI15_10_IRQn 1 */
-
- /* USER CODE END EXTI15_10_IRQn 1 */
-}
- 8001a08: bf00 nop
- 8001a0a: bd80 pop {r7, pc}
-
-08001a0c <TIM6_DAC_IRQHandler>:
-
-/**
- * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
- */
-void TIM6_DAC_IRQHandler(void)
-{
- 8001a0c: b580 push {r7, lr}
- 8001a0e: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
-
- /* USER CODE END TIM6_DAC_IRQn 0 */
- HAL_TIM_IRQHandler(&htim6);
- 8001a10: 4802 ldr r0, [pc, #8] ; (8001a1c <TIM6_DAC_IRQHandler+0x10>)
- 8001a12: f001 fdda bl 80035ca <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
-
- /* USER CODE END TIM6_DAC_IRQn 1 */
-}
- 8001a16: bf00 nop
- 8001a18: bd80 pop {r7, pc}
- 8001a1a: bf00 nop
- 8001a1c: 20000128 .word 0x20000128
-
-08001a20 <USART6_IRQHandler>:
-
-/**
- * @brief This function handles USART6 global interrupt.
- */
-void USART6_IRQHandler(void)
-{
- 8001a20: b580 push {r7, lr}
- 8001a22: af00 add r7, sp, #0
- /* USER CODE BEGIN USART6_IRQn 0 */
-
- /* USER CODE END USART6_IRQn 0 */
- HAL_UART_IRQHandler(&huart6);
- 8001a24: 4802 ldr r0, [pc, #8] ; (8001a30 <USART6_IRQHandler+0x10>)
- 8001a26: f002 fea3 bl 8004770 <HAL_UART_IRQHandler>
- /* USER CODE BEGIN USART6_IRQn 1 */
-
- /* USER CODE END USART6_IRQn 1 */
-}
- 8001a2a: bf00 nop
- 8001a2c: bd80 pop {r7, pc}
- 8001a2e: bf00 nop
- 8001a30: 20000168 .word 0x20000168
-
-08001a34 <SystemInit>:
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- 8001a34: b480 push {r7}
- 8001a36: af00 add r7, sp, #0
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 8001a38: 4b15 ldr r3, [pc, #84] ; (8001a90 <SystemInit+0x5c>)
- 8001a3a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001a3e: 4a14 ldr r2, [pc, #80] ; (8001a90 <SystemInit+0x5c>)
- 8001a40: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 8001a44: f8c2 3088 str.w r3, [r2, #136] ; 0x88
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
- 8001a48: 4b12 ldr r3, [pc, #72] ; (8001a94 <SystemInit+0x60>)
- 8001a4a: 681b ldr r3, [r3, #0]
- 8001a4c: 4a11 ldr r2, [pc, #68] ; (8001a94 <SystemInit+0x60>)
- 8001a4e: f043 0301 orr.w r3, r3, #1
- 8001a52: 6013 str r3, [r2, #0]
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
- 8001a54: 4b0f ldr r3, [pc, #60] ; (8001a94 <SystemInit+0x60>)
- 8001a56: 2200 movs r2, #0
- 8001a58: 609a str r2, [r3, #8]
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8001a5a: 4b0e ldr r3, [pc, #56] ; (8001a94 <SystemInit+0x60>)
- 8001a5c: 681a ldr r2, [r3, #0]
- 8001a5e: 490d ldr r1, [pc, #52] ; (8001a94 <SystemInit+0x60>)
- 8001a60: 4b0d ldr r3, [pc, #52] ; (8001a98 <SystemInit+0x64>)
- 8001a62: 4013 ands r3, r2
- 8001a64: 600b str r3, [r1, #0]
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
- 8001a66: 4b0b ldr r3, [pc, #44] ; (8001a94 <SystemInit+0x60>)
- 8001a68: 4a0c ldr r2, [pc, #48] ; (8001a9c <SystemInit+0x68>)
- 8001a6a: 605a str r2, [r3, #4]
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
- 8001a6c: 4b09 ldr r3, [pc, #36] ; (8001a94 <SystemInit+0x60>)
- 8001a6e: 681b ldr r3, [r3, #0]
- 8001a70: 4a08 ldr r2, [pc, #32] ; (8001a94 <SystemInit+0x60>)
- 8001a72: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8001a76: 6013 str r3, [r2, #0]
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
- 8001a78: 4b06 ldr r3, [pc, #24] ; (8001a94 <SystemInit+0x60>)
- 8001a7a: 2200 movs r2, #0
- 8001a7c: 60da str r2, [r3, #12]
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8001a7e: 4b04 ldr r3, [pc, #16] ; (8001a90 <SystemInit+0x5c>)
- 8001a80: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 8001a84: 609a str r2, [r3, #8]
-#endif
-}
- 8001a86: bf00 nop
- 8001a88: 46bd mov sp, r7
- 8001a8a: f85d 7b04 ldr.w r7, [sp], #4
- 8001a8e: 4770 bx lr
- 8001a90: e000ed00 .word 0xe000ed00
- 8001a94: 40023800 .word 0x40023800
- 8001a98: fef6ffff .word 0xfef6ffff
- 8001a9c: 24003010 .word 0x24003010
-
-08001aa0 <Reset_Handler>:
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
- 8001aa0: f8df d034 ldr.w sp, [pc, #52] ; 8001ad8 <LoopFillZerobss+0x14>
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- 8001aa4: 2100 movs r1, #0
- b LoopCopyDataInit
- 8001aa6: e003 b.n 8001ab0 <LoopCopyDataInit>
-
-08001aa8 <CopyDataInit>:
-
-CopyDataInit:
- ldr r3, =_sidata
- 8001aa8: 4b0c ldr r3, [pc, #48] ; (8001adc <LoopFillZerobss+0x18>)
- ldr r3, [r3, r1]
- 8001aaa: 585b ldr r3, [r3, r1]
- str r3, [r0, r1]
- 8001aac: 5043 str r3, [r0, r1]
- adds r1, r1, #4
- 8001aae: 3104 adds r1, #4
-
-08001ab0 <LoopCopyDataInit>:
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- 8001ab0: 480b ldr r0, [pc, #44] ; (8001ae0 <LoopFillZerobss+0x1c>)
- ldr r3, =_edata
- 8001ab2: 4b0c ldr r3, [pc, #48] ; (8001ae4 <LoopFillZerobss+0x20>)
- adds r2, r0, r1
- 8001ab4: 1842 adds r2, r0, r1
- cmp r2, r3
- 8001ab6: 429a cmp r2, r3
- bcc CopyDataInit
- 8001ab8: d3f6 bcc.n 8001aa8 <CopyDataInit>
- ldr r2, =_sbss
- 8001aba: 4a0b ldr r2, [pc, #44] ; (8001ae8 <LoopFillZerobss+0x24>)
- b LoopFillZerobss
- 8001abc: e002 b.n 8001ac4 <LoopFillZerobss>
-
-08001abe <FillZerobss>:
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- 8001abe: 2300 movs r3, #0
- str r3, [r2], #4
- 8001ac0: f842 3b04 str.w r3, [r2], #4
-
-08001ac4 <LoopFillZerobss>:
-
-LoopFillZerobss:
- ldr r3, = _ebss
- 8001ac4: 4b09 ldr r3, [pc, #36] ; (8001aec <LoopFillZerobss+0x28>)
- cmp r2, r3
- 8001ac6: 429a cmp r2, r3
- bcc FillZerobss
- 8001ac8: d3f9 bcc.n 8001abe <FillZerobss>
-
-/* Call the clock system initialization function.*/
- bl SystemInit
- 8001aca: f7ff ffb3 bl 8001a34 <SystemInit>
-/* Call static constructors */
- bl __libc_init_array
- 8001ace: f003 fc31 bl 8005334 <__libc_init_array>
-/* Call the application's entry point.*/
- bl main
- 8001ad2: f7ff f86b bl 8000bac <main>
- bx lr
- 8001ad6: 4770 bx lr
- ldr sp, =_estack /* set stack pointer */
- 8001ad8: 20080000 .word 0x20080000
- ldr r3, =_sidata
- 8001adc: 080053d0 .word 0x080053d0
- ldr r0, =_sdata
- 8001ae0: 20000000 .word 0x20000000
- ldr r3, =_edata
- 8001ae4: 2000000c .word 0x2000000c
- ldr r2, =_sbss
- 8001ae8: 2000000c .word 0x2000000c
- ldr r3, = _ebss
- 8001aec: 200002f0 .word 0x200002f0
-
-08001af0 <ADC_IRQHandler>:
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- 8001af0: e7fe b.n 8001af0 <ADC_IRQHandler>
-
-08001af2 <HAL_Init>:
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8001af2: b580 push {r7, lr}
- 8001af4: af00 add r7, sp, #0
-#if (PREFETCH_ENABLE != 0U)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8001af6: 2003 movs r0, #3
- 8001af8: f000 f928 bl 8001d4c <HAL_NVIC_SetPriorityGrouping>
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
- 8001afc: 2000 movs r0, #0
- 8001afe: f000 f805 bl 8001b0c <HAL_InitTick>
-
- /* Init the low level hardware */
- HAL_MspInit();
- 8001b02: f7ff fdcb bl 800169c <HAL_MspInit>
-
- /* Return function status */
- return HAL_OK;
- 8001b06: 2300 movs r3, #0
-}
- 8001b08: 4618 mov r0, r3
- 8001b0a: bd80 pop {r7, pc}
-
-08001b0c <HAL_InitTick>:
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- 8001b0c: b580 push {r7, lr}
- 8001b0e: b082 sub sp, #8
- 8001b10: af00 add r7, sp, #0
- 8001b12: 6078 str r0, [r7, #4]
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8001b14: 4b12 ldr r3, [pc, #72] ; (8001b60 <HAL_InitTick+0x54>)
- 8001b16: 681a ldr r2, [r3, #0]
- 8001b18: 4b12 ldr r3, [pc, #72] ; (8001b64 <HAL_InitTick+0x58>)
- 8001b1a: 781b ldrb r3, [r3, #0]
- 8001b1c: 4619 mov r1, r3
- 8001b1e: f44f 737a mov.w r3, #1000 ; 0x3e8
- 8001b22: fbb3 f3f1 udiv r3, r3, r1
- 8001b26: fbb2 f3f3 udiv r3, r2, r3
- 8001b2a: 4618 mov r0, r3
- 8001b2c: f000 f943 bl 8001db6 <HAL_SYSTICK_Config>
- 8001b30: 4603 mov r3, r0
- 8001b32: 2b00 cmp r3, #0
- 8001b34: d001 beq.n 8001b3a <HAL_InitTick+0x2e>
- {
- return HAL_ERROR;
- 8001b36: 2301 movs r3, #1
- 8001b38: e00e b.n 8001b58 <HAL_InitTick+0x4c>
- }
-
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8001b3a: 687b ldr r3, [r7, #4]
- 8001b3c: 2b0f cmp r3, #15
- 8001b3e: d80a bhi.n 8001b56 <HAL_InitTick+0x4a>
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8001b40: 2200 movs r2, #0
- 8001b42: 6879 ldr r1, [r7, #4]
- 8001b44: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001b48: f000 f90b bl 8001d62 <HAL_NVIC_SetPriority>
- uwTickPrio = TickPriority;
- 8001b4c: 4a06 ldr r2, [pc, #24] ; (8001b68 <HAL_InitTick+0x5c>)
- 8001b4e: 687b ldr r3, [r7, #4]
- 8001b50: 6013 str r3, [r2, #0]
- {
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
- 8001b52: 2300 movs r3, #0
- 8001b54: e000 b.n 8001b58 <HAL_InitTick+0x4c>
- return HAL_ERROR;
- 8001b56: 2301 movs r3, #1
-}
- 8001b58: 4618 mov r0, r3
- 8001b5a: 3708 adds r7, #8
- 8001b5c: 46bd mov sp, r7
- 8001b5e: bd80 pop {r7, pc}
- 8001b60: 20000000 .word 0x20000000
- 8001b64: 20000008 .word 0x20000008
- 8001b68: 20000004 .word 0x20000004
-
-08001b6c <HAL_IncTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- 8001b6c: b480 push {r7}
- 8001b6e: af00 add r7, sp, #0
- uwTick += uwTickFreq;
- 8001b70: 4b06 ldr r3, [pc, #24] ; (8001b8c <HAL_IncTick+0x20>)
- 8001b72: 781b ldrb r3, [r3, #0]
- 8001b74: 461a mov r2, r3
- 8001b76: 4b06 ldr r3, [pc, #24] ; (8001b90 <HAL_IncTick+0x24>)
- 8001b78: 681b ldr r3, [r3, #0]
- 8001b7a: 4413 add r3, r2
- 8001b7c: 4a04 ldr r2, [pc, #16] ; (8001b90 <HAL_IncTick+0x24>)
- 8001b7e: 6013 str r3, [r2, #0]
-}
- 8001b80: bf00 nop
- 8001b82: 46bd mov sp, r7
- 8001b84: f85d 7b04 ldr.w r7, [sp], #4
- 8001b88: 4770 bx lr
- 8001b8a: bf00 nop
- 8001b8c: 20000008 .word 0x20000008
- 8001b90: 200002ec .word 0x200002ec
-
-08001b94 <HAL_GetTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- 8001b94: b480 push {r7}
- 8001b96: af00 add r7, sp, #0
- return uwTick;
- 8001b98: 4b03 ldr r3, [pc, #12] ; (8001ba8 <HAL_GetTick+0x14>)
- 8001b9a: 681b ldr r3, [r3, #0]
-}
- 8001b9c: 4618 mov r0, r3
- 8001b9e: 46bd mov sp, r7
- 8001ba0: f85d 7b04 ldr.w r7, [sp], #4
- 8001ba4: 4770 bx lr
- 8001ba6: bf00 nop
- 8001ba8: 200002ec .word 0x200002ec
-
-08001bac <__NVIC_SetPriorityGrouping>:
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001bac: b480 push {r7}
- 8001bae: b085 sub sp, #20
- 8001bb0: af00 add r7, sp, #0
- 8001bb2: 6078 str r0, [r7, #4]
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001bb4: 687b ldr r3, [r7, #4]
- 8001bb6: f003 0307 and.w r3, r3, #7
- 8001bba: 60fb str r3, [r7, #12]
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- 8001bbc: 4b0b ldr r3, [pc, #44] ; (8001bec <__NVIC_SetPriorityGrouping+0x40>)
- 8001bbe: 68db ldr r3, [r3, #12]
- 8001bc0: 60bb str r3, [r7, #8]
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 8001bc2: 68ba ldr r2, [r7, #8]
- 8001bc4: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8001bc8: 4013 ands r3, r2
- 8001bca: 60bb str r3, [r7, #8]
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8001bcc: 68fb ldr r3, [r7, #12]
- 8001bce: 021a lsls r2, r3, #8
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8001bd0: 68bb ldr r3, [r7, #8]
- 8001bd2: 431a orrs r2, r3
- reg_value = (reg_value |
- 8001bd4: 4b06 ldr r3, [pc, #24] ; (8001bf0 <__NVIC_SetPriorityGrouping+0x44>)
- 8001bd6: 4313 orrs r3, r2
- 8001bd8: 60bb str r3, [r7, #8]
- SCB->AIRCR = reg_value;
- 8001bda: 4a04 ldr r2, [pc, #16] ; (8001bec <__NVIC_SetPriorityGrouping+0x40>)
- 8001bdc: 68bb ldr r3, [r7, #8]
- 8001bde: 60d3 str r3, [r2, #12]
-}
- 8001be0: bf00 nop
- 8001be2: 3714 adds r7, #20
- 8001be4: 46bd mov sp, r7
- 8001be6: f85d 7b04 ldr.w r7, [sp], #4
- 8001bea: 4770 bx lr
- 8001bec: e000ed00 .word 0xe000ed00
- 8001bf0: 05fa0000 .word 0x05fa0000
-
-08001bf4 <__NVIC_GetPriorityGrouping>:
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- 8001bf4: b480 push {r7}
- 8001bf6: af00 add r7, sp, #0
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8001bf8: 4b04 ldr r3, [pc, #16] ; (8001c0c <__NVIC_GetPriorityGrouping+0x18>)
- 8001bfa: 68db ldr r3, [r3, #12]
- 8001bfc: 0a1b lsrs r3, r3, #8
- 8001bfe: f003 0307 and.w r3, r3, #7
-}
- 8001c02: 4618 mov r0, r3
- 8001c04: 46bd mov sp, r7
- 8001c06: f85d 7b04 ldr.w r7, [sp], #4
- 8001c0a: 4770 bx lr
- 8001c0c: e000ed00 .word 0xe000ed00
-
-08001c10 <__NVIC_EnableIRQ>:
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001c10: b480 push {r7}
- 8001c12: b083 sub sp, #12
- 8001c14: af00 add r7, sp, #0
- 8001c16: 4603 mov r3, r0
- 8001c18: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001c1a: f997 3007 ldrsb.w r3, [r7, #7]
- 8001c1e: 2b00 cmp r3, #0
- 8001c20: db0b blt.n 8001c3a <__NVIC_EnableIRQ+0x2a>
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 8001c22: 79fb ldrb r3, [r7, #7]
- 8001c24: f003 021f and.w r2, r3, #31
- 8001c28: 4907 ldr r1, [pc, #28] ; (8001c48 <__NVIC_EnableIRQ+0x38>)
- 8001c2a: f997 3007 ldrsb.w r3, [r7, #7]
- 8001c2e: 095b lsrs r3, r3, #5
- 8001c30: 2001 movs r0, #1
- 8001c32: fa00 f202 lsl.w r2, r0, r2
- 8001c36: f841 2023 str.w r2, [r1, r3, lsl #2]
- }
-}
- 8001c3a: bf00 nop
- 8001c3c: 370c adds r7, #12
- 8001c3e: 46bd mov sp, r7
- 8001c40: f85d 7b04 ldr.w r7, [sp], #4
- 8001c44: 4770 bx lr
- 8001c46: bf00 nop
- 8001c48: e000e100 .word 0xe000e100
-
-08001c4c <__NVIC_SetPriority>:
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- 8001c4c: b480 push {r7}
- 8001c4e: b083 sub sp, #12
- 8001c50: af00 add r7, sp, #0
- 8001c52: 4603 mov r3, r0
- 8001c54: 6039 str r1, [r7, #0]
- 8001c56: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001c58: f997 3007 ldrsb.w r3, [r7, #7]
- 8001c5c: 2b00 cmp r3, #0
- 8001c5e: db0a blt.n 8001c76 <__NVIC_SetPriority+0x2a>
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001c60: 683b ldr r3, [r7, #0]
- 8001c62: b2da uxtb r2, r3
- 8001c64: 490c ldr r1, [pc, #48] ; (8001c98 <__NVIC_SetPriority+0x4c>)
- 8001c66: f997 3007 ldrsb.w r3, [r7, #7]
- 8001c6a: 0112 lsls r2, r2, #4
- 8001c6c: b2d2 uxtb r2, r2
- 8001c6e: 440b add r3, r1
- 8001c70: f883 2300 strb.w r2, [r3, #768] ; 0x300
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
- 8001c74: e00a b.n 8001c8c <__NVIC_SetPriority+0x40>
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001c76: 683b ldr r3, [r7, #0]
- 8001c78: b2da uxtb r2, r3
- 8001c7a: 4908 ldr r1, [pc, #32] ; (8001c9c <__NVIC_SetPriority+0x50>)
- 8001c7c: 79fb ldrb r3, [r7, #7]
- 8001c7e: f003 030f and.w r3, r3, #15
- 8001c82: 3b04 subs r3, #4
- 8001c84: 0112 lsls r2, r2, #4
- 8001c86: b2d2 uxtb r2, r2
- 8001c88: 440b add r3, r1
- 8001c8a: 761a strb r2, [r3, #24]
-}
- 8001c8c: bf00 nop
- 8001c8e: 370c adds r7, #12
- 8001c90: 46bd mov sp, r7
- 8001c92: f85d 7b04 ldr.w r7, [sp], #4
- 8001c96: 4770 bx lr
- 8001c98: e000e100 .word 0xe000e100
- 8001c9c: e000ed00 .word 0xe000ed00
-
-08001ca0 <NVIC_EncodePriority>:
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001ca0: b480 push {r7}
- 8001ca2: b089 sub sp, #36 ; 0x24
- 8001ca4: af00 add r7, sp, #0
- 8001ca6: 60f8 str r0, [r7, #12]
- 8001ca8: 60b9 str r1, [r7, #8]
- 8001caa: 607a str r2, [r7, #4]
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001cac: 68fb ldr r3, [r7, #12]
- 8001cae: f003 0307 and.w r3, r3, #7
- 8001cb2: 61fb str r3, [r7, #28]
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8001cb4: 69fb ldr r3, [r7, #28]
- 8001cb6: f1c3 0307 rsb r3, r3, #7
- 8001cba: 2b04 cmp r3, #4
- 8001cbc: bf28 it cs
- 8001cbe: 2304 movcs r3, #4
- 8001cc0: 61bb str r3, [r7, #24]
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8001cc2: 69fb ldr r3, [r7, #28]
- 8001cc4: 3304 adds r3, #4
- 8001cc6: 2b06 cmp r3, #6
- 8001cc8: d902 bls.n 8001cd0 <NVIC_EncodePriority+0x30>
- 8001cca: 69fb ldr r3, [r7, #28]
- 8001ccc: 3b03 subs r3, #3
- 8001cce: e000 b.n 8001cd2 <NVIC_EncodePriority+0x32>
- 8001cd0: 2300 movs r3, #0
- 8001cd2: 617b str r3, [r7, #20]
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001cd4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8001cd8: 69bb ldr r3, [r7, #24]
- 8001cda: fa02 f303 lsl.w r3, r2, r3
- 8001cde: 43da mvns r2, r3
- 8001ce0: 68bb ldr r3, [r7, #8]
- 8001ce2: 401a ands r2, r3
- 8001ce4: 697b ldr r3, [r7, #20]
- 8001ce6: 409a lsls r2, r3
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8001ce8: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 8001cec: 697b ldr r3, [r7, #20]
- 8001cee: fa01 f303 lsl.w r3, r1, r3
- 8001cf2: 43d9 mvns r1, r3
- 8001cf4: 687b ldr r3, [r7, #4]
- 8001cf6: 400b ands r3, r1
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001cf8: 4313 orrs r3, r2
- );
-}
- 8001cfa: 4618 mov r0, r3
- 8001cfc: 3724 adds r7, #36 ; 0x24
- 8001cfe: 46bd mov sp, r7
- 8001d00: f85d 7b04 ldr.w r7, [sp], #4
- 8001d04: 4770 bx lr
- ...
-
-08001d08 <SysTick_Config>:
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 8001d08: b580 push {r7, lr}
- 8001d0a: b082 sub sp, #8
- 8001d0c: af00 add r7, sp, #0
- 8001d0e: 6078 str r0, [r7, #4]
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8001d10: 687b ldr r3, [r7, #4]
- 8001d12: 3b01 subs r3, #1
- 8001d14: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8001d18: d301 bcc.n 8001d1e <SysTick_Config+0x16>
- {
- return (1UL); /* Reload value impossible */
- 8001d1a: 2301 movs r3, #1
- 8001d1c: e00f b.n 8001d3e <SysTick_Config+0x36>
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8001d1e: 4a0a ldr r2, [pc, #40] ; (8001d48 <SysTick_Config+0x40>)
- 8001d20: 687b ldr r3, [r7, #4]
- 8001d22: 3b01 subs r3, #1
- 8001d24: 6053 str r3, [r2, #4]
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8001d26: 210f movs r1, #15
- 8001d28: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001d2c: f7ff ff8e bl 8001c4c <__NVIC_SetPriority>
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8001d30: 4b05 ldr r3, [pc, #20] ; (8001d48 <SysTick_Config+0x40>)
- 8001d32: 2200 movs r2, #0
- 8001d34: 609a str r2, [r3, #8]
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001d36: 4b04 ldr r3, [pc, #16] ; (8001d48 <SysTick_Config+0x40>)
- 8001d38: 2207 movs r2, #7
- 8001d3a: 601a str r2, [r3, #0]
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
- 8001d3c: 2300 movs r3, #0
-}
- 8001d3e: 4618 mov r0, r3
- 8001d40: 3708 adds r7, #8
- 8001d42: 46bd mov sp, r7
- 8001d44: bd80 pop {r7, pc}
- 8001d46: bf00 nop
- 8001d48: e000e010 .word 0xe000e010
-
-08001d4c <HAL_NVIC_SetPriorityGrouping>:
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001d4c: b580 push {r7, lr}
- 8001d4e: b082 sub sp, #8
- 8001d50: af00 add r7, sp, #0
- 8001d52: 6078 str r0, [r7, #4]
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
- 8001d54: 6878 ldr r0, [r7, #4]
- 8001d56: f7ff ff29 bl 8001bac <__NVIC_SetPriorityGrouping>
-}
- 8001d5a: bf00 nop
- 8001d5c: 3708 adds r7, #8
- 8001d5e: 46bd mov sp, r7
- 8001d60: bd80 pop {r7, pc}
-
-08001d62 <HAL_NVIC_SetPriority>:
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001d62: b580 push {r7, lr}
- 8001d64: b086 sub sp, #24
- 8001d66: af00 add r7, sp, #0
- 8001d68: 4603 mov r3, r0
- 8001d6a: 60b9 str r1, [r7, #8]
- 8001d6c: 607a str r2, [r7, #4]
- 8001d6e: 73fb strb r3, [r7, #15]
- uint32_t prioritygroup = 0x00;
- 8001d70: 2300 movs r3, #0
- 8001d72: 617b str r3, [r7, #20]
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
- 8001d74: f7ff ff3e bl 8001bf4 <__NVIC_GetPriorityGrouping>
- 8001d78: 6178 str r0, [r7, #20]
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8001d7a: 687a ldr r2, [r7, #4]
- 8001d7c: 68b9 ldr r1, [r7, #8]
- 8001d7e: 6978 ldr r0, [r7, #20]
- 8001d80: f7ff ff8e bl 8001ca0 <NVIC_EncodePriority>
- 8001d84: 4602 mov r2, r0
- 8001d86: f997 300f ldrsb.w r3, [r7, #15]
- 8001d8a: 4611 mov r1, r2
- 8001d8c: 4618 mov r0, r3
- 8001d8e: f7ff ff5d bl 8001c4c <__NVIC_SetPriority>
-}
- 8001d92: bf00 nop
- 8001d94: 3718 adds r7, #24
- 8001d96: 46bd mov sp, r7
- 8001d98: bd80 pop {r7, pc}
-
-08001d9a <HAL_NVIC_EnableIRQ>:
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001d9a: b580 push {r7, lr}
- 8001d9c: b082 sub sp, #8
- 8001d9e: af00 add r7, sp, #0
- 8001da0: 4603 mov r3, r0
- 8001da2: 71fb strb r3, [r7, #7]
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
- 8001da4: f997 3007 ldrsb.w r3, [r7, #7]
- 8001da8: 4618 mov r0, r3
- 8001daa: f7ff ff31 bl 8001c10 <__NVIC_EnableIRQ>
-}
- 8001dae: bf00 nop
- 8001db0: 3708 adds r7, #8
- 8001db2: 46bd mov sp, r7
- 8001db4: bd80 pop {r7, pc}
-
-08001db6 <HAL_SYSTICK_Config>:
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 8001db6: b580 push {r7, lr}
- 8001db8: b082 sub sp, #8
- 8001dba: af00 add r7, sp, #0
- 8001dbc: 6078 str r0, [r7, #4]
- return SysTick_Config(TicksNumb);
- 8001dbe: 6878 ldr r0, [r7, #4]
- 8001dc0: f7ff ffa2 bl 8001d08 <SysTick_Config>
- 8001dc4: 4603 mov r3, r0
-}
- 8001dc6: 4618 mov r0, r3
- 8001dc8: 3708 adds r7, #8
- 8001dca: 46bd mov sp, r7
- 8001dcc: bd80 pop {r7, pc}
-
-08001dce <HAL_DMA_Abort_IT>:
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- 8001dce: b480 push {r7}
- 8001dd0: b083 sub sp, #12
- 8001dd2: af00 add r7, sp, #0
- 8001dd4: 6078 str r0, [r7, #4]
- if(hdma->State != HAL_DMA_STATE_BUSY)
- 8001dd6: 687b ldr r3, [r7, #4]
- 8001dd8: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
- 8001ddc: b2db uxtb r3, r3
- 8001dde: 2b02 cmp r3, #2
- 8001de0: d004 beq.n 8001dec <HAL_DMA_Abort_IT+0x1e>
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 8001de2: 687b ldr r3, [r7, #4]
- 8001de4: 2280 movs r2, #128 ; 0x80
- 8001de6: 655a str r2, [r3, #84] ; 0x54
- return HAL_ERROR;
- 8001de8: 2301 movs r3, #1
- 8001dea: e00c b.n 8001e06 <HAL_DMA_Abort_IT+0x38>
- }
- else
- {
- /* Set Abort State */
- hdma->State = HAL_DMA_STATE_ABORT;
- 8001dec: 687b ldr r3, [r7, #4]
- 8001dee: 2205 movs r2, #5
- 8001df0: f883 2035 strb.w r2, [r3, #53] ; 0x35
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
- 8001df4: 687b ldr r3, [r7, #4]
- 8001df6: 681b ldr r3, [r3, #0]
- 8001df8: 681a ldr r2, [r3, #0]
- 8001dfa: 687b ldr r3, [r7, #4]
- 8001dfc: 681b ldr r3, [r3, #0]
- 8001dfe: f022 0201 bic.w r2, r2, #1
- 8001e02: 601a str r2, [r3, #0]
- }
-
- return HAL_OK;
- 8001e04: 2300 movs r3, #0
-}
- 8001e06: 4618 mov r0, r3
- 8001e08: 370c adds r7, #12
- 8001e0a: 46bd mov sp, r7
- 8001e0c: f85d 7b04 ldr.w r7, [sp], #4
- 8001e10: 4770 bx lr
- ...
-
-08001e14 <HAL_GPIO_Init>:
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8001e14: b480 push {r7}
- 8001e16: b089 sub sp, #36 ; 0x24
- 8001e18: af00 add r7, sp, #0
- 8001e1a: 6078 str r0, [r7, #4]
- 8001e1c: 6039 str r1, [r7, #0]
- uint32_t position = 0x00;
- 8001e1e: 2300 movs r3, #0
- 8001e20: 61fb str r3, [r7, #28]
- uint32_t ioposition = 0x00;
- 8001e22: 2300 movs r3, #0
- 8001e24: 617b str r3, [r7, #20]
- uint32_t iocurrent = 0x00;
- 8001e26: 2300 movs r3, #0
- 8001e28: 613b str r3, [r7, #16]
- uint32_t temp = 0x00;
- 8001e2a: 2300 movs r3, #0
- 8001e2c: 61bb str r3, [r7, #24]
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
- 8001e2e: 2300 movs r3, #0
- 8001e30: 61fb str r3, [r7, #28]
- 8001e32: e175 b.n 8002120 <HAL_GPIO_Init+0x30c>
- {
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- 8001e34: 2201 movs r2, #1
- 8001e36: 69fb ldr r3, [r7, #28]
- 8001e38: fa02 f303 lsl.w r3, r2, r3
- 8001e3c: 617b str r3, [r7, #20]
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8001e3e: 683b ldr r3, [r7, #0]
- 8001e40: 681b ldr r3, [r3, #0]
- 8001e42: 697a ldr r2, [r7, #20]
- 8001e44: 4013 ands r3, r2
- 8001e46: 613b str r3, [r7, #16]
-
- if(iocurrent == ioposition)
- 8001e48: 693a ldr r2, [r7, #16]
- 8001e4a: 697b ldr r3, [r7, #20]
- 8001e4c: 429a cmp r2, r3
- 8001e4e: f040 8164 bne.w 800211a <HAL_GPIO_Init+0x306>
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8001e52: 683b ldr r3, [r7, #0]
- 8001e54: 685b ldr r3, [r3, #4]
- 8001e56: 2b02 cmp r3, #2
- 8001e58: d003 beq.n 8001e62 <HAL_GPIO_Init+0x4e>
- 8001e5a: 683b ldr r3, [r7, #0]
- 8001e5c: 685b ldr r3, [r3, #4]
- 8001e5e: 2b12 cmp r3, #18
- 8001e60: d123 bne.n 8001eaa <HAL_GPIO_Init+0x96>
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- 8001e62: 69fb ldr r3, [r7, #28]
- 8001e64: 08da lsrs r2, r3, #3
- 8001e66: 687b ldr r3, [r7, #4]
- 8001e68: 3208 adds r2, #8
- 8001e6a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 8001e6e: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 8001e70: 69fb ldr r3, [r7, #28]
- 8001e72: f003 0307 and.w r3, r3, #7
- 8001e76: 009b lsls r3, r3, #2
- 8001e78: 220f movs r2, #15
- 8001e7a: fa02 f303 lsl.w r3, r2, r3
- 8001e7e: 43db mvns r3, r3
- 8001e80: 69ba ldr r2, [r7, #24]
- 8001e82: 4013 ands r3, r2
- 8001e84: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 8001e86: 683b ldr r3, [r7, #0]
- 8001e88: 691a ldr r2, [r3, #16]
- 8001e8a: 69fb ldr r3, [r7, #28]
- 8001e8c: f003 0307 and.w r3, r3, #7
- 8001e90: 009b lsls r3, r3, #2
- 8001e92: fa02 f303 lsl.w r3, r2, r3
- 8001e96: 69ba ldr r2, [r7, #24]
- 8001e98: 4313 orrs r3, r2
- 8001e9a: 61bb str r3, [r7, #24]
- GPIOx->AFR[position >> 3] = temp;
- 8001e9c: 69fb ldr r3, [r7, #28]
- 8001e9e: 08da lsrs r2, r3, #3
- 8001ea0: 687b ldr r3, [r7, #4]
- 8001ea2: 3208 adds r2, #8
- 8001ea4: 69b9 ldr r1, [r7, #24]
- 8001ea6: f843 1022 str.w r1, [r3, r2, lsl #2]
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- 8001eaa: 687b ldr r3, [r7, #4]
- 8001eac: 681b ldr r3, [r3, #0]
- 8001eae: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 8001eb0: 69fb ldr r3, [r7, #28]
- 8001eb2: 005b lsls r3, r3, #1
- 8001eb4: 2203 movs r2, #3
- 8001eb6: fa02 f303 lsl.w r3, r2, r3
- 8001eba: 43db mvns r3, r3
- 8001ebc: 69ba ldr r2, [r7, #24]
- 8001ebe: 4013 ands r3, r2
- 8001ec0: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 8001ec2: 683b ldr r3, [r7, #0]
- 8001ec4: 685b ldr r3, [r3, #4]
- 8001ec6: f003 0203 and.w r2, r3, #3
- 8001eca: 69fb ldr r3, [r7, #28]
- 8001ecc: 005b lsls r3, r3, #1
- 8001ece: fa02 f303 lsl.w r3, r2, r3
- 8001ed2: 69ba ldr r2, [r7, #24]
- 8001ed4: 4313 orrs r3, r2
- 8001ed6: 61bb str r3, [r7, #24]
- GPIOx->MODER = temp;
- 8001ed8: 687b ldr r3, [r7, #4]
- 8001eda: 69ba ldr r2, [r7, #24]
- 8001edc: 601a str r2, [r3, #0]
-
- /* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8001ede: 683b ldr r3, [r7, #0]
- 8001ee0: 685b ldr r3, [r3, #4]
- 8001ee2: 2b01 cmp r3, #1
- 8001ee4: d00b beq.n 8001efe <HAL_GPIO_Init+0xea>
- 8001ee6: 683b ldr r3, [r7, #0]
- 8001ee8: 685b ldr r3, [r3, #4]
- 8001eea: 2b02 cmp r3, #2
- 8001eec: d007 beq.n 8001efe <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8001eee: 683b ldr r3, [r7, #0]
- 8001ef0: 685b ldr r3, [r3, #4]
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8001ef2: 2b11 cmp r3, #17
- 8001ef4: d003 beq.n 8001efe <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8001ef6: 683b ldr r3, [r7, #0]
- 8001ef8: 685b ldr r3, [r3, #4]
- 8001efa: 2b12 cmp r3, #18
- 8001efc: d130 bne.n 8001f60 <HAL_GPIO_Init+0x14c>
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- 8001efe: 687b ldr r3, [r7, #4]
- 8001f00: 689b ldr r3, [r3, #8]
- 8001f02: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8001f04: 69fb ldr r3, [r7, #28]
- 8001f06: 005b lsls r3, r3, #1
- 8001f08: 2203 movs r2, #3
- 8001f0a: fa02 f303 lsl.w r3, r2, r3
- 8001f0e: 43db mvns r3, r3
- 8001f10: 69ba ldr r2, [r7, #24]
- 8001f12: 4013 ands r3, r2
- 8001f14: 61bb str r3, [r7, #24]
- temp |= (GPIO_Init->Speed << (position * 2));
- 8001f16: 683b ldr r3, [r7, #0]
- 8001f18: 68da ldr r2, [r3, #12]
- 8001f1a: 69fb ldr r3, [r7, #28]
- 8001f1c: 005b lsls r3, r3, #1
- 8001f1e: fa02 f303 lsl.w r3, r2, r3
- 8001f22: 69ba ldr r2, [r7, #24]
- 8001f24: 4313 orrs r3, r2
- 8001f26: 61bb str r3, [r7, #24]
- GPIOx->OSPEEDR = temp;
- 8001f28: 687b ldr r3, [r7, #4]
- 8001f2a: 69ba ldr r2, [r7, #24]
- 8001f2c: 609a str r2, [r3, #8]
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- 8001f2e: 687b ldr r3, [r7, #4]
- 8001f30: 685b ldr r3, [r3, #4]
- 8001f32: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8001f34: 2201 movs r2, #1
- 8001f36: 69fb ldr r3, [r7, #28]
- 8001f38: fa02 f303 lsl.w r3, r2, r3
- 8001f3c: 43db mvns r3, r3
- 8001f3e: 69ba ldr r2, [r7, #24]
- 8001f40: 4013 ands r3, r2
- 8001f42: 61bb str r3, [r7, #24]
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 8001f44: 683b ldr r3, [r7, #0]
- 8001f46: 685b ldr r3, [r3, #4]
- 8001f48: 091b lsrs r3, r3, #4
- 8001f4a: f003 0201 and.w r2, r3, #1
- 8001f4e: 69fb ldr r3, [r7, #28]
- 8001f50: fa02 f303 lsl.w r3, r2, r3
- 8001f54: 69ba ldr r2, [r7, #24]
- 8001f56: 4313 orrs r3, r2
- 8001f58: 61bb str r3, [r7, #24]
- GPIOx->OTYPER = temp;
- 8001f5a: 687b ldr r3, [r7, #4]
- 8001f5c: 69ba ldr r2, [r7, #24]
- 8001f5e: 605a str r2, [r3, #4]
- }
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- 8001f60: 687b ldr r3, [r7, #4]
- 8001f62: 68db ldr r3, [r3, #12]
- 8001f64: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 8001f66: 69fb ldr r3, [r7, #28]
- 8001f68: 005b lsls r3, r3, #1
- 8001f6a: 2203 movs r2, #3
- 8001f6c: fa02 f303 lsl.w r3, r2, r3
- 8001f70: 43db mvns r3, r3
- 8001f72: 69ba ldr r2, [r7, #24]
- 8001f74: 4013 ands r3, r2
- 8001f76: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Pull) << (position * 2));
- 8001f78: 683b ldr r3, [r7, #0]
- 8001f7a: 689a ldr r2, [r3, #8]
- 8001f7c: 69fb ldr r3, [r7, #28]
- 8001f7e: 005b lsls r3, r3, #1
- 8001f80: fa02 f303 lsl.w r3, r2, r3
- 8001f84: 69ba ldr r2, [r7, #24]
- 8001f86: 4313 orrs r3, r2
- 8001f88: 61bb str r3, [r7, #24]
- GPIOx->PUPDR = temp;
- 8001f8a: 687b ldr r3, [r7, #4]
- 8001f8c: 69ba ldr r2, [r7, #24]
- 8001f8e: 60da str r2, [r3, #12]
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 8001f90: 683b ldr r3, [r7, #0]
- 8001f92: 685b ldr r3, [r3, #4]
- 8001f94: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001f98: 2b00 cmp r3, #0
- 8001f9a: f000 80be beq.w 800211a <HAL_GPIO_Init+0x306>
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 8001f9e: 4b65 ldr r3, [pc, #404] ; (8002134 <HAL_GPIO_Init+0x320>)
- 8001fa0: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001fa2: 4a64 ldr r2, [pc, #400] ; (8002134 <HAL_GPIO_Init+0x320>)
- 8001fa4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8001fa8: 6453 str r3, [r2, #68] ; 0x44
- 8001faa: 4b62 ldr r3, [pc, #392] ; (8002134 <HAL_GPIO_Init+0x320>)
- 8001fac: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001fae: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8001fb2: 60fb str r3, [r7, #12]
- 8001fb4: 68fb ldr r3, [r7, #12]
-
- temp = SYSCFG->EXTICR[position >> 2];
- 8001fb6: 4a60 ldr r2, [pc, #384] ; (8002138 <HAL_GPIO_Init+0x324>)
- 8001fb8: 69fb ldr r3, [r7, #28]
- 8001fba: 089b lsrs r3, r3, #2
- 8001fbc: 3302 adds r3, #2
- 8001fbe: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 8001fc2: 61bb str r3, [r7, #24]
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 8001fc4: 69fb ldr r3, [r7, #28]
- 8001fc6: f003 0303 and.w r3, r3, #3
- 8001fca: 009b lsls r3, r3, #2
- 8001fcc: 220f movs r2, #15
- 8001fce: fa02 f303 lsl.w r3, r2, r3
- 8001fd2: 43db mvns r3, r3
- 8001fd4: 69ba ldr r2, [r7, #24]
- 8001fd6: 4013 ands r3, r2
- 8001fd8: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 8001fda: 687b ldr r3, [r7, #4]
- 8001fdc: 4a57 ldr r2, [pc, #348] ; (800213c <HAL_GPIO_Init+0x328>)
- 8001fde: 4293 cmp r3, r2
- 8001fe0: d037 beq.n 8002052 <HAL_GPIO_Init+0x23e>
- 8001fe2: 687b ldr r3, [r7, #4]
- 8001fe4: 4a56 ldr r2, [pc, #344] ; (8002140 <HAL_GPIO_Init+0x32c>)
- 8001fe6: 4293 cmp r3, r2
- 8001fe8: d031 beq.n 800204e <HAL_GPIO_Init+0x23a>
- 8001fea: 687b ldr r3, [r7, #4]
- 8001fec: 4a55 ldr r2, [pc, #340] ; (8002144 <HAL_GPIO_Init+0x330>)
- 8001fee: 4293 cmp r3, r2
- 8001ff0: d02b beq.n 800204a <HAL_GPIO_Init+0x236>
- 8001ff2: 687b ldr r3, [r7, #4]
- 8001ff4: 4a54 ldr r2, [pc, #336] ; (8002148 <HAL_GPIO_Init+0x334>)
- 8001ff6: 4293 cmp r3, r2
- 8001ff8: d025 beq.n 8002046 <HAL_GPIO_Init+0x232>
- 8001ffa: 687b ldr r3, [r7, #4]
- 8001ffc: 4a53 ldr r2, [pc, #332] ; (800214c <HAL_GPIO_Init+0x338>)
- 8001ffe: 4293 cmp r3, r2
- 8002000: d01f beq.n 8002042 <HAL_GPIO_Init+0x22e>
- 8002002: 687b ldr r3, [r7, #4]
- 8002004: 4a52 ldr r2, [pc, #328] ; (8002150 <HAL_GPIO_Init+0x33c>)
- 8002006: 4293 cmp r3, r2
- 8002008: d019 beq.n 800203e <HAL_GPIO_Init+0x22a>
- 800200a: 687b ldr r3, [r7, #4]
- 800200c: 4a51 ldr r2, [pc, #324] ; (8002154 <HAL_GPIO_Init+0x340>)
- 800200e: 4293 cmp r3, r2
- 8002010: d013 beq.n 800203a <HAL_GPIO_Init+0x226>
- 8002012: 687b ldr r3, [r7, #4]
- 8002014: 4a50 ldr r2, [pc, #320] ; (8002158 <HAL_GPIO_Init+0x344>)
- 8002016: 4293 cmp r3, r2
- 8002018: d00d beq.n 8002036 <HAL_GPIO_Init+0x222>
- 800201a: 687b ldr r3, [r7, #4]
- 800201c: 4a4f ldr r2, [pc, #316] ; (800215c <HAL_GPIO_Init+0x348>)
- 800201e: 4293 cmp r3, r2
- 8002020: d007 beq.n 8002032 <HAL_GPIO_Init+0x21e>
- 8002022: 687b ldr r3, [r7, #4]
- 8002024: 4a4e ldr r2, [pc, #312] ; (8002160 <HAL_GPIO_Init+0x34c>)
- 8002026: 4293 cmp r3, r2
- 8002028: d101 bne.n 800202e <HAL_GPIO_Init+0x21a>
- 800202a: 2309 movs r3, #9
- 800202c: e012 b.n 8002054 <HAL_GPIO_Init+0x240>
- 800202e: 230a movs r3, #10
- 8002030: e010 b.n 8002054 <HAL_GPIO_Init+0x240>
- 8002032: 2308 movs r3, #8
- 8002034: e00e b.n 8002054 <HAL_GPIO_Init+0x240>
- 8002036: 2307 movs r3, #7
- 8002038: e00c b.n 8002054 <HAL_GPIO_Init+0x240>
- 800203a: 2306 movs r3, #6
- 800203c: e00a b.n 8002054 <HAL_GPIO_Init+0x240>
- 800203e: 2305 movs r3, #5
- 8002040: e008 b.n 8002054 <HAL_GPIO_Init+0x240>
- 8002042: 2304 movs r3, #4
- 8002044: e006 b.n 8002054 <HAL_GPIO_Init+0x240>
- 8002046: 2303 movs r3, #3
- 8002048: e004 b.n 8002054 <HAL_GPIO_Init+0x240>
- 800204a: 2302 movs r3, #2
- 800204c: e002 b.n 8002054 <HAL_GPIO_Init+0x240>
- 800204e: 2301 movs r3, #1
- 8002050: e000 b.n 8002054 <HAL_GPIO_Init+0x240>
- 8002052: 2300 movs r3, #0
- 8002054: 69fa ldr r2, [r7, #28]
- 8002056: f002 0203 and.w r2, r2, #3
- 800205a: 0092 lsls r2, r2, #2
- 800205c: 4093 lsls r3, r2
- 800205e: 69ba ldr r2, [r7, #24]
- 8002060: 4313 orrs r3, r2
- 8002062: 61bb str r3, [r7, #24]
- SYSCFG->EXTICR[position >> 2] = temp;
- 8002064: 4934 ldr r1, [pc, #208] ; (8002138 <HAL_GPIO_Init+0x324>)
- 8002066: 69fb ldr r3, [r7, #28]
- 8002068: 089b lsrs r3, r3, #2
- 800206a: 3302 adds r3, #2
- 800206c: 69ba ldr r2, [r7, #24]
- 800206e: f841 2023 str.w r2, [r1, r3, lsl #2]
-
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- 8002072: 4b3c ldr r3, [pc, #240] ; (8002164 <HAL_GPIO_Init+0x350>)
- 8002074: 681b ldr r3, [r3, #0]
- 8002076: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8002078: 693b ldr r3, [r7, #16]
- 800207a: 43db mvns r3, r3
- 800207c: 69ba ldr r2, [r7, #24]
- 800207e: 4013 ands r3, r2
- 8002080: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 8002082: 683b ldr r3, [r7, #0]
- 8002084: 685b ldr r3, [r3, #4]
- 8002086: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 800208a: 2b00 cmp r3, #0
- 800208c: d003 beq.n 8002096 <HAL_GPIO_Init+0x282>
- {
- temp |= iocurrent;
- 800208e: 69ba ldr r2, [r7, #24]
- 8002090: 693b ldr r3, [r7, #16]
- 8002092: 4313 orrs r3, r2
- 8002094: 61bb str r3, [r7, #24]
- }
- EXTI->IMR = temp;
- 8002096: 4a33 ldr r2, [pc, #204] ; (8002164 <HAL_GPIO_Init+0x350>)
- 8002098: 69bb ldr r3, [r7, #24]
- 800209a: 6013 str r3, [r2, #0]
-
- temp = EXTI->EMR;
- 800209c: 4b31 ldr r3, [pc, #196] ; (8002164 <HAL_GPIO_Init+0x350>)
- 800209e: 685b ldr r3, [r3, #4]
- 80020a0: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80020a2: 693b ldr r3, [r7, #16]
- 80020a4: 43db mvns r3, r3
- 80020a6: 69ba ldr r2, [r7, #24]
- 80020a8: 4013 ands r3, r2
- 80020aa: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 80020ac: 683b ldr r3, [r7, #0]
- 80020ae: 685b ldr r3, [r3, #4]
- 80020b0: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80020b4: 2b00 cmp r3, #0
- 80020b6: d003 beq.n 80020c0 <HAL_GPIO_Init+0x2ac>
- {
- temp |= iocurrent;
- 80020b8: 69ba ldr r2, [r7, #24]
- 80020ba: 693b ldr r3, [r7, #16]
- 80020bc: 4313 orrs r3, r2
- 80020be: 61bb str r3, [r7, #24]
- }
- EXTI->EMR = temp;
- 80020c0: 4a28 ldr r2, [pc, #160] ; (8002164 <HAL_GPIO_Init+0x350>)
- 80020c2: 69bb ldr r3, [r7, #24]
- 80020c4: 6053 str r3, [r2, #4]
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR;
- 80020c6: 4b27 ldr r3, [pc, #156] ; (8002164 <HAL_GPIO_Init+0x350>)
- 80020c8: 689b ldr r3, [r3, #8]
- 80020ca: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80020cc: 693b ldr r3, [r7, #16]
- 80020ce: 43db mvns r3, r3
- 80020d0: 69ba ldr r2, [r7, #24]
- 80020d2: 4013 ands r3, r2
- 80020d4: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 80020d6: 683b ldr r3, [r7, #0]
- 80020d8: 685b ldr r3, [r3, #4]
- 80020da: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 80020de: 2b00 cmp r3, #0
- 80020e0: d003 beq.n 80020ea <HAL_GPIO_Init+0x2d6>
- {
- temp |= iocurrent;
- 80020e2: 69ba ldr r2, [r7, #24]
- 80020e4: 693b ldr r3, [r7, #16]
- 80020e6: 4313 orrs r3, r2
- 80020e8: 61bb str r3, [r7, #24]
- }
- EXTI->RTSR = temp;
- 80020ea: 4a1e ldr r2, [pc, #120] ; (8002164 <HAL_GPIO_Init+0x350>)
- 80020ec: 69bb ldr r3, [r7, #24]
- 80020ee: 6093 str r3, [r2, #8]
-
- temp = EXTI->FTSR;
- 80020f0: 4b1c ldr r3, [pc, #112] ; (8002164 <HAL_GPIO_Init+0x350>)
- 80020f2: 68db ldr r3, [r3, #12]
- 80020f4: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80020f6: 693b ldr r3, [r7, #16]
- 80020f8: 43db mvns r3, r3
- 80020fa: 69ba ldr r2, [r7, #24]
- 80020fc: 4013 ands r3, r2
- 80020fe: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 8002100: 683b ldr r3, [r7, #0]
- 8002102: 685b ldr r3, [r3, #4]
- 8002104: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8002108: 2b00 cmp r3, #0
- 800210a: d003 beq.n 8002114 <HAL_GPIO_Init+0x300>
- {
- temp |= iocurrent;
- 800210c: 69ba ldr r2, [r7, #24]
- 800210e: 693b ldr r3, [r7, #16]
- 8002110: 4313 orrs r3, r2
- 8002112: 61bb str r3, [r7, #24]
- }
- EXTI->FTSR = temp;
- 8002114: 4a13 ldr r2, [pc, #76] ; (8002164 <HAL_GPIO_Init+0x350>)
- 8002116: 69bb ldr r3, [r7, #24]
- 8002118: 60d3 str r3, [r2, #12]
- for(position = 0; position < GPIO_NUMBER; position++)
- 800211a: 69fb ldr r3, [r7, #28]
- 800211c: 3301 adds r3, #1
- 800211e: 61fb str r3, [r7, #28]
- 8002120: 69fb ldr r3, [r7, #28]
- 8002122: 2b0f cmp r3, #15
- 8002124: f67f ae86 bls.w 8001e34 <HAL_GPIO_Init+0x20>
- }
- }
- }
-}
- 8002128: bf00 nop
- 800212a: 3724 adds r7, #36 ; 0x24
- 800212c: 46bd mov sp, r7
- 800212e: f85d 7b04 ldr.w r7, [sp], #4
- 8002132: 4770 bx lr
- 8002134: 40023800 .word 0x40023800
- 8002138: 40013800 .word 0x40013800
- 800213c: 40020000 .word 0x40020000
- 8002140: 40020400 .word 0x40020400
- 8002144: 40020800 .word 0x40020800
- 8002148: 40020c00 .word 0x40020c00
- 800214c: 40021000 .word 0x40021000
- 8002150: 40021400 .word 0x40021400
- 8002154: 40021800 .word 0x40021800
- 8002158: 40021c00 .word 0x40021c00
- 800215c: 40022000 .word 0x40022000
- 8002160: 40022400 .word 0x40022400
- 8002164: 40013c00 .word 0x40013c00
-
-08002168 <HAL_GPIO_WritePin>:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- 8002168: b480 push {r7}
- 800216a: b083 sub sp, #12
- 800216c: af00 add r7, sp, #0
- 800216e: 6078 str r0, [r7, #4]
- 8002170: 460b mov r3, r1
- 8002172: 807b strh r3, [r7, #2]
- 8002174: 4613 mov r3, r2
- 8002176: 707b strb r3, [r7, #1]
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- 8002178: 787b ldrb r3, [r7, #1]
- 800217a: 2b00 cmp r3, #0
- 800217c: d003 beq.n 8002186 <HAL_GPIO_WritePin+0x1e>
- {
- GPIOx->BSRR = GPIO_Pin;
- 800217e: 887a ldrh r2, [r7, #2]
- 8002180: 687b ldr r3, [r7, #4]
- 8002182: 619a str r2, [r3, #24]
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- }
-}
- 8002184: e003 b.n 800218e <HAL_GPIO_WritePin+0x26>
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- 8002186: 887b ldrh r3, [r7, #2]
- 8002188: 041a lsls r2, r3, #16
- 800218a: 687b ldr r3, [r7, #4]
- 800218c: 619a str r2, [r3, #24]
-}
- 800218e: bf00 nop
- 8002190: 370c adds r7, #12
- 8002192: 46bd mov sp, r7
- 8002194: f85d 7b04 ldr.w r7, [sp], #4
- 8002198: 4770 bx lr
- ...
-
-0800219c <HAL_GPIO_EXTI_IRQHandler>:
- * @brief This function handles EXTI interrupt request.
- * @param GPIO_Pin Specifies the pins connected EXTI line
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- 800219c: b580 push {r7, lr}
- 800219e: b082 sub sp, #8
- 80021a0: af00 add r7, sp, #0
- 80021a2: 4603 mov r3, r0
- 80021a4: 80fb strh r3, [r7, #6]
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- 80021a6: 4b08 ldr r3, [pc, #32] ; (80021c8 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80021a8: 695a ldr r2, [r3, #20]
- 80021aa: 88fb ldrh r3, [r7, #6]
- 80021ac: 4013 ands r3, r2
- 80021ae: 2b00 cmp r3, #0
- 80021b0: d006 beq.n 80021c0 <HAL_GPIO_EXTI_IRQHandler+0x24>
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- 80021b2: 4a05 ldr r2, [pc, #20] ; (80021c8 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80021b4: 88fb ldrh r3, [r7, #6]
- 80021b6: 6153 str r3, [r2, #20]
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- 80021b8: 88fb ldrh r3, [r7, #6]
- 80021ba: 4618 mov r0, r3
- 80021bc: f7ff f9c4 bl 8001548 <HAL_GPIO_EXTI_Callback>
- }
-}
- 80021c0: bf00 nop
- 80021c2: 3708 adds r7, #8
- 80021c4: 46bd mov sp, r7
- 80021c6: bd80 pop {r7, pc}
- 80021c8: 40013c00 .word 0x40013c00
-
-080021cc <HAL_RCC_OscConfig>:
- * supported by this function. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- 80021cc: b580 push {r7, lr}
- 80021ce: b086 sub sp, #24
- 80021d0: af00 add r7, sp, #0
- 80021d2: 6078 str r0, [r7, #4]
- uint32_t tickstart;
- FlagStatus pwrclkchanged = RESET;
- 80021d4: 2300 movs r3, #0
- 80021d6: 75fb strb r3, [r7, #23]
-
- /* Check Null pointer */
- if(RCC_OscInitStruct == NULL)
- 80021d8: 687b ldr r3, [r7, #4]
- 80021da: 2b00 cmp r3, #0
- 80021dc: d101 bne.n 80021e2 <HAL_RCC_OscConfig+0x16>
- {
- return HAL_ERROR;
- 80021de: 2301 movs r3, #1
- 80021e0: e25e b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 80021e2: 687b ldr r3, [r7, #4]
- 80021e4: 681b ldr r3, [r3, #0]
- 80021e6: f003 0301 and.w r3, r3, #1
- 80021ea: 2b00 cmp r3, #0
- 80021ec: f000 8087 beq.w 80022fe <HAL_RCC_OscConfig+0x132>
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 80021f0: 4b96 ldr r3, [pc, #600] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80021f2: 689b ldr r3, [r3, #8]
- 80021f4: f003 030c and.w r3, r3, #12
- 80021f8: 2b04 cmp r3, #4
- 80021fa: d00c beq.n 8002216 <HAL_RCC_OscConfig+0x4a>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 80021fc: 4b93 ldr r3, [pc, #588] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80021fe: 689b ldr r3, [r3, #8]
- 8002200: f003 030c and.w r3, r3, #12
- 8002204: 2b08 cmp r3, #8
- 8002206: d112 bne.n 800222e <HAL_RCC_OscConfig+0x62>
- 8002208: 4b90 ldr r3, [pc, #576] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800220a: 685b ldr r3, [r3, #4]
- 800220c: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002210: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002214: d10b bne.n 800222e <HAL_RCC_OscConfig+0x62>
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8002216: 4b8d ldr r3, [pc, #564] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002218: 681b ldr r3, [r3, #0]
- 800221a: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800221e: 2b00 cmp r3, #0
- 8002220: d06c beq.n 80022fc <HAL_RCC_OscConfig+0x130>
- 8002222: 687b ldr r3, [r7, #4]
- 8002224: 685b ldr r3, [r3, #4]
- 8002226: 2b00 cmp r3, #0
- 8002228: d168 bne.n 80022fc <HAL_RCC_OscConfig+0x130>
- {
- return HAL_ERROR;
- 800222a: 2301 movs r3, #1
- 800222c: e238 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 800222e: 687b ldr r3, [r7, #4]
- 8002230: 685b ldr r3, [r3, #4]
- 8002232: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8002236: d106 bne.n 8002246 <HAL_RCC_OscConfig+0x7a>
- 8002238: 4b84 ldr r3, [pc, #528] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800223a: 681b ldr r3, [r3, #0]
- 800223c: 4a83 ldr r2, [pc, #524] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800223e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002242: 6013 str r3, [r2, #0]
- 8002244: e02e b.n 80022a4 <HAL_RCC_OscConfig+0xd8>
- 8002246: 687b ldr r3, [r7, #4]
- 8002248: 685b ldr r3, [r3, #4]
- 800224a: 2b00 cmp r3, #0
- 800224c: d10c bne.n 8002268 <HAL_RCC_OscConfig+0x9c>
- 800224e: 4b7f ldr r3, [pc, #508] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002250: 681b ldr r3, [r3, #0]
- 8002252: 4a7e ldr r2, [pc, #504] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002254: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002258: 6013 str r3, [r2, #0]
- 800225a: 4b7c ldr r3, [pc, #496] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800225c: 681b ldr r3, [r3, #0]
- 800225e: 4a7b ldr r2, [pc, #492] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002260: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8002264: 6013 str r3, [r2, #0]
- 8002266: e01d b.n 80022a4 <HAL_RCC_OscConfig+0xd8>
- 8002268: 687b ldr r3, [r7, #4]
- 800226a: 685b ldr r3, [r3, #4]
- 800226c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 8002270: d10c bne.n 800228c <HAL_RCC_OscConfig+0xc0>
- 8002272: 4b76 ldr r3, [pc, #472] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002274: 681b ldr r3, [r3, #0]
- 8002276: 4a75 ldr r2, [pc, #468] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002278: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 800227c: 6013 str r3, [r2, #0]
- 800227e: 4b73 ldr r3, [pc, #460] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002280: 681b ldr r3, [r3, #0]
- 8002282: 4a72 ldr r2, [pc, #456] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002284: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002288: 6013 str r3, [r2, #0]
- 800228a: e00b b.n 80022a4 <HAL_RCC_OscConfig+0xd8>
- 800228c: 4b6f ldr r3, [pc, #444] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800228e: 681b ldr r3, [r3, #0]
- 8002290: 4a6e ldr r2, [pc, #440] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002292: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002296: 6013 str r3, [r2, #0]
- 8002298: 4b6c ldr r3, [pc, #432] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800229a: 681b ldr r3, [r3, #0]
- 800229c: 4a6b ldr r2, [pc, #428] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800229e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80022a2: 6013 str r3, [r2, #0]
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 80022a4: 687b ldr r3, [r7, #4]
- 80022a6: 685b ldr r3, [r3, #4]
- 80022a8: 2b00 cmp r3, #0
- 80022aa: d013 beq.n 80022d4 <HAL_RCC_OscConfig+0x108>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80022ac: f7ff fc72 bl 8001b94 <HAL_GetTick>
- 80022b0: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80022b2: e008 b.n 80022c6 <HAL_RCC_OscConfig+0xfa>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 80022b4: f7ff fc6e bl 8001b94 <HAL_GetTick>
- 80022b8: 4602 mov r2, r0
- 80022ba: 693b ldr r3, [r7, #16]
- 80022bc: 1ad3 subs r3, r2, r3
- 80022be: 2b64 cmp r3, #100 ; 0x64
- 80022c0: d901 bls.n 80022c6 <HAL_RCC_OscConfig+0xfa>
- {
- return HAL_TIMEOUT;
- 80022c2: 2303 movs r3, #3
- 80022c4: e1ec b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80022c6: 4b61 ldr r3, [pc, #388] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80022c8: 681b ldr r3, [r3, #0]
- 80022ca: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80022ce: 2b00 cmp r3, #0
- 80022d0: d0f0 beq.n 80022b4 <HAL_RCC_OscConfig+0xe8>
- 80022d2: e014 b.n 80022fe <HAL_RCC_OscConfig+0x132>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80022d4: f7ff fc5e bl 8001b94 <HAL_GetTick>
- 80022d8: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 80022da: e008 b.n 80022ee <HAL_RCC_OscConfig+0x122>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 80022dc: f7ff fc5a bl 8001b94 <HAL_GetTick>
- 80022e0: 4602 mov r2, r0
- 80022e2: 693b ldr r3, [r7, #16]
- 80022e4: 1ad3 subs r3, r2, r3
- 80022e6: 2b64 cmp r3, #100 ; 0x64
- 80022e8: d901 bls.n 80022ee <HAL_RCC_OscConfig+0x122>
- {
- return HAL_TIMEOUT;
- 80022ea: 2303 movs r3, #3
- 80022ec: e1d8 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 80022ee: 4b57 ldr r3, [pc, #348] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80022f0: 681b ldr r3, [r3, #0]
- 80022f2: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80022f6: 2b00 cmp r3, #0
- 80022f8: d1f0 bne.n 80022dc <HAL_RCC_OscConfig+0x110>
- 80022fa: e000 b.n 80022fe <HAL_RCC_OscConfig+0x132>
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 80022fc: bf00 nop
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 80022fe: 687b ldr r3, [r7, #4]
- 8002300: 681b ldr r3, [r3, #0]
- 8002302: f003 0302 and.w r3, r3, #2
- 8002306: 2b00 cmp r3, #0
- 8002308: d069 beq.n 80023de <HAL_RCC_OscConfig+0x212>
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 800230a: 4b50 ldr r3, [pc, #320] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800230c: 689b ldr r3, [r3, #8]
- 800230e: f003 030c and.w r3, r3, #12
- 8002312: 2b00 cmp r3, #0
- 8002314: d00b beq.n 800232e <HAL_RCC_OscConfig+0x162>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 8002316: 4b4d ldr r3, [pc, #308] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002318: 689b ldr r3, [r3, #8]
- 800231a: f003 030c and.w r3, r3, #12
- 800231e: 2b08 cmp r3, #8
- 8002320: d11c bne.n 800235c <HAL_RCC_OscConfig+0x190>
- 8002322: 4b4a ldr r3, [pc, #296] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002324: 685b ldr r3, [r3, #4]
- 8002326: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800232a: 2b00 cmp r3, #0
- 800232c: d116 bne.n 800235c <HAL_RCC_OscConfig+0x190>
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 800232e: 4b47 ldr r3, [pc, #284] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002330: 681b ldr r3, [r3, #0]
- 8002332: f003 0302 and.w r3, r3, #2
- 8002336: 2b00 cmp r3, #0
- 8002338: d005 beq.n 8002346 <HAL_RCC_OscConfig+0x17a>
- 800233a: 687b ldr r3, [r7, #4]
- 800233c: 68db ldr r3, [r3, #12]
- 800233e: 2b01 cmp r3, #1
- 8002340: d001 beq.n 8002346 <HAL_RCC_OscConfig+0x17a>
- {
- return HAL_ERROR;
- 8002342: 2301 movs r3, #1
- 8002344: e1ac b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8002346: 4b41 ldr r3, [pc, #260] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002348: 681b ldr r3, [r3, #0]
- 800234a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 800234e: 687b ldr r3, [r7, #4]
- 8002350: 691b ldr r3, [r3, #16]
- 8002352: 00db lsls r3, r3, #3
- 8002354: 493d ldr r1, [pc, #244] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002356: 4313 orrs r3, r2
- 8002358: 600b str r3, [r1, #0]
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 800235a: e040 b.n 80023de <HAL_RCC_OscConfig+0x212>
- }
- }
- else
- {
- /* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 800235c: 687b ldr r3, [r7, #4]
- 800235e: 68db ldr r3, [r3, #12]
- 8002360: 2b00 cmp r3, #0
- 8002362: d023 beq.n 80023ac <HAL_RCC_OscConfig+0x1e0>
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
- 8002364: 4b39 ldr r3, [pc, #228] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002366: 681b ldr r3, [r3, #0]
- 8002368: 4a38 ldr r2, [pc, #224] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800236a: f043 0301 orr.w r3, r3, #1
- 800236e: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002370: f7ff fc10 bl 8001b94 <HAL_GetTick>
- 8002374: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8002376: e008 b.n 800238a <HAL_RCC_OscConfig+0x1be>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8002378: f7ff fc0c bl 8001b94 <HAL_GetTick>
- 800237c: 4602 mov r2, r0
- 800237e: 693b ldr r3, [r7, #16]
- 8002380: 1ad3 subs r3, r2, r3
- 8002382: 2b02 cmp r3, #2
- 8002384: d901 bls.n 800238a <HAL_RCC_OscConfig+0x1be>
- {
- return HAL_TIMEOUT;
- 8002386: 2303 movs r3, #3
- 8002388: e18a b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 800238a: 4b30 ldr r3, [pc, #192] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800238c: 681b ldr r3, [r3, #0]
- 800238e: f003 0302 and.w r3, r3, #2
- 8002392: 2b00 cmp r3, #0
- 8002394: d0f0 beq.n 8002378 <HAL_RCC_OscConfig+0x1ac>
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8002396: 4b2d ldr r3, [pc, #180] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002398: 681b ldr r3, [r3, #0]
- 800239a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 800239e: 687b ldr r3, [r7, #4]
- 80023a0: 691b ldr r3, [r3, #16]
- 80023a2: 00db lsls r3, r3, #3
- 80023a4: 4929 ldr r1, [pc, #164] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80023a6: 4313 orrs r3, r2
- 80023a8: 600b str r3, [r1, #0]
- 80023aa: e018 b.n 80023de <HAL_RCC_OscConfig+0x212>
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
- 80023ac: 4b27 ldr r3, [pc, #156] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80023ae: 681b ldr r3, [r3, #0]
- 80023b0: 4a26 ldr r2, [pc, #152] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80023b2: f023 0301 bic.w r3, r3, #1
- 80023b6: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80023b8: f7ff fbec bl 8001b94 <HAL_GetTick>
- 80023bc: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 80023be: e008 b.n 80023d2 <HAL_RCC_OscConfig+0x206>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80023c0: f7ff fbe8 bl 8001b94 <HAL_GetTick>
- 80023c4: 4602 mov r2, r0
- 80023c6: 693b ldr r3, [r7, #16]
- 80023c8: 1ad3 subs r3, r2, r3
- 80023ca: 2b02 cmp r3, #2
- 80023cc: d901 bls.n 80023d2 <HAL_RCC_OscConfig+0x206>
- {
- return HAL_TIMEOUT;
- 80023ce: 2303 movs r3, #3
- 80023d0: e166 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 80023d2: 4b1e ldr r3, [pc, #120] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80023d4: 681b ldr r3, [r3, #0]
- 80023d6: f003 0302 and.w r3, r3, #2
- 80023da: 2b00 cmp r3, #0
- 80023dc: d1f0 bne.n 80023c0 <HAL_RCC_OscConfig+0x1f4>
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 80023de: 687b ldr r3, [r7, #4]
- 80023e0: 681b ldr r3, [r3, #0]
- 80023e2: f003 0308 and.w r3, r3, #8
- 80023e6: 2b00 cmp r3, #0
- 80023e8: d038 beq.n 800245c <HAL_RCC_OscConfig+0x290>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 80023ea: 687b ldr r3, [r7, #4]
- 80023ec: 695b ldr r3, [r3, #20]
- 80023ee: 2b00 cmp r3, #0
- 80023f0: d019 beq.n 8002426 <HAL_RCC_OscConfig+0x25a>
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
- 80023f2: 4b16 ldr r3, [pc, #88] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80023f4: 6f5b ldr r3, [r3, #116] ; 0x74
- 80023f6: 4a15 ldr r2, [pc, #84] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 80023f8: f043 0301 orr.w r3, r3, #1
- 80023fc: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80023fe: f7ff fbc9 bl 8001b94 <HAL_GetTick>
- 8002402: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8002404: e008 b.n 8002418 <HAL_RCC_OscConfig+0x24c>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8002406: f7ff fbc5 bl 8001b94 <HAL_GetTick>
- 800240a: 4602 mov r2, r0
- 800240c: 693b ldr r3, [r7, #16]
- 800240e: 1ad3 subs r3, r2, r3
- 8002410: 2b02 cmp r3, #2
- 8002412: d901 bls.n 8002418 <HAL_RCC_OscConfig+0x24c>
- {
- return HAL_TIMEOUT;
- 8002414: 2303 movs r3, #3
- 8002416: e143 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8002418: 4b0c ldr r3, [pc, #48] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800241a: 6f5b ldr r3, [r3, #116] ; 0x74
- 800241c: f003 0302 and.w r3, r3, #2
- 8002420: 2b00 cmp r3, #0
- 8002422: d0f0 beq.n 8002406 <HAL_RCC_OscConfig+0x23a>
- 8002424: e01a b.n 800245c <HAL_RCC_OscConfig+0x290>
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
- 8002426: 4b09 ldr r3, [pc, #36] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 8002428: 6f5b ldr r3, [r3, #116] ; 0x74
- 800242a: 4a08 ldr r2, [pc, #32] ; (800244c <HAL_RCC_OscConfig+0x280>)
- 800242c: f023 0301 bic.w r3, r3, #1
- 8002430: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002432: f7ff fbaf bl 8001b94 <HAL_GetTick>
- 8002436: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8002438: e00a b.n 8002450 <HAL_RCC_OscConfig+0x284>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800243a: f7ff fbab bl 8001b94 <HAL_GetTick>
- 800243e: 4602 mov r2, r0
- 8002440: 693b ldr r3, [r7, #16]
- 8002442: 1ad3 subs r3, r2, r3
- 8002444: 2b02 cmp r3, #2
- 8002446: d903 bls.n 8002450 <HAL_RCC_OscConfig+0x284>
- {
- return HAL_TIMEOUT;
- 8002448: 2303 movs r3, #3
- 800244a: e129 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- 800244c: 40023800 .word 0x40023800
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8002450: 4b95 ldr r3, [pc, #596] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002452: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002454: f003 0302 and.w r3, r3, #2
- 8002458: 2b00 cmp r3, #0
- 800245a: d1ee bne.n 800243a <HAL_RCC_OscConfig+0x26e>
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 800245c: 687b ldr r3, [r7, #4]
- 800245e: 681b ldr r3, [r3, #0]
- 8002460: f003 0304 and.w r3, r3, #4
- 8002464: 2b00 cmp r3, #0
- 8002466: f000 80a4 beq.w 80025b2 <HAL_RCC_OscConfig+0x3e6>
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 800246a: 4b8f ldr r3, [pc, #572] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800246c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800246e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002472: 2b00 cmp r3, #0
- 8002474: d10d bne.n 8002492 <HAL_RCC_OscConfig+0x2c6>
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 8002476: 4b8c ldr r3, [pc, #560] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002478: 6c1b ldr r3, [r3, #64] ; 0x40
- 800247a: 4a8b ldr r2, [pc, #556] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800247c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8002480: 6413 str r3, [r2, #64] ; 0x40
- 8002482: 4b89 ldr r3, [pc, #548] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002484: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002486: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 800248a: 60fb str r3, [r7, #12]
- 800248c: 68fb ldr r3, [r7, #12]
- pwrclkchanged = SET;
- 800248e: 2301 movs r3, #1
- 8002490: 75fb strb r3, [r7, #23]
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8002492: 4b86 ldr r3, [pc, #536] ; (80026ac <HAL_RCC_OscConfig+0x4e0>)
- 8002494: 681b ldr r3, [r3, #0]
- 8002496: f403 7380 and.w r3, r3, #256 ; 0x100
- 800249a: 2b00 cmp r3, #0
- 800249c: d118 bne.n 80024d0 <HAL_RCC_OscConfig+0x304>
- {
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 800249e: 4b83 ldr r3, [pc, #524] ; (80026ac <HAL_RCC_OscConfig+0x4e0>)
- 80024a0: 681b ldr r3, [r3, #0]
- 80024a2: 4a82 ldr r2, [pc, #520] ; (80026ac <HAL_RCC_OscConfig+0x4e0>)
- 80024a4: f443 7380 orr.w r3, r3, #256 ; 0x100
- 80024a8: 6013 str r3, [r2, #0]
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
- 80024aa: f7ff fb73 bl 8001b94 <HAL_GetTick>
- 80024ae: 6138 str r0, [r7, #16]
-
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80024b0: e008 b.n 80024c4 <HAL_RCC_OscConfig+0x2f8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 80024b2: f7ff fb6f bl 8001b94 <HAL_GetTick>
- 80024b6: 4602 mov r2, r0
- 80024b8: 693b ldr r3, [r7, #16]
- 80024ba: 1ad3 subs r3, r2, r3
- 80024bc: 2b64 cmp r3, #100 ; 0x64
- 80024be: d901 bls.n 80024c4 <HAL_RCC_OscConfig+0x2f8>
- {
- return HAL_TIMEOUT;
- 80024c0: 2303 movs r3, #3
- 80024c2: e0ed b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80024c4: 4b79 ldr r3, [pc, #484] ; (80026ac <HAL_RCC_OscConfig+0x4e0>)
- 80024c6: 681b ldr r3, [r3, #0]
- 80024c8: f403 7380 and.w r3, r3, #256 ; 0x100
- 80024cc: 2b00 cmp r3, #0
- 80024ce: d0f0 beq.n 80024b2 <HAL_RCC_OscConfig+0x2e6>
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 80024d0: 687b ldr r3, [r7, #4]
- 80024d2: 689b ldr r3, [r3, #8]
- 80024d4: 2b01 cmp r3, #1
- 80024d6: d106 bne.n 80024e6 <HAL_RCC_OscConfig+0x31a>
- 80024d8: 4b73 ldr r3, [pc, #460] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80024da: 6f1b ldr r3, [r3, #112] ; 0x70
- 80024dc: 4a72 ldr r2, [pc, #456] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80024de: f043 0301 orr.w r3, r3, #1
- 80024e2: 6713 str r3, [r2, #112] ; 0x70
- 80024e4: e02d b.n 8002542 <HAL_RCC_OscConfig+0x376>
- 80024e6: 687b ldr r3, [r7, #4]
- 80024e8: 689b ldr r3, [r3, #8]
- 80024ea: 2b00 cmp r3, #0
- 80024ec: d10c bne.n 8002508 <HAL_RCC_OscConfig+0x33c>
- 80024ee: 4b6e ldr r3, [pc, #440] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80024f0: 6f1b ldr r3, [r3, #112] ; 0x70
- 80024f2: 4a6d ldr r2, [pc, #436] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80024f4: f023 0301 bic.w r3, r3, #1
- 80024f8: 6713 str r3, [r2, #112] ; 0x70
- 80024fa: 4b6b ldr r3, [pc, #428] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80024fc: 6f1b ldr r3, [r3, #112] ; 0x70
- 80024fe: 4a6a ldr r2, [pc, #424] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002500: f023 0304 bic.w r3, r3, #4
- 8002504: 6713 str r3, [r2, #112] ; 0x70
- 8002506: e01c b.n 8002542 <HAL_RCC_OscConfig+0x376>
- 8002508: 687b ldr r3, [r7, #4]
- 800250a: 689b ldr r3, [r3, #8]
- 800250c: 2b05 cmp r3, #5
- 800250e: d10c bne.n 800252a <HAL_RCC_OscConfig+0x35e>
- 8002510: 4b65 ldr r3, [pc, #404] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002512: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002514: 4a64 ldr r2, [pc, #400] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002516: f043 0304 orr.w r3, r3, #4
- 800251a: 6713 str r3, [r2, #112] ; 0x70
- 800251c: 4b62 ldr r3, [pc, #392] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800251e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002520: 4a61 ldr r2, [pc, #388] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002522: f043 0301 orr.w r3, r3, #1
- 8002526: 6713 str r3, [r2, #112] ; 0x70
- 8002528: e00b b.n 8002542 <HAL_RCC_OscConfig+0x376>
- 800252a: 4b5f ldr r3, [pc, #380] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800252c: 6f1b ldr r3, [r3, #112] ; 0x70
- 800252e: 4a5e ldr r2, [pc, #376] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002530: f023 0301 bic.w r3, r3, #1
- 8002534: 6713 str r3, [r2, #112] ; 0x70
- 8002536: 4b5c ldr r3, [pc, #368] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002538: 6f1b ldr r3, [r3, #112] ; 0x70
- 800253a: 4a5b ldr r2, [pc, #364] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800253c: f023 0304 bic.w r3, r3, #4
- 8002540: 6713 str r3, [r2, #112] ; 0x70
- /* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 8002542: 687b ldr r3, [r7, #4]
- 8002544: 689b ldr r3, [r3, #8]
- 8002546: 2b00 cmp r3, #0
- 8002548: d015 beq.n 8002576 <HAL_RCC_OscConfig+0x3aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800254a: f7ff fb23 bl 8001b94 <HAL_GetTick>
- 800254e: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002550: e00a b.n 8002568 <HAL_RCC_OscConfig+0x39c>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002552: f7ff fb1f bl 8001b94 <HAL_GetTick>
- 8002556: 4602 mov r2, r0
- 8002558: 693b ldr r3, [r7, #16]
- 800255a: 1ad3 subs r3, r2, r3
- 800255c: f241 3288 movw r2, #5000 ; 0x1388
- 8002560: 4293 cmp r3, r2
- 8002562: d901 bls.n 8002568 <HAL_RCC_OscConfig+0x39c>
- {
- return HAL_TIMEOUT;
- 8002564: 2303 movs r3, #3
- 8002566: e09b b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002568: 4b4f ldr r3, [pc, #316] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800256a: 6f1b ldr r3, [r3, #112] ; 0x70
- 800256c: f003 0302 and.w r3, r3, #2
- 8002570: 2b00 cmp r3, #0
- 8002572: d0ee beq.n 8002552 <HAL_RCC_OscConfig+0x386>
- 8002574: e014 b.n 80025a0 <HAL_RCC_OscConfig+0x3d4>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002576: f7ff fb0d bl 8001b94 <HAL_GetTick>
- 800257a: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 800257c: e00a b.n 8002594 <HAL_RCC_OscConfig+0x3c8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 800257e: f7ff fb09 bl 8001b94 <HAL_GetTick>
- 8002582: 4602 mov r2, r0
- 8002584: 693b ldr r3, [r7, #16]
- 8002586: 1ad3 subs r3, r2, r3
- 8002588: f241 3288 movw r2, #5000 ; 0x1388
- 800258c: 4293 cmp r3, r2
- 800258e: d901 bls.n 8002594 <HAL_RCC_OscConfig+0x3c8>
- {
- return HAL_TIMEOUT;
- 8002590: 2303 movs r3, #3
- 8002592: e085 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8002594: 4b44 ldr r3, [pc, #272] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002596: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002598: f003 0302 and.w r3, r3, #2
- 800259c: 2b00 cmp r3, #0
- 800259e: d1ee bne.n 800257e <HAL_RCC_OscConfig+0x3b2>
- }
- }
- }
-
- /* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
- 80025a0: 7dfb ldrb r3, [r7, #23]
- 80025a2: 2b01 cmp r3, #1
- 80025a4: d105 bne.n 80025b2 <HAL_RCC_OscConfig+0x3e6>
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- 80025a6: 4b40 ldr r3, [pc, #256] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80025a8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80025aa: 4a3f ldr r2, [pc, #252] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80025ac: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 80025b0: 6413 str r3, [r2, #64] ; 0x40
- }
- }
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 80025b2: 687b ldr r3, [r7, #4]
- 80025b4: 699b ldr r3, [r3, #24]
- 80025b6: 2b00 cmp r3, #0
- 80025b8: d071 beq.n 800269e <HAL_RCC_OscConfig+0x4d2>
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 80025ba: 4b3b ldr r3, [pc, #236] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80025bc: 689b ldr r3, [r3, #8]
- 80025be: f003 030c and.w r3, r3, #12
- 80025c2: 2b08 cmp r3, #8
- 80025c4: d069 beq.n 800269a <HAL_RCC_OscConfig+0x4ce>
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 80025c6: 687b ldr r3, [r7, #4]
- 80025c8: 699b ldr r3, [r3, #24]
- 80025ca: 2b02 cmp r3, #2
- 80025cc: d14b bne.n 8002666 <HAL_RCC_OscConfig+0x49a>
-#if defined (RCC_PLLCFGR_PLLR)
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-#endif
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 80025ce: 4b36 ldr r3, [pc, #216] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80025d0: 681b ldr r3, [r3, #0]
- 80025d2: 4a35 ldr r2, [pc, #212] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80025d4: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80025d8: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80025da: f7ff fadb bl 8001b94 <HAL_GetTick>
- 80025de: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80025e0: e008 b.n 80025f4 <HAL_RCC_OscConfig+0x428>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80025e2: f7ff fad7 bl 8001b94 <HAL_GetTick>
- 80025e6: 4602 mov r2, r0
- 80025e8: 693b ldr r3, [r7, #16]
- 80025ea: 1ad3 subs r3, r2, r3
- 80025ec: 2b02 cmp r3, #2
- 80025ee: d901 bls.n 80025f4 <HAL_RCC_OscConfig+0x428>
- {
- return HAL_TIMEOUT;
- 80025f0: 2303 movs r3, #3
- 80025f2: e055 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80025f4: 4b2c ldr r3, [pc, #176] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 80025f6: 681b ldr r3, [r3, #0]
- 80025f8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80025fc: 2b00 cmp r3, #0
- 80025fe: d1f0 bne.n 80025e2 <HAL_RCC_OscConfig+0x416>
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
-#if defined (RCC_PLLCFGR_PLLR)
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8002600: 687b ldr r3, [r7, #4]
- 8002602: 69da ldr r2, [r3, #28]
- 8002604: 687b ldr r3, [r7, #4]
- 8002606: 6a1b ldr r3, [r3, #32]
- 8002608: 431a orrs r2, r3
- 800260a: 687b ldr r3, [r7, #4]
- 800260c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800260e: 019b lsls r3, r3, #6
- 8002610: 431a orrs r2, r3
- 8002612: 687b ldr r3, [r7, #4]
- 8002614: 6a9b ldr r3, [r3, #40] ; 0x28
- 8002616: 085b lsrs r3, r3, #1
- 8002618: 3b01 subs r3, #1
- 800261a: 041b lsls r3, r3, #16
- 800261c: 431a orrs r2, r3
- 800261e: 687b ldr r3, [r7, #4]
- 8002620: 6adb ldr r3, [r3, #44] ; 0x2c
- 8002622: 061b lsls r3, r3, #24
- 8002624: 431a orrs r2, r3
- 8002626: 687b ldr r3, [r7, #4]
- 8002628: 6b1b ldr r3, [r3, #48] ; 0x30
- 800262a: 071b lsls r3, r3, #28
- 800262c: 491e ldr r1, [pc, #120] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800262e: 4313 orrs r3, r2
- 8002630: 604b str r3, [r1, #4]
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
-#endif
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
- 8002632: 4b1d ldr r3, [pc, #116] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002634: 681b ldr r3, [r3, #0]
- 8002636: 4a1c ldr r2, [pc, #112] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002638: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 800263c: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800263e: f7ff faa9 bl 8001b94 <HAL_GetTick>
- 8002642: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8002644: e008 b.n 8002658 <HAL_RCC_OscConfig+0x48c>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8002646: f7ff faa5 bl 8001b94 <HAL_GetTick>
- 800264a: 4602 mov r2, r0
- 800264c: 693b ldr r3, [r7, #16]
- 800264e: 1ad3 subs r3, r2, r3
- 8002650: 2b02 cmp r3, #2
- 8002652: d901 bls.n 8002658 <HAL_RCC_OscConfig+0x48c>
- {
- return HAL_TIMEOUT;
- 8002654: 2303 movs r3, #3
- 8002656: e023 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8002658: 4b13 ldr r3, [pc, #76] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800265a: 681b ldr r3, [r3, #0]
- 800265c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002660: 2b00 cmp r3, #0
- 8002662: d0f0 beq.n 8002646 <HAL_RCC_OscConfig+0x47a>
- 8002664: e01b b.n 800269e <HAL_RCC_OscConfig+0x4d2>
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 8002666: 4b10 ldr r3, [pc, #64] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 8002668: 681b ldr r3, [r3, #0]
- 800266a: 4a0f ldr r2, [pc, #60] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800266c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002670: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002672: f7ff fa8f bl 8001b94 <HAL_GetTick>
- 8002676: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002678: e008 b.n 800268c <HAL_RCC_OscConfig+0x4c0>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 800267a: f7ff fa8b bl 8001b94 <HAL_GetTick>
- 800267e: 4602 mov r2, r0
- 8002680: 693b ldr r3, [r7, #16]
- 8002682: 1ad3 subs r3, r2, r3
- 8002684: 2b02 cmp r3, #2
- 8002686: d901 bls.n 800268c <HAL_RCC_OscConfig+0x4c0>
- {
- return HAL_TIMEOUT;
- 8002688: 2303 movs r3, #3
- 800268a: e009 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 800268c: 4b06 ldr r3, [pc, #24] ; (80026a8 <HAL_RCC_OscConfig+0x4dc>)
- 800268e: 681b ldr r3, [r3, #0]
- 8002690: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002694: 2b00 cmp r3, #0
- 8002696: d1f0 bne.n 800267a <HAL_RCC_OscConfig+0x4ae>
- 8002698: e001 b.n 800269e <HAL_RCC_OscConfig+0x4d2>
- }
- }
- }
- else
- {
- return HAL_ERROR;
- 800269a: 2301 movs r3, #1
- 800269c: e000 b.n 80026a0 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- return HAL_OK;
- 800269e: 2300 movs r3, #0
-}
- 80026a0: 4618 mov r0, r3
- 80026a2: 3718 adds r7, #24
- 80026a4: 46bd mov sp, r7
- 80026a6: bd80 pop {r7, pc}
- 80026a8: 40023800 .word 0x40023800
- 80026ac: 40007000 .word 0x40007000
-
-080026b0 <HAL_RCC_ClockConfig>:
- * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 80026b0: b580 push {r7, lr}
- 80026b2: b084 sub sp, #16
- 80026b4: af00 add r7, sp, #0
- 80026b6: 6078 str r0, [r7, #4]
- 80026b8: 6039 str r1, [r7, #0]
- uint32_t tickstart = 0;
- 80026ba: 2300 movs r3, #0
- 80026bc: 60fb str r3, [r7, #12]
-
- /* Check Null pointer */
- if(RCC_ClkInitStruct == NULL)
- 80026be: 687b ldr r3, [r7, #4]
- 80026c0: 2b00 cmp r3, #0
- 80026c2: d101 bne.n 80026c8 <HAL_RCC_ClockConfig+0x18>
- {
- return HAL_ERROR;
- 80026c4: 2301 movs r3, #1
- 80026c6: e0ce b.n 8002866 <HAL_RCC_ClockConfig+0x1b6>
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
- /* Increasing the CPU frequency */
- if(FLatency > __HAL_FLASH_GET_LATENCY())
- 80026c8: 4b69 ldr r3, [pc, #420] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80026ca: 681b ldr r3, [r3, #0]
- 80026cc: f003 030f and.w r3, r3, #15
- 80026d0: 683a ldr r2, [r7, #0]
- 80026d2: 429a cmp r2, r3
- 80026d4: d910 bls.n 80026f8 <HAL_RCC_ClockConfig+0x48>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 80026d6: 4b66 ldr r3, [pc, #408] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80026d8: 681b ldr r3, [r3, #0]
- 80026da: f023 020f bic.w r2, r3, #15
- 80026de: 4964 ldr r1, [pc, #400] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80026e0: 683b ldr r3, [r7, #0]
- 80026e2: 4313 orrs r3, r2
- 80026e4: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 80026e6: 4b62 ldr r3, [pc, #392] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80026e8: 681b ldr r3, [r3, #0]
- 80026ea: f003 030f and.w r3, r3, #15
- 80026ee: 683a ldr r2, [r7, #0]
- 80026f0: 429a cmp r2, r3
- 80026f2: d001 beq.n 80026f8 <HAL_RCC_ClockConfig+0x48>
- {
- return HAL_ERROR;
- 80026f4: 2301 movs r3, #1
- 80026f6: e0b6 b.n 8002866 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 80026f8: 687b ldr r3, [r7, #4]
- 80026fa: 681b ldr r3, [r3, #0]
- 80026fc: f003 0302 and.w r3, r3, #2
- 8002700: 2b00 cmp r3, #0
- 8002702: d020 beq.n 8002746 <HAL_RCC_ClockConfig+0x96>
- {
- /* Set the highest APBx dividers in order to ensure that we do not go through
- a non-spec phase whatever we decrease or increase HCLK. */
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002704: 687b ldr r3, [r7, #4]
- 8002706: 681b ldr r3, [r3, #0]
- 8002708: f003 0304 and.w r3, r3, #4
- 800270c: 2b00 cmp r3, #0
- 800270e: d005 beq.n 800271c <HAL_RCC_ClockConfig+0x6c>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 8002710: 4b58 ldr r3, [pc, #352] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002712: 689b ldr r3, [r3, #8]
- 8002714: 4a57 ldr r2, [pc, #348] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002716: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 800271a: 6093 str r3, [r2, #8]
- }
-
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 800271c: 687b ldr r3, [r7, #4]
- 800271e: 681b ldr r3, [r3, #0]
- 8002720: f003 0308 and.w r3, r3, #8
- 8002724: 2b00 cmp r3, #0
- 8002726: d005 beq.n 8002734 <HAL_RCC_ClockConfig+0x84>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 8002728: 4b52 ldr r3, [pc, #328] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 800272a: 689b ldr r3, [r3, #8]
- 800272c: 4a51 ldr r2, [pc, #324] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 800272e: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 8002732: 6093 str r3, [r2, #8]
- }
-
- /* Set the new HCLK clock divider */
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8002734: 4b4f ldr r3, [pc, #316] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002736: 689b ldr r3, [r3, #8]
- 8002738: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 800273c: 687b ldr r3, [r7, #4]
- 800273e: 689b ldr r3, [r3, #8]
- 8002740: 494c ldr r1, [pc, #304] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002742: 4313 orrs r3, r2
- 8002744: 608b str r3, [r1, #8]
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8002746: 687b ldr r3, [r7, #4]
- 8002748: 681b ldr r3, [r3, #0]
- 800274a: f003 0301 and.w r3, r3, #1
- 800274e: 2b00 cmp r3, #0
- 8002750: d040 beq.n 80027d4 <HAL_RCC_ClockConfig+0x124>
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8002752: 687b ldr r3, [r7, #4]
- 8002754: 685b ldr r3, [r3, #4]
- 8002756: 2b01 cmp r3, #1
- 8002758: d107 bne.n 800276a <HAL_RCC_ClockConfig+0xba>
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800275a: 4b46 ldr r3, [pc, #280] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 800275c: 681b ldr r3, [r3, #0]
- 800275e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002762: 2b00 cmp r3, #0
- 8002764: d115 bne.n 8002792 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 8002766: 2301 movs r3, #1
- 8002768: e07d b.n 8002866 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 800276a: 687b ldr r3, [r7, #4]
- 800276c: 685b ldr r3, [r3, #4]
- 800276e: 2b02 cmp r3, #2
- 8002770: d107 bne.n 8002782 <HAL_RCC_ClockConfig+0xd2>
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8002772: 4b40 ldr r3, [pc, #256] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002774: 681b ldr r3, [r3, #0]
- 8002776: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 800277a: 2b00 cmp r3, #0
- 800277c: d109 bne.n 8002792 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 800277e: 2301 movs r3, #1
- 8002780: e071 b.n 8002866 <HAL_RCC_ClockConfig+0x1b6>
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8002782: 4b3c ldr r3, [pc, #240] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002784: 681b ldr r3, [r3, #0]
- 8002786: f003 0302 and.w r3, r3, #2
- 800278a: 2b00 cmp r3, #0
- 800278c: d101 bne.n 8002792 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 800278e: 2301 movs r3, #1
- 8002790: e069 b.n 8002866 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 8002792: 4b38 ldr r3, [pc, #224] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002794: 689b ldr r3, [r3, #8]
- 8002796: f023 0203 bic.w r2, r3, #3
- 800279a: 687b ldr r3, [r7, #4]
- 800279c: 685b ldr r3, [r3, #4]
- 800279e: 4935 ldr r1, [pc, #212] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 80027a0: 4313 orrs r3, r2
- 80027a2: 608b str r3, [r1, #8]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80027a4: f7ff f9f6 bl 8001b94 <HAL_GetTick>
- 80027a8: 60f8 str r0, [r7, #12]
-
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 80027aa: e00a b.n 80027c2 <HAL_RCC_ClockConfig+0x112>
- {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 80027ac: f7ff f9f2 bl 8001b94 <HAL_GetTick>
- 80027b0: 4602 mov r2, r0
- 80027b2: 68fb ldr r3, [r7, #12]
- 80027b4: 1ad3 subs r3, r2, r3
- 80027b6: f241 3288 movw r2, #5000 ; 0x1388
- 80027ba: 4293 cmp r3, r2
- 80027bc: d901 bls.n 80027c2 <HAL_RCC_ClockConfig+0x112>
- {
- return HAL_TIMEOUT;
- 80027be: 2303 movs r3, #3
- 80027c0: e051 b.n 8002866 <HAL_RCC_ClockConfig+0x1b6>
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 80027c2: 4b2c ldr r3, [pc, #176] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 80027c4: 689b ldr r3, [r3, #8]
- 80027c6: f003 020c and.w r2, r3, #12
- 80027ca: 687b ldr r3, [r7, #4]
- 80027cc: 685b ldr r3, [r3, #4]
- 80027ce: 009b lsls r3, r3, #2
- 80027d0: 429a cmp r2, r3
- 80027d2: d1eb bne.n 80027ac <HAL_RCC_ClockConfig+0xfc>
- }
- }
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < __HAL_FLASH_GET_LATENCY())
- 80027d4: 4b26 ldr r3, [pc, #152] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80027d6: 681b ldr r3, [r3, #0]
- 80027d8: f003 030f and.w r3, r3, #15
- 80027dc: 683a ldr r2, [r7, #0]
- 80027de: 429a cmp r2, r3
- 80027e0: d210 bcs.n 8002804 <HAL_RCC_ClockConfig+0x154>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 80027e2: 4b23 ldr r3, [pc, #140] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80027e4: 681b ldr r3, [r3, #0]
- 80027e6: f023 020f bic.w r2, r3, #15
- 80027ea: 4921 ldr r1, [pc, #132] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80027ec: 683b ldr r3, [r7, #0]
- 80027ee: 4313 orrs r3, r2
- 80027f0: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 80027f2: 4b1f ldr r3, [pc, #124] ; (8002870 <HAL_RCC_ClockConfig+0x1c0>)
- 80027f4: 681b ldr r3, [r3, #0]
- 80027f6: f003 030f and.w r3, r3, #15
- 80027fa: 683a ldr r2, [r7, #0]
- 80027fc: 429a cmp r2, r3
- 80027fe: d001 beq.n 8002804 <HAL_RCC_ClockConfig+0x154>
- {
- return HAL_ERROR;
- 8002800: 2301 movs r3, #1
- 8002802: e030 b.n 8002866 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002804: 687b ldr r3, [r7, #4]
- 8002806: 681b ldr r3, [r3, #0]
- 8002808: f003 0304 and.w r3, r3, #4
- 800280c: 2b00 cmp r3, #0
- 800280e: d008 beq.n 8002822 <HAL_RCC_ClockConfig+0x172>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8002810: 4b18 ldr r3, [pc, #96] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002812: 689b ldr r3, [r3, #8]
- 8002814: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 8002818: 687b ldr r3, [r7, #4]
- 800281a: 68db ldr r3, [r3, #12]
- 800281c: 4915 ldr r1, [pc, #84] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 800281e: 4313 orrs r3, r2
- 8002820: 608b str r3, [r1, #8]
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8002822: 687b ldr r3, [r7, #4]
- 8002824: 681b ldr r3, [r3, #0]
- 8002826: f003 0308 and.w r3, r3, #8
- 800282a: 2b00 cmp r3, #0
- 800282c: d009 beq.n 8002842 <HAL_RCC_ClockConfig+0x192>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 800282e: 4b11 ldr r3, [pc, #68] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 8002830: 689b ldr r3, [r3, #8]
- 8002832: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 8002836: 687b ldr r3, [r7, #4]
- 8002838: 691b ldr r3, [r3, #16]
- 800283a: 00db lsls r3, r3, #3
- 800283c: 490d ldr r1, [pc, #52] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 800283e: 4313 orrs r3, r2
- 8002840: 608b str r3, [r1, #8]
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 8002842: f000 f81d bl 8002880 <HAL_RCC_GetSysClockFreq>
- 8002846: 4601 mov r1, r0
- 8002848: 4b0a ldr r3, [pc, #40] ; (8002874 <HAL_RCC_ClockConfig+0x1c4>)
- 800284a: 689b ldr r3, [r3, #8]
- 800284c: 091b lsrs r3, r3, #4
- 800284e: f003 030f and.w r3, r3, #15
- 8002852: 4a09 ldr r2, [pc, #36] ; (8002878 <HAL_RCC_ClockConfig+0x1c8>)
- 8002854: 5cd3 ldrb r3, [r2, r3]
- 8002856: fa21 f303 lsr.w r3, r1, r3
- 800285a: 4a08 ldr r2, [pc, #32] ; (800287c <HAL_RCC_ClockConfig+0x1cc>)
- 800285c: 6013 str r3, [r2, #0]
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
- 800285e: 2000 movs r0, #0
- 8002860: f7ff f954 bl 8001b0c <HAL_InitTick>
-
- return HAL_OK;
- 8002864: 2300 movs r3, #0
-}
- 8002866: 4618 mov r0, r3
- 8002868: 3710 adds r7, #16
- 800286a: 46bd mov sp, r7
- 800286c: bd80 pop {r7, pc}
- 800286e: bf00 nop
- 8002870: 40023c00 .word 0x40023c00
- 8002874: 40023800 .word 0x40023800
- 8002878: 080053a4 .word 0x080053a4
- 800287c: 20000000 .word 0x20000000
-
-08002880 <HAL_RCC_GetSysClockFreq>:
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- 8002880: b5f0 push {r4, r5, r6, r7, lr}
- 8002882: b085 sub sp, #20
- 8002884: af00 add r7, sp, #0
- uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 8002886: 2300 movs r3, #0
- 8002888: 607b str r3, [r7, #4]
- 800288a: 2300 movs r3, #0
- 800288c: 60fb str r3, [r7, #12]
- 800288e: 2300 movs r3, #0
- 8002890: 603b str r3, [r7, #0]
- uint32_t sysclockfreq = 0;
- 8002892: 2300 movs r3, #0
- 8002894: 60bb str r3, [r7, #8]
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (RCC->CFGR & RCC_CFGR_SWS)
- 8002896: 4b50 ldr r3, [pc, #320] ; (80029d8 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002898: 689b ldr r3, [r3, #8]
- 800289a: f003 030c and.w r3, r3, #12
- 800289e: 2b04 cmp r3, #4
- 80028a0: d007 beq.n 80028b2 <HAL_RCC_GetSysClockFreq+0x32>
- 80028a2: 2b08 cmp r3, #8
- 80028a4: d008 beq.n 80028b8 <HAL_RCC_GetSysClockFreq+0x38>
- 80028a6: 2b00 cmp r3, #0
- 80028a8: f040 808d bne.w 80029c6 <HAL_RCC_GetSysClockFreq+0x146>
- {
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- {
- sysclockfreq = HSI_VALUE;
- 80028ac: 4b4b ldr r3, [pc, #300] ; (80029dc <HAL_RCC_GetSysClockFreq+0x15c>)
- 80028ae: 60bb str r3, [r7, #8]
- break;
- 80028b0: e08c b.n 80029cc <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- {
- sysclockfreq = HSE_VALUE;
- 80028b2: 4b4b ldr r3, [pc, #300] ; (80029e0 <HAL_RCC_GetSysClockFreq+0x160>)
- 80028b4: 60bb str r3, [r7, #8]
- break;
- 80028b6: e089 b.n 80029cc <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
- {
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP */
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 80028b8: 4b47 ldr r3, [pc, #284] ; (80029d8 <HAL_RCC_GetSysClockFreq+0x158>)
- 80028ba: 685b ldr r3, [r3, #4]
- 80028bc: f003 033f and.w r3, r3, #63 ; 0x3f
- 80028c0: 607b str r3, [r7, #4]
- if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 80028c2: 4b45 ldr r3, [pc, #276] ; (80029d8 <HAL_RCC_GetSysClockFreq+0x158>)
- 80028c4: 685b ldr r3, [r3, #4]
- 80028c6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 80028ca: 2b00 cmp r3, #0
- 80028cc: d023 beq.n 8002916 <HAL_RCC_GetSysClockFreq+0x96>
- {
- /* HSE used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 80028ce: 4b42 ldr r3, [pc, #264] ; (80029d8 <HAL_RCC_GetSysClockFreq+0x158>)
- 80028d0: 685b ldr r3, [r3, #4]
- 80028d2: 099b lsrs r3, r3, #6
- 80028d4: f04f 0400 mov.w r4, #0
- 80028d8: f240 11ff movw r1, #511 ; 0x1ff
- 80028dc: f04f 0200 mov.w r2, #0
- 80028e0: ea03 0501 and.w r5, r3, r1
- 80028e4: ea04 0602 and.w r6, r4, r2
- 80028e8: 4a3d ldr r2, [pc, #244] ; (80029e0 <HAL_RCC_GetSysClockFreq+0x160>)
- 80028ea: fb02 f106 mul.w r1, r2, r6
- 80028ee: 2200 movs r2, #0
- 80028f0: fb02 f205 mul.w r2, r2, r5
- 80028f4: 440a add r2, r1
- 80028f6: 493a ldr r1, [pc, #232] ; (80029e0 <HAL_RCC_GetSysClockFreq+0x160>)
- 80028f8: fba5 0101 umull r0, r1, r5, r1
- 80028fc: 1853 adds r3, r2, r1
- 80028fe: 4619 mov r1, r3
- 8002900: 687b ldr r3, [r7, #4]
- 8002902: f04f 0400 mov.w r4, #0
- 8002906: 461a mov r2, r3
- 8002908: 4623 mov r3, r4
- 800290a: f7fd fc95 bl 8000238 <__aeabi_uldivmod>
- 800290e: 4603 mov r3, r0
- 8002910: 460c mov r4, r1
- 8002912: 60fb str r3, [r7, #12]
- 8002914: e049 b.n 80029aa <HAL_RCC_GetSysClockFreq+0x12a>
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002916: 4b30 ldr r3, [pc, #192] ; (80029d8 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002918: 685b ldr r3, [r3, #4]
- 800291a: 099b lsrs r3, r3, #6
- 800291c: f04f 0400 mov.w r4, #0
- 8002920: f240 11ff movw r1, #511 ; 0x1ff
- 8002924: f04f 0200 mov.w r2, #0
- 8002928: ea03 0501 and.w r5, r3, r1
- 800292c: ea04 0602 and.w r6, r4, r2
- 8002930: 4629 mov r1, r5
- 8002932: 4632 mov r2, r6
- 8002934: f04f 0300 mov.w r3, #0
- 8002938: f04f 0400 mov.w r4, #0
- 800293c: 0154 lsls r4, r2, #5
- 800293e: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 8002942: 014b lsls r3, r1, #5
- 8002944: 4619 mov r1, r3
- 8002946: 4622 mov r2, r4
- 8002948: 1b49 subs r1, r1, r5
- 800294a: eb62 0206 sbc.w r2, r2, r6
- 800294e: f04f 0300 mov.w r3, #0
- 8002952: f04f 0400 mov.w r4, #0
- 8002956: 0194 lsls r4, r2, #6
- 8002958: ea44 6491 orr.w r4, r4, r1, lsr #26
- 800295c: 018b lsls r3, r1, #6
- 800295e: 1a5b subs r3, r3, r1
- 8002960: eb64 0402 sbc.w r4, r4, r2
- 8002964: f04f 0100 mov.w r1, #0
- 8002968: f04f 0200 mov.w r2, #0
- 800296c: 00e2 lsls r2, r4, #3
- 800296e: ea42 7253 orr.w r2, r2, r3, lsr #29
- 8002972: 00d9 lsls r1, r3, #3
- 8002974: 460b mov r3, r1
- 8002976: 4614 mov r4, r2
- 8002978: 195b adds r3, r3, r5
- 800297a: eb44 0406 adc.w r4, r4, r6
- 800297e: f04f 0100 mov.w r1, #0
- 8002982: f04f 0200 mov.w r2, #0
- 8002986: 02a2 lsls r2, r4, #10
- 8002988: ea42 5293 orr.w r2, r2, r3, lsr #22
- 800298c: 0299 lsls r1, r3, #10
- 800298e: 460b mov r3, r1
- 8002990: 4614 mov r4, r2
- 8002992: 4618 mov r0, r3
- 8002994: 4621 mov r1, r4
- 8002996: 687b ldr r3, [r7, #4]
- 8002998: f04f 0400 mov.w r4, #0
- 800299c: 461a mov r2, r3
- 800299e: 4623 mov r3, r4
- 80029a0: f7fd fc4a bl 8000238 <__aeabi_uldivmod>
- 80029a4: 4603 mov r3, r0
- 80029a6: 460c mov r4, r1
- 80029a8: 60fb str r3, [r7, #12]
- }
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 80029aa: 4b0b ldr r3, [pc, #44] ; (80029d8 <HAL_RCC_GetSysClockFreq+0x158>)
- 80029ac: 685b ldr r3, [r3, #4]
- 80029ae: 0c1b lsrs r3, r3, #16
- 80029b0: f003 0303 and.w r3, r3, #3
- 80029b4: 3301 adds r3, #1
- 80029b6: 005b lsls r3, r3, #1
- 80029b8: 603b str r3, [r7, #0]
-
- sysclockfreq = pllvco/pllp;
- 80029ba: 68fa ldr r2, [r7, #12]
- 80029bc: 683b ldr r3, [r7, #0]
- 80029be: fbb2 f3f3 udiv r3, r2, r3
- 80029c2: 60bb str r3, [r7, #8]
- break;
- 80029c4: e002 b.n 80029cc <HAL_RCC_GetSysClockFreq+0x14c>
- }
- default:
- {
- sysclockfreq = HSI_VALUE;
- 80029c6: 4b05 ldr r3, [pc, #20] ; (80029dc <HAL_RCC_GetSysClockFreq+0x15c>)
- 80029c8: 60bb str r3, [r7, #8]
- break;
- 80029ca: bf00 nop
- }
- }
- return sysclockfreq;
- 80029cc: 68bb ldr r3, [r7, #8]
-}
- 80029ce: 4618 mov r0, r3
- 80029d0: 3714 adds r7, #20
- 80029d2: 46bd mov sp, r7
- 80029d4: bdf0 pop {r4, r5, r6, r7, pc}
- 80029d6: bf00 nop
- 80029d8: 40023800 .word 0x40023800
- 80029dc: 00f42400 .word 0x00f42400
- 80029e0: 017d7840 .word 0x017d7840
-
-080029e4 <HAL_RCC_GetHCLKFreq>:
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- 80029e4: b480 push {r7}
- 80029e6: af00 add r7, sp, #0
- return SystemCoreClock;
- 80029e8: 4b03 ldr r3, [pc, #12] ; (80029f8 <HAL_RCC_GetHCLKFreq+0x14>)
- 80029ea: 681b ldr r3, [r3, #0]
-}
- 80029ec: 4618 mov r0, r3
- 80029ee: 46bd mov sp, r7
- 80029f0: f85d 7b04 ldr.w r7, [sp], #4
- 80029f4: 4770 bx lr
- 80029f6: bf00 nop
- 80029f8: 20000000 .word 0x20000000
-
-080029fc <HAL_RCC_GetPCLK1Freq>:
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- 80029fc: b580 push {r7, lr}
- 80029fe: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 8002a00: f7ff fff0 bl 80029e4 <HAL_RCC_GetHCLKFreq>
- 8002a04: 4601 mov r1, r0
- 8002a06: 4b05 ldr r3, [pc, #20] ; (8002a1c <HAL_RCC_GetPCLK1Freq+0x20>)
- 8002a08: 689b ldr r3, [r3, #8]
- 8002a0a: 0a9b lsrs r3, r3, #10
- 8002a0c: f003 0307 and.w r3, r3, #7
- 8002a10: 4a03 ldr r2, [pc, #12] ; (8002a20 <HAL_RCC_GetPCLK1Freq+0x24>)
- 8002a12: 5cd3 ldrb r3, [r2, r3]
- 8002a14: fa21 f303 lsr.w r3, r1, r3
-}
- 8002a18: 4618 mov r0, r3
- 8002a1a: bd80 pop {r7, pc}
- 8002a1c: 40023800 .word 0x40023800
- 8002a20: 080053b4 .word 0x080053b4
-
-08002a24 <HAL_RCC_GetPCLK2Freq>:
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- 8002a24: b580 push {r7, lr}
- 8002a26: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 8002a28: f7ff ffdc bl 80029e4 <HAL_RCC_GetHCLKFreq>
- 8002a2c: 4601 mov r1, r0
- 8002a2e: 4b05 ldr r3, [pc, #20] ; (8002a44 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8002a30: 689b ldr r3, [r3, #8]
- 8002a32: 0b5b lsrs r3, r3, #13
- 8002a34: f003 0307 and.w r3, r3, #7
- 8002a38: 4a03 ldr r2, [pc, #12] ; (8002a48 <HAL_RCC_GetPCLK2Freq+0x24>)
- 8002a3a: 5cd3 ldrb r3, [r2, r3]
- 8002a3c: fa21 f303 lsr.w r3, r1, r3
-}
- 8002a40: 4618 mov r0, r3
- 8002a42: bd80 pop {r7, pc}
- 8002a44: 40023800 .word 0x40023800
- 8002a48: 080053b4 .word 0x080053b4
-
-08002a4c <HAL_RCCEx_PeriphCLKConfig>:
- * the backup registers) are set to their reset values.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- 8002a4c: b580 push {r7, lr}
- 8002a4e: b088 sub sp, #32
- 8002a50: af00 add r7, sp, #0
- 8002a52: 6078 str r0, [r7, #4]
- uint32_t tickstart = 0;
- 8002a54: 2300 movs r3, #0
- 8002a56: 617b str r3, [r7, #20]
- uint32_t tmpreg0 = 0;
- 8002a58: 2300 movs r3, #0
- 8002a5a: 613b str r3, [r7, #16]
- uint32_t tmpreg1 = 0;
- 8002a5c: 2300 movs r3, #0
- 8002a5e: 60fb str r3, [r7, #12]
- uint32_t plli2sused = 0;
- 8002a60: 2300 movs r3, #0
- 8002a62: 61fb str r3, [r7, #28]
- uint32_t pllsaiused = 0;
- 8002a64: 2300 movs r3, #0
- 8002a66: 61bb str r3, [r7, #24]
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*----------------------------------- I2S configuration ----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 8002a68: 687b ldr r3, [r7, #4]
- 8002a6a: 681b ldr r3, [r3, #0]
- 8002a6c: f003 0301 and.w r3, r3, #1
- 8002a70: 2b00 cmp r3, #0
- 8002a72: d012 beq.n 8002a9a <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure I2S Clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 8002a74: 4b69 ldr r3, [pc, #420] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a76: 689b ldr r3, [r3, #8]
- 8002a78: 4a68 ldr r2, [pc, #416] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a7a: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
- 8002a7e: 6093 str r3, [r2, #8]
- 8002a80: 4b66 ldr r3, [pc, #408] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a82: 689a ldr r2, [r3, #8]
- 8002a84: 687b ldr r3, [r7, #4]
- 8002a86: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002a88: 4964 ldr r1, [pc, #400] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a8a: 4313 orrs r3, r2
- 8002a8c: 608b str r3, [r1, #8]
-
- /* Enable the PLLI2S when it's used as clock source for I2S */
- if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 8002a8e: 687b ldr r3, [r7, #4]
- 8002a90: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002a92: 2b00 cmp r3, #0
- 8002a94: d101 bne.n 8002a9a <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- plli2sused = 1;
- 8002a96: 2301 movs r3, #1
- 8002a98: 61fb str r3, [r7, #28]
- }
- }
-
- /*------------------------------------ SAI1 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 8002a9a: 687b ldr r3, [r7, #4]
- 8002a9c: 681b ldr r3, [r3, #0]
- 8002a9e: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002aa2: 2b00 cmp r3, #0
- 8002aa4: d017 beq.n 8002ad6 <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
- /* Configure SAI1 Clock source */
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 8002aa6: 4b5d ldr r3, [pc, #372] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002aa8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002aac: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002ab0: 687b ldr r3, [r7, #4]
- 8002ab2: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002ab4: 4959 ldr r1, [pc, #356] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ab6: 4313 orrs r3, r2
- 8002ab8: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8002abc: 687b ldr r3, [r7, #4]
- 8002abe: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002ac0: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8002ac4: d101 bne.n 8002aca <HAL_RCCEx_PeriphCLKConfig+0x7e>
- {
- plli2sused = 1;
- 8002ac6: 2301 movs r3, #1
- 8002ac8: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 8002aca: 687b ldr r3, [r7, #4]
- 8002acc: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002ace: 2b00 cmp r3, #0
- 8002ad0: d101 bne.n 8002ad6 <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- pllsaiused = 1;
- 8002ad2: 2301 movs r3, #1
- 8002ad4: 61bb str r3, [r7, #24]
- }
- }
-
- /*------------------------------------ SAI2 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 8002ad6: 687b ldr r3, [r7, #4]
- 8002ad8: 681b ldr r3, [r3, #0]
- 8002ada: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8002ade: 2b00 cmp r3, #0
- 8002ae0: d017 beq.n 8002b12 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
- /* Configure SAI2 Clock source */
- __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 8002ae2: 4b4e ldr r3, [pc, #312] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ae4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002ae8: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002aec: 687b ldr r3, [r7, #4]
- 8002aee: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002af0: 494a ldr r1, [pc, #296] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002af2: 4313 orrs r3, r2
- 8002af4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
-
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 8002af8: 687b ldr r3, [r7, #4]
- 8002afa: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002afc: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002b00: d101 bne.n 8002b06 <HAL_RCCEx_PeriphCLKConfig+0xba>
- {
- plli2sused = 1;
- 8002b02: 2301 movs r3, #1
- 8002b04: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 8002b06: 687b ldr r3, [r7, #4]
- 8002b08: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002b0a: 2b00 cmp r3, #0
- 8002b0c: d101 bne.n 8002b12 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- pllsaiused = 1;
- 8002b0e: 2301 movs r3, #1
- 8002b10: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8002b12: 687b ldr r3, [r7, #4]
- 8002b14: 681b ldr r3, [r3, #0]
- 8002b16: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8002b1a: 2b00 cmp r3, #0
- 8002b1c: d001 beq.n 8002b22 <HAL_RCCEx_PeriphCLKConfig+0xd6>
- {
- plli2sused = 1;
- 8002b1e: 2301 movs r3, #1
- 8002b20: 61fb str r3, [r7, #28]
- }
-
- /*------------------------------------ RTC configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 8002b22: 687b ldr r3, [r7, #4]
- 8002b24: 681b ldr r3, [r3, #0]
- 8002b26: f003 0320 and.w r3, r3, #32
- 8002b2a: 2b00 cmp r3, #0
- 8002b2c: f000 808b beq.w 8002c46 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
- {
- /* Check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 8002b30: 4b3a ldr r3, [pc, #232] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002b32: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002b34: 4a39 ldr r2, [pc, #228] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002b36: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8002b3a: 6413 str r3, [r2, #64] ; 0x40
- 8002b3c: 4b37 ldr r3, [pc, #220] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002b3e: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002b40: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002b44: 60bb str r3, [r7, #8]
- 8002b46: 68bb ldr r3, [r7, #8]
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 8002b48: 4b35 ldr r3, [pc, #212] ; (8002c20 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002b4a: 681b ldr r3, [r3, #0]
- 8002b4c: 4a34 ldr r2, [pc, #208] ; (8002c20 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002b4e: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8002b52: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002b54: f7ff f81e bl 8001b94 <HAL_GetTick>
- 8002b58: 6178 str r0, [r7, #20]
-
- /* Wait for Backup domain Write protection disable */
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002b5a: e008 b.n 8002b6e <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8002b5c: f7ff f81a bl 8001b94 <HAL_GetTick>
- 8002b60: 4602 mov r2, r0
- 8002b62: 697b ldr r3, [r7, #20]
- 8002b64: 1ad3 subs r3, r2, r3
- 8002b66: 2b64 cmp r3, #100 ; 0x64
- 8002b68: d901 bls.n 8002b6e <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- return HAL_TIMEOUT;
- 8002b6a: 2303 movs r3, #3
- 8002b6c: e38d b.n 800328a <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002b6e: 4b2c ldr r3, [pc, #176] ; (8002c20 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002b70: 681b ldr r3, [r3, #0]
- 8002b72: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002b76: 2b00 cmp r3, #0
- 8002b78: d0f0 beq.n 8002b5c <HAL_RCCEx_PeriphCLKConfig+0x110>
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8002b7a: 4b28 ldr r3, [pc, #160] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002b7c: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002b7e: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002b82: 613b str r3, [r7, #16]
-
- if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8002b84: 693b ldr r3, [r7, #16]
- 8002b86: 2b00 cmp r3, #0
- 8002b88: d035 beq.n 8002bf6 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8002b8a: 687b ldr r3, [r7, #4]
- 8002b8c: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002b8e: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002b92: 693a ldr r2, [r7, #16]
- 8002b94: 429a cmp r2, r3
- 8002b96: d02e beq.n 8002bf6 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8002b98: 4b20 ldr r3, [pc, #128] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002b9a: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002b9c: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8002ba0: 613b str r3, [r7, #16]
-
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- 8002ba2: 4b1e ldr r3, [pc, #120] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ba4: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002ba6: 4a1d ldr r2, [pc, #116] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ba8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002bac: 6713 str r3, [r2, #112] ; 0x70
- __HAL_RCC_BACKUPRESET_RELEASE();
- 8002bae: 4b1b ldr r3, [pc, #108] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bb0: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002bb2: 4a1a ldr r2, [pc, #104] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bb4: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002bb8: 6713 str r3, [r2, #112] ; 0x70
-
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg0;
- 8002bba: 4a18 ldr r2, [pc, #96] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bbc: 693b ldr r3, [r7, #16]
- 8002bbe: 6713 str r3, [r2, #112] ; 0x70
-
- /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
- if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8002bc0: 4b16 ldr r3, [pc, #88] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bc2: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002bc4: f003 0301 and.w r3, r3, #1
- 8002bc8: 2b01 cmp r3, #1
- 8002bca: d114 bne.n 8002bf6 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002bcc: f7fe ffe2 bl 8001b94 <HAL_GetTick>
- 8002bd0: 6178 str r0, [r7, #20]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002bd2: e00a b.n 8002bea <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002bd4: f7fe ffde bl 8001b94 <HAL_GetTick>
- 8002bd8: 4602 mov r2, r0
- 8002bda: 697b ldr r3, [r7, #20]
- 8002bdc: 1ad3 subs r3, r2, r3
- 8002bde: f241 3288 movw r2, #5000 ; 0x1388
- 8002be2: 4293 cmp r3, r2
- 8002be4: d901 bls.n 8002bea <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- return HAL_TIMEOUT;
- 8002be6: 2303 movs r3, #3
- 8002be8: e34f b.n 800328a <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002bea: 4b0c ldr r3, [pc, #48] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bec: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002bee: f003 0302 and.w r3, r3, #2
- 8002bf2: 2b00 cmp r3, #0
- 8002bf4: d0ee beq.n 8002bd4 <HAL_RCCEx_PeriphCLKConfig+0x188>
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8002bf6: 687b ldr r3, [r7, #4]
- 8002bf8: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002bfa: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002bfe: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8002c02: d111 bne.n 8002c28 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8002c04: 4b05 ldr r3, [pc, #20] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002c06: 689b ldr r3, [r3, #8]
- 8002c08: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
- 8002c0c: 687b ldr r3, [r7, #4]
- 8002c0e: 6b19 ldr r1, [r3, #48] ; 0x30
- 8002c10: 4b04 ldr r3, [pc, #16] ; (8002c24 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8002c12: 400b ands r3, r1
- 8002c14: 4901 ldr r1, [pc, #4] ; (8002c1c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002c16: 4313 orrs r3, r2
- 8002c18: 608b str r3, [r1, #8]
- 8002c1a: e00b b.n 8002c34 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8002c1c: 40023800 .word 0x40023800
- 8002c20: 40007000 .word 0x40007000
- 8002c24: 0ffffcff .word 0x0ffffcff
- 8002c28: 4bb3 ldr r3, [pc, #716] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c2a: 689b ldr r3, [r3, #8]
- 8002c2c: 4ab2 ldr r2, [pc, #712] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c2e: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
- 8002c32: 6093 str r3, [r2, #8]
- 8002c34: 4bb0 ldr r3, [pc, #704] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c36: 6f1a ldr r2, [r3, #112] ; 0x70
- 8002c38: 687b ldr r3, [r7, #4]
- 8002c3a: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002c3c: f3c3 030b ubfx r3, r3, #0, #12
- 8002c40: 49ad ldr r1, [pc, #692] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c42: 4313 orrs r3, r2
- 8002c44: 670b str r3, [r1, #112] ; 0x70
- }
-
- /*------------------------------------ TIM configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 8002c46: 687b ldr r3, [r7, #4]
- 8002c48: 681b ldr r3, [r3, #0]
- 8002c4a: f003 0310 and.w r3, r3, #16
- 8002c4e: 2b00 cmp r3, #0
- 8002c50: d010 beq.n 8002c74 <HAL_RCCEx_PeriphCLKConfig+0x228>
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
-
- /* Configure Timer Prescaler */
- __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 8002c52: 4ba9 ldr r3, [pc, #676] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c54: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002c58: 4aa7 ldr r2, [pc, #668] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c5a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002c5e: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 8002c62: 4ba5 ldr r3, [pc, #660] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c64: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
- 8002c68: 687b ldr r3, [r7, #4]
- 8002c6a: 6b9b ldr r3, [r3, #56] ; 0x38
- 8002c6c: 49a2 ldr r1, [pc, #648] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c6e: 4313 orrs r3, r2
- 8002c70: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*-------------------------------------- I2C1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 8002c74: 687b ldr r3, [r7, #4]
- 8002c76: 681b ldr r3, [r3, #0]
- 8002c78: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8002c7c: 2b00 cmp r3, #0
- 8002c7e: d00a beq.n 8002c96 <HAL_RCCEx_PeriphCLKConfig+0x24a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8002c80: 4b9d ldr r3, [pc, #628] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c82: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002c86: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8002c8a: 687b ldr r3, [r7, #4]
- 8002c8c: 6e5b ldr r3, [r3, #100] ; 0x64
- 8002c8e: 499a ldr r1, [pc, #616] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c90: 4313 orrs r3, r2
- 8002c92: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 8002c96: 687b ldr r3, [r7, #4]
- 8002c98: 681b ldr r3, [r3, #0]
- 8002c9a: f403 4300 and.w r3, r3, #32768 ; 0x8000
- 8002c9e: 2b00 cmp r3, #0
- 8002ca0: d00a beq.n 8002cb8 <HAL_RCCEx_PeriphCLKConfig+0x26c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8002ca2: 4b95 ldr r3, [pc, #596] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ca4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ca8: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
- 8002cac: 687b ldr r3, [r7, #4]
- 8002cae: 6e9b ldr r3, [r3, #104] ; 0x68
- 8002cb0: 4991 ldr r1, [pc, #580] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cb2: 4313 orrs r3, r2
- 8002cb4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8002cb8: 687b ldr r3, [r7, #4]
- 8002cba: 681b ldr r3, [r3, #0]
- 8002cbc: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8002cc0: 2b00 cmp r3, #0
- 8002cc2: d00a beq.n 8002cda <HAL_RCCEx_PeriphCLKConfig+0x28e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8002cc4: 4b8c ldr r3, [pc, #560] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cc6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002cca: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002cce: 687b ldr r3, [r7, #4]
- 8002cd0: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002cd2: 4989 ldr r1, [pc, #548] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cd4: 4313 orrs r3, r2
- 8002cd6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8002cda: 687b ldr r3, [r7, #4]
- 8002cdc: 681b ldr r3, [r3, #0]
- 8002cde: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002ce2: 2b00 cmp r3, #0
- 8002ce4: d00a beq.n 8002cfc <HAL_RCCEx_PeriphCLKConfig+0x2b0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- /* Configure the I2C4 clock source */
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8002ce6: 4b84 ldr r3, [pc, #528] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ce8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002cec: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002cf0: 687b ldr r3, [r7, #4]
- 8002cf2: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002cf4: 4980 ldr r1, [pc, #512] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cf6: 4313 orrs r3, r2
- 8002cf8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8002cfc: 687b ldr r3, [r7, #4]
- 8002cfe: 681b ldr r3, [r3, #0]
- 8002d00: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002d04: 2b00 cmp r3, #0
- 8002d06: d00a beq.n 8002d1e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8002d08: 4b7b ldr r3, [pc, #492] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d0a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d0e: f023 0203 bic.w r2, r3, #3
- 8002d12: 687b ldr r3, [r7, #4]
- 8002d14: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002d16: 4978 ldr r1, [pc, #480] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d18: 4313 orrs r3, r2
- 8002d1a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8002d1e: 687b ldr r3, [r7, #4]
- 8002d20: 681b ldr r3, [r3, #0]
- 8002d22: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002d26: 2b00 cmp r3, #0
- 8002d28: d00a beq.n 8002d40 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8002d2a: 4b73 ldr r3, [pc, #460] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d2c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d30: f023 020c bic.w r2, r3, #12
- 8002d34: 687b ldr r3, [r7, #4]
- 8002d36: 6c9b ldr r3, [r3, #72] ; 0x48
- 8002d38: 496f ldr r1, [pc, #444] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d3a: 4313 orrs r3, r2
- 8002d3c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8002d40: 687b ldr r3, [r7, #4]
- 8002d42: 681b ldr r3, [r3, #0]
- 8002d44: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002d48: 2b00 cmp r3, #0
- 8002d4a: d00a beq.n 8002d62 <HAL_RCCEx_PeriphCLKConfig+0x316>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8002d4c: 4b6a ldr r3, [pc, #424] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d4e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d52: f023 0230 bic.w r2, r3, #48 ; 0x30
- 8002d56: 687b ldr r3, [r7, #4]
- 8002d58: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8002d5a: 4967 ldr r1, [pc, #412] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d5c: 4313 orrs r3, r2
- 8002d5e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8002d62: 687b ldr r3, [r7, #4]
- 8002d64: 681b ldr r3, [r3, #0]
- 8002d66: f403 7300 and.w r3, r3, #512 ; 0x200
- 8002d6a: 2b00 cmp r3, #0
- 8002d6c: d00a beq.n 8002d84 <HAL_RCCEx_PeriphCLKConfig+0x338>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8002d6e: 4b62 ldr r3, [pc, #392] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d70: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d74: f023 02c0 bic.w r2, r3, #192 ; 0xc0
- 8002d78: 687b ldr r3, [r7, #4]
- 8002d7a: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002d7c: 495e ldr r1, [pc, #376] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d7e: 4313 orrs r3, r2
- 8002d80: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART5 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8002d84: 687b ldr r3, [r7, #4]
- 8002d86: 681b ldr r3, [r3, #0]
- 8002d88: f403 6380 and.w r3, r3, #1024 ; 0x400
- 8002d8c: 2b00 cmp r3, #0
- 8002d8e: d00a beq.n 8002da6 <HAL_RCCEx_PeriphCLKConfig+0x35a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8002d90: 4b59 ldr r3, [pc, #356] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d92: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d96: f423 7240 bic.w r2, r3, #768 ; 0x300
- 8002d9a: 687b ldr r3, [r7, #4]
- 8002d9c: 6d5b ldr r3, [r3, #84] ; 0x54
- 8002d9e: 4956 ldr r1, [pc, #344] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002da0: 4313 orrs r3, r2
- 8002da2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART6 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8002da6: 687b ldr r3, [r7, #4]
- 8002da8: 681b ldr r3, [r3, #0]
- 8002daa: f403 6300 and.w r3, r3, #2048 ; 0x800
- 8002dae: 2b00 cmp r3, #0
- 8002db0: d00a beq.n 8002dc8 <HAL_RCCEx_PeriphCLKConfig+0x37c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
-
- /* Configure the USART6 clock source */
- __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8002db2: 4b51 ldr r3, [pc, #324] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002db4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002db8: f423 6240 bic.w r2, r3, #3072 ; 0xc00
- 8002dbc: 687b ldr r3, [r7, #4]
- 8002dbe: 6d9b ldr r3, [r3, #88] ; 0x58
- 8002dc0: 494d ldr r1, [pc, #308] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002dc2: 4313 orrs r3, r2
- 8002dc4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART7 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8002dc8: 687b ldr r3, [r7, #4]
- 8002dca: 681b ldr r3, [r3, #0]
- 8002dcc: f403 5380 and.w r3, r3, #4096 ; 0x1000
- 8002dd0: 2b00 cmp r3, #0
- 8002dd2: d00a beq.n 8002dea <HAL_RCCEx_PeriphCLKConfig+0x39e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
-
- /* Configure the UART7 clock source */
- __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8002dd4: 4b48 ldr r3, [pc, #288] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002dd6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002dda: f423 5240 bic.w r2, r3, #12288 ; 0x3000
- 8002dde: 687b ldr r3, [r7, #4]
- 8002de0: 6ddb ldr r3, [r3, #92] ; 0x5c
- 8002de2: 4945 ldr r1, [pc, #276] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002de4: 4313 orrs r3, r2
- 8002de6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART8 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 8002dea: 687b ldr r3, [r7, #4]
- 8002dec: 681b ldr r3, [r3, #0]
- 8002dee: f403 5300 and.w r3, r3, #8192 ; 0x2000
- 8002df2: 2b00 cmp r3, #0
- 8002df4: d00a beq.n 8002e0c <HAL_RCCEx_PeriphCLKConfig+0x3c0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
-
- /* Configure the UART8 clock source */
- __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 8002df6: 4b40 ldr r3, [pc, #256] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002df8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002dfc: f423 4240 bic.w r2, r3, #49152 ; 0xc000
- 8002e00: 687b ldr r3, [r7, #4]
- 8002e02: 6e1b ldr r3, [r3, #96] ; 0x60
- 8002e04: 493c ldr r1, [pc, #240] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e06: 4313 orrs r3, r2
- 8002e08: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*--------------------------------------- CEC Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 8002e0c: 687b ldr r3, [r7, #4]
- 8002e0e: 681b ldr r3, [r3, #0]
- 8002e10: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002e14: 2b00 cmp r3, #0
- 8002e16: d00a beq.n 8002e2e <HAL_RCCEx_PeriphCLKConfig+0x3e2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 8002e18: 4b37 ldr r3, [pc, #220] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e1a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e1e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8002e22: 687b ldr r3, [r7, #4]
- 8002e24: 6f9b ldr r3, [r3, #120] ; 0x78
- 8002e26: 4934 ldr r1, [pc, #208] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e28: 4313 orrs r3, r2
- 8002e2a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- CK48 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 8002e2e: 687b ldr r3, [r7, #4]
- 8002e30: 681b ldr r3, [r3, #0]
- 8002e32: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8002e36: 2b00 cmp r3, #0
- 8002e38: d011 beq.n 8002e5e <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
-
- /* Configure the CLK48 source */
- __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 8002e3a: 4b2f ldr r3, [pc, #188] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e3c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e40: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
- 8002e44: 687b ldr r3, [r7, #4]
- 8002e46: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002e48: 492b ldr r1, [pc, #172] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e4a: 4313 orrs r3, r2
- 8002e4c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
-
- /* Enable the PLLSAI when it's used as clock source for CK48 */
- if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 8002e50: 687b ldr r3, [r7, #4]
- 8002e52: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002e54: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8002e58: d101 bne.n 8002e5e <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- pllsaiused = 1;
- 8002e5a: 2301 movs r3, #1
- 8002e5c: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- LTDC Configuration -----------------------------------*/
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 8002e5e: 687b ldr r3, [r7, #4]
- 8002e60: 681b ldr r3, [r3, #0]
- 8002e62: f003 0308 and.w r3, r3, #8
- 8002e66: 2b00 cmp r3, #0
- 8002e68: d001 beq.n 8002e6e <HAL_RCCEx_PeriphCLKConfig+0x422>
- {
- pllsaiused = 1;
- 8002e6a: 2301 movs r3, #1
- 8002e6c: 61bb str r3, [r7, #24]
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 8002e6e: 687b ldr r3, [r7, #4]
- 8002e70: 681b ldr r3, [r3, #0]
- 8002e72: f403 2380 and.w r3, r3, #262144 ; 0x40000
- 8002e76: 2b00 cmp r3, #0
- 8002e78: d00a beq.n 8002e90 <HAL_RCCEx_PeriphCLKConfig+0x444>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
-
- /* Configure the LTPIM1 clock source */
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 8002e7a: 4b1f ldr r3, [pc, #124] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e7c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e80: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
- 8002e84: 687b ldr r3, [r7, #4]
- 8002e86: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002e88: 491b ldr r1, [pc, #108] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e8a: 4313 orrs r3, r2
- 8002e8c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 8002e90: 687b ldr r3, [r7, #4]
- 8002e92: 681b ldr r3, [r3, #0]
- 8002e94: f403 0300 and.w r3, r3, #8388608 ; 0x800000
- 8002e98: 2b00 cmp r3, #0
- 8002e9a: d00b beq.n 8002eb4 <HAL_RCCEx_PeriphCLKConfig+0x468>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
-
- /* Configure the SDMMC1 clock source */
- __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 8002e9c: 4b16 ldr r3, [pc, #88] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e9e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ea2: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
- 8002ea6: 687b ldr r3, [r7, #4]
- 8002ea8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
- 8002eac: 4912 ldr r1, [pc, #72] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002eae: 4313 orrs r3, r2
- 8002eb0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
- /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 8002eb4: 687b ldr r3, [r7, #4]
- 8002eb6: 681b ldr r3, [r3, #0]
- 8002eb8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
- 8002ebc: 2b00 cmp r3, #0
- 8002ebe: d00b beq.n 8002ed8 <HAL_RCCEx_PeriphCLKConfig+0x48c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
-
- /* Configure the SDMMC2 clock source */
- __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 8002ec0: 4b0d ldr r3, [pc, #52] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ec2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ec6: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
- 8002eca: 687b ldr r3, [r7, #4]
- 8002ecc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002ed0: 4909 ldr r1, [pc, #36] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ed2: 4313 orrs r3, r2
- 8002ed4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 8002ed8: 687b ldr r3, [r7, #4]
- 8002eda: 681b ldr r3, [r3, #0]
- 8002edc: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8002ee0: 2b00 cmp r3, #0
- 8002ee2: d00f beq.n 8002f04 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
- /* Configure the DFSDM1 interface clock source */
- __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8002ee4: 4b04 ldr r3, [pc, #16] ; (8002ef8 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ee6: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002eea: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
- 8002eee: 687b ldr r3, [r7, #4]
- 8002ef0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8002ef4: e002 b.n 8002efc <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 8002ef6: bf00 nop
- 8002ef8: 40023800 .word 0x40023800
- 8002efc: 4985 ldr r1, [pc, #532] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002efe: 4313 orrs r3, r2
- 8002f00: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8002f04: 687b ldr r3, [r7, #4]
- 8002f06: 681b ldr r3, [r3, #0]
- 8002f08: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002f0c: 2b00 cmp r3, #0
- 8002f0e: d00b beq.n 8002f28 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
- /* Configure the DFSDM interface clock source */
- __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 8002f10: 4b80 ldr r3, [pc, #512] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f12: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002f16: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8002f1a: 687b ldr r3, [r7, #4]
- 8002f1c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002f20: 497c ldr r1, [pc, #496] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f22: 4313 orrs r3, r2
- 8002f24: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
- /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
- /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
- if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 8002f28: 69fb ldr r3, [r7, #28]
- 8002f2a: 2b01 cmp r3, #1
- 8002f2c: d005 beq.n 8002f3a <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 8002f2e: 687b ldr r3, [r7, #4]
- 8002f30: 681b ldr r3, [r3, #0]
- 8002f32: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 8002f36: f040 80d6 bne.w 80030e6 <HAL_RCCEx_PeriphCLKConfig+0x69a>
- {
- /* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
- 8002f3a: 4b76 ldr r3, [pc, #472] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f3c: 681b ldr r3, [r3, #0]
- 8002f3e: 4a75 ldr r2, [pc, #468] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f40: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
- 8002f44: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002f46: f7fe fe25 bl 8001b94 <HAL_GetTick>
- 8002f4a: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8002f4c: e008 b.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8002f4e: f7fe fe21 bl 8001b94 <HAL_GetTick>
- 8002f52: 4602 mov r2, r0
- 8002f54: 697b ldr r3, [r7, #20]
- 8002f56: 1ad3 subs r3, r2, r3
- 8002f58: 2b64 cmp r3, #100 ; 0x64
- 8002f5a: d901 bls.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8002f5c: 2303 movs r3, #3
- 8002f5e: e194 b.n 800328a <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8002f60: 4b6c ldr r3, [pc, #432] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f62: 681b ldr r3, [r3, #0]
- 8002f64: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8002f68: 2b00 cmp r3, #0
- 8002f6a: d1f0 bne.n 8002f4e <HAL_RCCEx_PeriphCLKConfig+0x502>
-
- /* check for common PLLI2S Parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
- /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 8002f6c: 687b ldr r3, [r7, #4]
- 8002f6e: 681b ldr r3, [r3, #0]
- 8002f70: f003 0301 and.w r3, r3, #1
- 8002f74: 2b00 cmp r3, #0
- 8002f76: d021 beq.n 8002fbc <HAL_RCCEx_PeriphCLKConfig+0x570>
- 8002f78: 687b ldr r3, [r7, #4]
- 8002f7a: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002f7c: 2b00 cmp r3, #0
- 8002f7e: d11d bne.n 8002fbc <HAL_RCCEx_PeriphCLKConfig+0x570>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
- /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8002f80: 4b64 ldr r3, [pc, #400] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f82: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002f86: 0c1b lsrs r3, r3, #16
- 8002f88: f003 0303 and.w r3, r3, #3
- 8002f8c: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8002f8e: 4b61 ldr r3, [pc, #388] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f90: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002f94: 0e1b lsrs r3, r3, #24
- 8002f96: f003 030f and.w r3, r3, #15
- 8002f9a: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 8002f9c: 687b ldr r3, [r7, #4]
- 8002f9e: 685b ldr r3, [r3, #4]
- 8002fa0: 019a lsls r2, r3, #6
- 8002fa2: 693b ldr r3, [r7, #16]
- 8002fa4: 041b lsls r3, r3, #16
- 8002fa6: 431a orrs r2, r3
- 8002fa8: 68fb ldr r3, [r7, #12]
- 8002faa: 061b lsls r3, r3, #24
- 8002fac: 431a orrs r2, r3
- 8002fae: 687b ldr r3, [r7, #4]
- 8002fb0: 689b ldr r3, [r3, #8]
- 8002fb2: 071b lsls r3, r3, #28
- 8002fb4: 4957 ldr r1, [pc, #348] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002fb6: 4313 orrs r3, r2
- 8002fb8: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8002fbc: 687b ldr r3, [r7, #4]
- 8002fbe: 681b ldr r3, [r3, #0]
- 8002fc0: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002fc4: 2b00 cmp r3, #0
- 8002fc6: d004 beq.n 8002fd2 <HAL_RCCEx_PeriphCLKConfig+0x586>
- 8002fc8: 687b ldr r3, [r7, #4]
- 8002fca: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002fcc: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8002fd0: d00a beq.n 8002fe8 <HAL_RCCEx_PeriphCLKConfig+0x59c>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8002fd2: 687b ldr r3, [r7, #4]
- 8002fd4: 681b ldr r3, [r3, #0]
- 8002fd6: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8002fda: 2b00 cmp r3, #0
- 8002fdc: d02e beq.n 800303c <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8002fde: 687b ldr r3, [r7, #4]
- 8002fe0: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002fe2: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002fe6: d129 bne.n 800303c <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
- /* Check for PLLI2S/DIVQ parameters */
- assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
- /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8002fe8: 4b4a ldr r3, [pc, #296] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002fea: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002fee: 0c1b lsrs r3, r3, #16
- 8002ff0: f003 0303 and.w r3, r3, #3
- 8002ff4: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8002ff6: 4b47 ldr r3, [pc, #284] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002ff8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002ffc: 0f1b lsrs r3, r3, #28
- 8002ffe: f003 0307 and.w r3, r3, #7
- 8003002: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
- /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
- /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8003004: 687b ldr r3, [r7, #4]
- 8003006: 685b ldr r3, [r3, #4]
- 8003008: 019a lsls r2, r3, #6
- 800300a: 693b ldr r3, [r7, #16]
- 800300c: 041b lsls r3, r3, #16
- 800300e: 431a orrs r2, r3
- 8003010: 687b ldr r3, [r7, #4]
- 8003012: 68db ldr r3, [r3, #12]
- 8003014: 061b lsls r3, r3, #24
- 8003016: 431a orrs r2, r3
- 8003018: 68fb ldr r3, [r7, #12]
- 800301a: 071b lsls r3, r3, #28
- 800301c: 493d ldr r1, [pc, #244] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800301e: 4313 orrs r3, r2
- 8003020: f8c1 3084 str.w r3, [r1, #132] ; 0x84
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8003024: 4b3b ldr r3, [pc, #236] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003026: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800302a: f023 021f bic.w r2, r3, #31
- 800302e: 687b ldr r3, [r7, #4]
- 8003030: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003032: 3b01 subs r3, #1
- 8003034: 4937 ldr r1, [pc, #220] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003036: 4313 orrs r3, r2
- 8003038: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 800303c: 687b ldr r3, [r7, #4]
- 800303e: 681b ldr r3, [r3, #0]
- 8003040: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8003044: 2b00 cmp r3, #0
- 8003046: d01d beq.n 8003084 <HAL_RCCEx_PeriphCLKConfig+0x638>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-
- /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8003048: 4b32 ldr r3, [pc, #200] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800304a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 800304e: 0e1b lsrs r3, r3, #24
- 8003050: f003 030f and.w r3, r3, #15
- 8003054: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8003056: 4b2f ldr r3, [pc, #188] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003058: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 800305c: 0f1b lsrs r3, r3, #28
- 800305e: f003 0307 and.w r3, r3, #7
- 8003062: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 8003064: 687b ldr r3, [r7, #4]
- 8003066: 685b ldr r3, [r3, #4]
- 8003068: 019a lsls r2, r3, #6
- 800306a: 687b ldr r3, [r7, #4]
- 800306c: 691b ldr r3, [r3, #16]
- 800306e: 041b lsls r3, r3, #16
- 8003070: 431a orrs r2, r3
- 8003072: 693b ldr r3, [r7, #16]
- 8003074: 061b lsls r3, r3, #24
- 8003076: 431a orrs r2, r3
- 8003078: 68fb ldr r3, [r7, #12]
- 800307a: 071b lsls r3, r3, #28
- 800307c: 4925 ldr r1, [pc, #148] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800307e: 4313 orrs r3, r2
- 8003080: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is just selected -----------------*/
- if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 8003084: 687b ldr r3, [r7, #4]
- 8003086: 681b ldr r3, [r3, #0]
- 8003088: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 800308c: 2b00 cmp r3, #0
- 800308e: d011 beq.n 80030b4 <HAL_RCCEx_PeriphCLKConfig+0x668>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
- /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 8003090: 687b ldr r3, [r7, #4]
- 8003092: 685b ldr r3, [r3, #4]
- 8003094: 019a lsls r2, r3, #6
- 8003096: 687b ldr r3, [r7, #4]
- 8003098: 691b ldr r3, [r3, #16]
- 800309a: 041b lsls r3, r3, #16
- 800309c: 431a orrs r2, r3
- 800309e: 687b ldr r3, [r7, #4]
- 80030a0: 68db ldr r3, [r3, #12]
- 80030a2: 061b lsls r3, r3, #24
- 80030a4: 431a orrs r2, r3
- 80030a6: 687b ldr r3, [r7, #4]
- 80030a8: 689b ldr r3, [r3, #8]
- 80030aa: 071b lsls r3, r3, #28
- 80030ac: 4919 ldr r1, [pc, #100] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030ae: 4313 orrs r3, r2
- 80030b0: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /* Enable the PLLI2S */
- __HAL_RCC_PLLI2S_ENABLE();
- 80030b4: 4b17 ldr r3, [pc, #92] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030b6: 681b ldr r3, [r3, #0]
- 80030b8: 4a16 ldr r2, [pc, #88] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030ba: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
- 80030be: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80030c0: f7fe fd68 bl 8001b94 <HAL_GetTick>
- 80030c4: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 80030c6: e008 b.n 80030da <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 80030c8: f7fe fd64 bl 8001b94 <HAL_GetTick>
- 80030cc: 4602 mov r2, r0
- 80030ce: 697b ldr r3, [r7, #20]
- 80030d0: 1ad3 subs r3, r2, r3
- 80030d2: 2b64 cmp r3, #100 ; 0x64
- 80030d4: d901 bls.n 80030da <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 80030d6: 2303 movs r3, #3
- 80030d8: e0d7 b.n 800328a <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 80030da: 4b0e ldr r3, [pc, #56] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030dc: 681b ldr r3, [r3, #0]
- 80030de: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 80030e2: 2b00 cmp r3, #0
- 80030e4: d0f0 beq.n 80030c8 <HAL_RCCEx_PeriphCLKConfig+0x67c>
- }
- }
-
- /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
- /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
- if(pllsaiused == 1)
- 80030e6: 69bb ldr r3, [r7, #24]
- 80030e8: 2b01 cmp r3, #1
- 80030ea: f040 80cd bne.w 8003288 <HAL_RCCEx_PeriphCLKConfig+0x83c>
- {
- /* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
- 80030ee: 4b09 ldr r3, [pc, #36] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030f0: 681b ldr r3, [r3, #0]
- 80030f2: 4a08 ldr r2, [pc, #32] ; (8003114 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030f4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 80030f8: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80030fa: f7fe fd4b bl 8001b94 <HAL_GetTick>
- 80030fe: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is disabled */
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8003100: e00a b.n 8003118 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8003102: f7fe fd47 bl 8001b94 <HAL_GetTick>
- 8003106: 4602 mov r2, r0
- 8003108: 697b ldr r3, [r7, #20]
- 800310a: 1ad3 subs r3, r2, r3
- 800310c: 2b64 cmp r3, #100 ; 0x64
- 800310e: d903 bls.n 8003118 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003110: 2303 movs r3, #3
- 8003112: e0ba b.n 800328a <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 8003114: 40023800 .word 0x40023800
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8003118: 4b5e ldr r3, [pc, #376] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800311a: 681b ldr r3, [r3, #0]
- 800311c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8003120: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8003124: d0ed beq.n 8003102 <HAL_RCCEx_PeriphCLKConfig+0x6b6>
-
- /* Check the PLLSAI division factors */
- assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
- /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8003126: 687b ldr r3, [r7, #4]
- 8003128: 681b ldr r3, [r3, #0]
- 800312a: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 800312e: 2b00 cmp r3, #0
- 8003130: d003 beq.n 800313a <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 8003132: 687b ldr r3, [r7, #4]
- 8003134: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8003136: 2b00 cmp r3, #0
- 8003138: d009 beq.n 800314e <HAL_RCCEx_PeriphCLKConfig+0x702>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 800313a: 687b ldr r3, [r7, #4]
- 800313c: 681b ldr r3, [r3, #0]
- 800313e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8003142: 2b00 cmp r3, #0
- 8003144: d02e beq.n 80031a4 <HAL_RCCEx_PeriphCLKConfig+0x758>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 8003146: 687b ldr r3, [r7, #4]
- 8003148: 6c1b ldr r3, [r3, #64] ; 0x40
- 800314a: 2b00 cmp r3, #0
- 800314c: d12a bne.n 80031a4 <HAL_RCCEx_PeriphCLKConfig+0x758>
- assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
- /* check for PLLSAI/DIVQ Parameter */
- assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
- /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 800314e: 4b51 ldr r3, [pc, #324] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003150: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003154: 0c1b lsrs r3, r3, #16
- 8003156: f003 0303 and.w r3, r3, #3
- 800315a: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 800315c: 4b4d ldr r3, [pc, #308] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800315e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003162: 0f1b lsrs r3, r3, #28
- 8003164: f003 0307 and.w r3, r3, #7
- 8003168: 60fb str r3, [r7, #12]
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 800316a: 687b ldr r3, [r7, #4]
- 800316c: 695b ldr r3, [r3, #20]
- 800316e: 019a lsls r2, r3, #6
- 8003170: 693b ldr r3, [r7, #16]
- 8003172: 041b lsls r3, r3, #16
- 8003174: 431a orrs r2, r3
- 8003176: 687b ldr r3, [r7, #4]
- 8003178: 699b ldr r3, [r3, #24]
- 800317a: 061b lsls r3, r3, #24
- 800317c: 431a orrs r2, r3
- 800317e: 68fb ldr r3, [r7, #12]
- 8003180: 071b lsls r3, r3, #28
- 8003182: 4944 ldr r1, [pc, #272] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003184: 4313 orrs r3, r2
- 8003186: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 800318a: 4b42 ldr r3, [pc, #264] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800318c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003190: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
- 8003194: 687b ldr r3, [r7, #4]
- 8003196: 6a9b ldr r3, [r3, #40] ; 0x28
- 8003198: 3b01 subs r3, #1
- 800319a: 021b lsls r3, r3, #8
- 800319c: 493d ldr r1, [pc, #244] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800319e: 4313 orrs r3, r2
- 80031a0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
- /* In Case of PLLI2S is selected as source clock for CK48 */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 80031a4: 687b ldr r3, [r7, #4]
- 80031a6: 681b ldr r3, [r3, #0]
- 80031a8: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 80031ac: 2b00 cmp r3, #0
- 80031ae: d022 beq.n 80031f6 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 80031b0: 687b ldr r3, [r7, #4]
- 80031b2: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80031b4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 80031b8: d11d bne.n 80031f6 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
- /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 80031ba: 4b36 ldr r3, [pc, #216] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80031bc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80031c0: 0e1b lsrs r3, r3, #24
- 80031c2: f003 030f and.w r3, r3, #15
- 80031c6: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 80031c8: 4b32 ldr r3, [pc, #200] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80031ca: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80031ce: 0f1b lsrs r3, r3, #28
- 80031d0: f003 0307 and.w r3, r3, #7
- 80031d4: 60fb str r3, [r7, #12]
-
- /* Configure the PLLSAI division factors */
- /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
- /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 80031d6: 687b ldr r3, [r7, #4]
- 80031d8: 695b ldr r3, [r3, #20]
- 80031da: 019a lsls r2, r3, #6
- 80031dc: 687b ldr r3, [r7, #4]
- 80031de: 6a1b ldr r3, [r3, #32]
- 80031e0: 041b lsls r3, r3, #16
- 80031e2: 431a orrs r2, r3
- 80031e4: 693b ldr r3, [r7, #16]
- 80031e6: 061b lsls r3, r3, #24
- 80031e8: 431a orrs r2, r3
- 80031ea: 68fb ldr r3, [r7, #12]
- 80031ec: 071b lsls r3, r3, #28
- 80031ee: 4929 ldr r1, [pc, #164] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80031f0: 4313 orrs r3, r2
- 80031f2: f8c1 3088 str.w r3, [r1, #136] ; 0x88
- }
-
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- /*---------------------------- LTDC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 80031f6: 687b ldr r3, [r7, #4]
- 80031f8: 681b ldr r3, [r3, #0]
- 80031fa: f003 0308 and.w r3, r3, #8
- 80031fe: 2b00 cmp r3, #0
- 8003200: d028 beq.n 8003254 <HAL_RCCEx_PeriphCLKConfig+0x808>
- {
- assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
- assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
- /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 8003202: 4b24 ldr r3, [pc, #144] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003204: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003208: 0e1b lsrs r3, r3, #24
- 800320a: f003 030f and.w r3, r3, #15
- 800320e: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8003210: 4b20 ldr r3, [pc, #128] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003212: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003216: 0c1b lsrs r3, r3, #16
- 8003218: f003 0303 and.w r3, r3, #3
- 800321c: 60fb str r3, [r7, #12]
-
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 800321e: 687b ldr r3, [r7, #4]
- 8003220: 695b ldr r3, [r3, #20]
- 8003222: 019a lsls r2, r3, #6
- 8003224: 68fb ldr r3, [r7, #12]
- 8003226: 041b lsls r3, r3, #16
- 8003228: 431a orrs r2, r3
- 800322a: 693b ldr r3, [r7, #16]
- 800322c: 061b lsls r3, r3, #24
- 800322e: 431a orrs r2, r3
- 8003230: 687b ldr r3, [r7, #4]
- 8003232: 69db ldr r3, [r3, #28]
- 8003234: 071b lsls r3, r3, #28
- 8003236: 4917 ldr r1, [pc, #92] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003238: 4313 orrs r3, r2
- 800323a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 800323e: 4b15 ldr r3, [pc, #84] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003240: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003244: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8003248: 687b ldr r3, [r7, #4]
- 800324a: 6adb ldr r3, [r3, #44] ; 0x2c
- 800324c: 4911 ldr r1, [pc, #68] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800324e: 4313 orrs r3, r2
- 8003250: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /* Enable PLLSAI Clock */
- __HAL_RCC_PLLSAI_ENABLE();
- 8003254: 4b0f ldr r3, [pc, #60] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003256: 681b ldr r3, [r3, #0]
- 8003258: 4a0e ldr r2, [pc, #56] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800325a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 800325e: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8003260: f7fe fc98 bl 8001b94 <HAL_GetTick>
- 8003264: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is ready */
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 8003266: e008 b.n 800327a <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8003268: f7fe fc94 bl 8001b94 <HAL_GetTick>
- 800326c: 4602 mov r2, r0
- 800326e: 697b ldr r3, [r7, #20]
- 8003270: 1ad3 subs r3, r2, r3
- 8003272: 2b64 cmp r3, #100 ; 0x64
- 8003274: d901 bls.n 800327a <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003276: 2303 movs r3, #3
- 8003278: e007 b.n 800328a <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 800327a: 4b06 ldr r3, [pc, #24] ; (8003294 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800327c: 681b ldr r3, [r3, #0]
- 800327e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8003282: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8003286: d1ef bne.n 8003268 <HAL_RCCEx_PeriphCLKConfig+0x81c>
- }
- }
- }
- return HAL_OK;
- 8003288: 2300 movs r3, #0
-}
- 800328a: 4618 mov r0, r3
- 800328c: 3720 adds r7, #32
- 800328e: 46bd mov sp, r7
- 8003290: bd80 pop {r7, pc}
- 8003292: bf00 nop
- 8003294: 40023800 .word 0x40023800
-
-08003298 <HAL_TIM_Base_Init>:
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- 8003298: b580 push {r7, lr}
- 800329a: b082 sub sp, #8
- 800329c: af00 add r7, sp, #0
- 800329e: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 80032a0: 687b ldr r3, [r7, #4]
- 80032a2: 2b00 cmp r3, #0
- 80032a4: d101 bne.n 80032aa <HAL_TIM_Base_Init+0x12>
- {
- return HAL_ERROR;
- 80032a6: 2301 movs r3, #1
- 80032a8: e01d b.n 80032e6 <HAL_TIM_Base_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 80032aa: 687b ldr r3, [r7, #4]
- 80032ac: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 80032b0: b2db uxtb r3, r3
- 80032b2: 2b00 cmp r3, #0
- 80032b4: d106 bne.n 80032c4 <HAL_TIM_Base_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 80032b6: 687b ldr r3, [r7, #4]
- 80032b8: 2200 movs r2, #0
- 80032ba: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- 80032be: 6878 ldr r0, [r7, #4]
- 80032c0: f7fe faa0 bl 8001804 <HAL_TIM_Base_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80032c4: 687b ldr r3, [r7, #4]
- 80032c6: 2202 movs r2, #2
- 80032c8: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80032cc: 687b ldr r3, [r7, #4]
- 80032ce: 681a ldr r2, [r3, #0]
- 80032d0: 687b ldr r3, [r7, #4]
- 80032d2: 3304 adds r3, #4
- 80032d4: 4619 mov r1, r3
- 80032d6: 4610 mov r0, r2
- 80032d8: f000 fc90 bl 8003bfc <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 80032dc: 687b ldr r3, [r7, #4]
- 80032de: 2201 movs r2, #1
- 80032e0: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 80032e4: 2300 movs r3, #0
-}
- 80032e6: 4618 mov r0, r3
- 80032e8: 3708 adds r7, #8
- 80032ea: 46bd mov sp, r7
- 80032ec: bd80 pop {r7, pc}
- ...
-
-080032f0 <HAL_TIM_Base_Start_IT>:
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- 80032f0: b480 push {r7}
- 80032f2: b085 sub sp, #20
- 80032f4: af00 add r7, sp, #0
- 80032f6: 6078 str r0, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- 80032f8: 687b ldr r3, [r7, #4]
- 80032fa: 681b ldr r3, [r3, #0]
- 80032fc: 68da ldr r2, [r3, #12]
- 80032fe: 687b ldr r3, [r7, #4]
- 8003300: 681b ldr r3, [r3, #0]
- 8003302: f042 0201 orr.w r2, r2, #1
- 8003306: 60da str r2, [r3, #12]
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 8003308: 687b ldr r3, [r7, #4]
- 800330a: 681b ldr r3, [r3, #0]
- 800330c: 689a ldr r2, [r3, #8]
- 800330e: 4b0c ldr r3, [pc, #48] ; (8003340 <HAL_TIM_Base_Start_IT+0x50>)
- 8003310: 4013 ands r3, r2
- 8003312: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8003314: 68fb ldr r3, [r7, #12]
- 8003316: 2b06 cmp r3, #6
- 8003318: d00b beq.n 8003332 <HAL_TIM_Base_Start_IT+0x42>
- 800331a: 68fb ldr r3, [r7, #12]
- 800331c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8003320: d007 beq.n 8003332 <HAL_TIM_Base_Start_IT+0x42>
- {
- __HAL_TIM_ENABLE(htim);
- 8003322: 687b ldr r3, [r7, #4]
- 8003324: 681b ldr r3, [r3, #0]
- 8003326: 681a ldr r2, [r3, #0]
- 8003328: 687b ldr r3, [r7, #4]
- 800332a: 681b ldr r3, [r3, #0]
- 800332c: f042 0201 orr.w r2, r2, #1
- 8003330: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 8003332: 2300 movs r3, #0
-}
- 8003334: 4618 mov r0, r3
- 8003336: 3714 adds r7, #20
- 8003338: 46bd mov sp, r7
- 800333a: f85d 7b04 ldr.w r7, [sp], #4
- 800333e: 4770 bx lr
- 8003340: 00010007 .word 0x00010007
-
-08003344 <HAL_TIM_PWM_Init>:
- * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- 8003344: b580 push {r7, lr}
- 8003346: b082 sub sp, #8
- 8003348: af00 add r7, sp, #0
- 800334a: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 800334c: 687b ldr r3, [r7, #4]
- 800334e: 2b00 cmp r3, #0
- 8003350: d101 bne.n 8003356 <HAL_TIM_PWM_Init+0x12>
- {
- return HAL_ERROR;
- 8003352: 2301 movs r3, #1
- 8003354: e01d b.n 8003392 <HAL_TIM_PWM_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 8003356: 687b ldr r3, [r7, #4]
- 8003358: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 800335c: b2db uxtb r3, r3
- 800335e: 2b00 cmp r3, #0
- 8003360: d106 bne.n 8003370 <HAL_TIM_PWM_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 8003362: 687b ldr r3, [r7, #4]
- 8003364: 2200 movs r2, #0
- 8003366: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->PWM_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
- 800336a: 6878 ldr r0, [r7, #4]
- 800336c: f000 f815 bl 800339a <HAL_TIM_PWM_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 8003370: 687b ldr r3, [r7, #4]
- 8003372: 2202 movs r2, #2
- 8003374: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003378: 687b ldr r3, [r7, #4]
- 800337a: 681a ldr r2, [r3, #0]
- 800337c: 687b ldr r3, [r7, #4]
- 800337e: 3304 adds r3, #4
- 8003380: 4619 mov r1, r3
- 8003382: 4610 mov r0, r2
- 8003384: f000 fc3a bl 8003bfc <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 8003388: 687b ldr r3, [r7, #4]
- 800338a: 2201 movs r2, #1
- 800338c: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 8003390: 2300 movs r3, #0
-}
- 8003392: 4618 mov r0, r3
- 8003394: 3708 adds r7, #8
- 8003396: 46bd mov sp, r7
- 8003398: bd80 pop {r7, pc}
-
-0800339a <HAL_TIM_PWM_MspInit>:
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- 800339a: b480 push {r7}
- 800339c: b083 sub sp, #12
- 800339e: af00 add r7, sp, #0
- 80033a0: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
- 80033a2: bf00 nop
- 80033a4: 370c adds r7, #12
- 80033a6: 46bd mov sp, r7
- 80033a8: f85d 7b04 ldr.w r7, [sp], #4
- 80033ac: 4770 bx lr
- ...
-
-080033b0 <HAL_TIM_PWM_Start>:
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 80033b0: b580 push {r7, lr}
- 80033b2: b084 sub sp, #16
- 80033b4: af00 add r7, sp, #0
- 80033b6: 6078 str r0, [r7, #4]
- 80033b8: 6039 str r1, [r7, #0]
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- 80033ba: 687b ldr r3, [r7, #4]
- 80033bc: 681b ldr r3, [r3, #0]
- 80033be: 2201 movs r2, #1
- 80033c0: 6839 ldr r1, [r7, #0]
- 80033c2: 4618 mov r0, r3
- 80033c4: f000 ffb2 bl 800432c <TIM_CCxChannelCmd>
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- 80033c8: 687b ldr r3, [r7, #4]
- 80033ca: 681b ldr r3, [r3, #0]
- 80033cc: 4a17 ldr r2, [pc, #92] ; (800342c <HAL_TIM_PWM_Start+0x7c>)
- 80033ce: 4293 cmp r3, r2
- 80033d0: d004 beq.n 80033dc <HAL_TIM_PWM_Start+0x2c>
- 80033d2: 687b ldr r3, [r7, #4]
- 80033d4: 681b ldr r3, [r3, #0]
- 80033d6: 4a16 ldr r2, [pc, #88] ; (8003430 <HAL_TIM_PWM_Start+0x80>)
- 80033d8: 4293 cmp r3, r2
- 80033da: d101 bne.n 80033e0 <HAL_TIM_PWM_Start+0x30>
- 80033dc: 2301 movs r3, #1
- 80033de: e000 b.n 80033e2 <HAL_TIM_PWM_Start+0x32>
- 80033e0: 2300 movs r3, #0
- 80033e2: 2b00 cmp r3, #0
- 80033e4: d007 beq.n 80033f6 <HAL_TIM_PWM_Start+0x46>
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- 80033e6: 687b ldr r3, [r7, #4]
- 80033e8: 681b ldr r3, [r3, #0]
- 80033ea: 6c5a ldr r2, [r3, #68] ; 0x44
- 80033ec: 687b ldr r3, [r7, #4]
- 80033ee: 681b ldr r3, [r3, #0]
- 80033f0: f442 4200 orr.w r2, r2, #32768 ; 0x8000
- 80033f4: 645a str r2, [r3, #68] ; 0x44
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 80033f6: 687b ldr r3, [r7, #4]
- 80033f8: 681b ldr r3, [r3, #0]
- 80033fa: 689a ldr r2, [r3, #8]
- 80033fc: 4b0d ldr r3, [pc, #52] ; (8003434 <HAL_TIM_PWM_Start+0x84>)
- 80033fe: 4013 ands r3, r2
- 8003400: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8003402: 68fb ldr r3, [r7, #12]
- 8003404: 2b06 cmp r3, #6
- 8003406: d00b beq.n 8003420 <HAL_TIM_PWM_Start+0x70>
- 8003408: 68fb ldr r3, [r7, #12]
- 800340a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800340e: d007 beq.n 8003420 <HAL_TIM_PWM_Start+0x70>
- {
- __HAL_TIM_ENABLE(htim);
- 8003410: 687b ldr r3, [r7, #4]
- 8003412: 681b ldr r3, [r3, #0]
- 8003414: 681a ldr r2, [r3, #0]
- 8003416: 687b ldr r3, [r7, #4]
- 8003418: 681b ldr r3, [r3, #0]
- 800341a: f042 0201 orr.w r2, r2, #1
- 800341e: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 8003420: 2300 movs r3, #0
-}
- 8003422: 4618 mov r0, r3
- 8003424: 3710 adds r7, #16
- 8003426: 46bd mov sp, r7
- 8003428: bd80 pop {r7, pc}
- 800342a: bf00 nop
- 800342c: 40010000 .word 0x40010000
- 8003430: 40010400 .word 0x40010400
- 8003434: 00010007 .word 0x00010007
-
-08003438 <HAL_TIM_Encoder_Init>:
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
-{
- 8003438: b580 push {r7, lr}
- 800343a: b086 sub sp, #24
- 800343c: af00 add r7, sp, #0
- 800343e: 6078 str r0, [r7, #4]
- 8003440: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 8003442: 687b ldr r3, [r7, #4]
- 8003444: 2b00 cmp r3, #0
- 8003446: d101 bne.n 800344c <HAL_TIM_Encoder_Init+0x14>
- {
- return HAL_ERROR;
- 8003448: 2301 movs r3, #1
- 800344a: e07b b.n 8003544 <HAL_TIM_Encoder_Init+0x10c>
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 800344c: 687b ldr r3, [r7, #4]
- 800344e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8003452: b2db uxtb r3, r3
- 8003454: 2b00 cmp r3, #0
- 8003456: d106 bne.n 8003466 <HAL_TIM_Encoder_Init+0x2e>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 8003458: 687b ldr r3, [r7, #4]
- 800345a: 2200 movs r2, #0
- 800345c: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Encoder_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
- 8003460: 6878 ldr r0, [r7, #4]
- 8003462: f7fe f93f bl 80016e4 <HAL_TIM_Encoder_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 8003466: 687b ldr r3, [r7, #4]
- 8003468: 2202 movs r2, #2
- 800346a: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Reset the SMS and ECE bits */
- htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
- 800346e: 687b ldr r3, [r7, #4]
- 8003470: 681b ldr r3, [r3, #0]
- 8003472: 6899 ldr r1, [r3, #8]
- 8003474: 687b ldr r3, [r7, #4]
- 8003476: 681a ldr r2, [r3, #0]
- 8003478: 4b34 ldr r3, [pc, #208] ; (800354c <HAL_TIM_Encoder_Init+0x114>)
- 800347a: 400b ands r3, r1
- 800347c: 6093 str r3, [r2, #8]
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 800347e: 687b ldr r3, [r7, #4]
- 8003480: 681a ldr r2, [r3, #0]
- 8003482: 687b ldr r3, [r7, #4]
- 8003484: 3304 adds r3, #4
- 8003486: 4619 mov r1, r3
- 8003488: 4610 mov r0, r2
- 800348a: f000 fbb7 bl 8003bfc <TIM_Base_SetConfig>
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 800348e: 687b ldr r3, [r7, #4]
- 8003490: 681b ldr r3, [r3, #0]
- 8003492: 689b ldr r3, [r3, #8]
- 8003494: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
- 8003496: 687b ldr r3, [r7, #4]
- 8003498: 681b ldr r3, [r3, #0]
- 800349a: 699b ldr r3, [r3, #24]
- 800349c: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
- 800349e: 687b ldr r3, [r7, #4]
- 80034a0: 681b ldr r3, [r3, #0]
- 80034a2: 6a1b ldr r3, [r3, #32]
- 80034a4: 60fb str r3, [r7, #12]
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
- 80034a6: 683b ldr r3, [r7, #0]
- 80034a8: 681b ldr r3, [r3, #0]
- 80034aa: 697a ldr r2, [r7, #20]
- 80034ac: 4313 orrs r3, r2
- 80034ae: 617b str r3, [r7, #20]
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- 80034b0: 693a ldr r2, [r7, #16]
- 80034b2: 4b27 ldr r3, [pc, #156] ; (8003550 <HAL_TIM_Encoder_Init+0x118>)
- 80034b4: 4013 ands r3, r2
- 80034b6: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- 80034b8: 683b ldr r3, [r7, #0]
- 80034ba: 689a ldr r2, [r3, #8]
- 80034bc: 683b ldr r3, [r7, #0]
- 80034be: 699b ldr r3, [r3, #24]
- 80034c0: 021b lsls r3, r3, #8
- 80034c2: 4313 orrs r3, r2
- 80034c4: 693a ldr r2, [r7, #16]
- 80034c6: 4313 orrs r3, r2
- 80034c8: 613b str r3, [r7, #16]
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- 80034ca: 693a ldr r2, [r7, #16]
- 80034cc: 4b21 ldr r3, [pc, #132] ; (8003554 <HAL_TIM_Encoder_Init+0x11c>)
- 80034ce: 4013 ands r3, r2
- 80034d0: 613b str r3, [r7, #16]
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- 80034d2: 693a ldr r2, [r7, #16]
- 80034d4: 4b20 ldr r3, [pc, #128] ; (8003558 <HAL_TIM_Encoder_Init+0x120>)
- 80034d6: 4013 ands r3, r2
- 80034d8: 613b str r3, [r7, #16]
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- 80034da: 683b ldr r3, [r7, #0]
- 80034dc: 68da ldr r2, [r3, #12]
- 80034de: 683b ldr r3, [r7, #0]
- 80034e0: 69db ldr r3, [r3, #28]
- 80034e2: 021b lsls r3, r3, #8
- 80034e4: 4313 orrs r3, r2
- 80034e6: 693a ldr r2, [r7, #16]
- 80034e8: 4313 orrs r3, r2
- 80034ea: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
- 80034ec: 683b ldr r3, [r7, #0]
- 80034ee: 691b ldr r3, [r3, #16]
- 80034f0: 011a lsls r2, r3, #4
- 80034f2: 683b ldr r3, [r7, #0]
- 80034f4: 6a1b ldr r3, [r3, #32]
- 80034f6: 031b lsls r3, r3, #12
- 80034f8: 4313 orrs r3, r2
- 80034fa: 693a ldr r2, [r7, #16]
- 80034fc: 4313 orrs r3, r2
- 80034fe: 613b str r3, [r7, #16]
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- 8003500: 68fb ldr r3, [r7, #12]
- 8003502: f023 0322 bic.w r3, r3, #34 ; 0x22
- 8003506: 60fb str r3, [r7, #12]
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- 8003508: 68fb ldr r3, [r7, #12]
- 800350a: f023 0388 bic.w r3, r3, #136 ; 0x88
- 800350e: 60fb str r3, [r7, #12]
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
- 8003510: 683b ldr r3, [r7, #0]
- 8003512: 685a ldr r2, [r3, #4]
- 8003514: 683b ldr r3, [r7, #0]
- 8003516: 695b ldr r3, [r3, #20]
- 8003518: 011b lsls r3, r3, #4
- 800351a: 4313 orrs r3, r2
- 800351c: 68fa ldr r2, [r7, #12]
- 800351e: 4313 orrs r3, r2
- 8003520: 60fb str r3, [r7, #12]
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 8003522: 687b ldr r3, [r7, #4]
- 8003524: 681b ldr r3, [r3, #0]
- 8003526: 697a ldr r2, [r7, #20]
- 8003528: 609a str r2, [r3, #8]
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
- 800352a: 687b ldr r3, [r7, #4]
- 800352c: 681b ldr r3, [r3, #0]
- 800352e: 693a ldr r2, [r7, #16]
- 8003530: 619a str r2, [r3, #24]
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
- 8003532: 687b ldr r3, [r7, #4]
- 8003534: 681b ldr r3, [r3, #0]
- 8003536: 68fa ldr r2, [r7, #12]
- 8003538: 621a str r2, [r3, #32]
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 800353a: 687b ldr r3, [r7, #4]
- 800353c: 2201 movs r2, #1
- 800353e: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 8003542: 2300 movs r3, #0
-}
- 8003544: 4618 mov r0, r3
- 8003546: 3718 adds r7, #24
- 8003548: 46bd mov sp, r7
- 800354a: bd80 pop {r7, pc}
- 800354c: fffebff8 .word 0xfffebff8
- 8003550: fffffcfc .word 0xfffffcfc
- 8003554: fffff3f3 .word 0xfffff3f3
- 8003558: ffff0f0f .word 0xffff0f0f
-
-0800355c <HAL_TIM_Encoder_Start>:
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 800355c: b580 push {r7, lr}
- 800355e: b082 sub sp, #8
- 8003560: af00 add r7, sp, #0
- 8003562: 6078 str r0, [r7, #4]
- 8003564: 6039 str r1, [r7, #0]
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- switch (Channel)
- 8003566: 683b ldr r3, [r7, #0]
- 8003568: 2b00 cmp r3, #0
- 800356a: d002 beq.n 8003572 <HAL_TIM_Encoder_Start+0x16>
- 800356c: 2b04 cmp r3, #4
- 800356e: d008 beq.n 8003582 <HAL_TIM_Encoder_Start+0x26>
- 8003570: e00f b.n 8003592 <HAL_TIM_Encoder_Start+0x36>
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 8003572: 687b ldr r3, [r7, #4]
- 8003574: 681b ldr r3, [r3, #0]
- 8003576: 2201 movs r2, #1
- 8003578: 2100 movs r1, #0
- 800357a: 4618 mov r0, r3
- 800357c: f000 fed6 bl 800432c <TIM_CCxChannelCmd>
- break;
- 8003580: e016 b.n 80035b0 <HAL_TIM_Encoder_Start+0x54>
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 8003582: 687b ldr r3, [r7, #4]
- 8003584: 681b ldr r3, [r3, #0]
- 8003586: 2201 movs r2, #1
- 8003588: 2104 movs r1, #4
- 800358a: 4618 mov r0, r3
- 800358c: f000 fece bl 800432c <TIM_CCxChannelCmd>
- break;
- 8003590: e00e b.n 80035b0 <HAL_TIM_Encoder_Start+0x54>
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 8003592: 687b ldr r3, [r7, #4]
- 8003594: 681b ldr r3, [r3, #0]
- 8003596: 2201 movs r2, #1
- 8003598: 2100 movs r1, #0
- 800359a: 4618 mov r0, r3
- 800359c: f000 fec6 bl 800432c <TIM_CCxChannelCmd>
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 80035a0: 687b ldr r3, [r7, #4]
- 80035a2: 681b ldr r3, [r3, #0]
- 80035a4: 2201 movs r2, #1
- 80035a6: 2104 movs r1, #4
- 80035a8: 4618 mov r0, r3
- 80035aa: f000 febf bl 800432c <TIM_CCxChannelCmd>
- break;
- 80035ae: bf00 nop
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
- 80035b0: 687b ldr r3, [r7, #4]
- 80035b2: 681b ldr r3, [r3, #0]
- 80035b4: 681a ldr r2, [r3, #0]
- 80035b6: 687b ldr r3, [r7, #4]
- 80035b8: 681b ldr r3, [r3, #0]
- 80035ba: f042 0201 orr.w r2, r2, #1
- 80035be: 601a str r2, [r3, #0]
-
- /* Return function status */
- return HAL_OK;
- 80035c0: 2300 movs r3, #0
-}
- 80035c2: 4618 mov r0, r3
- 80035c4: 3708 adds r7, #8
- 80035c6: 46bd mov sp, r7
- 80035c8: bd80 pop {r7, pc}
-
-080035ca <HAL_TIM_IRQHandler>:
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- 80035ca: b580 push {r7, lr}
- 80035cc: b082 sub sp, #8
- 80035ce: af00 add r7, sp, #0
- 80035d0: 6078 str r0, [r7, #4]
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- 80035d2: 687b ldr r3, [r7, #4]
- 80035d4: 681b ldr r3, [r3, #0]
- 80035d6: 691b ldr r3, [r3, #16]
- 80035d8: f003 0302 and.w r3, r3, #2
- 80035dc: 2b02 cmp r3, #2
- 80035de: d122 bne.n 8003626 <HAL_TIM_IRQHandler+0x5c>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- 80035e0: 687b ldr r3, [r7, #4]
- 80035e2: 681b ldr r3, [r3, #0]
- 80035e4: 68db ldr r3, [r3, #12]
- 80035e6: f003 0302 and.w r3, r3, #2
- 80035ea: 2b02 cmp r3, #2
- 80035ec: d11b bne.n 8003626 <HAL_TIM_IRQHandler+0x5c>
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- 80035ee: 687b ldr r3, [r7, #4]
- 80035f0: 681b ldr r3, [r3, #0]
- 80035f2: f06f 0202 mvn.w r2, #2
- 80035f6: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- 80035f8: 687b ldr r3, [r7, #4]
- 80035fa: 2201 movs r2, #1
- 80035fc: 771a strb r2, [r3, #28]
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- 80035fe: 687b ldr r3, [r7, #4]
- 8003600: 681b ldr r3, [r3, #0]
- 8003602: 699b ldr r3, [r3, #24]
- 8003604: f003 0303 and.w r3, r3, #3
- 8003608: 2b00 cmp r3, #0
- 800360a: d003 beq.n 8003614 <HAL_TIM_IRQHandler+0x4a>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 800360c: 6878 ldr r0, [r7, #4]
- 800360e: f000 fad7 bl 8003bc0 <HAL_TIM_IC_CaptureCallback>
- 8003612: e005 b.n 8003620 <HAL_TIM_IRQHandler+0x56>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003614: 6878 ldr r0, [r7, #4]
- 8003616: f000 fac9 bl 8003bac <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 800361a: 6878 ldr r0, [r7, #4]
- 800361c: f000 fada bl 8003bd4 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003620: 687b ldr r3, [r7, #4]
- 8003622: 2200 movs r2, #0
- 8003624: 771a strb r2, [r3, #28]
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- 8003626: 687b ldr r3, [r7, #4]
- 8003628: 681b ldr r3, [r3, #0]
- 800362a: 691b ldr r3, [r3, #16]
- 800362c: f003 0304 and.w r3, r3, #4
- 8003630: 2b04 cmp r3, #4
- 8003632: d122 bne.n 800367a <HAL_TIM_IRQHandler+0xb0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- 8003634: 687b ldr r3, [r7, #4]
- 8003636: 681b ldr r3, [r3, #0]
- 8003638: 68db ldr r3, [r3, #12]
- 800363a: f003 0304 and.w r3, r3, #4
- 800363e: 2b04 cmp r3, #4
- 8003640: d11b bne.n 800367a <HAL_TIM_IRQHandler+0xb0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- 8003642: 687b ldr r3, [r7, #4]
- 8003644: 681b ldr r3, [r3, #0]
- 8003646: f06f 0204 mvn.w r2, #4
- 800364a: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- 800364c: 687b ldr r3, [r7, #4]
- 800364e: 2202 movs r2, #2
- 8003650: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- 8003652: 687b ldr r3, [r7, #4]
- 8003654: 681b ldr r3, [r3, #0]
- 8003656: 699b ldr r3, [r3, #24]
- 8003658: f403 7340 and.w r3, r3, #768 ; 0x300
- 800365c: 2b00 cmp r3, #0
- 800365e: d003 beq.n 8003668 <HAL_TIM_IRQHandler+0x9e>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003660: 6878 ldr r0, [r7, #4]
- 8003662: f000 faad bl 8003bc0 <HAL_TIM_IC_CaptureCallback>
- 8003666: e005 b.n 8003674 <HAL_TIM_IRQHandler+0xaa>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003668: 6878 ldr r0, [r7, #4]
- 800366a: f000 fa9f bl 8003bac <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 800366e: 6878 ldr r0, [r7, #4]
- 8003670: f000 fab0 bl 8003bd4 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003674: 687b ldr r3, [r7, #4]
- 8003676: 2200 movs r2, #0
- 8003678: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- 800367a: 687b ldr r3, [r7, #4]
- 800367c: 681b ldr r3, [r3, #0]
- 800367e: 691b ldr r3, [r3, #16]
- 8003680: f003 0308 and.w r3, r3, #8
- 8003684: 2b08 cmp r3, #8
- 8003686: d122 bne.n 80036ce <HAL_TIM_IRQHandler+0x104>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- 8003688: 687b ldr r3, [r7, #4]
- 800368a: 681b ldr r3, [r3, #0]
- 800368c: 68db ldr r3, [r3, #12]
- 800368e: f003 0308 and.w r3, r3, #8
- 8003692: 2b08 cmp r3, #8
- 8003694: d11b bne.n 80036ce <HAL_TIM_IRQHandler+0x104>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- 8003696: 687b ldr r3, [r7, #4]
- 8003698: 681b ldr r3, [r3, #0]
- 800369a: f06f 0208 mvn.w r2, #8
- 800369e: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- 80036a0: 687b ldr r3, [r7, #4]
- 80036a2: 2204 movs r2, #4
- 80036a4: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- 80036a6: 687b ldr r3, [r7, #4]
- 80036a8: 681b ldr r3, [r3, #0]
- 80036aa: 69db ldr r3, [r3, #28]
- 80036ac: f003 0303 and.w r3, r3, #3
- 80036b0: 2b00 cmp r3, #0
- 80036b2: d003 beq.n 80036bc <HAL_TIM_IRQHandler+0xf2>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 80036b4: 6878 ldr r0, [r7, #4]
- 80036b6: f000 fa83 bl 8003bc0 <HAL_TIM_IC_CaptureCallback>
- 80036ba: e005 b.n 80036c8 <HAL_TIM_IRQHandler+0xfe>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 80036bc: 6878 ldr r0, [r7, #4]
- 80036be: f000 fa75 bl 8003bac <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80036c2: 6878 ldr r0, [r7, #4]
- 80036c4: f000 fa86 bl 8003bd4 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80036c8: 687b ldr r3, [r7, #4]
- 80036ca: 2200 movs r2, #0
- 80036cc: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- 80036ce: 687b ldr r3, [r7, #4]
- 80036d0: 681b ldr r3, [r3, #0]
- 80036d2: 691b ldr r3, [r3, #16]
- 80036d4: f003 0310 and.w r3, r3, #16
- 80036d8: 2b10 cmp r3, #16
- 80036da: d122 bne.n 8003722 <HAL_TIM_IRQHandler+0x158>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- 80036dc: 687b ldr r3, [r7, #4]
- 80036de: 681b ldr r3, [r3, #0]
- 80036e0: 68db ldr r3, [r3, #12]
- 80036e2: f003 0310 and.w r3, r3, #16
- 80036e6: 2b10 cmp r3, #16
- 80036e8: d11b bne.n 8003722 <HAL_TIM_IRQHandler+0x158>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- 80036ea: 687b ldr r3, [r7, #4]
- 80036ec: 681b ldr r3, [r3, #0]
- 80036ee: f06f 0210 mvn.w r2, #16
- 80036f2: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- 80036f4: 687b ldr r3, [r7, #4]
- 80036f6: 2208 movs r2, #8
- 80036f8: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- 80036fa: 687b ldr r3, [r7, #4]
- 80036fc: 681b ldr r3, [r3, #0]
- 80036fe: 69db ldr r3, [r3, #28]
- 8003700: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003704: 2b00 cmp r3, #0
- 8003706: d003 beq.n 8003710 <HAL_TIM_IRQHandler+0x146>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003708: 6878 ldr r0, [r7, #4]
- 800370a: f000 fa59 bl 8003bc0 <HAL_TIM_IC_CaptureCallback>
- 800370e: e005 b.n 800371c <HAL_TIM_IRQHandler+0x152>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003710: 6878 ldr r0, [r7, #4]
- 8003712: f000 fa4b bl 8003bac <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8003716: 6878 ldr r0, [r7, #4]
- 8003718: f000 fa5c bl 8003bd4 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 800371c: 687b ldr r3, [r7, #4]
- 800371e: 2200 movs r2, #0
- 8003720: 771a strb r2, [r3, #28]
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- 8003722: 687b ldr r3, [r7, #4]
- 8003724: 681b ldr r3, [r3, #0]
- 8003726: 691b ldr r3, [r3, #16]
- 8003728: f003 0301 and.w r3, r3, #1
- 800372c: 2b01 cmp r3, #1
- 800372e: d10e bne.n 800374e <HAL_TIM_IRQHandler+0x184>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- 8003730: 687b ldr r3, [r7, #4]
- 8003732: 681b ldr r3, [r3, #0]
- 8003734: 68db ldr r3, [r3, #12]
- 8003736: f003 0301 and.w r3, r3, #1
- 800373a: 2b01 cmp r3, #1
- 800373c: d107 bne.n 800374e <HAL_TIM_IRQHandler+0x184>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- 800373e: 687b ldr r3, [r7, #4]
- 8003740: 681b ldr r3, [r3, #0]
- 8003742: f06f 0201 mvn.w r2, #1
- 8003746: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
- 8003748: 6878 ldr r0, [r7, #4]
- 800374a: f7fd fe2b bl 80013a4 <HAL_TIM_PeriodElapsedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- 800374e: 687b ldr r3, [r7, #4]
- 8003750: 681b ldr r3, [r3, #0]
- 8003752: 691b ldr r3, [r3, #16]
- 8003754: f003 0380 and.w r3, r3, #128 ; 0x80
- 8003758: 2b80 cmp r3, #128 ; 0x80
- 800375a: d10e bne.n 800377a <HAL_TIM_IRQHandler+0x1b0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 800375c: 687b ldr r3, [r7, #4]
- 800375e: 681b ldr r3, [r3, #0]
- 8003760: 68db ldr r3, [r3, #12]
- 8003762: f003 0380 and.w r3, r3, #128 ; 0x80
- 8003766: 2b80 cmp r3, #128 ; 0x80
- 8003768: d107 bne.n 800377a <HAL_TIM_IRQHandler+0x1b0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- 800376a: 687b ldr r3, [r7, #4]
- 800376c: 681b ldr r3, [r3, #0]
- 800376e: f06f 0280 mvn.w r2, #128 ; 0x80
- 8003772: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
- 8003774: 6878 ldr r0, [r7, #4]
- 8003776: f000 fe65 bl 8004444 <HAL_TIMEx_BreakCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- 800377a: 687b ldr r3, [r7, #4]
- 800377c: 681b ldr r3, [r3, #0]
- 800377e: 691b ldr r3, [r3, #16]
- 8003780: f403 7380 and.w r3, r3, #256 ; 0x100
- 8003784: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8003788: d10e bne.n 80037a8 <HAL_TIM_IRQHandler+0x1de>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 800378a: 687b ldr r3, [r7, #4]
- 800378c: 681b ldr r3, [r3, #0]
- 800378e: 68db ldr r3, [r3, #12]
- 8003790: f003 0380 and.w r3, r3, #128 ; 0x80
- 8003794: 2b80 cmp r3, #128 ; 0x80
- 8003796: d107 bne.n 80037a8 <HAL_TIM_IRQHandler+0x1de>
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- 8003798: 687b ldr r3, [r7, #4]
- 800379a: 681b ldr r3, [r3, #0]
- 800379c: f46f 7280 mvn.w r2, #256 ; 0x100
- 80037a0: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->Break2Callback(htim);
-#else
- HAL_TIMEx_Break2Callback(htim);
- 80037a2: 6878 ldr r0, [r7, #4]
- 80037a4: f000 fe58 bl 8004458 <HAL_TIMEx_Break2Callback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- 80037a8: 687b ldr r3, [r7, #4]
- 80037aa: 681b ldr r3, [r3, #0]
- 80037ac: 691b ldr r3, [r3, #16]
- 80037ae: f003 0340 and.w r3, r3, #64 ; 0x40
- 80037b2: 2b40 cmp r3, #64 ; 0x40
- 80037b4: d10e bne.n 80037d4 <HAL_TIM_IRQHandler+0x20a>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- 80037b6: 687b ldr r3, [r7, #4]
- 80037b8: 681b ldr r3, [r3, #0]
- 80037ba: 68db ldr r3, [r3, #12]
- 80037bc: f003 0340 and.w r3, r3, #64 ; 0x40
- 80037c0: 2b40 cmp r3, #64 ; 0x40
- 80037c2: d107 bne.n 80037d4 <HAL_TIM_IRQHandler+0x20a>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- 80037c4: 687b ldr r3, [r7, #4]
- 80037c6: 681b ldr r3, [r3, #0]
- 80037c8: f06f 0240 mvn.w r2, #64 ; 0x40
- 80037cc: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
- 80037ce: 6878 ldr r0, [r7, #4]
- 80037d0: f000 fa0a bl 8003be8 <HAL_TIM_TriggerCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- 80037d4: 687b ldr r3, [r7, #4]
- 80037d6: 681b ldr r3, [r3, #0]
- 80037d8: 691b ldr r3, [r3, #16]
- 80037da: f003 0320 and.w r3, r3, #32
- 80037de: 2b20 cmp r3, #32
- 80037e0: d10e bne.n 8003800 <HAL_TIM_IRQHandler+0x236>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- 80037e2: 687b ldr r3, [r7, #4]
- 80037e4: 681b ldr r3, [r3, #0]
- 80037e6: 68db ldr r3, [r3, #12]
- 80037e8: f003 0320 and.w r3, r3, #32
- 80037ec: 2b20 cmp r3, #32
- 80037ee: d107 bne.n 8003800 <HAL_TIM_IRQHandler+0x236>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- 80037f0: 687b ldr r3, [r7, #4]
- 80037f2: 681b ldr r3, [r3, #0]
- 80037f4: f06f 0220 mvn.w r2, #32
- 80037f8: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
- 80037fa: 6878 ldr r0, [r7, #4]
- 80037fc: f000 fe18 bl 8004430 <HAL_TIMEx_CommutCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
- 8003800: bf00 nop
- 8003802: 3708 adds r7, #8
- 8003804: 46bd mov sp, r7
- 8003806: bd80 pop {r7, pc}
-
-08003808 <HAL_TIM_PWM_ConfigChannel>:
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- 8003808: b580 push {r7, lr}
- 800380a: b084 sub sp, #16
- 800380c: af00 add r7, sp, #0
- 800380e: 60f8 str r0, [r7, #12]
- 8003810: 60b9 str r1, [r7, #8]
- 8003812: 607a str r2, [r7, #4]
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003814: 68fb ldr r3, [r7, #12]
- 8003816: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 800381a: 2b01 cmp r3, #1
- 800381c: d101 bne.n 8003822 <HAL_TIM_PWM_ConfigChannel+0x1a>
- 800381e: 2302 movs r3, #2
- 8003820: e105 b.n 8003a2e <HAL_TIM_PWM_ConfigChannel+0x226>
- 8003822: 68fb ldr r3, [r7, #12]
- 8003824: 2201 movs r2, #1
- 8003826: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 800382a: 68fb ldr r3, [r7, #12]
- 800382c: 2202 movs r2, #2
- 800382e: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- switch (Channel)
- 8003832: 687b ldr r3, [r7, #4]
- 8003834: 2b14 cmp r3, #20
- 8003836: f200 80f0 bhi.w 8003a1a <HAL_TIM_PWM_ConfigChannel+0x212>
- 800383a: a201 add r2, pc, #4 ; (adr r2, 8003840 <HAL_TIM_PWM_ConfigChannel+0x38>)
- 800383c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8003840: 08003895 .word 0x08003895
- 8003844: 08003a1b .word 0x08003a1b
- 8003848: 08003a1b .word 0x08003a1b
- 800384c: 08003a1b .word 0x08003a1b
- 8003850: 080038d5 .word 0x080038d5
- 8003854: 08003a1b .word 0x08003a1b
- 8003858: 08003a1b .word 0x08003a1b
- 800385c: 08003a1b .word 0x08003a1b
- 8003860: 08003917 .word 0x08003917
- 8003864: 08003a1b .word 0x08003a1b
- 8003868: 08003a1b .word 0x08003a1b
- 800386c: 08003a1b .word 0x08003a1b
- 8003870: 08003957 .word 0x08003957
- 8003874: 08003a1b .word 0x08003a1b
- 8003878: 08003a1b .word 0x08003a1b
- 800387c: 08003a1b .word 0x08003a1b
- 8003880: 08003999 .word 0x08003999
- 8003884: 08003a1b .word 0x08003a1b
- 8003888: 08003a1b .word 0x08003a1b
- 800388c: 08003a1b .word 0x08003a1b
- 8003890: 080039d9 .word 0x080039d9
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- 8003894: 68fb ldr r3, [r7, #12]
- 8003896: 681b ldr r3, [r3, #0]
- 8003898: 68b9 ldr r1, [r7, #8]
- 800389a: 4618 mov r0, r3
- 800389c: f000 fa4e bl 8003d3c <TIM_OC1_SetConfig>
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 80038a0: 68fb ldr r3, [r7, #12]
- 80038a2: 681b ldr r3, [r3, #0]
- 80038a4: 699a ldr r2, [r3, #24]
- 80038a6: 68fb ldr r3, [r7, #12]
- 80038a8: 681b ldr r3, [r3, #0]
- 80038aa: f042 0208 orr.w r2, r2, #8
- 80038ae: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- 80038b0: 68fb ldr r3, [r7, #12]
- 80038b2: 681b ldr r3, [r3, #0]
- 80038b4: 699a ldr r2, [r3, #24]
- 80038b6: 68fb ldr r3, [r7, #12]
- 80038b8: 681b ldr r3, [r3, #0]
- 80038ba: f022 0204 bic.w r2, r2, #4
- 80038be: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- 80038c0: 68fb ldr r3, [r7, #12]
- 80038c2: 681b ldr r3, [r3, #0]
- 80038c4: 6999 ldr r1, [r3, #24]
- 80038c6: 68bb ldr r3, [r7, #8]
- 80038c8: 691a ldr r2, [r3, #16]
- 80038ca: 68fb ldr r3, [r7, #12]
- 80038cc: 681b ldr r3, [r3, #0]
- 80038ce: 430a orrs r2, r1
- 80038d0: 619a str r2, [r3, #24]
- break;
- 80038d2: e0a3 b.n 8003a1c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- 80038d4: 68fb ldr r3, [r7, #12]
- 80038d6: 681b ldr r3, [r3, #0]
- 80038d8: 68b9 ldr r1, [r7, #8]
- 80038da: 4618 mov r0, r3
- 80038dc: f000 faa0 bl 8003e20 <TIM_OC2_SetConfig>
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 80038e0: 68fb ldr r3, [r7, #12]
- 80038e2: 681b ldr r3, [r3, #0]
- 80038e4: 699a ldr r2, [r3, #24]
- 80038e6: 68fb ldr r3, [r7, #12]
- 80038e8: 681b ldr r3, [r3, #0]
- 80038ea: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 80038ee: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 80038f0: 68fb ldr r3, [r7, #12]
- 80038f2: 681b ldr r3, [r3, #0]
- 80038f4: 699a ldr r2, [r3, #24]
- 80038f6: 68fb ldr r3, [r7, #12]
- 80038f8: 681b ldr r3, [r3, #0]
- 80038fa: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 80038fe: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- 8003900: 68fb ldr r3, [r7, #12]
- 8003902: 681b ldr r3, [r3, #0]
- 8003904: 6999 ldr r1, [r3, #24]
- 8003906: 68bb ldr r3, [r7, #8]
- 8003908: 691b ldr r3, [r3, #16]
- 800390a: 021a lsls r2, r3, #8
- 800390c: 68fb ldr r3, [r7, #12]
- 800390e: 681b ldr r3, [r3, #0]
- 8003910: 430a orrs r2, r1
- 8003912: 619a str r2, [r3, #24]
- break;
- 8003914: e082 b.n 8003a1c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- 8003916: 68fb ldr r3, [r7, #12]
- 8003918: 681b ldr r3, [r3, #0]
- 800391a: 68b9 ldr r1, [r7, #8]
- 800391c: 4618 mov r0, r3
- 800391e: f000 faf7 bl 8003f10 <TIM_OC3_SetConfig>
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 8003922: 68fb ldr r3, [r7, #12]
- 8003924: 681b ldr r3, [r3, #0]
- 8003926: 69da ldr r2, [r3, #28]
- 8003928: 68fb ldr r3, [r7, #12]
- 800392a: 681b ldr r3, [r3, #0]
- 800392c: f042 0208 orr.w r2, r2, #8
- 8003930: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- 8003932: 68fb ldr r3, [r7, #12]
- 8003934: 681b ldr r3, [r3, #0]
- 8003936: 69da ldr r2, [r3, #28]
- 8003938: 68fb ldr r3, [r7, #12]
- 800393a: 681b ldr r3, [r3, #0]
- 800393c: f022 0204 bic.w r2, r2, #4
- 8003940: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- 8003942: 68fb ldr r3, [r7, #12]
- 8003944: 681b ldr r3, [r3, #0]
- 8003946: 69d9 ldr r1, [r3, #28]
- 8003948: 68bb ldr r3, [r7, #8]
- 800394a: 691a ldr r2, [r3, #16]
- 800394c: 68fb ldr r3, [r7, #12]
- 800394e: 681b ldr r3, [r3, #0]
- 8003950: 430a orrs r2, r1
- 8003952: 61da str r2, [r3, #28]
- break;
- 8003954: e062 b.n 8003a1c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- 8003956: 68fb ldr r3, [r7, #12]
- 8003958: 681b ldr r3, [r3, #0]
- 800395a: 68b9 ldr r1, [r7, #8]
- 800395c: 4618 mov r0, r3
- 800395e: f000 fb4d bl 8003ffc <TIM_OC4_SetConfig>
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 8003962: 68fb ldr r3, [r7, #12]
- 8003964: 681b ldr r3, [r3, #0]
- 8003966: 69da ldr r2, [r3, #28]
- 8003968: 68fb ldr r3, [r7, #12]
- 800396a: 681b ldr r3, [r3, #0]
- 800396c: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003970: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 8003972: 68fb ldr r3, [r7, #12]
- 8003974: 681b ldr r3, [r3, #0]
- 8003976: 69da ldr r2, [r3, #28]
- 8003978: 68fb ldr r3, [r7, #12]
- 800397a: 681b ldr r3, [r3, #0]
- 800397c: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003980: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- 8003982: 68fb ldr r3, [r7, #12]
- 8003984: 681b ldr r3, [r3, #0]
- 8003986: 69d9 ldr r1, [r3, #28]
- 8003988: 68bb ldr r3, [r7, #8]
- 800398a: 691b ldr r3, [r3, #16]
- 800398c: 021a lsls r2, r3, #8
- 800398e: 68fb ldr r3, [r7, #12]
- 8003990: 681b ldr r3, [r3, #0]
- 8003992: 430a orrs r2, r1
- 8003994: 61da str r2, [r3, #28]
- break;
- 8003996: e041 b.n 8003a1c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- 8003998: 68fb ldr r3, [r7, #12]
- 800399a: 681b ldr r3, [r3, #0]
- 800399c: 68b9 ldr r1, [r7, #8]
- 800399e: 4618 mov r0, r3
- 80039a0: f000 fb84 bl 80040ac <TIM_OC5_SetConfig>
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
- 80039a4: 68fb ldr r3, [r7, #12]
- 80039a6: 681b ldr r3, [r3, #0]
- 80039a8: 6d5a ldr r2, [r3, #84] ; 0x54
- 80039aa: 68fb ldr r3, [r7, #12]
- 80039ac: 681b ldr r3, [r3, #0]
- 80039ae: f042 0208 orr.w r2, r2, #8
- 80039b2: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- 80039b4: 68fb ldr r3, [r7, #12]
- 80039b6: 681b ldr r3, [r3, #0]
- 80039b8: 6d5a ldr r2, [r3, #84] ; 0x54
- 80039ba: 68fb ldr r3, [r7, #12]
- 80039bc: 681b ldr r3, [r3, #0]
- 80039be: f022 0204 bic.w r2, r2, #4
- 80039c2: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- 80039c4: 68fb ldr r3, [r7, #12]
- 80039c6: 681b ldr r3, [r3, #0]
- 80039c8: 6d59 ldr r1, [r3, #84] ; 0x54
- 80039ca: 68bb ldr r3, [r7, #8]
- 80039cc: 691a ldr r2, [r3, #16]
- 80039ce: 68fb ldr r3, [r7, #12]
- 80039d0: 681b ldr r3, [r3, #0]
- 80039d2: 430a orrs r2, r1
- 80039d4: 655a str r2, [r3, #84] ; 0x54
- break;
- 80039d6: e021 b.n 8003a1c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 6 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- 80039d8: 68fb ldr r3, [r7, #12]
- 80039da: 681b ldr r3, [r3, #0]
- 80039dc: 68b9 ldr r1, [r7, #8]
- 80039de: 4618 mov r0, r3
- 80039e0: f000 fbb6 bl 8004150 <TIM_OC6_SetConfig>
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
- 80039e4: 68fb ldr r3, [r7, #12]
- 80039e6: 681b ldr r3, [r3, #0]
- 80039e8: 6d5a ldr r2, [r3, #84] ; 0x54
- 80039ea: 68fb ldr r3, [r7, #12]
- 80039ec: 681b ldr r3, [r3, #0]
- 80039ee: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 80039f2: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- 80039f4: 68fb ldr r3, [r7, #12]
- 80039f6: 681b ldr r3, [r3, #0]
- 80039f8: 6d5a ldr r2, [r3, #84] ; 0x54
- 80039fa: 68fb ldr r3, [r7, #12]
- 80039fc: 681b ldr r3, [r3, #0]
- 80039fe: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003a02: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- 8003a04: 68fb ldr r3, [r7, #12]
- 8003a06: 681b ldr r3, [r3, #0]
- 8003a08: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003a0a: 68bb ldr r3, [r7, #8]
- 8003a0c: 691b ldr r3, [r3, #16]
- 8003a0e: 021a lsls r2, r3, #8
- 8003a10: 68fb ldr r3, [r7, #12]
- 8003a12: 681b ldr r3, [r3, #0]
- 8003a14: 430a orrs r2, r1
- 8003a16: 655a str r2, [r3, #84] ; 0x54
- break;
- 8003a18: e000 b.n 8003a1c <HAL_TIM_PWM_ConfigChannel+0x214>
- }
-
- default:
- break;
- 8003a1a: bf00 nop
- }
-
- htim->State = HAL_TIM_STATE_READY;
- 8003a1c: 68fb ldr r3, [r7, #12]
- 8003a1e: 2201 movs r2, #1
- 8003a20: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003a24: 68fb ldr r3, [r7, #12]
- 8003a26: 2200 movs r2, #0
- 8003a28: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003a2c: 2300 movs r3, #0
-}
- 8003a2e: 4618 mov r0, r3
- 8003a30: 3710 adds r7, #16
- 8003a32: 46bd mov sp, r7
- 8003a34: bd80 pop {r7, pc}
- 8003a36: bf00 nop
-
-08003a38 <HAL_TIM_ConfigClockSource>:
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- 8003a38: b580 push {r7, lr}
- 8003a3a: b084 sub sp, #16
- 8003a3c: af00 add r7, sp, #0
- 8003a3e: 6078 str r0, [r7, #4]
- 8003a40: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003a42: 687b ldr r3, [r7, #4]
- 8003a44: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8003a48: 2b01 cmp r3, #1
- 8003a4a: d101 bne.n 8003a50 <HAL_TIM_ConfigClockSource+0x18>
- 8003a4c: 2302 movs r3, #2
- 8003a4e: e0a6 b.n 8003b9e <HAL_TIM_ConfigClockSource+0x166>
- 8003a50: 687b ldr r3, [r7, #4]
- 8003a52: 2201 movs r2, #1
- 8003a54: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8003a58: 687b ldr r3, [r7, #4]
- 8003a5a: 2202 movs r2, #2
- 8003a5c: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- 8003a60: 687b ldr r3, [r7, #4]
- 8003a62: 681b ldr r3, [r3, #0]
- 8003a64: 689b ldr r3, [r3, #8]
- 8003a66: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 8003a68: 68fa ldr r2, [r7, #12]
- 8003a6a: 4b4f ldr r3, [pc, #316] ; (8003ba8 <HAL_TIM_ConfigClockSource+0x170>)
- 8003a6c: 4013 ands r3, r2
- 8003a6e: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8003a70: 68fb ldr r3, [r7, #12]
- 8003a72: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8003a76: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003a78: 687b ldr r3, [r7, #4]
- 8003a7a: 681b ldr r3, [r3, #0]
- 8003a7c: 68fa ldr r2, [r7, #12]
- 8003a7e: 609a str r2, [r3, #8]
-
- switch (sClockSourceConfig->ClockSource)
- 8003a80: 683b ldr r3, [r7, #0]
- 8003a82: 681b ldr r3, [r3, #0]
- 8003a84: 2b40 cmp r3, #64 ; 0x40
- 8003a86: d067 beq.n 8003b58 <HAL_TIM_ConfigClockSource+0x120>
- 8003a88: 2b40 cmp r3, #64 ; 0x40
- 8003a8a: d80b bhi.n 8003aa4 <HAL_TIM_ConfigClockSource+0x6c>
- 8003a8c: 2b10 cmp r3, #16
- 8003a8e: d073 beq.n 8003b78 <HAL_TIM_ConfigClockSource+0x140>
- 8003a90: 2b10 cmp r3, #16
- 8003a92: d802 bhi.n 8003a9a <HAL_TIM_ConfigClockSource+0x62>
- 8003a94: 2b00 cmp r3, #0
- 8003a96: d06f beq.n 8003b78 <HAL_TIM_ConfigClockSource+0x140>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- break;
- 8003a98: e078 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003a9a: 2b20 cmp r3, #32
- 8003a9c: d06c beq.n 8003b78 <HAL_TIM_ConfigClockSource+0x140>
- 8003a9e: 2b30 cmp r3, #48 ; 0x30
- 8003aa0: d06a beq.n 8003b78 <HAL_TIM_ConfigClockSource+0x140>
- break;
- 8003aa2: e073 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003aa4: 2b70 cmp r3, #112 ; 0x70
- 8003aa6: d00d beq.n 8003ac4 <HAL_TIM_ConfigClockSource+0x8c>
- 8003aa8: 2b70 cmp r3, #112 ; 0x70
- 8003aaa: d804 bhi.n 8003ab6 <HAL_TIM_ConfigClockSource+0x7e>
- 8003aac: 2b50 cmp r3, #80 ; 0x50
- 8003aae: d033 beq.n 8003b18 <HAL_TIM_ConfigClockSource+0xe0>
- 8003ab0: 2b60 cmp r3, #96 ; 0x60
- 8003ab2: d041 beq.n 8003b38 <HAL_TIM_ConfigClockSource+0x100>
- break;
- 8003ab4: e06a b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003ab6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8003aba: d066 beq.n 8003b8a <HAL_TIM_ConfigClockSource+0x152>
- 8003abc: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8003ac0: d017 beq.n 8003af2 <HAL_TIM_ConfigClockSource+0xba>
- break;
- 8003ac2: e063 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003ac4: 687b ldr r3, [r7, #4]
- 8003ac6: 6818 ldr r0, [r3, #0]
- 8003ac8: 683b ldr r3, [r7, #0]
- 8003aca: 6899 ldr r1, [r3, #8]
- 8003acc: 683b ldr r3, [r7, #0]
- 8003ace: 685a ldr r2, [r3, #4]
- 8003ad0: 683b ldr r3, [r7, #0]
- 8003ad2: 68db ldr r3, [r3, #12]
- 8003ad4: f000 fc0a bl 80042ec <TIM_ETR_SetConfig>
- tmpsmcr = htim->Instance->SMCR;
- 8003ad8: 687b ldr r3, [r7, #4]
- 8003ada: 681b ldr r3, [r3, #0]
- 8003adc: 689b ldr r3, [r3, #8]
- 8003ade: 60fb str r3, [r7, #12]
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8003ae0: 68fb ldr r3, [r7, #12]
- 8003ae2: f043 0377 orr.w r3, r3, #119 ; 0x77
- 8003ae6: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003ae8: 687b ldr r3, [r7, #4]
- 8003aea: 681b ldr r3, [r3, #0]
- 8003aec: 68fa ldr r2, [r7, #12]
- 8003aee: 609a str r2, [r3, #8]
- break;
- 8003af0: e04c b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003af2: 687b ldr r3, [r7, #4]
- 8003af4: 6818 ldr r0, [r3, #0]
- 8003af6: 683b ldr r3, [r7, #0]
- 8003af8: 6899 ldr r1, [r3, #8]
- 8003afa: 683b ldr r3, [r7, #0]
- 8003afc: 685a ldr r2, [r3, #4]
- 8003afe: 683b ldr r3, [r7, #0]
- 8003b00: 68db ldr r3, [r3, #12]
- 8003b02: f000 fbf3 bl 80042ec <TIM_ETR_SetConfig>
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- 8003b06: 687b ldr r3, [r7, #4]
- 8003b08: 681b ldr r3, [r3, #0]
- 8003b0a: 689a ldr r2, [r3, #8]
- 8003b0c: 687b ldr r3, [r7, #4]
- 8003b0e: 681b ldr r3, [r3, #0]
- 8003b10: f442 4280 orr.w r2, r2, #16384 ; 0x4000
- 8003b14: 609a str r2, [r3, #8]
- break;
- 8003b16: e039 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003b18: 687b ldr r3, [r7, #4]
- 8003b1a: 6818 ldr r0, [r3, #0]
- 8003b1c: 683b ldr r3, [r7, #0]
- 8003b1e: 6859 ldr r1, [r3, #4]
- 8003b20: 683b ldr r3, [r7, #0]
- 8003b22: 68db ldr r3, [r3, #12]
- 8003b24: 461a mov r2, r3
- 8003b26: f000 fb67 bl 80041f8 <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 8003b2a: 687b ldr r3, [r7, #4]
- 8003b2c: 681b ldr r3, [r3, #0]
- 8003b2e: 2150 movs r1, #80 ; 0x50
- 8003b30: 4618 mov r0, r3
- 8003b32: f000 fbc0 bl 80042b6 <TIM_ITRx_SetConfig>
- break;
- 8003b36: e029 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI2_ConfigInputStage(htim->Instance,
- 8003b38: 687b ldr r3, [r7, #4]
- 8003b3a: 6818 ldr r0, [r3, #0]
- 8003b3c: 683b ldr r3, [r7, #0]
- 8003b3e: 6859 ldr r1, [r3, #4]
- 8003b40: 683b ldr r3, [r7, #0]
- 8003b42: 68db ldr r3, [r3, #12]
- 8003b44: 461a mov r2, r3
- 8003b46: f000 fb86 bl 8004256 <TIM_TI2_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 8003b4a: 687b ldr r3, [r7, #4]
- 8003b4c: 681b ldr r3, [r3, #0]
- 8003b4e: 2160 movs r1, #96 ; 0x60
- 8003b50: 4618 mov r0, r3
- 8003b52: f000 fbb0 bl 80042b6 <TIM_ITRx_SetConfig>
- break;
- 8003b56: e019 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003b58: 687b ldr r3, [r7, #4]
- 8003b5a: 6818 ldr r0, [r3, #0]
- 8003b5c: 683b ldr r3, [r7, #0]
- 8003b5e: 6859 ldr r1, [r3, #4]
- 8003b60: 683b ldr r3, [r7, #0]
- 8003b62: 68db ldr r3, [r3, #12]
- 8003b64: 461a mov r2, r3
- 8003b66: f000 fb47 bl 80041f8 <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 8003b6a: 687b ldr r3, [r7, #4]
- 8003b6c: 681b ldr r3, [r3, #0]
- 8003b6e: 2140 movs r1, #64 ; 0x40
- 8003b70: 4618 mov r0, r3
- 8003b72: f000 fba0 bl 80042b6 <TIM_ITRx_SetConfig>
- break;
- 8003b76: e009 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 8003b78: 687b ldr r3, [r7, #4]
- 8003b7a: 681a ldr r2, [r3, #0]
- 8003b7c: 683b ldr r3, [r7, #0]
- 8003b7e: 681b ldr r3, [r3, #0]
- 8003b80: 4619 mov r1, r3
- 8003b82: 4610 mov r0, r2
- 8003b84: f000 fb97 bl 80042b6 <TIM_ITRx_SetConfig>
- break;
- 8003b88: e000 b.n 8003b8c <HAL_TIM_ConfigClockSource+0x154>
- break;
- 8003b8a: bf00 nop
- }
- htim->State = HAL_TIM_STATE_READY;
- 8003b8c: 687b ldr r3, [r7, #4]
- 8003b8e: 2201 movs r2, #1
- 8003b90: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003b94: 687b ldr r3, [r7, #4]
- 8003b96: 2200 movs r2, #0
- 8003b98: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003b9c: 2300 movs r3, #0
-}
- 8003b9e: 4618 mov r0, r3
- 8003ba0: 3710 adds r7, #16
- 8003ba2: 46bd mov sp, r7
- 8003ba4: bd80 pop {r7, pc}
- 8003ba6: bf00 nop
- 8003ba8: fffeff88 .word 0xfffeff88
-
-08003bac <HAL_TIM_OC_DelayElapsedCallback>:
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- 8003bac: b480 push {r7}
- 8003bae: b083 sub sp, #12
- 8003bb0: af00 add r7, sp, #0
- 8003bb2: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
- 8003bb4: bf00 nop
- 8003bb6: 370c adds r7, #12
- 8003bb8: 46bd mov sp, r7
- 8003bba: f85d 7b04 ldr.w r7, [sp], #4
- 8003bbe: 4770 bx lr
-
-08003bc0 <HAL_TIM_IC_CaptureCallback>:
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- 8003bc0: b480 push {r7}
- 8003bc2: b083 sub sp, #12
- 8003bc4: af00 add r7, sp, #0
- 8003bc6: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
- 8003bc8: bf00 nop
- 8003bca: 370c adds r7, #12
- 8003bcc: 46bd mov sp, r7
- 8003bce: f85d 7b04 ldr.w r7, [sp], #4
- 8003bd2: 4770 bx lr
-
-08003bd4 <HAL_TIM_PWM_PulseFinishedCallback>:
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- 8003bd4: b480 push {r7}
- 8003bd6: b083 sub sp, #12
- 8003bd8: af00 add r7, sp, #0
- 8003bda: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
- 8003bdc: bf00 nop
- 8003bde: 370c adds r7, #12
- 8003be0: 46bd mov sp, r7
- 8003be2: f85d 7b04 ldr.w r7, [sp], #4
- 8003be6: 4770 bx lr
-
-08003be8 <HAL_TIM_TriggerCallback>:
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- 8003be8: b480 push {r7}
- 8003bea: b083 sub sp, #12
- 8003bec: af00 add r7, sp, #0
- 8003bee: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
- 8003bf0: bf00 nop
- 8003bf2: 370c adds r7, #12
- 8003bf4: 46bd mov sp, r7
- 8003bf6: f85d 7b04 ldr.w r7, [sp], #4
- 8003bfa: 4770 bx lr
-
-08003bfc <TIM_Base_SetConfig>:
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- 8003bfc: b480 push {r7}
- 8003bfe: b085 sub sp, #20
- 8003c00: af00 add r7, sp, #0
- 8003c02: 6078 str r0, [r7, #4]
- 8003c04: 6039 str r1, [r7, #0]
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
- 8003c06: 687b ldr r3, [r7, #4]
- 8003c08: 681b ldr r3, [r3, #0]
- 8003c0a: 60fb str r3, [r7, #12]
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8003c0c: 687b ldr r3, [r7, #4]
- 8003c0e: 4a40 ldr r2, [pc, #256] ; (8003d10 <TIM_Base_SetConfig+0x114>)
- 8003c10: 4293 cmp r3, r2
- 8003c12: d013 beq.n 8003c3c <TIM_Base_SetConfig+0x40>
- 8003c14: 687b ldr r3, [r7, #4]
- 8003c16: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003c1a: d00f beq.n 8003c3c <TIM_Base_SetConfig+0x40>
- 8003c1c: 687b ldr r3, [r7, #4]
- 8003c1e: 4a3d ldr r2, [pc, #244] ; (8003d14 <TIM_Base_SetConfig+0x118>)
- 8003c20: 4293 cmp r3, r2
- 8003c22: d00b beq.n 8003c3c <TIM_Base_SetConfig+0x40>
- 8003c24: 687b ldr r3, [r7, #4]
- 8003c26: 4a3c ldr r2, [pc, #240] ; (8003d18 <TIM_Base_SetConfig+0x11c>)
- 8003c28: 4293 cmp r3, r2
- 8003c2a: d007 beq.n 8003c3c <TIM_Base_SetConfig+0x40>
- 8003c2c: 687b ldr r3, [r7, #4]
- 8003c2e: 4a3b ldr r2, [pc, #236] ; (8003d1c <TIM_Base_SetConfig+0x120>)
- 8003c30: 4293 cmp r3, r2
- 8003c32: d003 beq.n 8003c3c <TIM_Base_SetConfig+0x40>
- 8003c34: 687b ldr r3, [r7, #4]
- 8003c36: 4a3a ldr r2, [pc, #232] ; (8003d20 <TIM_Base_SetConfig+0x124>)
- 8003c38: 4293 cmp r3, r2
- 8003c3a: d108 bne.n 8003c4e <TIM_Base_SetConfig+0x52>
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 8003c3c: 68fb ldr r3, [r7, #12]
- 8003c3e: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8003c42: 60fb str r3, [r7, #12]
- tmpcr1 |= Structure->CounterMode;
- 8003c44: 683b ldr r3, [r7, #0]
- 8003c46: 685b ldr r3, [r3, #4]
- 8003c48: 68fa ldr r2, [r7, #12]
- 8003c4a: 4313 orrs r3, r2
- 8003c4c: 60fb str r3, [r7, #12]
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 8003c4e: 687b ldr r3, [r7, #4]
- 8003c50: 4a2f ldr r2, [pc, #188] ; (8003d10 <TIM_Base_SetConfig+0x114>)
- 8003c52: 4293 cmp r3, r2
- 8003c54: d02b beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c56: 687b ldr r3, [r7, #4]
- 8003c58: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003c5c: d027 beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c5e: 687b ldr r3, [r7, #4]
- 8003c60: 4a2c ldr r2, [pc, #176] ; (8003d14 <TIM_Base_SetConfig+0x118>)
- 8003c62: 4293 cmp r3, r2
- 8003c64: d023 beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c66: 687b ldr r3, [r7, #4]
- 8003c68: 4a2b ldr r2, [pc, #172] ; (8003d18 <TIM_Base_SetConfig+0x11c>)
- 8003c6a: 4293 cmp r3, r2
- 8003c6c: d01f beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c6e: 687b ldr r3, [r7, #4]
- 8003c70: 4a2a ldr r2, [pc, #168] ; (8003d1c <TIM_Base_SetConfig+0x120>)
- 8003c72: 4293 cmp r3, r2
- 8003c74: d01b beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c76: 687b ldr r3, [r7, #4]
- 8003c78: 4a29 ldr r2, [pc, #164] ; (8003d20 <TIM_Base_SetConfig+0x124>)
- 8003c7a: 4293 cmp r3, r2
- 8003c7c: d017 beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c7e: 687b ldr r3, [r7, #4]
- 8003c80: 4a28 ldr r2, [pc, #160] ; (8003d24 <TIM_Base_SetConfig+0x128>)
- 8003c82: 4293 cmp r3, r2
- 8003c84: d013 beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c86: 687b ldr r3, [r7, #4]
- 8003c88: 4a27 ldr r2, [pc, #156] ; (8003d28 <TIM_Base_SetConfig+0x12c>)
- 8003c8a: 4293 cmp r3, r2
- 8003c8c: d00f beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c8e: 687b ldr r3, [r7, #4]
- 8003c90: 4a26 ldr r2, [pc, #152] ; (8003d2c <TIM_Base_SetConfig+0x130>)
- 8003c92: 4293 cmp r3, r2
- 8003c94: d00b beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c96: 687b ldr r3, [r7, #4]
- 8003c98: 4a25 ldr r2, [pc, #148] ; (8003d30 <TIM_Base_SetConfig+0x134>)
- 8003c9a: 4293 cmp r3, r2
- 8003c9c: d007 beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003c9e: 687b ldr r3, [r7, #4]
- 8003ca0: 4a24 ldr r2, [pc, #144] ; (8003d34 <TIM_Base_SetConfig+0x138>)
- 8003ca2: 4293 cmp r3, r2
- 8003ca4: d003 beq.n 8003cae <TIM_Base_SetConfig+0xb2>
- 8003ca6: 687b ldr r3, [r7, #4]
- 8003ca8: 4a23 ldr r2, [pc, #140] ; (8003d38 <TIM_Base_SetConfig+0x13c>)
- 8003caa: 4293 cmp r3, r2
- 8003cac: d108 bne.n 8003cc0 <TIM_Base_SetConfig+0xc4>
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- 8003cae: 68fb ldr r3, [r7, #12]
- 8003cb0: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003cb4: 60fb str r3, [r7, #12]
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 8003cb6: 683b ldr r3, [r7, #0]
- 8003cb8: 68db ldr r3, [r3, #12]
- 8003cba: 68fa ldr r2, [r7, #12]
- 8003cbc: 4313 orrs r3, r2
- 8003cbe: 60fb str r3, [r7, #12]
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8003cc0: 68fb ldr r3, [r7, #12]
- 8003cc2: f023 0280 bic.w r2, r3, #128 ; 0x80
- 8003cc6: 683b ldr r3, [r7, #0]
- 8003cc8: 695b ldr r3, [r3, #20]
- 8003cca: 4313 orrs r3, r2
- 8003ccc: 60fb str r3, [r7, #12]
-
- TIMx->CR1 = tmpcr1;
- 8003cce: 687b ldr r3, [r7, #4]
- 8003cd0: 68fa ldr r2, [r7, #12]
- 8003cd2: 601a str r2, [r3, #0]
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
- 8003cd4: 683b ldr r3, [r7, #0]
- 8003cd6: 689a ldr r2, [r3, #8]
- 8003cd8: 687b ldr r3, [r7, #4]
- 8003cda: 62da str r2, [r3, #44] ; 0x2c
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
- 8003cdc: 683b ldr r3, [r7, #0]
- 8003cde: 681a ldr r2, [r3, #0]
- 8003ce0: 687b ldr r3, [r7, #4]
- 8003ce2: 629a str r2, [r3, #40] ; 0x28
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8003ce4: 687b ldr r3, [r7, #4]
- 8003ce6: 4a0a ldr r2, [pc, #40] ; (8003d10 <TIM_Base_SetConfig+0x114>)
- 8003ce8: 4293 cmp r3, r2
- 8003cea: d003 beq.n 8003cf4 <TIM_Base_SetConfig+0xf8>
- 8003cec: 687b ldr r3, [r7, #4]
- 8003cee: 4a0c ldr r2, [pc, #48] ; (8003d20 <TIM_Base_SetConfig+0x124>)
- 8003cf0: 4293 cmp r3, r2
- 8003cf2: d103 bne.n 8003cfc <TIM_Base_SetConfig+0x100>
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- 8003cf4: 683b ldr r3, [r7, #0]
- 8003cf6: 691a ldr r2, [r3, #16]
- 8003cf8: 687b ldr r3, [r7, #4]
- 8003cfa: 631a str r2, [r3, #48] ; 0x30
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
- 8003cfc: 687b ldr r3, [r7, #4]
- 8003cfe: 2201 movs r2, #1
- 8003d00: 615a str r2, [r3, #20]
-}
- 8003d02: bf00 nop
- 8003d04: 3714 adds r7, #20
- 8003d06: 46bd mov sp, r7
- 8003d08: f85d 7b04 ldr.w r7, [sp], #4
- 8003d0c: 4770 bx lr
- 8003d0e: bf00 nop
- 8003d10: 40010000 .word 0x40010000
- 8003d14: 40000400 .word 0x40000400
- 8003d18: 40000800 .word 0x40000800
- 8003d1c: 40000c00 .word 0x40000c00
- 8003d20: 40010400 .word 0x40010400
- 8003d24: 40014000 .word 0x40014000
- 8003d28: 40014400 .word 0x40014400
- 8003d2c: 40014800 .word 0x40014800
- 8003d30: 40001800 .word 0x40001800
- 8003d34: 40001c00 .word 0x40001c00
- 8003d38: 40002000 .word 0x40002000
-
-08003d3c <TIM_OC1_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003d3c: b480 push {r7}
- 8003d3e: b087 sub sp, #28
- 8003d40: af00 add r7, sp, #0
- 8003d42: 6078 str r0, [r7, #4]
- 8003d44: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 8003d46: 687b ldr r3, [r7, #4]
- 8003d48: 6a1b ldr r3, [r3, #32]
- 8003d4a: f023 0201 bic.w r2, r3, #1
- 8003d4e: 687b ldr r3, [r7, #4]
- 8003d50: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8003d52: 687b ldr r3, [r7, #4]
- 8003d54: 6a1b ldr r3, [r3, #32]
- 8003d56: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8003d58: 687b ldr r3, [r7, #4]
- 8003d5a: 685b ldr r3, [r3, #4]
- 8003d5c: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 8003d5e: 687b ldr r3, [r7, #4]
- 8003d60: 699b ldr r3, [r3, #24]
- 8003d62: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- 8003d64: 68fa ldr r2, [r7, #12]
- 8003d66: 4b2b ldr r3, [pc, #172] ; (8003e14 <TIM_OC1_SetConfig+0xd8>)
- 8003d68: 4013 ands r3, r2
- 8003d6a: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- 8003d6c: 68fb ldr r3, [r7, #12]
- 8003d6e: f023 0303 bic.w r3, r3, #3
- 8003d72: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8003d74: 683b ldr r3, [r7, #0]
- 8003d76: 681b ldr r3, [r3, #0]
- 8003d78: 68fa ldr r2, [r7, #12]
- 8003d7a: 4313 orrs r3, r2
- 8003d7c: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- 8003d7e: 697b ldr r3, [r7, #20]
- 8003d80: f023 0302 bic.w r3, r3, #2
- 8003d84: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
- 8003d86: 683b ldr r3, [r7, #0]
- 8003d88: 689b ldr r3, [r3, #8]
- 8003d8a: 697a ldr r2, [r7, #20]
- 8003d8c: 4313 orrs r3, r2
- 8003d8e: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- 8003d90: 687b ldr r3, [r7, #4]
- 8003d92: 4a21 ldr r2, [pc, #132] ; (8003e18 <TIM_OC1_SetConfig+0xdc>)
- 8003d94: 4293 cmp r3, r2
- 8003d96: d003 beq.n 8003da0 <TIM_OC1_SetConfig+0x64>
- 8003d98: 687b ldr r3, [r7, #4]
- 8003d9a: 4a20 ldr r2, [pc, #128] ; (8003e1c <TIM_OC1_SetConfig+0xe0>)
- 8003d9c: 4293 cmp r3, r2
- 8003d9e: d10c bne.n 8003dba <TIM_OC1_SetConfig+0x7e>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- 8003da0: 697b ldr r3, [r7, #20]
- 8003da2: f023 0308 bic.w r3, r3, #8
- 8003da6: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- 8003da8: 683b ldr r3, [r7, #0]
- 8003daa: 68db ldr r3, [r3, #12]
- 8003dac: 697a ldr r2, [r7, #20]
- 8003dae: 4313 orrs r3, r2
- 8003db0: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- 8003db2: 697b ldr r3, [r7, #20]
- 8003db4: f023 0304 bic.w r3, r3, #4
- 8003db8: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003dba: 687b ldr r3, [r7, #4]
- 8003dbc: 4a16 ldr r2, [pc, #88] ; (8003e18 <TIM_OC1_SetConfig+0xdc>)
- 8003dbe: 4293 cmp r3, r2
- 8003dc0: d003 beq.n 8003dca <TIM_OC1_SetConfig+0x8e>
- 8003dc2: 687b ldr r3, [r7, #4]
- 8003dc4: 4a15 ldr r2, [pc, #84] ; (8003e1c <TIM_OC1_SetConfig+0xe0>)
- 8003dc6: 4293 cmp r3, r2
- 8003dc8: d111 bne.n 8003dee <TIM_OC1_SetConfig+0xb2>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- 8003dca: 693b ldr r3, [r7, #16]
- 8003dcc: f423 7380 bic.w r3, r3, #256 ; 0x100
- 8003dd0: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS1N;
- 8003dd2: 693b ldr r3, [r7, #16]
- 8003dd4: f423 7300 bic.w r3, r3, #512 ; 0x200
- 8003dd8: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- 8003dda: 683b ldr r3, [r7, #0]
- 8003ddc: 695b ldr r3, [r3, #20]
- 8003dde: 693a ldr r2, [r7, #16]
- 8003de0: 4313 orrs r3, r2
- 8003de2: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- 8003de4: 683b ldr r3, [r7, #0]
- 8003de6: 699b ldr r3, [r3, #24]
- 8003de8: 693a ldr r2, [r7, #16]
- 8003dea: 4313 orrs r3, r2
- 8003dec: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8003dee: 687b ldr r3, [r7, #4]
- 8003df0: 693a ldr r2, [r7, #16]
- 8003df2: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 8003df4: 687b ldr r3, [r7, #4]
- 8003df6: 68fa ldr r2, [r7, #12]
- 8003df8: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
- 8003dfa: 683b ldr r3, [r7, #0]
- 8003dfc: 685a ldr r2, [r3, #4]
- 8003dfe: 687b ldr r3, [r7, #4]
- 8003e00: 635a str r2, [r3, #52] ; 0x34
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8003e02: 687b ldr r3, [r7, #4]
- 8003e04: 697a ldr r2, [r7, #20]
- 8003e06: 621a str r2, [r3, #32]
-}
- 8003e08: bf00 nop
- 8003e0a: 371c adds r7, #28
- 8003e0c: 46bd mov sp, r7
- 8003e0e: f85d 7b04 ldr.w r7, [sp], #4
- 8003e12: 4770 bx lr
- 8003e14: fffeff8f .word 0xfffeff8f
- 8003e18: 40010000 .word 0x40010000
- 8003e1c: 40010400 .word 0x40010400
-
-08003e20 <TIM_OC2_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003e20: b480 push {r7}
- 8003e22: b087 sub sp, #28
- 8003e24: af00 add r7, sp, #0
- 8003e26: 6078 str r0, [r7, #4]
- 8003e28: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 8003e2a: 687b ldr r3, [r7, #4]
- 8003e2c: 6a1b ldr r3, [r3, #32]
- 8003e2e: f023 0210 bic.w r2, r3, #16
- 8003e32: 687b ldr r3, [r7, #4]
- 8003e34: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8003e36: 687b ldr r3, [r7, #4]
- 8003e38: 6a1b ldr r3, [r3, #32]
- 8003e3a: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8003e3c: 687b ldr r3, [r7, #4]
- 8003e3e: 685b ldr r3, [r3, #4]
- 8003e40: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 8003e42: 687b ldr r3, [r7, #4]
- 8003e44: 699b ldr r3, [r3, #24]
- 8003e46: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- 8003e48: 68fa ldr r2, [r7, #12]
- 8003e4a: 4b2e ldr r3, [pc, #184] ; (8003f04 <TIM_OC2_SetConfig+0xe4>)
- 8003e4c: 4013 ands r3, r2
- 8003e4e: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC2S;
- 8003e50: 68fb ldr r3, [r7, #12]
- 8003e52: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003e56: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 8003e58: 683b ldr r3, [r7, #0]
- 8003e5a: 681b ldr r3, [r3, #0]
- 8003e5c: 021b lsls r3, r3, #8
- 8003e5e: 68fa ldr r2, [r7, #12]
- 8003e60: 4313 orrs r3, r2
- 8003e62: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- 8003e64: 697b ldr r3, [r7, #20]
- 8003e66: f023 0320 bic.w r3, r3, #32
- 8003e6a: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
- 8003e6c: 683b ldr r3, [r7, #0]
- 8003e6e: 689b ldr r3, [r3, #8]
- 8003e70: 011b lsls r3, r3, #4
- 8003e72: 697a ldr r2, [r7, #20]
- 8003e74: 4313 orrs r3, r2
- 8003e76: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- 8003e78: 687b ldr r3, [r7, #4]
- 8003e7a: 4a23 ldr r2, [pc, #140] ; (8003f08 <TIM_OC2_SetConfig+0xe8>)
- 8003e7c: 4293 cmp r3, r2
- 8003e7e: d003 beq.n 8003e88 <TIM_OC2_SetConfig+0x68>
- 8003e80: 687b ldr r3, [r7, #4]
- 8003e82: 4a22 ldr r2, [pc, #136] ; (8003f0c <TIM_OC2_SetConfig+0xec>)
- 8003e84: 4293 cmp r3, r2
- 8003e86: d10d bne.n 8003ea4 <TIM_OC2_SetConfig+0x84>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- 8003e88: 697b ldr r3, [r7, #20]
- 8003e8a: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8003e8e: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- 8003e90: 683b ldr r3, [r7, #0]
- 8003e92: 68db ldr r3, [r3, #12]
- 8003e94: 011b lsls r3, r3, #4
- 8003e96: 697a ldr r2, [r7, #20]
- 8003e98: 4313 orrs r3, r2
- 8003e9a: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
- 8003e9c: 697b ldr r3, [r7, #20]
- 8003e9e: f023 0340 bic.w r3, r3, #64 ; 0x40
- 8003ea2: 617b str r3, [r7, #20]
-
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003ea4: 687b ldr r3, [r7, #4]
- 8003ea6: 4a18 ldr r2, [pc, #96] ; (8003f08 <TIM_OC2_SetConfig+0xe8>)
- 8003ea8: 4293 cmp r3, r2
- 8003eaa: d003 beq.n 8003eb4 <TIM_OC2_SetConfig+0x94>
- 8003eac: 687b ldr r3, [r7, #4]
- 8003eae: 4a17 ldr r2, [pc, #92] ; (8003f0c <TIM_OC2_SetConfig+0xec>)
- 8003eb0: 4293 cmp r3, r2
- 8003eb2: d113 bne.n 8003edc <TIM_OC2_SetConfig+0xbc>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- 8003eb4: 693b ldr r3, [r7, #16]
- 8003eb6: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 8003eba: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS2N;
- 8003ebc: 693b ldr r3, [r7, #16]
- 8003ebe: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8003ec2: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- 8003ec4: 683b ldr r3, [r7, #0]
- 8003ec6: 695b ldr r3, [r3, #20]
- 8003ec8: 009b lsls r3, r3, #2
- 8003eca: 693a ldr r2, [r7, #16]
- 8003ecc: 4313 orrs r3, r2
- 8003ece: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- 8003ed0: 683b ldr r3, [r7, #0]
- 8003ed2: 699b ldr r3, [r3, #24]
- 8003ed4: 009b lsls r3, r3, #2
- 8003ed6: 693a ldr r2, [r7, #16]
- 8003ed8: 4313 orrs r3, r2
- 8003eda: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8003edc: 687b ldr r3, [r7, #4]
- 8003ede: 693a ldr r2, [r7, #16]
- 8003ee0: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 8003ee2: 687b ldr r3, [r7, #4]
- 8003ee4: 68fa ldr r2, [r7, #12]
- 8003ee6: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
- 8003ee8: 683b ldr r3, [r7, #0]
- 8003eea: 685a ldr r2, [r3, #4]
- 8003eec: 687b ldr r3, [r7, #4]
- 8003eee: 639a str r2, [r3, #56] ; 0x38
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8003ef0: 687b ldr r3, [r7, #4]
- 8003ef2: 697a ldr r2, [r7, #20]
- 8003ef4: 621a str r2, [r3, #32]
-}
- 8003ef6: bf00 nop
- 8003ef8: 371c adds r7, #28
- 8003efa: 46bd mov sp, r7
- 8003efc: f85d 7b04 ldr.w r7, [sp], #4
- 8003f00: 4770 bx lr
- 8003f02: bf00 nop
- 8003f04: feff8fff .word 0xfeff8fff
- 8003f08: 40010000 .word 0x40010000
- 8003f0c: 40010400 .word 0x40010400
-
-08003f10 <TIM_OC3_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003f10: b480 push {r7}
- 8003f12: b087 sub sp, #28
- 8003f14: af00 add r7, sp, #0
- 8003f16: 6078 str r0, [r7, #4]
- 8003f18: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- 8003f1a: 687b ldr r3, [r7, #4]
- 8003f1c: 6a1b ldr r3, [r3, #32]
- 8003f1e: f423 7280 bic.w r2, r3, #256 ; 0x100
- 8003f22: 687b ldr r3, [r7, #4]
- 8003f24: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8003f26: 687b ldr r3, [r7, #4]
- 8003f28: 6a1b ldr r3, [r3, #32]
- 8003f2a: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8003f2c: 687b ldr r3, [r7, #4]
- 8003f2e: 685b ldr r3, [r3, #4]
- 8003f30: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 8003f32: 687b ldr r3, [r7, #4]
- 8003f34: 69db ldr r3, [r3, #28]
- 8003f36: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- 8003f38: 68fa ldr r2, [r7, #12]
- 8003f3a: 4b2d ldr r3, [pc, #180] ; (8003ff0 <TIM_OC3_SetConfig+0xe0>)
- 8003f3c: 4013 ands r3, r2
- 8003f3e: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- 8003f40: 68fb ldr r3, [r7, #12]
- 8003f42: f023 0303 bic.w r3, r3, #3
- 8003f46: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8003f48: 683b ldr r3, [r7, #0]
- 8003f4a: 681b ldr r3, [r3, #0]
- 8003f4c: 68fa ldr r2, [r7, #12]
- 8003f4e: 4313 orrs r3, r2
- 8003f50: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- 8003f52: 697b ldr r3, [r7, #20]
- 8003f54: f423 7300 bic.w r3, r3, #512 ; 0x200
- 8003f58: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
- 8003f5a: 683b ldr r3, [r7, #0]
- 8003f5c: 689b ldr r3, [r3, #8]
- 8003f5e: 021b lsls r3, r3, #8
- 8003f60: 697a ldr r2, [r7, #20]
- 8003f62: 4313 orrs r3, r2
- 8003f64: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- 8003f66: 687b ldr r3, [r7, #4]
- 8003f68: 4a22 ldr r2, [pc, #136] ; (8003ff4 <TIM_OC3_SetConfig+0xe4>)
- 8003f6a: 4293 cmp r3, r2
- 8003f6c: d003 beq.n 8003f76 <TIM_OC3_SetConfig+0x66>
- 8003f6e: 687b ldr r3, [r7, #4]
- 8003f70: 4a21 ldr r2, [pc, #132] ; (8003ff8 <TIM_OC3_SetConfig+0xe8>)
- 8003f72: 4293 cmp r3, r2
- 8003f74: d10d bne.n 8003f92 <TIM_OC3_SetConfig+0x82>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- 8003f76: 697b ldr r3, [r7, #20]
- 8003f78: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8003f7c: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- 8003f7e: 683b ldr r3, [r7, #0]
- 8003f80: 68db ldr r3, [r3, #12]
- 8003f82: 021b lsls r3, r3, #8
- 8003f84: 697a ldr r2, [r7, #20]
- 8003f86: 4313 orrs r3, r2
- 8003f88: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- 8003f8a: 697b ldr r3, [r7, #20]
- 8003f8c: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 8003f90: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003f92: 687b ldr r3, [r7, #4]
- 8003f94: 4a17 ldr r2, [pc, #92] ; (8003ff4 <TIM_OC3_SetConfig+0xe4>)
- 8003f96: 4293 cmp r3, r2
- 8003f98: d003 beq.n 8003fa2 <TIM_OC3_SetConfig+0x92>
- 8003f9a: 687b ldr r3, [r7, #4]
- 8003f9c: 4a16 ldr r2, [pc, #88] ; (8003ff8 <TIM_OC3_SetConfig+0xe8>)
- 8003f9e: 4293 cmp r3, r2
- 8003fa0: d113 bne.n 8003fca <TIM_OC3_SetConfig+0xba>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- 8003fa2: 693b ldr r3, [r7, #16]
- 8003fa4: f423 5380 bic.w r3, r3, #4096 ; 0x1000
- 8003fa8: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS3N;
- 8003faa: 693b ldr r3, [r7, #16]
- 8003fac: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8003fb0: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- 8003fb2: 683b ldr r3, [r7, #0]
- 8003fb4: 695b ldr r3, [r3, #20]
- 8003fb6: 011b lsls r3, r3, #4
- 8003fb8: 693a ldr r2, [r7, #16]
- 8003fba: 4313 orrs r3, r2
- 8003fbc: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- 8003fbe: 683b ldr r3, [r7, #0]
- 8003fc0: 699b ldr r3, [r3, #24]
- 8003fc2: 011b lsls r3, r3, #4
- 8003fc4: 693a ldr r2, [r7, #16]
- 8003fc6: 4313 orrs r3, r2
- 8003fc8: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8003fca: 687b ldr r3, [r7, #4]
- 8003fcc: 693a ldr r2, [r7, #16]
- 8003fce: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 8003fd0: 687b ldr r3, [r7, #4]
- 8003fd2: 68fa ldr r2, [r7, #12]
- 8003fd4: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
- 8003fd6: 683b ldr r3, [r7, #0]
- 8003fd8: 685a ldr r2, [r3, #4]
- 8003fda: 687b ldr r3, [r7, #4]
- 8003fdc: 63da str r2, [r3, #60] ; 0x3c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8003fde: 687b ldr r3, [r7, #4]
- 8003fe0: 697a ldr r2, [r7, #20]
- 8003fe2: 621a str r2, [r3, #32]
-}
- 8003fe4: bf00 nop
- 8003fe6: 371c adds r7, #28
- 8003fe8: 46bd mov sp, r7
- 8003fea: f85d 7b04 ldr.w r7, [sp], #4
- 8003fee: 4770 bx lr
- 8003ff0: fffeff8f .word 0xfffeff8f
- 8003ff4: 40010000 .word 0x40010000
- 8003ff8: 40010400 .word 0x40010400
-
-08003ffc <TIM_OC4_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003ffc: b480 push {r7}
- 8003ffe: b087 sub sp, #28
- 8004000: af00 add r7, sp, #0
- 8004002: 6078 str r0, [r7, #4]
- 8004004: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- 8004006: 687b ldr r3, [r7, #4]
- 8004008: 6a1b ldr r3, [r3, #32]
- 800400a: f423 5280 bic.w r2, r3, #4096 ; 0x1000
- 800400e: 687b ldr r3, [r7, #4]
- 8004010: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004012: 687b ldr r3, [r7, #4]
- 8004014: 6a1b ldr r3, [r3, #32]
- 8004016: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004018: 687b ldr r3, [r7, #4]
- 800401a: 685b ldr r3, [r3, #4]
- 800401c: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 800401e: 687b ldr r3, [r7, #4]
- 8004020: 69db ldr r3, [r3, #28]
- 8004022: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- 8004024: 68fa ldr r2, [r7, #12]
- 8004026: 4b1e ldr r3, [pc, #120] ; (80040a0 <TIM_OC4_SetConfig+0xa4>)
- 8004028: 4013 ands r3, r2
- 800402a: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC4S;
- 800402c: 68fb ldr r3, [r7, #12]
- 800402e: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8004032: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 8004034: 683b ldr r3, [r7, #0]
- 8004036: 681b ldr r3, [r3, #0]
- 8004038: 021b lsls r3, r3, #8
- 800403a: 68fa ldr r2, [r7, #12]
- 800403c: 4313 orrs r3, r2
- 800403e: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- 8004040: 693b ldr r3, [r7, #16]
- 8004042: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8004046: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
- 8004048: 683b ldr r3, [r7, #0]
- 800404a: 689b ldr r3, [r3, #8]
- 800404c: 031b lsls r3, r3, #12
- 800404e: 693a ldr r2, [r7, #16]
- 8004050: 4313 orrs r3, r2
- 8004052: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8004054: 687b ldr r3, [r7, #4]
- 8004056: 4a13 ldr r2, [pc, #76] ; (80040a4 <TIM_OC4_SetConfig+0xa8>)
- 8004058: 4293 cmp r3, r2
- 800405a: d003 beq.n 8004064 <TIM_OC4_SetConfig+0x68>
- 800405c: 687b ldr r3, [r7, #4]
- 800405e: 4a12 ldr r2, [pc, #72] ; (80040a8 <TIM_OC4_SetConfig+0xac>)
- 8004060: 4293 cmp r3, r2
- 8004062: d109 bne.n 8004078 <TIM_OC4_SetConfig+0x7c>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- 8004064: 697b ldr r3, [r7, #20]
- 8004066: f423 4380 bic.w r3, r3, #16384 ; 0x4000
- 800406a: 617b str r3, [r7, #20]
-
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- 800406c: 683b ldr r3, [r7, #0]
- 800406e: 695b ldr r3, [r3, #20]
- 8004070: 019b lsls r3, r3, #6
- 8004072: 697a ldr r2, [r7, #20]
- 8004074: 4313 orrs r3, r2
- 8004076: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004078: 687b ldr r3, [r7, #4]
- 800407a: 697a ldr r2, [r7, #20]
- 800407c: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 800407e: 687b ldr r3, [r7, #4]
- 8004080: 68fa ldr r2, [r7, #12]
- 8004082: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
- 8004084: 683b ldr r3, [r7, #0]
- 8004086: 685a ldr r2, [r3, #4]
- 8004088: 687b ldr r3, [r7, #4]
- 800408a: 641a str r2, [r3, #64] ; 0x40
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 800408c: 687b ldr r3, [r7, #4]
- 800408e: 693a ldr r2, [r7, #16]
- 8004090: 621a str r2, [r3, #32]
-}
- 8004092: bf00 nop
- 8004094: 371c adds r7, #28
- 8004096: 46bd mov sp, r7
- 8004098: f85d 7b04 ldr.w r7, [sp], #4
- 800409c: 4770 bx lr
- 800409e: bf00 nop
- 80040a0: feff8fff .word 0xfeff8fff
- 80040a4: 40010000 .word 0x40010000
- 80040a8: 40010400 .word 0x40010400
-
-080040ac <TIM_OC5_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 80040ac: b480 push {r7}
- 80040ae: b087 sub sp, #28
- 80040b0: af00 add r7, sp, #0
- 80040b2: 6078 str r0, [r7, #4]
- 80040b4: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
- 80040b6: 687b ldr r3, [r7, #4]
- 80040b8: 6a1b ldr r3, [r3, #32]
- 80040ba: f423 3280 bic.w r2, r3, #65536 ; 0x10000
- 80040be: 687b ldr r3, [r7, #4]
- 80040c0: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 80040c2: 687b ldr r3, [r7, #4]
- 80040c4: 6a1b ldr r3, [r3, #32]
- 80040c6: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 80040c8: 687b ldr r3, [r7, #4]
- 80040ca: 685b ldr r3, [r3, #4]
- 80040cc: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 80040ce: 687b ldr r3, [r7, #4]
- 80040d0: 6d5b ldr r3, [r3, #84] ; 0x54
- 80040d2: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- 80040d4: 68fa ldr r2, [r7, #12]
- 80040d6: 4b1b ldr r3, [pc, #108] ; (8004144 <TIM_OC5_SetConfig+0x98>)
- 80040d8: 4013 ands r3, r2
- 80040da: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 80040dc: 683b ldr r3, [r7, #0]
- 80040de: 681b ldr r3, [r3, #0]
- 80040e0: 68fa ldr r2, [r7, #12]
- 80040e2: 4313 orrs r3, r2
- 80040e4: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- 80040e6: 693b ldr r3, [r7, #16]
- 80040e8: f423 3300 bic.w r3, r3, #131072 ; 0x20000
- 80040ec: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16U);
- 80040ee: 683b ldr r3, [r7, #0]
- 80040f0: 689b ldr r3, [r3, #8]
- 80040f2: 041b lsls r3, r3, #16
- 80040f4: 693a ldr r2, [r7, #16]
- 80040f6: 4313 orrs r3, r2
- 80040f8: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80040fa: 687b ldr r3, [r7, #4]
- 80040fc: 4a12 ldr r2, [pc, #72] ; (8004148 <TIM_OC5_SetConfig+0x9c>)
- 80040fe: 4293 cmp r3, r2
- 8004100: d003 beq.n 800410a <TIM_OC5_SetConfig+0x5e>
- 8004102: 687b ldr r3, [r7, #4]
- 8004104: 4a11 ldr r2, [pc, #68] ; (800414c <TIM_OC5_SetConfig+0xa0>)
- 8004106: 4293 cmp r3, r2
- 8004108: d109 bne.n 800411e <TIM_OC5_SetConfig+0x72>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- 800410a: 697b ldr r3, [r7, #20]
- 800410c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8004110: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8U);
- 8004112: 683b ldr r3, [r7, #0]
- 8004114: 695b ldr r3, [r3, #20]
- 8004116: 021b lsls r3, r3, #8
- 8004118: 697a ldr r2, [r7, #20]
- 800411a: 4313 orrs r3, r2
- 800411c: 617b str r3, [r7, #20]
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 800411e: 687b ldr r3, [r7, #4]
- 8004120: 697a ldr r2, [r7, #20]
- 8004122: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 8004124: 687b ldr r3, [r7, #4]
- 8004126: 68fa ldr r2, [r7, #12]
- 8004128: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
- 800412a: 683b ldr r3, [r7, #0]
- 800412c: 685a ldr r2, [r3, #4]
- 800412e: 687b ldr r3, [r7, #4]
- 8004130: 659a str r2, [r3, #88] ; 0x58
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004132: 687b ldr r3, [r7, #4]
- 8004134: 693a ldr r2, [r7, #16]
- 8004136: 621a str r2, [r3, #32]
-}
- 8004138: bf00 nop
- 800413a: 371c adds r7, #28
- 800413c: 46bd mov sp, r7
- 800413e: f85d 7b04 ldr.w r7, [sp], #4
- 8004142: 4770 bx lr
- 8004144: fffeff8f .word 0xfffeff8f
- 8004148: 40010000 .word 0x40010000
- 800414c: 40010400 .word 0x40010400
-
-08004150 <TIM_OC6_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 8004150: b480 push {r7}
- 8004152: b087 sub sp, #28
- 8004154: af00 add r7, sp, #0
- 8004156: 6078 str r0, [r7, #4]
- 8004158: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
- 800415a: 687b ldr r3, [r7, #4]
- 800415c: 6a1b ldr r3, [r3, #32]
- 800415e: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
- 8004162: 687b ldr r3, [r7, #4]
- 8004164: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004166: 687b ldr r3, [r7, #4]
- 8004168: 6a1b ldr r3, [r3, #32]
- 800416a: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 800416c: 687b ldr r3, [r7, #4]
- 800416e: 685b ldr r3, [r3, #4]
- 8004170: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 8004172: 687b ldr r3, [r7, #4]
- 8004174: 6d5b ldr r3, [r3, #84] ; 0x54
- 8004176: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- 8004178: 68fa ldr r2, [r7, #12]
- 800417a: 4b1c ldr r3, [pc, #112] ; (80041ec <TIM_OC6_SetConfig+0x9c>)
- 800417c: 4013 ands r3, r2
- 800417e: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 8004180: 683b ldr r3, [r7, #0]
- 8004182: 681b ldr r3, [r3, #0]
- 8004184: 021b lsls r3, r3, #8
- 8004186: 68fa ldr r2, [r7, #12]
- 8004188: 4313 orrs r3, r2
- 800418a: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- 800418c: 693b ldr r3, [r7, #16]
- 800418e: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
- 8004192: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20U);
- 8004194: 683b ldr r3, [r7, #0]
- 8004196: 689b ldr r3, [r3, #8]
- 8004198: 051b lsls r3, r3, #20
- 800419a: 693a ldr r2, [r7, #16]
- 800419c: 4313 orrs r3, r2
- 800419e: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80041a0: 687b ldr r3, [r7, #4]
- 80041a2: 4a13 ldr r2, [pc, #76] ; (80041f0 <TIM_OC6_SetConfig+0xa0>)
- 80041a4: 4293 cmp r3, r2
- 80041a6: d003 beq.n 80041b0 <TIM_OC6_SetConfig+0x60>
- 80041a8: 687b ldr r3, [r7, #4]
- 80041aa: 4a12 ldr r2, [pc, #72] ; (80041f4 <TIM_OC6_SetConfig+0xa4>)
- 80041ac: 4293 cmp r3, r2
- 80041ae: d109 bne.n 80041c4 <TIM_OC6_SetConfig+0x74>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- 80041b0: 697b ldr r3, [r7, #20]
- 80041b2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80041b6: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10U);
- 80041b8: 683b ldr r3, [r7, #0]
- 80041ba: 695b ldr r3, [r3, #20]
- 80041bc: 029b lsls r3, r3, #10
- 80041be: 697a ldr r2, [r7, #20]
- 80041c0: 4313 orrs r3, r2
- 80041c2: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 80041c4: 687b ldr r3, [r7, #4]
- 80041c6: 697a ldr r2, [r7, #20]
- 80041c8: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 80041ca: 687b ldr r3, [r7, #4]
- 80041cc: 68fa ldr r2, [r7, #12]
- 80041ce: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
- 80041d0: 683b ldr r3, [r7, #0]
- 80041d2: 685a ldr r2, [r3, #4]
- 80041d4: 687b ldr r3, [r7, #4]
- 80041d6: 65da str r2, [r3, #92] ; 0x5c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 80041d8: 687b ldr r3, [r7, #4]
- 80041da: 693a ldr r2, [r7, #16]
- 80041dc: 621a str r2, [r3, #32]
-}
- 80041de: bf00 nop
- 80041e0: 371c adds r7, #28
- 80041e2: 46bd mov sp, r7
- 80041e4: f85d 7b04 ldr.w r7, [sp], #4
- 80041e8: 4770 bx lr
- 80041ea: bf00 nop
- 80041ec: feff8fff .word 0xfeff8fff
- 80041f0: 40010000 .word 0x40010000
- 80041f4: 40010400 .word 0x40010400
-
-080041f8 <TIM_TI1_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 80041f8: b480 push {r7}
- 80041fa: b087 sub sp, #28
- 80041fc: af00 add r7, sp, #0
- 80041fe: 60f8 str r0, [r7, #12]
- 8004200: 60b9 str r1, [r7, #8]
- 8004202: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- 8004204: 68fb ldr r3, [r7, #12]
- 8004206: 6a1b ldr r3, [r3, #32]
- 8004208: 617b str r3, [r7, #20]
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 800420a: 68fb ldr r3, [r7, #12]
- 800420c: 6a1b ldr r3, [r3, #32]
- 800420e: f023 0201 bic.w r2, r3, #1
- 8004212: 68fb ldr r3, [r7, #12]
- 8004214: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 8004216: 68fb ldr r3, [r7, #12]
- 8004218: 699b ldr r3, [r3, #24]
- 800421a: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 800421c: 693b ldr r3, [r7, #16]
- 800421e: f023 03f0 bic.w r3, r3, #240 ; 0xf0
- 8004222: 613b str r3, [r7, #16]
- tmpccmr1 |= (TIM_ICFilter << 4U);
- 8004224: 687b ldr r3, [r7, #4]
- 8004226: 011b lsls r3, r3, #4
- 8004228: 693a ldr r2, [r7, #16]
- 800422a: 4313 orrs r3, r2
- 800422c: 613b str r3, [r7, #16]
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 800422e: 697b ldr r3, [r7, #20]
- 8004230: f023 030a bic.w r3, r3, #10
- 8004234: 617b str r3, [r7, #20]
- tmpccer |= TIM_ICPolarity;
- 8004236: 697a ldr r2, [r7, #20]
- 8004238: 68bb ldr r3, [r7, #8]
- 800423a: 4313 orrs r3, r2
- 800423c: 617b str r3, [r7, #20]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- 800423e: 68fb ldr r3, [r7, #12]
- 8004240: 693a ldr r2, [r7, #16]
- 8004242: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 8004244: 68fb ldr r3, [r7, #12]
- 8004246: 697a ldr r2, [r7, #20]
- 8004248: 621a str r2, [r3, #32]
-}
- 800424a: bf00 nop
- 800424c: 371c adds r7, #28
- 800424e: 46bd mov sp, r7
- 8004250: f85d 7b04 ldr.w r7, [sp], #4
- 8004254: 4770 bx lr
-
-08004256 <TIM_TI2_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 8004256: b480 push {r7}
- 8004258: b087 sub sp, #28
- 800425a: af00 add r7, sp, #0
- 800425c: 60f8 str r0, [r7, #12]
- 800425e: 60b9 str r1, [r7, #8]
- 8004260: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 8004262: 68fb ldr r3, [r7, #12]
- 8004264: 6a1b ldr r3, [r3, #32]
- 8004266: f023 0210 bic.w r2, r3, #16
- 800426a: 68fb ldr r3, [r7, #12]
- 800426c: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 800426e: 68fb ldr r3, [r7, #12]
- 8004270: 699b ldr r3, [r3, #24]
- 8004272: 617b str r3, [r7, #20]
- tmpccer = TIMx->CCER;
- 8004274: 68fb ldr r3, [r7, #12]
- 8004276: 6a1b ldr r3, [r3, #32]
- 8004278: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 800427a: 697b ldr r3, [r7, #20]
- 800427c: f423 4370 bic.w r3, r3, #61440 ; 0xf000
- 8004280: 617b str r3, [r7, #20]
- tmpccmr1 |= (TIM_ICFilter << 12U);
- 8004282: 687b ldr r3, [r7, #4]
- 8004284: 031b lsls r3, r3, #12
- 8004286: 697a ldr r2, [r7, #20]
- 8004288: 4313 orrs r3, r2
- 800428a: 617b str r3, [r7, #20]
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 800428c: 693b ldr r3, [r7, #16]
- 800428e: f023 03a0 bic.w r3, r3, #160 ; 0xa0
- 8004292: 613b str r3, [r7, #16]
- tmpccer |= (TIM_ICPolarity << 4U);
- 8004294: 68bb ldr r3, [r7, #8]
- 8004296: 011b lsls r3, r3, #4
- 8004298: 693a ldr r2, [r7, #16]
- 800429a: 4313 orrs r3, r2
- 800429c: 613b str r3, [r7, #16]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- 800429e: 68fb ldr r3, [r7, #12]
- 80042a0: 697a ldr r2, [r7, #20]
- 80042a2: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 80042a4: 68fb ldr r3, [r7, #12]
- 80042a6: 693a ldr r2, [r7, #16]
- 80042a8: 621a str r2, [r3, #32]
-}
- 80042aa: bf00 nop
- 80042ac: 371c adds r7, #28
- 80042ae: 46bd mov sp, r7
- 80042b0: f85d 7b04 ldr.w r7, [sp], #4
- 80042b4: 4770 bx lr
-
-080042b6 <TIM_ITRx_SetConfig>:
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
- 80042b6: b480 push {r7}
- 80042b8: b085 sub sp, #20
- 80042ba: af00 add r7, sp, #0
- 80042bc: 6078 str r0, [r7, #4]
- 80042be: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- 80042c0: 687b ldr r3, [r7, #4]
- 80042c2: 689b ldr r3, [r3, #8]
- 80042c4: 60fb str r3, [r7, #12]
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- 80042c6: 68fb ldr r3, [r7, #12]
- 80042c8: f023 0370 bic.w r3, r3, #112 ; 0x70
- 80042cc: 60fb str r3, [r7, #12]
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 80042ce: 683a ldr r2, [r7, #0]
- 80042d0: 68fb ldr r3, [r7, #12]
- 80042d2: 4313 orrs r3, r2
- 80042d4: f043 0307 orr.w r3, r3, #7
- 80042d8: 60fb str r3, [r7, #12]
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 80042da: 687b ldr r3, [r7, #4]
- 80042dc: 68fa ldr r2, [r7, #12]
- 80042de: 609a str r2, [r3, #8]
-}
- 80042e0: bf00 nop
- 80042e2: 3714 adds r7, #20
- 80042e4: 46bd mov sp, r7
- 80042e6: f85d 7b04 ldr.w r7, [sp], #4
- 80042ea: 4770 bx lr
-
-080042ec <TIM_ETR_SetConfig>:
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- 80042ec: b480 push {r7}
- 80042ee: b087 sub sp, #28
- 80042f0: af00 add r7, sp, #0
- 80042f2: 60f8 str r0, [r7, #12]
- 80042f4: 60b9 str r1, [r7, #8]
- 80042f6: 607a str r2, [r7, #4]
- 80042f8: 603b str r3, [r7, #0]
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
- 80042fa: 68fb ldr r3, [r7, #12]
- 80042fc: 689b ldr r3, [r3, #8]
- 80042fe: 617b str r3, [r7, #20]
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8004300: 697b ldr r3, [r7, #20]
- 8004302: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8004306: 617b str r3, [r7, #20]
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 8004308: 683b ldr r3, [r7, #0]
- 800430a: 021a lsls r2, r3, #8
- 800430c: 687b ldr r3, [r7, #4]
- 800430e: 431a orrs r2, r3
- 8004310: 68bb ldr r3, [r7, #8]
- 8004312: 4313 orrs r3, r2
- 8004314: 697a ldr r2, [r7, #20]
- 8004316: 4313 orrs r3, r2
- 8004318: 617b str r3, [r7, #20]
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 800431a: 68fb ldr r3, [r7, #12]
- 800431c: 697a ldr r2, [r7, #20]
- 800431e: 609a str r2, [r3, #8]
-}
- 8004320: bf00 nop
- 8004322: 371c adds r7, #28
- 8004324: 46bd mov sp, r7
- 8004326: f85d 7b04 ldr.w r7, [sp], #4
- 800432a: 4770 bx lr
-
-0800432c <TIM_CCxChannelCmd>:
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- 800432c: b480 push {r7}
- 800432e: b087 sub sp, #28
- 8004330: af00 add r7, sp, #0
- 8004332: 60f8 str r0, [r7, #12]
- 8004334: 60b9 str r1, [r7, #8]
- 8004336: 607a str r2, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
- 8004338: 68bb ldr r3, [r7, #8]
- 800433a: f003 031f and.w r3, r3, #31
- 800433e: 2201 movs r2, #1
- 8004340: fa02 f303 lsl.w r3, r2, r3
- 8004344: 617b str r3, [r7, #20]
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
- 8004346: 68fb ldr r3, [r7, #12]
- 8004348: 6a1a ldr r2, [r3, #32]
- 800434a: 697b ldr r3, [r7, #20]
- 800434c: 43db mvns r3, r3
- 800434e: 401a ands r2, r3
- 8004350: 68fb ldr r3, [r7, #12]
- 8004352: 621a str r2, [r3, #32]
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
- 8004354: 68fb ldr r3, [r7, #12]
- 8004356: 6a1a ldr r2, [r3, #32]
- 8004358: 68bb ldr r3, [r7, #8]
- 800435a: f003 031f and.w r3, r3, #31
- 800435e: 6879 ldr r1, [r7, #4]
- 8004360: fa01 f303 lsl.w r3, r1, r3
- 8004364: 431a orrs r2, r3
- 8004366: 68fb ldr r3, [r7, #12]
- 8004368: 621a str r2, [r3, #32]
-}
- 800436a: bf00 nop
- 800436c: 371c adds r7, #28
- 800436e: 46bd mov sp, r7
- 8004370: f85d 7b04 ldr.w r7, [sp], #4
- 8004374: 4770 bx lr
- ...
-
-08004378 <HAL_TIMEx_MasterConfigSynchronization>:
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
-{
- 8004378: b480 push {r7}
- 800437a: b085 sub sp, #20
- 800437c: af00 add r7, sp, #0
- 800437e: 6078 str r0, [r7, #4]
- 8004380: 6039 str r1, [r7, #0]
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
- 8004382: 687b ldr r3, [r7, #4]
- 8004384: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8004388: 2b01 cmp r3, #1
- 800438a: d101 bne.n 8004390 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 800438c: 2302 movs r3, #2
- 800438e: e045 b.n 800441c <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 8004390: 687b ldr r3, [r7, #4]
- 8004392: 2201 movs r2, #1
- 8004394: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
- 8004398: 687b ldr r3, [r7, #4]
- 800439a: 2202 movs r2, #2
- 800439c: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
- 80043a0: 687b ldr r3, [r7, #4]
- 80043a2: 681b ldr r3, [r3, #0]
- 80043a4: 685b ldr r3, [r3, #4]
- 80043a6: 60fb str r3, [r7, #12]
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 80043a8: 687b ldr r3, [r7, #4]
- 80043aa: 681b ldr r3, [r3, #0]
- 80043ac: 689b ldr r3, [r3, #8]
- 80043ae: 60bb str r3, [r7, #8]
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 80043b0: 687b ldr r3, [r7, #4]
- 80043b2: 681b ldr r3, [r3, #0]
- 80043b4: 4a1c ldr r2, [pc, #112] ; (8004428 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 80043b6: 4293 cmp r3, r2
- 80043b8: d004 beq.n 80043c4 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 80043ba: 687b ldr r3, [r7, #4]
- 80043bc: 681b ldr r3, [r3, #0]
- 80043be: 4a1b ldr r2, [pc, #108] ; (800442c <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 80043c0: 4293 cmp r3, r2
- 80043c2: d108 bne.n 80043d6 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- 80043c4: 68fb ldr r3, [r7, #12]
- 80043c6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 80043ca: 60fb str r3, [r7, #12]
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 80043cc: 683b ldr r3, [r7, #0]
- 80043ce: 685b ldr r3, [r3, #4]
- 80043d0: 68fa ldr r2, [r7, #12]
- 80043d2: 4313 orrs r3, r2
- 80043d4: 60fb str r3, [r7, #12]
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- 80043d6: 68fb ldr r3, [r7, #12]
- 80043d8: f023 0370 bic.w r3, r3, #112 ; 0x70
- 80043dc: 60fb str r3, [r7, #12]
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 80043de: 683b ldr r3, [r7, #0]
- 80043e0: 681b ldr r3, [r3, #0]
- 80043e2: 68fa ldr r2, [r7, #12]
- 80043e4: 4313 orrs r3, r2
- 80043e6: 60fb str r3, [r7, #12]
-
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- 80043e8: 68bb ldr r3, [r7, #8]
- 80043ea: f023 0380 bic.w r3, r3, #128 ; 0x80
- 80043ee: 60bb str r3, [r7, #8]
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 80043f0: 683b ldr r3, [r7, #0]
- 80043f2: 689b ldr r3, [r3, #8]
- 80043f4: 68ba ldr r2, [r7, #8]
- 80043f6: 4313 orrs r3, r2
- 80043f8: 60bb str r3, [r7, #8]
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
- 80043fa: 687b ldr r3, [r7, #4]
- 80043fc: 681b ldr r3, [r3, #0]
- 80043fe: 68fa ldr r2, [r7, #12]
- 8004400: 605a str r2, [r3, #4]
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 8004402: 687b ldr r3, [r7, #4]
- 8004404: 681b ldr r3, [r3, #0]
- 8004406: 68ba ldr r2, [r7, #8]
- 8004408: 609a str r2, [r3, #8]
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
- 800440a: 687b ldr r3, [r7, #4]
- 800440c: 2201 movs r2, #1
- 800440e: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8004412: 687b ldr r3, [r7, #4]
- 8004414: 2200 movs r2, #0
- 8004416: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 800441a: 2300 movs r3, #0
-}
- 800441c: 4618 mov r0, r3
- 800441e: 3714 adds r7, #20
- 8004420: 46bd mov sp, r7
- 8004422: f85d 7b04 ldr.w r7, [sp], #4
- 8004426: 4770 bx lr
- 8004428: 40010000 .word 0x40010000
- 800442c: 40010400 .word 0x40010400
-
-08004430 <HAL_TIMEx_CommutCallback>:
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- 8004430: b480 push {r7}
- 8004432: b083 sub sp, #12
- 8004434: af00 add r7, sp, #0
- 8004436: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
- 8004438: bf00 nop
- 800443a: 370c adds r7, #12
- 800443c: 46bd mov sp, r7
- 800443e: f85d 7b04 ldr.w r7, [sp], #4
- 8004442: 4770 bx lr
-
-08004444 <HAL_TIMEx_BreakCallback>:
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- 8004444: b480 push {r7}
- 8004446: b083 sub sp, #12
- 8004448: af00 add r7, sp, #0
- 800444a: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
- 800444c: bf00 nop
- 800444e: 370c adds r7, #12
- 8004450: 46bd mov sp, r7
- 8004452: f85d 7b04 ldr.w r7, [sp], #4
- 8004456: 4770 bx lr
-
-08004458 <HAL_TIMEx_Break2Callback>:
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- 8004458: b480 push {r7}
- 800445a: b083 sub sp, #12
- 800445c: af00 add r7, sp, #0
- 800445e: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
- 8004460: bf00 nop
- 8004462: 370c adds r7, #12
- 8004464: 46bd mov sp, r7
- 8004466: f85d 7b04 ldr.w r7, [sp], #4
- 800446a: 4770 bx lr
-
-0800446c <HAL_UART_Init>:
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- 800446c: b580 push {r7, lr}
- 800446e: b082 sub sp, #8
- 8004470: af00 add r7, sp, #0
- 8004472: 6078 str r0, [r7, #4]
- /* Check the UART handle allocation */
- if (huart == NULL)
- 8004474: 687b ldr r3, [r7, #4]
- 8004476: 2b00 cmp r3, #0
- 8004478: d101 bne.n 800447e <HAL_UART_Init+0x12>
- {
- return HAL_ERROR;
- 800447a: 2301 movs r3, #1
- 800447c: e040 b.n 8004500 <HAL_UART_Init+0x94>
- {
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
- }
-
- if (huart->gState == HAL_UART_STATE_RESET)
- 800447e: 687b ldr r3, [r7, #4]
- 8004480: 6f5b ldr r3, [r3, #116] ; 0x74
- 8004482: 2b00 cmp r3, #0
- 8004484: d106 bne.n 8004494 <HAL_UART_Init+0x28>
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- 8004486: 687b ldr r3, [r7, #4]
- 8004488: 2200 movs r2, #0
- 800448a: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- 800448e: 6878 ldr r0, [r7, #4]
- 8004490: f7fd fa38 bl 8001904 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
- 8004494: 687b ldr r3, [r7, #4]
- 8004496: 2224 movs r2, #36 ; 0x24
- 8004498: 675a str r2, [r3, #116] ; 0x74
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
- 800449a: 687b ldr r3, [r7, #4]
- 800449c: 681b ldr r3, [r3, #0]
- 800449e: 681a ldr r2, [r3, #0]
- 80044a0: 687b ldr r3, [r7, #4]
- 80044a2: 681b ldr r3, [r3, #0]
- 80044a4: f022 0201 bic.w r2, r2, #1
- 80044a8: 601a str r2, [r3, #0]
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- 80044aa: 6878 ldr r0, [r7, #4]
- 80044ac: f000 fa90 bl 80049d0 <UART_SetConfig>
- 80044b0: 4603 mov r3, r0
- 80044b2: 2b01 cmp r3, #1
- 80044b4: d101 bne.n 80044ba <HAL_UART_Init+0x4e>
- {
- return HAL_ERROR;
- 80044b6: 2301 movs r3, #1
- 80044b8: e022 b.n 8004500 <HAL_UART_Init+0x94>
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 80044ba: 687b ldr r3, [r7, #4]
- 80044bc: 6a5b ldr r3, [r3, #36] ; 0x24
- 80044be: 2b00 cmp r3, #0
- 80044c0: d002 beq.n 80044c8 <HAL_UART_Init+0x5c>
- {
- UART_AdvFeatureConfig(huart);
- 80044c2: 6878 ldr r0, [r7, #4]
- 80044c4: f000 fd28 bl 8004f18 <UART_AdvFeatureConfig>
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 80044c8: 687b ldr r3, [r7, #4]
- 80044ca: 681b ldr r3, [r3, #0]
- 80044cc: 685a ldr r2, [r3, #4]
- 80044ce: 687b ldr r3, [r7, #4]
- 80044d0: 681b ldr r3, [r3, #0]
- 80044d2: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 80044d6: 605a str r2, [r3, #4]
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 80044d8: 687b ldr r3, [r7, #4]
- 80044da: 681b ldr r3, [r3, #0]
- 80044dc: 689a ldr r2, [r3, #8]
- 80044de: 687b ldr r3, [r7, #4]
- 80044e0: 681b ldr r3, [r3, #0]
- 80044e2: f022 022a bic.w r2, r2, #42 ; 0x2a
- 80044e6: 609a str r2, [r3, #8]
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
- 80044e8: 687b ldr r3, [r7, #4]
- 80044ea: 681b ldr r3, [r3, #0]
- 80044ec: 681a ldr r2, [r3, #0]
- 80044ee: 687b ldr r3, [r7, #4]
- 80044f0: 681b ldr r3, [r3, #0]
- 80044f2: f042 0201 orr.w r2, r2, #1
- 80044f6: 601a str r2, [r3, #0]
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
- 80044f8: 6878 ldr r0, [r7, #4]
- 80044fa: f000 fdaf bl 800505c <UART_CheckIdleState>
- 80044fe: 4603 mov r3, r0
-}
- 8004500: 4618 mov r0, r3
- 8004502: 3708 adds r7, #8
- 8004504: 46bd mov sp, r7
- 8004506: bd80 pop {r7, pc}
-
-08004508 <HAL_UART_Transmit>:
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- 8004508: b580 push {r7, lr}
- 800450a: b08a sub sp, #40 ; 0x28
- 800450c: af02 add r7, sp, #8
- 800450e: 60f8 str r0, [r7, #12]
- 8004510: 60b9 str r1, [r7, #8]
- 8004512: 603b str r3, [r7, #0]
- 8004514: 4613 mov r3, r2
- 8004516: 80fb strh r3, [r7, #6]
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
- uint32_t tickstart;
-
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY)
- 8004518: 68fb ldr r3, [r7, #12]
- 800451a: 6f5b ldr r3, [r3, #116] ; 0x74
- 800451c: 2b20 cmp r3, #32
- 800451e: d17f bne.n 8004620 <HAL_UART_Transmit+0x118>
- {
- if ((pData == NULL) || (Size == 0U))
- 8004520: 68bb ldr r3, [r7, #8]
- 8004522: 2b00 cmp r3, #0
- 8004524: d002 beq.n 800452c <HAL_UART_Transmit+0x24>
- 8004526: 88fb ldrh r3, [r7, #6]
- 8004528: 2b00 cmp r3, #0
- 800452a: d101 bne.n 8004530 <HAL_UART_Transmit+0x28>
- {
- return HAL_ERROR;
- 800452c: 2301 movs r3, #1
- 800452e: e078 b.n 8004622 <HAL_UART_Transmit+0x11a>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8004530: 68fb ldr r3, [r7, #12]
- 8004532: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 8004536: 2b01 cmp r3, #1
- 8004538: d101 bne.n 800453e <HAL_UART_Transmit+0x36>
- 800453a: 2302 movs r3, #2
- 800453c: e071 b.n 8004622 <HAL_UART_Transmit+0x11a>
- 800453e: 68fb ldr r3, [r7, #12]
- 8004540: 2201 movs r2, #1
- 8004542: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004546: 68fb ldr r3, [r7, #12]
- 8004548: 2200 movs r2, #0
- 800454a: 67da str r2, [r3, #124] ; 0x7c
- huart->gState = HAL_UART_STATE_BUSY_TX;
- 800454c: 68fb ldr r3, [r7, #12]
- 800454e: 2221 movs r2, #33 ; 0x21
- 8004550: 675a str r2, [r3, #116] ; 0x74
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 8004552: f7fd fb1f bl 8001b94 <HAL_GetTick>
- 8004556: 6178 str r0, [r7, #20]
-
- huart->TxXferSize = Size;
- 8004558: 68fb ldr r3, [r7, #12]
- 800455a: 88fa ldrh r2, [r7, #6]
- 800455c: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
- huart->TxXferCount = Size;
- 8004560: 68fb ldr r3, [r7, #12]
- 8004562: 88fa ldrh r2, [r7, #6]
- 8004564: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-
- /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8004568: 68fb ldr r3, [r7, #12]
- 800456a: 689b ldr r3, [r3, #8]
- 800456c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004570: d108 bne.n 8004584 <HAL_UART_Transmit+0x7c>
- 8004572: 68fb ldr r3, [r7, #12]
- 8004574: 691b ldr r3, [r3, #16]
- 8004576: 2b00 cmp r3, #0
- 8004578: d104 bne.n 8004584 <HAL_UART_Transmit+0x7c>
- {
- pdata8bits = NULL;
- 800457a: 2300 movs r3, #0
- 800457c: 61fb str r3, [r7, #28]
- pdata16bits = (uint16_t *) pData;
- 800457e: 68bb ldr r3, [r7, #8]
- 8004580: 61bb str r3, [r7, #24]
- 8004582: e003 b.n 800458c <HAL_UART_Transmit+0x84>
- }
- else
- {
- pdata8bits = pData;
- 8004584: 68bb ldr r3, [r7, #8]
- 8004586: 61fb str r3, [r7, #28]
- pdata16bits = NULL;
- 8004588: 2300 movs r3, #0
- 800458a: 61bb str r3, [r7, #24]
- }
-
- while (huart->TxXferCount > 0U)
- 800458c: e02c b.n 80045e8 <HAL_UART_Transmit+0xe0>
- {
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 800458e: 683b ldr r3, [r7, #0]
- 8004590: 9300 str r3, [sp, #0]
- 8004592: 697b ldr r3, [r7, #20]
- 8004594: 2200 movs r2, #0
- 8004596: 2180 movs r1, #128 ; 0x80
- 8004598: 68f8 ldr r0, [r7, #12]
- 800459a: f000 fd8e bl 80050ba <UART_WaitOnFlagUntilTimeout>
- 800459e: 4603 mov r3, r0
- 80045a0: 2b00 cmp r3, #0
- 80045a2: d001 beq.n 80045a8 <HAL_UART_Transmit+0xa0>
- {
- return HAL_TIMEOUT;
- 80045a4: 2303 movs r3, #3
- 80045a6: e03c b.n 8004622 <HAL_UART_Transmit+0x11a>
- }
- if (pdata8bits == NULL)
- 80045a8: 69fb ldr r3, [r7, #28]
- 80045aa: 2b00 cmp r3, #0
- 80045ac: d10b bne.n 80045c6 <HAL_UART_Transmit+0xbe>
- {
- huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 80045ae: 69bb ldr r3, [r7, #24]
- 80045b0: 881b ldrh r3, [r3, #0]
- 80045b2: 461a mov r2, r3
- 80045b4: 68fb ldr r3, [r7, #12]
- 80045b6: 681b ldr r3, [r3, #0]
- 80045b8: f3c2 0208 ubfx r2, r2, #0, #9
- 80045bc: 629a str r2, [r3, #40] ; 0x28
- pdata16bits++;
- 80045be: 69bb ldr r3, [r7, #24]
- 80045c0: 3302 adds r3, #2
- 80045c2: 61bb str r3, [r7, #24]
- 80045c4: e007 b.n 80045d6 <HAL_UART_Transmit+0xce>
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 80045c6: 69fb ldr r3, [r7, #28]
- 80045c8: 781a ldrb r2, [r3, #0]
- 80045ca: 68fb ldr r3, [r7, #12]
- 80045cc: 681b ldr r3, [r3, #0]
- 80045ce: 629a str r2, [r3, #40] ; 0x28
- pdata8bits++;
- 80045d0: 69fb ldr r3, [r7, #28]
- 80045d2: 3301 adds r3, #1
- 80045d4: 61fb str r3, [r7, #28]
- }
- huart->TxXferCount--;
- 80045d6: 68fb ldr r3, [r7, #12]
- 80045d8: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 80045dc: b29b uxth r3, r3
- 80045de: 3b01 subs r3, #1
- 80045e0: b29a uxth r2, r3
- 80045e2: 68fb ldr r3, [r7, #12]
- 80045e4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
- while (huart->TxXferCount > 0U)
- 80045e8: 68fb ldr r3, [r7, #12]
- 80045ea: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 80045ee: b29b uxth r3, r3
- 80045f0: 2b00 cmp r3, #0
- 80045f2: d1cc bne.n 800458e <HAL_UART_Transmit+0x86>
- }
-
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 80045f4: 683b ldr r3, [r7, #0]
- 80045f6: 9300 str r3, [sp, #0]
- 80045f8: 697b ldr r3, [r7, #20]
- 80045fa: 2200 movs r2, #0
- 80045fc: 2140 movs r1, #64 ; 0x40
- 80045fe: 68f8 ldr r0, [r7, #12]
- 8004600: f000 fd5b bl 80050ba <UART_WaitOnFlagUntilTimeout>
- 8004604: 4603 mov r3, r0
- 8004606: 2b00 cmp r3, #0
- 8004608: d001 beq.n 800460e <HAL_UART_Transmit+0x106>
- {
- return HAL_TIMEOUT;
- 800460a: 2303 movs r3, #3
- 800460c: e009 b.n 8004622 <HAL_UART_Transmit+0x11a>
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 800460e: 68fb ldr r3, [r7, #12]
- 8004610: 2220 movs r2, #32
- 8004612: 675a str r2, [r3, #116] ; 0x74
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8004614: 68fb ldr r3, [r7, #12]
- 8004616: 2200 movs r2, #0
- 8004618: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 800461c: 2300 movs r3, #0
- 800461e: e000 b.n 8004622 <HAL_UART_Transmit+0x11a>
- }
- else
- {
- return HAL_BUSY;
- 8004620: 2302 movs r3, #2
- }
-}
- 8004622: 4618 mov r0, r3
- 8004624: 3720 adds r7, #32
- 8004626: 46bd mov sp, r7
- 8004628: bd80 pop {r7, pc}
- ...
-
-0800462c <HAL_UART_Receive_IT>:
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- 800462c: b480 push {r7}
- 800462e: b085 sub sp, #20
- 8004630: af00 add r7, sp, #0
- 8004632: 60f8 str r0, [r7, #12]
- 8004634: 60b9 str r1, [r7, #8]
- 8004636: 4613 mov r3, r2
- 8004638: 80fb strh r3, [r7, #6]
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY)
- 800463a: 68fb ldr r3, [r7, #12]
- 800463c: 6f9b ldr r3, [r3, #120] ; 0x78
- 800463e: 2b20 cmp r3, #32
- 8004640: f040 808a bne.w 8004758 <HAL_UART_Receive_IT+0x12c>
- {
- if ((pData == NULL) || (Size == 0U))
- 8004644: 68bb ldr r3, [r7, #8]
- 8004646: 2b00 cmp r3, #0
- 8004648: d002 beq.n 8004650 <HAL_UART_Receive_IT+0x24>
- 800464a: 88fb ldrh r3, [r7, #6]
- 800464c: 2b00 cmp r3, #0
- 800464e: d101 bne.n 8004654 <HAL_UART_Receive_IT+0x28>
- {
- return HAL_ERROR;
- 8004650: 2301 movs r3, #1
- 8004652: e082 b.n 800475a <HAL_UART_Receive_IT+0x12e>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8004654: 68fb ldr r3, [r7, #12]
- 8004656: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 800465a: 2b01 cmp r3, #1
- 800465c: d101 bne.n 8004662 <HAL_UART_Receive_IT+0x36>
- 800465e: 2302 movs r3, #2
- 8004660: e07b b.n 800475a <HAL_UART_Receive_IT+0x12e>
- 8004662: 68fb ldr r3, [r7, #12]
- 8004664: 2201 movs r2, #1
- 8004666: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->pRxBuffPtr = pData;
- 800466a: 68fb ldr r3, [r7, #12]
- 800466c: 68ba ldr r2, [r7, #8]
- 800466e: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferSize = Size;
- 8004670: 68fb ldr r3, [r7, #12]
- 8004672: 88fa ldrh r2, [r7, #6]
- 8004674: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
- huart->RxXferCount = Size;
- 8004678: 68fb ldr r3, [r7, #12]
- 800467a: 88fa ldrh r2, [r7, #6]
- 800467c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->RxISR = NULL;
- 8004680: 68fb ldr r3, [r7, #12]
- 8004682: 2200 movs r2, #0
- 8004684: 661a str r2, [r3, #96] ; 0x60
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- 8004686: 68fb ldr r3, [r7, #12]
- 8004688: 689b ldr r3, [r3, #8]
- 800468a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 800468e: d10e bne.n 80046ae <HAL_UART_Receive_IT+0x82>
- 8004690: 68fb ldr r3, [r7, #12]
- 8004692: 691b ldr r3, [r3, #16]
- 8004694: 2b00 cmp r3, #0
- 8004696: d105 bne.n 80046a4 <HAL_UART_Receive_IT+0x78>
- 8004698: 68fb ldr r3, [r7, #12]
- 800469a: f240 12ff movw r2, #511 ; 0x1ff
- 800469e: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80046a2: e02d b.n 8004700 <HAL_UART_Receive_IT+0xd4>
- 80046a4: 68fb ldr r3, [r7, #12]
- 80046a6: 22ff movs r2, #255 ; 0xff
- 80046a8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80046ac: e028 b.n 8004700 <HAL_UART_Receive_IT+0xd4>
- 80046ae: 68fb ldr r3, [r7, #12]
- 80046b0: 689b ldr r3, [r3, #8]
- 80046b2: 2b00 cmp r3, #0
- 80046b4: d10d bne.n 80046d2 <HAL_UART_Receive_IT+0xa6>
- 80046b6: 68fb ldr r3, [r7, #12]
- 80046b8: 691b ldr r3, [r3, #16]
- 80046ba: 2b00 cmp r3, #0
- 80046bc: d104 bne.n 80046c8 <HAL_UART_Receive_IT+0x9c>
- 80046be: 68fb ldr r3, [r7, #12]
- 80046c0: 22ff movs r2, #255 ; 0xff
- 80046c2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80046c6: e01b b.n 8004700 <HAL_UART_Receive_IT+0xd4>
- 80046c8: 68fb ldr r3, [r7, #12]
- 80046ca: 227f movs r2, #127 ; 0x7f
- 80046cc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80046d0: e016 b.n 8004700 <HAL_UART_Receive_IT+0xd4>
- 80046d2: 68fb ldr r3, [r7, #12]
- 80046d4: 689b ldr r3, [r3, #8]
- 80046d6: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
- 80046da: d10d bne.n 80046f8 <HAL_UART_Receive_IT+0xcc>
- 80046dc: 68fb ldr r3, [r7, #12]
- 80046de: 691b ldr r3, [r3, #16]
- 80046e0: 2b00 cmp r3, #0
- 80046e2: d104 bne.n 80046ee <HAL_UART_Receive_IT+0xc2>
- 80046e4: 68fb ldr r3, [r7, #12]
- 80046e6: 227f movs r2, #127 ; 0x7f
- 80046e8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80046ec: e008 b.n 8004700 <HAL_UART_Receive_IT+0xd4>
- 80046ee: 68fb ldr r3, [r7, #12]
- 80046f0: 223f movs r2, #63 ; 0x3f
- 80046f2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80046f6: e003 b.n 8004700 <HAL_UART_Receive_IT+0xd4>
- 80046f8: 68fb ldr r3, [r7, #12]
- 80046fa: 2200 movs r2, #0
- 80046fc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004700: 68fb ldr r3, [r7, #12]
- 8004702: 2200 movs r2, #0
- 8004704: 67da str r2, [r3, #124] ; 0x7c
- huart->RxState = HAL_UART_STATE_BUSY_RX;
- 8004706: 68fb ldr r3, [r7, #12]
- 8004708: 2222 movs r2, #34 ; 0x22
- 800470a: 679a str r2, [r3, #120] ; 0x78
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800470c: 68fb ldr r3, [r7, #12]
- 800470e: 681b ldr r3, [r3, #0]
- 8004710: 689a ldr r2, [r3, #8]
- 8004712: 68fb ldr r3, [r7, #12]
- 8004714: 681b ldr r3, [r3, #0]
- 8004716: f042 0201 orr.w r2, r2, #1
- 800471a: 609a str r2, [r3, #8]
-
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 800471c: 68fb ldr r3, [r7, #12]
- 800471e: 689b ldr r3, [r3, #8]
- 8004720: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004724: d107 bne.n 8004736 <HAL_UART_Receive_IT+0x10a>
- 8004726: 68fb ldr r3, [r7, #12]
- 8004728: 691b ldr r3, [r3, #16]
- 800472a: 2b00 cmp r3, #0
- 800472c: d103 bne.n 8004736 <HAL_UART_Receive_IT+0x10a>
- {
- huart->RxISR = UART_RxISR_16BIT;
- 800472e: 68fb ldr r3, [r7, #12]
- 8004730: 4a0d ldr r2, [pc, #52] ; (8004768 <HAL_UART_Receive_IT+0x13c>)
- 8004732: 661a str r2, [r3, #96] ; 0x60
- 8004734: e002 b.n 800473c <HAL_UART_Receive_IT+0x110>
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- 8004736: 68fb ldr r3, [r7, #12]
- 8004738: 4a0c ldr r2, [pc, #48] ; (800476c <HAL_UART_Receive_IT+0x140>)
- 800473a: 661a str r2, [r3, #96] ; 0x60
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 800473c: 68fb ldr r3, [r7, #12]
- 800473e: 2200 movs r2, #0
- 8004740: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- 8004744: 68fb ldr r3, [r7, #12]
- 8004746: 681b ldr r3, [r3, #0]
- 8004748: 681a ldr r2, [r3, #0]
- 800474a: 68fb ldr r3, [r7, #12]
- 800474c: 681b ldr r3, [r3, #0]
- 800474e: f442 7290 orr.w r2, r2, #288 ; 0x120
- 8004752: 601a str r2, [r3, #0]
-
- return HAL_OK;
- 8004754: 2300 movs r3, #0
- 8004756: e000 b.n 800475a <HAL_UART_Receive_IT+0x12e>
- }
- else
- {
- return HAL_BUSY;
- 8004758: 2302 movs r3, #2
- }
-}
- 800475a: 4618 mov r0, r3
- 800475c: 3714 adds r7, #20
- 800475e: 46bd mov sp, r7
- 8004760: f85d 7b04 ldr.w r7, [sp], #4
- 8004764: 4770 bx lr
- 8004766: bf00 nop
- 8004768: 0800528f .word 0x0800528f
- 800476c: 080051e9 .word 0x080051e9
-
-08004770 <HAL_UART_IRQHandler>:
- * @brief Handle UART interrupt request.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- 8004770: b580 push {r7, lr}
- 8004772: b088 sub sp, #32
- 8004774: af00 add r7, sp, #0
- 8004776: 6078 str r0, [r7, #4]
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- 8004778: 687b ldr r3, [r7, #4]
- 800477a: 681b ldr r3, [r3, #0]
- 800477c: 69db ldr r3, [r3, #28]
- 800477e: 61fb str r3, [r7, #28]
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- 8004780: 687b ldr r3, [r7, #4]
- 8004782: 681b ldr r3, [r3, #0]
- 8004784: 681b ldr r3, [r3, #0]
- 8004786: 61bb str r3, [r7, #24]
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- 8004788: 687b ldr r3, [r7, #4]
- 800478a: 681b ldr r3, [r3, #0]
- 800478c: 689b ldr r3, [r3, #8]
- 800478e: 617b str r3, [r7, #20]
-
- uint32_t errorflags;
- uint32_t errorcode;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- 8004790: 69fb ldr r3, [r7, #28]
- 8004792: f003 030f and.w r3, r3, #15
- 8004796: 613b str r3, [r7, #16]
- if (errorflags == 0U)
- 8004798: 693b ldr r3, [r7, #16]
- 800479a: 2b00 cmp r3, #0
- 800479c: d113 bne.n 80047c6 <HAL_UART_IRQHandler+0x56>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 800479e: 69fb ldr r3, [r7, #28]
- 80047a0: f003 0320 and.w r3, r3, #32
- 80047a4: 2b00 cmp r3, #0
- 80047a6: d00e beq.n 80047c6 <HAL_UART_IRQHandler+0x56>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 80047a8: 69bb ldr r3, [r7, #24]
- 80047aa: f003 0320 and.w r3, r3, #32
- 80047ae: 2b00 cmp r3, #0
- 80047b0: d009 beq.n 80047c6 <HAL_UART_IRQHandler+0x56>
- {
- if (huart->RxISR != NULL)
- 80047b2: 687b ldr r3, [r7, #4]
- 80047b4: 6e1b ldr r3, [r3, #96] ; 0x60
- 80047b6: 2b00 cmp r3, #0
- 80047b8: f000 80eb beq.w 8004992 <HAL_UART_IRQHandler+0x222>
- {
- huart->RxISR(huart);
- 80047bc: 687b ldr r3, [r7, #4]
- 80047be: 6e1b ldr r3, [r3, #96] ; 0x60
- 80047c0: 6878 ldr r0, [r7, #4]
- 80047c2: 4798 blx r3
- }
- return;
- 80047c4: e0e5 b.n 8004992 <HAL_UART_IRQHandler+0x222>
- }
- }
-
- /* If some errors occur */
- if ((errorflags != 0U)
- 80047c6: 693b ldr r3, [r7, #16]
- 80047c8: 2b00 cmp r3, #0
- 80047ca: f000 80c0 beq.w 800494e <HAL_UART_IRQHandler+0x1de>
- && (((cr3its & USART_CR3_EIE) != 0U)
- 80047ce: 697b ldr r3, [r7, #20]
- 80047d0: f003 0301 and.w r3, r3, #1
- 80047d4: 2b00 cmp r3, #0
- 80047d6: d105 bne.n 80047e4 <HAL_UART_IRQHandler+0x74>
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
- 80047d8: 69bb ldr r3, [r7, #24]
- 80047da: f403 7390 and.w r3, r3, #288 ; 0x120
- 80047de: 2b00 cmp r3, #0
- 80047e0: f000 80b5 beq.w 800494e <HAL_UART_IRQHandler+0x1de>
- {
- /* UART parity error interrupt occurred -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
- 80047e4: 69fb ldr r3, [r7, #28]
- 80047e6: f003 0301 and.w r3, r3, #1
- 80047ea: 2b00 cmp r3, #0
- 80047ec: d00e beq.n 800480c <HAL_UART_IRQHandler+0x9c>
- 80047ee: 69bb ldr r3, [r7, #24]
- 80047f0: f403 7380 and.w r3, r3, #256 ; 0x100
- 80047f4: 2b00 cmp r3, #0
- 80047f6: d009 beq.n 800480c <HAL_UART_IRQHandler+0x9c>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
- 80047f8: 687b ldr r3, [r7, #4]
- 80047fa: 681b ldr r3, [r3, #0]
- 80047fc: 2201 movs r2, #1
- 80047fe: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- 8004800: 687b ldr r3, [r7, #4]
- 8004802: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004804: f043 0201 orr.w r2, r3, #1
- 8004808: 687b ldr r3, [r7, #4]
- 800480a: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 800480c: 69fb ldr r3, [r7, #28]
- 800480e: f003 0302 and.w r3, r3, #2
- 8004812: 2b00 cmp r3, #0
- 8004814: d00e beq.n 8004834 <HAL_UART_IRQHandler+0xc4>
- 8004816: 697b ldr r3, [r7, #20]
- 8004818: f003 0301 and.w r3, r3, #1
- 800481c: 2b00 cmp r3, #0
- 800481e: d009 beq.n 8004834 <HAL_UART_IRQHandler+0xc4>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
- 8004820: 687b ldr r3, [r7, #4]
- 8004822: 681b ldr r3, [r3, #0]
- 8004824: 2202 movs r2, #2
- 8004826: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- 8004828: 687b ldr r3, [r7, #4]
- 800482a: 6fdb ldr r3, [r3, #124] ; 0x7c
- 800482c: f043 0204 orr.w r2, r3, #4
- 8004830: 687b ldr r3, [r7, #4]
- 8004832: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004834: 69fb ldr r3, [r7, #28]
- 8004836: f003 0304 and.w r3, r3, #4
- 800483a: 2b00 cmp r3, #0
- 800483c: d00e beq.n 800485c <HAL_UART_IRQHandler+0xec>
- 800483e: 697b ldr r3, [r7, #20]
- 8004840: f003 0301 and.w r3, r3, #1
- 8004844: 2b00 cmp r3, #0
- 8004846: d009 beq.n 800485c <HAL_UART_IRQHandler+0xec>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
- 8004848: 687b ldr r3, [r7, #4]
- 800484a: 681b ldr r3, [r3, #0]
- 800484c: 2204 movs r2, #4
- 800484e: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- 8004850: 687b ldr r3, [r7, #4]
- 8004852: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004854: f043 0202 orr.w r2, r3, #2
- 8004858: 687b ldr r3, [r7, #4]
- 800485a: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if (((isrflags & USART_ISR_ORE) != 0U)
- 800485c: 69fb ldr r3, [r7, #28]
- 800485e: f003 0308 and.w r3, r3, #8
- 8004862: 2b00 cmp r3, #0
- 8004864: d013 beq.n 800488e <HAL_UART_IRQHandler+0x11e>
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8004866: 69bb ldr r3, [r7, #24]
- 8004868: f003 0320 and.w r3, r3, #32
- 800486c: 2b00 cmp r3, #0
- 800486e: d104 bne.n 800487a <HAL_UART_IRQHandler+0x10a>
- ((cr3its & USART_CR3_EIE) != 0U)))
- 8004870: 697b ldr r3, [r7, #20]
- 8004872: f003 0301 and.w r3, r3, #1
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8004876: 2b00 cmp r3, #0
- 8004878: d009 beq.n 800488e <HAL_UART_IRQHandler+0x11e>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 800487a: 687b ldr r3, [r7, #4]
- 800487c: 681b ldr r3, [r3, #0]
- 800487e: 2208 movs r2, #8
- 8004880: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 8004882: 687b ldr r3, [r7, #4]
- 8004884: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004886: f043 0208 orr.w r2, r3, #8
- 800488a: 687b ldr r3, [r7, #4]
- 800488c: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 800488e: 687b ldr r3, [r7, #4]
- 8004890: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004892: 2b00 cmp r3, #0
- 8004894: d07f beq.n 8004996 <HAL_UART_IRQHandler+0x226>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 8004896: 69fb ldr r3, [r7, #28]
- 8004898: f003 0320 and.w r3, r3, #32
- 800489c: 2b00 cmp r3, #0
- 800489e: d00c beq.n 80048ba <HAL_UART_IRQHandler+0x14a>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 80048a0: 69bb ldr r3, [r7, #24]
- 80048a2: f003 0320 and.w r3, r3, #32
- 80048a6: 2b00 cmp r3, #0
- 80048a8: d007 beq.n 80048ba <HAL_UART_IRQHandler+0x14a>
- {
- if (huart->RxISR != NULL)
- 80048aa: 687b ldr r3, [r7, #4]
- 80048ac: 6e1b ldr r3, [r3, #96] ; 0x60
- 80048ae: 2b00 cmp r3, #0
- 80048b0: d003 beq.n 80048ba <HAL_UART_IRQHandler+0x14a>
- {
- huart->RxISR(huart);
- 80048b2: 687b ldr r3, [r7, #4]
- 80048b4: 6e1b ldr r3, [r3, #96] ; 0x60
- 80048b6: 6878 ldr r0, [r7, #4]
- 80048b8: 4798 blx r3
- }
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- errorcode = huart->ErrorCode;
- 80048ba: 687b ldr r3, [r7, #4]
- 80048bc: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80048be: 60fb str r3, [r7, #12]
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 80048c0: 687b ldr r3, [r7, #4]
- 80048c2: 681b ldr r3, [r3, #0]
- 80048c4: 689b ldr r3, [r3, #8]
- 80048c6: f003 0340 and.w r3, r3, #64 ; 0x40
- 80048ca: 2b40 cmp r3, #64 ; 0x40
- 80048cc: d004 beq.n 80048d8 <HAL_UART_IRQHandler+0x168>
- ((errorcode & HAL_UART_ERROR_ORE) != 0U))
- 80048ce: 68fb ldr r3, [r7, #12]
- 80048d0: f003 0308 and.w r3, r3, #8
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 80048d4: 2b00 cmp r3, #0
- 80048d6: d031 beq.n 800493c <HAL_UART_IRQHandler+0x1cc>
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
- 80048d8: 6878 ldr r0, [r7, #4]
- 80048da: f000 fc36 bl 800514a <UART_EndRxTransfer>
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80048de: 687b ldr r3, [r7, #4]
- 80048e0: 681b ldr r3, [r3, #0]
- 80048e2: 689b ldr r3, [r3, #8]
- 80048e4: f003 0340 and.w r3, r3, #64 ; 0x40
- 80048e8: 2b40 cmp r3, #64 ; 0x40
- 80048ea: d123 bne.n 8004934 <HAL_UART_IRQHandler+0x1c4>
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 80048ec: 687b ldr r3, [r7, #4]
- 80048ee: 681b ldr r3, [r3, #0]
- 80048f0: 689a ldr r2, [r3, #8]
- 80048f2: 687b ldr r3, [r7, #4]
- 80048f4: 681b ldr r3, [r3, #0]
- 80048f6: f022 0240 bic.w r2, r2, #64 ; 0x40
- 80048fa: 609a str r2, [r3, #8]
-
- /* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL)
- 80048fc: 687b ldr r3, [r7, #4]
- 80048fe: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004900: 2b00 cmp r3, #0
- 8004902: d013 beq.n 800492c <HAL_UART_IRQHandler+0x1bc>
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8004904: 687b ldr r3, [r7, #4]
- 8004906: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004908: 4a26 ldr r2, [pc, #152] ; (80049a4 <HAL_UART_IRQHandler+0x234>)
- 800490a: 651a str r2, [r3, #80] ; 0x50
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 800490c: 687b ldr r3, [r7, #4]
- 800490e: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004910: 4618 mov r0, r3
- 8004912: f7fd fa5c bl 8001dce <HAL_DMA_Abort_IT>
- 8004916: 4603 mov r3, r0
- 8004918: 2b00 cmp r3, #0
- 800491a: d016 beq.n 800494a <HAL_UART_IRQHandler+0x1da>
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 800491c: 687b ldr r3, [r7, #4]
- 800491e: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004920: 6d1b ldr r3, [r3, #80] ; 0x50
- 8004922: 687a ldr r2, [r7, #4]
- 8004924: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 8004926: 4610 mov r0, r2
- 8004928: 4798 blx r3
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 800492a: e00e b.n 800494a <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 800492c: 6878 ldr r0, [r7, #4]
- 800492e: f000 f845 bl 80049bc <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004932: e00a b.n 800494a <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004934: 6878 ldr r0, [r7, #4]
- 8004936: f000 f841 bl 80049bc <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 800493a: e006 b.n 800494a <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 800493c: 6878 ldr r0, [r7, #4]
- 800493e: f000 f83d bl 80049bc <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004942: 687b ldr r3, [r7, #4]
- 8004944: 2200 movs r2, #0
- 8004946: 67da str r2, [r3, #124] ; 0x7c
- }
- }
- return;
- 8004948: e025 b.n 8004996 <HAL_UART_IRQHandler+0x226>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 800494a: bf00 nop
- return;
- 800494c: e023 b.n 8004996 <HAL_UART_IRQHandler+0x226>
-
- } /* End if some error occurs */
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if (((isrflags & USART_ISR_TXE) != 0U)
- 800494e: 69fb ldr r3, [r7, #28]
- 8004950: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004954: 2b00 cmp r3, #0
- 8004956: d00d beq.n 8004974 <HAL_UART_IRQHandler+0x204>
- && ((cr1its & USART_CR1_TXEIE) != 0U))
- 8004958: 69bb ldr r3, [r7, #24]
- 800495a: f003 0380 and.w r3, r3, #128 ; 0x80
- 800495e: 2b00 cmp r3, #0
- 8004960: d008 beq.n 8004974 <HAL_UART_IRQHandler+0x204>
- {
- if (huart->TxISR != NULL)
- 8004962: 687b ldr r3, [r7, #4]
- 8004964: 6e5b ldr r3, [r3, #100] ; 0x64
- 8004966: 2b00 cmp r3, #0
- 8004968: d017 beq.n 800499a <HAL_UART_IRQHandler+0x22a>
- {
- huart->TxISR(huart);
- 800496a: 687b ldr r3, [r7, #4]
- 800496c: 6e5b ldr r3, [r3, #100] ; 0x64
- 800496e: 6878 ldr r0, [r7, #4]
- 8004970: 4798 blx r3
- }
- return;
- 8004972: e012 b.n 800499a <HAL_UART_IRQHandler+0x22a>
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
- 8004974: 69fb ldr r3, [r7, #28]
- 8004976: f003 0340 and.w r3, r3, #64 ; 0x40
- 800497a: 2b00 cmp r3, #0
- 800497c: d00e beq.n 800499c <HAL_UART_IRQHandler+0x22c>
- 800497e: 69bb ldr r3, [r7, #24]
- 8004980: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004984: 2b00 cmp r3, #0
- 8004986: d009 beq.n 800499c <HAL_UART_IRQHandler+0x22c>
- {
- UART_EndTransmit_IT(huart);
- 8004988: 6878 ldr r0, [r7, #4]
- 800498a: f000 fc14 bl 80051b6 <UART_EndTransmit_IT>
- return;
- 800498e: bf00 nop
- 8004990: e004 b.n 800499c <HAL_UART_IRQHandler+0x22c>
- return;
- 8004992: bf00 nop
- 8004994: e002 b.n 800499c <HAL_UART_IRQHandler+0x22c>
- return;
- 8004996: bf00 nop
- 8004998: e000 b.n 800499c <HAL_UART_IRQHandler+0x22c>
- return;
- 800499a: bf00 nop
- }
-
-}
- 800499c: 3720 adds r7, #32
- 800499e: 46bd mov sp, r7
- 80049a0: bd80 pop {r7, pc}
- 80049a2: bf00 nop
- 80049a4: 0800518b .word 0x0800518b
-
-080049a8 <HAL_UART_TxCpltCallback>:
- * @brief Tx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- 80049a8: b480 push {r7}
- 80049aa: b083 sub sp, #12
- 80049ac: af00 add r7, sp, #0
- 80049ae: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
- 80049b0: bf00 nop
- 80049b2: 370c adds r7, #12
- 80049b4: 46bd mov sp, r7
- 80049b6: f85d 7b04 ldr.w r7, [sp], #4
- 80049ba: 4770 bx lr
-
-080049bc <HAL_UART_ErrorCallback>:
- * @brief UART error callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- 80049bc: b480 push {r7}
- 80049be: b083 sub sp, #12
- 80049c0: af00 add r7, sp, #0
- 80049c2: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file.
- */
-}
- 80049c4: bf00 nop
- 80049c6: 370c adds r7, #12
- 80049c8: 46bd mov sp, r7
- 80049ca: f85d 7b04 ldr.w r7, [sp], #4
- 80049ce: 4770 bx lr
-
-080049d0 <UART_SetConfig>:
- * @brief Configure the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- 80049d0: b580 push {r7, lr}
- 80049d2: b088 sub sp, #32
- 80049d4: af00 add r7, sp, #0
- 80049d6: 6078 str r0, [r7, #4]
- uint32_t tmpreg;
- uint16_t brrtemp;
- UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv = 0x00000000U;
- 80049d8: 2300 movs r3, #0
- 80049da: 61bb str r3, [r7, #24]
- HAL_StatusTypeDef ret = HAL_OK;
- 80049dc: 2300 movs r3, #0
- 80049de: 75fb strb r3, [r7, #23]
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 80049e0: 687b ldr r3, [r7, #4]
- 80049e2: 689a ldr r2, [r3, #8]
- 80049e4: 687b ldr r3, [r7, #4]
- 80049e6: 691b ldr r3, [r3, #16]
- 80049e8: 431a orrs r2, r3
- 80049ea: 687b ldr r3, [r7, #4]
- 80049ec: 695b ldr r3, [r3, #20]
- 80049ee: 431a orrs r2, r3
- 80049f0: 687b ldr r3, [r7, #4]
- 80049f2: 69db ldr r3, [r3, #28]
- 80049f4: 4313 orrs r3, r2
- 80049f6: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 80049f8: 687b ldr r3, [r7, #4]
- 80049fa: 681b ldr r3, [r3, #0]
- 80049fc: 681a ldr r2, [r3, #0]
- 80049fe: 4bb1 ldr r3, [pc, #708] ; (8004cc4 <UART_SetConfig+0x2f4>)
- 8004a00: 4013 ands r3, r2
- 8004a02: 687a ldr r2, [r7, #4]
- 8004a04: 6812 ldr r2, [r2, #0]
- 8004a06: 6939 ldr r1, [r7, #16]
- 8004a08: 430b orrs r3, r1
- 8004a0a: 6013 str r3, [r2, #0]
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8004a0c: 687b ldr r3, [r7, #4]
- 8004a0e: 681b ldr r3, [r3, #0]
- 8004a10: 685b ldr r3, [r3, #4]
- 8004a12: f423 5140 bic.w r1, r3, #12288 ; 0x3000
- 8004a16: 687b ldr r3, [r7, #4]
- 8004a18: 68da ldr r2, [r3, #12]
- 8004a1a: 687b ldr r3, [r7, #4]
- 8004a1c: 681b ldr r3, [r3, #0]
- 8004a1e: 430a orrs r2, r1
- 8004a20: 605a str r2, [r3, #4]
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling (not applicable to LPUART) */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8004a22: 687b ldr r3, [r7, #4]
- 8004a24: 699b ldr r3, [r3, #24]
- 8004a26: 613b str r3, [r7, #16]
-
- tmpreg |= huart->Init.OneBitSampling;
- 8004a28: 687b ldr r3, [r7, #4]
- 8004a2a: 6a1b ldr r3, [r3, #32]
- 8004a2c: 693a ldr r2, [r7, #16]
- 8004a2e: 4313 orrs r3, r2
- 8004a30: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8004a32: 687b ldr r3, [r7, #4]
- 8004a34: 681b ldr r3, [r3, #0]
- 8004a36: 689b ldr r3, [r3, #8]
- 8004a38: f423 6130 bic.w r1, r3, #2816 ; 0xb00
- 8004a3c: 687b ldr r3, [r7, #4]
- 8004a3e: 681b ldr r3, [r3, #0]
- 8004a40: 693a ldr r2, [r7, #16]
- 8004a42: 430a orrs r2, r1
- 8004a44: 609a str r2, [r3, #8]
-
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
- 8004a46: 687b ldr r3, [r7, #4]
- 8004a48: 681b ldr r3, [r3, #0]
- 8004a4a: 4a9f ldr r2, [pc, #636] ; (8004cc8 <UART_SetConfig+0x2f8>)
- 8004a4c: 4293 cmp r3, r2
- 8004a4e: d121 bne.n 8004a94 <UART_SetConfig+0xc4>
- 8004a50: 4b9e ldr r3, [pc, #632] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004a52: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004a56: f003 0303 and.w r3, r3, #3
- 8004a5a: 2b03 cmp r3, #3
- 8004a5c: d816 bhi.n 8004a8c <UART_SetConfig+0xbc>
- 8004a5e: a201 add r2, pc, #4 ; (adr r2, 8004a64 <UART_SetConfig+0x94>)
- 8004a60: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004a64: 08004a75 .word 0x08004a75
- 8004a68: 08004a81 .word 0x08004a81
- 8004a6c: 08004a7b .word 0x08004a7b
- 8004a70: 08004a87 .word 0x08004a87
- 8004a74: 2301 movs r3, #1
- 8004a76: 77fb strb r3, [r7, #31]
- 8004a78: e151 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004a7a: 2302 movs r3, #2
- 8004a7c: 77fb strb r3, [r7, #31]
- 8004a7e: e14e b.n 8004d1e <UART_SetConfig+0x34e>
- 8004a80: 2304 movs r3, #4
- 8004a82: 77fb strb r3, [r7, #31]
- 8004a84: e14b b.n 8004d1e <UART_SetConfig+0x34e>
- 8004a86: 2308 movs r3, #8
- 8004a88: 77fb strb r3, [r7, #31]
- 8004a8a: e148 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004a8c: 2310 movs r3, #16
- 8004a8e: 77fb strb r3, [r7, #31]
- 8004a90: bf00 nop
- 8004a92: e144 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004a94: 687b ldr r3, [r7, #4]
- 8004a96: 681b ldr r3, [r3, #0]
- 8004a98: 4a8d ldr r2, [pc, #564] ; (8004cd0 <UART_SetConfig+0x300>)
- 8004a9a: 4293 cmp r3, r2
- 8004a9c: d134 bne.n 8004b08 <UART_SetConfig+0x138>
- 8004a9e: 4b8b ldr r3, [pc, #556] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004aa0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004aa4: f003 030c and.w r3, r3, #12
- 8004aa8: 2b0c cmp r3, #12
- 8004aaa: d829 bhi.n 8004b00 <UART_SetConfig+0x130>
- 8004aac: a201 add r2, pc, #4 ; (adr r2, 8004ab4 <UART_SetConfig+0xe4>)
- 8004aae: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004ab2: bf00 nop
- 8004ab4: 08004ae9 .word 0x08004ae9
- 8004ab8: 08004b01 .word 0x08004b01
- 8004abc: 08004b01 .word 0x08004b01
- 8004ac0: 08004b01 .word 0x08004b01
- 8004ac4: 08004af5 .word 0x08004af5
- 8004ac8: 08004b01 .word 0x08004b01
- 8004acc: 08004b01 .word 0x08004b01
- 8004ad0: 08004b01 .word 0x08004b01
- 8004ad4: 08004aef .word 0x08004aef
- 8004ad8: 08004b01 .word 0x08004b01
- 8004adc: 08004b01 .word 0x08004b01
- 8004ae0: 08004b01 .word 0x08004b01
- 8004ae4: 08004afb .word 0x08004afb
- 8004ae8: 2300 movs r3, #0
- 8004aea: 77fb strb r3, [r7, #31]
- 8004aec: e117 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004aee: 2302 movs r3, #2
- 8004af0: 77fb strb r3, [r7, #31]
- 8004af2: e114 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004af4: 2304 movs r3, #4
- 8004af6: 77fb strb r3, [r7, #31]
- 8004af8: e111 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004afa: 2308 movs r3, #8
- 8004afc: 77fb strb r3, [r7, #31]
- 8004afe: e10e b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b00: 2310 movs r3, #16
- 8004b02: 77fb strb r3, [r7, #31]
- 8004b04: bf00 nop
- 8004b06: e10a b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b08: 687b ldr r3, [r7, #4]
- 8004b0a: 681b ldr r3, [r3, #0]
- 8004b0c: 4a71 ldr r2, [pc, #452] ; (8004cd4 <UART_SetConfig+0x304>)
- 8004b0e: 4293 cmp r3, r2
- 8004b10: d120 bne.n 8004b54 <UART_SetConfig+0x184>
- 8004b12: 4b6e ldr r3, [pc, #440] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004b14: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004b18: f003 0330 and.w r3, r3, #48 ; 0x30
- 8004b1c: 2b10 cmp r3, #16
- 8004b1e: d00f beq.n 8004b40 <UART_SetConfig+0x170>
- 8004b20: 2b10 cmp r3, #16
- 8004b22: d802 bhi.n 8004b2a <UART_SetConfig+0x15a>
- 8004b24: 2b00 cmp r3, #0
- 8004b26: d005 beq.n 8004b34 <UART_SetConfig+0x164>
- 8004b28: e010 b.n 8004b4c <UART_SetConfig+0x17c>
- 8004b2a: 2b20 cmp r3, #32
- 8004b2c: d005 beq.n 8004b3a <UART_SetConfig+0x16a>
- 8004b2e: 2b30 cmp r3, #48 ; 0x30
- 8004b30: d009 beq.n 8004b46 <UART_SetConfig+0x176>
- 8004b32: e00b b.n 8004b4c <UART_SetConfig+0x17c>
- 8004b34: 2300 movs r3, #0
- 8004b36: 77fb strb r3, [r7, #31]
- 8004b38: e0f1 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b3a: 2302 movs r3, #2
- 8004b3c: 77fb strb r3, [r7, #31]
- 8004b3e: e0ee b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b40: 2304 movs r3, #4
- 8004b42: 77fb strb r3, [r7, #31]
- 8004b44: e0eb b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b46: 2308 movs r3, #8
- 8004b48: 77fb strb r3, [r7, #31]
- 8004b4a: e0e8 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b4c: 2310 movs r3, #16
- 8004b4e: 77fb strb r3, [r7, #31]
- 8004b50: bf00 nop
- 8004b52: e0e4 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b54: 687b ldr r3, [r7, #4]
- 8004b56: 681b ldr r3, [r3, #0]
- 8004b58: 4a5f ldr r2, [pc, #380] ; (8004cd8 <UART_SetConfig+0x308>)
- 8004b5a: 4293 cmp r3, r2
- 8004b5c: d120 bne.n 8004ba0 <UART_SetConfig+0x1d0>
- 8004b5e: 4b5b ldr r3, [pc, #364] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004b60: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004b64: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 8004b68: 2b40 cmp r3, #64 ; 0x40
- 8004b6a: d00f beq.n 8004b8c <UART_SetConfig+0x1bc>
- 8004b6c: 2b40 cmp r3, #64 ; 0x40
- 8004b6e: d802 bhi.n 8004b76 <UART_SetConfig+0x1a6>
- 8004b70: 2b00 cmp r3, #0
- 8004b72: d005 beq.n 8004b80 <UART_SetConfig+0x1b0>
- 8004b74: e010 b.n 8004b98 <UART_SetConfig+0x1c8>
- 8004b76: 2b80 cmp r3, #128 ; 0x80
- 8004b78: d005 beq.n 8004b86 <UART_SetConfig+0x1b6>
- 8004b7a: 2bc0 cmp r3, #192 ; 0xc0
- 8004b7c: d009 beq.n 8004b92 <UART_SetConfig+0x1c2>
- 8004b7e: e00b b.n 8004b98 <UART_SetConfig+0x1c8>
- 8004b80: 2300 movs r3, #0
- 8004b82: 77fb strb r3, [r7, #31]
- 8004b84: e0cb b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b86: 2302 movs r3, #2
- 8004b88: 77fb strb r3, [r7, #31]
- 8004b8a: e0c8 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b8c: 2304 movs r3, #4
- 8004b8e: 77fb strb r3, [r7, #31]
- 8004b90: e0c5 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b92: 2308 movs r3, #8
- 8004b94: 77fb strb r3, [r7, #31]
- 8004b96: e0c2 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004b98: 2310 movs r3, #16
- 8004b9a: 77fb strb r3, [r7, #31]
- 8004b9c: bf00 nop
- 8004b9e: e0be b.n 8004d1e <UART_SetConfig+0x34e>
- 8004ba0: 687b ldr r3, [r7, #4]
- 8004ba2: 681b ldr r3, [r3, #0]
- 8004ba4: 4a4d ldr r2, [pc, #308] ; (8004cdc <UART_SetConfig+0x30c>)
- 8004ba6: 4293 cmp r3, r2
- 8004ba8: d124 bne.n 8004bf4 <UART_SetConfig+0x224>
- 8004baa: 4b48 ldr r3, [pc, #288] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004bac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004bb0: f403 7340 and.w r3, r3, #768 ; 0x300
- 8004bb4: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004bb8: d012 beq.n 8004be0 <UART_SetConfig+0x210>
- 8004bba: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004bbe: d802 bhi.n 8004bc6 <UART_SetConfig+0x1f6>
- 8004bc0: 2b00 cmp r3, #0
- 8004bc2: d007 beq.n 8004bd4 <UART_SetConfig+0x204>
- 8004bc4: e012 b.n 8004bec <UART_SetConfig+0x21c>
- 8004bc6: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 8004bca: d006 beq.n 8004bda <UART_SetConfig+0x20a>
- 8004bcc: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8004bd0: d009 beq.n 8004be6 <UART_SetConfig+0x216>
- 8004bd2: e00b b.n 8004bec <UART_SetConfig+0x21c>
- 8004bd4: 2300 movs r3, #0
- 8004bd6: 77fb strb r3, [r7, #31]
- 8004bd8: e0a1 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004bda: 2302 movs r3, #2
- 8004bdc: 77fb strb r3, [r7, #31]
- 8004bde: e09e b.n 8004d1e <UART_SetConfig+0x34e>
- 8004be0: 2304 movs r3, #4
- 8004be2: 77fb strb r3, [r7, #31]
- 8004be4: e09b b.n 8004d1e <UART_SetConfig+0x34e>
- 8004be6: 2308 movs r3, #8
- 8004be8: 77fb strb r3, [r7, #31]
- 8004bea: e098 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004bec: 2310 movs r3, #16
- 8004bee: 77fb strb r3, [r7, #31]
- 8004bf0: bf00 nop
- 8004bf2: e094 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004bf4: 687b ldr r3, [r7, #4]
- 8004bf6: 681b ldr r3, [r3, #0]
- 8004bf8: 4a39 ldr r2, [pc, #228] ; (8004ce0 <UART_SetConfig+0x310>)
- 8004bfa: 4293 cmp r3, r2
- 8004bfc: d124 bne.n 8004c48 <UART_SetConfig+0x278>
- 8004bfe: 4b33 ldr r3, [pc, #204] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004c00: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004c04: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 8004c08: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004c0c: d012 beq.n 8004c34 <UART_SetConfig+0x264>
- 8004c0e: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004c12: d802 bhi.n 8004c1a <UART_SetConfig+0x24a>
- 8004c14: 2b00 cmp r3, #0
- 8004c16: d007 beq.n 8004c28 <UART_SetConfig+0x258>
- 8004c18: e012 b.n 8004c40 <UART_SetConfig+0x270>
- 8004c1a: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 8004c1e: d006 beq.n 8004c2e <UART_SetConfig+0x25e>
- 8004c20: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 8004c24: d009 beq.n 8004c3a <UART_SetConfig+0x26a>
- 8004c26: e00b b.n 8004c40 <UART_SetConfig+0x270>
- 8004c28: 2301 movs r3, #1
- 8004c2a: 77fb strb r3, [r7, #31]
- 8004c2c: e077 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c2e: 2302 movs r3, #2
- 8004c30: 77fb strb r3, [r7, #31]
- 8004c32: e074 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c34: 2304 movs r3, #4
- 8004c36: 77fb strb r3, [r7, #31]
- 8004c38: e071 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c3a: 2308 movs r3, #8
- 8004c3c: 77fb strb r3, [r7, #31]
- 8004c3e: e06e b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c40: 2310 movs r3, #16
- 8004c42: 77fb strb r3, [r7, #31]
- 8004c44: bf00 nop
- 8004c46: e06a b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c48: 687b ldr r3, [r7, #4]
- 8004c4a: 681b ldr r3, [r3, #0]
- 8004c4c: 4a25 ldr r2, [pc, #148] ; (8004ce4 <UART_SetConfig+0x314>)
- 8004c4e: 4293 cmp r3, r2
- 8004c50: d124 bne.n 8004c9c <UART_SetConfig+0x2cc>
- 8004c52: 4b1e ldr r3, [pc, #120] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004c54: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004c58: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 8004c5c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004c60: d012 beq.n 8004c88 <UART_SetConfig+0x2b8>
- 8004c62: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004c66: d802 bhi.n 8004c6e <UART_SetConfig+0x29e>
- 8004c68: 2b00 cmp r3, #0
- 8004c6a: d007 beq.n 8004c7c <UART_SetConfig+0x2ac>
- 8004c6c: e012 b.n 8004c94 <UART_SetConfig+0x2c4>
- 8004c6e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8004c72: d006 beq.n 8004c82 <UART_SetConfig+0x2b2>
- 8004c74: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 8004c78: d009 beq.n 8004c8e <UART_SetConfig+0x2be>
- 8004c7a: e00b b.n 8004c94 <UART_SetConfig+0x2c4>
- 8004c7c: 2300 movs r3, #0
- 8004c7e: 77fb strb r3, [r7, #31]
- 8004c80: e04d b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c82: 2302 movs r3, #2
- 8004c84: 77fb strb r3, [r7, #31]
- 8004c86: e04a b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c88: 2304 movs r3, #4
- 8004c8a: 77fb strb r3, [r7, #31]
- 8004c8c: e047 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c8e: 2308 movs r3, #8
- 8004c90: 77fb strb r3, [r7, #31]
- 8004c92: e044 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c94: 2310 movs r3, #16
- 8004c96: 77fb strb r3, [r7, #31]
- 8004c98: bf00 nop
- 8004c9a: e040 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004c9c: 687b ldr r3, [r7, #4]
- 8004c9e: 681b ldr r3, [r3, #0]
- 8004ca0: 4a11 ldr r2, [pc, #68] ; (8004ce8 <UART_SetConfig+0x318>)
- 8004ca2: 4293 cmp r3, r2
- 8004ca4: d139 bne.n 8004d1a <UART_SetConfig+0x34a>
- 8004ca6: 4b09 ldr r3, [pc, #36] ; (8004ccc <UART_SetConfig+0x2fc>)
- 8004ca8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004cac: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8004cb0: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004cb4: d027 beq.n 8004d06 <UART_SetConfig+0x336>
- 8004cb6: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004cba: d817 bhi.n 8004cec <UART_SetConfig+0x31c>
- 8004cbc: 2b00 cmp r3, #0
- 8004cbe: d01c beq.n 8004cfa <UART_SetConfig+0x32a>
- 8004cc0: e027 b.n 8004d12 <UART_SetConfig+0x342>
- 8004cc2: bf00 nop
- 8004cc4: efff69f3 .word 0xefff69f3
- 8004cc8: 40011000 .word 0x40011000
- 8004ccc: 40023800 .word 0x40023800
- 8004cd0: 40004400 .word 0x40004400
- 8004cd4: 40004800 .word 0x40004800
- 8004cd8: 40004c00 .word 0x40004c00
- 8004cdc: 40005000 .word 0x40005000
- 8004ce0: 40011400 .word 0x40011400
- 8004ce4: 40007800 .word 0x40007800
- 8004ce8: 40007c00 .word 0x40007c00
- 8004cec: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004cf0: d006 beq.n 8004d00 <UART_SetConfig+0x330>
- 8004cf2: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 8004cf6: d009 beq.n 8004d0c <UART_SetConfig+0x33c>
- 8004cf8: e00b b.n 8004d12 <UART_SetConfig+0x342>
- 8004cfa: 2300 movs r3, #0
- 8004cfc: 77fb strb r3, [r7, #31]
- 8004cfe: e00e b.n 8004d1e <UART_SetConfig+0x34e>
- 8004d00: 2302 movs r3, #2
- 8004d02: 77fb strb r3, [r7, #31]
- 8004d04: e00b b.n 8004d1e <UART_SetConfig+0x34e>
- 8004d06: 2304 movs r3, #4
- 8004d08: 77fb strb r3, [r7, #31]
- 8004d0a: e008 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004d0c: 2308 movs r3, #8
- 8004d0e: 77fb strb r3, [r7, #31]
- 8004d10: e005 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004d12: 2310 movs r3, #16
- 8004d14: 77fb strb r3, [r7, #31]
- 8004d16: bf00 nop
- 8004d18: e001 b.n 8004d1e <UART_SetConfig+0x34e>
- 8004d1a: 2310 movs r3, #16
- 8004d1c: 77fb strb r3, [r7, #31]
-
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8004d1e: 687b ldr r3, [r7, #4]
- 8004d20: 69db ldr r3, [r3, #28]
- 8004d22: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004d26: d17c bne.n 8004e22 <UART_SetConfig+0x452>
- {
- switch (clocksource)
- 8004d28: 7ffb ldrb r3, [r7, #31]
- 8004d2a: 2b08 cmp r3, #8
- 8004d2c: d859 bhi.n 8004de2 <UART_SetConfig+0x412>
- 8004d2e: a201 add r2, pc, #4 ; (adr r2, 8004d34 <UART_SetConfig+0x364>)
- 8004d30: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004d34: 08004d59 .word 0x08004d59
- 8004d38: 08004d77 .word 0x08004d77
- 8004d3c: 08004d95 .word 0x08004d95
- 8004d40: 08004de3 .word 0x08004de3
- 8004d44: 08004dad .word 0x08004dad
- 8004d48: 08004de3 .word 0x08004de3
- 8004d4c: 08004de3 .word 0x08004de3
- 8004d50: 08004de3 .word 0x08004de3
- 8004d54: 08004dcb .word 0x08004dcb
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004d58: f7fd fe50 bl 80029fc <HAL_RCC_GetPCLK1Freq>
- 8004d5c: 4603 mov r3, r0
- 8004d5e: 005a lsls r2, r3, #1
- 8004d60: 687b ldr r3, [r7, #4]
- 8004d62: 685b ldr r3, [r3, #4]
- 8004d64: 085b lsrs r3, r3, #1
- 8004d66: 441a add r2, r3
- 8004d68: 687b ldr r3, [r7, #4]
- 8004d6a: 685b ldr r3, [r3, #4]
- 8004d6c: fbb2 f3f3 udiv r3, r2, r3
- 8004d70: b29b uxth r3, r3
- 8004d72: 61bb str r3, [r7, #24]
- break;
- 8004d74: e038 b.n 8004de8 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004d76: f7fd fe55 bl 8002a24 <HAL_RCC_GetPCLK2Freq>
- 8004d7a: 4603 mov r3, r0
- 8004d7c: 005a lsls r2, r3, #1
- 8004d7e: 687b ldr r3, [r7, #4]
- 8004d80: 685b ldr r3, [r3, #4]
- 8004d82: 085b lsrs r3, r3, #1
- 8004d84: 441a add r2, r3
- 8004d86: 687b ldr r3, [r7, #4]
- 8004d88: 685b ldr r3, [r3, #4]
- 8004d8a: fbb2 f3f3 udiv r3, r2, r3
- 8004d8e: b29b uxth r3, r3
- 8004d90: 61bb str r3, [r7, #24]
- break;
- 8004d92: e029 b.n 8004de8 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8004d94: 687b ldr r3, [r7, #4]
- 8004d96: 685b ldr r3, [r3, #4]
- 8004d98: 085a lsrs r2, r3, #1
- 8004d9a: 4b5d ldr r3, [pc, #372] ; (8004f10 <UART_SetConfig+0x540>)
- 8004d9c: 4413 add r3, r2
- 8004d9e: 687a ldr r2, [r7, #4]
- 8004da0: 6852 ldr r2, [r2, #4]
- 8004da2: fbb3 f3f2 udiv r3, r3, r2
- 8004da6: b29b uxth r3, r3
- 8004da8: 61bb str r3, [r7, #24]
- break;
- 8004daa: e01d b.n 8004de8 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8004dac: f7fd fd68 bl 8002880 <HAL_RCC_GetSysClockFreq>
- 8004db0: 4603 mov r3, r0
- 8004db2: 005a lsls r2, r3, #1
- 8004db4: 687b ldr r3, [r7, #4]
- 8004db6: 685b ldr r3, [r3, #4]
- 8004db8: 085b lsrs r3, r3, #1
- 8004dba: 441a add r2, r3
- 8004dbc: 687b ldr r3, [r7, #4]
- 8004dbe: 685b ldr r3, [r3, #4]
- 8004dc0: fbb2 f3f3 udiv r3, r2, r3
- 8004dc4: b29b uxth r3, r3
- 8004dc6: 61bb str r3, [r7, #24]
- break;
- 8004dc8: e00e b.n 8004de8 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 8004dca: 687b ldr r3, [r7, #4]
- 8004dcc: 685b ldr r3, [r3, #4]
- 8004dce: 085b lsrs r3, r3, #1
- 8004dd0: f503 3280 add.w r2, r3, #65536 ; 0x10000
- 8004dd4: 687b ldr r3, [r7, #4]
- 8004dd6: 685b ldr r3, [r3, #4]
- 8004dd8: fbb2 f3f3 udiv r3, r2, r3
- 8004ddc: b29b uxth r3, r3
- 8004dde: 61bb str r3, [r7, #24]
- break;
- 8004de0: e002 b.n 8004de8 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8004de2: 2301 movs r3, #1
- 8004de4: 75fb strb r3, [r7, #23]
- break;
- 8004de6: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8004de8: 69bb ldr r3, [r7, #24]
- 8004dea: 2b0f cmp r3, #15
- 8004dec: d916 bls.n 8004e1c <UART_SetConfig+0x44c>
- 8004dee: 69bb ldr r3, [r7, #24]
- 8004df0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8004df4: d212 bcs.n 8004e1c <UART_SetConfig+0x44c>
- {
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 8004df6: 69bb ldr r3, [r7, #24]
- 8004df8: b29b uxth r3, r3
- 8004dfa: f023 030f bic.w r3, r3, #15
- 8004dfe: 81fb strh r3, [r7, #14]
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8004e00: 69bb ldr r3, [r7, #24]
- 8004e02: 085b lsrs r3, r3, #1
- 8004e04: b29b uxth r3, r3
- 8004e06: f003 0307 and.w r3, r3, #7
- 8004e0a: b29a uxth r2, r3
- 8004e0c: 89fb ldrh r3, [r7, #14]
- 8004e0e: 4313 orrs r3, r2
- 8004e10: 81fb strh r3, [r7, #14]
- huart->Instance->BRR = brrtemp;
- 8004e12: 687b ldr r3, [r7, #4]
- 8004e14: 681b ldr r3, [r3, #0]
- 8004e16: 89fa ldrh r2, [r7, #14]
- 8004e18: 60da str r2, [r3, #12]
- 8004e1a: e06e b.n 8004efa <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 8004e1c: 2301 movs r3, #1
- 8004e1e: 75fb strb r3, [r7, #23]
- 8004e20: e06b b.n 8004efa <UART_SetConfig+0x52a>
- }
- }
- else
- {
- switch (clocksource)
- 8004e22: 7ffb ldrb r3, [r7, #31]
- 8004e24: 2b08 cmp r3, #8
- 8004e26: d857 bhi.n 8004ed8 <UART_SetConfig+0x508>
- 8004e28: a201 add r2, pc, #4 ; (adr r2, 8004e30 <UART_SetConfig+0x460>)
- 8004e2a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004e2e: bf00 nop
- 8004e30: 08004e55 .word 0x08004e55
- 8004e34: 08004e71 .word 0x08004e71
- 8004e38: 08004e8d .word 0x08004e8d
- 8004e3c: 08004ed9 .word 0x08004ed9
- 8004e40: 08004ea5 .word 0x08004ea5
- 8004e44: 08004ed9 .word 0x08004ed9
- 8004e48: 08004ed9 .word 0x08004ed9
- 8004e4c: 08004ed9 .word 0x08004ed9
- 8004e50: 08004ec1 .word 0x08004ec1
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004e54: f7fd fdd2 bl 80029fc <HAL_RCC_GetPCLK1Freq>
- 8004e58: 4602 mov r2, r0
- 8004e5a: 687b ldr r3, [r7, #4]
- 8004e5c: 685b ldr r3, [r3, #4]
- 8004e5e: 085b lsrs r3, r3, #1
- 8004e60: 441a add r2, r3
- 8004e62: 687b ldr r3, [r7, #4]
- 8004e64: 685b ldr r3, [r3, #4]
- 8004e66: fbb2 f3f3 udiv r3, r2, r3
- 8004e6a: b29b uxth r3, r3
- 8004e6c: 61bb str r3, [r7, #24]
- break;
- 8004e6e: e036 b.n 8004ede <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004e70: f7fd fdd8 bl 8002a24 <HAL_RCC_GetPCLK2Freq>
- 8004e74: 4602 mov r2, r0
- 8004e76: 687b ldr r3, [r7, #4]
- 8004e78: 685b ldr r3, [r3, #4]
- 8004e7a: 085b lsrs r3, r3, #1
- 8004e7c: 441a add r2, r3
- 8004e7e: 687b ldr r3, [r7, #4]
- 8004e80: 685b ldr r3, [r3, #4]
- 8004e82: fbb2 f3f3 udiv r3, r2, r3
- 8004e86: b29b uxth r3, r3
- 8004e88: 61bb str r3, [r7, #24]
- break;
- 8004e8a: e028 b.n 8004ede <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 8004e8c: 687b ldr r3, [r7, #4]
- 8004e8e: 685b ldr r3, [r3, #4]
- 8004e90: 085a lsrs r2, r3, #1
- 8004e92: 4b20 ldr r3, [pc, #128] ; (8004f14 <UART_SetConfig+0x544>)
- 8004e94: 4413 add r3, r2
- 8004e96: 687a ldr r2, [r7, #4]
- 8004e98: 6852 ldr r2, [r2, #4]
- 8004e9a: fbb3 f3f2 udiv r3, r3, r2
- 8004e9e: b29b uxth r3, r3
- 8004ea0: 61bb str r3, [r7, #24]
- break;
- 8004ea2: e01c b.n 8004ede <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8004ea4: f7fd fcec bl 8002880 <HAL_RCC_GetSysClockFreq>
- 8004ea8: 4602 mov r2, r0
- 8004eaa: 687b ldr r3, [r7, #4]
- 8004eac: 685b ldr r3, [r3, #4]
- 8004eae: 085b lsrs r3, r3, #1
- 8004eb0: 441a add r2, r3
- 8004eb2: 687b ldr r3, [r7, #4]
- 8004eb4: 685b ldr r3, [r3, #4]
- 8004eb6: fbb2 f3f3 udiv r3, r2, r3
- 8004eba: b29b uxth r3, r3
- 8004ebc: 61bb str r3, [r7, #24]
- break;
- 8004ebe: e00e b.n 8004ede <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 8004ec0: 687b ldr r3, [r7, #4]
- 8004ec2: 685b ldr r3, [r3, #4]
- 8004ec4: 085b lsrs r3, r3, #1
- 8004ec6: f503 4200 add.w r2, r3, #32768 ; 0x8000
- 8004eca: 687b ldr r3, [r7, #4]
- 8004ecc: 685b ldr r3, [r3, #4]
- 8004ece: fbb2 f3f3 udiv r3, r2, r3
- 8004ed2: b29b uxth r3, r3
- 8004ed4: 61bb str r3, [r7, #24]
- break;
- 8004ed6: e002 b.n 8004ede <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8004ed8: 2301 movs r3, #1
- 8004eda: 75fb strb r3, [r7, #23]
- break;
- 8004edc: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8004ede: 69bb ldr r3, [r7, #24]
- 8004ee0: 2b0f cmp r3, #15
- 8004ee2: d908 bls.n 8004ef6 <UART_SetConfig+0x526>
- 8004ee4: 69bb ldr r3, [r7, #24]
- 8004ee6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8004eea: d204 bcs.n 8004ef6 <UART_SetConfig+0x526>
- {
- huart->Instance->BRR = usartdiv;
- 8004eec: 687b ldr r3, [r7, #4]
- 8004eee: 681b ldr r3, [r3, #0]
- 8004ef0: 69ba ldr r2, [r7, #24]
- 8004ef2: 60da str r2, [r3, #12]
- 8004ef4: e001 b.n 8004efa <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 8004ef6: 2301 movs r3, #1
- 8004ef8: 75fb strb r3, [r7, #23]
- }
- }
-
-
- /* Clear ISR function pointers */
- huart->RxISR = NULL;
- 8004efa: 687b ldr r3, [r7, #4]
- 8004efc: 2200 movs r2, #0
- 8004efe: 661a str r2, [r3, #96] ; 0x60
- huart->TxISR = NULL;
- 8004f00: 687b ldr r3, [r7, #4]
- 8004f02: 2200 movs r2, #0
- 8004f04: 665a str r2, [r3, #100] ; 0x64
-
- return ret;
- 8004f06: 7dfb ldrb r3, [r7, #23]
-}
- 8004f08: 4618 mov r0, r3
- 8004f0a: 3720 adds r7, #32
- 8004f0c: 46bd mov sp, r7
- 8004f0e: bd80 pop {r7, pc}
- 8004f10: 01e84800 .word 0x01e84800
- 8004f14: 00f42400 .word 0x00f42400
-
-08004f18 <UART_AdvFeatureConfig>:
- * @brief Configure the UART peripheral advanced features.
- * @param huart UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- 8004f18: b480 push {r7}
- 8004f1a: b083 sub sp, #12
- 8004f1c: af00 add r7, sp, #0
- 8004f1e: 6078 str r0, [r7, #4]
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 8004f20: 687b ldr r3, [r7, #4]
- 8004f22: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004f24: f003 0301 and.w r3, r3, #1
- 8004f28: 2b00 cmp r3, #0
- 8004f2a: d00a beq.n 8004f42 <UART_AdvFeatureConfig+0x2a>
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8004f2c: 687b ldr r3, [r7, #4]
- 8004f2e: 681b ldr r3, [r3, #0]
- 8004f30: 685b ldr r3, [r3, #4]
- 8004f32: f423 3100 bic.w r1, r3, #131072 ; 0x20000
- 8004f36: 687b ldr r3, [r7, #4]
- 8004f38: 6a9a ldr r2, [r3, #40] ; 0x28
- 8004f3a: 687b ldr r3, [r7, #4]
- 8004f3c: 681b ldr r3, [r3, #0]
- 8004f3e: 430a orrs r2, r1
- 8004f40: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 8004f42: 687b ldr r3, [r7, #4]
- 8004f44: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004f46: f003 0302 and.w r3, r3, #2
- 8004f4a: 2b00 cmp r3, #0
- 8004f4c: d00a beq.n 8004f64 <UART_AdvFeatureConfig+0x4c>
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 8004f4e: 687b ldr r3, [r7, #4]
- 8004f50: 681b ldr r3, [r3, #0]
- 8004f52: 685b ldr r3, [r3, #4]
- 8004f54: f423 3180 bic.w r1, r3, #65536 ; 0x10000
- 8004f58: 687b ldr r3, [r7, #4]
- 8004f5a: 6ada ldr r2, [r3, #44] ; 0x2c
- 8004f5c: 687b ldr r3, [r7, #4]
- 8004f5e: 681b ldr r3, [r3, #0]
- 8004f60: 430a orrs r2, r1
- 8004f62: 605a str r2, [r3, #4]
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 8004f64: 687b ldr r3, [r7, #4]
- 8004f66: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004f68: f003 0304 and.w r3, r3, #4
- 8004f6c: 2b00 cmp r3, #0
- 8004f6e: d00a beq.n 8004f86 <UART_AdvFeatureConfig+0x6e>
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 8004f70: 687b ldr r3, [r7, #4]
- 8004f72: 681b ldr r3, [r3, #0]
- 8004f74: 685b ldr r3, [r3, #4]
- 8004f76: f423 2180 bic.w r1, r3, #262144 ; 0x40000
- 8004f7a: 687b ldr r3, [r7, #4]
- 8004f7c: 6b1a ldr r2, [r3, #48] ; 0x30
- 8004f7e: 687b ldr r3, [r7, #4]
- 8004f80: 681b ldr r3, [r3, #0]
- 8004f82: 430a orrs r2, r1
- 8004f84: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 8004f86: 687b ldr r3, [r7, #4]
- 8004f88: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004f8a: f003 0308 and.w r3, r3, #8
- 8004f8e: 2b00 cmp r3, #0
- 8004f90: d00a beq.n 8004fa8 <UART_AdvFeatureConfig+0x90>
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 8004f92: 687b ldr r3, [r7, #4]
- 8004f94: 681b ldr r3, [r3, #0]
- 8004f96: 685b ldr r3, [r3, #4]
- 8004f98: f423 4100 bic.w r1, r3, #32768 ; 0x8000
- 8004f9c: 687b ldr r3, [r7, #4]
- 8004f9e: 6b5a ldr r2, [r3, #52] ; 0x34
- 8004fa0: 687b ldr r3, [r7, #4]
- 8004fa2: 681b ldr r3, [r3, #0]
- 8004fa4: 430a orrs r2, r1
- 8004fa6: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 8004fa8: 687b ldr r3, [r7, #4]
- 8004faa: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004fac: f003 0310 and.w r3, r3, #16
- 8004fb0: 2b00 cmp r3, #0
- 8004fb2: d00a beq.n 8004fca <UART_AdvFeatureConfig+0xb2>
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 8004fb4: 687b ldr r3, [r7, #4]
- 8004fb6: 681b ldr r3, [r3, #0]
- 8004fb8: 689b ldr r3, [r3, #8]
- 8004fba: f423 5180 bic.w r1, r3, #4096 ; 0x1000
- 8004fbe: 687b ldr r3, [r7, #4]
- 8004fc0: 6b9a ldr r2, [r3, #56] ; 0x38
- 8004fc2: 687b ldr r3, [r7, #4]
- 8004fc4: 681b ldr r3, [r3, #0]
- 8004fc6: 430a orrs r2, r1
- 8004fc8: 609a str r2, [r3, #8]
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 8004fca: 687b ldr r3, [r7, #4]
- 8004fcc: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004fce: f003 0320 and.w r3, r3, #32
- 8004fd2: 2b00 cmp r3, #0
- 8004fd4: d00a beq.n 8004fec <UART_AdvFeatureConfig+0xd4>
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 8004fd6: 687b ldr r3, [r7, #4]
- 8004fd8: 681b ldr r3, [r3, #0]
- 8004fda: 689b ldr r3, [r3, #8]
- 8004fdc: f423 5100 bic.w r1, r3, #8192 ; 0x2000
- 8004fe0: 687b ldr r3, [r7, #4]
- 8004fe2: 6bda ldr r2, [r3, #60] ; 0x3c
- 8004fe4: 687b ldr r3, [r7, #4]
- 8004fe6: 681b ldr r3, [r3, #0]
- 8004fe8: 430a orrs r2, r1
- 8004fea: 609a str r2, [r3, #8]
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 8004fec: 687b ldr r3, [r7, #4]
- 8004fee: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004ff0: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004ff4: 2b00 cmp r3, #0
- 8004ff6: d01a beq.n 800502e <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 8004ff8: 687b ldr r3, [r7, #4]
- 8004ffa: 681b ldr r3, [r3, #0]
- 8004ffc: 685b ldr r3, [r3, #4]
- 8004ffe: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
- 8005002: 687b ldr r3, [r7, #4]
- 8005004: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005006: 687b ldr r3, [r7, #4]
- 8005008: 681b ldr r3, [r3, #0]
- 800500a: 430a orrs r2, r1
- 800500c: 605a str r2, [r3, #4]
- /* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 800500e: 687b ldr r3, [r7, #4]
- 8005010: 6c1b ldr r3, [r3, #64] ; 0x40
- 8005012: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8005016: d10a bne.n 800502e <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8005018: 687b ldr r3, [r7, #4]
- 800501a: 681b ldr r3, [r3, #0]
- 800501c: 685b ldr r3, [r3, #4]
- 800501e: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
- 8005022: 687b ldr r3, [r7, #4]
- 8005024: 6c5a ldr r2, [r3, #68] ; 0x44
- 8005026: 687b ldr r3, [r7, #4]
- 8005028: 681b ldr r3, [r3, #0]
- 800502a: 430a orrs r2, r1
- 800502c: 605a str r2, [r3, #4]
- }
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 800502e: 687b ldr r3, [r7, #4]
- 8005030: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005032: f003 0380 and.w r3, r3, #128 ; 0x80
- 8005036: 2b00 cmp r3, #0
- 8005038: d00a beq.n 8005050 <UART_AdvFeatureConfig+0x138>
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 800503a: 687b ldr r3, [r7, #4]
- 800503c: 681b ldr r3, [r3, #0]
- 800503e: 685b ldr r3, [r3, #4]
- 8005040: f423 2100 bic.w r1, r3, #524288 ; 0x80000
- 8005044: 687b ldr r3, [r7, #4]
- 8005046: 6c9a ldr r2, [r3, #72] ; 0x48
- 8005048: 687b ldr r3, [r7, #4]
- 800504a: 681b ldr r3, [r3, #0]
- 800504c: 430a orrs r2, r1
- 800504e: 605a str r2, [r3, #4]
- }
-}
- 8005050: bf00 nop
- 8005052: 370c adds r7, #12
- 8005054: 46bd mov sp, r7
- 8005056: f85d 7b04 ldr.w r7, [sp], #4
- 800505a: 4770 bx lr
-
-0800505c <UART_CheckIdleState>:
- * @brief Check the UART Idle State.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- 800505c: b580 push {r7, lr}
- 800505e: b086 sub sp, #24
- 8005060: af02 add r7, sp, #8
- 8005062: 6078 str r0, [r7, #4]
- uint32_t tickstart;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8005064: 687b ldr r3, [r7, #4]
- 8005066: 2200 movs r2, #0
- 8005068: 67da str r2, [r3, #124] ; 0x7c
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 800506a: f7fc fd93 bl 8001b94 <HAL_GetTick>
- 800506e: 60f8 str r0, [r7, #12]
-
- /* Check if the Transmitter is enabled */
- if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 8005070: 687b ldr r3, [r7, #4]
- 8005072: 681b ldr r3, [r3, #0]
- 8005074: 681b ldr r3, [r3, #0]
- 8005076: f003 0308 and.w r3, r3, #8
- 800507a: 2b08 cmp r3, #8
- 800507c: d10e bne.n 800509c <UART_CheckIdleState+0x40>
- {
- /* Wait until TEACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 800507e: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
- 8005082: 9300 str r3, [sp, #0]
- 8005084: 68fb ldr r3, [r7, #12]
- 8005086: 2200 movs r2, #0
- 8005088: f44f 1100 mov.w r1, #2097152 ; 0x200000
- 800508c: 6878 ldr r0, [r7, #4]
- 800508e: f000 f814 bl 80050ba <UART_WaitOnFlagUntilTimeout>
- 8005092: 4603 mov r3, r0
- 8005094: 2b00 cmp r3, #0
- 8005096: d001 beq.n 800509c <UART_CheckIdleState+0x40>
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- 8005098: 2303 movs r3, #3
- 800509a: e00a b.n 80050b2 <UART_CheckIdleState+0x56>
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- 800509c: 687b ldr r3, [r7, #4]
- 800509e: 2220 movs r2, #32
- 80050a0: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 80050a2: 687b ldr r3, [r7, #4]
- 80050a4: 2220 movs r2, #32
- 80050a6: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 80050a8: 687b ldr r3, [r7, #4]
- 80050aa: 2200 movs r2, #0
- 80050ac: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 80050b0: 2300 movs r3, #0
-}
- 80050b2: 4618 mov r0, r3
- 80050b4: 3710 adds r7, #16
- 80050b6: 46bd mov sp, r7
- 80050b8: bd80 pop {r7, pc}
-
-080050ba <UART_WaitOnFlagUntilTimeout>:
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- 80050ba: b580 push {r7, lr}
- 80050bc: b084 sub sp, #16
- 80050be: af00 add r7, sp, #0
- 80050c0: 60f8 str r0, [r7, #12]
- 80050c2: 60b9 str r1, [r7, #8]
- 80050c4: 603b str r3, [r7, #0]
- 80050c6: 4613 mov r3, r2
- 80050c8: 71fb strb r3, [r7, #7]
- /* Wait until flag is set */
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 80050ca: e02a b.n 8005122 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- 80050cc: 69bb ldr r3, [r7, #24]
- 80050ce: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 80050d2: d026 beq.n 8005122 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 80050d4: f7fc fd5e bl 8001b94 <HAL_GetTick>
- 80050d8: 4602 mov r2, r0
- 80050da: 683b ldr r3, [r7, #0]
- 80050dc: 1ad3 subs r3, r2, r3
- 80050de: 69ba ldr r2, [r7, #24]
- 80050e0: 429a cmp r2, r3
- 80050e2: d302 bcc.n 80050ea <UART_WaitOnFlagUntilTimeout+0x30>
- 80050e4: 69bb ldr r3, [r7, #24]
- 80050e6: 2b00 cmp r3, #0
- 80050e8: d11b bne.n 8005122 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 80050ea: 68fb ldr r3, [r7, #12]
- 80050ec: 681b ldr r3, [r3, #0]
- 80050ee: 681a ldr r2, [r3, #0]
- 80050f0: 68fb ldr r3, [r7, #12]
- 80050f2: 681b ldr r3, [r3, #0]
- 80050f4: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 80050f8: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80050fa: 68fb ldr r3, [r7, #12]
- 80050fc: 681b ldr r3, [r3, #0]
- 80050fe: 689a ldr r2, [r3, #8]
- 8005100: 68fb ldr r3, [r7, #12]
- 8005102: 681b ldr r3, [r3, #0]
- 8005104: f022 0201 bic.w r2, r2, #1
- 8005108: 609a str r2, [r3, #8]
-
- huart->gState = HAL_UART_STATE_READY;
- 800510a: 68fb ldr r3, [r7, #12]
- 800510c: 2220 movs r2, #32
- 800510e: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 8005110: 68fb ldr r3, [r7, #12]
- 8005112: 2220 movs r2, #32
- 8005114: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8005116: 68fb ldr r3, [r7, #12]
- 8005118: 2200 movs r2, #0
- 800511a: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_TIMEOUT;
- 800511e: 2303 movs r3, #3
- 8005120: e00f b.n 8005142 <UART_WaitOnFlagUntilTimeout+0x88>
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8005122: 68fb ldr r3, [r7, #12]
- 8005124: 681b ldr r3, [r3, #0]
- 8005126: 69da ldr r2, [r3, #28]
- 8005128: 68bb ldr r3, [r7, #8]
- 800512a: 4013 ands r3, r2
- 800512c: 68ba ldr r2, [r7, #8]
- 800512e: 429a cmp r2, r3
- 8005130: bf0c ite eq
- 8005132: 2301 moveq r3, #1
- 8005134: 2300 movne r3, #0
- 8005136: b2db uxtb r3, r3
- 8005138: 461a mov r2, r3
- 800513a: 79fb ldrb r3, [r7, #7]
- 800513c: 429a cmp r2, r3
- 800513e: d0c5 beq.n 80050cc <UART_WaitOnFlagUntilTimeout+0x12>
- }
- }
- }
- return HAL_OK;
- 8005140: 2300 movs r3, #0
-}
- 8005142: 4618 mov r0, r3
- 8005144: 3710 adds r7, #16
- 8005146: 46bd mov sp, r7
- 8005148: bd80 pop {r7, pc}
-
-0800514a <UART_EndRxTransfer>:
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- 800514a: b480 push {r7}
- 800514c: b083 sub sp, #12
- 800514e: af00 add r7, sp, #0
- 8005150: 6078 str r0, [r7, #4]
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8005152: 687b ldr r3, [r7, #4]
- 8005154: 681b ldr r3, [r3, #0]
- 8005156: 681a ldr r2, [r3, #0]
- 8005158: 687b ldr r3, [r7, #4]
- 800515a: 681b ldr r3, [r3, #0]
- 800515c: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8005160: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8005162: 687b ldr r3, [r7, #4]
- 8005164: 681b ldr r3, [r3, #0]
- 8005166: 689a ldr r2, [r3, #8]
- 8005168: 687b ldr r3, [r7, #4]
- 800516a: 681b ldr r3, [r3, #0]
- 800516c: f022 0201 bic.w r2, r2, #1
- 8005170: 609a str r2, [r3, #8]
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 8005172: 687b ldr r3, [r7, #4]
- 8005174: 2220 movs r2, #32
- 8005176: 679a str r2, [r3, #120] ; 0x78
-
- /* Reset RxIsr function pointer */
- huart->RxISR = NULL;
- 8005178: 687b ldr r3, [r7, #4]
- 800517a: 2200 movs r2, #0
- 800517c: 661a str r2, [r3, #96] ; 0x60
-}
- 800517e: bf00 nop
- 8005180: 370c adds r7, #12
- 8005182: 46bd mov sp, r7
- 8005184: f85d 7b04 ldr.w r7, [sp], #4
- 8005188: 4770 bx lr
-
-0800518a <UART_DMAAbortOnError>:
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- 800518a: b580 push {r7, lr}
- 800518c: b084 sub sp, #16
- 800518e: af00 add r7, sp, #0
- 8005190: 6078 str r0, [r7, #4]
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 8005192: 687b ldr r3, [r7, #4]
- 8005194: 6b9b ldr r3, [r3, #56] ; 0x38
- 8005196: 60fb str r3, [r7, #12]
- huart->RxXferCount = 0U;
- 8005198: 68fb ldr r3, [r7, #12]
- 800519a: 2200 movs r2, #0
- 800519c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->TxXferCount = 0U;
- 80051a0: 68fb ldr r3, [r7, #12]
- 80051a2: 2200 movs r2, #0
- 80051a4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 80051a8: 68f8 ldr r0, [r7, #12]
- 80051aa: f7ff fc07 bl 80049bc <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 80051ae: bf00 nop
- 80051b0: 3710 adds r7, #16
- 80051b2: 46bd mov sp, r7
- 80051b4: bd80 pop {r7, pc}
-
-080051b6 <UART_EndTransmit_IT>:
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- 80051b6: b580 push {r7, lr}
- 80051b8: b082 sub sp, #8
- 80051ba: af00 add r7, sp, #0
- 80051bc: 6078 str r0, [r7, #4]
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- 80051be: 687b ldr r3, [r7, #4]
- 80051c0: 681b ldr r3, [r3, #0]
- 80051c2: 681a ldr r2, [r3, #0]
- 80051c4: 687b ldr r3, [r7, #4]
- 80051c6: 681b ldr r3, [r3, #0]
- 80051c8: f022 0240 bic.w r2, r2, #64 ; 0x40
- 80051cc: 601a str r2, [r3, #0]
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 80051ce: 687b ldr r3, [r7, #4]
- 80051d0: 2220 movs r2, #32
- 80051d2: 675a str r2, [r3, #116] ; 0x74
-
- /* Cleat TxISR function pointer */
- huart->TxISR = NULL;
- 80051d4: 687b ldr r3, [r7, #4]
- 80051d6: 2200 movs r2, #0
- 80051d8: 665a str r2, [r3, #100] ; 0x64
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx complete callback*/
- huart->TxCpltCallback(huart);
-#else
- /*Call legacy weak Tx complete callback*/
- HAL_UART_TxCpltCallback(huart);
- 80051da: 6878 ldr r0, [r7, #4]
- 80051dc: f7ff fbe4 bl 80049a8 <HAL_UART_TxCpltCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 80051e0: bf00 nop
- 80051e2: 3708 adds r7, #8
- 80051e4: 46bd mov sp, r7
- 80051e6: bd80 pop {r7, pc}
-
-080051e8 <UART_RxISR_8BIT>:
- * @brief RX interrrupt handler for 7 or 8 bits data word length .
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
-{
- 80051e8: b580 push {r7, lr}
- 80051ea: b084 sub sp, #16
- 80051ec: af00 add r7, sp, #0
- 80051ee: 6078 str r0, [r7, #4]
- uint16_t uhMask = huart->Mask;
- 80051f0: 687b ldr r3, [r7, #4]
- 80051f2: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 80051f6: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 80051f8: 687b ldr r3, [r7, #4]
- 80051fa: 6f9b ldr r3, [r3, #120] ; 0x78
- 80051fc: 2b22 cmp r3, #34 ; 0x22
- 80051fe: d13a bne.n 8005276 <UART_RxISR_8BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 8005200: 687b ldr r3, [r7, #4]
- 8005202: 681b ldr r3, [r3, #0]
- 8005204: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005206: 81bb strh r3, [r7, #12]
- *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
- 8005208: 89bb ldrh r3, [r7, #12]
- 800520a: b2d9 uxtb r1, r3
- 800520c: 89fb ldrh r3, [r7, #14]
- 800520e: b2da uxtb r2, r3
- 8005210: 687b ldr r3, [r7, #4]
- 8005212: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005214: 400a ands r2, r1
- 8005216: b2d2 uxtb r2, r2
- 8005218: 701a strb r2, [r3, #0]
- huart->pRxBuffPtr++;
- 800521a: 687b ldr r3, [r7, #4]
- 800521c: 6d5b ldr r3, [r3, #84] ; 0x54
- 800521e: 1c5a adds r2, r3, #1
- 8005220: 687b ldr r3, [r7, #4]
- 8005222: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 8005224: 687b ldr r3, [r7, #4]
- 8005226: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 800522a: b29b uxth r3, r3
- 800522c: 3b01 subs r3, #1
- 800522e: b29a uxth r2, r3
- 8005230: 687b ldr r3, [r7, #4]
- 8005232: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 8005236: 687b ldr r3, [r7, #4]
- 8005238: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 800523c: b29b uxth r3, r3
- 800523e: 2b00 cmp r3, #0
- 8005240: d121 bne.n 8005286 <UART_RxISR_8BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8005242: 687b ldr r3, [r7, #4]
- 8005244: 681b ldr r3, [r3, #0]
- 8005246: 681a ldr r2, [r3, #0]
- 8005248: 687b ldr r3, [r7, #4]
- 800524a: 681b ldr r3, [r3, #0]
- 800524c: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8005250: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8005252: 687b ldr r3, [r7, #4]
- 8005254: 681b ldr r3, [r3, #0]
- 8005256: 689a ldr r2, [r3, #8]
- 8005258: 687b ldr r3, [r7, #4]
- 800525a: 681b ldr r3, [r3, #0]
- 800525c: f022 0201 bic.w r2, r2, #1
- 8005260: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 8005262: 687b ldr r3, [r7, #4]
- 8005264: 2220 movs r2, #32
- 8005266: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 8005268: 687b ldr r3, [r7, #4]
- 800526a: 2200 movs r2, #0
- 800526c: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 800526e: 6878 ldr r0, [r7, #4]
- 8005270: f7fc f91e bl 80014b0 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 8005274: e007 b.n 8005286 <UART_RxISR_8BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 8005276: 687b ldr r3, [r7, #4]
- 8005278: 681b ldr r3, [r3, #0]
- 800527a: 699a ldr r2, [r3, #24]
- 800527c: 687b ldr r3, [r7, #4]
- 800527e: 681b ldr r3, [r3, #0]
- 8005280: f042 0208 orr.w r2, r2, #8
- 8005284: 619a str r2, [r3, #24]
-}
- 8005286: bf00 nop
- 8005288: 3710 adds r7, #16
- 800528a: 46bd mov sp, r7
- 800528c: bd80 pop {r7, pc}
-
-0800528e <UART_RxISR_16BIT>:
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
-{
- 800528e: b580 push {r7, lr}
- 8005290: b084 sub sp, #16
- 8005292: af00 add r7, sp, #0
- 8005294: 6078 str r0, [r7, #4]
- uint16_t *tmp;
- uint16_t uhMask = huart->Mask;
- 8005296: 687b ldr r3, [r7, #4]
- 8005298: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 800529c: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 800529e: 687b ldr r3, [r7, #4]
- 80052a0: 6f9b ldr r3, [r3, #120] ; 0x78
- 80052a2: 2b22 cmp r3, #34 ; 0x22
- 80052a4: d13a bne.n 800531c <UART_RxISR_16BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 80052a6: 687b ldr r3, [r7, #4]
- 80052a8: 681b ldr r3, [r3, #0]
- 80052aa: 6a5b ldr r3, [r3, #36] ; 0x24
- 80052ac: 81bb strh r3, [r7, #12]
- tmp = (uint16_t *) huart->pRxBuffPtr ;
- 80052ae: 687b ldr r3, [r7, #4]
- 80052b0: 6d5b ldr r3, [r3, #84] ; 0x54
- 80052b2: 60bb str r3, [r7, #8]
- *tmp = (uint16_t)(uhdata & uhMask);
- 80052b4: 89ba ldrh r2, [r7, #12]
- 80052b6: 89fb ldrh r3, [r7, #14]
- 80052b8: 4013 ands r3, r2
- 80052ba: b29a uxth r2, r3
- 80052bc: 68bb ldr r3, [r7, #8]
- 80052be: 801a strh r2, [r3, #0]
- huart->pRxBuffPtr += 2U;
- 80052c0: 687b ldr r3, [r7, #4]
- 80052c2: 6d5b ldr r3, [r3, #84] ; 0x54
- 80052c4: 1c9a adds r2, r3, #2
- 80052c6: 687b ldr r3, [r7, #4]
- 80052c8: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 80052ca: 687b ldr r3, [r7, #4]
- 80052cc: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 80052d0: b29b uxth r3, r3
- 80052d2: 3b01 subs r3, #1
- 80052d4: b29a uxth r2, r3
- 80052d6: 687b ldr r3, [r7, #4]
- 80052d8: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 80052dc: 687b ldr r3, [r7, #4]
- 80052de: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 80052e2: b29b uxth r3, r3
- 80052e4: 2b00 cmp r3, #0
- 80052e6: d121 bne.n 800532c <UART_RxISR_16BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 80052e8: 687b ldr r3, [r7, #4]
- 80052ea: 681b ldr r3, [r3, #0]
- 80052ec: 681a ldr r2, [r3, #0]
- 80052ee: 687b ldr r3, [r7, #4]
- 80052f0: 681b ldr r3, [r3, #0]
- 80052f2: f422 7290 bic.w r2, r2, #288 ; 0x120
- 80052f6: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80052f8: 687b ldr r3, [r7, #4]
- 80052fa: 681b ldr r3, [r3, #0]
- 80052fc: 689a ldr r2, [r3, #8]
- 80052fe: 687b ldr r3, [r7, #4]
- 8005300: 681b ldr r3, [r3, #0]
- 8005302: f022 0201 bic.w r2, r2, #1
- 8005306: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 8005308: 687b ldr r3, [r7, #4]
- 800530a: 2220 movs r2, #32
- 800530c: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 800530e: 687b ldr r3, [r7, #4]
- 8005310: 2200 movs r2, #0
- 8005312: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 8005314: 6878 ldr r0, [r7, #4]
- 8005316: f7fc f8cb bl 80014b0 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 800531a: e007 b.n 800532c <UART_RxISR_16BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 800531c: 687b ldr r3, [r7, #4]
- 800531e: 681b ldr r3, [r3, #0]
- 8005320: 699a ldr r2, [r3, #24]
- 8005322: 687b ldr r3, [r7, #4]
- 8005324: 681b ldr r3, [r3, #0]
- 8005326: f042 0208 orr.w r2, r2, #8
- 800532a: 619a str r2, [r3, #24]
-}
- 800532c: bf00 nop
- 800532e: 3710 adds r7, #16
- 8005330: 46bd mov sp, r7
- 8005332: bd80 pop {r7, pc}
-
-08005334 <__libc_init_array>:
- 8005334: b570 push {r4, r5, r6, lr}
- 8005336: 4e0d ldr r6, [pc, #52] ; (800536c <__libc_init_array+0x38>)
- 8005338: 4c0d ldr r4, [pc, #52] ; (8005370 <__libc_init_array+0x3c>)
- 800533a: 1ba4 subs r4, r4, r6
- 800533c: 10a4 asrs r4, r4, #2
- 800533e: 2500 movs r5, #0
- 8005340: 42a5 cmp r5, r4
- 8005342: d109 bne.n 8005358 <__libc_init_array+0x24>
- 8005344: 4e0b ldr r6, [pc, #44] ; (8005374 <__libc_init_array+0x40>)
- 8005346: 4c0c ldr r4, [pc, #48] ; (8005378 <__libc_init_array+0x44>)
- 8005348: f000 f820 bl 800538c <_init>
- 800534c: 1ba4 subs r4, r4, r6
- 800534e: 10a4 asrs r4, r4, #2
- 8005350: 2500 movs r5, #0
- 8005352: 42a5 cmp r5, r4
- 8005354: d105 bne.n 8005362 <__libc_init_array+0x2e>
- 8005356: bd70 pop {r4, r5, r6, pc}
- 8005358: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 800535c: 4798 blx r3
- 800535e: 3501 adds r5, #1
- 8005360: e7ee b.n 8005340 <__libc_init_array+0xc>
- 8005362: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8005366: 4798 blx r3
- 8005368: 3501 adds r5, #1
- 800536a: e7f2 b.n 8005352 <__libc_init_array+0x1e>
- 800536c: 080053c4 .word 0x080053c4
- 8005370: 080053c4 .word 0x080053c4
- 8005374: 080053c4 .word 0x080053c4
- 8005378: 080053cc .word 0x080053cc
-
-0800537c <memset>:
- 800537c: 4402 add r2, r0
- 800537e: 4603 mov r3, r0
- 8005380: 4293 cmp r3, r2
- 8005382: d100 bne.n 8005386 <memset+0xa>
- 8005384: 4770 bx lr
- 8005386: f803 1b01 strb.w r1, [r3], #1
- 800538a: e7f9 b.n 8005380 <memset+0x4>
-
-0800538c <_init>:
- 800538c: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800538e: bf00 nop
- 8005390: bcf8 pop {r3, r4, r5, r6, r7}
- 8005392: bc08 pop {r3}
- 8005394: 469e mov lr, r3
- 8005396: 4770 bx lr
-
-08005398 <_fini>:
- 8005398: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800539a: bf00 nop
- 800539c: bcf8 pop {r3, r4, r5, r6, r7}
- 800539e: bc08 pop {r3}
- 80053a0: 469e mov lr, r3
- 80053a2: 4770 bx lr
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-ELF_SRCS :=
-C_UPPER_SRCS :=
-CXX_SRCS :=
-C++_SRCS :=
-OBJ_SRCS :=
-S_SRCS :=
-CC_SRCS :=
-C_SRCS :=
-CPP_SRCS :=
-S_UPPER_SRCS :=
-O_SRCS :=
-CC_DEPS :=
-SIZE_OUTPUT :=
-OBJDUMP_LIST :=
-C++_DEPS :=
-EXECUTABLES :=
-OBJS :=
-C_UPPER_DEPS :=
-CXX_DEPS :=
-C_DEPS :=
-CPP_DEPS :=
-
-# Every subdirectory with source files must be described here
-SUBDIRS := \
-Core/Src \
-Core/Startup \
-Drivers/STM32F7xx_HAL_Driver/Src \
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Core/Src/stm32f7xx_hal_msp.c \
-../Core/Src/stm32f7xx_it.c \
-../Core/Src/syscalls.c \
-../Core/Src/sysmem.c \
-../Core/Src/system_stm32f7xx.c
-
-CPP_SRCS += \
-../Core/Src/encoder.cpp \
-../Core/Src/main.cpp
-
-OBJS += \
-./Core/Src/encoder.o \
-./Core/Src/main.o \
-./Core/Src/stm32f7xx_hal_msp.o \
-./Core/Src/stm32f7xx_it.o \
-./Core/Src/syscalls.o \
-./Core/Src/sysmem.o \
-./Core/Src/system_stm32f7xx.o
-
-C_DEPS += \
-./Core/Src/stm32f7xx_hal_msp.d \
-./Core/Src/stm32f7xx_it.d \
-./Core/Src/syscalls.d \
-./Core/Src/sysmem.d \
-./Core/Src/system_stm32f7xx.d
-
-CPP_DEPS += \
-./Core/Src/encoder.d \
-./Core/Src/main.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Src/encoder.o: ../Core/Src/encoder.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/encoder.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/main.o: ../Core/Src/main.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/syscalls.o: ../Core/Src/syscalls.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/sysmem.o: ../Core/Src/sysmem.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-S_SRCS += \
-../Core/Startup/startup_stm32f767zitx.s
-
-OBJS += \
-./Core/Startup/startup_stm32f767zitx.o
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Startup/%.o: ../Core/Startup/%.s
- arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
-
-OBJS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o
-
-C_DEPS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
--include ../makefile.init
-
-RM := rm -rf
-
-# All of the sources participating in the build are defined here
--include sources.mk
--include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk
--include Core/Startup/subdir.mk
--include Core/Src/subdir.mk
--include subdir.mk
--include objects.mk
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(CC_DEPS)),)
--include $(CC_DEPS)
-endif
-ifneq ($(strip $(C++_DEPS)),)
--include $(C++_DEPS)
-endif
-ifneq ($(strip $(C_UPPER_DEPS)),)
--include $(C_UPPER_DEPS)
-endif
-ifneq ($(strip $(CXX_DEPS)),)
--include $(CXX_DEPS)
-endif
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-ifneq ($(strip $(CPP_DEPS)),)
--include $(CPP_DEPS)
-endif
-endif
-
--include ../makefile.defs
-
-# Add inputs and outputs from these tool invocations to the build variables
-EXECUTABLES += \
-otto_pid_tuning.elf \
-
-SIZE_OUTPUT += \
-default.size.stdout \
-
-OBJDUMP_LIST += \
-otto_pid_tuning.list \
-
-
-# All Target
-all: otto_pid_tuning.elf secondary-outputs
-
-# Tool invocations
-otto_pid_tuning.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/utils/pid_tuning/otto_pid_tuning/STM32F767ZITX_FLASH.ld
- arm-none-eabi-g++ -o "otto_pid_tuning.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/utils/pid_tuning/otto_pid_tuning/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_pid_tuning.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
- @echo 'Finished building target: $@'
- @echo ' '
-
-default.size.stdout: $(EXECUTABLES)
- arm-none-eabi-size $(EXECUTABLES)
- @echo 'Finished building: $@'
- @echo ' '
-
-otto_pid_tuning.list: $(EXECUTABLES)
- arm-none-eabi-objdump -h -S $(EXECUTABLES) > "otto_pid_tuning.list"
- @echo 'Finished building: $@'
- @echo ' '
-
-# Other Targets
-clean:
- -$(RM) *
- -@echo ' '
-
-secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
-
-.PHONY: all clean dependents
-.SECONDARY:
-
--include ../makefile.targets
+++ /dev/null
-"Core/Src/encoder.o"
-"Core/Src/main.o"
-"Core/Src/stm32f7xx_hal_msp.o"
-"Core/Src/stm32f7xx_it.o"
-"Core/Src/syscalls.o"
-"Core/Src/sysmem.o"
-"Core/Src/system_stm32f7xx.o"
-"Core/Startup/startup_stm32f767zitx.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o"
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-USER_OBJS :=
-
-LIBS :=
-
+++ /dev/null
-
-otto_pid_tuning.elf: file format elf32-littlearm
-
-Sections:
-Idx Name Size VMA LMA File off Algn
- 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 0000540c 080001f8 080001f8 000101f8 2**3
- CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000018 08005604 08005604 00015604 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 0800561c 0800561c 00020010 2**0
- CONTENTS
- 4 .ARM 00000008 0800561c 0800561c 0001561c 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 08005624 08005624 00020010 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000008 08005624 08005624 00015624 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 0800562c 0800562c 0001562c 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 8 .data 00000010 20000000 08005630 00020000 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 00000304 20000010 08005640 00020010 2**2
- ALLOC
- 10 ._user_heap_stack 00000604 20000314 08005640 00020314 2**0
- ALLOC
- 11 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0
- CONTENTS, READONLY
- 12 .debug_info 0000dbc0 00000000 00000000 0002003e 2**0
- CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00001e4a 00000000 00000000 0002dbfe 2**0
- CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000d60 00000000 00000000 0002fa48 2**3
- CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000c78 00000000 00000000 000307a8 2**3
- CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 00028243 00000000 00000000 00031420 2**0
- CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 00009a73 00000000 00000000 00059663 2**0
- CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000f1e57 00000000 00000000 000630d6 2**0
- CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 00154f2d 2**0
- CONTENTS, READONLY
- 20 .debug_frame 00003834 00000000 00000000 00154fa8 2**2
- CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-080001f8 <__do_global_dtors_aux>:
- 80001f8: b510 push {r4, lr}
- 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
- 80001fc: 7823 ldrb r3, [r4, #0]
- 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
- 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
- 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
- 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
- 8000206: f3af 8000 nop.w
- 800020a: 2301 movs r3, #1
- 800020c: 7023 strb r3, [r4, #0]
- 800020e: bd10 pop {r4, pc}
- 8000210: 20000010 .word 0x20000010
- 8000214: 00000000 .word 0x00000000
- 8000218: 080055ec .word 0x080055ec
-
-0800021c <frame_dummy>:
- 800021c: b508 push {r3, lr}
- 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
- 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
- 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
- 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
- 8000226: f3af 8000 nop.w
- 800022a: bd08 pop {r3, pc}
- 800022c: 00000000 .word 0x00000000
- 8000230: 20000014 .word 0x20000014
- 8000234: 080055ec .word 0x080055ec
-
-08000238 <__aeabi_uldivmod>:
- 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
- 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
- 800023c: 2900 cmp r1, #0
- 800023e: bf08 it eq
- 8000240: 2800 cmpeq r0, #0
- 8000242: bf1c itt ne
- 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
- 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
- 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0>
- 8000250: f1ad 0c08 sub.w ip, sp, #8
- 8000254: e96d ce04 strd ip, lr, [sp, #-16]!
- 8000258: f000 f806 bl 8000268 <__udivmoddi4>
- 800025c: f8dd e004 ldr.w lr, [sp, #4]
- 8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
- 8000264: b004 add sp, #16
- 8000266: 4770 bx lr
-
-08000268 <__udivmoddi4>:
- 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 800026c: 9e08 ldr r6, [sp, #32]
- 800026e: 4604 mov r4, r0
- 8000270: 4688 mov r8, r1
- 8000272: 2b00 cmp r3, #0
- 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6>
- 8000276: 428a cmp r2, r1
- 8000278: 4615 mov r5, r2
- 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4>
- 800027c: fab2 f282 clz r2, r2
- 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e>
- 8000282: f1c2 0720 rsb r7, r2, #32
- 8000286: fa01 f302 lsl.w r3, r1, r2
- 800028a: fa20 f707 lsr.w r7, r0, r7
- 800028e: 4095 lsls r5, r2
- 8000290: ea47 0803 orr.w r8, r7, r3
- 8000294: 4094 lsls r4, r2
- 8000296: ea4f 4e15 mov.w lr, r5, lsr #16
- 800029a: 0c23 lsrs r3, r4, #16
- 800029c: fbb8 f7fe udiv r7, r8, lr
- 80002a0: fa1f fc85 uxth.w ip, r5
- 80002a4: fb0e 8817 mls r8, lr, r7, r8
- 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16
- 80002ac: fb07 f10c mul.w r1, r7, ip
- 80002b0: 4299 cmp r1, r3
- 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60>
- 80002b4: 18eb adds r3, r5, r3
- 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
- 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c>
- 80002be: 4299 cmp r1, r3
- 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c>
- 80002c4: 3f02 subs r7, #2
- 80002c6: 442b add r3, r5
- 80002c8: 1a5b subs r3, r3, r1
- 80002ca: b2a4 uxth r4, r4
- 80002cc: fbb3 f0fe udiv r0, r3, lr
- 80002d0: fb0e 3310 mls r3, lr, r0, r3
- 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16
- 80002d8: fb00 fc0c mul.w ip, r0, ip
- 80002dc: 45a4 cmp ip, r4
- 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c>
- 80002e0: 192c adds r4, r5, r4
- 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290>
- 80002ea: 45a4 cmp ip, r4
- 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290>
- 80002f0: 3802 subs r0, #2
- 80002f2: 442c add r4, r5
- 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16
- 80002f8: eba4 040c sub.w r4, r4, ip
- 80002fc: 2700 movs r7, #0
- 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0>
- 8000300: 40d4 lsrs r4, r2
- 8000302: 2300 movs r3, #0
- 8000304: e9c6 4300 strd r4, r3, [r6]
- 8000308: 4639 mov r1, r7
- 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 800030e: 428b cmp r3, r1
- 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe>
- 8000312: 2e00 cmp r6, #0
- 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286>
- 8000318: 2700 movs r7, #0
- 800031a: e9c6 0100 strd r0, r1, [r6]
- 800031e: 4638 mov r0, r7
- 8000320: 4639 mov r1, r7
- 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000326: fab3 f783 clz r7, r3
- 800032a: 2f00 cmp r7, #0
- 800032c: d147 bne.n 80003be <__udivmoddi4+0x156>
- 800032e: 428b cmp r3, r1
- 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0>
- 8000332: 4282 cmp r2, r0
- 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4>
- 8000338: 1a84 subs r4, r0, r2
- 800033a: eb61 0303 sbc.w r3, r1, r3
- 800033e: 2001 movs r0, #1
- 8000340: 4698 mov r8, r3
- 8000342: 2e00 cmp r6, #0
- 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0>
- 8000346: e9c6 4800 strd r4, r8, [r6]
- 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0>
- 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8>
- 800034e: deff udf #255 ; 0xff
- 8000350: fab2 f282 clz r2, r2
- 8000354: 2a00 cmp r2, #0
- 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210>
- 800035a: 1b49 subs r1, r1, r5
- 800035c: ea4f 4e15 mov.w lr, r5, lsr #16
- 8000360: fa1f f885 uxth.w r8, r5
- 8000364: 2701 movs r7, #1
- 8000366: fbb1 fcfe udiv ip, r1, lr
- 800036a: 0c23 lsrs r3, r4, #16
- 800036c: fb0e 111c mls r1, lr, ip, r1
- 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16
- 8000374: fb08 f10c mul.w r1, r8, ip
- 8000378: 4299 cmp r1, r3
- 800037a: d907 bls.n 800038c <__udivmoddi4+0x124>
- 800037c: 18eb adds r3, r5, r3
- 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
- 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122>
- 8000384: 4299 cmp r1, r3
- 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc>
- 800038a: 4684 mov ip, r0
- 800038c: 1a59 subs r1, r3, r1
- 800038e: b2a3 uxth r3, r4
- 8000390: fbb1 f0fe udiv r0, r1, lr
- 8000394: fb0e 1410 mls r4, lr, r0, r1
- 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16
- 800039c: fb08 f800 mul.w r8, r8, r0
- 80003a0: 45a0 cmp r8, r4
- 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c>
- 80003a4: 192c adds r4, r5, r4
- 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a>
- 80003ac: 45a0 cmp r8, r4
- 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6>
- 80003b2: 4618 mov r0, r3
- 80003b4: eba4 0408 sub.w r4, r4, r8
- 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16
- 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96>
- 80003be: f1c7 0c20 rsb ip, r7, #32
- 80003c2: 40bb lsls r3, r7
- 80003c4: fa22 fe0c lsr.w lr, r2, ip
- 80003c8: ea4e 0e03 orr.w lr, lr, r3
- 80003cc: fa01 f407 lsl.w r4, r1, r7
- 80003d0: fa20 f50c lsr.w r5, r0, ip
- 80003d4: fa21 f30c lsr.w r3, r1, ip
- 80003d8: ea4f 481e mov.w r8, lr, lsr #16
- 80003dc: 4325 orrs r5, r4
- 80003de: fbb3 f9f8 udiv r9, r3, r8
- 80003e2: 0c2c lsrs r4, r5, #16
- 80003e4: fb08 3319 mls r3, r8, r9, r3
- 80003e8: fa1f fa8e uxth.w sl, lr
- 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16
- 80003f0: fb09 f40a mul.w r4, r9, sl
- 80003f4: 429c cmp r4, r3
- 80003f6: fa02 f207 lsl.w r2, r2, r7
- 80003fa: fa00 f107 lsl.w r1, r0, r7
- 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0>
- 8000400: eb1e 0303 adds.w r3, lr, r3
- 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
- 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2>
- 800040c: 429c cmp r4, r3
- 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2>
- 8000412: f1a9 0902 sub.w r9, r9, #2
- 8000416: 4473 add r3, lr
- 8000418: 1b1b subs r3, r3, r4
- 800041a: b2ad uxth r5, r5
- 800041c: fbb3 f0f8 udiv r0, r3, r8
- 8000420: fb08 3310 mls r3, r8, r0, r3
- 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16
- 8000428: fb00 fa0a mul.w sl, r0, sl
- 800042c: 45a2 cmp sl, r4
- 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da>
- 8000430: eb1e 0404 adds.w r4, lr, r4
- 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa>
- 800043a: 45a2 cmp sl, r4
- 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa>
- 800043e: 3802 subs r0, #2
- 8000440: 4474 add r4, lr
- 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16
- 8000446: fba0 8902 umull r8, r9, r0, r2
- 800044a: eba4 040a sub.w r4, r4, sl
- 800044e: 454c cmp r4, r9
- 8000450: 46c2 mov sl, r8
- 8000452: 464b mov r3, r9
- 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298>
- 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294>
- 8000458: 2e00 cmp r6, #0
- 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8>
- 800045c: ebb1 050a subs.w r5, r1, sl
- 8000460: eb64 0403 sbc.w r4, r4, r3
- 8000464: fa04 fc0c lsl.w ip, r4, ip
- 8000468: 40fd lsrs r5, r7
- 800046a: 40fc lsrs r4, r7
- 800046c: ea4c 0505 orr.w r5, ip, r5
- 8000470: e9c6 5400 strd r5, r4, [r6]
- 8000474: 2700 movs r7, #0
- 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0>
- 8000478: f1c2 0320 rsb r3, r2, #32
- 800047c: fa20 f703 lsr.w r7, r0, r3
- 8000480: 4095 lsls r5, r2
- 8000482: fa01 f002 lsl.w r0, r1, r2
- 8000486: fa21 f303 lsr.w r3, r1, r3
- 800048a: ea4f 4e15 mov.w lr, r5, lsr #16
- 800048e: 4338 orrs r0, r7
- 8000490: 0c01 lsrs r1, r0, #16
- 8000492: fbb3 f7fe udiv r7, r3, lr
- 8000496: fa1f f885 uxth.w r8, r5
- 800049a: fb0e 3317 mls r3, lr, r7, r3
- 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004a2: fb07 f308 mul.w r3, r7, r8
- 80004a6: 428b cmp r3, r1
- 80004a8: fa04 f402 lsl.w r4, r4, r2
- 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256>
- 80004ae: 1869 adds r1, r5, r1
- 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
- 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae>
- 80004b6: 428b cmp r3, r1
- 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae>
- 80004ba: 3f02 subs r7, #2
- 80004bc: 4429 add r1, r5
- 80004be: 1acb subs r3, r1, r3
- 80004c0: b281 uxth r1, r0
- 80004c2: fbb3 f0fe udiv r0, r3, lr
- 80004c6: fb0e 3310 mls r3, lr, r0, r3
- 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004ce: fb00 f308 mul.w r3, r0, r8
- 80004d2: 428b cmp r3, r1
- 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e>
- 80004d6: 1869 adds r1, r5, r1
- 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
- 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6>
- 80004de: 428b cmp r3, r1
- 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6>
- 80004e2: 3802 subs r0, #2
- 80004e4: 4429 add r1, r5
- 80004e6: 1ac9 subs r1, r1, r3
- 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16
- 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe>
- 80004ee: 4637 mov r7, r6
- 80004f0: 4630 mov r0, r6
- 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0>
- 80004f4: 4607 mov r7, r0
- 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60>
- 80004f8: 4618 mov r0, r3
- 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c>
- 80004fc: 4541 cmp r1, r8
- 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0>
- 8000500: ebb8 0a02 subs.w sl, r8, r2
- 8000504: eb69 020e sbc.w r2, r9, lr
- 8000508: 3801 subs r0, #1
- 800050a: 4613 mov r3, r2
- 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0>
- 800050e: 4660 mov r0, ip
- 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e>
- 8000512: 4618 mov r0, r3
- 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da>
- 8000516: 4667 mov r7, ip
- 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256>
- 800051a: 4681 mov r9, r0
- 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0>
- 800051e: 3802 subs r0, #2
- 8000520: 442c add r4, r5
- 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c>
- 8000524: f1ac 0c02 sub.w ip, ip, #2
- 8000528: 442b add r3, r5
- 800052a: e72f b.n 800038c <__udivmoddi4+0x124>
- 800052c: 4638 mov r0, r7
- 800052e: e708 b.n 8000342 <__udivmoddi4+0xda>
- 8000530: 4637 mov r7, r6
- 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0>
-
-08000534 <__aeabi_idiv0>:
- 8000534: 4770 bx lr
- 8000536: bf00 nop
-
-08000538 <_ZN7Encoder8GetCountEv>:
- Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters);
-
-
- void Setup();
-
- int GetCount() {
- 8000538: b480 push {r7}
- 800053a: b085 sub sp, #20
- 800053c: af00 add r7, sp, #0
- 800053e: 6078 str r0, [r7, #4]
- int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_)
- 8000540: 687b ldr r3, [r7, #4]
- 8000542: 681b ldr r3, [r3, #0]
- 8000544: 681b ldr r3, [r3, #0]
- 8000546: 6a5a ldr r2, [r3, #36] ; 0x24
- - ((this->timer_->Init.Period) / 2));
- 8000548: 687b ldr r3, [r7, #4]
- 800054a: 681b ldr r3, [r3, #0]
- 800054c: 68db ldr r3, [r3, #12]
- 800054e: 085b lsrs r3, r3, #1
- 8000550: 1ad3 subs r3, r2, r3
- 8000552: 60fb str r3, [r7, #12]
- return count;
- 8000554: 68fb ldr r3, [r7, #12]
- }
- 8000556: 4618 mov r0, r3
- 8000558: 3714 adds r7, #20
- 800055a: 46bd mov sp, r7
- 800055c: f85d 7b04 ldr.w r7, [sp], #4
- 8000560: 4770 bx lr
-
-08000562 <_ZN7Encoder10ResetCountEv>:
-
- void ResetCount() {
- 8000562: b480 push {r7}
- 8000564: b083 sub sp, #12
- 8000566: af00 add r7, sp, #0
- 8000568: 6078 str r0, [r7, #4]
- //set counter to half its maximum value
- __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period / 2));
- 800056a: 687b ldr r3, [r7, #4]
- 800056c: 681b ldr r3, [r3, #0]
- 800056e: 68da ldr r2, [r3, #12]
- 8000570: 687b ldr r3, [r7, #4]
- 8000572: 681b ldr r3, [r3, #0]
- 8000574: 681b ldr r3, [r3, #0]
- 8000576: 0852 lsrs r2, r2, #1
- 8000578: 625a str r2, [r3, #36] ; 0x24
- }
- 800057a: bf00 nop
- 800057c: 370c adds r7, #12
- 800057e: 46bd mov sp, r7
- 8000580: f85d 7b04 ldr.w r7, [sp], #4
- 8000584: 4770 bx lr
-
-08000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>:
-// timer_ = timer;
-// wheel_circumference_ = wheel_circ;
-//
-//}
-
-Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) {
- 8000586: b480 push {r7}
- 8000588: b085 sub sp, #20
- 800058a: af00 add r7, sp, #0
- 800058c: 60f8 str r0, [r7, #12]
- 800058e: 60b9 str r1, [r7, #8]
- 8000590: 607a str r2, [r7, #4]
- timer_ = timer;
- 8000592: 68fb ldr r3, [r7, #12]
- 8000594: 68ba ldr r2, [r7, #8]
- 8000596: 601a str r2, [r3, #0]
- ticks_per_meter_ = ticks_per_meter;
- 8000598: 68fb ldr r3, [r7, #12]
- 800059a: 687a ldr r2, [r7, #4]
- 800059c: 615a str r2, [r3, #20]
-
-}
- 800059e: 68fb ldr r3, [r7, #12]
- 80005a0: 4618 mov r0, r3
- 80005a2: 3714 adds r7, #20
- 80005a4: 46bd mov sp, r7
- 80005a6: f85d 7b04 ldr.w r7, [sp], #4
- 80005aa: 4770 bx lr
-
-080005ac <_ZN7Encoder5SetupEv>:
-
-void Encoder::Setup() {
- 80005ac: b580 push {r7, lr}
- 80005ae: b082 sub sp, #8
- 80005b0: af00 add r7, sp, #0
- 80005b2: 6078 str r0, [r7, #4]
- HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL);
- 80005b4: 687b ldr r3, [r7, #4]
- 80005b6: 681b ldr r3, [r3, #0]
- 80005b8: 213c movs r1, #60 ; 0x3c
- 80005ba: 4618 mov r0, r3
- 80005bc: f003 f8fe bl 80037bc <HAL_TIM_Encoder_Start>
- this->ResetCount();
- 80005c0: 6878 ldr r0, [r7, #4]
- 80005c2: f7ff ffce bl 8000562 <_ZN7Encoder10ResetCountEv>
- this->previous_millis_ = 0;
- 80005c6: 687b ldr r3, [r7, #4]
- 80005c8: 2200 movs r2, #0
- 80005ca: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005cc: f001 fc12 bl 8001df4 <HAL_GetTick>
- 80005d0: 4602 mov r2, r0
- 80005d2: 687b ldr r3, [r7, #4]
- 80005d4: 609a str r2, [r3, #8]
-}
- 80005d6: bf00 nop
- 80005d8: 3708 adds r7, #8
- 80005da: 46bd mov sp, r7
- 80005dc: bd80 pop {r7, pc}
-
-080005de <_ZN7Encoder12UpdateValuesEv>:
-
-void Encoder::UpdateValues() {
- 80005de: b580 push {r7, lr}
- 80005e0: b082 sub sp, #8
- 80005e2: af00 add r7, sp, #0
- 80005e4: 6078 str r0, [r7, #4]
- this->previous_millis_ = this->current_millis_;
- 80005e6: 687b ldr r3, [r7, #4]
- 80005e8: 689a ldr r2, [r3, #8]
- 80005ea: 687b ldr r3, [r7, #4]
- 80005ec: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005ee: f001 fc01 bl 8001df4 <HAL_GetTick>
- 80005f2: 4602 mov r2, r0
- 80005f4: 687b ldr r3, [r7, #4]
- 80005f6: 609a str r2, [r3, #8]
- this->ticks_ = this->GetCount();
- 80005f8: 6878 ldr r0, [r7, #4]
- 80005fa: f7ff ff9d bl 8000538 <_ZN7Encoder8GetCountEv>
- 80005fe: 4602 mov r2, r0
- 8000600: 687b ldr r3, [r7, #4]
- 8000602: 60da str r2, [r3, #12]
- this->ResetCount();
- 8000604: 6878 ldr r0, [r7, #4]
- 8000606: f7ff ffac bl 8000562 <_ZN7Encoder10ResetCountEv>
-}
- 800060a: bf00 nop
- 800060c: 3708 adds r7, #8
- 800060e: 46bd mov sp, r7
- 8000610: bd80 pop {r7, pc}
-
-08000612 <_ZN7Encoder9GetMetersEv>:
-// float meters = ((float) this->ticks_ * this->wheel_circumference_)
-// / TICKS_PER_REVOLUTION;
-// return meters;
-//}
-
-float Encoder::GetMeters() {
- 8000612: b480 push {r7}
- 8000614: b085 sub sp, #20
- 8000616: af00 add r7, sp, #0
- 8000618: 6078 str r0, [r7, #4]
- float meters = (((float) this->ticks_) / this->ticks_per_meter_);
- 800061a: 687b ldr r3, [r7, #4]
- 800061c: 68db ldr r3, [r3, #12]
- 800061e: ee07 3a90 vmov s15, r3
- 8000622: eef8 6ae7 vcvt.f32.s32 s13, s15
- 8000626: 687b ldr r3, [r7, #4]
- 8000628: 695b ldr r3, [r3, #20]
- 800062a: ee07 3a90 vmov s15, r3
- 800062e: eeb8 7ae7 vcvt.f32.s32 s14, s15
- 8000632: eec6 7a87 vdiv.f32 s15, s13, s14
- 8000636: edc7 7a03 vstr s15, [r7, #12]
- return meters;
- 800063a: 68fb ldr r3, [r7, #12]
- 800063c: ee07 3a90 vmov s15, r3
-}
- 8000640: eeb0 0a67 vmov.f32 s0, s15
- 8000644: 3714 adds r7, #20
- 8000646: 46bd mov sp, r7
- 8000648: f85d 7b04 ldr.w r7, [sp], #4
- 800064c: 4770 bx lr
- ...
-
-08000650 <_ZN7Encoder17GetLinearVelocityEv>:
-
-
-float Encoder::GetLinearVelocity() {
- 8000650: b580 push {r7, lr}
- 8000652: b086 sub sp, #24
- 8000654: af00 add r7, sp, #0
- 8000656: 6078 str r0, [r7, #4]
- this->UpdateValues();
- 8000658: 6878 ldr r0, [r7, #4]
- 800065a: f7ff ffc0 bl 80005de <_ZN7Encoder12UpdateValuesEv>
- float meters = this->GetMeters();
- 800065e: 6878 ldr r0, [r7, #4]
- 8000660: f7ff ffd7 bl 8000612 <_ZN7Encoder9GetMetersEv>
- 8000664: ed87 0a05 vstr s0, [r7, #20]
- float deltaTime = this->current_millis_ - this->previous_millis_;
- 8000668: 687b ldr r3, [r7, #4]
- 800066a: 689a ldr r2, [r3, #8]
- 800066c: 687b ldr r3, [r7, #4]
- 800066e: 685b ldr r3, [r3, #4]
- 8000670: 1ad3 subs r3, r2, r3
- 8000672: ee07 3a90 vmov s15, r3
- 8000676: eef8 7a67 vcvt.f32.u32 s15, s15
- 800067a: edc7 7a04 vstr s15, [r7, #16]
- if (deltaTime == 0)
- 800067e: edd7 7a04 vldr s15, [r7, #16]
- 8000682: eef5 7a40 vcmp.f32 s15, #0.0
- 8000686: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800068a: d102 bne.n 8000692 <_ZN7Encoder17GetLinearVelocityEv+0x42>
- return 0;
- 800068c: f04f 0300 mov.w r3, #0
- 8000690: e00c b.n 80006ac <_ZN7Encoder17GetLinearVelocityEv+0x5c>
- float linear_velocity = (meters / (deltaTime / 1000));
- 8000692: edd7 7a04 vldr s15, [r7, #16]
- 8000696: eddf 6a09 vldr s13, [pc, #36] ; 80006bc <_ZN7Encoder17GetLinearVelocityEv+0x6c>
- 800069a: ee87 7aa6 vdiv.f32 s14, s15, s13
- 800069e: edd7 6a05 vldr s13, [r7, #20]
- 80006a2: eec6 7a87 vdiv.f32 s15, s13, s14
- 80006a6: edc7 7a03 vstr s15, [r7, #12]
- return linear_velocity;
- 80006aa: 68fb ldr r3, [r7, #12]
- 80006ac: ee07 3a90 vmov s15, r3
-}
- 80006b0: eeb0 0a67 vmov.f32 s0, s15
- 80006b4: 3718 adds r7, #24
- 80006b6: 46bd mov sp, r7
- 80006b8: bd80 pop {r7, pc}
- 80006ba: bf00 nop
- 80006bc: 447a0000 .word 0x447a0000
-
-080006c0 <_ZN8OdometryC1Ev>:
- float left_velocity_;
- float right_velocity_;
-
-
- public:
- Odometry() {
- 80006c0: b480 push {r7}
- 80006c2: b083 sub sp, #12
- 80006c4: af00 add r7, sp, #0
- 80006c6: 6078 str r0, [r7, #4]
- left_velocity_ = 0;
- 80006c8: 687b ldr r3, [r7, #4]
- 80006ca: f04f 0200 mov.w r2, #0
- 80006ce: 601a str r2, [r3, #0]
- right_velocity_ = 0;
- 80006d0: 687b ldr r3, [r7, #4]
- 80006d2: f04f 0200 mov.w r2, #0
- 80006d6: 605a str r2, [r3, #4]
- }
- 80006d8: 687b ldr r3, [r7, #4]
- 80006da: 4618 mov r0, r3
- 80006dc: 370c adds r7, #12
- 80006de: 46bd mov sp, r7
- 80006e0: f85d 7b04 ldr.w r7, [sp], #4
- 80006e4: 4770 bx lr
- ...
-
-080006e8 <_ZN8Odometry12UpdateValuesEff>:
-
- void UpdateValues(float linear_vel, float angular_vel) {
- 80006e8: b480 push {r7}
- 80006ea: b085 sub sp, #20
- 80006ec: af00 add r7, sp, #0
- 80006ee: 60f8 str r0, [r7, #12]
- 80006f0: ed87 0a02 vstr s0, [r7, #8]
- 80006f4: edc7 0a01 vstr s1, [r7, #4]
- left_velocity_ = linear_vel - (BASELINE * angular_vel)/2;
- 80006f8: edd7 7a02 vldr s15, [r7, #8]
- 80006fc: eeb7 6ae7 vcvt.f64.f32 d6, s15
- 8000700: edd7 7a01 vldr s15, [r7, #4]
- 8000704: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 8000708: ed9f 5b15 vldr d5, [pc, #84] ; 8000760 <_ZN8Odometry12UpdateValuesEff+0x78>
- 800070c: ee27 5b05 vmul.f64 d5, d7, d5
- 8000710: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 8000714: ee85 7b04 vdiv.f64 d7, d5, d4
- 8000718: ee36 7b47 vsub.f64 d7, d6, d7
- 800071c: eef7 7bc7 vcvt.f32.f64 s15, d7
- 8000720: 68fb ldr r3, [r7, #12]
- 8000722: edc3 7a00 vstr s15, [r3]
- right_velocity_ = linear_vel + (BASELINE * angular_vel)/2;
- 8000726: edd7 7a02 vldr s15, [r7, #8]
- 800072a: eeb7 6ae7 vcvt.f64.f32 d6, s15
- 800072e: edd7 7a01 vldr s15, [r7, #4]
- 8000732: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 8000736: ed9f 5b0a vldr d5, [pc, #40] ; 8000760 <_ZN8Odometry12UpdateValuesEff+0x78>
- 800073a: ee27 5b05 vmul.f64 d5, d7, d5
- 800073e: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 8000742: ee85 7b04 vdiv.f64 d7, d5, d4
- 8000746: ee36 7b07 vadd.f64 d7, d6, d7
- 800074a: eef7 7bc7 vcvt.f32.f64 s15, d7
- 800074e: 68fb ldr r3, [r7, #12]
- 8000750: edc3 7a01 vstr s15, [r3, #4]
- }
- 8000754: bf00 nop
- 8000756: 3714 adds r7, #20
- 8000758: 46bd mov sp, r7
- 800075a: f85d 7b04 ldr.w r7, [sp], #4
- 800075e: 4770 bx lr
- 8000760: 33333333 .word 0x33333333
- 8000764: 3fd33333 .word 0x3fd33333
-
-08000768 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>:
- GPIO_TypeDef *dir_gpio_port_;
- uint16_t dir_pin_;
- TIM_HandleTypeDef *pwm_timer_;
- uint32_t pwm_channel_;
-
- MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin,
- 8000768: b480 push {r7}
- 800076a: b085 sub sp, #20
- 800076c: af00 add r7, sp, #0
- 800076e: 60f8 str r0, [r7, #12]
- 8000770: 60b9 str r1, [r7, #8]
- 8000772: 603b str r3, [r7, #0]
- 8000774: 4613 mov r3, r2
- 8000776: 80fb strh r3, [r7, #6]
- GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin,
- TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) {
- this->sleep_gpio_port_ = sleep_gpio_port;
- 8000778: 68fb ldr r3, [r7, #12]
- 800077a: 68ba ldr r2, [r7, #8]
- 800077c: 601a str r2, [r3, #0]
- this->sleep_pin_ = sleep_pin;
- 800077e: 68fb ldr r3, [r7, #12]
- 8000780: 88fa ldrh r2, [r7, #6]
- 8000782: 809a strh r2, [r3, #4]
- this->dir_gpio_port_ = dir_gpio_port;
- 8000784: 68fb ldr r3, [r7, #12]
- 8000786: 683a ldr r2, [r7, #0]
- 8000788: 609a str r2, [r3, #8]
- this->dir_pin_ = dir_pin;
- 800078a: 68fb ldr r3, [r7, #12]
- 800078c: 8b3a ldrh r2, [r7, #24]
- 800078e: 819a strh r2, [r3, #12]
- this->pwm_timer_ = pwm_timer;
- 8000790: 68fb ldr r3, [r7, #12]
- 8000792: 69fa ldr r2, [r7, #28]
- 8000794: 611a str r2, [r3, #16]
- this->pwm_channel_ = pwm_channel;
- 8000796: 68fb ldr r3, [r7, #12]
- 8000798: 6a3a ldr r2, [r7, #32]
- 800079a: 615a str r2, [r3, #20]
- }
- 800079c: 68fb ldr r3, [r7, #12]
- 800079e: 4618 mov r0, r3
- 80007a0: 3714 adds r7, #20
- 80007a2: 46bd mov sp, r7
- 80007a4: f85d 7b04 ldr.w r7, [sp], #4
- 80007a8: 4770 bx lr
-
-080007aa <_ZN15MotorController5setupEv>:
-
- void setup() {
- 80007aa: b580 push {r7, lr}
- 80007ac: b082 sub sp, #8
- 80007ae: af00 add r7, sp, #0
- 80007b0: 6078 str r0, [r7, #4]
- HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_);
- 80007b2: 687b ldr r3, [r7, #4]
- 80007b4: 691a ldr r2, [r3, #16]
- 80007b6: 687b ldr r3, [r7, #4]
- 80007b8: 695b ldr r3, [r3, #20]
- 80007ba: 4619 mov r1, r3
- 80007bc: 4610 mov r0, r2
- 80007be: f002 ff27 bl 8003610 <HAL_TIM_PWM_Start>
- }
- 80007c2: bf00 nop
- 80007c4: 3708 adds r7, #8
- 80007c6: 46bd mov sp, r7
- 80007c8: bd80 pop {r7, pc}
- ...
-
-080007cc <_ZN15MotorController9set_speedEi>:
-
- void set_speed(int duty_cycle) {
- 80007cc: b580 push {r7, lr}
- 80007ce: b082 sub sp, #8
- 80007d0: af00 add r7, sp, #0
- 80007d2: 6078 str r0, [r7, #4]
- 80007d4: 6039 str r1, [r7, #0]
- if (duty_cycle >= 0) {
- 80007d6: 683b ldr r3, [r7, #0]
- 80007d8: 2b00 cmp r3, #0
- 80007da: f2c0 8083 blt.w 80008e4 <_ZN15MotorController9set_speedEi+0x118>
- //set direction to forward
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
- 80007de: 687b ldr r3, [r7, #4]
- 80007e0: 6898 ldr r0, [r3, #8]
- 80007e2: 687b ldr r3, [r7, #4]
- 80007e4: 899b ldrh r3, [r3, #12]
- 80007e6: 2201 movs r2, #1
- 80007e8: 4619 mov r1, r3
- 80007ea: f001 fded bl 80023c8 <HAL_GPIO_WritePin>
-
- //check if duty_cycle exceeds maximum
- if (duty_cycle > MAX_DUTY_CYCLE)
- 80007ee: 683b ldr r3, [r7, #0]
- 80007f0: f240 3216 movw r2, #790 ; 0x316
- 80007f4: 4293 cmp r3, r2
- 80007f6: dd3d ble.n 8000874 <_ZN15MotorController9set_speedEi+0xa8>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 80007f8: 687b ldr r3, [r7, #4]
- 80007fa: 695b ldr r3, [r3, #20]
- 80007fc: 2b00 cmp r3, #0
- 80007fe: d106 bne.n 800080e <_ZN15MotorController9set_speedEi+0x42>
- 8000800: 687b ldr r3, [r7, #4]
- 8000802: 691b ldr r3, [r3, #16]
- 8000804: 681b ldr r3, [r3, #0]
- 8000806: f240 3216 movw r2, #790 ; 0x316
- 800080a: 635a str r2, [r3, #52] ; 0x34
- 800080c: e0f5 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 800080e: 687b ldr r3, [r7, #4]
- 8000810: 695b ldr r3, [r3, #20]
- 8000812: 2b04 cmp r3, #4
- 8000814: d106 bne.n 8000824 <_ZN15MotorController9set_speedEi+0x58>
- 8000816: 687b ldr r3, [r7, #4]
- 8000818: 691b ldr r3, [r3, #16]
- 800081a: 681b ldr r3, [r3, #0]
- 800081c: f240 3216 movw r2, #790 ; 0x316
- 8000820: 639a str r2, [r3, #56] ; 0x38
- 8000822: e0ea b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000824: 687b ldr r3, [r7, #4]
- 8000826: 695b ldr r3, [r3, #20]
- 8000828: 2b08 cmp r3, #8
- 800082a: d106 bne.n 800083a <_ZN15MotorController9set_speedEi+0x6e>
- 800082c: 687b ldr r3, [r7, #4]
- 800082e: 691b ldr r3, [r3, #16]
- 8000830: 681b ldr r3, [r3, #0]
- 8000832: f240 3216 movw r2, #790 ; 0x316
- 8000836: 63da str r2, [r3, #60] ; 0x3c
- 8000838: e0df b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 800083a: 687b ldr r3, [r7, #4]
- 800083c: 695b ldr r3, [r3, #20]
- 800083e: 2b0c cmp r3, #12
- 8000840: d106 bne.n 8000850 <_ZN15MotorController9set_speedEi+0x84>
- 8000842: 687b ldr r3, [r7, #4]
- 8000844: 691b ldr r3, [r3, #16]
- 8000846: 681b ldr r3, [r3, #0]
- 8000848: f240 3216 movw r2, #790 ; 0x316
- 800084c: 641a str r2, [r3, #64] ; 0x40
- 800084e: e0d4 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000850: 687b ldr r3, [r7, #4]
- 8000852: 695b ldr r3, [r3, #20]
- 8000854: 2b10 cmp r3, #16
- 8000856: d106 bne.n 8000866 <_ZN15MotorController9set_speedEi+0x9a>
- 8000858: 687b ldr r3, [r7, #4]
- 800085a: 691b ldr r3, [r3, #16]
- 800085c: 681b ldr r3, [r3, #0]
- 800085e: f240 3216 movw r2, #790 ; 0x316
- 8000862: 659a str r2, [r3, #88] ; 0x58
- 8000864: e0c9 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000866: 687b ldr r3, [r7, #4]
- 8000868: 691b ldr r3, [r3, #16]
- 800086a: 681b ldr r3, [r3, #0]
- 800086c: f240 3216 movw r2, #790 ; 0x316
- 8000870: 65da str r2, [r3, #92] ; 0x5c
- 8000872: e0c2 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- else
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 8000874: 687b ldr r3, [r7, #4]
- 8000876: 695b ldr r3, [r3, #20]
- 8000878: 2b00 cmp r3, #0
- 800087a: d105 bne.n 8000888 <_ZN15MotorController9set_speedEi+0xbc>
- 800087c: 683a ldr r2, [r7, #0]
- 800087e: 687b ldr r3, [r7, #4]
- 8000880: 691b ldr r3, [r3, #16]
- 8000882: 681b ldr r3, [r3, #0]
- 8000884: 635a str r2, [r3, #52] ; 0x34
- 8000886: e0b8 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000888: 687b ldr r3, [r7, #4]
- 800088a: 695b ldr r3, [r3, #20]
- 800088c: 2b04 cmp r3, #4
- 800088e: d105 bne.n 800089c <_ZN15MotorController9set_speedEi+0xd0>
- 8000890: 683a ldr r2, [r7, #0]
- 8000892: 687b ldr r3, [r7, #4]
- 8000894: 691b ldr r3, [r3, #16]
- 8000896: 681b ldr r3, [r3, #0]
- 8000898: 639a str r2, [r3, #56] ; 0x38
- 800089a: e0ae b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 800089c: 687b ldr r3, [r7, #4]
- 800089e: 695b ldr r3, [r3, #20]
- 80008a0: 2b08 cmp r3, #8
- 80008a2: d105 bne.n 80008b0 <_ZN15MotorController9set_speedEi+0xe4>
- 80008a4: 683a ldr r2, [r7, #0]
- 80008a6: 687b ldr r3, [r7, #4]
- 80008a8: 691b ldr r3, [r3, #16]
- 80008aa: 681b ldr r3, [r3, #0]
- 80008ac: 63da str r2, [r3, #60] ; 0x3c
- 80008ae: e0a4 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 80008b0: 687b ldr r3, [r7, #4]
- 80008b2: 695b ldr r3, [r3, #20]
- 80008b4: 2b0c cmp r3, #12
- 80008b6: d105 bne.n 80008c4 <_ZN15MotorController9set_speedEi+0xf8>
- 80008b8: 683a ldr r2, [r7, #0]
- 80008ba: 687b ldr r3, [r7, #4]
- 80008bc: 691b ldr r3, [r3, #16]
- 80008be: 681b ldr r3, [r3, #0]
- 80008c0: 641a str r2, [r3, #64] ; 0x40
- 80008c2: e09a b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 80008c4: 687b ldr r3, [r7, #4]
- 80008c6: 695b ldr r3, [r3, #20]
- 80008c8: 2b10 cmp r3, #16
- 80008ca: d105 bne.n 80008d8 <_ZN15MotorController9set_speedEi+0x10c>
- 80008cc: 683a ldr r2, [r7, #0]
- 80008ce: 687b ldr r3, [r7, #4]
- 80008d0: 691b ldr r3, [r3, #16]
- 80008d2: 681b ldr r3, [r3, #0]
- 80008d4: 659a str r2, [r3, #88] ; 0x58
- 80008d6: e090 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 80008d8: 683a ldr r2, [r7, #0]
- 80008da: 687b ldr r3, [r7, #4]
- 80008dc: 691b ldr r3, [r3, #16]
- 80008de: 681b ldr r3, [r3, #0]
- 80008e0: 65da str r2, [r3, #92] ; 0x5c
- 80008e2: e08a b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
-
- } else if (duty_cycle < 0){
- 80008e4: 683b ldr r3, [r7, #0]
- 80008e6: 2b00 cmp r3, #0
- 80008e8: f280 8087 bge.w 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- //set direction to backwards
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET);
- 80008ec: 687b ldr r3, [r7, #4]
- 80008ee: 6898 ldr r0, [r3, #8]
- 80008f0: 687b ldr r3, [r7, #4]
- 80008f2: 899b ldrh r3, [r3, #12]
- 80008f4: 2200 movs r2, #0
- 80008f6: 4619 mov r1, r3
- 80008f8: f001 fd66 bl 80023c8 <HAL_GPIO_WritePin>
-
- //check if duty_cycle is lower than minimum
- if (duty_cycle < -MAX_DUTY_CYCLE)
- 80008fc: 683b ldr r3, [r7, #0]
- 80008fe: 4a45 ldr r2, [pc, #276] ; (8000a14 <_ZN15MotorController9set_speedEi+0x248>)
- 8000900: 4293 cmp r3, r2
- 8000902: da3d bge.n 8000980 <_ZN15MotorController9set_speedEi+0x1b4>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 8000904: 687b ldr r3, [r7, #4]
- 8000906: 695b ldr r3, [r3, #20]
- 8000908: 2b00 cmp r3, #0
- 800090a: d106 bne.n 800091a <_ZN15MotorController9set_speedEi+0x14e>
- 800090c: 687b ldr r3, [r7, #4]
- 800090e: 691b ldr r3, [r3, #16]
- 8000910: 681b ldr r3, [r3, #0]
- 8000912: f240 3216 movw r2, #790 ; 0x316
- 8000916: 635a str r2, [r3, #52] ; 0x34
- 8000918: e06f b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 800091a: 687b ldr r3, [r7, #4]
- 800091c: 695b ldr r3, [r3, #20]
- 800091e: 2b04 cmp r3, #4
- 8000920: d106 bne.n 8000930 <_ZN15MotorController9set_speedEi+0x164>
- 8000922: 687b ldr r3, [r7, #4]
- 8000924: 691b ldr r3, [r3, #16]
- 8000926: 681b ldr r3, [r3, #0]
- 8000928: f240 3216 movw r2, #790 ; 0x316
- 800092c: 639a str r2, [r3, #56] ; 0x38
- 800092e: e064 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000930: 687b ldr r3, [r7, #4]
- 8000932: 695b ldr r3, [r3, #20]
- 8000934: 2b08 cmp r3, #8
- 8000936: d106 bne.n 8000946 <_ZN15MotorController9set_speedEi+0x17a>
- 8000938: 687b ldr r3, [r7, #4]
- 800093a: 691b ldr r3, [r3, #16]
- 800093c: 681b ldr r3, [r3, #0]
- 800093e: f240 3216 movw r2, #790 ; 0x316
- 8000942: 63da str r2, [r3, #60] ; 0x3c
- 8000944: e059 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000946: 687b ldr r3, [r7, #4]
- 8000948: 695b ldr r3, [r3, #20]
- 800094a: 2b0c cmp r3, #12
- 800094c: d106 bne.n 800095c <_ZN15MotorController9set_speedEi+0x190>
- 800094e: 687b ldr r3, [r7, #4]
- 8000950: 691b ldr r3, [r3, #16]
- 8000952: 681b ldr r3, [r3, #0]
- 8000954: f240 3216 movw r2, #790 ; 0x316
- 8000958: 641a str r2, [r3, #64] ; 0x40
- 800095a: e04e b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 800095c: 687b ldr r3, [r7, #4]
- 800095e: 695b ldr r3, [r3, #20]
- 8000960: 2b10 cmp r3, #16
- 8000962: d106 bne.n 8000972 <_ZN15MotorController9set_speedEi+0x1a6>
- 8000964: 687b ldr r3, [r7, #4]
- 8000966: 691b ldr r3, [r3, #16]
- 8000968: 681b ldr r3, [r3, #0]
- 800096a: f240 3216 movw r2, #790 ; 0x316
- 800096e: 659a str r2, [r3, #88] ; 0x58
- 8000970: e043 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000972: 687b ldr r3, [r7, #4]
- 8000974: 691b ldr r3, [r3, #16]
- 8000976: 681b ldr r3, [r3, #0]
- 8000978: f240 3216 movw r2, #790 ; 0x316
- 800097c: 65da str r2, [r3, #92] ; 0x5c
- 800097e: e03c b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- else
- //invert sign to make duty_cycle positive
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 8000980: 687b ldr r3, [r7, #4]
- 8000982: 695b ldr r3, [r3, #20]
- 8000984: 2b00 cmp r3, #0
- 8000986: d106 bne.n 8000996 <_ZN15MotorController9set_speedEi+0x1ca>
- 8000988: 683b ldr r3, [r7, #0]
- 800098a: 425a negs r2, r3
- 800098c: 687b ldr r3, [r7, #4]
- 800098e: 691b ldr r3, [r3, #16]
- 8000990: 681b ldr r3, [r3, #0]
- 8000992: 635a str r2, [r3, #52] ; 0x34
- 8000994: e031 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 8000996: 687b ldr r3, [r7, #4]
- 8000998: 695b ldr r3, [r3, #20]
- 800099a: 2b04 cmp r3, #4
- 800099c: d106 bne.n 80009ac <_ZN15MotorController9set_speedEi+0x1e0>
- 800099e: 683b ldr r3, [r7, #0]
- 80009a0: 425a negs r2, r3
- 80009a2: 687b ldr r3, [r7, #4]
- 80009a4: 691b ldr r3, [r3, #16]
- 80009a6: 681b ldr r3, [r3, #0]
- 80009a8: 639a str r2, [r3, #56] ; 0x38
- 80009aa: e026 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 80009ac: 687b ldr r3, [r7, #4]
- 80009ae: 695b ldr r3, [r3, #20]
- 80009b0: 2b08 cmp r3, #8
- 80009b2: d106 bne.n 80009c2 <_ZN15MotorController9set_speedEi+0x1f6>
- 80009b4: 683b ldr r3, [r7, #0]
- 80009b6: 425a negs r2, r3
- 80009b8: 687b ldr r3, [r7, #4]
- 80009ba: 691b ldr r3, [r3, #16]
- 80009bc: 681b ldr r3, [r3, #0]
- 80009be: 63da str r2, [r3, #60] ; 0x3c
- 80009c0: e01b b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 80009c2: 687b ldr r3, [r7, #4]
- 80009c4: 695b ldr r3, [r3, #20]
- 80009c6: 2b0c cmp r3, #12
- 80009c8: d106 bne.n 80009d8 <_ZN15MotorController9set_speedEi+0x20c>
- 80009ca: 683b ldr r3, [r7, #0]
- 80009cc: 425a negs r2, r3
- 80009ce: 687b ldr r3, [r7, #4]
- 80009d0: 691b ldr r3, [r3, #16]
- 80009d2: 681b ldr r3, [r3, #0]
- 80009d4: 641a str r2, [r3, #64] ; 0x40
- 80009d6: e010 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 80009d8: 687b ldr r3, [r7, #4]
- 80009da: 695b ldr r3, [r3, #20]
- 80009dc: 2b10 cmp r3, #16
- 80009de: d106 bne.n 80009ee <_ZN15MotorController9set_speedEi+0x222>
- 80009e0: 683b ldr r3, [r7, #0]
- 80009e2: 425a negs r2, r3
- 80009e4: 687b ldr r3, [r7, #4]
- 80009e6: 691b ldr r3, [r3, #16]
- 80009e8: 681b ldr r3, [r3, #0]
- 80009ea: 659a str r2, [r3, #88] ; 0x58
- 80009ec: e005 b.n 80009fa <_ZN15MotorController9set_speedEi+0x22e>
- 80009ee: 683b ldr r3, [r7, #0]
- 80009f0: 425a negs r2, r3
- 80009f2: 687b ldr r3, [r7, #4]
- 80009f4: 691b ldr r3, [r3, #16]
- 80009f6: 681b ldr r3, [r3, #0]
- 80009f8: 65da str r2, [r3, #92] ; 0x5c
- }
-
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- 80009fa: 687b ldr r3, [r7, #4]
- 80009fc: 6818 ldr r0, [r3, #0]
- 80009fe: 687b ldr r3, [r7, #4]
- 8000a00: 889b ldrh r3, [r3, #4]
- 8000a02: 2201 movs r2, #1
- 8000a04: 4619 mov r1, r3
- 8000a06: f001 fcdf bl 80023c8 <HAL_GPIO_WritePin>
-
- }
- 8000a0a: bf00 nop
- 8000a0c: 3708 adds r7, #8
- 8000a0e: 46bd mov sp, r7
- 8000a10: bd80 pop {r7, pc}
- 8000a12: bf00 nop
- 8000a14: fffffcea .word 0xfffffcea
-
-08000a18 <_ZN15MotorController5coastEv>:
- void brake() {
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- }
-
- void coast() {
- 8000a18: b580 push {r7, lr}
- 8000a1a: b082 sub sp, #8
- 8000a1c: af00 add r7, sp, #0
- 8000a1e: 6078 str r0, [r7, #4]
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET);
- 8000a20: 687b ldr r3, [r7, #4]
- 8000a22: 6818 ldr r0, [r3, #0]
- 8000a24: 687b ldr r3, [r7, #4]
- 8000a26: 889b ldrh r3, [r3, #4]
- 8000a28: 2200 movs r2, #0
- 8000a2a: 4619 mov r1, r3
- 8000a2c: f001 fccc bl 80023c8 <HAL_GPIO_WritePin>
- }
- 8000a30: bf00 nop
- 8000a32: 3708 adds r7, #8
- 8000a34: 46bd mov sp, r7
- 8000a36: bd80 pop {r7, pc}
-
-08000a38 <_ZN3PidC1Efff>:
- float previous_error_;
-
- int min_;
- int max_;
-
- Pid(float kp, float ki, float kd) {
- 8000a38: b480 push {r7}
- 8000a3a: b085 sub sp, #20
- 8000a3c: af00 add r7, sp, #0
- 8000a3e: 60f8 str r0, [r7, #12]
- 8000a40: ed87 0a02 vstr s0, [r7, #8]
- 8000a44: edc7 0a01 vstr s1, [r7, #4]
- 8000a48: ed87 1a00 vstr s2, [r7]
- this->kp_ = kp;
- 8000a4c: 68fb ldr r3, [r7, #12]
- 8000a4e: 68ba ldr r2, [r7, #8]
- 8000a50: 601a str r2, [r3, #0]
- this->ki_ = ki;
- 8000a52: 68fb ldr r3, [r7, #12]
- 8000a54: 687a ldr r2, [r7, #4]
- 8000a56: 605a str r2, [r3, #4]
- this->kd_ = kd;
- 8000a58: 68fb ldr r3, [r7, #12]
- 8000a5a: 683a ldr r2, [r7, #0]
- 8000a5c: 609a str r2, [r3, #8]
-
- this->error_ = 0;
- 8000a5e: 68fb ldr r3, [r7, #12]
- 8000a60: f04f 0200 mov.w r2, #0
- 8000a64: 60da str r2, [r3, #12]
- this->setpoint_ = 0;
- 8000a66: 68fb ldr r3, [r7, #12]
- 8000a68: f04f 0200 mov.w r2, #0
- 8000a6c: 611a str r2, [r3, #16]
-
- this->previous_error_ = 0;
- 8000a6e: 68fb ldr r3, [r7, #12]
- 8000a70: f04f 0200 mov.w r2, #0
- 8000a74: 619a str r2, [r3, #24]
- this->error_sum_ = 0;
- 8000a76: 68fb ldr r3, [r7, #12]
- 8000a78: f04f 0200 mov.w r2, #0
- 8000a7c: 615a str r2, [r3, #20]
-
- this->min_ = -MAX_DUTY_CYCLE;
- 8000a7e: 68fb ldr r3, [r7, #12]
- 8000a80: 4a06 ldr r2, [pc, #24] ; (8000a9c <_ZN3PidC1Efff+0x64>)
- 8000a82: 61da str r2, [r3, #28]
- this->max_ = MAX_DUTY_CYCLE;
- 8000a84: 68fb ldr r3, [r7, #12]
- 8000a86: f240 3216 movw r2, #790 ; 0x316
- 8000a8a: 621a str r2, [r3, #32]
-
- }
- 8000a8c: 68fb ldr r3, [r7, #12]
- 8000a8e: 4618 mov r0, r3
- 8000a90: 3714 adds r7, #20
- 8000a92: 46bd mov sp, r7
- 8000a94: f85d 7b04 ldr.w r7, [sp], #4
- 8000a98: 4770 bx lr
- 8000a9a: bf00 nop
- 8000a9c: fffffcea .word 0xfffffcea
-
-08000aa0 <_ZN3Pid6configEfff>:
-
- void config(float kp, float ki, float kd) {
- 8000aa0: b480 push {r7}
- 8000aa2: b085 sub sp, #20
- 8000aa4: af00 add r7, sp, #0
- 8000aa6: 60f8 str r0, [r7, #12]
- 8000aa8: ed87 0a02 vstr s0, [r7, #8]
- 8000aac: edc7 0a01 vstr s1, [r7, #4]
- 8000ab0: ed87 1a00 vstr s2, [r7]
- this->kp_ = kp;
- 8000ab4: 68fb ldr r3, [r7, #12]
- 8000ab6: 68ba ldr r2, [r7, #8]
- 8000ab8: 601a str r2, [r3, #0]
- this->ki_ = ki;
- 8000aba: 68fb ldr r3, [r7, #12]
- 8000abc: 687a ldr r2, [r7, #4]
- 8000abe: 605a str r2, [r3, #4]
- this->kd_ = kd;
- 8000ac0: 68fb ldr r3, [r7, #12]
- 8000ac2: 683a ldr r2, [r7, #0]
- 8000ac4: 609a str r2, [r3, #8]
-
- this->error_ = 0;
- 8000ac6: 68fb ldr r3, [r7, #12]
- 8000ac8: f04f 0200 mov.w r2, #0
- 8000acc: 60da str r2, [r3, #12]
- this->setpoint_ = 0;
- 8000ace: 68fb ldr r3, [r7, #12]
- 8000ad0: f04f 0200 mov.w r2, #0
- 8000ad4: 611a str r2, [r3, #16]
-
- this->previous_error_ = 0;
- 8000ad6: 68fb ldr r3, [r7, #12]
- 8000ad8: f04f 0200 mov.w r2, #0
- 8000adc: 619a str r2, [r3, #24]
- this->error_sum_ = 0;
- 8000ade: 68fb ldr r3, [r7, #12]
- 8000ae0: f04f 0200 mov.w r2, #0
- 8000ae4: 615a str r2, [r3, #20]
-
- }
- 8000ae6: bf00 nop
- 8000ae8: 3714 adds r7, #20
- 8000aea: 46bd mov sp, r7
- 8000aec: f85d 7b04 ldr.w r7, [sp], #4
- 8000af0: 4770 bx lr
-
-08000af2 <_ZN3Pid3setEf>:
-
- void set(float setpoint) {
- 8000af2: b480 push {r7}
- 8000af4: b083 sub sp, #12
- 8000af6: af00 add r7, sp, #0
- 8000af8: 6078 str r0, [r7, #4]
- 8000afa: ed87 0a00 vstr s0, [r7]
- this->setpoint_ = setpoint;
- 8000afe: 687b ldr r3, [r7, #4]
- 8000b00: 683a ldr r2, [r7, #0]
- 8000b02: 611a str r2, [r3, #16]
- }
- 8000b04: bf00 nop
- 8000b06: 370c adds r7, #12
- 8000b08: 46bd mov sp, r7
- 8000b0a: f85d 7b04 ldr.w r7, [sp], #4
- 8000b0e: 4770 bx lr
-
-08000b10 <_ZN3Pid6updateEf>:
-
- int update(float measure) {
- 8000b10: b480 push {r7}
- 8000b12: b085 sub sp, #20
- 8000b14: af00 add r7, sp, #0
- 8000b16: 6078 str r0, [r7, #4]
- 8000b18: ed87 0a00 vstr s0, [r7]
-
- this->error_ = this->setpoint_ - measure;
- 8000b1c: 687b ldr r3, [r7, #4]
- 8000b1e: ed93 7a04 vldr s14, [r3, #16]
- 8000b22: edd7 7a00 vldr s15, [r7]
- 8000b26: ee77 7a67 vsub.f32 s15, s14, s15
- 8000b2a: 687b ldr r3, [r7, #4]
- 8000b2c: edc3 7a03 vstr s15, [r3, #12]
-
- //proportional term
- float output = this->error_ * this->kp_;
- 8000b30: 687b ldr r3, [r7, #4]
- 8000b32: ed93 7a03 vldr s14, [r3, #12]
- 8000b36: 687b ldr r3, [r7, #4]
- 8000b38: edd3 7a00 vldr s15, [r3]
- 8000b3c: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b40: edc7 7a03 vstr s15, [r7, #12]
-
- //integral term without windup
- error_sum_ += this->error_;
- 8000b44: 687b ldr r3, [r7, #4]
- 8000b46: ed93 7a05 vldr s14, [r3, #20]
- 8000b4a: 687b ldr r3, [r7, #4]
- 8000b4c: edd3 7a03 vldr s15, [r3, #12]
- 8000b50: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b54: 687b ldr r3, [r7, #4]
- 8000b56: edc3 7a05 vstr s15, [r3, #20]
- output += error_sum_ * this->ki_;
- 8000b5a: 687b ldr r3, [r7, #4]
- 8000b5c: ed93 7a05 vldr s14, [r3, #20]
- 8000b60: 687b ldr r3, [r7, #4]
- 8000b62: edd3 7a01 vldr s15, [r3, #4]
- 8000b66: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b6a: ed97 7a03 vldr s14, [r7, #12]
- 8000b6e: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b72: edc7 7a03 vstr s15, [r7, #12]
-
- //derivative term
- output += (this->error_ - this->previous_error_) * kd_;
- 8000b76: 687b ldr r3, [r7, #4]
- 8000b78: ed93 7a03 vldr s14, [r3, #12]
- 8000b7c: 687b ldr r3, [r7, #4]
- 8000b7e: edd3 7a06 vldr s15, [r3, #24]
- 8000b82: ee37 7a67 vsub.f32 s14, s14, s15
- 8000b86: 687b ldr r3, [r7, #4]
- 8000b88: edd3 7a02 vldr s15, [r3, #8]
- 8000b8c: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b90: ed97 7a03 vldr s14, [r7, #12]
- 8000b94: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b98: edc7 7a03 vstr s15, [r7, #12]
- this->previous_error_ = this->error_;
- 8000b9c: 687b ldr r3, [r7, #4]
- 8000b9e: 68da ldr r2, [r3, #12]
- 8000ba0: 687b ldr r3, [r7, #4]
- 8000ba2: 619a str r2, [r3, #24]
-
- int integer_output = static_cast<int> (output);
- 8000ba4: edd7 7a03 vldr s15, [r7, #12]
- 8000ba8: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8000bac: ee17 3a90 vmov r3, s15
- 8000bb0: 60bb str r3, [r7, #8]
-// if(integer_output > this->max_)
-// integer_output = this->max_;
-// else if (integer_output < this->min_)
-// integer_output = this->min_;
-
- return integer_output;
- 8000bb2: 68bb ldr r3, [r7, #8]
-
- }
- 8000bb4: 4618 mov r0, r3
- 8000bb6: 3714 adds r7, #20
- 8000bb8: 46bd mov sp, r7
- 8000bba: f85d 7b04 ldr.w r7, [sp], #4
- 8000bbe: 4770 bx lr
-
-08000bc0 <main>:
-
-/**
- * @brief The application entry point.
- * @retval int
- */
-int main(void) {
- 8000bc0: b580 push {r7, lr}
- 8000bc2: af00 add r7, sp, #0
- /* USER CODE END 1 */
-
- /* MCU Configuration--------------------------------------------------------*/
-
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
- 8000bc4: f001 f8c5 bl 8001d52 <HAL_Init>
- /* USER CODE BEGIN Init */
-
- /* USER CODE END Init */
-
- /* Configure the system clock */
- SystemClock_Config();
- 8000bc8: f000 f842 bl 8000c50 <_Z18SystemClock_Configv>
- /* USER CODE BEGIN SysInit */
-
- /* USER CODE END SysInit */
-
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- 8000bcc: f000 fb1a bl 8001204 <_ZL12MX_GPIO_Initv>
- MX_TIM2_Init();
- 8000bd0: f000 f8e4 bl 8000d9c <_ZL12MX_TIM2_Initv>
- MX_TIM3_Init();
- 8000bd4: f000 f940 bl 8000e58 <_ZL12MX_TIM3_Initv>
- MX_TIM4_Init();
- 8000bd8: f000 f99c bl 8000f14 <_ZL12MX_TIM4_Initv>
- MX_TIM5_Init();
- 8000bdc: f000 fa3a bl 8001054 <_ZL12MX_TIM5_Initv>
- MX_USART6_UART_Init();
- 8000be0: f000 fada bl 8001198 <_ZL19MX_USART6_UART_Initv>
- MX_TIM6_Init();
- 8000be4: f000 fa96 bl 8001114 <_ZL12MX_TIM6_Initv>
-
- /* Initialize interrupts */
- MX_NVIC_Init();
- 8000be8: f000 f8bc bl 8000d64 <_ZL12MX_NVIC_Initv>
- /* USER CODE BEGIN 2 */
-
- left_encoder.Setup();
- 8000bec: 480f ldr r0, [pc, #60] ; (8000c2c <main+0x6c>)
- 8000bee: f7ff fcdd bl 80005ac <_ZN7Encoder5SetupEv>
- right_encoder.Setup();
- 8000bf2: 480f ldr r0, [pc, #60] ; (8000c30 <main+0x70>)
- 8000bf4: f7ff fcda bl 80005ac <_ZN7Encoder5SetupEv>
-
- left_motor.setup();
- 8000bf8: 480e ldr r0, [pc, #56] ; (8000c34 <main+0x74>)
- 8000bfa: f7ff fdd6 bl 80007aa <_ZN15MotorController5setupEv>
- right_motor.setup();
- 8000bfe: 480e ldr r0, [pc, #56] ; (8000c38 <main+0x78>)
- 8000c00: f7ff fdd3 bl 80007aa <_ZN15MotorController5setupEv>
-
- left_motor.coast();
- 8000c04: 480b ldr r0, [pc, #44] ; (8000c34 <main+0x74>)
- 8000c06: f7ff ff07 bl 8000a18 <_ZN15MotorController5coastEv>
- right_motor.coast();
- 8000c0a: 480b ldr r0, [pc, #44] ; (8000c38 <main+0x78>)
- 8000c0c: f7ff ff04 bl 8000a18 <_ZN15MotorController5coastEv>
-
- tx_buffer = (uint8_t*) &output_msg;
- 8000c10: 4b0a ldr r3, [pc, #40] ; (8000c3c <main+0x7c>)
- 8000c12: 4a0b ldr r2, [pc, #44] ; (8000c40 <main+0x80>)
- 8000c14: 601a str r2, [r3, #0]
- rx_buffer = (uint8_t*) &input_msg;
- 8000c16: 4b0b ldr r3, [pc, #44] ; (8000c44 <main+0x84>)
- 8000c18: 4a0b ldr r2, [pc, #44] ; (8000c48 <main+0x88>)
- 8000c1a: 601a str r2, [r3, #0]
-
- //Enables UART RX interrupt
- HAL_UART_Receive_IT(&huart6, rx_buffer, 28);
- 8000c1c: 4b09 ldr r3, [pc, #36] ; (8000c44 <main+0x84>)
- 8000c1e: 681b ldr r3, [r3, #0]
- 8000c20: 221c movs r2, #28
- 8000c22: 4619 mov r1, r3
- 8000c24: 4809 ldr r0, [pc, #36] ; (8000c4c <main+0x8c>)
- 8000c26: f003 fe31 bl 800488c <HAL_UART_Receive_IT>
-
- /* USER CODE END 2 */
-
- /* Infinite loop */
- /* USER CODE BEGIN WHILE */
- while (1) {
- 8000c2a: e7fe b.n 8000c2a <main+0x6a>
- 8000c2c: 20000204 .word 0x20000204
- 8000c30: 200001ec .word 0x200001ec
- 8000c34: 200002c4 .word 0x200002c4
- 8000c38: 200002ac .word 0x200002ac
- 8000c3c: 200002dc .word 0x200002dc
- 8000c40: 20000300 .word 0x20000300
- 8000c44: 200002e0 .word 0x200002e0
- 8000c48: 200002e4 .word 0x200002e4
- 8000c4c: 2000016c .word 0x2000016c
-
-08000c50 <_Z18SystemClock_Configv>:
-
-/**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void) {
- 8000c50: b580 push {r7, lr}
- 8000c52: b0b8 sub sp, #224 ; 0xe0
- 8000c54: af00 add r7, sp, #0
- RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
- 8000c56: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000c5a: 2234 movs r2, #52 ; 0x34
- 8000c5c: 2100 movs r1, #0
- 8000c5e: 4618 mov r0, r3
- 8000c60: f004 fcbc bl 80055dc <memset>
- RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
- 8000c64: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000c68: 2200 movs r2, #0
- 8000c6a: 601a str r2, [r3, #0]
- 8000c6c: 605a str r2, [r3, #4]
- 8000c6e: 609a str r2, [r3, #8]
- 8000c70: 60da str r2, [r3, #12]
- 8000c72: 611a str r2, [r3, #16]
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
- 8000c74: f107 0308 add.w r3, r7, #8
- 8000c78: 2290 movs r2, #144 ; 0x90
- 8000c7a: 2100 movs r1, #0
- 8000c7c: 4618 mov r0, r3
- 8000c7e: f004 fcad bl 80055dc <memset>
-
- /** Configure the main internal regulator output voltage
- */
- __HAL_RCC_PWR_CLK_ENABLE();
- 8000c82: 4b36 ldr r3, [pc, #216] ; (8000d5c <_Z18SystemClock_Configv+0x10c>)
- 8000c84: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000c86: 4a35 ldr r2, [pc, #212] ; (8000d5c <_Z18SystemClock_Configv+0x10c>)
- 8000c88: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8000c8c: 6413 str r3, [r2, #64] ; 0x40
- 8000c8e: 4b33 ldr r3, [pc, #204] ; (8000d5c <_Z18SystemClock_Configv+0x10c>)
- 8000c90: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000c92: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000c96: 607b str r3, [r7, #4]
- 8000c98: 687b ldr r3, [r7, #4]
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 8000c9a: 4b31 ldr r3, [pc, #196] ; (8000d60 <_Z18SystemClock_Configv+0x110>)
- 8000c9c: 681b ldr r3, [r3, #0]
- 8000c9e: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 8000ca2: 4a2f ldr r2, [pc, #188] ; (8000d60 <_Z18SystemClock_Configv+0x110>)
- 8000ca4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000ca8: 6013 str r3, [r2, #0]
- 8000caa: 4b2d ldr r3, [pc, #180] ; (8000d60 <_Z18SystemClock_Configv+0x110>)
- 8000cac: 681b ldr r3, [r3, #0]
- 8000cae: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8000cb2: 603b str r3, [r7, #0]
- 8000cb4: 683b ldr r3, [r7, #0]
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8000cb6: 2302 movs r3, #2
- 8000cb8: f8c7 30ac str.w r3, [r7, #172] ; 0xac
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000cbc: 2301 movs r3, #1
- 8000cbe: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000cc2: 2310 movs r3, #16
- 8000cc4: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8000cc8: 2300 movs r3, #0
- 8000cca: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- 8000cce: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000cd2: 4618 mov r0, r3
- 8000cd4: f001 fbaa bl 800242c <HAL_RCC_OscConfig>
- 8000cd8: 4603 mov r3, r0
- 8000cda: 2b00 cmp r3, #0
- 8000cdc: bf14 ite ne
- 8000cde: 2301 movne r3, #1
- 8000ce0: 2300 moveq r3, #0
- 8000ce2: b2db uxtb r3, r3
- 8000ce4: 2b00 cmp r3, #0
- 8000ce6: d001 beq.n 8000cec <_Z18SystemClock_Configv+0x9c>
- Error_Handler();
- 8000ce8: f000 fd88 bl 80017fc <Error_Handler>
- }
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
- 8000cec: 230f movs r3, #15
- 8000cee: f8c7 3098 str.w r3, [r7, #152] ; 0x98
- | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 8000cf2: 2300 movs r3, #0
- 8000cf4: f8c7 309c str.w r3, [r7, #156] ; 0x9c
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000cf8: 2300 movs r3, #0
- 8000cfa: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8000cfe: 2300 movs r3, #0
- 8000d00: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8000d04: 2300 movs r3, #0
- 8000d06: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
-
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
- 8000d0a: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000d0e: 2100 movs r1, #0
- 8000d10: 4618 mov r0, r3
- 8000d12: f001 fdfd bl 8002910 <HAL_RCC_ClockConfig>
- 8000d16: 4603 mov r3, r0
- 8000d18: 2b00 cmp r3, #0
- 8000d1a: bf14 ite ne
- 8000d1c: 2301 movne r3, #1
- 8000d1e: 2300 moveq r3, #0
- 8000d20: b2db uxtb r3, r3
- 8000d22: 2b00 cmp r3, #0
- 8000d24: d001 beq.n 8000d2a <_Z18SystemClock_Configv+0xda>
- Error_Handler();
- 8000d26: f000 fd69 bl 80017fc <Error_Handler>
- }
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
- 8000d2a: f44f 6300 mov.w r3, #2048 ; 0x800
- 8000d2e: 60bb str r3, [r7, #8]
- PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
- 8000d30: 2300 movs r3, #0
- 8000d32: 663b str r3, [r7, #96] ; 0x60
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
- 8000d34: f107 0308 add.w r3, r7, #8
- 8000d38: 4618 mov r0, r3
- 8000d3a: f001 ffb7 bl 8002cac <HAL_RCCEx_PeriphCLKConfig>
- 8000d3e: 4603 mov r3, r0
- 8000d40: 2b00 cmp r3, #0
- 8000d42: bf14 ite ne
- 8000d44: 2301 movne r3, #1
- 8000d46: 2300 moveq r3, #0
- 8000d48: b2db uxtb r3, r3
- 8000d4a: 2b00 cmp r3, #0
- 8000d4c: d001 beq.n 8000d52 <_Z18SystemClock_Configv+0x102>
- Error_Handler();
- 8000d4e: f000 fd55 bl 80017fc <Error_Handler>
- }
-}
- 8000d52: bf00 nop
- 8000d54: 37e0 adds r7, #224 ; 0xe0
- 8000d56: 46bd mov sp, r7
- 8000d58: bd80 pop {r7, pc}
- 8000d5a: bf00 nop
- 8000d5c: 40023800 .word 0x40023800
- 8000d60: 40007000 .word 0x40007000
-
-08000d64 <_ZL12MX_NVIC_Initv>:
-
-/**
- * @brief NVIC Configuration.
- * @retval None
- */
-static void MX_NVIC_Init(void) {
- 8000d64: b580 push {r7, lr}
- 8000d66: af00 add r7, sp, #0
- /* TIM3_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1);
- 8000d68: 2201 movs r2, #1
- 8000d6a: 2102 movs r1, #2
- 8000d6c: 201d movs r0, #29
- 8000d6e: f001 f928 bl 8001fc2 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM3_IRQn);
- 8000d72: 201d movs r0, #29
- 8000d74: f001 f941 bl 8001ffa <HAL_NVIC_EnableIRQ>
- /* TIM6_DAC_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2);
- 8000d78: 2202 movs r2, #2
- 8000d7a: 2102 movs r1, #2
- 8000d7c: 2036 movs r0, #54 ; 0x36
- 8000d7e: f001 f920 bl 8001fc2 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
- 8000d82: 2036 movs r0, #54 ; 0x36
- 8000d84: f001 f939 bl 8001ffa <HAL_NVIC_EnableIRQ>
- /* USART6_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(USART6_IRQn, 2, 0);
- 8000d88: 2200 movs r2, #0
- 8000d8a: 2102 movs r1, #2
- 8000d8c: 2047 movs r0, #71 ; 0x47
- 8000d8e: f001 f918 bl 8001fc2 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(USART6_IRQn);
- 8000d92: 2047 movs r0, #71 ; 0x47
- 8000d94: f001 f931 bl 8001ffa <HAL_NVIC_EnableIRQ>
-}
- 8000d98: bf00 nop
- 8000d9a: bd80 pop {r7, pc}
-
-08000d9c <_ZL12MX_TIM2_Initv>:
-/**
- * @brief TIM2 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM2_Init(void) {
- 8000d9c: b580 push {r7, lr}
- 8000d9e: b08c sub sp, #48 ; 0x30
- 8000da0: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM2_Init 0 */
-
- /* USER CODE END TIM2_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = { 0 };
- 8000da2: f107 030c add.w r3, r7, #12
- 8000da6: 2224 movs r2, #36 ; 0x24
- 8000da8: 2100 movs r1, #0
- 8000daa: 4618 mov r0, r3
- 8000dac: f004 fc16 bl 80055dc <memset>
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000db0: 463b mov r3, r7
- 8000db2: 2200 movs r2, #0
- 8000db4: 601a str r2, [r3, #0]
- 8000db6: 605a str r2, [r3, #4]
- 8000db8: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM2_Init 1 */
-
- /* USER CODE END TIM2_Init 1 */
- htim2.Instance = TIM2;
- 8000dba: 4b26 ldr r3, [pc, #152] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dbc: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
- 8000dc0: 601a str r2, [r3, #0]
- htim2.Init.Prescaler = 0;
- 8000dc2: 4b24 ldr r3, [pc, #144] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dc4: 2200 movs r2, #0
- 8000dc6: 605a str r2, [r3, #4]
- htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000dc8: 4b22 ldr r3, [pc, #136] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dca: 2200 movs r2, #0
- 8000dcc: 609a str r2, [r3, #8]
- htim2.Init.Period = 4294967295;
- 8000dce: 4b21 ldr r3, [pc, #132] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dd0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000dd4: 60da str r2, [r3, #12]
- htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000dd6: 4b1f ldr r3, [pc, #124] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dd8: 2200 movs r2, #0
- 8000dda: 611a str r2, [r3, #16]
- htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000ddc: 4b1d ldr r3, [pc, #116] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000dde: 2200 movs r2, #0
- 8000de0: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8000de2: 2303 movs r3, #3
- 8000de4: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8000de6: 2300 movs r3, #0
- 8000de8: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8000dea: 2301 movs r3, #1
- 8000dec: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8000dee: 2300 movs r3, #0
- 8000df0: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 8000df2: 2300 movs r3, #0
- 8000df4: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8000df6: 2300 movs r3, #0
- 8000df8: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8000dfa: 2301 movs r3, #1
- 8000dfc: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8000dfe: 2300 movs r3, #0
- 8000e00: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 8000e02: 2300 movs r3, #0
- 8000e04: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) {
- 8000e06: f107 030c add.w r3, r7, #12
- 8000e0a: 4619 mov r1, r3
- 8000e0c: 4811 ldr r0, [pc, #68] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e0e: f002 fc43 bl 8003698 <HAL_TIM_Encoder_Init>
- 8000e12: 4603 mov r3, r0
- 8000e14: 2b00 cmp r3, #0
- 8000e16: bf14 ite ne
- 8000e18: 2301 movne r3, #1
- 8000e1a: 2300 moveq r3, #0
- 8000e1c: b2db uxtb r3, r3
- 8000e1e: 2b00 cmp r3, #0
- 8000e20: d001 beq.n 8000e26 <_ZL12MX_TIM2_Initv+0x8a>
- Error_Handler();
- 8000e22: f000 fceb bl 80017fc <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000e26: 2300 movs r3, #0
- 8000e28: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000e2a: 2300 movs r3, #0
- 8000e2c: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) {
- 8000e2e: 463b mov r3, r7
- 8000e30: 4619 mov r1, r3
- 8000e32: 4808 ldr r0, [pc, #32] ; (8000e54 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e34: f003 fbd0 bl 80045d8 <HAL_TIMEx_MasterConfigSynchronization>
- 8000e38: 4603 mov r3, r0
- 8000e3a: 2b00 cmp r3, #0
- 8000e3c: bf14 ite ne
- 8000e3e: 2301 movne r3, #1
- 8000e40: 2300 moveq r3, #0
- 8000e42: b2db uxtb r3, r3
- 8000e44: 2b00 cmp r3, #0
- 8000e46: d001 beq.n 8000e4c <_ZL12MX_TIM2_Initv+0xb0>
- Error_Handler();
- 8000e48: f000 fcd8 bl 80017fc <Error_Handler>
- }
- /* USER CODE BEGIN TIM2_Init 2 */
-
- /* USER CODE END TIM2_Init 2 */
-
-}
- 8000e4c: bf00 nop
- 8000e4e: 3730 adds r7, #48 ; 0x30
- 8000e50: 46bd mov sp, r7
- 8000e52: bd80 pop {r7, pc}
- 8000e54: 2000002c .word 0x2000002c
-
-08000e58 <_ZL12MX_TIM3_Initv>:
-/**
- * @brief TIM3 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM3_Init(void) {
- 8000e58: b580 push {r7, lr}
- 8000e5a: b088 sub sp, #32
- 8000e5c: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM3_Init 0 */
-
- /* USER CODE END TIM3_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };
- 8000e5e: f107 0310 add.w r3, r7, #16
- 8000e62: 2200 movs r2, #0
- 8000e64: 601a str r2, [r3, #0]
- 8000e66: 605a str r2, [r3, #4]
- 8000e68: 609a str r2, [r3, #8]
- 8000e6a: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000e6c: 1d3b adds r3, r7, #4
- 8000e6e: 2200 movs r2, #0
- 8000e70: 601a str r2, [r3, #0]
- 8000e72: 605a str r2, [r3, #4]
- 8000e74: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM3_Init 1 */
-
- /* USER CODE END TIM3_Init 1 */
- htim3.Instance = TIM3;
- 8000e76: 4b25 ldr r3, [pc, #148] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e78: 4a25 ldr r2, [pc, #148] ; (8000f10 <_ZL12MX_TIM3_Initv+0xb8>)
- 8000e7a: 601a str r2, [r3, #0]
- htim3.Init.Prescaler = 999;
- 8000e7c: 4b23 ldr r3, [pc, #140] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e7e: f240 32e7 movw r2, #999 ; 0x3e7
- 8000e82: 605a str r2, [r3, #4]
- htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000e84: 4b21 ldr r3, [pc, #132] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e86: 2200 movs r2, #0
- 8000e88: 609a str r2, [r3, #8]
- htim3.Init.Period = 159;
- 8000e8a: 4b20 ldr r3, [pc, #128] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e8c: 229f movs r2, #159 ; 0x9f
- 8000e8e: 60da str r2, [r3, #12]
- htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000e90: 4b1e ldr r3, [pc, #120] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e92: 2200 movs r2, #0
- 8000e94: 611a str r2, [r3, #16]
- htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000e96: 4b1d ldr r3, [pc, #116] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e98: 2200 movs r2, #0
- 8000e9a: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim3) != HAL_OK) {
- 8000e9c: 481b ldr r0, [pc, #108] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e9e: f002 fb2b bl 80034f8 <HAL_TIM_Base_Init>
- 8000ea2: 4603 mov r3, r0
- 8000ea4: 2b00 cmp r3, #0
- 8000ea6: bf14 ite ne
- 8000ea8: 2301 movne r3, #1
- 8000eaa: 2300 moveq r3, #0
- 8000eac: b2db uxtb r3, r3
- 8000eae: 2b00 cmp r3, #0
- 8000eb0: d001 beq.n 8000eb6 <_ZL12MX_TIM3_Initv+0x5e>
- Error_Handler();
- 8000eb2: f000 fca3 bl 80017fc <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000eb6: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000eba: 613b str r3, [r7, #16]
- if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) {
- 8000ebc: f107 0310 add.w r3, r7, #16
- 8000ec0: 4619 mov r1, r3
- 8000ec2: 4812 ldr r0, [pc, #72] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000ec4: f002 fee8 bl 8003c98 <HAL_TIM_ConfigClockSource>
- 8000ec8: 4603 mov r3, r0
- 8000eca: 2b00 cmp r3, #0
- 8000ecc: bf14 ite ne
- 8000ece: 2301 movne r3, #1
- 8000ed0: 2300 moveq r3, #0
- 8000ed2: b2db uxtb r3, r3
- 8000ed4: 2b00 cmp r3, #0
- 8000ed6: d001 beq.n 8000edc <_ZL12MX_TIM3_Initv+0x84>
- Error_Handler();
- 8000ed8: f000 fc90 bl 80017fc <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000edc: 2300 movs r3, #0
- 8000ede: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000ee0: 2300 movs r3, #0
- 8000ee2: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) {
- 8000ee4: 1d3b adds r3, r7, #4
- 8000ee6: 4619 mov r1, r3
- 8000ee8: 4808 ldr r0, [pc, #32] ; (8000f0c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000eea: f003 fb75 bl 80045d8 <HAL_TIMEx_MasterConfigSynchronization>
- 8000eee: 4603 mov r3, r0
- 8000ef0: 2b00 cmp r3, #0
- 8000ef2: bf14 ite ne
- 8000ef4: 2301 movne r3, #1
- 8000ef6: 2300 moveq r3, #0
- 8000ef8: b2db uxtb r3, r3
- 8000efa: 2b00 cmp r3, #0
- 8000efc: d001 beq.n 8000f02 <_ZL12MX_TIM3_Initv+0xaa>
- Error_Handler();
- 8000efe: f000 fc7d bl 80017fc <Error_Handler>
- }
- /* USER CODE BEGIN TIM3_Init 2 */
-
- /* USER CODE END TIM3_Init 2 */
-
-}
- 8000f02: bf00 nop
- 8000f04: 3720 adds r7, #32
- 8000f06: 46bd mov sp, r7
- 8000f08: bd80 pop {r7, pc}
- 8000f0a: bf00 nop
- 8000f0c: 2000006c .word 0x2000006c
- 8000f10: 40000400 .word 0x40000400
-
-08000f14 <_ZL12MX_TIM4_Initv>:
-/**
- * @brief TIM4 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM4_Init(void) {
- 8000f14: b580 push {r7, lr}
- 8000f16: b08e sub sp, #56 ; 0x38
- 8000f18: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM4_Init 0 */
-
- /* USER CODE END TIM4_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };
- 8000f1a: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000f1e: 2200 movs r2, #0
- 8000f20: 601a str r2, [r3, #0]
- 8000f22: 605a str r2, [r3, #4]
- 8000f24: 609a str r2, [r3, #8]
- 8000f26: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000f28: f107 031c add.w r3, r7, #28
- 8000f2c: 2200 movs r2, #0
- 8000f2e: 601a str r2, [r3, #0]
- 8000f30: 605a str r2, [r3, #4]
- 8000f32: 609a str r2, [r3, #8]
- TIM_OC_InitTypeDef sConfigOC = { 0 };
- 8000f34: 463b mov r3, r7
- 8000f36: 2200 movs r2, #0
- 8000f38: 601a str r2, [r3, #0]
- 8000f3a: 605a str r2, [r3, #4]
- 8000f3c: 609a str r2, [r3, #8]
- 8000f3e: 60da str r2, [r3, #12]
- 8000f40: 611a str r2, [r3, #16]
- 8000f42: 615a str r2, [r3, #20]
- 8000f44: 619a str r2, [r3, #24]
-
- /* USER CODE BEGIN TIM4_Init 1 */
-
- /* USER CODE END TIM4_Init 1 */
- htim4.Instance = TIM4;
- 8000f46: 4b41 ldr r3, [pc, #260] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f48: 4a41 ldr r2, [pc, #260] ; (8001050 <_ZL12MX_TIM4_Initv+0x13c>)
- 8000f4a: 601a str r2, [r3, #0]
- htim4.Init.Prescaler = 0;
- 8000f4c: 4b3f ldr r3, [pc, #252] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f4e: 2200 movs r2, #0
- 8000f50: 605a str r2, [r3, #4]
- htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000f52: 4b3e ldr r3, [pc, #248] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f54: 2200 movs r2, #0
- 8000f56: 609a str r2, [r3, #8]
- htim4.Init.Period = 799;
- 8000f58: 4b3c ldr r3, [pc, #240] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f5a: f240 321f movw r2, #799 ; 0x31f
- 8000f5e: 60da str r2, [r3, #12]
- htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000f60: 4b3a ldr r3, [pc, #232] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f62: 2200 movs r2, #0
- 8000f64: 611a str r2, [r3, #16]
- htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000f66: 4b39 ldr r3, [pc, #228] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f68: 2200 movs r2, #0
- 8000f6a: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim4) != HAL_OK) {
- 8000f6c: 4837 ldr r0, [pc, #220] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f6e: f002 fac3 bl 80034f8 <HAL_TIM_Base_Init>
- 8000f72: 4603 mov r3, r0
- 8000f74: 2b00 cmp r3, #0
- 8000f76: bf14 ite ne
- 8000f78: 2301 movne r3, #1
- 8000f7a: 2300 moveq r3, #0
- 8000f7c: b2db uxtb r3, r3
- 8000f7e: 2b00 cmp r3, #0
- 8000f80: d001 beq.n 8000f86 <_ZL12MX_TIM4_Initv+0x72>
- Error_Handler();
- 8000f82: f000 fc3b bl 80017fc <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000f86: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000f8a: 62bb str r3, [r7, #40] ; 0x28
- if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) {
- 8000f8c: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000f90: 4619 mov r1, r3
- 8000f92: 482e ldr r0, [pc, #184] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f94: f002 fe80 bl 8003c98 <HAL_TIM_ConfigClockSource>
- 8000f98: 4603 mov r3, r0
- 8000f9a: 2b00 cmp r3, #0
- 8000f9c: bf14 ite ne
- 8000f9e: 2301 movne r3, #1
- 8000fa0: 2300 moveq r3, #0
- 8000fa2: b2db uxtb r3, r3
- 8000fa4: 2b00 cmp r3, #0
- 8000fa6: d001 beq.n 8000fac <_ZL12MX_TIM4_Initv+0x98>
- Error_Handler();
- 8000fa8: f000 fc28 bl 80017fc <Error_Handler>
- }
- if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) {
- 8000fac: 4827 ldr r0, [pc, #156] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000fae: f002 faf9 bl 80035a4 <HAL_TIM_PWM_Init>
- 8000fb2: 4603 mov r3, r0
- 8000fb4: 2b00 cmp r3, #0
- 8000fb6: bf14 ite ne
- 8000fb8: 2301 movne r3, #1
- 8000fba: 2300 moveq r3, #0
- 8000fbc: b2db uxtb r3, r3
- 8000fbe: 2b00 cmp r3, #0
- 8000fc0: d001 beq.n 8000fc6 <_ZL12MX_TIM4_Initv+0xb2>
- Error_Handler();
- 8000fc2: f000 fc1b bl 80017fc <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000fc6: 2300 movs r3, #0
- 8000fc8: 61fb str r3, [r7, #28]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000fca: 2300 movs r3, #0
- 8000fcc: 627b str r3, [r7, #36] ; 0x24
- if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) {
- 8000fce: f107 031c add.w r3, r7, #28
- 8000fd2: 4619 mov r1, r3
- 8000fd4: 481d ldr r0, [pc, #116] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8000fd6: f003 faff bl 80045d8 <HAL_TIMEx_MasterConfigSynchronization>
- 8000fda: 4603 mov r3, r0
- 8000fdc: 2b00 cmp r3, #0
- 8000fde: bf14 ite ne
- 8000fe0: 2301 movne r3, #1
- 8000fe2: 2300 moveq r3, #0
- 8000fe4: b2db uxtb r3, r3
- 8000fe6: 2b00 cmp r3, #0
- 8000fe8: d001 beq.n 8000fee <_ZL12MX_TIM4_Initv+0xda>
- Error_Handler();
- 8000fea: f000 fc07 bl 80017fc <Error_Handler>
- }
- sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8000fee: 2360 movs r3, #96 ; 0x60
- 8000ff0: 603b str r3, [r7, #0]
- sConfigOC.Pulse = 0;
- 8000ff2: 2300 movs r3, #0
- 8000ff4: 607b str r3, [r7, #4]
- sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 8000ff6: 2300 movs r3, #0
- 8000ff8: 60bb str r3, [r7, #8]
- sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 8000ffa: 2300 movs r3, #0
- 8000ffc: 613b str r3, [r7, #16]
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) {
- 8000ffe: 463b mov r3, r7
- 8001000: 2208 movs r2, #8
- 8001002: 4619 mov r1, r3
- 8001004: 4811 ldr r0, [pc, #68] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8001006: f002 fd2f bl 8003a68 <HAL_TIM_PWM_ConfigChannel>
- 800100a: 4603 mov r3, r0
- 800100c: 2b00 cmp r3, #0
- 800100e: bf14 ite ne
- 8001010: 2301 movne r3, #1
- 8001012: 2300 moveq r3, #0
- 8001014: b2db uxtb r3, r3
- 8001016: 2b00 cmp r3, #0
- 8001018: d001 beq.n 800101e <_ZL12MX_TIM4_Initv+0x10a>
- Error_Handler();
- 800101a: f000 fbef bl 80017fc <Error_Handler>
- }
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) {
- 800101e: 463b mov r3, r7
- 8001020: 220c movs r2, #12
- 8001022: 4619 mov r1, r3
- 8001024: 4809 ldr r0, [pc, #36] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8001026: f002 fd1f bl 8003a68 <HAL_TIM_PWM_ConfigChannel>
- 800102a: 4603 mov r3, r0
- 800102c: 2b00 cmp r3, #0
- 800102e: bf14 ite ne
- 8001030: 2301 movne r3, #1
- 8001032: 2300 moveq r3, #0
- 8001034: b2db uxtb r3, r3
- 8001036: 2b00 cmp r3, #0
- 8001038: d001 beq.n 800103e <_ZL12MX_TIM4_Initv+0x12a>
- Error_Handler();
- 800103a: f000 fbdf bl 80017fc <Error_Handler>
- }
- /* USER CODE BEGIN TIM4_Init 2 */
-
- /* USER CODE END TIM4_Init 2 */
- HAL_TIM_MspPostInit(&htim4);
- 800103e: 4803 ldr r0, [pc, #12] ; (800104c <_ZL12MX_TIM4_Initv+0x138>)
- 8001040: f000 fd58 bl 8001af4 <HAL_TIM_MspPostInit>
-
-}
- 8001044: bf00 nop
- 8001046: 3738 adds r7, #56 ; 0x38
- 8001048: 46bd mov sp, r7
- 800104a: bd80 pop {r7, pc}
- 800104c: 200000ac .word 0x200000ac
- 8001050: 40000800 .word 0x40000800
-
-08001054 <_ZL12MX_TIM5_Initv>:
-/**
- * @brief TIM5 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM5_Init(void) {
- 8001054: b580 push {r7, lr}
- 8001056: b08c sub sp, #48 ; 0x30
- 8001058: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM5_Init 0 */
-
- /* USER CODE END TIM5_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = { 0 };
- 800105a: f107 030c add.w r3, r7, #12
- 800105e: 2224 movs r2, #36 ; 0x24
- 8001060: 2100 movs r1, #0
- 8001062: 4618 mov r0, r3
- 8001064: f004 faba bl 80055dc <memset>
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8001068: 463b mov r3, r7
- 800106a: 2200 movs r2, #0
- 800106c: 601a str r2, [r3, #0]
- 800106e: 605a str r2, [r3, #4]
- 8001070: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM5_Init 1 */
-
- /* USER CODE END TIM5_Init 1 */
- htim5.Instance = TIM5;
- 8001072: 4b26 ldr r3, [pc, #152] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 8001074: 4a26 ldr r2, [pc, #152] ; (8001110 <_ZL12MX_TIM5_Initv+0xbc>)
- 8001076: 601a str r2, [r3, #0]
- htim5.Init.Prescaler = 0;
- 8001078: 4b24 ldr r3, [pc, #144] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 800107a: 2200 movs r2, #0
- 800107c: 605a str r2, [r3, #4]
- htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
- 800107e: 4b23 ldr r3, [pc, #140] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 8001080: 2200 movs r2, #0
- 8001082: 609a str r2, [r3, #8]
- htim5.Init.Period = 4294967295;
- 8001084: 4b21 ldr r3, [pc, #132] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 8001086: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 800108a: 60da str r2, [r3, #12]
- htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 800108c: 4b1f ldr r3, [pc, #124] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 800108e: 2200 movs r2, #0
- 8001090: 611a str r2, [r3, #16]
- htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001092: 4b1e ldr r3, [pc, #120] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 8001094: 2200 movs r2, #0
- 8001096: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8001098: 2303 movs r3, #3
- 800109a: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 800109c: 2300 movs r3, #0
- 800109e: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 80010a0: 2301 movs r3, #1
- 80010a2: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 80010a4: 2300 movs r3, #0
- 80010a6: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 80010a8: 2300 movs r3, #0
- 80010aa: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 80010ac: 2300 movs r3, #0
- 80010ae: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 80010b0: 2301 movs r3, #1
- 80010b2: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 80010b4: 2300 movs r3, #0
- 80010b6: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 80010b8: 2300 movs r3, #0
- 80010ba: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) {
- 80010bc: f107 030c add.w r3, r7, #12
- 80010c0: 4619 mov r1, r3
- 80010c2: 4812 ldr r0, [pc, #72] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 80010c4: f002 fae8 bl 8003698 <HAL_TIM_Encoder_Init>
- 80010c8: 4603 mov r3, r0
- 80010ca: 2b00 cmp r3, #0
- 80010cc: bf14 ite ne
- 80010ce: 2301 movne r3, #1
- 80010d0: 2300 moveq r3, #0
- 80010d2: b2db uxtb r3, r3
- 80010d4: 2b00 cmp r3, #0
- 80010d6: d001 beq.n 80010dc <_ZL12MX_TIM5_Initv+0x88>
- Error_Handler();
- 80010d8: f000 fb90 bl 80017fc <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 80010dc: 2300 movs r3, #0
- 80010de: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 80010e0: 2300 movs r3, #0
- 80010e2: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) {
- 80010e4: 463b mov r3, r7
- 80010e6: 4619 mov r1, r3
- 80010e8: 4808 ldr r0, [pc, #32] ; (800110c <_ZL12MX_TIM5_Initv+0xb8>)
- 80010ea: f003 fa75 bl 80045d8 <HAL_TIMEx_MasterConfigSynchronization>
- 80010ee: 4603 mov r3, r0
- 80010f0: 2b00 cmp r3, #0
- 80010f2: bf14 ite ne
- 80010f4: 2301 movne r3, #1
- 80010f6: 2300 moveq r3, #0
- 80010f8: b2db uxtb r3, r3
- 80010fa: 2b00 cmp r3, #0
- 80010fc: d001 beq.n 8001102 <_ZL12MX_TIM5_Initv+0xae>
- Error_Handler();
- 80010fe: f000 fb7d bl 80017fc <Error_Handler>
- }
- /* USER CODE BEGIN TIM5_Init 2 */
-
- /* USER CODE END TIM5_Init 2 */
-
-}
- 8001102: bf00 nop
- 8001104: 3730 adds r7, #48 ; 0x30
- 8001106: 46bd mov sp, r7
- 8001108: bd80 pop {r7, pc}
- 800110a: bf00 nop
- 800110c: 200000ec .word 0x200000ec
- 8001110: 40000c00 .word 0x40000c00
-
-08001114 <_ZL12MX_TIM6_Initv>:
-/**
- * @brief TIM6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM6_Init(void) {
- 8001114: b580 push {r7, lr}
- 8001116: b084 sub sp, #16
- 8001118: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM6_Init 0 */
-
- /* USER CODE END TIM6_Init 0 */
-
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 800111a: 1d3b adds r3, r7, #4
- 800111c: 2200 movs r2, #0
- 800111e: 601a str r2, [r3, #0]
- 8001120: 605a str r2, [r3, #4]
- 8001122: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM6_Init 1 */
-
- /* USER CODE END TIM6_Init 1 */
- htim6.Instance = TIM6;
- 8001124: 4b1a ldr r3, [pc, #104] ; (8001190 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001126: 4a1b ldr r2, [pc, #108] ; (8001194 <_ZL12MX_TIM6_Initv+0x80>)
- 8001128: 601a str r2, [r3, #0]
- htim6.Init.Prescaler = 9999;
- 800112a: 4b19 ldr r3, [pc, #100] ; (8001190 <_ZL12MX_TIM6_Initv+0x7c>)
- 800112c: f242 720f movw r2, #9999 ; 0x270f
- 8001130: 605a str r2, [r3, #4]
- htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001132: 4b17 ldr r3, [pc, #92] ; (8001190 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001134: 2200 movs r2, #0
- 8001136: 609a str r2, [r3, #8]
- htim6.Init.Period = 799;
- 8001138: 4b15 ldr r3, [pc, #84] ; (8001190 <_ZL12MX_TIM6_Initv+0x7c>)
- 800113a: f240 321f movw r2, #799 ; 0x31f
- 800113e: 60da str r2, [r3, #12]
- htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001140: 4b13 ldr r3, [pc, #76] ; (8001190 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001142: 2200 movs r2, #0
- 8001144: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim6) != HAL_OK) {
- 8001146: 4812 ldr r0, [pc, #72] ; (8001190 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001148: f002 f9d6 bl 80034f8 <HAL_TIM_Base_Init>
- 800114c: 4603 mov r3, r0
- 800114e: 2b00 cmp r3, #0
- 8001150: bf14 ite ne
- 8001152: 2301 movne r3, #1
- 8001154: 2300 moveq r3, #0
- 8001156: b2db uxtb r3, r3
- 8001158: 2b00 cmp r3, #0
- 800115a: d001 beq.n 8001160 <_ZL12MX_TIM6_Initv+0x4c>
- Error_Handler();
- 800115c: f000 fb4e bl 80017fc <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001160: 2300 movs r3, #0
- 8001162: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8001164: 2300 movs r3, #0
- 8001166: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) {
- 8001168: 1d3b adds r3, r7, #4
- 800116a: 4619 mov r1, r3
- 800116c: 4808 ldr r0, [pc, #32] ; (8001190 <_ZL12MX_TIM6_Initv+0x7c>)
- 800116e: f003 fa33 bl 80045d8 <HAL_TIMEx_MasterConfigSynchronization>
- 8001172: 4603 mov r3, r0
- 8001174: 2b00 cmp r3, #0
- 8001176: bf14 ite ne
- 8001178: 2301 movne r3, #1
- 800117a: 2300 moveq r3, #0
- 800117c: b2db uxtb r3, r3
- 800117e: 2b00 cmp r3, #0
- 8001180: d001 beq.n 8001186 <_ZL12MX_TIM6_Initv+0x72>
- Error_Handler();
- 8001182: f000 fb3b bl 80017fc <Error_Handler>
- }
- /* USER CODE BEGIN TIM6_Init 2 */
-
- /* USER CODE END TIM6_Init 2 */
-
-}
- 8001186: bf00 nop
- 8001188: 3710 adds r7, #16
- 800118a: 46bd mov sp, r7
- 800118c: bd80 pop {r7, pc}
- 800118e: bf00 nop
- 8001190: 2000012c .word 0x2000012c
- 8001194: 40001000 .word 0x40001000
-
-08001198 <_ZL19MX_USART6_UART_Initv>:
-/**
- * @brief USART6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_USART6_UART_Init(void) {
- 8001198: b580 push {r7, lr}
- 800119a: af00 add r7, sp, #0
- /* USER CODE END USART6_Init 0 */
-
- /* USER CODE BEGIN USART6_Init 1 */
-
- /* USER CODE END USART6_Init 1 */
- huart6.Instance = USART6;
- 800119c: 4b17 ldr r3, [pc, #92] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 800119e: 4a18 ldr r2, [pc, #96] ; (8001200 <_ZL19MX_USART6_UART_Initv+0x68>)
- 80011a0: 601a str r2, [r3, #0]
- huart6.Init.BaudRate = 115200;
- 80011a2: 4b16 ldr r3, [pc, #88] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011a4: f44f 32e1 mov.w r2, #115200 ; 0x1c200
- 80011a8: 605a str r2, [r3, #4]
- huart6.Init.WordLength = UART_WORDLENGTH_9B;
- 80011aa: 4b14 ldr r3, [pc, #80] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011ac: f44f 5280 mov.w r2, #4096 ; 0x1000
- 80011b0: 609a str r2, [r3, #8]
- huart6.Init.StopBits = UART_STOPBITS_1;
- 80011b2: 4b12 ldr r3, [pc, #72] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011b4: 2200 movs r2, #0
- 80011b6: 60da str r2, [r3, #12]
- huart6.Init.Parity = UART_PARITY_ODD;
- 80011b8: 4b10 ldr r3, [pc, #64] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011ba: f44f 62c0 mov.w r2, #1536 ; 0x600
- 80011be: 611a str r2, [r3, #16]
- huart6.Init.Mode = UART_MODE_TX_RX;
- 80011c0: 4b0e ldr r3, [pc, #56] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011c2: 220c movs r2, #12
- 80011c4: 615a str r2, [r3, #20]
- huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 80011c6: 4b0d ldr r3, [pc, #52] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011c8: 2200 movs r2, #0
- 80011ca: 619a str r2, [r3, #24]
- huart6.Init.OverSampling = UART_OVERSAMPLING_16;
- 80011cc: 4b0b ldr r3, [pc, #44] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011ce: 2200 movs r2, #0
- 80011d0: 61da str r2, [r3, #28]
- huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 80011d2: 4b0a ldr r3, [pc, #40] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011d4: 2200 movs r2, #0
- 80011d6: 621a str r2, [r3, #32]
- huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 80011d8: 4b08 ldr r3, [pc, #32] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011da: 2200 movs r2, #0
- 80011dc: 625a str r2, [r3, #36] ; 0x24
- if (HAL_UART_Init(&huart6) != HAL_OK) {
- 80011de: 4807 ldr r0, [pc, #28] ; (80011fc <_ZL19MX_USART6_UART_Initv+0x64>)
- 80011e0: f003 fa74 bl 80046cc <HAL_UART_Init>
- 80011e4: 4603 mov r3, r0
- 80011e6: 2b00 cmp r3, #0
- 80011e8: bf14 ite ne
- 80011ea: 2301 movne r3, #1
- 80011ec: 2300 moveq r3, #0
- 80011ee: b2db uxtb r3, r3
- 80011f0: 2b00 cmp r3, #0
- 80011f2: d001 beq.n 80011f8 <_ZL19MX_USART6_UART_Initv+0x60>
- Error_Handler();
- 80011f4: f000 fb02 bl 80017fc <Error_Handler>
- }
- /* USER CODE BEGIN USART6_Init 2 */
-
- /* USER CODE END USART6_Init 2 */
-
-}
- 80011f8: bf00 nop
- 80011fa: bd80 pop {r7, pc}
- 80011fc: 2000016c .word 0x2000016c
- 8001200: 40011400 .word 0x40011400
-
-08001204 <_ZL12MX_GPIO_Initv>:
-/**
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void) {
- 8001204: b580 push {r7, lr}
- 8001206: b08c sub sp, #48 ; 0x30
- 8001208: af00 add r7, sp, #0
- GPIO_InitTypeDef GPIO_InitStruct = { 0 };
- 800120a: f107 031c add.w r3, r7, #28
- 800120e: 2200 movs r2, #0
- 8001210: 601a str r2, [r3, #0]
- 8001212: 605a str r2, [r3, #4]
- 8001214: 609a str r2, [r3, #8]
- 8001216: 60da str r2, [r3, #12]
- 8001218: 611a str r2, [r3, #16]
-
- /* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 800121a: 4b5e ldr r3, [pc, #376] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 800121c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800121e: 4a5d ldr r2, [pc, #372] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001220: f043 0304 orr.w r3, r3, #4
- 8001224: 6313 str r3, [r2, #48] ; 0x30
- 8001226: 4b5b ldr r3, [pc, #364] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001228: 6b1b ldr r3, [r3, #48] ; 0x30
- 800122a: f003 0304 and.w r3, r3, #4
- 800122e: 61bb str r3, [r7, #24]
- 8001230: 69bb ldr r3, [r7, #24]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001232: 4b58 ldr r3, [pc, #352] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001234: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001236: 4a57 ldr r2, [pc, #348] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001238: f043 0301 orr.w r3, r3, #1
- 800123c: 6313 str r3, [r2, #48] ; 0x30
- 800123e: 4b55 ldr r3, [pc, #340] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001240: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001242: f003 0301 and.w r3, r3, #1
- 8001246: 617b str r3, [r7, #20]
- 8001248: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOF_CLK_ENABLE();
- 800124a: 4b52 ldr r3, [pc, #328] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 800124c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800124e: 4a51 ldr r2, [pc, #324] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001250: f043 0320 orr.w r3, r3, #32
- 8001254: 6313 str r3, [r2, #48] ; 0x30
- 8001256: 4b4f ldr r3, [pc, #316] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001258: 6b1b ldr r3, [r3, #48] ; 0x30
- 800125a: f003 0320 and.w r3, r3, #32
- 800125e: 613b str r3, [r7, #16]
- 8001260: 693b ldr r3, [r7, #16]
- __HAL_RCC_GPIOE_CLK_ENABLE();
- 8001262: 4b4c ldr r3, [pc, #304] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001264: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001266: 4a4b ldr r2, [pc, #300] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001268: f043 0310 orr.w r3, r3, #16
- 800126c: 6313 str r3, [r2, #48] ; 0x30
- 800126e: 4b49 ldr r3, [pc, #292] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001270: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001272: f003 0310 and.w r3, r3, #16
- 8001276: 60fb str r3, [r7, #12]
- 8001278: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 800127a: 4b46 ldr r3, [pc, #280] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 800127c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800127e: 4a45 ldr r2, [pc, #276] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001280: f043 0308 orr.w r3, r3, #8
- 8001284: 6313 str r3, [r2, #48] ; 0x30
- 8001286: 4b43 ldr r3, [pc, #268] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001288: 6b1b ldr r3, [r3, #48] ; 0x30
- 800128a: f003 0308 and.w r3, r3, #8
- 800128e: 60bb str r3, [r7, #8]
- 8001290: 68bb ldr r3, [r7, #8]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 8001292: 4b40 ldr r3, [pc, #256] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001294: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001296: 4a3f ldr r2, [pc, #252] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 8001298: f043 0302 orr.w r3, r3, #2
- 800129c: 6313 str r3, [r2, #48] ; 0x30
- 800129e: 4b3d ldr r3, [pc, #244] ; (8001394 <_ZL12MX_GPIO_Initv+0x190>)
- 80012a0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80012a2: f003 0302 and.w r3, r3, #2
- 80012a6: 607b str r3, [r7, #4]
- 80012a8: 687b ldr r3, [r7, #4]
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET);
- 80012aa: 2200 movs r2, #0
- 80012ac: f44f 5140 mov.w r1, #12288 ; 0x3000
- 80012b0: 4839 ldr r0, [pc, #228] ; (8001398 <_ZL12MX_GPIO_Initv+0x194>)
- 80012b2: f001 f889 bl 80023c8 <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET);
- 80012b6: 2201 movs r2, #1
- 80012b8: f44f 4140 mov.w r1, #49152 ; 0xc000
- 80012bc: 4836 ldr r0, [pc, #216] ; (8001398 <_ZL12MX_GPIO_Initv+0x194>)
- 80012be: f001 f883 bl 80023c8 <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin : user_button_Pin */
- GPIO_InitStruct.Pin = user_button_Pin;
- 80012c2: f44f 5300 mov.w r3, #8192 ; 0x2000
- 80012c6: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
- 80012c8: 4b34 ldr r3, [pc, #208] ; (800139c <_ZL12MX_GPIO_Initv+0x198>)
- 80012ca: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012cc: 2300 movs r3, #0
- 80012ce: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct);
- 80012d0: f107 031c add.w r3, r7, #28
- 80012d4: 4619 mov r1, r3
- 80012d6: 4832 ldr r0, [pc, #200] ; (80013a0 <_ZL12MX_GPIO_Initv+0x19c>)
- 80012d8: f000 fecc bl 8002074 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current2_Pin */
- GPIO_InitStruct.Pin = current2_Pin;
- 80012dc: 2301 movs r3, #1
- 80012de: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 80012e0: 2303 movs r3, #3
- 80012e2: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012e4: 2300 movs r3, #0
- 80012e6: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct);
- 80012e8: f107 031c add.w r3, r7, #28
- 80012ec: 4619 mov r1, r3
- 80012ee: 482c ldr r0, [pc, #176] ; (80013a0 <_ZL12MX_GPIO_Initv+0x19c>)
- 80012f0: f000 fec0 bl 8002074 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current1_Pin */
- GPIO_InitStruct.Pin = current1_Pin;
- 80012f4: 2308 movs r3, #8
- 80012f6: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 80012f8: 2303 movs r3, #3
- 80012fa: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80012fc: 2300 movs r3, #0
- 80012fe: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct);
- 8001300: f107 031c add.w r3, r7, #28
- 8001304: 4619 mov r1, r3
- 8001306: 4827 ldr r0, [pc, #156] ; (80013a4 <_ZL12MX_GPIO_Initv+0x1a0>)
- 8001308: f000 feb4 bl 8002074 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault2_Pin */
- GPIO_InitStruct.Pin = fault2_Pin;
- 800130c: 2340 movs r3, #64 ; 0x40
- 800130e: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001310: 2300 movs r3, #0
- 8001312: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001314: 2300 movs r3, #0
- 8001316: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct);
- 8001318: f107 031c add.w r3, r7, #28
- 800131c: 4619 mov r1, r3
- 800131e: 4821 ldr r0, [pc, #132] ; (80013a4 <_ZL12MX_GPIO_Initv+0x1a0>)
- 8001320: f000 fea8 bl 8002074 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : dir2_Pin dir1_Pin */
- GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin;
- 8001324: f44f 5340 mov.w r3, #12288 ; 0x3000
- 8001328: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 800132a: 2301 movs r3, #1
- 800132c: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800132e: 2300 movs r3, #0
- 8001330: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001332: 2300 movs r3, #0
- 8001334: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 8001336: f107 031c add.w r3, r7, #28
- 800133a: 4619 mov r1, r3
- 800133c: 4816 ldr r0, [pc, #88] ; (8001398 <_ZL12MX_GPIO_Initv+0x194>)
- 800133e: f000 fe99 bl 8002074 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : sleep2_Pin sleep1_Pin */
- GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin;
- 8001342: f44f 4340 mov.w r3, #49152 ; 0xc000
- 8001346: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 8001348: 2301 movs r3, #1
- 800134a: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- 800134c: 2301 movs r3, #1
- 800134e: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001350: 2300 movs r3, #0
- 8001352: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 8001354: f107 031c add.w r3, r7, #28
- 8001358: 4619 mov r1, r3
- 800135a: 480f ldr r0, [pc, #60] ; (8001398 <_ZL12MX_GPIO_Initv+0x194>)
- 800135c: f000 fe8a bl 8002074 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault1_Pin */
- GPIO_InitStruct.Pin = fault1_Pin;
- 8001360: f44f 7300 mov.w r3, #512 ; 0x200
- 8001364: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001366: 2300 movs r3, #0
- 8001368: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800136a: 2300 movs r3, #0
- 800136c: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct);
- 800136e: f107 031c add.w r3, r7, #28
- 8001372: 4619 mov r1, r3
- 8001374: 480c ldr r0, [pc, #48] ; (80013a8 <_ZL12MX_GPIO_Initv+0x1a4>)
- 8001376: f000 fe7d bl 8002074 <HAL_GPIO_Init>
-
- /* EXTI interrupt init*/
- HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
- 800137a: 2200 movs r2, #0
- 800137c: 2100 movs r1, #0
- 800137e: 2028 movs r0, #40 ; 0x28
- 8001380: f000 fe1f bl 8001fc2 <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
- 8001384: 2028 movs r0, #40 ; 0x28
- 8001386: f000 fe38 bl 8001ffa <HAL_NVIC_EnableIRQ>
-
-}
- 800138a: bf00 nop
- 800138c: 3730 adds r7, #48 ; 0x30
- 800138e: 46bd mov sp, r7
- 8001390: bd80 pop {r7, pc}
- 8001392: bf00 nop
- 8001394: 40023800 .word 0x40023800
- 8001398: 40021400 .word 0x40021400
- 800139c: 10110000 .word 0x10110000
- 80013a0: 40020800 .word 0x40020800
- 80013a4: 40020000 .word 0x40020000
- 80013a8: 40021000 .word 0x40021000
-
-080013ac <HAL_TIM_PeriodElapsedCallback>:
-
-/* USER CODE BEGIN 4 */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
- 80013ac: b580 push {r7, lr}
- 80013ae: b084 sub sp, #16
- 80013b0: af00 add r7, sp, #0
- 80013b2: 6078 str r0, [r7, #4]
-
- //TIMER 100Hz PID control
- if (htim->Instance == TIM3) {
- 80013b4: 687b ldr r3, [r7, #4]
- 80013b6: 681b ldr r3, [r3, #0]
- 80013b8: 4a62 ldr r2, [pc, #392] ; (8001544 <HAL_TIM_PeriodElapsedCallback+0x198>)
- 80013ba: 4293 cmp r3, r2
- 80013bc: f040 80be bne.w 800153c <HAL_TIM_PeriodElapsedCallback+0x190>
-
- if (mode == 1) {
- 80013c0: 4b61 ldr r3, [pc, #388] ; (8001548 <HAL_TIM_PeriodElapsedCallback+0x19c>)
- 80013c2: edd3 7a00 vldr s15, [r3]
- 80013c6: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0
- 80013ca: eef4 7a47 vcmp.f32 s15, s14
- 80013ce: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80013d2: d123 bne.n 800141c <HAL_TIM_PeriodElapsedCallback+0x70>
- left_velocity = left_encoder.GetLinearVelocity();
- 80013d4: 485d ldr r0, [pc, #372] ; (800154c <HAL_TIM_PeriodElapsedCallback+0x1a0>)
- 80013d6: f7ff f93b bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 80013da: eef0 7a40 vmov.f32 s15, s0
- 80013de: 4b5c ldr r3, [pc, #368] ; (8001550 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80013e0: edc3 7a00 vstr s15, [r3]
- output_msg.velocity = left_velocity;
- 80013e4: 4b5a ldr r3, [pc, #360] ; (8001550 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80013e6: 681b ldr r3, [r3, #0]
- 80013e8: 4a5a ldr r2, [pc, #360] ; (8001554 <HAL_TIM_PeriodElapsedCallback+0x1a8>)
- 80013ea: 6013 str r3, [r2, #0]
- left_dutycycle = left_pid.update(left_velocity);
- 80013ec: 4b58 ldr r3, [pc, #352] ; (8001550 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80013ee: edd3 7a00 vldr s15, [r3]
- 80013f2: eeb0 0a67 vmov.f32 s0, s15
- 80013f6: 4858 ldr r0, [pc, #352] ; (8001558 <HAL_TIM_PeriodElapsedCallback+0x1ac>)
- 80013f8: f7ff fb8a bl 8000b10 <_ZN3Pid6updateEf>
- 80013fc: 4602 mov r2, r0
- 80013fe: 4b57 ldr r3, [pc, #348] ; (800155c <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 8001400: 601a str r2, [r3, #0]
- left_motor.set_speed(left_dutycycle);
- 8001402: 4b56 ldr r3, [pc, #344] ; (800155c <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 8001404: 681b ldr r3, [r3, #0]
- 8001406: 4619 mov r1, r3
- 8001408: 4855 ldr r0, [pc, #340] ; (8001560 <HAL_TIM_PeriodElapsedCallback+0x1b4>)
- 800140a: f7ff f9df bl 80007cc <_ZN15MotorController9set_speedEi>
- HAL_UART_Transmit(&huart6, tx_buffer, 4, 100);
- 800140e: 4b55 ldr r3, [pc, #340] ; (8001564 <HAL_TIM_PeriodElapsedCallback+0x1b8>)
- 8001410: 6819 ldr r1, [r3, #0]
- 8001412: 2364 movs r3, #100 ; 0x64
- 8001414: 2204 movs r2, #4
- 8001416: 4854 ldr r0, [pc, #336] ; (8001568 <HAL_TIM_PeriodElapsedCallback+0x1bc>)
- 8001418: f003 f9a6 bl 8004768 <HAL_UART_Transmit>
-
- }
- if (mode == 2) {
- 800141c: 4b4a ldr r3, [pc, #296] ; (8001548 <HAL_TIM_PeriodElapsedCallback+0x19c>)
- 800141e: edd3 7a00 vldr s15, [r3]
- 8001422: eeb0 7a00 vmov.f32 s14, #0 ; 0x40000000 2.0
- 8001426: eef4 7a47 vcmp.f32 s15, s14
- 800142a: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800142e: d123 bne.n 8001478 <HAL_TIM_PeriodElapsedCallback+0xcc>
- right_velocity = right_encoder.GetLinearVelocity();
- 8001430: 484e ldr r0, [pc, #312] ; (800156c <HAL_TIM_PeriodElapsedCallback+0x1c0>)
- 8001432: f7ff f90d bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 8001436: eef0 7a40 vmov.f32 s15, s0
- 800143a: 4b4d ldr r3, [pc, #308] ; (8001570 <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 800143c: edc3 7a00 vstr s15, [r3]
- output_msg.velocity = right_velocity;
- 8001440: 4b4b ldr r3, [pc, #300] ; (8001570 <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 8001442: 681b ldr r3, [r3, #0]
- 8001444: 4a43 ldr r2, [pc, #268] ; (8001554 <HAL_TIM_PeriodElapsedCallback+0x1a8>)
- 8001446: 6013 str r3, [r2, #0]
- right_dutycycle = right_pid.update(right_velocity);
- 8001448: 4b49 ldr r3, [pc, #292] ; (8001570 <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 800144a: edd3 7a00 vldr s15, [r3]
- 800144e: eeb0 0a67 vmov.f32 s0, s15
- 8001452: 4848 ldr r0, [pc, #288] ; (8001574 <HAL_TIM_PeriodElapsedCallback+0x1c8>)
- 8001454: f7ff fb5c bl 8000b10 <_ZN3Pid6updateEf>
- 8001458: 4602 mov r2, r0
- 800145a: 4b47 ldr r3, [pc, #284] ; (8001578 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 800145c: 601a str r2, [r3, #0]
- right_motor.set_speed(right_dutycycle);
- 800145e: 4b46 ldr r3, [pc, #280] ; (8001578 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 8001460: 681b ldr r3, [r3, #0]
- 8001462: 4619 mov r1, r3
- 8001464: 4845 ldr r0, [pc, #276] ; (800157c <HAL_TIM_PeriodElapsedCallback+0x1d0>)
- 8001466: f7ff f9b1 bl 80007cc <_ZN15MotorController9set_speedEi>
- HAL_UART_Transmit(&huart6, tx_buffer, 4, 100);
- 800146a: 4b3e ldr r3, [pc, #248] ; (8001564 <HAL_TIM_PeriodElapsedCallback+0x1b8>)
- 800146c: 6819 ldr r1, [r3, #0]
- 800146e: 2364 movs r3, #100 ; 0x64
- 8001470: 2204 movs r2, #4
- 8001472: 483d ldr r0, [pc, #244] ; (8001568 <HAL_TIM_PeriodElapsedCallback+0x1bc>)
- 8001474: f003 f978 bl 8004768 <HAL_UART_Transmit>
- }
- if (mode == 3) {
- 8001478: 4b33 ldr r3, [pc, #204] ; (8001548 <HAL_TIM_PeriodElapsedCallback+0x19c>)
- 800147a: edd3 7a00 vldr s15, [r3]
- 800147e: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0
- 8001482: eef4 7a47 vcmp.f32 s15, s14
- 8001486: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800148a: d157 bne.n 800153c <HAL_TIM_PeriodElapsedCallback+0x190>
-
- left_velocity = left_encoder.GetLinearVelocity();
- 800148c: 482f ldr r0, [pc, #188] ; (800154c <HAL_TIM_PeriodElapsedCallback+0x1a0>)
- 800148e: f7ff f8df bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 8001492: eef0 7a40 vmov.f32 s15, s0
- 8001496: 4b2e ldr r3, [pc, #184] ; (8001550 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 8001498: edc3 7a00 vstr s15, [r3]
- left_dutycycle = left_pid.update(left_velocity);
- 800149c: 4b2c ldr r3, [pc, #176] ; (8001550 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 800149e: edd3 7a00 vldr s15, [r3]
- 80014a2: eeb0 0a67 vmov.f32 s0, s15
- 80014a6: 482c ldr r0, [pc, #176] ; (8001558 <HAL_TIM_PeriodElapsedCallback+0x1ac>)
- 80014a8: f7ff fb32 bl 8000b10 <_ZN3Pid6updateEf>
- 80014ac: 4602 mov r2, r0
- 80014ae: 4b2b ldr r3, [pc, #172] ; (800155c <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 80014b0: 601a str r2, [r3, #0]
- left_motor.set_speed(left_dutycycle);
- 80014b2: 4b2a ldr r3, [pc, #168] ; (800155c <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 80014b4: 681b ldr r3, [r3, #0]
- 80014b6: 4619 mov r1, r3
- 80014b8: 4829 ldr r0, [pc, #164] ; (8001560 <HAL_TIM_PeriodElapsedCallback+0x1b4>)
- 80014ba: f7ff f987 bl 80007cc <_ZN15MotorController9set_speedEi>
-
- right_velocity = right_encoder.GetLinearVelocity();
- 80014be: 482b ldr r0, [pc, #172] ; (800156c <HAL_TIM_PeriodElapsedCallback+0x1c0>)
- 80014c0: f7ff f8c6 bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 80014c4: eef0 7a40 vmov.f32 s15, s0
- 80014c8: 4b29 ldr r3, [pc, #164] ; (8001570 <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 80014ca: edc3 7a00 vstr s15, [r3]
- right_dutycycle = right_pid.update(right_velocity);
- 80014ce: 4b28 ldr r3, [pc, #160] ; (8001570 <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 80014d0: edd3 7a00 vldr s15, [r3]
- 80014d4: eeb0 0a67 vmov.f32 s0, s15
- 80014d8: 4826 ldr r0, [pc, #152] ; (8001574 <HAL_TIM_PeriodElapsedCallback+0x1c8>)
- 80014da: f7ff fb19 bl 8000b10 <_ZN3Pid6updateEf>
- 80014de: 4602 mov r2, r0
- 80014e0: 4b25 ldr r3, [pc, #148] ; (8001578 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 80014e2: 601a str r2, [r3, #0]
- right_motor.set_speed(right_dutycycle);
- 80014e4: 4b24 ldr r3, [pc, #144] ; (8001578 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 80014e6: 681b ldr r3, [r3, #0]
- 80014e8: 4619 mov r1, r3
- 80014ea: 4824 ldr r0, [pc, #144] ; (800157c <HAL_TIM_PeriodElapsedCallback+0x1d0>)
- 80014ec: f7ff f96e bl 80007cc <_ZN15MotorController9set_speedEi>
-
- float difference = left_velocity - right_velocity;
- 80014f0: 4b17 ldr r3, [pc, #92] ; (8001550 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
- 80014f2: ed93 7a00 vldr s14, [r3]
- 80014f6: 4b1e ldr r3, [pc, #120] ; (8001570 <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 80014f8: edd3 7a00 vldr s15, [r3]
- 80014fc: ee77 7a67 vsub.f32 s15, s14, s15
- 8001500: edc7 7a03 vstr s15, [r7, #12]
-
- int cross_dutycycle = cross_pid.update(difference);
- 8001504: ed97 0a03 vldr s0, [r7, #12]
- 8001508: 481d ldr r0, [pc, #116] ; (8001580 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 800150a: f7ff fb01 bl 8000b10 <_ZN3Pid6updateEf>
- 800150e: 60b8 str r0, [r7, #8]
-
- left_dutycycle += cross_dutycycle;
- 8001510: 4b12 ldr r3, [pc, #72] ; (800155c <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 8001512: 681a ldr r2, [r3, #0]
- 8001514: 68bb ldr r3, [r7, #8]
- 8001516: 4413 add r3, r2
- 8001518: 4a10 ldr r2, [pc, #64] ; (800155c <HAL_TIM_PeriodElapsedCallback+0x1b0>)
- 800151a: 6013 str r3, [r2, #0]
- right_dutycycle -= cross_dutycycle;
- 800151c: 4b16 ldr r3, [pc, #88] ; (8001578 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 800151e: 681a ldr r2, [r3, #0]
- 8001520: 68bb ldr r3, [r7, #8]
- 8001522: 1ad3 subs r3, r2, r3
- 8001524: 4a14 ldr r2, [pc, #80] ; (8001578 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 8001526: 6013 str r3, [r2, #0]
-
- output_msg.velocity = difference;
- 8001528: 4a0a ldr r2, [pc, #40] ; (8001554 <HAL_TIM_PeriodElapsedCallback+0x1a8>)
- 800152a: 68fb ldr r3, [r7, #12]
- 800152c: 6013 str r3, [r2, #0]
- HAL_UART_Transmit(&huart6, tx_buffer, 4, 100);
- 800152e: 4b0d ldr r3, [pc, #52] ; (8001564 <HAL_TIM_PeriodElapsedCallback+0x1b8>)
- 8001530: 6819 ldr r1, [r3, #0]
- 8001532: 2364 movs r3, #100 ; 0x64
- 8001534: 2204 movs r2, #4
- 8001536: 480c ldr r0, [pc, #48] ; (8001568 <HAL_TIM_PeriodElapsedCallback+0x1bc>)
- 8001538: f003 f916 bl 8004768 <HAL_UART_Transmit>
- }
-
- //TIMER 2Hz Transmit
- if (htim->Instance == TIM6) {
- }
-}
- 800153c: bf00 nop
- 800153e: 3710 adds r7, #16
- 8001540: 46bd mov sp, r7
- 8001542: bd80 pop {r7, pc}
- 8001544: 40000400 .word 0x40000400
- 8001548: 2000030c .word 0x2000030c
- 800154c: 20000204 .word 0x20000204
- 8001550: 20000224 .word 0x20000224
- 8001554: 20000300 .word 0x20000300
- 8001558: 2000022c .word 0x2000022c
- 800155c: 200002a4 .word 0x200002a4
- 8001560: 200002c4 .word 0x200002c4
- 8001564: 200002dc .word 0x200002dc
- 8001568: 2000016c .word 0x2000016c
- 800156c: 200001ec .word 0x200001ec
- 8001570: 20000228 .word 0x20000228
- 8001574: 20000250 .word 0x20000250
- 8001578: 200002a8 .word 0x200002a8
- 800157c: 200002ac .word 0x200002ac
- 8001580: 20000274 .word 0x20000274
- 8001584: 00000000 .word 0x00000000
-
-08001588 <HAL_UART_RxCpltCallback>:
-
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {
- 8001588: b580 push {r7, lr}
- 800158a: b082 sub sp, #8
- 800158c: af00 add r7, sp, #0
- 800158e: 6078 str r0, [r7, #4]
-
- if (input_msg.pid_select == 1) {
- 8001590: 4b6b ldr r3, [pc, #428] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001592: edd3 7a00 vldr s15, [r3]
- 8001596: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0
- 800159a: eef4 7a47 vcmp.f32 s15, s14
- 800159e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80015a2: d11a bne.n 80015da <HAL_UART_RxCpltCallback+0x52>
-
- left_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd);
- 80015a4: 4b66 ldr r3, [pc, #408] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015a6: edd3 7a04 vldr s15, [r3, #16]
- 80015aa: 4b65 ldr r3, [pc, #404] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015ac: ed93 7a05 vldr s14, [r3, #20]
- 80015b0: 4b63 ldr r3, [pc, #396] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015b2: edd3 6a06 vldr s13, [r3, #24]
- 80015b6: eeb0 1a66 vmov.f32 s2, s13
- 80015ba: eef0 0a47 vmov.f32 s1, s14
- 80015be: eeb0 0a67 vmov.f32 s0, s15
- 80015c2: 4860 ldr r0, [pc, #384] ; (8001744 <HAL_UART_RxCpltCallback+0x1bc>)
- 80015c4: f7ff fa6c bl 8000aa0 <_ZN3Pid6configEfff>
- left_pid.set(input_msg.pid_setpoint_fixed);
- 80015c8: 4b5d ldr r3, [pc, #372] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015ca: edd3 7a01 vldr s15, [r3, #4]
- 80015ce: eeb0 0a67 vmov.f32 s0, s15
- 80015d2: 485c ldr r0, [pc, #368] ; (8001744 <HAL_UART_RxCpltCallback+0x1bc>)
- 80015d4: f7ff fa8d bl 8000af2 <_ZN3Pid3setEf>
-
- cross_setpoint = left_setpoint - right_setpoint;
- cross_pid.set(cross_setpoint);
- }
-
-}
- 80015d8: e0a8 b.n 800172c <HAL_UART_RxCpltCallback+0x1a4>
- } else if (input_msg.pid_select == 2) {
- 80015da: 4b59 ldr r3, [pc, #356] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015dc: edd3 7a00 vldr s15, [r3]
- 80015e0: eeb0 7a00 vmov.f32 s14, #0 ; 0x40000000 2.0
- 80015e4: eef4 7a47 vcmp.f32 s15, s14
- 80015e8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80015ec: d11a bne.n 8001624 <HAL_UART_RxCpltCallback+0x9c>
- right_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd);
- 80015ee: 4b54 ldr r3, [pc, #336] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015f0: edd3 7a04 vldr s15, [r3, #16]
- 80015f4: 4b52 ldr r3, [pc, #328] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015f6: ed93 7a05 vldr s14, [r3, #20]
- 80015fa: 4b51 ldr r3, [pc, #324] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80015fc: edd3 6a06 vldr s13, [r3, #24]
- 8001600: eeb0 1a66 vmov.f32 s2, s13
- 8001604: eef0 0a47 vmov.f32 s1, s14
- 8001608: eeb0 0a67 vmov.f32 s0, s15
- 800160c: 484e ldr r0, [pc, #312] ; (8001748 <HAL_UART_RxCpltCallback+0x1c0>)
- 800160e: f7ff fa47 bl 8000aa0 <_ZN3Pid6configEfff>
- right_pid.set(input_msg.pid_setpoint_fixed);
- 8001612: 4b4b ldr r3, [pc, #300] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001614: edd3 7a01 vldr s15, [r3, #4]
- 8001618: eeb0 0a67 vmov.f32 s0, s15
- 800161c: 484a ldr r0, [pc, #296] ; (8001748 <HAL_UART_RxCpltCallback+0x1c0>)
- 800161e: f7ff fa68 bl 8000af2 <_ZN3Pid3setEf>
-}
- 8001622: e083 b.n 800172c <HAL_UART_RxCpltCallback+0x1a4>
- } else if (input_msg.pid_select == 3) {
- 8001624: 4b46 ldr r3, [pc, #280] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001626: edd3 7a00 vldr s15, [r3]
- 800162a: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0
- 800162e: eef4 7a47 vcmp.f32 s15, s14
- 8001632: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001636: d179 bne.n 800172c <HAL_UART_RxCpltCallback+0x1a4>
- left_pid.config(180, 200, 0);
- 8001638: ed9f 1a44 vldr s2, [pc, #272] ; 800174c <HAL_UART_RxCpltCallback+0x1c4>
- 800163c: eddf 0a44 vldr s1, [pc, #272] ; 8001750 <HAL_UART_RxCpltCallback+0x1c8>
- 8001640: ed9f 0a44 vldr s0, [pc, #272] ; 8001754 <HAL_UART_RxCpltCallback+0x1cc>
- 8001644: 483f ldr r0, [pc, #252] ; (8001744 <HAL_UART_RxCpltCallback+0x1bc>)
- 8001646: f7ff fa2b bl 8000aa0 <_ZN3Pid6configEfff>
- right_pid.config(185, 195, 0);
- 800164a: ed9f 1a40 vldr s2, [pc, #256] ; 800174c <HAL_UART_RxCpltCallback+0x1c4>
- 800164e: eddf 0a42 vldr s1, [pc, #264] ; 8001758 <HAL_UART_RxCpltCallback+0x1d0>
- 8001652: ed9f 0a42 vldr s0, [pc, #264] ; 800175c <HAL_UART_RxCpltCallback+0x1d4>
- 8001656: 483c ldr r0, [pc, #240] ; (8001748 <HAL_UART_RxCpltCallback+0x1c0>)
- 8001658: f7ff fa22 bl 8000aa0 <_ZN3Pid6configEfff>
- cross_pid.config(input_msg.pid_kp, input_msg.pid_ki, input_msg.pid_kd);
- 800165c: 4b38 ldr r3, [pc, #224] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 800165e: edd3 7a04 vldr s15, [r3, #16]
- 8001662: 4b37 ldr r3, [pc, #220] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001664: ed93 7a05 vldr s14, [r3, #20]
- 8001668: 4b35 ldr r3, [pc, #212] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 800166a: edd3 6a06 vldr s13, [r3, #24]
- 800166e: eeb0 1a66 vmov.f32 s2, s13
- 8001672: eef0 0a47 vmov.f32 s1, s14
- 8001676: eeb0 0a67 vmov.f32 s0, s15
- 800167a: 4839 ldr r0, [pc, #228] ; (8001760 <HAL_UART_RxCpltCallback+0x1d8>)
- 800167c: f7ff fa10 bl 8000aa0 <_ZN3Pid6configEfff>
- odom.UpdateValues(input_msg.pid_setpoint_lin, input_msg.pid_setpoint_ang);
- 8001680: 4b2f ldr r3, [pc, #188] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001682: edd3 7a02 vldr s15, [r3, #8]
- 8001686: 4b2e ldr r3, [pc, #184] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 8001688: ed93 7a03 vldr s14, [r3, #12]
- 800168c: eef0 0a47 vmov.f32 s1, s14
- 8001690: eeb0 0a67 vmov.f32 s0, s15
- 8001694: 4833 ldr r0, [pc, #204] ; (8001764 <HAL_UART_RxCpltCallback+0x1dc>)
- 8001696: f7ff f827 bl 80006e8 <_ZN8Odometry12UpdateValuesEff>
- left_setpoint = input_msg.pid_setpoint_lin
- 800169a: 4b29 ldr r3, [pc, #164] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 800169c: edd3 7a02 vldr s15, [r3, #8]
- 80016a0: eeb7 6ae7 vcvt.f64.f32 d6, s15
- - (BASELINE * input_msg.pid_setpoint_ang) / 2;
- 80016a4: 4b26 ldr r3, [pc, #152] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80016a6: edd3 7a03 vldr s15, [r3, #12]
- 80016aa: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 80016ae: ed9f 5b22 vldr d5, [pc, #136] ; 8001738 <HAL_UART_RxCpltCallback+0x1b0>
- 80016b2: ee27 5b05 vmul.f64 d5, d7, d5
- 80016b6: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 80016ba: ee85 7b04 vdiv.f64 d7, d5, d4
- 80016be: ee36 7b47 vsub.f64 d7, d6, d7
- 80016c2: eef7 7bc7 vcvt.f32.f64 s15, d7
- left_setpoint = input_msg.pid_setpoint_lin
- 80016c6: 4b28 ldr r3, [pc, #160] ; (8001768 <HAL_UART_RxCpltCallback+0x1e0>)
- 80016c8: edc3 7a00 vstr s15, [r3]
- right_setpoint = 2 * input_msg.pid_setpoint_lin - left_setpoint;
- 80016cc: 4b1c ldr r3, [pc, #112] ; (8001740 <HAL_UART_RxCpltCallback+0x1b8>)
- 80016ce: edd3 7a02 vldr s15, [r3, #8]
- 80016d2: ee37 7aa7 vadd.f32 s14, s15, s15
- 80016d6: 4b24 ldr r3, [pc, #144] ; (8001768 <HAL_UART_RxCpltCallback+0x1e0>)
- 80016d8: edd3 7a00 vldr s15, [r3]
- 80016dc: ee77 7a67 vsub.f32 s15, s14, s15
- 80016e0: 4b22 ldr r3, [pc, #136] ; (800176c <HAL_UART_RxCpltCallback+0x1e4>)
- 80016e2: edc3 7a00 vstr s15, [r3]
- left_pid.set(left_setpoint);
- 80016e6: 4b20 ldr r3, [pc, #128] ; (8001768 <HAL_UART_RxCpltCallback+0x1e0>)
- 80016e8: edd3 7a00 vldr s15, [r3]
- 80016ec: eeb0 0a67 vmov.f32 s0, s15
- 80016f0: 4814 ldr r0, [pc, #80] ; (8001744 <HAL_UART_RxCpltCallback+0x1bc>)
- 80016f2: f7ff f9fe bl 8000af2 <_ZN3Pid3setEf>
- right_pid.set(right_setpoint);
- 80016f6: 4b1d ldr r3, [pc, #116] ; (800176c <HAL_UART_RxCpltCallback+0x1e4>)
- 80016f8: edd3 7a00 vldr s15, [r3]
- 80016fc: eeb0 0a67 vmov.f32 s0, s15
- 8001700: 4811 ldr r0, [pc, #68] ; (8001748 <HAL_UART_RxCpltCallback+0x1c0>)
- 8001702: f7ff f9f6 bl 8000af2 <_ZN3Pid3setEf>
- cross_setpoint = left_setpoint - right_setpoint;
- 8001706: 4b18 ldr r3, [pc, #96] ; (8001768 <HAL_UART_RxCpltCallback+0x1e0>)
- 8001708: ed93 7a00 vldr s14, [r3]
- 800170c: 4b17 ldr r3, [pc, #92] ; (800176c <HAL_UART_RxCpltCallback+0x1e4>)
- 800170e: edd3 7a00 vldr s15, [r3]
- 8001712: ee77 7a67 vsub.f32 s15, s14, s15
- 8001716: 4b16 ldr r3, [pc, #88] ; (8001770 <HAL_UART_RxCpltCallback+0x1e8>)
- 8001718: edc3 7a00 vstr s15, [r3]
- cross_pid.set(cross_setpoint);
- 800171c: 4b14 ldr r3, [pc, #80] ; (8001770 <HAL_UART_RxCpltCallback+0x1e8>)
- 800171e: edd3 7a00 vldr s15, [r3]
- 8001722: eeb0 0a67 vmov.f32 s0, s15
- 8001726: 480e ldr r0, [pc, #56] ; (8001760 <HAL_UART_RxCpltCallback+0x1d8>)
- 8001728: f7ff f9e3 bl 8000af2 <_ZN3Pid3setEf>
-}
- 800172c: bf00 nop
- 800172e: 3708 adds r7, #8
- 8001730: 46bd mov sp, r7
- 8001732: bd80 pop {r7, pc}
- 8001734: f3af 8000 nop.w
- 8001738: 33333333 .word 0x33333333
- 800173c: 3fd33333 .word 0x3fd33333
- 8001740: 200002e4 .word 0x200002e4
- 8001744: 2000022c .word 0x2000022c
- 8001748: 20000250 .word 0x20000250
- 800174c: 00000000 .word 0x00000000
- 8001750: 43480000 .word 0x43480000
- 8001754: 43340000 .word 0x43340000
- 8001758: 43430000 .word 0x43430000
- 800175c: 43390000 .word 0x43390000
- 8001760: 20000274 .word 0x20000274
- 8001764: 2000021c .word 0x2000021c
- 8001768: 20000298 .word 0x20000298
- 800176c: 2000029c .word 0x2000029c
- 8001770: 200002a0 .word 0x200002a0
-
-08001774 <HAL_GPIO_EXTI_Callback>:
-
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
- 8001774: b580 push {r7, lr}
- 8001776: b082 sub sp, #8
- 8001778: af00 add r7, sp, #0
- 800177a: 4603 mov r3, r0
- 800177c: 80fb strh r3, [r7, #6]
- //Blue user button
- if (GPIO_Pin == GPIO_PIN_13) {
- 800177e: 88fb ldrh r3, [r7, #6]
- 8001780: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8001784: d12a bne.n 80017dc <HAL_GPIO_EXTI_Callback+0x68>
- previous_millis = current_millis;
- 8001786: 4b17 ldr r3, [pc, #92] ; (80017e4 <HAL_GPIO_EXTI_Callback+0x70>)
- 8001788: 681b ldr r3, [r3, #0]
- 800178a: 4a17 ldr r2, [pc, #92] ; (80017e8 <HAL_GPIO_EXTI_Callback+0x74>)
- 800178c: 6013 str r3, [r2, #0]
- current_millis = HAL_GetTick();
- 800178e: f000 fb31 bl 8001df4 <HAL_GetTick>
- 8001792: 4603 mov r3, r0
- 8001794: 461a mov r2, r3
- 8001796: 4b13 ldr r3, [pc, #76] ; (80017e4 <HAL_GPIO_EXTI_Callback+0x70>)
- 8001798: 601a str r2, [r3, #0]
- if (current_millis - previous_millis < 200)
- 800179a: 4b12 ldr r3, [pc, #72] ; (80017e4 <HAL_GPIO_EXTI_Callback+0x70>)
- 800179c: 681a ldr r2, [r3, #0]
- 800179e: 4b12 ldr r3, [pc, #72] ; (80017e8 <HAL_GPIO_EXTI_Callback+0x74>)
- 80017a0: 681b ldr r3, [r3, #0]
- 80017a2: 1ad3 subs r3, r2, r3
- 80017a4: 2bc7 cmp r3, #199 ; 0xc7
- 80017a6: dc03 bgt.n 80017b0 <HAL_GPIO_EXTI_Callback+0x3c>
- debounce = false;
- 80017a8: 4b10 ldr r3, [pc, #64] ; (80017ec <HAL_GPIO_EXTI_Callback+0x78>)
- 80017aa: 2200 movs r2, #0
- 80017ac: 701a strb r2, [r3, #0]
- 80017ae: e002 b.n 80017b6 <HAL_GPIO_EXTI_Callback+0x42>
- else
- debounce = true;
- 80017b0: 4b0e ldr r3, [pc, #56] ; (80017ec <HAL_GPIO_EXTI_Callback+0x78>)
- 80017b2: 2201 movs r2, #1
- 80017b4: 701a strb r2, [r3, #0]
- if (mode == 0 && debounce) {
- 80017b6: 4b0e ldr r3, [pc, #56] ; (80017f0 <HAL_GPIO_EXTI_Callback+0x7c>)
- 80017b8: edd3 7a00 vldr s15, [r3]
- 80017bc: eef5 7a40 vcmp.f32 s15, #0.0
- 80017c0: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80017c4: d10a bne.n 80017dc <HAL_GPIO_EXTI_Callback+0x68>
- 80017c6: 4b09 ldr r3, [pc, #36] ; (80017ec <HAL_GPIO_EXTI_Callback+0x78>)
- 80017c8: 781b ldrb r3, [r3, #0]
- 80017ca: 2b00 cmp r3, #0
- 80017cc: d006 beq.n 80017dc <HAL_GPIO_EXTI_Callback+0x68>
- mode = input_msg.pid_select;
- 80017ce: 4b09 ldr r3, [pc, #36] ; (80017f4 <HAL_GPIO_EXTI_Callback+0x80>)
- 80017d0: 681b ldr r3, [r3, #0]
- 80017d2: 4a07 ldr r2, [pc, #28] ; (80017f0 <HAL_GPIO_EXTI_Callback+0x7c>)
- 80017d4: 6013 str r3, [r2, #0]
- //Enables TIM3 interrupt (used for PID control)
- HAL_TIM_Base_Start_IT(&htim3);
- 80017d6: 4808 ldr r0, [pc, #32] ; (80017f8 <HAL_GPIO_EXTI_Callback+0x84>)
- 80017d8: f001 feba bl 8003550 <HAL_TIM_Base_Start_IT>
- }
- }
-}
- 80017dc: bf00 nop
- 80017de: 3708 adds r7, #8
- 80017e0: 46bd mov sp, r7
- 80017e2: bd80 pop {r7, pc}
- 80017e4: 20000308 .word 0x20000308
- 80017e8: 20000304 .word 0x20000304
- 80017ec: 20000000 .word 0x20000000
- 80017f0: 2000030c .word 0x2000030c
- 80017f4: 200002e4 .word 0x200002e4
- 80017f8: 2000006c .word 0x2000006c
-
-080017fc <Error_Handler>:
-
-/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void) {
- 80017fc: b480 push {r7}
- 80017fe: af00 add r7, sp, #0
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
-
- /* USER CODE END Error_Handler_Debug */
-}
- 8001800: bf00 nop
- 8001802: 46bd mov sp, r7
- 8001804: f85d 7b04 ldr.w r7, [sp], #4
- 8001808: 4770 bx lr
- ...
-
-0800180c <_Z41__static_initialization_and_destruction_0ii>:
- 800180c: b580 push {r7, lr}
- 800180e: b086 sub sp, #24
- 8001810: af04 add r7, sp, #16
- 8001812: 6078 str r0, [r7, #4]
- 8001814: 6039 str r1, [r7, #0]
- 8001816: 687b ldr r3, [r7, #4]
- 8001818: 2b01 cmp r3, #1
- 800181a: d148 bne.n 80018ae <_Z41__static_initialization_and_destruction_0ii+0xa2>
- 800181c: 683b ldr r3, [r7, #0]
- 800181e: f64f 72ff movw r2, #65535 ; 0xffff
- 8001822: 4293 cmp r3, r2
- 8001824: d143 bne.n 80018ae <_Z41__static_initialization_and_destruction_0ii+0xa2>
-Encoder right_encoder = Encoder(&htim5, RIGHT_WHEEL_CIRCUMFERENCE);
- 8001826: 2200 movs r2, #0
- 8001828: 4923 ldr r1, [pc, #140] ; (80018b8 <_Z41__static_initialization_and_destruction_0ii+0xac>)
- 800182a: 4824 ldr r0, [pc, #144] ; (80018bc <_Z41__static_initialization_and_destruction_0ii+0xb0>)
- 800182c: f7fe feab bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>
-Encoder left_encoder = Encoder(&htim2, LEFT_WHEEL_CIRCUMFERENCE);
- 8001830: 2200 movs r2, #0
- 8001832: 4923 ldr r1, [pc, #140] ; (80018c0 <_Z41__static_initialization_and_destruction_0ii+0xb4>)
- 8001834: 4823 ldr r0, [pc, #140] ; (80018c4 <_Z41__static_initialization_and_destruction_0ii+0xb8>)
- 8001836: f7fe fea6 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>
-Odometry odom = Odometry();
- 800183a: 4823 ldr r0, [pc, #140] ; (80018c8 <_Z41__static_initialization_and_destruction_0ii+0xbc>)
- 800183c: f7fe ff40 bl 80006c0 <_ZN8OdometryC1Ev>
-Pid left_pid(0, 0, 0);
- 8001840: ed9f 1a22 vldr s2, [pc, #136] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 8001844: eddf 0a21 vldr s1, [pc, #132] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 8001848: ed9f 0a20 vldr s0, [pc, #128] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 800184c: 4820 ldr r0, [pc, #128] ; (80018d0 <_Z41__static_initialization_and_destruction_0ii+0xc4>)
- 800184e: f7ff f8f3 bl 8000a38 <_ZN3PidC1Efff>
-Pid right_pid(0, 0, 0);
- 8001852: ed9f 1a1e vldr s2, [pc, #120] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 8001856: eddf 0a1d vldr s1, [pc, #116] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 800185a: ed9f 0a1c vldr s0, [pc, #112] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 800185e: 481d ldr r0, [pc, #116] ; (80018d4 <_Z41__static_initialization_and_destruction_0ii+0xc8>)
- 8001860: f7ff f8ea bl 8000a38 <_ZN3PidC1Efff>
-Pid cross_pid(0, 0, 0);
- 8001864: ed9f 1a19 vldr s2, [pc, #100] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 8001868: eddf 0a18 vldr s1, [pc, #96] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 800186c: ed9f 0a17 vldr s0, [pc, #92] ; 80018cc <_Z41__static_initialization_and_destruction_0ii+0xc0>
- 8001870: 4819 ldr r0, [pc, #100] ; (80018d8 <_Z41__static_initialization_and_destruction_0ii+0xcc>)
- 8001872: f7ff f8e1 bl 8000a38 <_ZN3PidC1Efff>
- TIM_CHANNEL_4);
- 8001876: 230c movs r3, #12
- 8001878: 9302 str r3, [sp, #8]
- 800187a: 4b18 ldr r3, [pc, #96] ; (80018dc <_Z41__static_initialization_and_destruction_0ii+0xd0>)
- 800187c: 9301 str r3, [sp, #4]
- 800187e: f44f 5300 mov.w r3, #8192 ; 0x2000
- 8001882: 9300 str r3, [sp, #0]
- 8001884: 4b16 ldr r3, [pc, #88] ; (80018e0 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 8001886: f44f 4200 mov.w r2, #32768 ; 0x8000
- 800188a: 4915 ldr r1, [pc, #84] ; (80018e0 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 800188c: 4815 ldr r0, [pc, #84] ; (80018e4 <_Z41__static_initialization_and_destruction_0ii+0xd8>)
- 800188e: f7fe ff6b bl 8000768 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
- TIM_CHANNEL_3);
- 8001892: 2308 movs r3, #8
- 8001894: 9302 str r3, [sp, #8]
- 8001896: 4b11 ldr r3, [pc, #68] ; (80018dc <_Z41__static_initialization_and_destruction_0ii+0xd0>)
- 8001898: 9301 str r3, [sp, #4]
- 800189a: f44f 5380 mov.w r3, #4096 ; 0x1000
- 800189e: 9300 str r3, [sp, #0]
- 80018a0: 4b0f ldr r3, [pc, #60] ; (80018e0 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 80018a2: f44f 4280 mov.w r2, #16384 ; 0x4000
- 80018a6: 490e ldr r1, [pc, #56] ; (80018e0 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 80018a8: 480f ldr r0, [pc, #60] ; (80018e8 <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 80018aa: f7fe ff5d bl 8000768 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
-}
- 80018ae: bf00 nop
- 80018b0: 3708 adds r7, #8
- 80018b2: 46bd mov sp, r7
- 80018b4: bd80 pop {r7, pc}
- 80018b6: bf00 nop
- 80018b8: 200000ec .word 0x200000ec
- 80018bc: 200001ec .word 0x200001ec
- 80018c0: 2000002c .word 0x2000002c
- 80018c4: 20000204 .word 0x20000204
- 80018c8: 2000021c .word 0x2000021c
- 80018cc: 00000000 .word 0x00000000
- 80018d0: 2000022c .word 0x2000022c
- 80018d4: 20000250 .word 0x20000250
- 80018d8: 20000274 .word 0x20000274
- 80018dc: 200000ac .word 0x200000ac
- 80018e0: 40021400 .word 0x40021400
- 80018e4: 200002ac .word 0x200002ac
- 80018e8: 200002c4 .word 0x200002c4
-
-080018ec <_GLOBAL__sub_I_htim2>:
- 80018ec: b580 push {r7, lr}
- 80018ee: af00 add r7, sp, #0
- 80018f0: f64f 71ff movw r1, #65535 ; 0xffff
- 80018f4: 2001 movs r0, #1
- 80018f6: f7ff ff89 bl 800180c <_Z41__static_initialization_and_destruction_0ii>
- 80018fa: bd80 pop {r7, pc}
-
-080018fc <HAL_MspInit>:
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
- /**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- 80018fc: b480 push {r7}
- 80018fe: b083 sub sp, #12
- 8001900: af00 add r7, sp, #0
- /* USER CODE BEGIN MspInit 0 */
-
- /* USER CODE END MspInit 0 */
-
- __HAL_RCC_PWR_CLK_ENABLE();
- 8001902: 4b0f ldr r3, [pc, #60] ; (8001940 <HAL_MspInit+0x44>)
- 8001904: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001906: 4a0e ldr r2, [pc, #56] ; (8001940 <HAL_MspInit+0x44>)
- 8001908: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 800190c: 6413 str r3, [r2, #64] ; 0x40
- 800190e: 4b0c ldr r3, [pc, #48] ; (8001940 <HAL_MspInit+0x44>)
- 8001910: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001912: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001916: 607b str r3, [r7, #4]
- 8001918: 687b ldr r3, [r7, #4]
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 800191a: 4b09 ldr r3, [pc, #36] ; (8001940 <HAL_MspInit+0x44>)
- 800191c: 6c5b ldr r3, [r3, #68] ; 0x44
- 800191e: 4a08 ldr r2, [pc, #32] ; (8001940 <HAL_MspInit+0x44>)
- 8001920: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8001924: 6453 str r3, [r2, #68] ; 0x44
- 8001926: 4b06 ldr r3, [pc, #24] ; (8001940 <HAL_MspInit+0x44>)
- 8001928: 6c5b ldr r3, [r3, #68] ; 0x44
- 800192a: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 800192e: 603b str r3, [r7, #0]
- 8001930: 683b ldr r3, [r7, #0]
- /* System interrupt init*/
-
- /* USER CODE BEGIN MspInit 1 */
-
- /* USER CODE END MspInit 1 */
-}
- 8001932: bf00 nop
- 8001934: 370c adds r7, #12
- 8001936: 46bd mov sp, r7
- 8001938: f85d 7b04 ldr.w r7, [sp], #4
- 800193c: 4770 bx lr
- 800193e: bf00 nop
- 8001940: 40023800 .word 0x40023800
-
-08001944 <HAL_TIM_Encoder_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_encoder: TIM_Encoder handle pointer
-* @retval None
-*/
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
-{
- 8001944: b580 push {r7, lr}
- 8001946: b08c sub sp, #48 ; 0x30
- 8001948: af00 add r7, sp, #0
- 800194a: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800194c: f107 031c add.w r3, r7, #28
- 8001950: 2200 movs r2, #0
- 8001952: 601a str r2, [r3, #0]
- 8001954: 605a str r2, [r3, #4]
- 8001956: 609a str r2, [r3, #8]
- 8001958: 60da str r2, [r3, #12]
- 800195a: 611a str r2, [r3, #16]
- if(htim_encoder->Instance==TIM2)
- 800195c: 687b ldr r3, [r7, #4]
- 800195e: 681b ldr r3, [r3, #0]
- 8001960: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8001964: d144 bne.n 80019f0 <HAL_TIM_Encoder_MspInit+0xac>
- {
- /* USER CODE BEGIN TIM2_MspInit 0 */
-
- /* USER CODE END TIM2_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM2_CLK_ENABLE();
- 8001966: 4b3b ldr r3, [pc, #236] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001968: 6c1b ldr r3, [r3, #64] ; 0x40
- 800196a: 4a3a ldr r2, [pc, #232] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 800196c: f043 0301 orr.w r3, r3, #1
- 8001970: 6413 str r3, [r2, #64] ; 0x40
- 8001972: 4b38 ldr r3, [pc, #224] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001974: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001976: f003 0301 and.w r3, r3, #1
- 800197a: 61bb str r3, [r7, #24]
- 800197c: 69bb ldr r3, [r7, #24]
-
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 800197e: 4b35 ldr r3, [pc, #212] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001980: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001982: 4a34 ldr r2, [pc, #208] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001984: f043 0301 orr.w r3, r3, #1
- 8001988: 6313 str r3, [r2, #48] ; 0x30
- 800198a: 4b32 ldr r3, [pc, #200] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 800198c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800198e: f003 0301 and.w r3, r3, #1
- 8001992: 617b str r3, [r7, #20]
- 8001994: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 8001996: 4b2f ldr r3, [pc, #188] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001998: 6b1b ldr r3, [r3, #48] ; 0x30
- 800199a: 4a2e ldr r2, [pc, #184] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 800199c: f043 0302 orr.w r3, r3, #2
- 80019a0: 6313 str r3, [r2, #48] ; 0x30
- 80019a2: 4b2c ldr r3, [pc, #176] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019a4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80019a6: f003 0302 and.w r3, r3, #2
- 80019aa: 613b str r3, [r7, #16]
- 80019ac: 693b ldr r3, [r7, #16]
- /**TIM2 GPIO Configuration
- PA5 ------> TIM2_CH1
- PB3 ------> TIM2_CH2
- */
- GPIO_InitStruct.Pin = encoder_sx1_Pin;
- 80019ae: 2320 movs r3, #32
- 80019b0: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80019b2: 2302 movs r3, #2
- 80019b4: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80019b6: 2300 movs r3, #0
- 80019b8: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80019ba: 2300 movs r3, #0
- 80019bc: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 80019be: 2301 movs r3, #1
- 80019c0: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct);
- 80019c2: f107 031c add.w r3, r7, #28
- 80019c6: 4619 mov r1, r3
- 80019c8: 4823 ldr r0, [pc, #140] ; (8001a58 <HAL_TIM_Encoder_MspInit+0x114>)
- 80019ca: f000 fb53 bl 8002074 <HAL_GPIO_Init>
-
- GPIO_InitStruct.Pin = encoder_sx2_Pin;
- 80019ce: 2308 movs r3, #8
- 80019d0: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80019d2: 2302 movs r3, #2
- 80019d4: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80019d6: 2300 movs r3, #0
- 80019d8: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80019da: 2300 movs r3, #0
- 80019dc: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 80019de: 2301 movs r3, #1
- 80019e0: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct);
- 80019e2: f107 031c add.w r3, r7, #28
- 80019e6: 4619 mov r1, r3
- 80019e8: 481c ldr r0, [pc, #112] ; (8001a5c <HAL_TIM_Encoder_MspInit+0x118>)
- 80019ea: f000 fb43 bl 8002074 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM5_MspInit 1 */
-
- /* USER CODE END TIM5_MspInit 1 */
- }
-
-}
- 80019ee: e02c b.n 8001a4a <HAL_TIM_Encoder_MspInit+0x106>
- else if(htim_encoder->Instance==TIM5)
- 80019f0: 687b ldr r3, [r7, #4]
- 80019f2: 681b ldr r3, [r3, #0]
- 80019f4: 4a1a ldr r2, [pc, #104] ; (8001a60 <HAL_TIM_Encoder_MspInit+0x11c>)
- 80019f6: 4293 cmp r3, r2
- 80019f8: d127 bne.n 8001a4a <HAL_TIM_Encoder_MspInit+0x106>
- __HAL_RCC_TIM5_CLK_ENABLE();
- 80019fa: 4b16 ldr r3, [pc, #88] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 80019fc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80019fe: 4a15 ldr r2, [pc, #84] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001a00: f043 0308 orr.w r3, r3, #8
- 8001a04: 6413 str r3, [r2, #64] ; 0x40
- 8001a06: 4b13 ldr r3, [pc, #76] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001a08: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a0a: f003 0308 and.w r3, r3, #8
- 8001a0e: 60fb str r3, [r7, #12]
- 8001a10: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001a12: 4b10 ldr r3, [pc, #64] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001a14: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001a16: 4a0f ldr r2, [pc, #60] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001a18: f043 0301 orr.w r3, r3, #1
- 8001a1c: 6313 str r3, [r2, #48] ; 0x30
- 8001a1e: 4b0d ldr r3, [pc, #52] ; (8001a54 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001a20: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001a22: f003 0301 and.w r3, r3, #1
- 8001a26: 60bb str r3, [r7, #8]
- 8001a28: 68bb ldr r3, [r7, #8]
- GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin;
- 8001a2a: 2303 movs r3, #3
- 8001a2c: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001a2e: 2302 movs r3, #2
- 8001a30: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001a32: 2300 movs r3, #0
- 8001a34: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001a36: 2300 movs r3, #0
- 8001a38: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
- 8001a3a: 2302 movs r3, #2
- 8001a3c: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8001a3e: f107 031c add.w r3, r7, #28
- 8001a42: 4619 mov r1, r3
- 8001a44: 4804 ldr r0, [pc, #16] ; (8001a58 <HAL_TIM_Encoder_MspInit+0x114>)
- 8001a46: f000 fb15 bl 8002074 <HAL_GPIO_Init>
-}
- 8001a4a: bf00 nop
- 8001a4c: 3730 adds r7, #48 ; 0x30
- 8001a4e: 46bd mov sp, r7
- 8001a50: bd80 pop {r7, pc}
- 8001a52: bf00 nop
- 8001a54: 40023800 .word 0x40023800
- 8001a58: 40020000 .word 0x40020000
- 8001a5c: 40020400 .word 0x40020400
- 8001a60: 40000c00 .word 0x40000c00
-
-08001a64 <HAL_TIM_Base_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
- 8001a64: b480 push {r7}
- 8001a66: b087 sub sp, #28
- 8001a68: af00 add r7, sp, #0
- 8001a6a: 6078 str r0, [r7, #4]
- if(htim_base->Instance==TIM3)
- 8001a6c: 687b ldr r3, [r7, #4]
- 8001a6e: 681b ldr r3, [r3, #0]
- 8001a70: 4a1c ldr r2, [pc, #112] ; (8001ae4 <HAL_TIM_Base_MspInit+0x80>)
- 8001a72: 4293 cmp r3, r2
- 8001a74: d10c bne.n 8001a90 <HAL_TIM_Base_MspInit+0x2c>
- {
- /* USER CODE BEGIN TIM3_MspInit 0 */
-
- /* USER CODE END TIM3_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM3_CLK_ENABLE();
- 8001a76: 4b1c ldr r3, [pc, #112] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001a78: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a7a: 4a1b ldr r2, [pc, #108] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001a7c: f043 0302 orr.w r3, r3, #2
- 8001a80: 6413 str r3, [r2, #64] ; 0x40
- 8001a82: 4b19 ldr r3, [pc, #100] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001a84: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a86: f003 0302 and.w r3, r3, #2
- 8001a8a: 617b str r3, [r7, #20]
- 8001a8c: 697b ldr r3, [r7, #20]
- /* USER CODE BEGIN TIM6_MspInit 1 */
-
- /* USER CODE END TIM6_MspInit 1 */
- }
-
-}
- 8001a8e: e022 b.n 8001ad6 <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM4)
- 8001a90: 687b ldr r3, [r7, #4]
- 8001a92: 681b ldr r3, [r3, #0]
- 8001a94: 4a15 ldr r2, [pc, #84] ; (8001aec <HAL_TIM_Base_MspInit+0x88>)
- 8001a96: 4293 cmp r3, r2
- 8001a98: d10c bne.n 8001ab4 <HAL_TIM_Base_MspInit+0x50>
- __HAL_RCC_TIM4_CLK_ENABLE();
- 8001a9a: 4b13 ldr r3, [pc, #76] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001a9c: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a9e: 4a12 ldr r2, [pc, #72] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001aa0: f043 0304 orr.w r3, r3, #4
- 8001aa4: 6413 str r3, [r2, #64] ; 0x40
- 8001aa6: 4b10 ldr r3, [pc, #64] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001aa8: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001aaa: f003 0304 and.w r3, r3, #4
- 8001aae: 613b str r3, [r7, #16]
- 8001ab0: 693b ldr r3, [r7, #16]
-}
- 8001ab2: e010 b.n 8001ad6 <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM6)
- 8001ab4: 687b ldr r3, [r7, #4]
- 8001ab6: 681b ldr r3, [r3, #0]
- 8001ab8: 4a0d ldr r2, [pc, #52] ; (8001af0 <HAL_TIM_Base_MspInit+0x8c>)
- 8001aba: 4293 cmp r3, r2
- 8001abc: d10b bne.n 8001ad6 <HAL_TIM_Base_MspInit+0x72>
- __HAL_RCC_TIM6_CLK_ENABLE();
- 8001abe: 4b0a ldr r3, [pc, #40] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001ac0: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001ac2: 4a09 ldr r2, [pc, #36] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001ac4: f043 0310 orr.w r3, r3, #16
- 8001ac8: 6413 str r3, [r2, #64] ; 0x40
- 8001aca: 4b07 ldr r3, [pc, #28] ; (8001ae8 <HAL_TIM_Base_MspInit+0x84>)
- 8001acc: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001ace: f003 0310 and.w r3, r3, #16
- 8001ad2: 60fb str r3, [r7, #12]
- 8001ad4: 68fb ldr r3, [r7, #12]
-}
- 8001ad6: bf00 nop
- 8001ad8: 371c adds r7, #28
- 8001ada: 46bd mov sp, r7
- 8001adc: f85d 7b04 ldr.w r7, [sp], #4
- 8001ae0: 4770 bx lr
- 8001ae2: bf00 nop
- 8001ae4: 40000400 .word 0x40000400
- 8001ae8: 40023800 .word 0x40023800
- 8001aec: 40000800 .word 0x40000800
- 8001af0: 40001000 .word 0x40001000
-
-08001af4 <HAL_TIM_MspPostInit>:
-
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
-{
- 8001af4: b580 push {r7, lr}
- 8001af6: b088 sub sp, #32
- 8001af8: af00 add r7, sp, #0
- 8001afa: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001afc: f107 030c add.w r3, r7, #12
- 8001b00: 2200 movs r2, #0
- 8001b02: 601a str r2, [r3, #0]
- 8001b04: 605a str r2, [r3, #4]
- 8001b06: 609a str r2, [r3, #8]
- 8001b08: 60da str r2, [r3, #12]
- 8001b0a: 611a str r2, [r3, #16]
- if(htim->Instance==TIM4)
- 8001b0c: 687b ldr r3, [r7, #4]
- 8001b0e: 681b ldr r3, [r3, #0]
- 8001b10: 4a11 ldr r2, [pc, #68] ; (8001b58 <HAL_TIM_MspPostInit+0x64>)
- 8001b12: 4293 cmp r3, r2
- 8001b14: d11c bne.n 8001b50 <HAL_TIM_MspPostInit+0x5c>
- {
- /* USER CODE BEGIN TIM4_MspPostInit 0 */
-
- /* USER CODE END TIM4_MspPostInit 0 */
-
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 8001b16: 4b11 ldr r3, [pc, #68] ; (8001b5c <HAL_TIM_MspPostInit+0x68>)
- 8001b18: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001b1a: 4a10 ldr r2, [pc, #64] ; (8001b5c <HAL_TIM_MspPostInit+0x68>)
- 8001b1c: f043 0308 orr.w r3, r3, #8
- 8001b20: 6313 str r3, [r2, #48] ; 0x30
- 8001b22: 4b0e ldr r3, [pc, #56] ; (8001b5c <HAL_TIM_MspPostInit+0x68>)
- 8001b24: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001b26: f003 0308 and.w r3, r3, #8
- 8001b2a: 60bb str r3, [r7, #8]
- 8001b2c: 68bb ldr r3, [r7, #8]
- /**TIM4 GPIO Configuration
- PD14 ------> TIM4_CH3
- PD15 ------> TIM4_CH4
- */
- GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin;
- 8001b2e: f44f 4340 mov.w r3, #49152 ; 0xc000
- 8001b32: 60fb str r3, [r7, #12]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001b34: 2302 movs r3, #2
- 8001b36: 613b str r3, [r7, #16]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001b38: 2300 movs r3, #0
- 8001b3a: 617b str r3, [r7, #20]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001b3c: 2300 movs r3, #0
- 8001b3e: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
- 8001b40: 2302 movs r3, #2
- 8001b42: 61fb str r3, [r7, #28]
- HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
- 8001b44: f107 030c add.w r3, r7, #12
- 8001b48: 4619 mov r1, r3
- 8001b4a: 4805 ldr r0, [pc, #20] ; (8001b60 <HAL_TIM_MspPostInit+0x6c>)
- 8001b4c: f000 fa92 bl 8002074 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM4_MspPostInit 1 */
-
- /* USER CODE END TIM4_MspPostInit 1 */
- }
-
-}
- 8001b50: bf00 nop
- 8001b52: 3720 adds r7, #32
- 8001b54: 46bd mov sp, r7
- 8001b56: bd80 pop {r7, pc}
- 8001b58: 40000800 .word 0x40000800
- 8001b5c: 40023800 .word 0x40023800
- 8001b60: 40020c00 .word 0x40020c00
-
-08001b64 <HAL_UART_MspInit>:
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
- 8001b64: b580 push {r7, lr}
- 8001b66: b08a sub sp, #40 ; 0x28
- 8001b68: af00 add r7, sp, #0
- 8001b6a: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001b6c: f107 0314 add.w r3, r7, #20
- 8001b70: 2200 movs r2, #0
- 8001b72: 601a str r2, [r3, #0]
- 8001b74: 605a str r2, [r3, #4]
- 8001b76: 609a str r2, [r3, #8]
- 8001b78: 60da str r2, [r3, #12]
- 8001b7a: 611a str r2, [r3, #16]
- if(huart->Instance==USART6)
- 8001b7c: 687b ldr r3, [r7, #4]
- 8001b7e: 681b ldr r3, [r3, #0]
- 8001b80: 4a17 ldr r2, [pc, #92] ; (8001be0 <HAL_UART_MspInit+0x7c>)
- 8001b82: 4293 cmp r3, r2
- 8001b84: d127 bne.n 8001bd6 <HAL_UART_MspInit+0x72>
- {
- /* USER CODE BEGIN USART6_MspInit 0 */
-
- /* USER CODE END USART6_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_USART6_CLK_ENABLE();
- 8001b86: 4b17 ldr r3, [pc, #92] ; (8001be4 <HAL_UART_MspInit+0x80>)
- 8001b88: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001b8a: 4a16 ldr r2, [pc, #88] ; (8001be4 <HAL_UART_MspInit+0x80>)
- 8001b8c: f043 0320 orr.w r3, r3, #32
- 8001b90: 6453 str r3, [r2, #68] ; 0x44
- 8001b92: 4b14 ldr r3, [pc, #80] ; (8001be4 <HAL_UART_MspInit+0x80>)
- 8001b94: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001b96: f003 0320 and.w r3, r3, #32
- 8001b9a: 613b str r3, [r7, #16]
- 8001b9c: 693b ldr r3, [r7, #16]
-
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 8001b9e: 4b11 ldr r3, [pc, #68] ; (8001be4 <HAL_UART_MspInit+0x80>)
- 8001ba0: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001ba2: 4a10 ldr r2, [pc, #64] ; (8001be4 <HAL_UART_MspInit+0x80>)
- 8001ba4: f043 0304 orr.w r3, r3, #4
- 8001ba8: 6313 str r3, [r2, #48] ; 0x30
- 8001baa: 4b0e ldr r3, [pc, #56] ; (8001be4 <HAL_UART_MspInit+0x80>)
- 8001bac: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001bae: f003 0304 and.w r3, r3, #4
- 8001bb2: 60fb str r3, [r7, #12]
- 8001bb4: 68fb ldr r3, [r7, #12]
- /**USART6 GPIO Configuration
- PC6 ------> USART6_TX
- PC7 ------> USART6_RX
- */
- GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 8001bb6: 23c0 movs r3, #192 ; 0xc0
- 8001bb8: 617b str r3, [r7, #20]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001bba: 2302 movs r3, #2
- 8001bbc: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001bbe: 2300 movs r3, #0
- 8001bc0: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8001bc2: 2303 movs r3, #3
- 8001bc4: 623b str r3, [r7, #32]
- GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
- 8001bc6: 2308 movs r3, #8
- 8001bc8: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8001bca: f107 0314 add.w r3, r7, #20
- 8001bce: 4619 mov r1, r3
- 8001bd0: 4805 ldr r0, [pc, #20] ; (8001be8 <HAL_UART_MspInit+0x84>)
- 8001bd2: f000 fa4f bl 8002074 <HAL_GPIO_Init>
- /* USER CODE BEGIN USART6_MspInit 1 */
-
- /* USER CODE END USART6_MspInit 1 */
- }
-
-}
- 8001bd6: bf00 nop
- 8001bd8: 3728 adds r7, #40 ; 0x28
- 8001bda: 46bd mov sp, r7
- 8001bdc: bd80 pop {r7, pc}
- 8001bde: bf00 nop
- 8001be0: 40011400 .word 0x40011400
- 8001be4: 40023800 .word 0x40023800
- 8001be8: 40020800 .word 0x40020800
-
-08001bec <NMI_Handler>:
-/******************************************************************************/
-/**
- * @brief This function handles Non maskable interrupt.
- */
-void NMI_Handler(void)
-{
- 8001bec: b480 push {r7}
- 8001bee: af00 add r7, sp, #0
-
- /* USER CODE END NonMaskableInt_IRQn 0 */
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
- /* USER CODE END NonMaskableInt_IRQn 1 */
-}
- 8001bf0: bf00 nop
- 8001bf2: 46bd mov sp, r7
- 8001bf4: f85d 7b04 ldr.w r7, [sp], #4
- 8001bf8: 4770 bx lr
-
-08001bfa <HardFault_Handler>:
-
-/**
- * @brief This function handles Hard fault interrupt.
- */
-void HardFault_Handler(void)
-{
- 8001bfa: b480 push {r7}
- 8001bfc: af00 add r7, sp, #0
- /* USER CODE BEGIN HardFault_IRQn 0 */
-
- /* USER CODE END HardFault_IRQn 0 */
- while (1)
- 8001bfe: e7fe b.n 8001bfe <HardFault_Handler+0x4>
-
-08001c00 <MemManage_Handler>:
-
-/**
- * @brief This function handles Memory management fault.
- */
-void MemManage_Handler(void)
-{
- 8001c00: b480 push {r7}
- 8001c02: af00 add r7, sp, #0
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
- /* USER CODE END MemoryManagement_IRQn 0 */
- while (1)
- 8001c04: e7fe b.n 8001c04 <MemManage_Handler+0x4>
-
-08001c06 <BusFault_Handler>:
-
-/**
- * @brief This function handles Pre-fetch fault, memory access fault.
- */
-void BusFault_Handler(void)
-{
- 8001c06: b480 push {r7}
- 8001c08: af00 add r7, sp, #0
- /* USER CODE BEGIN BusFault_IRQn 0 */
-
- /* USER CODE END BusFault_IRQn 0 */
- while (1)
- 8001c0a: e7fe b.n 8001c0a <BusFault_Handler+0x4>
-
-08001c0c <UsageFault_Handler>:
-
-/**
- * @brief This function handles Undefined instruction or illegal state.
- */
-void UsageFault_Handler(void)
-{
- 8001c0c: b480 push {r7}
- 8001c0e: af00 add r7, sp, #0
- /* USER CODE BEGIN UsageFault_IRQn 0 */
-
- /* USER CODE END UsageFault_IRQn 0 */
- while (1)
- 8001c10: e7fe b.n 8001c10 <UsageFault_Handler+0x4>
-
-08001c12 <SVC_Handler>:
-
-/**
- * @brief This function handles System service call via SWI instruction.
- */
-void SVC_Handler(void)
-{
- 8001c12: b480 push {r7}
- 8001c14: af00 add r7, sp, #0
-
- /* USER CODE END SVCall_IRQn 0 */
- /* USER CODE BEGIN SVCall_IRQn 1 */
-
- /* USER CODE END SVCall_IRQn 1 */
-}
- 8001c16: bf00 nop
- 8001c18: 46bd mov sp, r7
- 8001c1a: f85d 7b04 ldr.w r7, [sp], #4
- 8001c1e: 4770 bx lr
-
-08001c20 <DebugMon_Handler>:
-
-/**
- * @brief This function handles Debug monitor.
- */
-void DebugMon_Handler(void)
-{
- 8001c20: b480 push {r7}
- 8001c22: af00 add r7, sp, #0
-
- /* USER CODE END DebugMonitor_IRQn 0 */
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
- /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 8001c24: bf00 nop
- 8001c26: 46bd mov sp, r7
- 8001c28: f85d 7b04 ldr.w r7, [sp], #4
- 8001c2c: 4770 bx lr
-
-08001c2e <PendSV_Handler>:
-
-/**
- * @brief This function handles Pendable request for system service.
- */
-void PendSV_Handler(void)
-{
- 8001c2e: b480 push {r7}
- 8001c30: af00 add r7, sp, #0
-
- /* USER CODE END PendSV_IRQn 0 */
- /* USER CODE BEGIN PendSV_IRQn 1 */
-
- /* USER CODE END PendSV_IRQn 1 */
-}
- 8001c32: bf00 nop
- 8001c34: 46bd mov sp, r7
- 8001c36: f85d 7b04 ldr.w r7, [sp], #4
- 8001c3a: 4770 bx lr
-
-08001c3c <SysTick_Handler>:
-
-/**
- * @brief This function handles System tick timer.
- */
-void SysTick_Handler(void)
-{
- 8001c3c: b580 push {r7, lr}
- 8001c3e: af00 add r7, sp, #0
- /* USER CODE BEGIN SysTick_IRQn 0 */
-
- /* USER CODE END SysTick_IRQn 0 */
- HAL_IncTick();
- 8001c40: f000 f8c4 bl 8001dcc <HAL_IncTick>
- /* USER CODE BEGIN SysTick_IRQn 1 */
-
- /* USER CODE END SysTick_IRQn 1 */
-}
- 8001c44: bf00 nop
- 8001c46: bd80 pop {r7, pc}
-
-08001c48 <TIM3_IRQHandler>:
-
-/**
- * @brief This function handles TIM3 global interrupt.
- */
-void TIM3_IRQHandler(void)
-{
- 8001c48: b580 push {r7, lr}
- 8001c4a: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM3_IRQn 0 */
-
- /* USER CODE END TIM3_IRQn 0 */
- HAL_TIM_IRQHandler(&htim3);
- 8001c4c: 4802 ldr r0, [pc, #8] ; (8001c58 <TIM3_IRQHandler+0x10>)
- 8001c4e: f001 fdec bl 800382a <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM3_IRQn 1 */
-
- /* USER CODE END TIM3_IRQn 1 */
-}
- 8001c52: bf00 nop
- 8001c54: bd80 pop {r7, pc}
- 8001c56: bf00 nop
- 8001c58: 2000006c .word 0x2000006c
-
-08001c5c <EXTI15_10_IRQHandler>:
-
-/**
- * @brief This function handles EXTI line[15:10] interrupts.
- */
-void EXTI15_10_IRQHandler(void)
-{
- 8001c5c: b580 push {r7, lr}
- 8001c5e: af00 add r7, sp, #0
- /* USER CODE BEGIN EXTI15_10_IRQn 0 */
-
- /* USER CODE END EXTI15_10_IRQn 0 */
- HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
- 8001c60: f44f 5000 mov.w r0, #8192 ; 0x2000
- 8001c64: f000 fbca bl 80023fc <HAL_GPIO_EXTI_IRQHandler>
- /* USER CODE BEGIN EXTI15_10_IRQn 1 */
-
- /* USER CODE END EXTI15_10_IRQn 1 */
-}
- 8001c68: bf00 nop
- 8001c6a: bd80 pop {r7, pc}
-
-08001c6c <TIM6_DAC_IRQHandler>:
-
-/**
- * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
- */
-void TIM6_DAC_IRQHandler(void)
-{
- 8001c6c: b580 push {r7, lr}
- 8001c6e: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
-
- /* USER CODE END TIM6_DAC_IRQn 0 */
- HAL_TIM_IRQHandler(&htim6);
- 8001c70: 4802 ldr r0, [pc, #8] ; (8001c7c <TIM6_DAC_IRQHandler+0x10>)
- 8001c72: f001 fdda bl 800382a <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
-
- /* USER CODE END TIM6_DAC_IRQn 1 */
-}
- 8001c76: bf00 nop
- 8001c78: bd80 pop {r7, pc}
- 8001c7a: bf00 nop
- 8001c7c: 2000012c .word 0x2000012c
-
-08001c80 <USART6_IRQHandler>:
-
-/**
- * @brief This function handles USART6 global interrupt.
- */
-void USART6_IRQHandler(void)
-{
- 8001c80: b580 push {r7, lr}
- 8001c82: af00 add r7, sp, #0
- /* USER CODE BEGIN USART6_IRQn 0 */
-
- /* USER CODE END USART6_IRQn 0 */
- HAL_UART_IRQHandler(&huart6);
- 8001c84: 4802 ldr r0, [pc, #8] ; (8001c90 <USART6_IRQHandler+0x10>)
- 8001c86: f002 fea3 bl 80049d0 <HAL_UART_IRQHandler>
- /* USER CODE BEGIN USART6_IRQn 1 */
-
- /* USER CODE END USART6_IRQn 1 */
-}
- 8001c8a: bf00 nop
- 8001c8c: bd80 pop {r7, pc}
- 8001c8e: bf00 nop
- 8001c90: 2000016c .word 0x2000016c
-
-08001c94 <SystemInit>:
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- 8001c94: b480 push {r7}
- 8001c96: af00 add r7, sp, #0
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 8001c98: 4b15 ldr r3, [pc, #84] ; (8001cf0 <SystemInit+0x5c>)
- 8001c9a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001c9e: 4a14 ldr r2, [pc, #80] ; (8001cf0 <SystemInit+0x5c>)
- 8001ca0: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 8001ca4: f8c2 3088 str.w r3, [r2, #136] ; 0x88
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
- 8001ca8: 4b12 ldr r3, [pc, #72] ; (8001cf4 <SystemInit+0x60>)
- 8001caa: 681b ldr r3, [r3, #0]
- 8001cac: 4a11 ldr r2, [pc, #68] ; (8001cf4 <SystemInit+0x60>)
- 8001cae: f043 0301 orr.w r3, r3, #1
- 8001cb2: 6013 str r3, [r2, #0]
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
- 8001cb4: 4b0f ldr r3, [pc, #60] ; (8001cf4 <SystemInit+0x60>)
- 8001cb6: 2200 movs r2, #0
- 8001cb8: 609a str r2, [r3, #8]
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8001cba: 4b0e ldr r3, [pc, #56] ; (8001cf4 <SystemInit+0x60>)
- 8001cbc: 681a ldr r2, [r3, #0]
- 8001cbe: 490d ldr r1, [pc, #52] ; (8001cf4 <SystemInit+0x60>)
- 8001cc0: 4b0d ldr r3, [pc, #52] ; (8001cf8 <SystemInit+0x64>)
- 8001cc2: 4013 ands r3, r2
- 8001cc4: 600b str r3, [r1, #0]
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
- 8001cc6: 4b0b ldr r3, [pc, #44] ; (8001cf4 <SystemInit+0x60>)
- 8001cc8: 4a0c ldr r2, [pc, #48] ; (8001cfc <SystemInit+0x68>)
- 8001cca: 605a str r2, [r3, #4]
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
- 8001ccc: 4b09 ldr r3, [pc, #36] ; (8001cf4 <SystemInit+0x60>)
- 8001cce: 681b ldr r3, [r3, #0]
- 8001cd0: 4a08 ldr r2, [pc, #32] ; (8001cf4 <SystemInit+0x60>)
- 8001cd2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8001cd6: 6013 str r3, [r2, #0]
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
- 8001cd8: 4b06 ldr r3, [pc, #24] ; (8001cf4 <SystemInit+0x60>)
- 8001cda: 2200 movs r2, #0
- 8001cdc: 60da str r2, [r3, #12]
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8001cde: 4b04 ldr r3, [pc, #16] ; (8001cf0 <SystemInit+0x5c>)
- 8001ce0: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 8001ce4: 609a str r2, [r3, #8]
-#endif
-}
- 8001ce6: bf00 nop
- 8001ce8: 46bd mov sp, r7
- 8001cea: f85d 7b04 ldr.w r7, [sp], #4
- 8001cee: 4770 bx lr
- 8001cf0: e000ed00 .word 0xe000ed00
- 8001cf4: 40023800 .word 0x40023800
- 8001cf8: fef6ffff .word 0xfef6ffff
- 8001cfc: 24003010 .word 0x24003010
-
-08001d00 <Reset_Handler>:
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
- 8001d00: f8df d034 ldr.w sp, [pc, #52] ; 8001d38 <LoopFillZerobss+0x14>
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- 8001d04: 2100 movs r1, #0
- b LoopCopyDataInit
- 8001d06: e003 b.n 8001d10 <LoopCopyDataInit>
-
-08001d08 <CopyDataInit>:
-
-CopyDataInit:
- ldr r3, =_sidata
- 8001d08: 4b0c ldr r3, [pc, #48] ; (8001d3c <LoopFillZerobss+0x18>)
- ldr r3, [r3, r1]
- 8001d0a: 585b ldr r3, [r3, r1]
- str r3, [r0, r1]
- 8001d0c: 5043 str r3, [r0, r1]
- adds r1, r1, #4
- 8001d0e: 3104 adds r1, #4
-
-08001d10 <LoopCopyDataInit>:
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- 8001d10: 480b ldr r0, [pc, #44] ; (8001d40 <LoopFillZerobss+0x1c>)
- ldr r3, =_edata
- 8001d12: 4b0c ldr r3, [pc, #48] ; (8001d44 <LoopFillZerobss+0x20>)
- adds r2, r0, r1
- 8001d14: 1842 adds r2, r0, r1
- cmp r2, r3
- 8001d16: 429a cmp r2, r3
- bcc CopyDataInit
- 8001d18: d3f6 bcc.n 8001d08 <CopyDataInit>
- ldr r2, =_sbss
- 8001d1a: 4a0b ldr r2, [pc, #44] ; (8001d48 <LoopFillZerobss+0x24>)
- b LoopFillZerobss
- 8001d1c: e002 b.n 8001d24 <LoopFillZerobss>
-
-08001d1e <FillZerobss>:
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- 8001d1e: 2300 movs r3, #0
- str r3, [r2], #4
- 8001d20: f842 3b04 str.w r3, [r2], #4
-
-08001d24 <LoopFillZerobss>:
-
-LoopFillZerobss:
- ldr r3, = _ebss
- 8001d24: 4b09 ldr r3, [pc, #36] ; (8001d4c <LoopFillZerobss+0x28>)
- cmp r2, r3
- 8001d26: 429a cmp r2, r3
- bcc FillZerobss
- 8001d28: d3f9 bcc.n 8001d1e <FillZerobss>
-
-/* Call the clock system initialization function.*/
- bl SystemInit
- 8001d2a: f7ff ffb3 bl 8001c94 <SystemInit>
-/* Call static constructors */
- bl __libc_init_array
- 8001d2e: f003 fc31 bl 8005594 <__libc_init_array>
-/* Call the application's entry point.*/
- bl main
- 8001d32: f7fe ff45 bl 8000bc0 <main>
- bx lr
- 8001d36: 4770 bx lr
- ldr sp, =_estack /* set stack pointer */
- 8001d38: 20080000 .word 0x20080000
- ldr r3, =_sidata
- 8001d3c: 08005630 .word 0x08005630
- ldr r0, =_sdata
- 8001d40: 20000000 .word 0x20000000
- ldr r3, =_edata
- 8001d44: 20000010 .word 0x20000010
- ldr r2, =_sbss
- 8001d48: 20000010 .word 0x20000010
- ldr r3, = _ebss
- 8001d4c: 20000314 .word 0x20000314
-
-08001d50 <ADC_IRQHandler>:
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- 8001d50: e7fe b.n 8001d50 <ADC_IRQHandler>
-
-08001d52 <HAL_Init>:
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8001d52: b580 push {r7, lr}
- 8001d54: af00 add r7, sp, #0
-#if (PREFETCH_ENABLE != 0U)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8001d56: 2003 movs r0, #3
- 8001d58: f000 f928 bl 8001fac <HAL_NVIC_SetPriorityGrouping>
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
- 8001d5c: 2000 movs r0, #0
- 8001d5e: f000 f805 bl 8001d6c <HAL_InitTick>
-
- /* Init the low level hardware */
- HAL_MspInit();
- 8001d62: f7ff fdcb bl 80018fc <HAL_MspInit>
-
- /* Return function status */
- return HAL_OK;
- 8001d66: 2300 movs r3, #0
-}
- 8001d68: 4618 mov r0, r3
- 8001d6a: bd80 pop {r7, pc}
-
-08001d6c <HAL_InitTick>:
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- 8001d6c: b580 push {r7, lr}
- 8001d6e: b082 sub sp, #8
- 8001d70: af00 add r7, sp, #0
- 8001d72: 6078 str r0, [r7, #4]
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8001d74: 4b12 ldr r3, [pc, #72] ; (8001dc0 <HAL_InitTick+0x54>)
- 8001d76: 681a ldr r2, [r3, #0]
- 8001d78: 4b12 ldr r3, [pc, #72] ; (8001dc4 <HAL_InitTick+0x58>)
- 8001d7a: 781b ldrb r3, [r3, #0]
- 8001d7c: 4619 mov r1, r3
- 8001d7e: f44f 737a mov.w r3, #1000 ; 0x3e8
- 8001d82: fbb3 f3f1 udiv r3, r3, r1
- 8001d86: fbb2 f3f3 udiv r3, r2, r3
- 8001d8a: 4618 mov r0, r3
- 8001d8c: f000 f943 bl 8002016 <HAL_SYSTICK_Config>
- 8001d90: 4603 mov r3, r0
- 8001d92: 2b00 cmp r3, #0
- 8001d94: d001 beq.n 8001d9a <HAL_InitTick+0x2e>
- {
- return HAL_ERROR;
- 8001d96: 2301 movs r3, #1
- 8001d98: e00e b.n 8001db8 <HAL_InitTick+0x4c>
- }
-
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8001d9a: 687b ldr r3, [r7, #4]
- 8001d9c: 2b0f cmp r3, #15
- 8001d9e: d80a bhi.n 8001db6 <HAL_InitTick+0x4a>
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8001da0: 2200 movs r2, #0
- 8001da2: 6879 ldr r1, [r7, #4]
- 8001da4: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001da8: f000 f90b bl 8001fc2 <HAL_NVIC_SetPriority>
- uwTickPrio = TickPriority;
- 8001dac: 4a06 ldr r2, [pc, #24] ; (8001dc8 <HAL_InitTick+0x5c>)
- 8001dae: 687b ldr r3, [r7, #4]
- 8001db0: 6013 str r3, [r2, #0]
- {
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
- 8001db2: 2300 movs r3, #0
- 8001db4: e000 b.n 8001db8 <HAL_InitTick+0x4c>
- return HAL_ERROR;
- 8001db6: 2301 movs r3, #1
-}
- 8001db8: 4618 mov r0, r3
- 8001dba: 3708 adds r7, #8
- 8001dbc: 46bd mov sp, r7
- 8001dbe: bd80 pop {r7, pc}
- 8001dc0: 20000004 .word 0x20000004
- 8001dc4: 2000000c .word 0x2000000c
- 8001dc8: 20000008 .word 0x20000008
-
-08001dcc <HAL_IncTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- 8001dcc: b480 push {r7}
- 8001dce: af00 add r7, sp, #0
- uwTick += uwTickFreq;
- 8001dd0: 4b06 ldr r3, [pc, #24] ; (8001dec <HAL_IncTick+0x20>)
- 8001dd2: 781b ldrb r3, [r3, #0]
- 8001dd4: 461a mov r2, r3
- 8001dd6: 4b06 ldr r3, [pc, #24] ; (8001df0 <HAL_IncTick+0x24>)
- 8001dd8: 681b ldr r3, [r3, #0]
- 8001dda: 4413 add r3, r2
- 8001ddc: 4a04 ldr r2, [pc, #16] ; (8001df0 <HAL_IncTick+0x24>)
- 8001dde: 6013 str r3, [r2, #0]
-}
- 8001de0: bf00 nop
- 8001de2: 46bd mov sp, r7
- 8001de4: f85d 7b04 ldr.w r7, [sp], #4
- 8001de8: 4770 bx lr
- 8001dea: bf00 nop
- 8001dec: 2000000c .word 0x2000000c
- 8001df0: 20000310 .word 0x20000310
-
-08001df4 <HAL_GetTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- 8001df4: b480 push {r7}
- 8001df6: af00 add r7, sp, #0
- return uwTick;
- 8001df8: 4b03 ldr r3, [pc, #12] ; (8001e08 <HAL_GetTick+0x14>)
- 8001dfa: 681b ldr r3, [r3, #0]
-}
- 8001dfc: 4618 mov r0, r3
- 8001dfe: 46bd mov sp, r7
- 8001e00: f85d 7b04 ldr.w r7, [sp], #4
- 8001e04: 4770 bx lr
- 8001e06: bf00 nop
- 8001e08: 20000310 .word 0x20000310
-
-08001e0c <__NVIC_SetPriorityGrouping>:
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001e0c: b480 push {r7}
- 8001e0e: b085 sub sp, #20
- 8001e10: af00 add r7, sp, #0
- 8001e12: 6078 str r0, [r7, #4]
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001e14: 687b ldr r3, [r7, #4]
- 8001e16: f003 0307 and.w r3, r3, #7
- 8001e1a: 60fb str r3, [r7, #12]
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- 8001e1c: 4b0b ldr r3, [pc, #44] ; (8001e4c <__NVIC_SetPriorityGrouping+0x40>)
- 8001e1e: 68db ldr r3, [r3, #12]
- 8001e20: 60bb str r3, [r7, #8]
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 8001e22: 68ba ldr r2, [r7, #8]
- 8001e24: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8001e28: 4013 ands r3, r2
- 8001e2a: 60bb str r3, [r7, #8]
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8001e2c: 68fb ldr r3, [r7, #12]
- 8001e2e: 021a lsls r2, r3, #8
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8001e30: 68bb ldr r3, [r7, #8]
- 8001e32: 431a orrs r2, r3
- reg_value = (reg_value |
- 8001e34: 4b06 ldr r3, [pc, #24] ; (8001e50 <__NVIC_SetPriorityGrouping+0x44>)
- 8001e36: 4313 orrs r3, r2
- 8001e38: 60bb str r3, [r7, #8]
- SCB->AIRCR = reg_value;
- 8001e3a: 4a04 ldr r2, [pc, #16] ; (8001e4c <__NVIC_SetPriorityGrouping+0x40>)
- 8001e3c: 68bb ldr r3, [r7, #8]
- 8001e3e: 60d3 str r3, [r2, #12]
-}
- 8001e40: bf00 nop
- 8001e42: 3714 adds r7, #20
- 8001e44: 46bd mov sp, r7
- 8001e46: f85d 7b04 ldr.w r7, [sp], #4
- 8001e4a: 4770 bx lr
- 8001e4c: e000ed00 .word 0xe000ed00
- 8001e50: 05fa0000 .word 0x05fa0000
-
-08001e54 <__NVIC_GetPriorityGrouping>:
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- 8001e54: b480 push {r7}
- 8001e56: af00 add r7, sp, #0
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8001e58: 4b04 ldr r3, [pc, #16] ; (8001e6c <__NVIC_GetPriorityGrouping+0x18>)
- 8001e5a: 68db ldr r3, [r3, #12]
- 8001e5c: 0a1b lsrs r3, r3, #8
- 8001e5e: f003 0307 and.w r3, r3, #7
-}
- 8001e62: 4618 mov r0, r3
- 8001e64: 46bd mov sp, r7
- 8001e66: f85d 7b04 ldr.w r7, [sp], #4
- 8001e6a: 4770 bx lr
- 8001e6c: e000ed00 .word 0xe000ed00
-
-08001e70 <__NVIC_EnableIRQ>:
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001e70: b480 push {r7}
- 8001e72: b083 sub sp, #12
- 8001e74: af00 add r7, sp, #0
- 8001e76: 4603 mov r3, r0
- 8001e78: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001e7a: f997 3007 ldrsb.w r3, [r7, #7]
- 8001e7e: 2b00 cmp r3, #0
- 8001e80: db0b blt.n 8001e9a <__NVIC_EnableIRQ+0x2a>
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 8001e82: 79fb ldrb r3, [r7, #7]
- 8001e84: f003 021f and.w r2, r3, #31
- 8001e88: 4907 ldr r1, [pc, #28] ; (8001ea8 <__NVIC_EnableIRQ+0x38>)
- 8001e8a: f997 3007 ldrsb.w r3, [r7, #7]
- 8001e8e: 095b lsrs r3, r3, #5
- 8001e90: 2001 movs r0, #1
- 8001e92: fa00 f202 lsl.w r2, r0, r2
- 8001e96: f841 2023 str.w r2, [r1, r3, lsl #2]
- }
-}
- 8001e9a: bf00 nop
- 8001e9c: 370c adds r7, #12
- 8001e9e: 46bd mov sp, r7
- 8001ea0: f85d 7b04 ldr.w r7, [sp], #4
- 8001ea4: 4770 bx lr
- 8001ea6: bf00 nop
- 8001ea8: e000e100 .word 0xe000e100
-
-08001eac <__NVIC_SetPriority>:
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- 8001eac: b480 push {r7}
- 8001eae: b083 sub sp, #12
- 8001eb0: af00 add r7, sp, #0
- 8001eb2: 4603 mov r3, r0
- 8001eb4: 6039 str r1, [r7, #0]
- 8001eb6: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001eb8: f997 3007 ldrsb.w r3, [r7, #7]
- 8001ebc: 2b00 cmp r3, #0
- 8001ebe: db0a blt.n 8001ed6 <__NVIC_SetPriority+0x2a>
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001ec0: 683b ldr r3, [r7, #0]
- 8001ec2: b2da uxtb r2, r3
- 8001ec4: 490c ldr r1, [pc, #48] ; (8001ef8 <__NVIC_SetPriority+0x4c>)
- 8001ec6: f997 3007 ldrsb.w r3, [r7, #7]
- 8001eca: 0112 lsls r2, r2, #4
- 8001ecc: b2d2 uxtb r2, r2
- 8001ece: 440b add r3, r1
- 8001ed0: f883 2300 strb.w r2, [r3, #768] ; 0x300
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
- 8001ed4: e00a b.n 8001eec <__NVIC_SetPriority+0x40>
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001ed6: 683b ldr r3, [r7, #0]
- 8001ed8: b2da uxtb r2, r3
- 8001eda: 4908 ldr r1, [pc, #32] ; (8001efc <__NVIC_SetPriority+0x50>)
- 8001edc: 79fb ldrb r3, [r7, #7]
- 8001ede: f003 030f and.w r3, r3, #15
- 8001ee2: 3b04 subs r3, #4
- 8001ee4: 0112 lsls r2, r2, #4
- 8001ee6: b2d2 uxtb r2, r2
- 8001ee8: 440b add r3, r1
- 8001eea: 761a strb r2, [r3, #24]
-}
- 8001eec: bf00 nop
- 8001eee: 370c adds r7, #12
- 8001ef0: 46bd mov sp, r7
- 8001ef2: f85d 7b04 ldr.w r7, [sp], #4
- 8001ef6: 4770 bx lr
- 8001ef8: e000e100 .word 0xe000e100
- 8001efc: e000ed00 .word 0xe000ed00
-
-08001f00 <NVIC_EncodePriority>:
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001f00: b480 push {r7}
- 8001f02: b089 sub sp, #36 ; 0x24
- 8001f04: af00 add r7, sp, #0
- 8001f06: 60f8 str r0, [r7, #12]
- 8001f08: 60b9 str r1, [r7, #8]
- 8001f0a: 607a str r2, [r7, #4]
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001f0c: 68fb ldr r3, [r7, #12]
- 8001f0e: f003 0307 and.w r3, r3, #7
- 8001f12: 61fb str r3, [r7, #28]
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8001f14: 69fb ldr r3, [r7, #28]
- 8001f16: f1c3 0307 rsb r3, r3, #7
- 8001f1a: 2b04 cmp r3, #4
- 8001f1c: bf28 it cs
- 8001f1e: 2304 movcs r3, #4
- 8001f20: 61bb str r3, [r7, #24]
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8001f22: 69fb ldr r3, [r7, #28]
- 8001f24: 3304 adds r3, #4
- 8001f26: 2b06 cmp r3, #6
- 8001f28: d902 bls.n 8001f30 <NVIC_EncodePriority+0x30>
- 8001f2a: 69fb ldr r3, [r7, #28]
- 8001f2c: 3b03 subs r3, #3
- 8001f2e: e000 b.n 8001f32 <NVIC_EncodePriority+0x32>
- 8001f30: 2300 movs r3, #0
- 8001f32: 617b str r3, [r7, #20]
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001f34: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8001f38: 69bb ldr r3, [r7, #24]
- 8001f3a: fa02 f303 lsl.w r3, r2, r3
- 8001f3e: 43da mvns r2, r3
- 8001f40: 68bb ldr r3, [r7, #8]
- 8001f42: 401a ands r2, r3
- 8001f44: 697b ldr r3, [r7, #20]
- 8001f46: 409a lsls r2, r3
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8001f48: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 8001f4c: 697b ldr r3, [r7, #20]
- 8001f4e: fa01 f303 lsl.w r3, r1, r3
- 8001f52: 43d9 mvns r1, r3
- 8001f54: 687b ldr r3, [r7, #4]
- 8001f56: 400b ands r3, r1
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001f58: 4313 orrs r3, r2
- );
-}
- 8001f5a: 4618 mov r0, r3
- 8001f5c: 3724 adds r7, #36 ; 0x24
- 8001f5e: 46bd mov sp, r7
- 8001f60: f85d 7b04 ldr.w r7, [sp], #4
- 8001f64: 4770 bx lr
- ...
-
-08001f68 <SysTick_Config>:
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 8001f68: b580 push {r7, lr}
- 8001f6a: b082 sub sp, #8
- 8001f6c: af00 add r7, sp, #0
- 8001f6e: 6078 str r0, [r7, #4]
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8001f70: 687b ldr r3, [r7, #4]
- 8001f72: 3b01 subs r3, #1
- 8001f74: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8001f78: d301 bcc.n 8001f7e <SysTick_Config+0x16>
- {
- return (1UL); /* Reload value impossible */
- 8001f7a: 2301 movs r3, #1
- 8001f7c: e00f b.n 8001f9e <SysTick_Config+0x36>
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8001f7e: 4a0a ldr r2, [pc, #40] ; (8001fa8 <SysTick_Config+0x40>)
- 8001f80: 687b ldr r3, [r7, #4]
- 8001f82: 3b01 subs r3, #1
- 8001f84: 6053 str r3, [r2, #4]
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8001f86: 210f movs r1, #15
- 8001f88: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001f8c: f7ff ff8e bl 8001eac <__NVIC_SetPriority>
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8001f90: 4b05 ldr r3, [pc, #20] ; (8001fa8 <SysTick_Config+0x40>)
- 8001f92: 2200 movs r2, #0
- 8001f94: 609a str r2, [r3, #8]
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001f96: 4b04 ldr r3, [pc, #16] ; (8001fa8 <SysTick_Config+0x40>)
- 8001f98: 2207 movs r2, #7
- 8001f9a: 601a str r2, [r3, #0]
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
- 8001f9c: 2300 movs r3, #0
-}
- 8001f9e: 4618 mov r0, r3
- 8001fa0: 3708 adds r7, #8
- 8001fa2: 46bd mov sp, r7
- 8001fa4: bd80 pop {r7, pc}
- 8001fa6: bf00 nop
- 8001fa8: e000e010 .word 0xe000e010
-
-08001fac <HAL_NVIC_SetPriorityGrouping>:
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001fac: b580 push {r7, lr}
- 8001fae: b082 sub sp, #8
- 8001fb0: af00 add r7, sp, #0
- 8001fb2: 6078 str r0, [r7, #4]
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
- 8001fb4: 6878 ldr r0, [r7, #4]
- 8001fb6: f7ff ff29 bl 8001e0c <__NVIC_SetPriorityGrouping>
-}
- 8001fba: bf00 nop
- 8001fbc: 3708 adds r7, #8
- 8001fbe: 46bd mov sp, r7
- 8001fc0: bd80 pop {r7, pc}
-
-08001fc2 <HAL_NVIC_SetPriority>:
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001fc2: b580 push {r7, lr}
- 8001fc4: b086 sub sp, #24
- 8001fc6: af00 add r7, sp, #0
- 8001fc8: 4603 mov r3, r0
- 8001fca: 60b9 str r1, [r7, #8]
- 8001fcc: 607a str r2, [r7, #4]
- 8001fce: 73fb strb r3, [r7, #15]
- uint32_t prioritygroup = 0x00;
- 8001fd0: 2300 movs r3, #0
- 8001fd2: 617b str r3, [r7, #20]
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
- 8001fd4: f7ff ff3e bl 8001e54 <__NVIC_GetPriorityGrouping>
- 8001fd8: 6178 str r0, [r7, #20]
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8001fda: 687a ldr r2, [r7, #4]
- 8001fdc: 68b9 ldr r1, [r7, #8]
- 8001fde: 6978 ldr r0, [r7, #20]
- 8001fe0: f7ff ff8e bl 8001f00 <NVIC_EncodePriority>
- 8001fe4: 4602 mov r2, r0
- 8001fe6: f997 300f ldrsb.w r3, [r7, #15]
- 8001fea: 4611 mov r1, r2
- 8001fec: 4618 mov r0, r3
- 8001fee: f7ff ff5d bl 8001eac <__NVIC_SetPriority>
-}
- 8001ff2: bf00 nop
- 8001ff4: 3718 adds r7, #24
- 8001ff6: 46bd mov sp, r7
- 8001ff8: bd80 pop {r7, pc}
-
-08001ffa <HAL_NVIC_EnableIRQ>:
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001ffa: b580 push {r7, lr}
- 8001ffc: b082 sub sp, #8
- 8001ffe: af00 add r7, sp, #0
- 8002000: 4603 mov r3, r0
- 8002002: 71fb strb r3, [r7, #7]
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
- 8002004: f997 3007 ldrsb.w r3, [r7, #7]
- 8002008: 4618 mov r0, r3
- 800200a: f7ff ff31 bl 8001e70 <__NVIC_EnableIRQ>
-}
- 800200e: bf00 nop
- 8002010: 3708 adds r7, #8
- 8002012: 46bd mov sp, r7
- 8002014: bd80 pop {r7, pc}
-
-08002016 <HAL_SYSTICK_Config>:
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 8002016: b580 push {r7, lr}
- 8002018: b082 sub sp, #8
- 800201a: af00 add r7, sp, #0
- 800201c: 6078 str r0, [r7, #4]
- return SysTick_Config(TicksNumb);
- 800201e: 6878 ldr r0, [r7, #4]
- 8002020: f7ff ffa2 bl 8001f68 <SysTick_Config>
- 8002024: 4603 mov r3, r0
-}
- 8002026: 4618 mov r0, r3
- 8002028: 3708 adds r7, #8
- 800202a: 46bd mov sp, r7
- 800202c: bd80 pop {r7, pc}
-
-0800202e <HAL_DMA_Abort_IT>:
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- 800202e: b480 push {r7}
- 8002030: b083 sub sp, #12
- 8002032: af00 add r7, sp, #0
- 8002034: 6078 str r0, [r7, #4]
- if(hdma->State != HAL_DMA_STATE_BUSY)
- 8002036: 687b ldr r3, [r7, #4]
- 8002038: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
- 800203c: b2db uxtb r3, r3
- 800203e: 2b02 cmp r3, #2
- 8002040: d004 beq.n 800204c <HAL_DMA_Abort_IT+0x1e>
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 8002042: 687b ldr r3, [r7, #4]
- 8002044: 2280 movs r2, #128 ; 0x80
- 8002046: 655a str r2, [r3, #84] ; 0x54
- return HAL_ERROR;
- 8002048: 2301 movs r3, #1
- 800204a: e00c b.n 8002066 <HAL_DMA_Abort_IT+0x38>
- }
- else
- {
- /* Set Abort State */
- hdma->State = HAL_DMA_STATE_ABORT;
- 800204c: 687b ldr r3, [r7, #4]
- 800204e: 2205 movs r2, #5
- 8002050: f883 2035 strb.w r2, [r3, #53] ; 0x35
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
- 8002054: 687b ldr r3, [r7, #4]
- 8002056: 681b ldr r3, [r3, #0]
- 8002058: 681a ldr r2, [r3, #0]
- 800205a: 687b ldr r3, [r7, #4]
- 800205c: 681b ldr r3, [r3, #0]
- 800205e: f022 0201 bic.w r2, r2, #1
- 8002062: 601a str r2, [r3, #0]
- }
-
- return HAL_OK;
- 8002064: 2300 movs r3, #0
-}
- 8002066: 4618 mov r0, r3
- 8002068: 370c adds r7, #12
- 800206a: 46bd mov sp, r7
- 800206c: f85d 7b04 ldr.w r7, [sp], #4
- 8002070: 4770 bx lr
- ...
-
-08002074 <HAL_GPIO_Init>:
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8002074: b480 push {r7}
- 8002076: b089 sub sp, #36 ; 0x24
- 8002078: af00 add r7, sp, #0
- 800207a: 6078 str r0, [r7, #4]
- 800207c: 6039 str r1, [r7, #0]
- uint32_t position = 0x00;
- 800207e: 2300 movs r3, #0
- 8002080: 61fb str r3, [r7, #28]
- uint32_t ioposition = 0x00;
- 8002082: 2300 movs r3, #0
- 8002084: 617b str r3, [r7, #20]
- uint32_t iocurrent = 0x00;
- 8002086: 2300 movs r3, #0
- 8002088: 613b str r3, [r7, #16]
- uint32_t temp = 0x00;
- 800208a: 2300 movs r3, #0
- 800208c: 61bb str r3, [r7, #24]
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
- 800208e: 2300 movs r3, #0
- 8002090: 61fb str r3, [r7, #28]
- 8002092: e175 b.n 8002380 <HAL_GPIO_Init+0x30c>
- {
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- 8002094: 2201 movs r2, #1
- 8002096: 69fb ldr r3, [r7, #28]
- 8002098: fa02 f303 lsl.w r3, r2, r3
- 800209c: 617b str r3, [r7, #20]
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 800209e: 683b ldr r3, [r7, #0]
- 80020a0: 681b ldr r3, [r3, #0]
- 80020a2: 697a ldr r2, [r7, #20]
- 80020a4: 4013 ands r3, r2
- 80020a6: 613b str r3, [r7, #16]
-
- if(iocurrent == ioposition)
- 80020a8: 693a ldr r2, [r7, #16]
- 80020aa: 697b ldr r3, [r7, #20]
- 80020ac: 429a cmp r2, r3
- 80020ae: f040 8164 bne.w 800237a <HAL_GPIO_Init+0x306>
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 80020b2: 683b ldr r3, [r7, #0]
- 80020b4: 685b ldr r3, [r3, #4]
- 80020b6: 2b02 cmp r3, #2
- 80020b8: d003 beq.n 80020c2 <HAL_GPIO_Init+0x4e>
- 80020ba: 683b ldr r3, [r7, #0]
- 80020bc: 685b ldr r3, [r3, #4]
- 80020be: 2b12 cmp r3, #18
- 80020c0: d123 bne.n 800210a <HAL_GPIO_Init+0x96>
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- 80020c2: 69fb ldr r3, [r7, #28]
- 80020c4: 08da lsrs r2, r3, #3
- 80020c6: 687b ldr r3, [r7, #4]
- 80020c8: 3208 adds r2, #8
- 80020ca: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 80020ce: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 80020d0: 69fb ldr r3, [r7, #28]
- 80020d2: f003 0307 and.w r3, r3, #7
- 80020d6: 009b lsls r3, r3, #2
- 80020d8: 220f movs r2, #15
- 80020da: fa02 f303 lsl.w r3, r2, r3
- 80020de: 43db mvns r3, r3
- 80020e0: 69ba ldr r2, [r7, #24]
- 80020e2: 4013 ands r3, r2
- 80020e4: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 80020e6: 683b ldr r3, [r7, #0]
- 80020e8: 691a ldr r2, [r3, #16]
- 80020ea: 69fb ldr r3, [r7, #28]
- 80020ec: f003 0307 and.w r3, r3, #7
- 80020f0: 009b lsls r3, r3, #2
- 80020f2: fa02 f303 lsl.w r3, r2, r3
- 80020f6: 69ba ldr r2, [r7, #24]
- 80020f8: 4313 orrs r3, r2
- 80020fa: 61bb str r3, [r7, #24]
- GPIOx->AFR[position >> 3] = temp;
- 80020fc: 69fb ldr r3, [r7, #28]
- 80020fe: 08da lsrs r2, r3, #3
- 8002100: 687b ldr r3, [r7, #4]
- 8002102: 3208 adds r2, #8
- 8002104: 69b9 ldr r1, [r7, #24]
- 8002106: f843 1022 str.w r1, [r3, r2, lsl #2]
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- 800210a: 687b ldr r3, [r7, #4]
- 800210c: 681b ldr r3, [r3, #0]
- 800210e: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 8002110: 69fb ldr r3, [r7, #28]
- 8002112: 005b lsls r3, r3, #1
- 8002114: 2203 movs r2, #3
- 8002116: fa02 f303 lsl.w r3, r2, r3
- 800211a: 43db mvns r3, r3
- 800211c: 69ba ldr r2, [r7, #24]
- 800211e: 4013 ands r3, r2
- 8002120: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 8002122: 683b ldr r3, [r7, #0]
- 8002124: 685b ldr r3, [r3, #4]
- 8002126: f003 0203 and.w r2, r3, #3
- 800212a: 69fb ldr r3, [r7, #28]
- 800212c: 005b lsls r3, r3, #1
- 800212e: fa02 f303 lsl.w r3, r2, r3
- 8002132: 69ba ldr r2, [r7, #24]
- 8002134: 4313 orrs r3, r2
- 8002136: 61bb str r3, [r7, #24]
- GPIOx->MODER = temp;
- 8002138: 687b ldr r3, [r7, #4]
- 800213a: 69ba ldr r2, [r7, #24]
- 800213c: 601a str r2, [r3, #0]
-
- /* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 800213e: 683b ldr r3, [r7, #0]
- 8002140: 685b ldr r3, [r3, #4]
- 8002142: 2b01 cmp r3, #1
- 8002144: d00b beq.n 800215e <HAL_GPIO_Init+0xea>
- 8002146: 683b ldr r3, [r7, #0]
- 8002148: 685b ldr r3, [r3, #4]
- 800214a: 2b02 cmp r3, #2
- 800214c: d007 beq.n 800215e <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 800214e: 683b ldr r3, [r7, #0]
- 8002150: 685b ldr r3, [r3, #4]
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8002152: 2b11 cmp r3, #17
- 8002154: d003 beq.n 800215e <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8002156: 683b ldr r3, [r7, #0]
- 8002158: 685b ldr r3, [r3, #4]
- 800215a: 2b12 cmp r3, #18
- 800215c: d130 bne.n 80021c0 <HAL_GPIO_Init+0x14c>
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- 800215e: 687b ldr r3, [r7, #4]
- 8002160: 689b ldr r3, [r3, #8]
- 8002162: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8002164: 69fb ldr r3, [r7, #28]
- 8002166: 005b lsls r3, r3, #1
- 8002168: 2203 movs r2, #3
- 800216a: fa02 f303 lsl.w r3, r2, r3
- 800216e: 43db mvns r3, r3
- 8002170: 69ba ldr r2, [r7, #24]
- 8002172: 4013 ands r3, r2
- 8002174: 61bb str r3, [r7, #24]
- temp |= (GPIO_Init->Speed << (position * 2));
- 8002176: 683b ldr r3, [r7, #0]
- 8002178: 68da ldr r2, [r3, #12]
- 800217a: 69fb ldr r3, [r7, #28]
- 800217c: 005b lsls r3, r3, #1
- 800217e: fa02 f303 lsl.w r3, r2, r3
- 8002182: 69ba ldr r2, [r7, #24]
- 8002184: 4313 orrs r3, r2
- 8002186: 61bb str r3, [r7, #24]
- GPIOx->OSPEEDR = temp;
- 8002188: 687b ldr r3, [r7, #4]
- 800218a: 69ba ldr r2, [r7, #24]
- 800218c: 609a str r2, [r3, #8]
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- 800218e: 687b ldr r3, [r7, #4]
- 8002190: 685b ldr r3, [r3, #4]
- 8002192: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8002194: 2201 movs r2, #1
- 8002196: 69fb ldr r3, [r7, #28]
- 8002198: fa02 f303 lsl.w r3, r2, r3
- 800219c: 43db mvns r3, r3
- 800219e: 69ba ldr r2, [r7, #24]
- 80021a0: 4013 ands r3, r2
- 80021a2: 61bb str r3, [r7, #24]
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 80021a4: 683b ldr r3, [r7, #0]
- 80021a6: 685b ldr r3, [r3, #4]
- 80021a8: 091b lsrs r3, r3, #4
- 80021aa: f003 0201 and.w r2, r3, #1
- 80021ae: 69fb ldr r3, [r7, #28]
- 80021b0: fa02 f303 lsl.w r3, r2, r3
- 80021b4: 69ba ldr r2, [r7, #24]
- 80021b6: 4313 orrs r3, r2
- 80021b8: 61bb str r3, [r7, #24]
- GPIOx->OTYPER = temp;
- 80021ba: 687b ldr r3, [r7, #4]
- 80021bc: 69ba ldr r2, [r7, #24]
- 80021be: 605a str r2, [r3, #4]
- }
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- 80021c0: 687b ldr r3, [r7, #4]
- 80021c2: 68db ldr r3, [r3, #12]
- 80021c4: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 80021c6: 69fb ldr r3, [r7, #28]
- 80021c8: 005b lsls r3, r3, #1
- 80021ca: 2203 movs r2, #3
- 80021cc: fa02 f303 lsl.w r3, r2, r3
- 80021d0: 43db mvns r3, r3
- 80021d2: 69ba ldr r2, [r7, #24]
- 80021d4: 4013 ands r3, r2
- 80021d6: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Pull) << (position * 2));
- 80021d8: 683b ldr r3, [r7, #0]
- 80021da: 689a ldr r2, [r3, #8]
- 80021dc: 69fb ldr r3, [r7, #28]
- 80021de: 005b lsls r3, r3, #1
- 80021e0: fa02 f303 lsl.w r3, r2, r3
- 80021e4: 69ba ldr r2, [r7, #24]
- 80021e6: 4313 orrs r3, r2
- 80021e8: 61bb str r3, [r7, #24]
- GPIOx->PUPDR = temp;
- 80021ea: 687b ldr r3, [r7, #4]
- 80021ec: 69ba ldr r2, [r7, #24]
- 80021ee: 60da str r2, [r3, #12]
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 80021f0: 683b ldr r3, [r7, #0]
- 80021f2: 685b ldr r3, [r3, #4]
- 80021f4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80021f8: 2b00 cmp r3, #0
- 80021fa: f000 80be beq.w 800237a <HAL_GPIO_Init+0x306>
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80021fe: 4b65 ldr r3, [pc, #404] ; (8002394 <HAL_GPIO_Init+0x320>)
- 8002200: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002202: 4a64 ldr r2, [pc, #400] ; (8002394 <HAL_GPIO_Init+0x320>)
- 8002204: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8002208: 6453 str r3, [r2, #68] ; 0x44
- 800220a: 4b62 ldr r3, [pc, #392] ; (8002394 <HAL_GPIO_Init+0x320>)
- 800220c: 6c5b ldr r3, [r3, #68] ; 0x44
- 800220e: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8002212: 60fb str r3, [r7, #12]
- 8002214: 68fb ldr r3, [r7, #12]
-
- temp = SYSCFG->EXTICR[position >> 2];
- 8002216: 4a60 ldr r2, [pc, #384] ; (8002398 <HAL_GPIO_Init+0x324>)
- 8002218: 69fb ldr r3, [r7, #28]
- 800221a: 089b lsrs r3, r3, #2
- 800221c: 3302 adds r3, #2
- 800221e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 8002222: 61bb str r3, [r7, #24]
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 8002224: 69fb ldr r3, [r7, #28]
- 8002226: f003 0303 and.w r3, r3, #3
- 800222a: 009b lsls r3, r3, #2
- 800222c: 220f movs r2, #15
- 800222e: fa02 f303 lsl.w r3, r2, r3
- 8002232: 43db mvns r3, r3
- 8002234: 69ba ldr r2, [r7, #24]
- 8002236: 4013 ands r3, r2
- 8002238: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 800223a: 687b ldr r3, [r7, #4]
- 800223c: 4a57 ldr r2, [pc, #348] ; (800239c <HAL_GPIO_Init+0x328>)
- 800223e: 4293 cmp r3, r2
- 8002240: d037 beq.n 80022b2 <HAL_GPIO_Init+0x23e>
- 8002242: 687b ldr r3, [r7, #4]
- 8002244: 4a56 ldr r2, [pc, #344] ; (80023a0 <HAL_GPIO_Init+0x32c>)
- 8002246: 4293 cmp r3, r2
- 8002248: d031 beq.n 80022ae <HAL_GPIO_Init+0x23a>
- 800224a: 687b ldr r3, [r7, #4]
- 800224c: 4a55 ldr r2, [pc, #340] ; (80023a4 <HAL_GPIO_Init+0x330>)
- 800224e: 4293 cmp r3, r2
- 8002250: d02b beq.n 80022aa <HAL_GPIO_Init+0x236>
- 8002252: 687b ldr r3, [r7, #4]
- 8002254: 4a54 ldr r2, [pc, #336] ; (80023a8 <HAL_GPIO_Init+0x334>)
- 8002256: 4293 cmp r3, r2
- 8002258: d025 beq.n 80022a6 <HAL_GPIO_Init+0x232>
- 800225a: 687b ldr r3, [r7, #4]
- 800225c: 4a53 ldr r2, [pc, #332] ; (80023ac <HAL_GPIO_Init+0x338>)
- 800225e: 4293 cmp r3, r2
- 8002260: d01f beq.n 80022a2 <HAL_GPIO_Init+0x22e>
- 8002262: 687b ldr r3, [r7, #4]
- 8002264: 4a52 ldr r2, [pc, #328] ; (80023b0 <HAL_GPIO_Init+0x33c>)
- 8002266: 4293 cmp r3, r2
- 8002268: d019 beq.n 800229e <HAL_GPIO_Init+0x22a>
- 800226a: 687b ldr r3, [r7, #4]
- 800226c: 4a51 ldr r2, [pc, #324] ; (80023b4 <HAL_GPIO_Init+0x340>)
- 800226e: 4293 cmp r3, r2
- 8002270: d013 beq.n 800229a <HAL_GPIO_Init+0x226>
- 8002272: 687b ldr r3, [r7, #4]
- 8002274: 4a50 ldr r2, [pc, #320] ; (80023b8 <HAL_GPIO_Init+0x344>)
- 8002276: 4293 cmp r3, r2
- 8002278: d00d beq.n 8002296 <HAL_GPIO_Init+0x222>
- 800227a: 687b ldr r3, [r7, #4]
- 800227c: 4a4f ldr r2, [pc, #316] ; (80023bc <HAL_GPIO_Init+0x348>)
- 800227e: 4293 cmp r3, r2
- 8002280: d007 beq.n 8002292 <HAL_GPIO_Init+0x21e>
- 8002282: 687b ldr r3, [r7, #4]
- 8002284: 4a4e ldr r2, [pc, #312] ; (80023c0 <HAL_GPIO_Init+0x34c>)
- 8002286: 4293 cmp r3, r2
- 8002288: d101 bne.n 800228e <HAL_GPIO_Init+0x21a>
- 800228a: 2309 movs r3, #9
- 800228c: e012 b.n 80022b4 <HAL_GPIO_Init+0x240>
- 800228e: 230a movs r3, #10
- 8002290: e010 b.n 80022b4 <HAL_GPIO_Init+0x240>
- 8002292: 2308 movs r3, #8
- 8002294: e00e b.n 80022b4 <HAL_GPIO_Init+0x240>
- 8002296: 2307 movs r3, #7
- 8002298: e00c b.n 80022b4 <HAL_GPIO_Init+0x240>
- 800229a: 2306 movs r3, #6
- 800229c: e00a b.n 80022b4 <HAL_GPIO_Init+0x240>
- 800229e: 2305 movs r3, #5
- 80022a0: e008 b.n 80022b4 <HAL_GPIO_Init+0x240>
- 80022a2: 2304 movs r3, #4
- 80022a4: e006 b.n 80022b4 <HAL_GPIO_Init+0x240>
- 80022a6: 2303 movs r3, #3
- 80022a8: e004 b.n 80022b4 <HAL_GPIO_Init+0x240>
- 80022aa: 2302 movs r3, #2
- 80022ac: e002 b.n 80022b4 <HAL_GPIO_Init+0x240>
- 80022ae: 2301 movs r3, #1
- 80022b0: e000 b.n 80022b4 <HAL_GPIO_Init+0x240>
- 80022b2: 2300 movs r3, #0
- 80022b4: 69fa ldr r2, [r7, #28]
- 80022b6: f002 0203 and.w r2, r2, #3
- 80022ba: 0092 lsls r2, r2, #2
- 80022bc: 4093 lsls r3, r2
- 80022be: 69ba ldr r2, [r7, #24]
- 80022c0: 4313 orrs r3, r2
- 80022c2: 61bb str r3, [r7, #24]
- SYSCFG->EXTICR[position >> 2] = temp;
- 80022c4: 4934 ldr r1, [pc, #208] ; (8002398 <HAL_GPIO_Init+0x324>)
- 80022c6: 69fb ldr r3, [r7, #28]
- 80022c8: 089b lsrs r3, r3, #2
- 80022ca: 3302 adds r3, #2
- 80022cc: 69ba ldr r2, [r7, #24]
- 80022ce: f841 2023 str.w r2, [r1, r3, lsl #2]
-
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- 80022d2: 4b3c ldr r3, [pc, #240] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 80022d4: 681b ldr r3, [r3, #0]
- 80022d6: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80022d8: 693b ldr r3, [r7, #16]
- 80022da: 43db mvns r3, r3
- 80022dc: 69ba ldr r2, [r7, #24]
- 80022de: 4013 ands r3, r2
- 80022e0: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 80022e2: 683b ldr r3, [r7, #0]
- 80022e4: 685b ldr r3, [r3, #4]
- 80022e6: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 80022ea: 2b00 cmp r3, #0
- 80022ec: d003 beq.n 80022f6 <HAL_GPIO_Init+0x282>
- {
- temp |= iocurrent;
- 80022ee: 69ba ldr r2, [r7, #24]
- 80022f0: 693b ldr r3, [r7, #16]
- 80022f2: 4313 orrs r3, r2
- 80022f4: 61bb str r3, [r7, #24]
- }
- EXTI->IMR = temp;
- 80022f6: 4a33 ldr r2, [pc, #204] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 80022f8: 69bb ldr r3, [r7, #24]
- 80022fa: 6013 str r3, [r2, #0]
-
- temp = EXTI->EMR;
- 80022fc: 4b31 ldr r3, [pc, #196] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 80022fe: 685b ldr r3, [r3, #4]
- 8002300: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8002302: 693b ldr r3, [r7, #16]
- 8002304: 43db mvns r3, r3
- 8002306: 69ba ldr r2, [r7, #24]
- 8002308: 4013 ands r3, r2
- 800230a: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 800230c: 683b ldr r3, [r7, #0]
- 800230e: 685b ldr r3, [r3, #4]
- 8002310: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002314: 2b00 cmp r3, #0
- 8002316: d003 beq.n 8002320 <HAL_GPIO_Init+0x2ac>
- {
- temp |= iocurrent;
- 8002318: 69ba ldr r2, [r7, #24]
- 800231a: 693b ldr r3, [r7, #16]
- 800231c: 4313 orrs r3, r2
- 800231e: 61bb str r3, [r7, #24]
- }
- EXTI->EMR = temp;
- 8002320: 4a28 ldr r2, [pc, #160] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 8002322: 69bb ldr r3, [r7, #24]
- 8002324: 6053 str r3, [r2, #4]
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR;
- 8002326: 4b27 ldr r3, [pc, #156] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 8002328: 689b ldr r3, [r3, #8]
- 800232a: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 800232c: 693b ldr r3, [r7, #16]
- 800232e: 43db mvns r3, r3
- 8002330: 69ba ldr r2, [r7, #24]
- 8002332: 4013 ands r3, r2
- 8002334: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 8002336: 683b ldr r3, [r7, #0]
- 8002338: 685b ldr r3, [r3, #4]
- 800233a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 800233e: 2b00 cmp r3, #0
- 8002340: d003 beq.n 800234a <HAL_GPIO_Init+0x2d6>
- {
- temp |= iocurrent;
- 8002342: 69ba ldr r2, [r7, #24]
- 8002344: 693b ldr r3, [r7, #16]
- 8002346: 4313 orrs r3, r2
- 8002348: 61bb str r3, [r7, #24]
- }
- EXTI->RTSR = temp;
- 800234a: 4a1e ldr r2, [pc, #120] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 800234c: 69bb ldr r3, [r7, #24]
- 800234e: 6093 str r3, [r2, #8]
-
- temp = EXTI->FTSR;
- 8002350: 4b1c ldr r3, [pc, #112] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 8002352: 68db ldr r3, [r3, #12]
- 8002354: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8002356: 693b ldr r3, [r7, #16]
- 8002358: 43db mvns r3, r3
- 800235a: 69ba ldr r2, [r7, #24]
- 800235c: 4013 ands r3, r2
- 800235e: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 8002360: 683b ldr r3, [r7, #0]
- 8002362: 685b ldr r3, [r3, #4]
- 8002364: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8002368: 2b00 cmp r3, #0
- 800236a: d003 beq.n 8002374 <HAL_GPIO_Init+0x300>
- {
- temp |= iocurrent;
- 800236c: 69ba ldr r2, [r7, #24]
- 800236e: 693b ldr r3, [r7, #16]
- 8002370: 4313 orrs r3, r2
- 8002372: 61bb str r3, [r7, #24]
- }
- EXTI->FTSR = temp;
- 8002374: 4a13 ldr r2, [pc, #76] ; (80023c4 <HAL_GPIO_Init+0x350>)
- 8002376: 69bb ldr r3, [r7, #24]
- 8002378: 60d3 str r3, [r2, #12]
- for(position = 0; position < GPIO_NUMBER; position++)
- 800237a: 69fb ldr r3, [r7, #28]
- 800237c: 3301 adds r3, #1
- 800237e: 61fb str r3, [r7, #28]
- 8002380: 69fb ldr r3, [r7, #28]
- 8002382: 2b0f cmp r3, #15
- 8002384: f67f ae86 bls.w 8002094 <HAL_GPIO_Init+0x20>
- }
- }
- }
-}
- 8002388: bf00 nop
- 800238a: 3724 adds r7, #36 ; 0x24
- 800238c: 46bd mov sp, r7
- 800238e: f85d 7b04 ldr.w r7, [sp], #4
- 8002392: 4770 bx lr
- 8002394: 40023800 .word 0x40023800
- 8002398: 40013800 .word 0x40013800
- 800239c: 40020000 .word 0x40020000
- 80023a0: 40020400 .word 0x40020400
- 80023a4: 40020800 .word 0x40020800
- 80023a8: 40020c00 .word 0x40020c00
- 80023ac: 40021000 .word 0x40021000
- 80023b0: 40021400 .word 0x40021400
- 80023b4: 40021800 .word 0x40021800
- 80023b8: 40021c00 .word 0x40021c00
- 80023bc: 40022000 .word 0x40022000
- 80023c0: 40022400 .word 0x40022400
- 80023c4: 40013c00 .word 0x40013c00
-
-080023c8 <HAL_GPIO_WritePin>:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- 80023c8: b480 push {r7}
- 80023ca: b083 sub sp, #12
- 80023cc: af00 add r7, sp, #0
- 80023ce: 6078 str r0, [r7, #4]
- 80023d0: 460b mov r3, r1
- 80023d2: 807b strh r3, [r7, #2]
- 80023d4: 4613 mov r3, r2
- 80023d6: 707b strb r3, [r7, #1]
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- 80023d8: 787b ldrb r3, [r7, #1]
- 80023da: 2b00 cmp r3, #0
- 80023dc: d003 beq.n 80023e6 <HAL_GPIO_WritePin+0x1e>
- {
- GPIOx->BSRR = GPIO_Pin;
- 80023de: 887a ldrh r2, [r7, #2]
- 80023e0: 687b ldr r3, [r7, #4]
- 80023e2: 619a str r2, [r3, #24]
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- }
-}
- 80023e4: e003 b.n 80023ee <HAL_GPIO_WritePin+0x26>
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- 80023e6: 887b ldrh r3, [r7, #2]
- 80023e8: 041a lsls r2, r3, #16
- 80023ea: 687b ldr r3, [r7, #4]
- 80023ec: 619a str r2, [r3, #24]
-}
- 80023ee: bf00 nop
- 80023f0: 370c adds r7, #12
- 80023f2: 46bd mov sp, r7
- 80023f4: f85d 7b04 ldr.w r7, [sp], #4
- 80023f8: 4770 bx lr
- ...
-
-080023fc <HAL_GPIO_EXTI_IRQHandler>:
- * @brief This function handles EXTI interrupt request.
- * @param GPIO_Pin Specifies the pins connected EXTI line
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- 80023fc: b580 push {r7, lr}
- 80023fe: b082 sub sp, #8
- 8002400: af00 add r7, sp, #0
- 8002402: 4603 mov r3, r0
- 8002404: 80fb strh r3, [r7, #6]
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- 8002406: 4b08 ldr r3, [pc, #32] ; (8002428 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 8002408: 695a ldr r2, [r3, #20]
- 800240a: 88fb ldrh r3, [r7, #6]
- 800240c: 4013 ands r3, r2
- 800240e: 2b00 cmp r3, #0
- 8002410: d006 beq.n 8002420 <HAL_GPIO_EXTI_IRQHandler+0x24>
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- 8002412: 4a05 ldr r2, [pc, #20] ; (8002428 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 8002414: 88fb ldrh r3, [r7, #6]
- 8002416: 6153 str r3, [r2, #20]
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- 8002418: 88fb ldrh r3, [r7, #6]
- 800241a: 4618 mov r0, r3
- 800241c: f7ff f9aa bl 8001774 <HAL_GPIO_EXTI_Callback>
- }
-}
- 8002420: bf00 nop
- 8002422: 3708 adds r7, #8
- 8002424: 46bd mov sp, r7
- 8002426: bd80 pop {r7, pc}
- 8002428: 40013c00 .word 0x40013c00
-
-0800242c <HAL_RCC_OscConfig>:
- * supported by this function. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- 800242c: b580 push {r7, lr}
- 800242e: b086 sub sp, #24
- 8002430: af00 add r7, sp, #0
- 8002432: 6078 str r0, [r7, #4]
- uint32_t tickstart;
- FlagStatus pwrclkchanged = RESET;
- 8002434: 2300 movs r3, #0
- 8002436: 75fb strb r3, [r7, #23]
-
- /* Check Null pointer */
- if(RCC_OscInitStruct == NULL)
- 8002438: 687b ldr r3, [r7, #4]
- 800243a: 2b00 cmp r3, #0
- 800243c: d101 bne.n 8002442 <HAL_RCC_OscConfig+0x16>
- {
- return HAL_ERROR;
- 800243e: 2301 movs r3, #1
- 8002440: e25e b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8002442: 687b ldr r3, [r7, #4]
- 8002444: 681b ldr r3, [r3, #0]
- 8002446: f003 0301 and.w r3, r3, #1
- 800244a: 2b00 cmp r3, #0
- 800244c: f000 8087 beq.w 800255e <HAL_RCC_OscConfig+0x132>
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8002450: 4b96 ldr r3, [pc, #600] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002452: 689b ldr r3, [r3, #8]
- 8002454: f003 030c and.w r3, r3, #12
- 8002458: 2b04 cmp r3, #4
- 800245a: d00c beq.n 8002476 <HAL_RCC_OscConfig+0x4a>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 800245c: 4b93 ldr r3, [pc, #588] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800245e: 689b ldr r3, [r3, #8]
- 8002460: f003 030c and.w r3, r3, #12
- 8002464: 2b08 cmp r3, #8
- 8002466: d112 bne.n 800248e <HAL_RCC_OscConfig+0x62>
- 8002468: 4b90 ldr r3, [pc, #576] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800246a: 685b ldr r3, [r3, #4]
- 800246c: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002470: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002474: d10b bne.n 800248e <HAL_RCC_OscConfig+0x62>
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8002476: 4b8d ldr r3, [pc, #564] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002478: 681b ldr r3, [r3, #0]
- 800247a: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800247e: 2b00 cmp r3, #0
- 8002480: d06c beq.n 800255c <HAL_RCC_OscConfig+0x130>
- 8002482: 687b ldr r3, [r7, #4]
- 8002484: 685b ldr r3, [r3, #4]
- 8002486: 2b00 cmp r3, #0
- 8002488: d168 bne.n 800255c <HAL_RCC_OscConfig+0x130>
- {
- return HAL_ERROR;
- 800248a: 2301 movs r3, #1
- 800248c: e238 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 800248e: 687b ldr r3, [r7, #4]
- 8002490: 685b ldr r3, [r3, #4]
- 8002492: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8002496: d106 bne.n 80024a6 <HAL_RCC_OscConfig+0x7a>
- 8002498: 4b84 ldr r3, [pc, #528] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800249a: 681b ldr r3, [r3, #0]
- 800249c: 4a83 ldr r2, [pc, #524] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800249e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 80024a2: 6013 str r3, [r2, #0]
- 80024a4: e02e b.n 8002504 <HAL_RCC_OscConfig+0xd8>
- 80024a6: 687b ldr r3, [r7, #4]
- 80024a8: 685b ldr r3, [r3, #4]
- 80024aa: 2b00 cmp r3, #0
- 80024ac: d10c bne.n 80024c8 <HAL_RCC_OscConfig+0x9c>
- 80024ae: 4b7f ldr r3, [pc, #508] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024b0: 681b ldr r3, [r3, #0]
- 80024b2: 4a7e ldr r2, [pc, #504] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024b4: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 80024b8: 6013 str r3, [r2, #0]
- 80024ba: 4b7c ldr r3, [pc, #496] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024bc: 681b ldr r3, [r3, #0]
- 80024be: 4a7b ldr r2, [pc, #492] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024c0: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80024c4: 6013 str r3, [r2, #0]
- 80024c6: e01d b.n 8002504 <HAL_RCC_OscConfig+0xd8>
- 80024c8: 687b ldr r3, [r7, #4]
- 80024ca: 685b ldr r3, [r3, #4]
- 80024cc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 80024d0: d10c bne.n 80024ec <HAL_RCC_OscConfig+0xc0>
- 80024d2: 4b76 ldr r3, [pc, #472] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024d4: 681b ldr r3, [r3, #0]
- 80024d6: 4a75 ldr r2, [pc, #468] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024d8: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 80024dc: 6013 str r3, [r2, #0]
- 80024de: 4b73 ldr r3, [pc, #460] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024e0: 681b ldr r3, [r3, #0]
- 80024e2: 4a72 ldr r2, [pc, #456] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024e4: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 80024e8: 6013 str r3, [r2, #0]
- 80024ea: e00b b.n 8002504 <HAL_RCC_OscConfig+0xd8>
- 80024ec: 4b6f ldr r3, [pc, #444] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024ee: 681b ldr r3, [r3, #0]
- 80024f0: 4a6e ldr r2, [pc, #440] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024f2: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 80024f6: 6013 str r3, [r2, #0]
- 80024f8: 4b6c ldr r3, [pc, #432] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024fa: 681b ldr r3, [r3, #0]
- 80024fc: 4a6b ldr r2, [pc, #428] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80024fe: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8002502: 6013 str r3, [r2, #0]
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8002504: 687b ldr r3, [r7, #4]
- 8002506: 685b ldr r3, [r3, #4]
- 8002508: 2b00 cmp r3, #0
- 800250a: d013 beq.n 8002534 <HAL_RCC_OscConfig+0x108>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800250c: f7ff fc72 bl 8001df4 <HAL_GetTick>
- 8002510: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8002512: e008 b.n 8002526 <HAL_RCC_OscConfig+0xfa>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8002514: f7ff fc6e bl 8001df4 <HAL_GetTick>
- 8002518: 4602 mov r2, r0
- 800251a: 693b ldr r3, [r7, #16]
- 800251c: 1ad3 subs r3, r2, r3
- 800251e: 2b64 cmp r3, #100 ; 0x64
- 8002520: d901 bls.n 8002526 <HAL_RCC_OscConfig+0xfa>
- {
- return HAL_TIMEOUT;
- 8002522: 2303 movs r3, #3
- 8002524: e1ec b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8002526: 4b61 ldr r3, [pc, #388] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002528: 681b ldr r3, [r3, #0]
- 800252a: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800252e: 2b00 cmp r3, #0
- 8002530: d0f0 beq.n 8002514 <HAL_RCC_OscConfig+0xe8>
- 8002532: e014 b.n 800255e <HAL_RCC_OscConfig+0x132>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002534: f7ff fc5e bl 8001df4 <HAL_GetTick>
- 8002538: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 800253a: e008 b.n 800254e <HAL_RCC_OscConfig+0x122>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 800253c: f7ff fc5a bl 8001df4 <HAL_GetTick>
- 8002540: 4602 mov r2, r0
- 8002542: 693b ldr r3, [r7, #16]
- 8002544: 1ad3 subs r3, r2, r3
- 8002546: 2b64 cmp r3, #100 ; 0x64
- 8002548: d901 bls.n 800254e <HAL_RCC_OscConfig+0x122>
- {
- return HAL_TIMEOUT;
- 800254a: 2303 movs r3, #3
- 800254c: e1d8 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 800254e: 4b57 ldr r3, [pc, #348] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002550: 681b ldr r3, [r3, #0]
- 8002552: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002556: 2b00 cmp r3, #0
- 8002558: d1f0 bne.n 800253c <HAL_RCC_OscConfig+0x110>
- 800255a: e000 b.n 800255e <HAL_RCC_OscConfig+0x132>
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 800255c: bf00 nop
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 800255e: 687b ldr r3, [r7, #4]
- 8002560: 681b ldr r3, [r3, #0]
- 8002562: f003 0302 and.w r3, r3, #2
- 8002566: 2b00 cmp r3, #0
- 8002568: d069 beq.n 800263e <HAL_RCC_OscConfig+0x212>
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 800256a: 4b50 ldr r3, [pc, #320] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800256c: 689b ldr r3, [r3, #8]
- 800256e: f003 030c and.w r3, r3, #12
- 8002572: 2b00 cmp r3, #0
- 8002574: d00b beq.n 800258e <HAL_RCC_OscConfig+0x162>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 8002576: 4b4d ldr r3, [pc, #308] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002578: 689b ldr r3, [r3, #8]
- 800257a: f003 030c and.w r3, r3, #12
- 800257e: 2b08 cmp r3, #8
- 8002580: d11c bne.n 80025bc <HAL_RCC_OscConfig+0x190>
- 8002582: 4b4a ldr r3, [pc, #296] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002584: 685b ldr r3, [r3, #4]
- 8002586: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800258a: 2b00 cmp r3, #0
- 800258c: d116 bne.n 80025bc <HAL_RCC_OscConfig+0x190>
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 800258e: 4b47 ldr r3, [pc, #284] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002590: 681b ldr r3, [r3, #0]
- 8002592: f003 0302 and.w r3, r3, #2
- 8002596: 2b00 cmp r3, #0
- 8002598: d005 beq.n 80025a6 <HAL_RCC_OscConfig+0x17a>
- 800259a: 687b ldr r3, [r7, #4]
- 800259c: 68db ldr r3, [r3, #12]
- 800259e: 2b01 cmp r3, #1
- 80025a0: d001 beq.n 80025a6 <HAL_RCC_OscConfig+0x17a>
- {
- return HAL_ERROR;
- 80025a2: 2301 movs r3, #1
- 80025a4: e1ac b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80025a6: 4b41 ldr r3, [pc, #260] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80025a8: 681b ldr r3, [r3, #0]
- 80025aa: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 80025ae: 687b ldr r3, [r7, #4]
- 80025b0: 691b ldr r3, [r3, #16]
- 80025b2: 00db lsls r3, r3, #3
- 80025b4: 493d ldr r1, [pc, #244] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80025b6: 4313 orrs r3, r2
- 80025b8: 600b str r3, [r1, #0]
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80025ba: e040 b.n 800263e <HAL_RCC_OscConfig+0x212>
- }
- }
- else
- {
- /* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 80025bc: 687b ldr r3, [r7, #4]
- 80025be: 68db ldr r3, [r3, #12]
- 80025c0: 2b00 cmp r3, #0
- 80025c2: d023 beq.n 800260c <HAL_RCC_OscConfig+0x1e0>
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
- 80025c4: 4b39 ldr r3, [pc, #228] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80025c6: 681b ldr r3, [r3, #0]
- 80025c8: 4a38 ldr r2, [pc, #224] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80025ca: f043 0301 orr.w r3, r3, #1
- 80025ce: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80025d0: f7ff fc10 bl 8001df4 <HAL_GetTick>
- 80025d4: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80025d6: e008 b.n 80025ea <HAL_RCC_OscConfig+0x1be>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80025d8: f7ff fc0c bl 8001df4 <HAL_GetTick>
- 80025dc: 4602 mov r2, r0
- 80025de: 693b ldr r3, [r7, #16]
- 80025e0: 1ad3 subs r3, r2, r3
- 80025e2: 2b02 cmp r3, #2
- 80025e4: d901 bls.n 80025ea <HAL_RCC_OscConfig+0x1be>
- {
- return HAL_TIMEOUT;
- 80025e6: 2303 movs r3, #3
- 80025e8: e18a b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80025ea: 4b30 ldr r3, [pc, #192] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80025ec: 681b ldr r3, [r3, #0]
- 80025ee: f003 0302 and.w r3, r3, #2
- 80025f2: 2b00 cmp r3, #0
- 80025f4: d0f0 beq.n 80025d8 <HAL_RCC_OscConfig+0x1ac>
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80025f6: 4b2d ldr r3, [pc, #180] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 80025f8: 681b ldr r3, [r3, #0]
- 80025fa: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 80025fe: 687b ldr r3, [r7, #4]
- 8002600: 691b ldr r3, [r3, #16]
- 8002602: 00db lsls r3, r3, #3
- 8002604: 4929 ldr r1, [pc, #164] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002606: 4313 orrs r3, r2
- 8002608: 600b str r3, [r1, #0]
- 800260a: e018 b.n 800263e <HAL_RCC_OscConfig+0x212>
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
- 800260c: 4b27 ldr r3, [pc, #156] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800260e: 681b ldr r3, [r3, #0]
- 8002610: 4a26 ldr r2, [pc, #152] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002612: f023 0301 bic.w r3, r3, #1
- 8002616: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002618: f7ff fbec bl 8001df4 <HAL_GetTick>
- 800261c: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 800261e: e008 b.n 8002632 <HAL_RCC_OscConfig+0x206>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8002620: f7ff fbe8 bl 8001df4 <HAL_GetTick>
- 8002624: 4602 mov r2, r0
- 8002626: 693b ldr r3, [r7, #16]
- 8002628: 1ad3 subs r3, r2, r3
- 800262a: 2b02 cmp r3, #2
- 800262c: d901 bls.n 8002632 <HAL_RCC_OscConfig+0x206>
- {
- return HAL_TIMEOUT;
- 800262e: 2303 movs r3, #3
- 8002630: e166 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8002632: 4b1e ldr r3, [pc, #120] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002634: 681b ldr r3, [r3, #0]
- 8002636: f003 0302 and.w r3, r3, #2
- 800263a: 2b00 cmp r3, #0
- 800263c: d1f0 bne.n 8002620 <HAL_RCC_OscConfig+0x1f4>
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 800263e: 687b ldr r3, [r7, #4]
- 8002640: 681b ldr r3, [r3, #0]
- 8002642: f003 0308 and.w r3, r3, #8
- 8002646: 2b00 cmp r3, #0
- 8002648: d038 beq.n 80026bc <HAL_RCC_OscConfig+0x290>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 800264a: 687b ldr r3, [r7, #4]
- 800264c: 695b ldr r3, [r3, #20]
- 800264e: 2b00 cmp r3, #0
- 8002650: d019 beq.n 8002686 <HAL_RCC_OscConfig+0x25a>
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
- 8002652: 4b16 ldr r3, [pc, #88] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002654: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002656: 4a15 ldr r2, [pc, #84] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002658: f043 0301 orr.w r3, r3, #1
- 800265c: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800265e: f7ff fbc9 bl 8001df4 <HAL_GetTick>
- 8002662: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8002664: e008 b.n 8002678 <HAL_RCC_OscConfig+0x24c>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8002666: f7ff fbc5 bl 8001df4 <HAL_GetTick>
- 800266a: 4602 mov r2, r0
- 800266c: 693b ldr r3, [r7, #16]
- 800266e: 1ad3 subs r3, r2, r3
- 8002670: 2b02 cmp r3, #2
- 8002672: d901 bls.n 8002678 <HAL_RCC_OscConfig+0x24c>
- {
- return HAL_TIMEOUT;
- 8002674: 2303 movs r3, #3
- 8002676: e143 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8002678: 4b0c ldr r3, [pc, #48] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800267a: 6f5b ldr r3, [r3, #116] ; 0x74
- 800267c: f003 0302 and.w r3, r3, #2
- 8002680: 2b00 cmp r3, #0
- 8002682: d0f0 beq.n 8002666 <HAL_RCC_OscConfig+0x23a>
- 8002684: e01a b.n 80026bc <HAL_RCC_OscConfig+0x290>
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
- 8002686: 4b09 ldr r3, [pc, #36] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 8002688: 6f5b ldr r3, [r3, #116] ; 0x74
- 800268a: 4a08 ldr r2, [pc, #32] ; (80026ac <HAL_RCC_OscConfig+0x280>)
- 800268c: f023 0301 bic.w r3, r3, #1
- 8002690: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002692: f7ff fbaf bl 8001df4 <HAL_GetTick>
- 8002696: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8002698: e00a b.n 80026b0 <HAL_RCC_OscConfig+0x284>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800269a: f7ff fbab bl 8001df4 <HAL_GetTick>
- 800269e: 4602 mov r2, r0
- 80026a0: 693b ldr r3, [r7, #16]
- 80026a2: 1ad3 subs r3, r2, r3
- 80026a4: 2b02 cmp r3, #2
- 80026a6: d903 bls.n 80026b0 <HAL_RCC_OscConfig+0x284>
- {
- return HAL_TIMEOUT;
- 80026a8: 2303 movs r3, #3
- 80026aa: e129 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- 80026ac: 40023800 .word 0x40023800
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 80026b0: 4b95 ldr r3, [pc, #596] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80026b2: 6f5b ldr r3, [r3, #116] ; 0x74
- 80026b4: f003 0302 and.w r3, r3, #2
- 80026b8: 2b00 cmp r3, #0
- 80026ba: d1ee bne.n 800269a <HAL_RCC_OscConfig+0x26e>
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 80026bc: 687b ldr r3, [r7, #4]
- 80026be: 681b ldr r3, [r3, #0]
- 80026c0: f003 0304 and.w r3, r3, #4
- 80026c4: 2b00 cmp r3, #0
- 80026c6: f000 80a4 beq.w 8002812 <HAL_RCC_OscConfig+0x3e6>
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80026ca: 4b8f ldr r3, [pc, #572] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80026cc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80026ce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80026d2: 2b00 cmp r3, #0
- 80026d4: d10d bne.n 80026f2 <HAL_RCC_OscConfig+0x2c6>
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 80026d6: 4b8c ldr r3, [pc, #560] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80026d8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80026da: 4a8b ldr r2, [pc, #556] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80026dc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80026e0: 6413 str r3, [r2, #64] ; 0x40
- 80026e2: 4b89 ldr r3, [pc, #548] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80026e4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80026e6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80026ea: 60fb str r3, [r7, #12]
- 80026ec: 68fb ldr r3, [r7, #12]
- pwrclkchanged = SET;
- 80026ee: 2301 movs r3, #1
- 80026f0: 75fb strb r3, [r7, #23]
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80026f2: 4b86 ldr r3, [pc, #536] ; (800290c <HAL_RCC_OscConfig+0x4e0>)
- 80026f4: 681b ldr r3, [r3, #0]
- 80026f6: f403 7380 and.w r3, r3, #256 ; 0x100
- 80026fa: 2b00 cmp r3, #0
- 80026fc: d118 bne.n 8002730 <HAL_RCC_OscConfig+0x304>
- {
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 80026fe: 4b83 ldr r3, [pc, #524] ; (800290c <HAL_RCC_OscConfig+0x4e0>)
- 8002700: 681b ldr r3, [r3, #0]
- 8002702: 4a82 ldr r2, [pc, #520] ; (800290c <HAL_RCC_OscConfig+0x4e0>)
- 8002704: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8002708: 6013 str r3, [r2, #0]
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
- 800270a: f7ff fb73 bl 8001df4 <HAL_GetTick>
- 800270e: 6138 str r0, [r7, #16]
-
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8002710: e008 b.n 8002724 <HAL_RCC_OscConfig+0x2f8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 8002712: f7ff fb6f bl 8001df4 <HAL_GetTick>
- 8002716: 4602 mov r2, r0
- 8002718: 693b ldr r3, [r7, #16]
- 800271a: 1ad3 subs r3, r2, r3
- 800271c: 2b64 cmp r3, #100 ; 0x64
- 800271e: d901 bls.n 8002724 <HAL_RCC_OscConfig+0x2f8>
- {
- return HAL_TIMEOUT;
- 8002720: 2303 movs r3, #3
- 8002722: e0ed b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8002724: 4b79 ldr r3, [pc, #484] ; (800290c <HAL_RCC_OscConfig+0x4e0>)
- 8002726: 681b ldr r3, [r3, #0]
- 8002728: f403 7380 and.w r3, r3, #256 ; 0x100
- 800272c: 2b00 cmp r3, #0
- 800272e: d0f0 beq.n 8002712 <HAL_RCC_OscConfig+0x2e6>
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8002730: 687b ldr r3, [r7, #4]
- 8002732: 689b ldr r3, [r3, #8]
- 8002734: 2b01 cmp r3, #1
- 8002736: d106 bne.n 8002746 <HAL_RCC_OscConfig+0x31a>
- 8002738: 4b73 ldr r3, [pc, #460] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800273a: 6f1b ldr r3, [r3, #112] ; 0x70
- 800273c: 4a72 ldr r2, [pc, #456] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800273e: f043 0301 orr.w r3, r3, #1
- 8002742: 6713 str r3, [r2, #112] ; 0x70
- 8002744: e02d b.n 80027a2 <HAL_RCC_OscConfig+0x376>
- 8002746: 687b ldr r3, [r7, #4]
- 8002748: 689b ldr r3, [r3, #8]
- 800274a: 2b00 cmp r3, #0
- 800274c: d10c bne.n 8002768 <HAL_RCC_OscConfig+0x33c>
- 800274e: 4b6e ldr r3, [pc, #440] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002750: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002752: 4a6d ldr r2, [pc, #436] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002754: f023 0301 bic.w r3, r3, #1
- 8002758: 6713 str r3, [r2, #112] ; 0x70
- 800275a: 4b6b ldr r3, [pc, #428] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800275c: 6f1b ldr r3, [r3, #112] ; 0x70
- 800275e: 4a6a ldr r2, [pc, #424] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002760: f023 0304 bic.w r3, r3, #4
- 8002764: 6713 str r3, [r2, #112] ; 0x70
- 8002766: e01c b.n 80027a2 <HAL_RCC_OscConfig+0x376>
- 8002768: 687b ldr r3, [r7, #4]
- 800276a: 689b ldr r3, [r3, #8]
- 800276c: 2b05 cmp r3, #5
- 800276e: d10c bne.n 800278a <HAL_RCC_OscConfig+0x35e>
- 8002770: 4b65 ldr r3, [pc, #404] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002772: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002774: 4a64 ldr r2, [pc, #400] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002776: f043 0304 orr.w r3, r3, #4
- 800277a: 6713 str r3, [r2, #112] ; 0x70
- 800277c: 4b62 ldr r3, [pc, #392] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800277e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002780: 4a61 ldr r2, [pc, #388] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002782: f043 0301 orr.w r3, r3, #1
- 8002786: 6713 str r3, [r2, #112] ; 0x70
- 8002788: e00b b.n 80027a2 <HAL_RCC_OscConfig+0x376>
- 800278a: 4b5f ldr r3, [pc, #380] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800278c: 6f1b ldr r3, [r3, #112] ; 0x70
- 800278e: 4a5e ldr r2, [pc, #376] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002790: f023 0301 bic.w r3, r3, #1
- 8002794: 6713 str r3, [r2, #112] ; 0x70
- 8002796: 4b5c ldr r3, [pc, #368] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002798: 6f1b ldr r3, [r3, #112] ; 0x70
- 800279a: 4a5b ldr r2, [pc, #364] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800279c: f023 0304 bic.w r3, r3, #4
- 80027a0: 6713 str r3, [r2, #112] ; 0x70
- /* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 80027a2: 687b ldr r3, [r7, #4]
- 80027a4: 689b ldr r3, [r3, #8]
- 80027a6: 2b00 cmp r3, #0
- 80027a8: d015 beq.n 80027d6 <HAL_RCC_OscConfig+0x3aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80027aa: f7ff fb23 bl 8001df4 <HAL_GetTick>
- 80027ae: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80027b0: e00a b.n 80027c8 <HAL_RCC_OscConfig+0x39c>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80027b2: f7ff fb1f bl 8001df4 <HAL_GetTick>
- 80027b6: 4602 mov r2, r0
- 80027b8: 693b ldr r3, [r7, #16]
- 80027ba: 1ad3 subs r3, r2, r3
- 80027bc: f241 3288 movw r2, #5000 ; 0x1388
- 80027c0: 4293 cmp r3, r2
- 80027c2: d901 bls.n 80027c8 <HAL_RCC_OscConfig+0x39c>
- {
- return HAL_TIMEOUT;
- 80027c4: 2303 movs r3, #3
- 80027c6: e09b b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80027c8: 4b4f ldr r3, [pc, #316] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80027ca: 6f1b ldr r3, [r3, #112] ; 0x70
- 80027cc: f003 0302 and.w r3, r3, #2
- 80027d0: 2b00 cmp r3, #0
- 80027d2: d0ee beq.n 80027b2 <HAL_RCC_OscConfig+0x386>
- 80027d4: e014 b.n 8002800 <HAL_RCC_OscConfig+0x3d4>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80027d6: f7ff fb0d bl 8001df4 <HAL_GetTick>
- 80027da: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80027dc: e00a b.n 80027f4 <HAL_RCC_OscConfig+0x3c8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80027de: f7ff fb09 bl 8001df4 <HAL_GetTick>
- 80027e2: 4602 mov r2, r0
- 80027e4: 693b ldr r3, [r7, #16]
- 80027e6: 1ad3 subs r3, r2, r3
- 80027e8: f241 3288 movw r2, #5000 ; 0x1388
- 80027ec: 4293 cmp r3, r2
- 80027ee: d901 bls.n 80027f4 <HAL_RCC_OscConfig+0x3c8>
- {
- return HAL_TIMEOUT;
- 80027f0: 2303 movs r3, #3
- 80027f2: e085 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80027f4: 4b44 ldr r3, [pc, #272] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80027f6: 6f1b ldr r3, [r3, #112] ; 0x70
- 80027f8: f003 0302 and.w r3, r3, #2
- 80027fc: 2b00 cmp r3, #0
- 80027fe: d1ee bne.n 80027de <HAL_RCC_OscConfig+0x3b2>
- }
- }
- }
-
- /* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
- 8002800: 7dfb ldrb r3, [r7, #23]
- 8002802: 2b01 cmp r3, #1
- 8002804: d105 bne.n 8002812 <HAL_RCC_OscConfig+0x3e6>
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- 8002806: 4b40 ldr r3, [pc, #256] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002808: 6c1b ldr r3, [r3, #64] ; 0x40
- 800280a: 4a3f ldr r2, [pc, #252] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800280c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8002810: 6413 str r3, [r2, #64] ; 0x40
- }
- }
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8002812: 687b ldr r3, [r7, #4]
- 8002814: 699b ldr r3, [r3, #24]
- 8002816: 2b00 cmp r3, #0
- 8002818: d071 beq.n 80028fe <HAL_RCC_OscConfig+0x4d2>
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 800281a: 4b3b ldr r3, [pc, #236] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800281c: 689b ldr r3, [r3, #8]
- 800281e: f003 030c and.w r3, r3, #12
- 8002822: 2b08 cmp r3, #8
- 8002824: d069 beq.n 80028fa <HAL_RCC_OscConfig+0x4ce>
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8002826: 687b ldr r3, [r7, #4]
- 8002828: 699b ldr r3, [r3, #24]
- 800282a: 2b02 cmp r3, #2
- 800282c: d14b bne.n 80028c6 <HAL_RCC_OscConfig+0x49a>
-#if defined (RCC_PLLCFGR_PLLR)
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-#endif
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 800282e: 4b36 ldr r3, [pc, #216] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002830: 681b ldr r3, [r3, #0]
- 8002832: 4a35 ldr r2, [pc, #212] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002834: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002838: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800283a: f7ff fadb bl 8001df4 <HAL_GetTick>
- 800283e: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002840: e008 b.n 8002854 <HAL_RCC_OscConfig+0x428>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8002842: f7ff fad7 bl 8001df4 <HAL_GetTick>
- 8002846: 4602 mov r2, r0
- 8002848: 693b ldr r3, [r7, #16]
- 800284a: 1ad3 subs r3, r2, r3
- 800284c: 2b02 cmp r3, #2
- 800284e: d901 bls.n 8002854 <HAL_RCC_OscConfig+0x428>
- {
- return HAL_TIMEOUT;
- 8002850: 2303 movs r3, #3
- 8002852: e055 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002854: 4b2c ldr r3, [pc, #176] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002856: 681b ldr r3, [r3, #0]
- 8002858: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 800285c: 2b00 cmp r3, #0
- 800285e: d1f0 bne.n 8002842 <HAL_RCC_OscConfig+0x416>
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
-#if defined (RCC_PLLCFGR_PLLR)
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8002860: 687b ldr r3, [r7, #4]
- 8002862: 69da ldr r2, [r3, #28]
- 8002864: 687b ldr r3, [r7, #4]
- 8002866: 6a1b ldr r3, [r3, #32]
- 8002868: 431a orrs r2, r3
- 800286a: 687b ldr r3, [r7, #4]
- 800286c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800286e: 019b lsls r3, r3, #6
- 8002870: 431a orrs r2, r3
- 8002872: 687b ldr r3, [r7, #4]
- 8002874: 6a9b ldr r3, [r3, #40] ; 0x28
- 8002876: 085b lsrs r3, r3, #1
- 8002878: 3b01 subs r3, #1
- 800287a: 041b lsls r3, r3, #16
- 800287c: 431a orrs r2, r3
- 800287e: 687b ldr r3, [r7, #4]
- 8002880: 6adb ldr r3, [r3, #44] ; 0x2c
- 8002882: 061b lsls r3, r3, #24
- 8002884: 431a orrs r2, r3
- 8002886: 687b ldr r3, [r7, #4]
- 8002888: 6b1b ldr r3, [r3, #48] ; 0x30
- 800288a: 071b lsls r3, r3, #28
- 800288c: 491e ldr r1, [pc, #120] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 800288e: 4313 orrs r3, r2
- 8002890: 604b str r3, [r1, #4]
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
-#endif
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
- 8002892: 4b1d ldr r3, [pc, #116] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002894: 681b ldr r3, [r3, #0]
- 8002896: 4a1c ldr r2, [pc, #112] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 8002898: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 800289c: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800289e: f7ff faa9 bl 8001df4 <HAL_GetTick>
- 80028a2: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80028a4: e008 b.n 80028b8 <HAL_RCC_OscConfig+0x48c>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80028a6: f7ff faa5 bl 8001df4 <HAL_GetTick>
- 80028aa: 4602 mov r2, r0
- 80028ac: 693b ldr r3, [r7, #16]
- 80028ae: 1ad3 subs r3, r2, r3
- 80028b0: 2b02 cmp r3, #2
- 80028b2: d901 bls.n 80028b8 <HAL_RCC_OscConfig+0x48c>
- {
- return HAL_TIMEOUT;
- 80028b4: 2303 movs r3, #3
- 80028b6: e023 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80028b8: 4b13 ldr r3, [pc, #76] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80028ba: 681b ldr r3, [r3, #0]
- 80028bc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80028c0: 2b00 cmp r3, #0
- 80028c2: d0f0 beq.n 80028a6 <HAL_RCC_OscConfig+0x47a>
- 80028c4: e01b b.n 80028fe <HAL_RCC_OscConfig+0x4d2>
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 80028c6: 4b10 ldr r3, [pc, #64] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80028c8: 681b ldr r3, [r3, #0]
- 80028ca: 4a0f ldr r2, [pc, #60] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80028cc: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80028d0: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80028d2: f7ff fa8f bl 8001df4 <HAL_GetTick>
- 80028d6: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80028d8: e008 b.n 80028ec <HAL_RCC_OscConfig+0x4c0>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80028da: f7ff fa8b bl 8001df4 <HAL_GetTick>
- 80028de: 4602 mov r2, r0
- 80028e0: 693b ldr r3, [r7, #16]
- 80028e2: 1ad3 subs r3, r2, r3
- 80028e4: 2b02 cmp r3, #2
- 80028e6: d901 bls.n 80028ec <HAL_RCC_OscConfig+0x4c0>
- {
- return HAL_TIMEOUT;
- 80028e8: 2303 movs r3, #3
- 80028ea: e009 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80028ec: 4b06 ldr r3, [pc, #24] ; (8002908 <HAL_RCC_OscConfig+0x4dc>)
- 80028ee: 681b ldr r3, [r3, #0]
- 80028f0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80028f4: 2b00 cmp r3, #0
- 80028f6: d1f0 bne.n 80028da <HAL_RCC_OscConfig+0x4ae>
- 80028f8: e001 b.n 80028fe <HAL_RCC_OscConfig+0x4d2>
- }
- }
- }
- else
- {
- return HAL_ERROR;
- 80028fa: 2301 movs r3, #1
- 80028fc: e000 b.n 8002900 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- return HAL_OK;
- 80028fe: 2300 movs r3, #0
-}
- 8002900: 4618 mov r0, r3
- 8002902: 3718 adds r7, #24
- 8002904: 46bd mov sp, r7
- 8002906: bd80 pop {r7, pc}
- 8002908: 40023800 .word 0x40023800
- 800290c: 40007000 .word 0x40007000
-
-08002910 <HAL_RCC_ClockConfig>:
- * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 8002910: b580 push {r7, lr}
- 8002912: b084 sub sp, #16
- 8002914: af00 add r7, sp, #0
- 8002916: 6078 str r0, [r7, #4]
- 8002918: 6039 str r1, [r7, #0]
- uint32_t tickstart = 0;
- 800291a: 2300 movs r3, #0
- 800291c: 60fb str r3, [r7, #12]
-
- /* Check Null pointer */
- if(RCC_ClkInitStruct == NULL)
- 800291e: 687b ldr r3, [r7, #4]
- 8002920: 2b00 cmp r3, #0
- 8002922: d101 bne.n 8002928 <HAL_RCC_ClockConfig+0x18>
- {
- return HAL_ERROR;
- 8002924: 2301 movs r3, #1
- 8002926: e0ce b.n 8002ac6 <HAL_RCC_ClockConfig+0x1b6>
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
- /* Increasing the CPU frequency */
- if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8002928: 4b69 ldr r3, [pc, #420] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 800292a: 681b ldr r3, [r3, #0]
- 800292c: f003 030f and.w r3, r3, #15
- 8002930: 683a ldr r2, [r7, #0]
- 8002932: 429a cmp r2, r3
- 8002934: d910 bls.n 8002958 <HAL_RCC_ClockConfig+0x48>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 8002936: 4b66 ldr r3, [pc, #408] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 8002938: 681b ldr r3, [r3, #0]
- 800293a: f023 020f bic.w r2, r3, #15
- 800293e: 4964 ldr r1, [pc, #400] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 8002940: 683b ldr r3, [r7, #0]
- 8002942: 4313 orrs r3, r2
- 8002944: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002946: 4b62 ldr r3, [pc, #392] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 8002948: 681b ldr r3, [r3, #0]
- 800294a: f003 030f and.w r3, r3, #15
- 800294e: 683a ldr r2, [r7, #0]
- 8002950: 429a cmp r2, r3
- 8002952: d001 beq.n 8002958 <HAL_RCC_ClockConfig+0x48>
- {
- return HAL_ERROR;
- 8002954: 2301 movs r3, #1
- 8002956: e0b6 b.n 8002ac6 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8002958: 687b ldr r3, [r7, #4]
- 800295a: 681b ldr r3, [r3, #0]
- 800295c: f003 0302 and.w r3, r3, #2
- 8002960: 2b00 cmp r3, #0
- 8002962: d020 beq.n 80029a6 <HAL_RCC_ClockConfig+0x96>
- {
- /* Set the highest APBx dividers in order to ensure that we do not go through
- a non-spec phase whatever we decrease or increase HCLK. */
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002964: 687b ldr r3, [r7, #4]
- 8002966: 681b ldr r3, [r3, #0]
- 8002968: f003 0304 and.w r3, r3, #4
- 800296c: 2b00 cmp r3, #0
- 800296e: d005 beq.n 800297c <HAL_RCC_ClockConfig+0x6c>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 8002970: 4b58 ldr r3, [pc, #352] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002972: 689b ldr r3, [r3, #8]
- 8002974: 4a57 ldr r2, [pc, #348] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002976: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 800297a: 6093 str r3, [r2, #8]
- }
-
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 800297c: 687b ldr r3, [r7, #4]
- 800297e: 681b ldr r3, [r3, #0]
- 8002980: f003 0308 and.w r3, r3, #8
- 8002984: 2b00 cmp r3, #0
- 8002986: d005 beq.n 8002994 <HAL_RCC_ClockConfig+0x84>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 8002988: 4b52 ldr r3, [pc, #328] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 800298a: 689b ldr r3, [r3, #8]
- 800298c: 4a51 ldr r2, [pc, #324] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 800298e: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 8002992: 6093 str r3, [r2, #8]
- }
-
- /* Set the new HCLK clock divider */
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8002994: 4b4f ldr r3, [pc, #316] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002996: 689b ldr r3, [r3, #8]
- 8002998: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 800299c: 687b ldr r3, [r7, #4]
- 800299e: 689b ldr r3, [r3, #8]
- 80029a0: 494c ldr r1, [pc, #304] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 80029a2: 4313 orrs r3, r2
- 80029a4: 608b str r3, [r1, #8]
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 80029a6: 687b ldr r3, [r7, #4]
- 80029a8: 681b ldr r3, [r3, #0]
- 80029aa: f003 0301 and.w r3, r3, #1
- 80029ae: 2b00 cmp r3, #0
- 80029b0: d040 beq.n 8002a34 <HAL_RCC_ClockConfig+0x124>
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 80029b2: 687b ldr r3, [r7, #4]
- 80029b4: 685b ldr r3, [r3, #4]
- 80029b6: 2b01 cmp r3, #1
- 80029b8: d107 bne.n 80029ca <HAL_RCC_ClockConfig+0xba>
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80029ba: 4b46 ldr r3, [pc, #280] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 80029bc: 681b ldr r3, [r3, #0]
- 80029be: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80029c2: 2b00 cmp r3, #0
- 80029c4: d115 bne.n 80029f2 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80029c6: 2301 movs r3, #1
- 80029c8: e07d b.n 8002ac6 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 80029ca: 687b ldr r3, [r7, #4]
- 80029cc: 685b ldr r3, [r3, #4]
- 80029ce: 2b02 cmp r3, #2
- 80029d0: d107 bne.n 80029e2 <HAL_RCC_ClockConfig+0xd2>
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80029d2: 4b40 ldr r3, [pc, #256] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 80029d4: 681b ldr r3, [r3, #0]
- 80029d6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80029da: 2b00 cmp r3, #0
- 80029dc: d109 bne.n 80029f2 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80029de: 2301 movs r3, #1
- 80029e0: e071 b.n 8002ac6 <HAL_RCC_ClockConfig+0x1b6>
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80029e2: 4b3c ldr r3, [pc, #240] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 80029e4: 681b ldr r3, [r3, #0]
- 80029e6: f003 0302 and.w r3, r3, #2
- 80029ea: 2b00 cmp r3, #0
- 80029ec: d101 bne.n 80029f2 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80029ee: 2301 movs r3, #1
- 80029f0: e069 b.n 8002ac6 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 80029f2: 4b38 ldr r3, [pc, #224] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 80029f4: 689b ldr r3, [r3, #8]
- 80029f6: f023 0203 bic.w r2, r3, #3
- 80029fa: 687b ldr r3, [r7, #4]
- 80029fc: 685b ldr r3, [r3, #4]
- 80029fe: 4935 ldr r1, [pc, #212] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a00: 4313 orrs r3, r2
- 8002a02: 608b str r3, [r1, #8]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002a04: f7ff f9f6 bl 8001df4 <HAL_GetTick>
- 8002a08: 60f8 str r0, [r7, #12]
-
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8002a0a: e00a b.n 8002a22 <HAL_RCC_ClockConfig+0x112>
- {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002a0c: f7ff f9f2 bl 8001df4 <HAL_GetTick>
- 8002a10: 4602 mov r2, r0
- 8002a12: 68fb ldr r3, [r7, #12]
- 8002a14: 1ad3 subs r3, r2, r3
- 8002a16: f241 3288 movw r2, #5000 ; 0x1388
- 8002a1a: 4293 cmp r3, r2
- 8002a1c: d901 bls.n 8002a22 <HAL_RCC_ClockConfig+0x112>
- {
- return HAL_TIMEOUT;
- 8002a1e: 2303 movs r3, #3
- 8002a20: e051 b.n 8002ac6 <HAL_RCC_ClockConfig+0x1b6>
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8002a22: 4b2c ldr r3, [pc, #176] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a24: 689b ldr r3, [r3, #8]
- 8002a26: f003 020c and.w r2, r3, #12
- 8002a2a: 687b ldr r3, [r7, #4]
- 8002a2c: 685b ldr r3, [r3, #4]
- 8002a2e: 009b lsls r3, r3, #2
- 8002a30: 429a cmp r2, r3
- 8002a32: d1eb bne.n 8002a0c <HAL_RCC_ClockConfig+0xfc>
- }
- }
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8002a34: 4b26 ldr r3, [pc, #152] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a36: 681b ldr r3, [r3, #0]
- 8002a38: f003 030f and.w r3, r3, #15
- 8002a3c: 683a ldr r2, [r7, #0]
- 8002a3e: 429a cmp r2, r3
- 8002a40: d210 bcs.n 8002a64 <HAL_RCC_ClockConfig+0x154>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 8002a42: 4b23 ldr r3, [pc, #140] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a44: 681b ldr r3, [r3, #0]
- 8002a46: f023 020f bic.w r2, r3, #15
- 8002a4a: 4921 ldr r1, [pc, #132] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a4c: 683b ldr r3, [r7, #0]
- 8002a4e: 4313 orrs r3, r2
- 8002a50: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002a52: 4b1f ldr r3, [pc, #124] ; (8002ad0 <HAL_RCC_ClockConfig+0x1c0>)
- 8002a54: 681b ldr r3, [r3, #0]
- 8002a56: f003 030f and.w r3, r3, #15
- 8002a5a: 683a ldr r2, [r7, #0]
- 8002a5c: 429a cmp r2, r3
- 8002a5e: d001 beq.n 8002a64 <HAL_RCC_ClockConfig+0x154>
- {
- return HAL_ERROR;
- 8002a60: 2301 movs r3, #1
- 8002a62: e030 b.n 8002ac6 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002a64: 687b ldr r3, [r7, #4]
- 8002a66: 681b ldr r3, [r3, #0]
- 8002a68: f003 0304 and.w r3, r3, #4
- 8002a6c: 2b00 cmp r3, #0
- 8002a6e: d008 beq.n 8002a82 <HAL_RCC_ClockConfig+0x172>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8002a70: 4b18 ldr r3, [pc, #96] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a72: 689b ldr r3, [r3, #8]
- 8002a74: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 8002a78: 687b ldr r3, [r7, #4]
- 8002a7a: 68db ldr r3, [r3, #12]
- 8002a7c: 4915 ldr r1, [pc, #84] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a7e: 4313 orrs r3, r2
- 8002a80: 608b str r3, [r1, #8]
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8002a82: 687b ldr r3, [r7, #4]
- 8002a84: 681b ldr r3, [r3, #0]
- 8002a86: f003 0308 and.w r3, r3, #8
- 8002a8a: 2b00 cmp r3, #0
- 8002a8c: d009 beq.n 8002aa2 <HAL_RCC_ClockConfig+0x192>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 8002a8e: 4b11 ldr r3, [pc, #68] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a90: 689b ldr r3, [r3, #8]
- 8002a92: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 8002a96: 687b ldr r3, [r7, #4]
- 8002a98: 691b ldr r3, [r3, #16]
- 8002a9a: 00db lsls r3, r3, #3
- 8002a9c: 490d ldr r1, [pc, #52] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002a9e: 4313 orrs r3, r2
- 8002aa0: 608b str r3, [r1, #8]
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 8002aa2: f000 f81d bl 8002ae0 <HAL_RCC_GetSysClockFreq>
- 8002aa6: 4601 mov r1, r0
- 8002aa8: 4b0a ldr r3, [pc, #40] ; (8002ad4 <HAL_RCC_ClockConfig+0x1c4>)
- 8002aaa: 689b ldr r3, [r3, #8]
- 8002aac: 091b lsrs r3, r3, #4
- 8002aae: f003 030f and.w r3, r3, #15
- 8002ab2: 4a09 ldr r2, [pc, #36] ; (8002ad8 <HAL_RCC_ClockConfig+0x1c8>)
- 8002ab4: 5cd3 ldrb r3, [r2, r3]
- 8002ab6: fa21 f303 lsr.w r3, r1, r3
- 8002aba: 4a08 ldr r2, [pc, #32] ; (8002adc <HAL_RCC_ClockConfig+0x1cc>)
- 8002abc: 6013 str r3, [r2, #0]
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
- 8002abe: 2000 movs r0, #0
- 8002ac0: f7ff f954 bl 8001d6c <HAL_InitTick>
-
- return HAL_OK;
- 8002ac4: 2300 movs r3, #0
-}
- 8002ac6: 4618 mov r0, r3
- 8002ac8: 3710 adds r7, #16
- 8002aca: 46bd mov sp, r7
- 8002acc: bd80 pop {r7, pc}
- 8002ace: bf00 nop
- 8002ad0: 40023c00 .word 0x40023c00
- 8002ad4: 40023800 .word 0x40023800
- 8002ad8: 08005604 .word 0x08005604
- 8002adc: 20000004 .word 0x20000004
-
-08002ae0 <HAL_RCC_GetSysClockFreq>:
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- 8002ae0: b5f0 push {r4, r5, r6, r7, lr}
- 8002ae2: b085 sub sp, #20
- 8002ae4: af00 add r7, sp, #0
- uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 8002ae6: 2300 movs r3, #0
- 8002ae8: 607b str r3, [r7, #4]
- 8002aea: 2300 movs r3, #0
- 8002aec: 60fb str r3, [r7, #12]
- 8002aee: 2300 movs r3, #0
- 8002af0: 603b str r3, [r7, #0]
- uint32_t sysclockfreq = 0;
- 8002af2: 2300 movs r3, #0
- 8002af4: 60bb str r3, [r7, #8]
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (RCC->CFGR & RCC_CFGR_SWS)
- 8002af6: 4b50 ldr r3, [pc, #320] ; (8002c38 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002af8: 689b ldr r3, [r3, #8]
- 8002afa: f003 030c and.w r3, r3, #12
- 8002afe: 2b04 cmp r3, #4
- 8002b00: d007 beq.n 8002b12 <HAL_RCC_GetSysClockFreq+0x32>
- 8002b02: 2b08 cmp r3, #8
- 8002b04: d008 beq.n 8002b18 <HAL_RCC_GetSysClockFreq+0x38>
- 8002b06: 2b00 cmp r3, #0
- 8002b08: f040 808d bne.w 8002c26 <HAL_RCC_GetSysClockFreq+0x146>
- {
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- {
- sysclockfreq = HSI_VALUE;
- 8002b0c: 4b4b ldr r3, [pc, #300] ; (8002c3c <HAL_RCC_GetSysClockFreq+0x15c>)
- 8002b0e: 60bb str r3, [r7, #8]
- break;
- 8002b10: e08c b.n 8002c2c <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- {
- sysclockfreq = HSE_VALUE;
- 8002b12: 4b4b ldr r3, [pc, #300] ; (8002c40 <HAL_RCC_GetSysClockFreq+0x160>)
- 8002b14: 60bb str r3, [r7, #8]
- break;
- 8002b16: e089 b.n 8002c2c <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
- {
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP */
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 8002b18: 4b47 ldr r3, [pc, #284] ; (8002c38 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002b1a: 685b ldr r3, [r3, #4]
- 8002b1c: f003 033f and.w r3, r3, #63 ; 0x3f
- 8002b20: 607b str r3, [r7, #4]
- if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 8002b22: 4b45 ldr r3, [pc, #276] ; (8002c38 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002b24: 685b ldr r3, [r3, #4]
- 8002b26: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002b2a: 2b00 cmp r3, #0
- 8002b2c: d023 beq.n 8002b76 <HAL_RCC_GetSysClockFreq+0x96>
- {
- /* HSE used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002b2e: 4b42 ldr r3, [pc, #264] ; (8002c38 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002b30: 685b ldr r3, [r3, #4]
- 8002b32: 099b lsrs r3, r3, #6
- 8002b34: f04f 0400 mov.w r4, #0
- 8002b38: f240 11ff movw r1, #511 ; 0x1ff
- 8002b3c: f04f 0200 mov.w r2, #0
- 8002b40: ea03 0501 and.w r5, r3, r1
- 8002b44: ea04 0602 and.w r6, r4, r2
- 8002b48: 4a3d ldr r2, [pc, #244] ; (8002c40 <HAL_RCC_GetSysClockFreq+0x160>)
- 8002b4a: fb02 f106 mul.w r1, r2, r6
- 8002b4e: 2200 movs r2, #0
- 8002b50: fb02 f205 mul.w r2, r2, r5
- 8002b54: 440a add r2, r1
- 8002b56: 493a ldr r1, [pc, #232] ; (8002c40 <HAL_RCC_GetSysClockFreq+0x160>)
- 8002b58: fba5 0101 umull r0, r1, r5, r1
- 8002b5c: 1853 adds r3, r2, r1
- 8002b5e: 4619 mov r1, r3
- 8002b60: 687b ldr r3, [r7, #4]
- 8002b62: f04f 0400 mov.w r4, #0
- 8002b66: 461a mov r2, r3
- 8002b68: 4623 mov r3, r4
- 8002b6a: f7fd fb65 bl 8000238 <__aeabi_uldivmod>
- 8002b6e: 4603 mov r3, r0
- 8002b70: 460c mov r4, r1
- 8002b72: 60fb str r3, [r7, #12]
- 8002b74: e049 b.n 8002c0a <HAL_RCC_GetSysClockFreq+0x12a>
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002b76: 4b30 ldr r3, [pc, #192] ; (8002c38 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002b78: 685b ldr r3, [r3, #4]
- 8002b7a: 099b lsrs r3, r3, #6
- 8002b7c: f04f 0400 mov.w r4, #0
- 8002b80: f240 11ff movw r1, #511 ; 0x1ff
- 8002b84: f04f 0200 mov.w r2, #0
- 8002b88: ea03 0501 and.w r5, r3, r1
- 8002b8c: ea04 0602 and.w r6, r4, r2
- 8002b90: 4629 mov r1, r5
- 8002b92: 4632 mov r2, r6
- 8002b94: f04f 0300 mov.w r3, #0
- 8002b98: f04f 0400 mov.w r4, #0
- 8002b9c: 0154 lsls r4, r2, #5
- 8002b9e: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 8002ba2: 014b lsls r3, r1, #5
- 8002ba4: 4619 mov r1, r3
- 8002ba6: 4622 mov r2, r4
- 8002ba8: 1b49 subs r1, r1, r5
- 8002baa: eb62 0206 sbc.w r2, r2, r6
- 8002bae: f04f 0300 mov.w r3, #0
- 8002bb2: f04f 0400 mov.w r4, #0
- 8002bb6: 0194 lsls r4, r2, #6
- 8002bb8: ea44 6491 orr.w r4, r4, r1, lsr #26
- 8002bbc: 018b lsls r3, r1, #6
- 8002bbe: 1a5b subs r3, r3, r1
- 8002bc0: eb64 0402 sbc.w r4, r4, r2
- 8002bc4: f04f 0100 mov.w r1, #0
- 8002bc8: f04f 0200 mov.w r2, #0
- 8002bcc: 00e2 lsls r2, r4, #3
- 8002bce: ea42 7253 orr.w r2, r2, r3, lsr #29
- 8002bd2: 00d9 lsls r1, r3, #3
- 8002bd4: 460b mov r3, r1
- 8002bd6: 4614 mov r4, r2
- 8002bd8: 195b adds r3, r3, r5
- 8002bda: eb44 0406 adc.w r4, r4, r6
- 8002bde: f04f 0100 mov.w r1, #0
- 8002be2: f04f 0200 mov.w r2, #0
- 8002be6: 02a2 lsls r2, r4, #10
- 8002be8: ea42 5293 orr.w r2, r2, r3, lsr #22
- 8002bec: 0299 lsls r1, r3, #10
- 8002bee: 460b mov r3, r1
- 8002bf0: 4614 mov r4, r2
- 8002bf2: 4618 mov r0, r3
- 8002bf4: 4621 mov r1, r4
- 8002bf6: 687b ldr r3, [r7, #4]
- 8002bf8: f04f 0400 mov.w r4, #0
- 8002bfc: 461a mov r2, r3
- 8002bfe: 4623 mov r3, r4
- 8002c00: f7fd fb1a bl 8000238 <__aeabi_uldivmod>
- 8002c04: 4603 mov r3, r0
- 8002c06: 460c mov r4, r1
- 8002c08: 60fb str r3, [r7, #12]
- }
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 8002c0a: 4b0b ldr r3, [pc, #44] ; (8002c38 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002c0c: 685b ldr r3, [r3, #4]
- 8002c0e: 0c1b lsrs r3, r3, #16
- 8002c10: f003 0303 and.w r3, r3, #3
- 8002c14: 3301 adds r3, #1
- 8002c16: 005b lsls r3, r3, #1
- 8002c18: 603b str r3, [r7, #0]
-
- sysclockfreq = pllvco/pllp;
- 8002c1a: 68fa ldr r2, [r7, #12]
- 8002c1c: 683b ldr r3, [r7, #0]
- 8002c1e: fbb2 f3f3 udiv r3, r2, r3
- 8002c22: 60bb str r3, [r7, #8]
- break;
- 8002c24: e002 b.n 8002c2c <HAL_RCC_GetSysClockFreq+0x14c>
- }
- default:
- {
- sysclockfreq = HSI_VALUE;
- 8002c26: 4b05 ldr r3, [pc, #20] ; (8002c3c <HAL_RCC_GetSysClockFreq+0x15c>)
- 8002c28: 60bb str r3, [r7, #8]
- break;
- 8002c2a: bf00 nop
- }
- }
- return sysclockfreq;
- 8002c2c: 68bb ldr r3, [r7, #8]
-}
- 8002c2e: 4618 mov r0, r3
- 8002c30: 3714 adds r7, #20
- 8002c32: 46bd mov sp, r7
- 8002c34: bdf0 pop {r4, r5, r6, r7, pc}
- 8002c36: bf00 nop
- 8002c38: 40023800 .word 0x40023800
- 8002c3c: 00f42400 .word 0x00f42400
- 8002c40: 017d7840 .word 0x017d7840
-
-08002c44 <HAL_RCC_GetHCLKFreq>:
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- 8002c44: b480 push {r7}
- 8002c46: af00 add r7, sp, #0
- return SystemCoreClock;
- 8002c48: 4b03 ldr r3, [pc, #12] ; (8002c58 <HAL_RCC_GetHCLKFreq+0x14>)
- 8002c4a: 681b ldr r3, [r3, #0]
-}
- 8002c4c: 4618 mov r0, r3
- 8002c4e: 46bd mov sp, r7
- 8002c50: f85d 7b04 ldr.w r7, [sp], #4
- 8002c54: 4770 bx lr
- 8002c56: bf00 nop
- 8002c58: 20000004 .word 0x20000004
-
-08002c5c <HAL_RCC_GetPCLK1Freq>:
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- 8002c5c: b580 push {r7, lr}
- 8002c5e: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 8002c60: f7ff fff0 bl 8002c44 <HAL_RCC_GetHCLKFreq>
- 8002c64: 4601 mov r1, r0
- 8002c66: 4b05 ldr r3, [pc, #20] ; (8002c7c <HAL_RCC_GetPCLK1Freq+0x20>)
- 8002c68: 689b ldr r3, [r3, #8]
- 8002c6a: 0a9b lsrs r3, r3, #10
- 8002c6c: f003 0307 and.w r3, r3, #7
- 8002c70: 4a03 ldr r2, [pc, #12] ; (8002c80 <HAL_RCC_GetPCLK1Freq+0x24>)
- 8002c72: 5cd3 ldrb r3, [r2, r3]
- 8002c74: fa21 f303 lsr.w r3, r1, r3
-}
- 8002c78: 4618 mov r0, r3
- 8002c7a: bd80 pop {r7, pc}
- 8002c7c: 40023800 .word 0x40023800
- 8002c80: 08005614 .word 0x08005614
-
-08002c84 <HAL_RCC_GetPCLK2Freq>:
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- 8002c84: b580 push {r7, lr}
- 8002c86: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 8002c88: f7ff ffdc bl 8002c44 <HAL_RCC_GetHCLKFreq>
- 8002c8c: 4601 mov r1, r0
- 8002c8e: 4b05 ldr r3, [pc, #20] ; (8002ca4 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8002c90: 689b ldr r3, [r3, #8]
- 8002c92: 0b5b lsrs r3, r3, #13
- 8002c94: f003 0307 and.w r3, r3, #7
- 8002c98: 4a03 ldr r2, [pc, #12] ; (8002ca8 <HAL_RCC_GetPCLK2Freq+0x24>)
- 8002c9a: 5cd3 ldrb r3, [r2, r3]
- 8002c9c: fa21 f303 lsr.w r3, r1, r3
-}
- 8002ca0: 4618 mov r0, r3
- 8002ca2: bd80 pop {r7, pc}
- 8002ca4: 40023800 .word 0x40023800
- 8002ca8: 08005614 .word 0x08005614
-
-08002cac <HAL_RCCEx_PeriphCLKConfig>:
- * the backup registers) are set to their reset values.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- 8002cac: b580 push {r7, lr}
- 8002cae: b088 sub sp, #32
- 8002cb0: af00 add r7, sp, #0
- 8002cb2: 6078 str r0, [r7, #4]
- uint32_t tickstart = 0;
- 8002cb4: 2300 movs r3, #0
- 8002cb6: 617b str r3, [r7, #20]
- uint32_t tmpreg0 = 0;
- 8002cb8: 2300 movs r3, #0
- 8002cba: 613b str r3, [r7, #16]
- uint32_t tmpreg1 = 0;
- 8002cbc: 2300 movs r3, #0
- 8002cbe: 60fb str r3, [r7, #12]
- uint32_t plli2sused = 0;
- 8002cc0: 2300 movs r3, #0
- 8002cc2: 61fb str r3, [r7, #28]
- uint32_t pllsaiused = 0;
- 8002cc4: 2300 movs r3, #0
- 8002cc6: 61bb str r3, [r7, #24]
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*----------------------------------- I2S configuration ----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 8002cc8: 687b ldr r3, [r7, #4]
- 8002cca: 681b ldr r3, [r3, #0]
- 8002ccc: f003 0301 and.w r3, r3, #1
- 8002cd0: 2b00 cmp r3, #0
- 8002cd2: d012 beq.n 8002cfa <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure I2S Clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 8002cd4: 4b69 ldr r3, [pc, #420] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cd6: 689b ldr r3, [r3, #8]
- 8002cd8: 4a68 ldr r2, [pc, #416] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cda: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
- 8002cde: 6093 str r3, [r2, #8]
- 8002ce0: 4b66 ldr r3, [pc, #408] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ce2: 689a ldr r2, [r3, #8]
- 8002ce4: 687b ldr r3, [r7, #4]
- 8002ce6: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002ce8: 4964 ldr r1, [pc, #400] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cea: 4313 orrs r3, r2
- 8002cec: 608b str r3, [r1, #8]
-
- /* Enable the PLLI2S when it's used as clock source for I2S */
- if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 8002cee: 687b ldr r3, [r7, #4]
- 8002cf0: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002cf2: 2b00 cmp r3, #0
- 8002cf4: d101 bne.n 8002cfa <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- plli2sused = 1;
- 8002cf6: 2301 movs r3, #1
- 8002cf8: 61fb str r3, [r7, #28]
- }
- }
-
- /*------------------------------------ SAI1 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 8002cfa: 687b ldr r3, [r7, #4]
- 8002cfc: 681b ldr r3, [r3, #0]
- 8002cfe: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002d02: 2b00 cmp r3, #0
- 8002d04: d017 beq.n 8002d36 <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
- /* Configure SAI1 Clock source */
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 8002d06: 4b5d ldr r3, [pc, #372] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d08: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002d0c: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002d10: 687b ldr r3, [r7, #4]
- 8002d12: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002d14: 4959 ldr r1, [pc, #356] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d16: 4313 orrs r3, r2
- 8002d18: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8002d1c: 687b ldr r3, [r7, #4]
- 8002d1e: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002d20: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8002d24: d101 bne.n 8002d2a <HAL_RCCEx_PeriphCLKConfig+0x7e>
- {
- plli2sused = 1;
- 8002d26: 2301 movs r3, #1
- 8002d28: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 8002d2a: 687b ldr r3, [r7, #4]
- 8002d2c: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002d2e: 2b00 cmp r3, #0
- 8002d30: d101 bne.n 8002d36 <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- pllsaiused = 1;
- 8002d32: 2301 movs r3, #1
- 8002d34: 61bb str r3, [r7, #24]
- }
- }
-
- /*------------------------------------ SAI2 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 8002d36: 687b ldr r3, [r7, #4]
- 8002d38: 681b ldr r3, [r3, #0]
- 8002d3a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8002d3e: 2b00 cmp r3, #0
- 8002d40: d017 beq.n 8002d72 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
- /* Configure SAI2 Clock source */
- __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 8002d42: 4b4e ldr r3, [pc, #312] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d44: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002d48: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002d4c: 687b ldr r3, [r7, #4]
- 8002d4e: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d50: 494a ldr r1, [pc, #296] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d52: 4313 orrs r3, r2
- 8002d54: f8c1 308c str.w r3, [r1, #140] ; 0x8c
-
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 8002d58: 687b ldr r3, [r7, #4]
- 8002d5a: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d5c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002d60: d101 bne.n 8002d66 <HAL_RCCEx_PeriphCLKConfig+0xba>
- {
- plli2sused = 1;
- 8002d62: 2301 movs r3, #1
- 8002d64: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 8002d66: 687b ldr r3, [r7, #4]
- 8002d68: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d6a: 2b00 cmp r3, #0
- 8002d6c: d101 bne.n 8002d72 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- pllsaiused = 1;
- 8002d6e: 2301 movs r3, #1
- 8002d70: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8002d72: 687b ldr r3, [r7, #4]
- 8002d74: 681b ldr r3, [r3, #0]
- 8002d76: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8002d7a: 2b00 cmp r3, #0
- 8002d7c: d001 beq.n 8002d82 <HAL_RCCEx_PeriphCLKConfig+0xd6>
- {
- plli2sused = 1;
- 8002d7e: 2301 movs r3, #1
- 8002d80: 61fb str r3, [r7, #28]
- }
-
- /*------------------------------------ RTC configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 8002d82: 687b ldr r3, [r7, #4]
- 8002d84: 681b ldr r3, [r3, #0]
- 8002d86: f003 0320 and.w r3, r3, #32
- 8002d8a: 2b00 cmp r3, #0
- 8002d8c: f000 808b beq.w 8002ea6 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
- {
- /* Check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 8002d90: 4b3a ldr r3, [pc, #232] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d92: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002d94: 4a39 ldr r2, [pc, #228] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d96: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8002d9a: 6413 str r3, [r2, #64] ; 0x40
- 8002d9c: 4b37 ldr r3, [pc, #220] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d9e: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002da0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002da4: 60bb str r3, [r7, #8]
- 8002da6: 68bb ldr r3, [r7, #8]
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 8002da8: 4b35 ldr r3, [pc, #212] ; (8002e80 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002daa: 681b ldr r3, [r3, #0]
- 8002dac: 4a34 ldr r2, [pc, #208] ; (8002e80 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002dae: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8002db2: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002db4: f7ff f81e bl 8001df4 <HAL_GetTick>
- 8002db8: 6178 str r0, [r7, #20]
-
- /* Wait for Backup domain Write protection disable */
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002dba: e008 b.n 8002dce <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8002dbc: f7ff f81a bl 8001df4 <HAL_GetTick>
- 8002dc0: 4602 mov r2, r0
- 8002dc2: 697b ldr r3, [r7, #20]
- 8002dc4: 1ad3 subs r3, r2, r3
- 8002dc6: 2b64 cmp r3, #100 ; 0x64
- 8002dc8: d901 bls.n 8002dce <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- return HAL_TIMEOUT;
- 8002dca: 2303 movs r3, #3
- 8002dcc: e38d b.n 80034ea <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002dce: 4b2c ldr r3, [pc, #176] ; (8002e80 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002dd0: 681b ldr r3, [r3, #0]
- 8002dd2: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002dd6: 2b00 cmp r3, #0
- 8002dd8: d0f0 beq.n 8002dbc <HAL_RCCEx_PeriphCLKConfig+0x110>
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8002dda: 4b28 ldr r3, [pc, #160] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ddc: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002dde: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002de2: 613b str r3, [r7, #16]
-
- if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8002de4: 693b ldr r3, [r7, #16]
- 8002de6: 2b00 cmp r3, #0
- 8002de8: d035 beq.n 8002e56 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8002dea: 687b ldr r3, [r7, #4]
- 8002dec: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002dee: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002df2: 693a ldr r2, [r7, #16]
- 8002df4: 429a cmp r2, r3
- 8002df6: d02e beq.n 8002e56 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8002df8: 4b20 ldr r3, [pc, #128] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002dfa: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002dfc: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8002e00: 613b str r3, [r7, #16]
-
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- 8002e02: 4b1e ldr r3, [pc, #120] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e04: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002e06: 4a1d ldr r2, [pc, #116] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e08: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002e0c: 6713 str r3, [r2, #112] ; 0x70
- __HAL_RCC_BACKUPRESET_RELEASE();
- 8002e0e: 4b1b ldr r3, [pc, #108] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e10: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002e12: 4a1a ldr r2, [pc, #104] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e14: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002e18: 6713 str r3, [r2, #112] ; 0x70
-
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg0;
- 8002e1a: 4a18 ldr r2, [pc, #96] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e1c: 693b ldr r3, [r7, #16]
- 8002e1e: 6713 str r3, [r2, #112] ; 0x70
-
- /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
- if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8002e20: 4b16 ldr r3, [pc, #88] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e22: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002e24: f003 0301 and.w r3, r3, #1
- 8002e28: 2b01 cmp r3, #1
- 8002e2a: d114 bne.n 8002e56 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002e2c: f7fe ffe2 bl 8001df4 <HAL_GetTick>
- 8002e30: 6178 str r0, [r7, #20]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002e32: e00a b.n 8002e4a <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002e34: f7fe ffde bl 8001df4 <HAL_GetTick>
- 8002e38: 4602 mov r2, r0
- 8002e3a: 697b ldr r3, [r7, #20]
- 8002e3c: 1ad3 subs r3, r2, r3
- 8002e3e: f241 3288 movw r2, #5000 ; 0x1388
- 8002e42: 4293 cmp r3, r2
- 8002e44: d901 bls.n 8002e4a <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- return HAL_TIMEOUT;
- 8002e46: 2303 movs r3, #3
- 8002e48: e34f b.n 80034ea <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002e4a: 4b0c ldr r3, [pc, #48] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e4c: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002e4e: f003 0302 and.w r3, r3, #2
- 8002e52: 2b00 cmp r3, #0
- 8002e54: d0ee beq.n 8002e34 <HAL_RCCEx_PeriphCLKConfig+0x188>
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8002e56: 687b ldr r3, [r7, #4]
- 8002e58: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002e5a: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002e5e: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8002e62: d111 bne.n 8002e88 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8002e64: 4b05 ldr r3, [pc, #20] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e66: 689b ldr r3, [r3, #8]
- 8002e68: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
- 8002e6c: 687b ldr r3, [r7, #4]
- 8002e6e: 6b19 ldr r1, [r3, #48] ; 0x30
- 8002e70: 4b04 ldr r3, [pc, #16] ; (8002e84 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8002e72: 400b ands r3, r1
- 8002e74: 4901 ldr r1, [pc, #4] ; (8002e7c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002e76: 4313 orrs r3, r2
- 8002e78: 608b str r3, [r1, #8]
- 8002e7a: e00b b.n 8002e94 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8002e7c: 40023800 .word 0x40023800
- 8002e80: 40007000 .word 0x40007000
- 8002e84: 0ffffcff .word 0x0ffffcff
- 8002e88: 4bb3 ldr r3, [pc, #716] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e8a: 689b ldr r3, [r3, #8]
- 8002e8c: 4ab2 ldr r2, [pc, #712] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e8e: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
- 8002e92: 6093 str r3, [r2, #8]
- 8002e94: 4bb0 ldr r3, [pc, #704] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e96: 6f1a ldr r2, [r3, #112] ; 0x70
- 8002e98: 687b ldr r3, [r7, #4]
- 8002e9a: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002e9c: f3c3 030b ubfx r3, r3, #0, #12
- 8002ea0: 49ad ldr r1, [pc, #692] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ea2: 4313 orrs r3, r2
- 8002ea4: 670b str r3, [r1, #112] ; 0x70
- }
-
- /*------------------------------------ TIM configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 8002ea6: 687b ldr r3, [r7, #4]
- 8002ea8: 681b ldr r3, [r3, #0]
- 8002eaa: f003 0310 and.w r3, r3, #16
- 8002eae: 2b00 cmp r3, #0
- 8002eb0: d010 beq.n 8002ed4 <HAL_RCCEx_PeriphCLKConfig+0x228>
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
-
- /* Configure Timer Prescaler */
- __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 8002eb2: 4ba9 ldr r3, [pc, #676] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002eb4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002eb8: 4aa7 ldr r2, [pc, #668] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002eba: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002ebe: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 8002ec2: 4ba5 ldr r3, [pc, #660] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ec4: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
- 8002ec8: 687b ldr r3, [r7, #4]
- 8002eca: 6b9b ldr r3, [r3, #56] ; 0x38
- 8002ecc: 49a2 ldr r1, [pc, #648] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ece: 4313 orrs r3, r2
- 8002ed0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*-------------------------------------- I2C1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 8002ed4: 687b ldr r3, [r7, #4]
- 8002ed6: 681b ldr r3, [r3, #0]
- 8002ed8: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8002edc: 2b00 cmp r3, #0
- 8002ede: d00a beq.n 8002ef6 <HAL_RCCEx_PeriphCLKConfig+0x24a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8002ee0: 4b9d ldr r3, [pc, #628] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ee2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ee6: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8002eea: 687b ldr r3, [r7, #4]
- 8002eec: 6e5b ldr r3, [r3, #100] ; 0x64
- 8002eee: 499a ldr r1, [pc, #616] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ef0: 4313 orrs r3, r2
- 8002ef2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 8002ef6: 687b ldr r3, [r7, #4]
- 8002ef8: 681b ldr r3, [r3, #0]
- 8002efa: f403 4300 and.w r3, r3, #32768 ; 0x8000
- 8002efe: 2b00 cmp r3, #0
- 8002f00: d00a beq.n 8002f18 <HAL_RCCEx_PeriphCLKConfig+0x26c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8002f02: 4b95 ldr r3, [pc, #596] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f04: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f08: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
- 8002f0c: 687b ldr r3, [r7, #4]
- 8002f0e: 6e9b ldr r3, [r3, #104] ; 0x68
- 8002f10: 4991 ldr r1, [pc, #580] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f12: 4313 orrs r3, r2
- 8002f14: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8002f18: 687b ldr r3, [r7, #4]
- 8002f1a: 681b ldr r3, [r3, #0]
- 8002f1c: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8002f20: 2b00 cmp r3, #0
- 8002f22: d00a beq.n 8002f3a <HAL_RCCEx_PeriphCLKConfig+0x28e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8002f24: 4b8c ldr r3, [pc, #560] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f26: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f2a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002f2e: 687b ldr r3, [r7, #4]
- 8002f30: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002f32: 4989 ldr r1, [pc, #548] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f34: 4313 orrs r3, r2
- 8002f36: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8002f3a: 687b ldr r3, [r7, #4]
- 8002f3c: 681b ldr r3, [r3, #0]
- 8002f3e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002f42: 2b00 cmp r3, #0
- 8002f44: d00a beq.n 8002f5c <HAL_RCCEx_PeriphCLKConfig+0x2b0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- /* Configure the I2C4 clock source */
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8002f46: 4b84 ldr r3, [pc, #528] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f48: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f4c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002f50: 687b ldr r3, [r7, #4]
- 8002f52: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002f54: 4980 ldr r1, [pc, #512] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f56: 4313 orrs r3, r2
- 8002f58: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8002f5c: 687b ldr r3, [r7, #4]
- 8002f5e: 681b ldr r3, [r3, #0]
- 8002f60: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002f64: 2b00 cmp r3, #0
- 8002f66: d00a beq.n 8002f7e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8002f68: 4b7b ldr r3, [pc, #492] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f6a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f6e: f023 0203 bic.w r2, r3, #3
- 8002f72: 687b ldr r3, [r7, #4]
- 8002f74: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002f76: 4978 ldr r1, [pc, #480] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f78: 4313 orrs r3, r2
- 8002f7a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8002f7e: 687b ldr r3, [r7, #4]
- 8002f80: 681b ldr r3, [r3, #0]
- 8002f82: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002f86: 2b00 cmp r3, #0
- 8002f88: d00a beq.n 8002fa0 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8002f8a: 4b73 ldr r3, [pc, #460] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f8c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f90: f023 020c bic.w r2, r3, #12
- 8002f94: 687b ldr r3, [r7, #4]
- 8002f96: 6c9b ldr r3, [r3, #72] ; 0x48
- 8002f98: 496f ldr r1, [pc, #444] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f9a: 4313 orrs r3, r2
- 8002f9c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8002fa0: 687b ldr r3, [r7, #4]
- 8002fa2: 681b ldr r3, [r3, #0]
- 8002fa4: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002fa8: 2b00 cmp r3, #0
- 8002faa: d00a beq.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x316>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8002fac: 4b6a ldr r3, [pc, #424] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fae: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fb2: f023 0230 bic.w r2, r3, #48 ; 0x30
- 8002fb6: 687b ldr r3, [r7, #4]
- 8002fb8: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8002fba: 4967 ldr r1, [pc, #412] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fbc: 4313 orrs r3, r2
- 8002fbe: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8002fc2: 687b ldr r3, [r7, #4]
- 8002fc4: 681b ldr r3, [r3, #0]
- 8002fc6: f403 7300 and.w r3, r3, #512 ; 0x200
- 8002fca: 2b00 cmp r3, #0
- 8002fcc: d00a beq.n 8002fe4 <HAL_RCCEx_PeriphCLKConfig+0x338>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8002fce: 4b62 ldr r3, [pc, #392] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fd0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fd4: f023 02c0 bic.w r2, r3, #192 ; 0xc0
- 8002fd8: 687b ldr r3, [r7, #4]
- 8002fda: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002fdc: 495e ldr r1, [pc, #376] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fde: 4313 orrs r3, r2
- 8002fe0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART5 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8002fe4: 687b ldr r3, [r7, #4]
- 8002fe6: 681b ldr r3, [r3, #0]
- 8002fe8: f403 6380 and.w r3, r3, #1024 ; 0x400
- 8002fec: 2b00 cmp r3, #0
- 8002fee: d00a beq.n 8003006 <HAL_RCCEx_PeriphCLKConfig+0x35a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8002ff0: 4b59 ldr r3, [pc, #356] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ff2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ff6: f423 7240 bic.w r2, r3, #768 ; 0x300
- 8002ffa: 687b ldr r3, [r7, #4]
- 8002ffc: 6d5b ldr r3, [r3, #84] ; 0x54
- 8002ffe: 4956 ldr r1, [pc, #344] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003000: 4313 orrs r3, r2
- 8003002: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART6 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8003006: 687b ldr r3, [r7, #4]
- 8003008: 681b ldr r3, [r3, #0]
- 800300a: f403 6300 and.w r3, r3, #2048 ; 0x800
- 800300e: 2b00 cmp r3, #0
- 8003010: d00a beq.n 8003028 <HAL_RCCEx_PeriphCLKConfig+0x37c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
-
- /* Configure the USART6 clock source */
- __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8003012: 4b51 ldr r3, [pc, #324] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003014: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003018: f423 6240 bic.w r2, r3, #3072 ; 0xc00
- 800301c: 687b ldr r3, [r7, #4]
- 800301e: 6d9b ldr r3, [r3, #88] ; 0x58
- 8003020: 494d ldr r1, [pc, #308] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003022: 4313 orrs r3, r2
- 8003024: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART7 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8003028: 687b ldr r3, [r7, #4]
- 800302a: 681b ldr r3, [r3, #0]
- 800302c: f403 5380 and.w r3, r3, #4096 ; 0x1000
- 8003030: 2b00 cmp r3, #0
- 8003032: d00a beq.n 800304a <HAL_RCCEx_PeriphCLKConfig+0x39e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
-
- /* Configure the UART7 clock source */
- __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8003034: 4b48 ldr r3, [pc, #288] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003036: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800303a: f423 5240 bic.w r2, r3, #12288 ; 0x3000
- 800303e: 687b ldr r3, [r7, #4]
- 8003040: 6ddb ldr r3, [r3, #92] ; 0x5c
- 8003042: 4945 ldr r1, [pc, #276] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003044: 4313 orrs r3, r2
- 8003046: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART8 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 800304a: 687b ldr r3, [r7, #4]
- 800304c: 681b ldr r3, [r3, #0]
- 800304e: f403 5300 and.w r3, r3, #8192 ; 0x2000
- 8003052: 2b00 cmp r3, #0
- 8003054: d00a beq.n 800306c <HAL_RCCEx_PeriphCLKConfig+0x3c0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
-
- /* Configure the UART8 clock source */
- __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 8003056: 4b40 ldr r3, [pc, #256] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003058: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800305c: f423 4240 bic.w r2, r3, #49152 ; 0xc000
- 8003060: 687b ldr r3, [r7, #4]
- 8003062: 6e1b ldr r3, [r3, #96] ; 0x60
- 8003064: 493c ldr r1, [pc, #240] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003066: 4313 orrs r3, r2
- 8003068: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*--------------------------------------- CEC Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 800306c: 687b ldr r3, [r7, #4]
- 800306e: 681b ldr r3, [r3, #0]
- 8003070: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8003074: 2b00 cmp r3, #0
- 8003076: d00a beq.n 800308e <HAL_RCCEx_PeriphCLKConfig+0x3e2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 8003078: 4b37 ldr r3, [pc, #220] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800307a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800307e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8003082: 687b ldr r3, [r7, #4]
- 8003084: 6f9b ldr r3, [r3, #120] ; 0x78
- 8003086: 4934 ldr r1, [pc, #208] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003088: 4313 orrs r3, r2
- 800308a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- CK48 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 800308e: 687b ldr r3, [r7, #4]
- 8003090: 681b ldr r3, [r3, #0]
- 8003092: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8003096: 2b00 cmp r3, #0
- 8003098: d011 beq.n 80030be <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
-
- /* Configure the CLK48 source */
- __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 800309a: 4b2f ldr r3, [pc, #188] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800309c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80030a0: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
- 80030a4: 687b ldr r3, [r7, #4]
- 80030a6: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80030a8: 492b ldr r1, [pc, #172] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030aa: 4313 orrs r3, r2
- 80030ac: f8c1 3090 str.w r3, [r1, #144] ; 0x90
-
- /* Enable the PLLSAI when it's used as clock source for CK48 */
- if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 80030b0: 687b ldr r3, [r7, #4]
- 80030b2: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80030b4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 80030b8: d101 bne.n 80030be <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- pllsaiused = 1;
- 80030ba: 2301 movs r3, #1
- 80030bc: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- LTDC Configuration -----------------------------------*/
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 80030be: 687b ldr r3, [r7, #4]
- 80030c0: 681b ldr r3, [r3, #0]
- 80030c2: f003 0308 and.w r3, r3, #8
- 80030c6: 2b00 cmp r3, #0
- 80030c8: d001 beq.n 80030ce <HAL_RCCEx_PeriphCLKConfig+0x422>
- {
- pllsaiused = 1;
- 80030ca: 2301 movs r3, #1
- 80030cc: 61bb str r3, [r7, #24]
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 80030ce: 687b ldr r3, [r7, #4]
- 80030d0: 681b ldr r3, [r3, #0]
- 80030d2: f403 2380 and.w r3, r3, #262144 ; 0x40000
- 80030d6: 2b00 cmp r3, #0
- 80030d8: d00a beq.n 80030f0 <HAL_RCCEx_PeriphCLKConfig+0x444>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
-
- /* Configure the LTPIM1 clock source */
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 80030da: 4b1f ldr r3, [pc, #124] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030dc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80030e0: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
- 80030e4: 687b ldr r3, [r7, #4]
- 80030e6: 6f5b ldr r3, [r3, #116] ; 0x74
- 80030e8: 491b ldr r1, [pc, #108] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030ea: 4313 orrs r3, r2
- 80030ec: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 80030f0: 687b ldr r3, [r7, #4]
- 80030f2: 681b ldr r3, [r3, #0]
- 80030f4: f403 0300 and.w r3, r3, #8388608 ; 0x800000
- 80030f8: 2b00 cmp r3, #0
- 80030fa: d00b beq.n 8003114 <HAL_RCCEx_PeriphCLKConfig+0x468>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
-
- /* Configure the SDMMC1 clock source */
- __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 80030fc: 4b16 ldr r3, [pc, #88] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80030fe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003102: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
- 8003106: 687b ldr r3, [r7, #4]
- 8003108: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
- 800310c: 4912 ldr r1, [pc, #72] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800310e: 4313 orrs r3, r2
- 8003110: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
- /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 8003114: 687b ldr r3, [r7, #4]
- 8003116: 681b ldr r3, [r3, #0]
- 8003118: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
- 800311c: 2b00 cmp r3, #0
- 800311e: d00b beq.n 8003138 <HAL_RCCEx_PeriphCLKConfig+0x48c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
-
- /* Configure the SDMMC2 clock source */
- __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 8003120: 4b0d ldr r3, [pc, #52] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003122: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003126: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
- 800312a: 687b ldr r3, [r7, #4]
- 800312c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003130: 4909 ldr r1, [pc, #36] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003132: 4313 orrs r3, r2
- 8003134: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 8003138: 687b ldr r3, [r7, #4]
- 800313a: 681b ldr r3, [r3, #0]
- 800313c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8003140: 2b00 cmp r3, #0
- 8003142: d00f beq.n 8003164 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
- /* Configure the DFSDM1 interface clock source */
- __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8003144: 4b04 ldr r3, [pc, #16] ; (8003158 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003146: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800314a: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
- 800314e: 687b ldr r3, [r7, #4]
- 8003150: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003154: e002 b.n 800315c <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 8003156: bf00 nop
- 8003158: 40023800 .word 0x40023800
- 800315c: 4985 ldr r1, [pc, #532] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800315e: 4313 orrs r3, r2
- 8003160: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8003164: 687b ldr r3, [r7, #4]
- 8003166: 681b ldr r3, [r3, #0]
- 8003168: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 800316c: 2b00 cmp r3, #0
- 800316e: d00b beq.n 8003188 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
- /* Configure the DFSDM interface clock source */
- __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 8003170: 4b80 ldr r3, [pc, #512] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003172: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003176: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 800317a: 687b ldr r3, [r7, #4]
- 800317c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003180: 497c ldr r1, [pc, #496] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003182: 4313 orrs r3, r2
- 8003184: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
- /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
- /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
- if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 8003188: 69fb ldr r3, [r7, #28]
- 800318a: 2b01 cmp r3, #1
- 800318c: d005 beq.n 800319a <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 800318e: 687b ldr r3, [r7, #4]
- 8003190: 681b ldr r3, [r3, #0]
- 8003192: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 8003196: f040 80d6 bne.w 8003346 <HAL_RCCEx_PeriphCLKConfig+0x69a>
- {
- /* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
- 800319a: 4b76 ldr r3, [pc, #472] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800319c: 681b ldr r3, [r3, #0]
- 800319e: 4a75 ldr r2, [pc, #468] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031a0: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
- 80031a4: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80031a6: f7fe fe25 bl 8001df4 <HAL_GetTick>
- 80031aa: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 80031ac: e008 b.n 80031c0 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 80031ae: f7fe fe21 bl 8001df4 <HAL_GetTick>
- 80031b2: 4602 mov r2, r0
- 80031b4: 697b ldr r3, [r7, #20]
- 80031b6: 1ad3 subs r3, r2, r3
- 80031b8: 2b64 cmp r3, #100 ; 0x64
- 80031ba: d901 bls.n 80031c0 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 80031bc: 2303 movs r3, #3
- 80031be: e194 b.n 80034ea <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 80031c0: 4b6c ldr r3, [pc, #432] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031c2: 681b ldr r3, [r3, #0]
- 80031c4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 80031c8: 2b00 cmp r3, #0
- 80031ca: d1f0 bne.n 80031ae <HAL_RCCEx_PeriphCLKConfig+0x502>
-
- /* check for common PLLI2S Parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
- /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 80031cc: 687b ldr r3, [r7, #4]
- 80031ce: 681b ldr r3, [r3, #0]
- 80031d0: f003 0301 and.w r3, r3, #1
- 80031d4: 2b00 cmp r3, #0
- 80031d6: d021 beq.n 800321c <HAL_RCCEx_PeriphCLKConfig+0x570>
- 80031d8: 687b ldr r3, [r7, #4]
- 80031da: 6b5b ldr r3, [r3, #52] ; 0x34
- 80031dc: 2b00 cmp r3, #0
- 80031de: d11d bne.n 800321c <HAL_RCCEx_PeriphCLKConfig+0x570>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
- /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 80031e0: 4b64 ldr r3, [pc, #400] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031e2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80031e6: 0c1b lsrs r3, r3, #16
- 80031e8: f003 0303 and.w r3, r3, #3
- 80031ec: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 80031ee: 4b61 ldr r3, [pc, #388] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031f0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80031f4: 0e1b lsrs r3, r3, #24
- 80031f6: f003 030f and.w r3, r3, #15
- 80031fa: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 80031fc: 687b ldr r3, [r7, #4]
- 80031fe: 685b ldr r3, [r3, #4]
- 8003200: 019a lsls r2, r3, #6
- 8003202: 693b ldr r3, [r7, #16]
- 8003204: 041b lsls r3, r3, #16
- 8003206: 431a orrs r2, r3
- 8003208: 68fb ldr r3, [r7, #12]
- 800320a: 061b lsls r3, r3, #24
- 800320c: 431a orrs r2, r3
- 800320e: 687b ldr r3, [r7, #4]
- 8003210: 689b ldr r3, [r3, #8]
- 8003212: 071b lsls r3, r3, #28
- 8003214: 4957 ldr r1, [pc, #348] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003216: 4313 orrs r3, r2
- 8003218: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 800321c: 687b ldr r3, [r7, #4]
- 800321e: 681b ldr r3, [r3, #0]
- 8003220: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8003224: 2b00 cmp r3, #0
- 8003226: d004 beq.n 8003232 <HAL_RCCEx_PeriphCLKConfig+0x586>
- 8003228: 687b ldr r3, [r7, #4]
- 800322a: 6bdb ldr r3, [r3, #60] ; 0x3c
- 800322c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8003230: d00a beq.n 8003248 <HAL_RCCEx_PeriphCLKConfig+0x59c>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8003232: 687b ldr r3, [r7, #4]
- 8003234: 681b ldr r3, [r3, #0]
- 8003236: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 800323a: 2b00 cmp r3, #0
- 800323c: d02e beq.n 800329c <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 800323e: 687b ldr r3, [r7, #4]
- 8003240: 6c1b ldr r3, [r3, #64] ; 0x40
- 8003242: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8003246: d129 bne.n 800329c <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
- /* Check for PLLI2S/DIVQ parameters */
- assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
- /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8003248: 4b4a ldr r3, [pc, #296] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800324a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 800324e: 0c1b lsrs r3, r3, #16
- 8003250: f003 0303 and.w r3, r3, #3
- 8003254: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8003256: 4b47 ldr r3, [pc, #284] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003258: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 800325c: 0f1b lsrs r3, r3, #28
- 800325e: f003 0307 and.w r3, r3, #7
- 8003262: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
- /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
- /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8003264: 687b ldr r3, [r7, #4]
- 8003266: 685b ldr r3, [r3, #4]
- 8003268: 019a lsls r2, r3, #6
- 800326a: 693b ldr r3, [r7, #16]
- 800326c: 041b lsls r3, r3, #16
- 800326e: 431a orrs r2, r3
- 8003270: 687b ldr r3, [r7, #4]
- 8003272: 68db ldr r3, [r3, #12]
- 8003274: 061b lsls r3, r3, #24
- 8003276: 431a orrs r2, r3
- 8003278: 68fb ldr r3, [r7, #12]
- 800327a: 071b lsls r3, r3, #28
- 800327c: 493d ldr r1, [pc, #244] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800327e: 4313 orrs r3, r2
- 8003280: f8c1 3084 str.w r3, [r1, #132] ; 0x84
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8003284: 4b3b ldr r3, [pc, #236] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003286: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800328a: f023 021f bic.w r2, r3, #31
- 800328e: 687b ldr r3, [r7, #4]
- 8003290: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003292: 3b01 subs r3, #1
- 8003294: 4937 ldr r1, [pc, #220] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003296: 4313 orrs r3, r2
- 8003298: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 800329c: 687b ldr r3, [r7, #4]
- 800329e: 681b ldr r3, [r3, #0]
- 80032a0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 80032a4: 2b00 cmp r3, #0
- 80032a6: d01d beq.n 80032e4 <HAL_RCCEx_PeriphCLKConfig+0x638>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-
- /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 80032a8: 4b32 ldr r3, [pc, #200] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80032aa: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80032ae: 0e1b lsrs r3, r3, #24
- 80032b0: f003 030f and.w r3, r3, #15
- 80032b4: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 80032b6: 4b2f ldr r3, [pc, #188] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80032b8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80032bc: 0f1b lsrs r3, r3, #28
- 80032be: f003 0307 and.w r3, r3, #7
- 80032c2: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 80032c4: 687b ldr r3, [r7, #4]
- 80032c6: 685b ldr r3, [r3, #4]
- 80032c8: 019a lsls r2, r3, #6
- 80032ca: 687b ldr r3, [r7, #4]
- 80032cc: 691b ldr r3, [r3, #16]
- 80032ce: 041b lsls r3, r3, #16
- 80032d0: 431a orrs r2, r3
- 80032d2: 693b ldr r3, [r7, #16]
- 80032d4: 061b lsls r3, r3, #24
- 80032d6: 431a orrs r2, r3
- 80032d8: 68fb ldr r3, [r7, #12]
- 80032da: 071b lsls r3, r3, #28
- 80032dc: 4925 ldr r1, [pc, #148] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80032de: 4313 orrs r3, r2
- 80032e0: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is just selected -----------------*/
- if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 80032e4: 687b ldr r3, [r7, #4]
- 80032e6: 681b ldr r3, [r3, #0]
- 80032e8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80032ec: 2b00 cmp r3, #0
- 80032ee: d011 beq.n 8003314 <HAL_RCCEx_PeriphCLKConfig+0x668>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
- /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 80032f0: 687b ldr r3, [r7, #4]
- 80032f2: 685b ldr r3, [r3, #4]
- 80032f4: 019a lsls r2, r3, #6
- 80032f6: 687b ldr r3, [r7, #4]
- 80032f8: 691b ldr r3, [r3, #16]
- 80032fa: 041b lsls r3, r3, #16
- 80032fc: 431a orrs r2, r3
- 80032fe: 687b ldr r3, [r7, #4]
- 8003300: 68db ldr r3, [r3, #12]
- 8003302: 061b lsls r3, r3, #24
- 8003304: 431a orrs r2, r3
- 8003306: 687b ldr r3, [r7, #4]
- 8003308: 689b ldr r3, [r3, #8]
- 800330a: 071b lsls r3, r3, #28
- 800330c: 4919 ldr r1, [pc, #100] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800330e: 4313 orrs r3, r2
- 8003310: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /* Enable the PLLI2S */
- __HAL_RCC_PLLI2S_ENABLE();
- 8003314: 4b17 ldr r3, [pc, #92] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003316: 681b ldr r3, [r3, #0]
- 8003318: 4a16 ldr r2, [pc, #88] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800331a: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
- 800331e: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8003320: f7fe fd68 bl 8001df4 <HAL_GetTick>
- 8003324: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 8003326: e008 b.n 800333a <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8003328: f7fe fd64 bl 8001df4 <HAL_GetTick>
- 800332c: 4602 mov r2, r0
- 800332e: 697b ldr r3, [r7, #20]
- 8003330: 1ad3 subs r3, r2, r3
- 8003332: 2b64 cmp r3, #100 ; 0x64
- 8003334: d901 bls.n 800333a <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003336: 2303 movs r3, #3
- 8003338: e0d7 b.n 80034ea <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 800333a: 4b0e ldr r3, [pc, #56] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800333c: 681b ldr r3, [r3, #0]
- 800333e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8003342: 2b00 cmp r3, #0
- 8003344: d0f0 beq.n 8003328 <HAL_RCCEx_PeriphCLKConfig+0x67c>
- }
- }
-
- /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
- /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
- if(pllsaiused == 1)
- 8003346: 69bb ldr r3, [r7, #24]
- 8003348: 2b01 cmp r3, #1
- 800334a: f040 80cd bne.w 80034e8 <HAL_RCCEx_PeriphCLKConfig+0x83c>
- {
- /* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
- 800334e: 4b09 ldr r3, [pc, #36] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003350: 681b ldr r3, [r3, #0]
- 8003352: 4a08 ldr r2, [pc, #32] ; (8003374 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003354: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8003358: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800335a: f7fe fd4b bl 8001df4 <HAL_GetTick>
- 800335e: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is disabled */
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8003360: e00a b.n 8003378 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8003362: f7fe fd47 bl 8001df4 <HAL_GetTick>
- 8003366: 4602 mov r2, r0
- 8003368: 697b ldr r3, [r7, #20]
- 800336a: 1ad3 subs r3, r2, r3
- 800336c: 2b64 cmp r3, #100 ; 0x64
- 800336e: d903 bls.n 8003378 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003370: 2303 movs r3, #3
- 8003372: e0ba b.n 80034ea <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 8003374: 40023800 .word 0x40023800
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8003378: 4b5e ldr r3, [pc, #376] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800337a: 681b ldr r3, [r3, #0]
- 800337c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8003380: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8003384: d0ed beq.n 8003362 <HAL_RCCEx_PeriphCLKConfig+0x6b6>
-
- /* Check the PLLSAI division factors */
- assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
- /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8003386: 687b ldr r3, [r7, #4]
- 8003388: 681b ldr r3, [r3, #0]
- 800338a: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 800338e: 2b00 cmp r3, #0
- 8003390: d003 beq.n 800339a <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 8003392: 687b ldr r3, [r7, #4]
- 8003394: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8003396: 2b00 cmp r3, #0
- 8003398: d009 beq.n 80033ae <HAL_RCCEx_PeriphCLKConfig+0x702>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 800339a: 687b ldr r3, [r7, #4]
- 800339c: 681b ldr r3, [r3, #0]
- 800339e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 80033a2: 2b00 cmp r3, #0
- 80033a4: d02e beq.n 8003404 <HAL_RCCEx_PeriphCLKConfig+0x758>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 80033a6: 687b ldr r3, [r7, #4]
- 80033a8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80033aa: 2b00 cmp r3, #0
- 80033ac: d12a bne.n 8003404 <HAL_RCCEx_PeriphCLKConfig+0x758>
- assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
- /* check for PLLSAI/DIVQ Parameter */
- assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
- /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 80033ae: 4b51 ldr r3, [pc, #324] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033b0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80033b4: 0c1b lsrs r3, r3, #16
- 80033b6: f003 0303 and.w r3, r3, #3
- 80033ba: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 80033bc: 4b4d ldr r3, [pc, #308] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033be: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80033c2: 0f1b lsrs r3, r3, #28
- 80033c4: f003 0307 and.w r3, r3, #7
- 80033c8: 60fb str r3, [r7, #12]
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 80033ca: 687b ldr r3, [r7, #4]
- 80033cc: 695b ldr r3, [r3, #20]
- 80033ce: 019a lsls r2, r3, #6
- 80033d0: 693b ldr r3, [r7, #16]
- 80033d2: 041b lsls r3, r3, #16
- 80033d4: 431a orrs r2, r3
- 80033d6: 687b ldr r3, [r7, #4]
- 80033d8: 699b ldr r3, [r3, #24]
- 80033da: 061b lsls r3, r3, #24
- 80033dc: 431a orrs r2, r3
- 80033de: 68fb ldr r3, [r7, #12]
- 80033e0: 071b lsls r3, r3, #28
- 80033e2: 4944 ldr r1, [pc, #272] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033e4: 4313 orrs r3, r2
- 80033e6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 80033ea: 4b42 ldr r3, [pc, #264] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033ec: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80033f0: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
- 80033f4: 687b ldr r3, [r7, #4]
- 80033f6: 6a9b ldr r3, [r3, #40] ; 0x28
- 80033f8: 3b01 subs r3, #1
- 80033fa: 021b lsls r3, r3, #8
- 80033fc: 493d ldr r1, [pc, #244] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033fe: 4313 orrs r3, r2
- 8003400: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
- /* In Case of PLLI2S is selected as source clock for CK48 */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 8003404: 687b ldr r3, [r7, #4]
- 8003406: 681b ldr r3, [r3, #0]
- 8003408: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 800340c: 2b00 cmp r3, #0
- 800340e: d022 beq.n 8003456 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 8003410: 687b ldr r3, [r7, #4]
- 8003412: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8003414: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8003418: d11d bne.n 8003456 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
- /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 800341a: 4b36 ldr r3, [pc, #216] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800341c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003420: 0e1b lsrs r3, r3, #24
- 8003422: f003 030f and.w r3, r3, #15
- 8003426: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8003428: 4b32 ldr r3, [pc, #200] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800342a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800342e: 0f1b lsrs r3, r3, #28
- 8003430: f003 0307 and.w r3, r3, #7
- 8003434: 60fb str r3, [r7, #12]
-
- /* Configure the PLLSAI division factors */
- /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
- /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 8003436: 687b ldr r3, [r7, #4]
- 8003438: 695b ldr r3, [r3, #20]
- 800343a: 019a lsls r2, r3, #6
- 800343c: 687b ldr r3, [r7, #4]
- 800343e: 6a1b ldr r3, [r3, #32]
- 8003440: 041b lsls r3, r3, #16
- 8003442: 431a orrs r2, r3
- 8003444: 693b ldr r3, [r7, #16]
- 8003446: 061b lsls r3, r3, #24
- 8003448: 431a orrs r2, r3
- 800344a: 68fb ldr r3, [r7, #12]
- 800344c: 071b lsls r3, r3, #28
- 800344e: 4929 ldr r1, [pc, #164] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003450: 4313 orrs r3, r2
- 8003452: f8c1 3088 str.w r3, [r1, #136] ; 0x88
- }
-
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- /*---------------------------- LTDC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 8003456: 687b ldr r3, [r7, #4]
- 8003458: 681b ldr r3, [r3, #0]
- 800345a: f003 0308 and.w r3, r3, #8
- 800345e: 2b00 cmp r3, #0
- 8003460: d028 beq.n 80034b4 <HAL_RCCEx_PeriphCLKConfig+0x808>
- {
- assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
- assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
- /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 8003462: 4b24 ldr r3, [pc, #144] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003464: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003468: 0e1b lsrs r3, r3, #24
- 800346a: f003 030f and.w r3, r3, #15
- 800346e: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8003470: 4b20 ldr r3, [pc, #128] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003472: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003476: 0c1b lsrs r3, r3, #16
- 8003478: f003 0303 and.w r3, r3, #3
- 800347c: 60fb str r3, [r7, #12]
-
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 800347e: 687b ldr r3, [r7, #4]
- 8003480: 695b ldr r3, [r3, #20]
- 8003482: 019a lsls r2, r3, #6
- 8003484: 68fb ldr r3, [r7, #12]
- 8003486: 041b lsls r3, r3, #16
- 8003488: 431a orrs r2, r3
- 800348a: 693b ldr r3, [r7, #16]
- 800348c: 061b lsls r3, r3, #24
- 800348e: 431a orrs r2, r3
- 8003490: 687b ldr r3, [r7, #4]
- 8003492: 69db ldr r3, [r3, #28]
- 8003494: 071b lsls r3, r3, #28
- 8003496: 4917 ldr r1, [pc, #92] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003498: 4313 orrs r3, r2
- 800349a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 800349e: 4b15 ldr r3, [pc, #84] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80034a0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80034a4: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 80034a8: 687b ldr r3, [r7, #4]
- 80034aa: 6adb ldr r3, [r3, #44] ; 0x2c
- 80034ac: 4911 ldr r1, [pc, #68] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80034ae: 4313 orrs r3, r2
- 80034b0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /* Enable PLLSAI Clock */
- __HAL_RCC_PLLSAI_ENABLE();
- 80034b4: 4b0f ldr r3, [pc, #60] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80034b6: 681b ldr r3, [r3, #0]
- 80034b8: 4a0e ldr r2, [pc, #56] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80034ba: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80034be: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80034c0: f7fe fc98 bl 8001df4 <HAL_GetTick>
- 80034c4: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is ready */
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 80034c6: e008 b.n 80034da <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 80034c8: f7fe fc94 bl 8001df4 <HAL_GetTick>
- 80034cc: 4602 mov r2, r0
- 80034ce: 697b ldr r3, [r7, #20]
- 80034d0: 1ad3 subs r3, r2, r3
- 80034d2: 2b64 cmp r3, #100 ; 0x64
- 80034d4: d901 bls.n 80034da <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 80034d6: 2303 movs r3, #3
- 80034d8: e007 b.n 80034ea <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 80034da: 4b06 ldr r3, [pc, #24] ; (80034f4 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80034dc: 681b ldr r3, [r3, #0]
- 80034de: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 80034e2: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 80034e6: d1ef bne.n 80034c8 <HAL_RCCEx_PeriphCLKConfig+0x81c>
- }
- }
- }
- return HAL_OK;
- 80034e8: 2300 movs r3, #0
-}
- 80034ea: 4618 mov r0, r3
- 80034ec: 3720 adds r7, #32
- 80034ee: 46bd mov sp, r7
- 80034f0: bd80 pop {r7, pc}
- 80034f2: bf00 nop
- 80034f4: 40023800 .word 0x40023800
-
-080034f8 <HAL_TIM_Base_Init>:
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- 80034f8: b580 push {r7, lr}
- 80034fa: b082 sub sp, #8
- 80034fc: af00 add r7, sp, #0
- 80034fe: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 8003500: 687b ldr r3, [r7, #4]
- 8003502: 2b00 cmp r3, #0
- 8003504: d101 bne.n 800350a <HAL_TIM_Base_Init+0x12>
- {
- return HAL_ERROR;
- 8003506: 2301 movs r3, #1
- 8003508: e01d b.n 8003546 <HAL_TIM_Base_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 800350a: 687b ldr r3, [r7, #4]
- 800350c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8003510: b2db uxtb r3, r3
- 8003512: 2b00 cmp r3, #0
- 8003514: d106 bne.n 8003524 <HAL_TIM_Base_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 8003516: 687b ldr r3, [r7, #4]
- 8003518: 2200 movs r2, #0
- 800351a: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- 800351e: 6878 ldr r0, [r7, #4]
- 8003520: f7fe faa0 bl 8001a64 <HAL_TIM_Base_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 8003524: 687b ldr r3, [r7, #4]
- 8003526: 2202 movs r2, #2
- 8003528: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 800352c: 687b ldr r3, [r7, #4]
- 800352e: 681a ldr r2, [r3, #0]
- 8003530: 687b ldr r3, [r7, #4]
- 8003532: 3304 adds r3, #4
- 8003534: 4619 mov r1, r3
- 8003536: 4610 mov r0, r2
- 8003538: f000 fc90 bl 8003e5c <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 800353c: 687b ldr r3, [r7, #4]
- 800353e: 2201 movs r2, #1
- 8003540: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 8003544: 2300 movs r3, #0
-}
- 8003546: 4618 mov r0, r3
- 8003548: 3708 adds r7, #8
- 800354a: 46bd mov sp, r7
- 800354c: bd80 pop {r7, pc}
- ...
-
-08003550 <HAL_TIM_Base_Start_IT>:
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- 8003550: b480 push {r7}
- 8003552: b085 sub sp, #20
- 8003554: af00 add r7, sp, #0
- 8003556: 6078 str r0, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- 8003558: 687b ldr r3, [r7, #4]
- 800355a: 681b ldr r3, [r3, #0]
- 800355c: 68da ldr r2, [r3, #12]
- 800355e: 687b ldr r3, [r7, #4]
- 8003560: 681b ldr r3, [r3, #0]
- 8003562: f042 0201 orr.w r2, r2, #1
- 8003566: 60da str r2, [r3, #12]
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 8003568: 687b ldr r3, [r7, #4]
- 800356a: 681b ldr r3, [r3, #0]
- 800356c: 689a ldr r2, [r3, #8]
- 800356e: 4b0c ldr r3, [pc, #48] ; (80035a0 <HAL_TIM_Base_Start_IT+0x50>)
- 8003570: 4013 ands r3, r2
- 8003572: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8003574: 68fb ldr r3, [r7, #12]
- 8003576: 2b06 cmp r3, #6
- 8003578: d00b beq.n 8003592 <HAL_TIM_Base_Start_IT+0x42>
- 800357a: 68fb ldr r3, [r7, #12]
- 800357c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8003580: d007 beq.n 8003592 <HAL_TIM_Base_Start_IT+0x42>
- {
- __HAL_TIM_ENABLE(htim);
- 8003582: 687b ldr r3, [r7, #4]
- 8003584: 681b ldr r3, [r3, #0]
- 8003586: 681a ldr r2, [r3, #0]
- 8003588: 687b ldr r3, [r7, #4]
- 800358a: 681b ldr r3, [r3, #0]
- 800358c: f042 0201 orr.w r2, r2, #1
- 8003590: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 8003592: 2300 movs r3, #0
-}
- 8003594: 4618 mov r0, r3
- 8003596: 3714 adds r7, #20
- 8003598: 46bd mov sp, r7
- 800359a: f85d 7b04 ldr.w r7, [sp], #4
- 800359e: 4770 bx lr
- 80035a0: 00010007 .word 0x00010007
-
-080035a4 <HAL_TIM_PWM_Init>:
- * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- 80035a4: b580 push {r7, lr}
- 80035a6: b082 sub sp, #8
- 80035a8: af00 add r7, sp, #0
- 80035aa: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 80035ac: 687b ldr r3, [r7, #4]
- 80035ae: 2b00 cmp r3, #0
- 80035b0: d101 bne.n 80035b6 <HAL_TIM_PWM_Init+0x12>
- {
- return HAL_ERROR;
- 80035b2: 2301 movs r3, #1
- 80035b4: e01d b.n 80035f2 <HAL_TIM_PWM_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 80035b6: 687b ldr r3, [r7, #4]
- 80035b8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 80035bc: b2db uxtb r3, r3
- 80035be: 2b00 cmp r3, #0
- 80035c0: d106 bne.n 80035d0 <HAL_TIM_PWM_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 80035c2: 687b ldr r3, [r7, #4]
- 80035c4: 2200 movs r2, #0
- 80035c6: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->PWM_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
- 80035ca: 6878 ldr r0, [r7, #4]
- 80035cc: f000 f815 bl 80035fa <HAL_TIM_PWM_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80035d0: 687b ldr r3, [r7, #4]
- 80035d2: 2202 movs r2, #2
- 80035d4: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80035d8: 687b ldr r3, [r7, #4]
- 80035da: 681a ldr r2, [r3, #0]
- 80035dc: 687b ldr r3, [r7, #4]
- 80035de: 3304 adds r3, #4
- 80035e0: 4619 mov r1, r3
- 80035e2: 4610 mov r0, r2
- 80035e4: f000 fc3a bl 8003e5c <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 80035e8: 687b ldr r3, [r7, #4]
- 80035ea: 2201 movs r2, #1
- 80035ec: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 80035f0: 2300 movs r3, #0
-}
- 80035f2: 4618 mov r0, r3
- 80035f4: 3708 adds r7, #8
- 80035f6: 46bd mov sp, r7
- 80035f8: bd80 pop {r7, pc}
-
-080035fa <HAL_TIM_PWM_MspInit>:
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- 80035fa: b480 push {r7}
- 80035fc: b083 sub sp, #12
- 80035fe: af00 add r7, sp, #0
- 8003600: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
- 8003602: bf00 nop
- 8003604: 370c adds r7, #12
- 8003606: 46bd mov sp, r7
- 8003608: f85d 7b04 ldr.w r7, [sp], #4
- 800360c: 4770 bx lr
- ...
-
-08003610 <HAL_TIM_PWM_Start>:
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 8003610: b580 push {r7, lr}
- 8003612: b084 sub sp, #16
- 8003614: af00 add r7, sp, #0
- 8003616: 6078 str r0, [r7, #4]
- 8003618: 6039 str r1, [r7, #0]
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- 800361a: 687b ldr r3, [r7, #4]
- 800361c: 681b ldr r3, [r3, #0]
- 800361e: 2201 movs r2, #1
- 8003620: 6839 ldr r1, [r7, #0]
- 8003622: 4618 mov r0, r3
- 8003624: f000 ffb2 bl 800458c <TIM_CCxChannelCmd>
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- 8003628: 687b ldr r3, [r7, #4]
- 800362a: 681b ldr r3, [r3, #0]
- 800362c: 4a17 ldr r2, [pc, #92] ; (800368c <HAL_TIM_PWM_Start+0x7c>)
- 800362e: 4293 cmp r3, r2
- 8003630: d004 beq.n 800363c <HAL_TIM_PWM_Start+0x2c>
- 8003632: 687b ldr r3, [r7, #4]
- 8003634: 681b ldr r3, [r3, #0]
- 8003636: 4a16 ldr r2, [pc, #88] ; (8003690 <HAL_TIM_PWM_Start+0x80>)
- 8003638: 4293 cmp r3, r2
- 800363a: d101 bne.n 8003640 <HAL_TIM_PWM_Start+0x30>
- 800363c: 2301 movs r3, #1
- 800363e: e000 b.n 8003642 <HAL_TIM_PWM_Start+0x32>
- 8003640: 2300 movs r3, #0
- 8003642: 2b00 cmp r3, #0
- 8003644: d007 beq.n 8003656 <HAL_TIM_PWM_Start+0x46>
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- 8003646: 687b ldr r3, [r7, #4]
- 8003648: 681b ldr r3, [r3, #0]
- 800364a: 6c5a ldr r2, [r3, #68] ; 0x44
- 800364c: 687b ldr r3, [r7, #4]
- 800364e: 681b ldr r3, [r3, #0]
- 8003650: f442 4200 orr.w r2, r2, #32768 ; 0x8000
- 8003654: 645a str r2, [r3, #68] ; 0x44
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 8003656: 687b ldr r3, [r7, #4]
- 8003658: 681b ldr r3, [r3, #0]
- 800365a: 689a ldr r2, [r3, #8]
- 800365c: 4b0d ldr r3, [pc, #52] ; (8003694 <HAL_TIM_PWM_Start+0x84>)
- 800365e: 4013 ands r3, r2
- 8003660: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8003662: 68fb ldr r3, [r7, #12]
- 8003664: 2b06 cmp r3, #6
- 8003666: d00b beq.n 8003680 <HAL_TIM_PWM_Start+0x70>
- 8003668: 68fb ldr r3, [r7, #12]
- 800366a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800366e: d007 beq.n 8003680 <HAL_TIM_PWM_Start+0x70>
- {
- __HAL_TIM_ENABLE(htim);
- 8003670: 687b ldr r3, [r7, #4]
- 8003672: 681b ldr r3, [r3, #0]
- 8003674: 681a ldr r2, [r3, #0]
- 8003676: 687b ldr r3, [r7, #4]
- 8003678: 681b ldr r3, [r3, #0]
- 800367a: f042 0201 orr.w r2, r2, #1
- 800367e: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 8003680: 2300 movs r3, #0
-}
- 8003682: 4618 mov r0, r3
- 8003684: 3710 adds r7, #16
- 8003686: 46bd mov sp, r7
- 8003688: bd80 pop {r7, pc}
- 800368a: bf00 nop
- 800368c: 40010000 .word 0x40010000
- 8003690: 40010400 .word 0x40010400
- 8003694: 00010007 .word 0x00010007
-
-08003698 <HAL_TIM_Encoder_Init>:
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
-{
- 8003698: b580 push {r7, lr}
- 800369a: b086 sub sp, #24
- 800369c: af00 add r7, sp, #0
- 800369e: 6078 str r0, [r7, #4]
- 80036a0: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 80036a2: 687b ldr r3, [r7, #4]
- 80036a4: 2b00 cmp r3, #0
- 80036a6: d101 bne.n 80036ac <HAL_TIM_Encoder_Init+0x14>
- {
- return HAL_ERROR;
- 80036a8: 2301 movs r3, #1
- 80036aa: e07b b.n 80037a4 <HAL_TIM_Encoder_Init+0x10c>
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 80036ac: 687b ldr r3, [r7, #4]
- 80036ae: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 80036b2: b2db uxtb r3, r3
- 80036b4: 2b00 cmp r3, #0
- 80036b6: d106 bne.n 80036c6 <HAL_TIM_Encoder_Init+0x2e>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 80036b8: 687b ldr r3, [r7, #4]
- 80036ba: 2200 movs r2, #0
- 80036bc: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Encoder_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
- 80036c0: 6878 ldr r0, [r7, #4]
- 80036c2: f7fe f93f bl 8001944 <HAL_TIM_Encoder_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80036c6: 687b ldr r3, [r7, #4]
- 80036c8: 2202 movs r2, #2
- 80036ca: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Reset the SMS and ECE bits */
- htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
- 80036ce: 687b ldr r3, [r7, #4]
- 80036d0: 681b ldr r3, [r3, #0]
- 80036d2: 6899 ldr r1, [r3, #8]
- 80036d4: 687b ldr r3, [r7, #4]
- 80036d6: 681a ldr r2, [r3, #0]
- 80036d8: 4b34 ldr r3, [pc, #208] ; (80037ac <HAL_TIM_Encoder_Init+0x114>)
- 80036da: 400b ands r3, r1
- 80036dc: 6093 str r3, [r2, #8]
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80036de: 687b ldr r3, [r7, #4]
- 80036e0: 681a ldr r2, [r3, #0]
- 80036e2: 687b ldr r3, [r7, #4]
- 80036e4: 3304 adds r3, #4
- 80036e6: 4619 mov r1, r3
- 80036e8: 4610 mov r0, r2
- 80036ea: f000 fbb7 bl 8003e5c <TIM_Base_SetConfig>
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 80036ee: 687b ldr r3, [r7, #4]
- 80036f0: 681b ldr r3, [r3, #0]
- 80036f2: 689b ldr r3, [r3, #8]
- 80036f4: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
- 80036f6: 687b ldr r3, [r7, #4]
- 80036f8: 681b ldr r3, [r3, #0]
- 80036fa: 699b ldr r3, [r3, #24]
- 80036fc: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
- 80036fe: 687b ldr r3, [r7, #4]
- 8003700: 681b ldr r3, [r3, #0]
- 8003702: 6a1b ldr r3, [r3, #32]
- 8003704: 60fb str r3, [r7, #12]
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
- 8003706: 683b ldr r3, [r7, #0]
- 8003708: 681b ldr r3, [r3, #0]
- 800370a: 697a ldr r2, [r7, #20]
- 800370c: 4313 orrs r3, r2
- 800370e: 617b str r3, [r7, #20]
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- 8003710: 693a ldr r2, [r7, #16]
- 8003712: 4b27 ldr r3, [pc, #156] ; (80037b0 <HAL_TIM_Encoder_Init+0x118>)
- 8003714: 4013 ands r3, r2
- 8003716: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- 8003718: 683b ldr r3, [r7, #0]
- 800371a: 689a ldr r2, [r3, #8]
- 800371c: 683b ldr r3, [r7, #0]
- 800371e: 699b ldr r3, [r3, #24]
- 8003720: 021b lsls r3, r3, #8
- 8003722: 4313 orrs r3, r2
- 8003724: 693a ldr r2, [r7, #16]
- 8003726: 4313 orrs r3, r2
- 8003728: 613b str r3, [r7, #16]
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- 800372a: 693a ldr r2, [r7, #16]
- 800372c: 4b21 ldr r3, [pc, #132] ; (80037b4 <HAL_TIM_Encoder_Init+0x11c>)
- 800372e: 4013 ands r3, r2
- 8003730: 613b str r3, [r7, #16]
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- 8003732: 693a ldr r2, [r7, #16]
- 8003734: 4b20 ldr r3, [pc, #128] ; (80037b8 <HAL_TIM_Encoder_Init+0x120>)
- 8003736: 4013 ands r3, r2
- 8003738: 613b str r3, [r7, #16]
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- 800373a: 683b ldr r3, [r7, #0]
- 800373c: 68da ldr r2, [r3, #12]
- 800373e: 683b ldr r3, [r7, #0]
- 8003740: 69db ldr r3, [r3, #28]
- 8003742: 021b lsls r3, r3, #8
- 8003744: 4313 orrs r3, r2
- 8003746: 693a ldr r2, [r7, #16]
- 8003748: 4313 orrs r3, r2
- 800374a: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
- 800374c: 683b ldr r3, [r7, #0]
- 800374e: 691b ldr r3, [r3, #16]
- 8003750: 011a lsls r2, r3, #4
- 8003752: 683b ldr r3, [r7, #0]
- 8003754: 6a1b ldr r3, [r3, #32]
- 8003756: 031b lsls r3, r3, #12
- 8003758: 4313 orrs r3, r2
- 800375a: 693a ldr r2, [r7, #16]
- 800375c: 4313 orrs r3, r2
- 800375e: 613b str r3, [r7, #16]
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- 8003760: 68fb ldr r3, [r7, #12]
- 8003762: f023 0322 bic.w r3, r3, #34 ; 0x22
- 8003766: 60fb str r3, [r7, #12]
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- 8003768: 68fb ldr r3, [r7, #12]
- 800376a: f023 0388 bic.w r3, r3, #136 ; 0x88
- 800376e: 60fb str r3, [r7, #12]
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
- 8003770: 683b ldr r3, [r7, #0]
- 8003772: 685a ldr r2, [r3, #4]
- 8003774: 683b ldr r3, [r7, #0]
- 8003776: 695b ldr r3, [r3, #20]
- 8003778: 011b lsls r3, r3, #4
- 800377a: 4313 orrs r3, r2
- 800377c: 68fa ldr r2, [r7, #12]
- 800377e: 4313 orrs r3, r2
- 8003780: 60fb str r3, [r7, #12]
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 8003782: 687b ldr r3, [r7, #4]
- 8003784: 681b ldr r3, [r3, #0]
- 8003786: 697a ldr r2, [r7, #20]
- 8003788: 609a str r2, [r3, #8]
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
- 800378a: 687b ldr r3, [r7, #4]
- 800378c: 681b ldr r3, [r3, #0]
- 800378e: 693a ldr r2, [r7, #16]
- 8003790: 619a str r2, [r3, #24]
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
- 8003792: 687b ldr r3, [r7, #4]
- 8003794: 681b ldr r3, [r3, #0]
- 8003796: 68fa ldr r2, [r7, #12]
- 8003798: 621a str r2, [r3, #32]
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 800379a: 687b ldr r3, [r7, #4]
- 800379c: 2201 movs r2, #1
- 800379e: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 80037a2: 2300 movs r3, #0
-}
- 80037a4: 4618 mov r0, r3
- 80037a6: 3718 adds r7, #24
- 80037a8: 46bd mov sp, r7
- 80037aa: bd80 pop {r7, pc}
- 80037ac: fffebff8 .word 0xfffebff8
- 80037b0: fffffcfc .word 0xfffffcfc
- 80037b4: fffff3f3 .word 0xfffff3f3
- 80037b8: ffff0f0f .word 0xffff0f0f
-
-080037bc <HAL_TIM_Encoder_Start>:
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 80037bc: b580 push {r7, lr}
- 80037be: b082 sub sp, #8
- 80037c0: af00 add r7, sp, #0
- 80037c2: 6078 str r0, [r7, #4]
- 80037c4: 6039 str r1, [r7, #0]
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- switch (Channel)
- 80037c6: 683b ldr r3, [r7, #0]
- 80037c8: 2b00 cmp r3, #0
- 80037ca: d002 beq.n 80037d2 <HAL_TIM_Encoder_Start+0x16>
- 80037cc: 2b04 cmp r3, #4
- 80037ce: d008 beq.n 80037e2 <HAL_TIM_Encoder_Start+0x26>
- 80037d0: e00f b.n 80037f2 <HAL_TIM_Encoder_Start+0x36>
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 80037d2: 687b ldr r3, [r7, #4]
- 80037d4: 681b ldr r3, [r3, #0]
- 80037d6: 2201 movs r2, #1
- 80037d8: 2100 movs r1, #0
- 80037da: 4618 mov r0, r3
- 80037dc: f000 fed6 bl 800458c <TIM_CCxChannelCmd>
- break;
- 80037e0: e016 b.n 8003810 <HAL_TIM_Encoder_Start+0x54>
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 80037e2: 687b ldr r3, [r7, #4]
- 80037e4: 681b ldr r3, [r3, #0]
- 80037e6: 2201 movs r2, #1
- 80037e8: 2104 movs r1, #4
- 80037ea: 4618 mov r0, r3
- 80037ec: f000 fece bl 800458c <TIM_CCxChannelCmd>
- break;
- 80037f0: e00e b.n 8003810 <HAL_TIM_Encoder_Start+0x54>
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 80037f2: 687b ldr r3, [r7, #4]
- 80037f4: 681b ldr r3, [r3, #0]
- 80037f6: 2201 movs r2, #1
- 80037f8: 2100 movs r1, #0
- 80037fa: 4618 mov r0, r3
- 80037fc: f000 fec6 bl 800458c <TIM_CCxChannelCmd>
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 8003800: 687b ldr r3, [r7, #4]
- 8003802: 681b ldr r3, [r3, #0]
- 8003804: 2201 movs r2, #1
- 8003806: 2104 movs r1, #4
- 8003808: 4618 mov r0, r3
- 800380a: f000 febf bl 800458c <TIM_CCxChannelCmd>
- break;
- 800380e: bf00 nop
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
- 8003810: 687b ldr r3, [r7, #4]
- 8003812: 681b ldr r3, [r3, #0]
- 8003814: 681a ldr r2, [r3, #0]
- 8003816: 687b ldr r3, [r7, #4]
- 8003818: 681b ldr r3, [r3, #0]
- 800381a: f042 0201 orr.w r2, r2, #1
- 800381e: 601a str r2, [r3, #0]
-
- /* Return function status */
- return HAL_OK;
- 8003820: 2300 movs r3, #0
-}
- 8003822: 4618 mov r0, r3
- 8003824: 3708 adds r7, #8
- 8003826: 46bd mov sp, r7
- 8003828: bd80 pop {r7, pc}
-
-0800382a <HAL_TIM_IRQHandler>:
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- 800382a: b580 push {r7, lr}
- 800382c: b082 sub sp, #8
- 800382e: af00 add r7, sp, #0
- 8003830: 6078 str r0, [r7, #4]
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- 8003832: 687b ldr r3, [r7, #4]
- 8003834: 681b ldr r3, [r3, #0]
- 8003836: 691b ldr r3, [r3, #16]
- 8003838: f003 0302 and.w r3, r3, #2
- 800383c: 2b02 cmp r3, #2
- 800383e: d122 bne.n 8003886 <HAL_TIM_IRQHandler+0x5c>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- 8003840: 687b ldr r3, [r7, #4]
- 8003842: 681b ldr r3, [r3, #0]
- 8003844: 68db ldr r3, [r3, #12]
- 8003846: f003 0302 and.w r3, r3, #2
- 800384a: 2b02 cmp r3, #2
- 800384c: d11b bne.n 8003886 <HAL_TIM_IRQHandler+0x5c>
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- 800384e: 687b ldr r3, [r7, #4]
- 8003850: 681b ldr r3, [r3, #0]
- 8003852: f06f 0202 mvn.w r2, #2
- 8003856: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- 8003858: 687b ldr r3, [r7, #4]
- 800385a: 2201 movs r2, #1
- 800385c: 771a strb r2, [r3, #28]
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- 800385e: 687b ldr r3, [r7, #4]
- 8003860: 681b ldr r3, [r3, #0]
- 8003862: 699b ldr r3, [r3, #24]
- 8003864: f003 0303 and.w r3, r3, #3
- 8003868: 2b00 cmp r3, #0
- 800386a: d003 beq.n 8003874 <HAL_TIM_IRQHandler+0x4a>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 800386c: 6878 ldr r0, [r7, #4]
- 800386e: f000 fad7 bl 8003e20 <HAL_TIM_IC_CaptureCallback>
- 8003872: e005 b.n 8003880 <HAL_TIM_IRQHandler+0x56>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003874: 6878 ldr r0, [r7, #4]
- 8003876: f000 fac9 bl 8003e0c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 800387a: 6878 ldr r0, [r7, #4]
- 800387c: f000 fada bl 8003e34 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003880: 687b ldr r3, [r7, #4]
- 8003882: 2200 movs r2, #0
- 8003884: 771a strb r2, [r3, #28]
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- 8003886: 687b ldr r3, [r7, #4]
- 8003888: 681b ldr r3, [r3, #0]
- 800388a: 691b ldr r3, [r3, #16]
- 800388c: f003 0304 and.w r3, r3, #4
- 8003890: 2b04 cmp r3, #4
- 8003892: d122 bne.n 80038da <HAL_TIM_IRQHandler+0xb0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- 8003894: 687b ldr r3, [r7, #4]
- 8003896: 681b ldr r3, [r3, #0]
- 8003898: 68db ldr r3, [r3, #12]
- 800389a: f003 0304 and.w r3, r3, #4
- 800389e: 2b04 cmp r3, #4
- 80038a0: d11b bne.n 80038da <HAL_TIM_IRQHandler+0xb0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- 80038a2: 687b ldr r3, [r7, #4]
- 80038a4: 681b ldr r3, [r3, #0]
- 80038a6: f06f 0204 mvn.w r2, #4
- 80038aa: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- 80038ac: 687b ldr r3, [r7, #4]
- 80038ae: 2202 movs r2, #2
- 80038b0: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- 80038b2: 687b ldr r3, [r7, #4]
- 80038b4: 681b ldr r3, [r3, #0]
- 80038b6: 699b ldr r3, [r3, #24]
- 80038b8: f403 7340 and.w r3, r3, #768 ; 0x300
- 80038bc: 2b00 cmp r3, #0
- 80038be: d003 beq.n 80038c8 <HAL_TIM_IRQHandler+0x9e>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 80038c0: 6878 ldr r0, [r7, #4]
- 80038c2: f000 faad bl 8003e20 <HAL_TIM_IC_CaptureCallback>
- 80038c6: e005 b.n 80038d4 <HAL_TIM_IRQHandler+0xaa>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 80038c8: 6878 ldr r0, [r7, #4]
- 80038ca: f000 fa9f bl 8003e0c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80038ce: 6878 ldr r0, [r7, #4]
- 80038d0: f000 fab0 bl 8003e34 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80038d4: 687b ldr r3, [r7, #4]
- 80038d6: 2200 movs r2, #0
- 80038d8: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- 80038da: 687b ldr r3, [r7, #4]
- 80038dc: 681b ldr r3, [r3, #0]
- 80038de: 691b ldr r3, [r3, #16]
- 80038e0: f003 0308 and.w r3, r3, #8
- 80038e4: 2b08 cmp r3, #8
- 80038e6: d122 bne.n 800392e <HAL_TIM_IRQHandler+0x104>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- 80038e8: 687b ldr r3, [r7, #4]
- 80038ea: 681b ldr r3, [r3, #0]
- 80038ec: 68db ldr r3, [r3, #12]
- 80038ee: f003 0308 and.w r3, r3, #8
- 80038f2: 2b08 cmp r3, #8
- 80038f4: d11b bne.n 800392e <HAL_TIM_IRQHandler+0x104>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- 80038f6: 687b ldr r3, [r7, #4]
- 80038f8: 681b ldr r3, [r3, #0]
- 80038fa: f06f 0208 mvn.w r2, #8
- 80038fe: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- 8003900: 687b ldr r3, [r7, #4]
- 8003902: 2204 movs r2, #4
- 8003904: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- 8003906: 687b ldr r3, [r7, #4]
- 8003908: 681b ldr r3, [r3, #0]
- 800390a: 69db ldr r3, [r3, #28]
- 800390c: f003 0303 and.w r3, r3, #3
- 8003910: 2b00 cmp r3, #0
- 8003912: d003 beq.n 800391c <HAL_TIM_IRQHandler+0xf2>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003914: 6878 ldr r0, [r7, #4]
- 8003916: f000 fa83 bl 8003e20 <HAL_TIM_IC_CaptureCallback>
- 800391a: e005 b.n 8003928 <HAL_TIM_IRQHandler+0xfe>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 800391c: 6878 ldr r0, [r7, #4]
- 800391e: f000 fa75 bl 8003e0c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8003922: 6878 ldr r0, [r7, #4]
- 8003924: f000 fa86 bl 8003e34 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003928: 687b ldr r3, [r7, #4]
- 800392a: 2200 movs r2, #0
- 800392c: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- 800392e: 687b ldr r3, [r7, #4]
- 8003930: 681b ldr r3, [r3, #0]
- 8003932: 691b ldr r3, [r3, #16]
- 8003934: f003 0310 and.w r3, r3, #16
- 8003938: 2b10 cmp r3, #16
- 800393a: d122 bne.n 8003982 <HAL_TIM_IRQHandler+0x158>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- 800393c: 687b ldr r3, [r7, #4]
- 800393e: 681b ldr r3, [r3, #0]
- 8003940: 68db ldr r3, [r3, #12]
- 8003942: f003 0310 and.w r3, r3, #16
- 8003946: 2b10 cmp r3, #16
- 8003948: d11b bne.n 8003982 <HAL_TIM_IRQHandler+0x158>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- 800394a: 687b ldr r3, [r7, #4]
- 800394c: 681b ldr r3, [r3, #0]
- 800394e: f06f 0210 mvn.w r2, #16
- 8003952: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- 8003954: 687b ldr r3, [r7, #4]
- 8003956: 2208 movs r2, #8
- 8003958: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- 800395a: 687b ldr r3, [r7, #4]
- 800395c: 681b ldr r3, [r3, #0]
- 800395e: 69db ldr r3, [r3, #28]
- 8003960: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003964: 2b00 cmp r3, #0
- 8003966: d003 beq.n 8003970 <HAL_TIM_IRQHandler+0x146>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003968: 6878 ldr r0, [r7, #4]
- 800396a: f000 fa59 bl 8003e20 <HAL_TIM_IC_CaptureCallback>
- 800396e: e005 b.n 800397c <HAL_TIM_IRQHandler+0x152>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003970: 6878 ldr r0, [r7, #4]
- 8003972: f000 fa4b bl 8003e0c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8003976: 6878 ldr r0, [r7, #4]
- 8003978: f000 fa5c bl 8003e34 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 800397c: 687b ldr r3, [r7, #4]
- 800397e: 2200 movs r2, #0
- 8003980: 771a strb r2, [r3, #28]
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- 8003982: 687b ldr r3, [r7, #4]
- 8003984: 681b ldr r3, [r3, #0]
- 8003986: 691b ldr r3, [r3, #16]
- 8003988: f003 0301 and.w r3, r3, #1
- 800398c: 2b01 cmp r3, #1
- 800398e: d10e bne.n 80039ae <HAL_TIM_IRQHandler+0x184>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- 8003990: 687b ldr r3, [r7, #4]
- 8003992: 681b ldr r3, [r3, #0]
- 8003994: 68db ldr r3, [r3, #12]
- 8003996: f003 0301 and.w r3, r3, #1
- 800399a: 2b01 cmp r3, #1
- 800399c: d107 bne.n 80039ae <HAL_TIM_IRQHandler+0x184>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- 800399e: 687b ldr r3, [r7, #4]
- 80039a0: 681b ldr r3, [r3, #0]
- 80039a2: f06f 0201 mvn.w r2, #1
- 80039a6: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
- 80039a8: 6878 ldr r0, [r7, #4]
- 80039aa: f7fd fcff bl 80013ac <HAL_TIM_PeriodElapsedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- 80039ae: 687b ldr r3, [r7, #4]
- 80039b0: 681b ldr r3, [r3, #0]
- 80039b2: 691b ldr r3, [r3, #16]
- 80039b4: f003 0380 and.w r3, r3, #128 ; 0x80
- 80039b8: 2b80 cmp r3, #128 ; 0x80
- 80039ba: d10e bne.n 80039da <HAL_TIM_IRQHandler+0x1b0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 80039bc: 687b ldr r3, [r7, #4]
- 80039be: 681b ldr r3, [r3, #0]
- 80039c0: 68db ldr r3, [r3, #12]
- 80039c2: f003 0380 and.w r3, r3, #128 ; 0x80
- 80039c6: 2b80 cmp r3, #128 ; 0x80
- 80039c8: d107 bne.n 80039da <HAL_TIM_IRQHandler+0x1b0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- 80039ca: 687b ldr r3, [r7, #4]
- 80039cc: 681b ldr r3, [r3, #0]
- 80039ce: f06f 0280 mvn.w r2, #128 ; 0x80
- 80039d2: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
- 80039d4: 6878 ldr r0, [r7, #4]
- 80039d6: f000 fe65 bl 80046a4 <HAL_TIMEx_BreakCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- 80039da: 687b ldr r3, [r7, #4]
- 80039dc: 681b ldr r3, [r3, #0]
- 80039de: 691b ldr r3, [r3, #16]
- 80039e0: f403 7380 and.w r3, r3, #256 ; 0x100
- 80039e4: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 80039e8: d10e bne.n 8003a08 <HAL_TIM_IRQHandler+0x1de>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 80039ea: 687b ldr r3, [r7, #4]
- 80039ec: 681b ldr r3, [r3, #0]
- 80039ee: 68db ldr r3, [r3, #12]
- 80039f0: f003 0380 and.w r3, r3, #128 ; 0x80
- 80039f4: 2b80 cmp r3, #128 ; 0x80
- 80039f6: d107 bne.n 8003a08 <HAL_TIM_IRQHandler+0x1de>
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- 80039f8: 687b ldr r3, [r7, #4]
- 80039fa: 681b ldr r3, [r3, #0]
- 80039fc: f46f 7280 mvn.w r2, #256 ; 0x100
- 8003a00: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->Break2Callback(htim);
-#else
- HAL_TIMEx_Break2Callback(htim);
- 8003a02: 6878 ldr r0, [r7, #4]
- 8003a04: f000 fe58 bl 80046b8 <HAL_TIMEx_Break2Callback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- 8003a08: 687b ldr r3, [r7, #4]
- 8003a0a: 681b ldr r3, [r3, #0]
- 8003a0c: 691b ldr r3, [r3, #16]
- 8003a0e: f003 0340 and.w r3, r3, #64 ; 0x40
- 8003a12: 2b40 cmp r3, #64 ; 0x40
- 8003a14: d10e bne.n 8003a34 <HAL_TIM_IRQHandler+0x20a>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- 8003a16: 687b ldr r3, [r7, #4]
- 8003a18: 681b ldr r3, [r3, #0]
- 8003a1a: 68db ldr r3, [r3, #12]
- 8003a1c: f003 0340 and.w r3, r3, #64 ; 0x40
- 8003a20: 2b40 cmp r3, #64 ; 0x40
- 8003a22: d107 bne.n 8003a34 <HAL_TIM_IRQHandler+0x20a>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- 8003a24: 687b ldr r3, [r7, #4]
- 8003a26: 681b ldr r3, [r3, #0]
- 8003a28: f06f 0240 mvn.w r2, #64 ; 0x40
- 8003a2c: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
- 8003a2e: 6878 ldr r0, [r7, #4]
- 8003a30: f000 fa0a bl 8003e48 <HAL_TIM_TriggerCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- 8003a34: 687b ldr r3, [r7, #4]
- 8003a36: 681b ldr r3, [r3, #0]
- 8003a38: 691b ldr r3, [r3, #16]
- 8003a3a: f003 0320 and.w r3, r3, #32
- 8003a3e: 2b20 cmp r3, #32
- 8003a40: d10e bne.n 8003a60 <HAL_TIM_IRQHandler+0x236>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- 8003a42: 687b ldr r3, [r7, #4]
- 8003a44: 681b ldr r3, [r3, #0]
- 8003a46: 68db ldr r3, [r3, #12]
- 8003a48: f003 0320 and.w r3, r3, #32
- 8003a4c: 2b20 cmp r3, #32
- 8003a4e: d107 bne.n 8003a60 <HAL_TIM_IRQHandler+0x236>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- 8003a50: 687b ldr r3, [r7, #4]
- 8003a52: 681b ldr r3, [r3, #0]
- 8003a54: f06f 0220 mvn.w r2, #32
- 8003a58: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
- 8003a5a: 6878 ldr r0, [r7, #4]
- 8003a5c: f000 fe18 bl 8004690 <HAL_TIMEx_CommutCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
- 8003a60: bf00 nop
- 8003a62: 3708 adds r7, #8
- 8003a64: 46bd mov sp, r7
- 8003a66: bd80 pop {r7, pc}
-
-08003a68 <HAL_TIM_PWM_ConfigChannel>:
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- 8003a68: b580 push {r7, lr}
- 8003a6a: b084 sub sp, #16
- 8003a6c: af00 add r7, sp, #0
- 8003a6e: 60f8 str r0, [r7, #12]
- 8003a70: 60b9 str r1, [r7, #8]
- 8003a72: 607a str r2, [r7, #4]
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003a74: 68fb ldr r3, [r7, #12]
- 8003a76: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8003a7a: 2b01 cmp r3, #1
- 8003a7c: d101 bne.n 8003a82 <HAL_TIM_PWM_ConfigChannel+0x1a>
- 8003a7e: 2302 movs r3, #2
- 8003a80: e105 b.n 8003c8e <HAL_TIM_PWM_ConfigChannel+0x226>
- 8003a82: 68fb ldr r3, [r7, #12]
- 8003a84: 2201 movs r2, #1
- 8003a86: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8003a8a: 68fb ldr r3, [r7, #12]
- 8003a8c: 2202 movs r2, #2
- 8003a8e: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- switch (Channel)
- 8003a92: 687b ldr r3, [r7, #4]
- 8003a94: 2b14 cmp r3, #20
- 8003a96: f200 80f0 bhi.w 8003c7a <HAL_TIM_PWM_ConfigChannel+0x212>
- 8003a9a: a201 add r2, pc, #4 ; (adr r2, 8003aa0 <HAL_TIM_PWM_ConfigChannel+0x38>)
- 8003a9c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8003aa0: 08003af5 .word 0x08003af5
- 8003aa4: 08003c7b .word 0x08003c7b
- 8003aa8: 08003c7b .word 0x08003c7b
- 8003aac: 08003c7b .word 0x08003c7b
- 8003ab0: 08003b35 .word 0x08003b35
- 8003ab4: 08003c7b .word 0x08003c7b
- 8003ab8: 08003c7b .word 0x08003c7b
- 8003abc: 08003c7b .word 0x08003c7b
- 8003ac0: 08003b77 .word 0x08003b77
- 8003ac4: 08003c7b .word 0x08003c7b
- 8003ac8: 08003c7b .word 0x08003c7b
- 8003acc: 08003c7b .word 0x08003c7b
- 8003ad0: 08003bb7 .word 0x08003bb7
- 8003ad4: 08003c7b .word 0x08003c7b
- 8003ad8: 08003c7b .word 0x08003c7b
- 8003adc: 08003c7b .word 0x08003c7b
- 8003ae0: 08003bf9 .word 0x08003bf9
- 8003ae4: 08003c7b .word 0x08003c7b
- 8003ae8: 08003c7b .word 0x08003c7b
- 8003aec: 08003c7b .word 0x08003c7b
- 8003af0: 08003c39 .word 0x08003c39
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- 8003af4: 68fb ldr r3, [r7, #12]
- 8003af6: 681b ldr r3, [r3, #0]
- 8003af8: 68b9 ldr r1, [r7, #8]
- 8003afa: 4618 mov r0, r3
- 8003afc: f000 fa4e bl 8003f9c <TIM_OC1_SetConfig>
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 8003b00: 68fb ldr r3, [r7, #12]
- 8003b02: 681b ldr r3, [r3, #0]
- 8003b04: 699a ldr r2, [r3, #24]
- 8003b06: 68fb ldr r3, [r7, #12]
- 8003b08: 681b ldr r3, [r3, #0]
- 8003b0a: f042 0208 orr.w r2, r2, #8
- 8003b0e: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- 8003b10: 68fb ldr r3, [r7, #12]
- 8003b12: 681b ldr r3, [r3, #0]
- 8003b14: 699a ldr r2, [r3, #24]
- 8003b16: 68fb ldr r3, [r7, #12]
- 8003b18: 681b ldr r3, [r3, #0]
- 8003b1a: f022 0204 bic.w r2, r2, #4
- 8003b1e: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- 8003b20: 68fb ldr r3, [r7, #12]
- 8003b22: 681b ldr r3, [r3, #0]
- 8003b24: 6999 ldr r1, [r3, #24]
- 8003b26: 68bb ldr r3, [r7, #8]
- 8003b28: 691a ldr r2, [r3, #16]
- 8003b2a: 68fb ldr r3, [r7, #12]
- 8003b2c: 681b ldr r3, [r3, #0]
- 8003b2e: 430a orrs r2, r1
- 8003b30: 619a str r2, [r3, #24]
- break;
- 8003b32: e0a3 b.n 8003c7c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- 8003b34: 68fb ldr r3, [r7, #12]
- 8003b36: 681b ldr r3, [r3, #0]
- 8003b38: 68b9 ldr r1, [r7, #8]
- 8003b3a: 4618 mov r0, r3
- 8003b3c: f000 faa0 bl 8004080 <TIM_OC2_SetConfig>
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 8003b40: 68fb ldr r3, [r7, #12]
- 8003b42: 681b ldr r3, [r3, #0]
- 8003b44: 699a ldr r2, [r3, #24]
- 8003b46: 68fb ldr r3, [r7, #12]
- 8003b48: 681b ldr r3, [r3, #0]
- 8003b4a: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003b4e: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 8003b50: 68fb ldr r3, [r7, #12]
- 8003b52: 681b ldr r3, [r3, #0]
- 8003b54: 699a ldr r2, [r3, #24]
- 8003b56: 68fb ldr r3, [r7, #12]
- 8003b58: 681b ldr r3, [r3, #0]
- 8003b5a: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003b5e: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- 8003b60: 68fb ldr r3, [r7, #12]
- 8003b62: 681b ldr r3, [r3, #0]
- 8003b64: 6999 ldr r1, [r3, #24]
- 8003b66: 68bb ldr r3, [r7, #8]
- 8003b68: 691b ldr r3, [r3, #16]
- 8003b6a: 021a lsls r2, r3, #8
- 8003b6c: 68fb ldr r3, [r7, #12]
- 8003b6e: 681b ldr r3, [r3, #0]
- 8003b70: 430a orrs r2, r1
- 8003b72: 619a str r2, [r3, #24]
- break;
- 8003b74: e082 b.n 8003c7c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- 8003b76: 68fb ldr r3, [r7, #12]
- 8003b78: 681b ldr r3, [r3, #0]
- 8003b7a: 68b9 ldr r1, [r7, #8]
- 8003b7c: 4618 mov r0, r3
- 8003b7e: f000 faf7 bl 8004170 <TIM_OC3_SetConfig>
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 8003b82: 68fb ldr r3, [r7, #12]
- 8003b84: 681b ldr r3, [r3, #0]
- 8003b86: 69da ldr r2, [r3, #28]
- 8003b88: 68fb ldr r3, [r7, #12]
- 8003b8a: 681b ldr r3, [r3, #0]
- 8003b8c: f042 0208 orr.w r2, r2, #8
- 8003b90: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- 8003b92: 68fb ldr r3, [r7, #12]
- 8003b94: 681b ldr r3, [r3, #0]
- 8003b96: 69da ldr r2, [r3, #28]
- 8003b98: 68fb ldr r3, [r7, #12]
- 8003b9a: 681b ldr r3, [r3, #0]
- 8003b9c: f022 0204 bic.w r2, r2, #4
- 8003ba0: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- 8003ba2: 68fb ldr r3, [r7, #12]
- 8003ba4: 681b ldr r3, [r3, #0]
- 8003ba6: 69d9 ldr r1, [r3, #28]
- 8003ba8: 68bb ldr r3, [r7, #8]
- 8003baa: 691a ldr r2, [r3, #16]
- 8003bac: 68fb ldr r3, [r7, #12]
- 8003bae: 681b ldr r3, [r3, #0]
- 8003bb0: 430a orrs r2, r1
- 8003bb2: 61da str r2, [r3, #28]
- break;
- 8003bb4: e062 b.n 8003c7c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- 8003bb6: 68fb ldr r3, [r7, #12]
- 8003bb8: 681b ldr r3, [r3, #0]
- 8003bba: 68b9 ldr r1, [r7, #8]
- 8003bbc: 4618 mov r0, r3
- 8003bbe: f000 fb4d bl 800425c <TIM_OC4_SetConfig>
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 8003bc2: 68fb ldr r3, [r7, #12]
- 8003bc4: 681b ldr r3, [r3, #0]
- 8003bc6: 69da ldr r2, [r3, #28]
- 8003bc8: 68fb ldr r3, [r7, #12]
- 8003bca: 681b ldr r3, [r3, #0]
- 8003bcc: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003bd0: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 8003bd2: 68fb ldr r3, [r7, #12]
- 8003bd4: 681b ldr r3, [r3, #0]
- 8003bd6: 69da ldr r2, [r3, #28]
- 8003bd8: 68fb ldr r3, [r7, #12]
- 8003bda: 681b ldr r3, [r3, #0]
- 8003bdc: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003be0: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- 8003be2: 68fb ldr r3, [r7, #12]
- 8003be4: 681b ldr r3, [r3, #0]
- 8003be6: 69d9 ldr r1, [r3, #28]
- 8003be8: 68bb ldr r3, [r7, #8]
- 8003bea: 691b ldr r3, [r3, #16]
- 8003bec: 021a lsls r2, r3, #8
- 8003bee: 68fb ldr r3, [r7, #12]
- 8003bf0: 681b ldr r3, [r3, #0]
- 8003bf2: 430a orrs r2, r1
- 8003bf4: 61da str r2, [r3, #28]
- break;
- 8003bf6: e041 b.n 8003c7c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- 8003bf8: 68fb ldr r3, [r7, #12]
- 8003bfa: 681b ldr r3, [r3, #0]
- 8003bfc: 68b9 ldr r1, [r7, #8]
- 8003bfe: 4618 mov r0, r3
- 8003c00: f000 fb84 bl 800430c <TIM_OC5_SetConfig>
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
- 8003c04: 68fb ldr r3, [r7, #12]
- 8003c06: 681b ldr r3, [r3, #0]
- 8003c08: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003c0a: 68fb ldr r3, [r7, #12]
- 8003c0c: 681b ldr r3, [r3, #0]
- 8003c0e: f042 0208 orr.w r2, r2, #8
- 8003c12: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- 8003c14: 68fb ldr r3, [r7, #12]
- 8003c16: 681b ldr r3, [r3, #0]
- 8003c18: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003c1a: 68fb ldr r3, [r7, #12]
- 8003c1c: 681b ldr r3, [r3, #0]
- 8003c1e: f022 0204 bic.w r2, r2, #4
- 8003c22: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- 8003c24: 68fb ldr r3, [r7, #12]
- 8003c26: 681b ldr r3, [r3, #0]
- 8003c28: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003c2a: 68bb ldr r3, [r7, #8]
- 8003c2c: 691a ldr r2, [r3, #16]
- 8003c2e: 68fb ldr r3, [r7, #12]
- 8003c30: 681b ldr r3, [r3, #0]
- 8003c32: 430a orrs r2, r1
- 8003c34: 655a str r2, [r3, #84] ; 0x54
- break;
- 8003c36: e021 b.n 8003c7c <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 6 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- 8003c38: 68fb ldr r3, [r7, #12]
- 8003c3a: 681b ldr r3, [r3, #0]
- 8003c3c: 68b9 ldr r1, [r7, #8]
- 8003c3e: 4618 mov r0, r3
- 8003c40: f000 fbb6 bl 80043b0 <TIM_OC6_SetConfig>
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
- 8003c44: 68fb ldr r3, [r7, #12]
- 8003c46: 681b ldr r3, [r3, #0]
- 8003c48: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003c4a: 68fb ldr r3, [r7, #12]
- 8003c4c: 681b ldr r3, [r3, #0]
- 8003c4e: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003c52: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- 8003c54: 68fb ldr r3, [r7, #12]
- 8003c56: 681b ldr r3, [r3, #0]
- 8003c58: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003c5a: 68fb ldr r3, [r7, #12]
- 8003c5c: 681b ldr r3, [r3, #0]
- 8003c5e: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003c62: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- 8003c64: 68fb ldr r3, [r7, #12]
- 8003c66: 681b ldr r3, [r3, #0]
- 8003c68: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003c6a: 68bb ldr r3, [r7, #8]
- 8003c6c: 691b ldr r3, [r3, #16]
- 8003c6e: 021a lsls r2, r3, #8
- 8003c70: 68fb ldr r3, [r7, #12]
- 8003c72: 681b ldr r3, [r3, #0]
- 8003c74: 430a orrs r2, r1
- 8003c76: 655a str r2, [r3, #84] ; 0x54
- break;
- 8003c78: e000 b.n 8003c7c <HAL_TIM_PWM_ConfigChannel+0x214>
- }
-
- default:
- break;
- 8003c7a: bf00 nop
- }
-
- htim->State = HAL_TIM_STATE_READY;
- 8003c7c: 68fb ldr r3, [r7, #12]
- 8003c7e: 2201 movs r2, #1
- 8003c80: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003c84: 68fb ldr r3, [r7, #12]
- 8003c86: 2200 movs r2, #0
- 8003c88: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003c8c: 2300 movs r3, #0
-}
- 8003c8e: 4618 mov r0, r3
- 8003c90: 3710 adds r7, #16
- 8003c92: 46bd mov sp, r7
- 8003c94: bd80 pop {r7, pc}
- 8003c96: bf00 nop
-
-08003c98 <HAL_TIM_ConfigClockSource>:
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- 8003c98: b580 push {r7, lr}
- 8003c9a: b084 sub sp, #16
- 8003c9c: af00 add r7, sp, #0
- 8003c9e: 6078 str r0, [r7, #4]
- 8003ca0: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003ca2: 687b ldr r3, [r7, #4]
- 8003ca4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8003ca8: 2b01 cmp r3, #1
- 8003caa: d101 bne.n 8003cb0 <HAL_TIM_ConfigClockSource+0x18>
- 8003cac: 2302 movs r3, #2
- 8003cae: e0a6 b.n 8003dfe <HAL_TIM_ConfigClockSource+0x166>
- 8003cb0: 687b ldr r3, [r7, #4]
- 8003cb2: 2201 movs r2, #1
- 8003cb4: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8003cb8: 687b ldr r3, [r7, #4]
- 8003cba: 2202 movs r2, #2
- 8003cbc: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- 8003cc0: 687b ldr r3, [r7, #4]
- 8003cc2: 681b ldr r3, [r3, #0]
- 8003cc4: 689b ldr r3, [r3, #8]
- 8003cc6: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 8003cc8: 68fa ldr r2, [r7, #12]
- 8003cca: 4b4f ldr r3, [pc, #316] ; (8003e08 <HAL_TIM_ConfigClockSource+0x170>)
- 8003ccc: 4013 ands r3, r2
- 8003cce: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8003cd0: 68fb ldr r3, [r7, #12]
- 8003cd2: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8003cd6: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003cd8: 687b ldr r3, [r7, #4]
- 8003cda: 681b ldr r3, [r3, #0]
- 8003cdc: 68fa ldr r2, [r7, #12]
- 8003cde: 609a str r2, [r3, #8]
-
- switch (sClockSourceConfig->ClockSource)
- 8003ce0: 683b ldr r3, [r7, #0]
- 8003ce2: 681b ldr r3, [r3, #0]
- 8003ce4: 2b40 cmp r3, #64 ; 0x40
- 8003ce6: d067 beq.n 8003db8 <HAL_TIM_ConfigClockSource+0x120>
- 8003ce8: 2b40 cmp r3, #64 ; 0x40
- 8003cea: d80b bhi.n 8003d04 <HAL_TIM_ConfigClockSource+0x6c>
- 8003cec: 2b10 cmp r3, #16
- 8003cee: d073 beq.n 8003dd8 <HAL_TIM_ConfigClockSource+0x140>
- 8003cf0: 2b10 cmp r3, #16
- 8003cf2: d802 bhi.n 8003cfa <HAL_TIM_ConfigClockSource+0x62>
- 8003cf4: 2b00 cmp r3, #0
- 8003cf6: d06f beq.n 8003dd8 <HAL_TIM_ConfigClockSource+0x140>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- break;
- 8003cf8: e078 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003cfa: 2b20 cmp r3, #32
- 8003cfc: d06c beq.n 8003dd8 <HAL_TIM_ConfigClockSource+0x140>
- 8003cfe: 2b30 cmp r3, #48 ; 0x30
- 8003d00: d06a beq.n 8003dd8 <HAL_TIM_ConfigClockSource+0x140>
- break;
- 8003d02: e073 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003d04: 2b70 cmp r3, #112 ; 0x70
- 8003d06: d00d beq.n 8003d24 <HAL_TIM_ConfigClockSource+0x8c>
- 8003d08: 2b70 cmp r3, #112 ; 0x70
- 8003d0a: d804 bhi.n 8003d16 <HAL_TIM_ConfigClockSource+0x7e>
- 8003d0c: 2b50 cmp r3, #80 ; 0x50
- 8003d0e: d033 beq.n 8003d78 <HAL_TIM_ConfigClockSource+0xe0>
- 8003d10: 2b60 cmp r3, #96 ; 0x60
- 8003d12: d041 beq.n 8003d98 <HAL_TIM_ConfigClockSource+0x100>
- break;
- 8003d14: e06a b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003d16: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8003d1a: d066 beq.n 8003dea <HAL_TIM_ConfigClockSource+0x152>
- 8003d1c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8003d20: d017 beq.n 8003d52 <HAL_TIM_ConfigClockSource+0xba>
- break;
- 8003d22: e063 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003d24: 687b ldr r3, [r7, #4]
- 8003d26: 6818 ldr r0, [r3, #0]
- 8003d28: 683b ldr r3, [r7, #0]
- 8003d2a: 6899 ldr r1, [r3, #8]
- 8003d2c: 683b ldr r3, [r7, #0]
- 8003d2e: 685a ldr r2, [r3, #4]
- 8003d30: 683b ldr r3, [r7, #0]
- 8003d32: 68db ldr r3, [r3, #12]
- 8003d34: f000 fc0a bl 800454c <TIM_ETR_SetConfig>
- tmpsmcr = htim->Instance->SMCR;
- 8003d38: 687b ldr r3, [r7, #4]
- 8003d3a: 681b ldr r3, [r3, #0]
- 8003d3c: 689b ldr r3, [r3, #8]
- 8003d3e: 60fb str r3, [r7, #12]
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8003d40: 68fb ldr r3, [r7, #12]
- 8003d42: f043 0377 orr.w r3, r3, #119 ; 0x77
- 8003d46: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003d48: 687b ldr r3, [r7, #4]
- 8003d4a: 681b ldr r3, [r3, #0]
- 8003d4c: 68fa ldr r2, [r7, #12]
- 8003d4e: 609a str r2, [r3, #8]
- break;
- 8003d50: e04c b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003d52: 687b ldr r3, [r7, #4]
- 8003d54: 6818 ldr r0, [r3, #0]
- 8003d56: 683b ldr r3, [r7, #0]
- 8003d58: 6899 ldr r1, [r3, #8]
- 8003d5a: 683b ldr r3, [r7, #0]
- 8003d5c: 685a ldr r2, [r3, #4]
- 8003d5e: 683b ldr r3, [r7, #0]
- 8003d60: 68db ldr r3, [r3, #12]
- 8003d62: f000 fbf3 bl 800454c <TIM_ETR_SetConfig>
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- 8003d66: 687b ldr r3, [r7, #4]
- 8003d68: 681b ldr r3, [r3, #0]
- 8003d6a: 689a ldr r2, [r3, #8]
- 8003d6c: 687b ldr r3, [r7, #4]
- 8003d6e: 681b ldr r3, [r3, #0]
- 8003d70: f442 4280 orr.w r2, r2, #16384 ; 0x4000
- 8003d74: 609a str r2, [r3, #8]
- break;
- 8003d76: e039 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003d78: 687b ldr r3, [r7, #4]
- 8003d7a: 6818 ldr r0, [r3, #0]
- 8003d7c: 683b ldr r3, [r7, #0]
- 8003d7e: 6859 ldr r1, [r3, #4]
- 8003d80: 683b ldr r3, [r7, #0]
- 8003d82: 68db ldr r3, [r3, #12]
- 8003d84: 461a mov r2, r3
- 8003d86: f000 fb67 bl 8004458 <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 8003d8a: 687b ldr r3, [r7, #4]
- 8003d8c: 681b ldr r3, [r3, #0]
- 8003d8e: 2150 movs r1, #80 ; 0x50
- 8003d90: 4618 mov r0, r3
- 8003d92: f000 fbc0 bl 8004516 <TIM_ITRx_SetConfig>
- break;
- 8003d96: e029 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI2_ConfigInputStage(htim->Instance,
- 8003d98: 687b ldr r3, [r7, #4]
- 8003d9a: 6818 ldr r0, [r3, #0]
- 8003d9c: 683b ldr r3, [r7, #0]
- 8003d9e: 6859 ldr r1, [r3, #4]
- 8003da0: 683b ldr r3, [r7, #0]
- 8003da2: 68db ldr r3, [r3, #12]
- 8003da4: 461a mov r2, r3
- 8003da6: f000 fb86 bl 80044b6 <TIM_TI2_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 8003daa: 687b ldr r3, [r7, #4]
- 8003dac: 681b ldr r3, [r3, #0]
- 8003dae: 2160 movs r1, #96 ; 0x60
- 8003db0: 4618 mov r0, r3
- 8003db2: f000 fbb0 bl 8004516 <TIM_ITRx_SetConfig>
- break;
- 8003db6: e019 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003db8: 687b ldr r3, [r7, #4]
- 8003dba: 6818 ldr r0, [r3, #0]
- 8003dbc: 683b ldr r3, [r7, #0]
- 8003dbe: 6859 ldr r1, [r3, #4]
- 8003dc0: 683b ldr r3, [r7, #0]
- 8003dc2: 68db ldr r3, [r3, #12]
- 8003dc4: 461a mov r2, r3
- 8003dc6: f000 fb47 bl 8004458 <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 8003dca: 687b ldr r3, [r7, #4]
- 8003dcc: 681b ldr r3, [r3, #0]
- 8003dce: 2140 movs r1, #64 ; 0x40
- 8003dd0: 4618 mov r0, r3
- 8003dd2: f000 fba0 bl 8004516 <TIM_ITRx_SetConfig>
- break;
- 8003dd6: e009 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 8003dd8: 687b ldr r3, [r7, #4]
- 8003dda: 681a ldr r2, [r3, #0]
- 8003ddc: 683b ldr r3, [r7, #0]
- 8003dde: 681b ldr r3, [r3, #0]
- 8003de0: 4619 mov r1, r3
- 8003de2: 4610 mov r0, r2
- 8003de4: f000 fb97 bl 8004516 <TIM_ITRx_SetConfig>
- break;
- 8003de8: e000 b.n 8003dec <HAL_TIM_ConfigClockSource+0x154>
- break;
- 8003dea: bf00 nop
- }
- htim->State = HAL_TIM_STATE_READY;
- 8003dec: 687b ldr r3, [r7, #4]
- 8003dee: 2201 movs r2, #1
- 8003df0: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003df4: 687b ldr r3, [r7, #4]
- 8003df6: 2200 movs r2, #0
- 8003df8: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003dfc: 2300 movs r3, #0
-}
- 8003dfe: 4618 mov r0, r3
- 8003e00: 3710 adds r7, #16
- 8003e02: 46bd mov sp, r7
- 8003e04: bd80 pop {r7, pc}
- 8003e06: bf00 nop
- 8003e08: fffeff88 .word 0xfffeff88
-
-08003e0c <HAL_TIM_OC_DelayElapsedCallback>:
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- 8003e0c: b480 push {r7}
- 8003e0e: b083 sub sp, #12
- 8003e10: af00 add r7, sp, #0
- 8003e12: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
- 8003e14: bf00 nop
- 8003e16: 370c adds r7, #12
- 8003e18: 46bd mov sp, r7
- 8003e1a: f85d 7b04 ldr.w r7, [sp], #4
- 8003e1e: 4770 bx lr
-
-08003e20 <HAL_TIM_IC_CaptureCallback>:
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- 8003e20: b480 push {r7}
- 8003e22: b083 sub sp, #12
- 8003e24: af00 add r7, sp, #0
- 8003e26: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
- 8003e28: bf00 nop
- 8003e2a: 370c adds r7, #12
- 8003e2c: 46bd mov sp, r7
- 8003e2e: f85d 7b04 ldr.w r7, [sp], #4
- 8003e32: 4770 bx lr
-
-08003e34 <HAL_TIM_PWM_PulseFinishedCallback>:
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- 8003e34: b480 push {r7}
- 8003e36: b083 sub sp, #12
- 8003e38: af00 add r7, sp, #0
- 8003e3a: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
- 8003e3c: bf00 nop
- 8003e3e: 370c adds r7, #12
- 8003e40: 46bd mov sp, r7
- 8003e42: f85d 7b04 ldr.w r7, [sp], #4
- 8003e46: 4770 bx lr
-
-08003e48 <HAL_TIM_TriggerCallback>:
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- 8003e48: b480 push {r7}
- 8003e4a: b083 sub sp, #12
- 8003e4c: af00 add r7, sp, #0
- 8003e4e: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
- 8003e50: bf00 nop
- 8003e52: 370c adds r7, #12
- 8003e54: 46bd mov sp, r7
- 8003e56: f85d 7b04 ldr.w r7, [sp], #4
- 8003e5a: 4770 bx lr
-
-08003e5c <TIM_Base_SetConfig>:
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- 8003e5c: b480 push {r7}
- 8003e5e: b085 sub sp, #20
- 8003e60: af00 add r7, sp, #0
- 8003e62: 6078 str r0, [r7, #4]
- 8003e64: 6039 str r1, [r7, #0]
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
- 8003e66: 687b ldr r3, [r7, #4]
- 8003e68: 681b ldr r3, [r3, #0]
- 8003e6a: 60fb str r3, [r7, #12]
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8003e6c: 687b ldr r3, [r7, #4]
- 8003e6e: 4a40 ldr r2, [pc, #256] ; (8003f70 <TIM_Base_SetConfig+0x114>)
- 8003e70: 4293 cmp r3, r2
- 8003e72: d013 beq.n 8003e9c <TIM_Base_SetConfig+0x40>
- 8003e74: 687b ldr r3, [r7, #4]
- 8003e76: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003e7a: d00f beq.n 8003e9c <TIM_Base_SetConfig+0x40>
- 8003e7c: 687b ldr r3, [r7, #4]
- 8003e7e: 4a3d ldr r2, [pc, #244] ; (8003f74 <TIM_Base_SetConfig+0x118>)
- 8003e80: 4293 cmp r3, r2
- 8003e82: d00b beq.n 8003e9c <TIM_Base_SetConfig+0x40>
- 8003e84: 687b ldr r3, [r7, #4]
- 8003e86: 4a3c ldr r2, [pc, #240] ; (8003f78 <TIM_Base_SetConfig+0x11c>)
- 8003e88: 4293 cmp r3, r2
- 8003e8a: d007 beq.n 8003e9c <TIM_Base_SetConfig+0x40>
- 8003e8c: 687b ldr r3, [r7, #4]
- 8003e8e: 4a3b ldr r2, [pc, #236] ; (8003f7c <TIM_Base_SetConfig+0x120>)
- 8003e90: 4293 cmp r3, r2
- 8003e92: d003 beq.n 8003e9c <TIM_Base_SetConfig+0x40>
- 8003e94: 687b ldr r3, [r7, #4]
- 8003e96: 4a3a ldr r2, [pc, #232] ; (8003f80 <TIM_Base_SetConfig+0x124>)
- 8003e98: 4293 cmp r3, r2
- 8003e9a: d108 bne.n 8003eae <TIM_Base_SetConfig+0x52>
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 8003e9c: 68fb ldr r3, [r7, #12]
- 8003e9e: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8003ea2: 60fb str r3, [r7, #12]
- tmpcr1 |= Structure->CounterMode;
- 8003ea4: 683b ldr r3, [r7, #0]
- 8003ea6: 685b ldr r3, [r3, #4]
- 8003ea8: 68fa ldr r2, [r7, #12]
- 8003eaa: 4313 orrs r3, r2
- 8003eac: 60fb str r3, [r7, #12]
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 8003eae: 687b ldr r3, [r7, #4]
- 8003eb0: 4a2f ldr r2, [pc, #188] ; (8003f70 <TIM_Base_SetConfig+0x114>)
- 8003eb2: 4293 cmp r3, r2
- 8003eb4: d02b beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003eb6: 687b ldr r3, [r7, #4]
- 8003eb8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003ebc: d027 beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003ebe: 687b ldr r3, [r7, #4]
- 8003ec0: 4a2c ldr r2, [pc, #176] ; (8003f74 <TIM_Base_SetConfig+0x118>)
- 8003ec2: 4293 cmp r3, r2
- 8003ec4: d023 beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003ec6: 687b ldr r3, [r7, #4]
- 8003ec8: 4a2b ldr r2, [pc, #172] ; (8003f78 <TIM_Base_SetConfig+0x11c>)
- 8003eca: 4293 cmp r3, r2
- 8003ecc: d01f beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003ece: 687b ldr r3, [r7, #4]
- 8003ed0: 4a2a ldr r2, [pc, #168] ; (8003f7c <TIM_Base_SetConfig+0x120>)
- 8003ed2: 4293 cmp r3, r2
- 8003ed4: d01b beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003ed6: 687b ldr r3, [r7, #4]
- 8003ed8: 4a29 ldr r2, [pc, #164] ; (8003f80 <TIM_Base_SetConfig+0x124>)
- 8003eda: 4293 cmp r3, r2
- 8003edc: d017 beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003ede: 687b ldr r3, [r7, #4]
- 8003ee0: 4a28 ldr r2, [pc, #160] ; (8003f84 <TIM_Base_SetConfig+0x128>)
- 8003ee2: 4293 cmp r3, r2
- 8003ee4: d013 beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003ee6: 687b ldr r3, [r7, #4]
- 8003ee8: 4a27 ldr r2, [pc, #156] ; (8003f88 <TIM_Base_SetConfig+0x12c>)
- 8003eea: 4293 cmp r3, r2
- 8003eec: d00f beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003eee: 687b ldr r3, [r7, #4]
- 8003ef0: 4a26 ldr r2, [pc, #152] ; (8003f8c <TIM_Base_SetConfig+0x130>)
- 8003ef2: 4293 cmp r3, r2
- 8003ef4: d00b beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003ef6: 687b ldr r3, [r7, #4]
- 8003ef8: 4a25 ldr r2, [pc, #148] ; (8003f90 <TIM_Base_SetConfig+0x134>)
- 8003efa: 4293 cmp r3, r2
- 8003efc: d007 beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003efe: 687b ldr r3, [r7, #4]
- 8003f00: 4a24 ldr r2, [pc, #144] ; (8003f94 <TIM_Base_SetConfig+0x138>)
- 8003f02: 4293 cmp r3, r2
- 8003f04: d003 beq.n 8003f0e <TIM_Base_SetConfig+0xb2>
- 8003f06: 687b ldr r3, [r7, #4]
- 8003f08: 4a23 ldr r2, [pc, #140] ; (8003f98 <TIM_Base_SetConfig+0x13c>)
- 8003f0a: 4293 cmp r3, r2
- 8003f0c: d108 bne.n 8003f20 <TIM_Base_SetConfig+0xc4>
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- 8003f0e: 68fb ldr r3, [r7, #12]
- 8003f10: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003f14: 60fb str r3, [r7, #12]
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 8003f16: 683b ldr r3, [r7, #0]
- 8003f18: 68db ldr r3, [r3, #12]
- 8003f1a: 68fa ldr r2, [r7, #12]
- 8003f1c: 4313 orrs r3, r2
- 8003f1e: 60fb str r3, [r7, #12]
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8003f20: 68fb ldr r3, [r7, #12]
- 8003f22: f023 0280 bic.w r2, r3, #128 ; 0x80
- 8003f26: 683b ldr r3, [r7, #0]
- 8003f28: 695b ldr r3, [r3, #20]
- 8003f2a: 4313 orrs r3, r2
- 8003f2c: 60fb str r3, [r7, #12]
-
- TIMx->CR1 = tmpcr1;
- 8003f2e: 687b ldr r3, [r7, #4]
- 8003f30: 68fa ldr r2, [r7, #12]
- 8003f32: 601a str r2, [r3, #0]
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
- 8003f34: 683b ldr r3, [r7, #0]
- 8003f36: 689a ldr r2, [r3, #8]
- 8003f38: 687b ldr r3, [r7, #4]
- 8003f3a: 62da str r2, [r3, #44] ; 0x2c
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
- 8003f3c: 683b ldr r3, [r7, #0]
- 8003f3e: 681a ldr r2, [r3, #0]
- 8003f40: 687b ldr r3, [r7, #4]
- 8003f42: 629a str r2, [r3, #40] ; 0x28
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8003f44: 687b ldr r3, [r7, #4]
- 8003f46: 4a0a ldr r2, [pc, #40] ; (8003f70 <TIM_Base_SetConfig+0x114>)
- 8003f48: 4293 cmp r3, r2
- 8003f4a: d003 beq.n 8003f54 <TIM_Base_SetConfig+0xf8>
- 8003f4c: 687b ldr r3, [r7, #4]
- 8003f4e: 4a0c ldr r2, [pc, #48] ; (8003f80 <TIM_Base_SetConfig+0x124>)
- 8003f50: 4293 cmp r3, r2
- 8003f52: d103 bne.n 8003f5c <TIM_Base_SetConfig+0x100>
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- 8003f54: 683b ldr r3, [r7, #0]
- 8003f56: 691a ldr r2, [r3, #16]
- 8003f58: 687b ldr r3, [r7, #4]
- 8003f5a: 631a str r2, [r3, #48] ; 0x30
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
- 8003f5c: 687b ldr r3, [r7, #4]
- 8003f5e: 2201 movs r2, #1
- 8003f60: 615a str r2, [r3, #20]
-}
- 8003f62: bf00 nop
- 8003f64: 3714 adds r7, #20
- 8003f66: 46bd mov sp, r7
- 8003f68: f85d 7b04 ldr.w r7, [sp], #4
- 8003f6c: 4770 bx lr
- 8003f6e: bf00 nop
- 8003f70: 40010000 .word 0x40010000
- 8003f74: 40000400 .word 0x40000400
- 8003f78: 40000800 .word 0x40000800
- 8003f7c: 40000c00 .word 0x40000c00
- 8003f80: 40010400 .word 0x40010400
- 8003f84: 40014000 .word 0x40014000
- 8003f88: 40014400 .word 0x40014400
- 8003f8c: 40014800 .word 0x40014800
- 8003f90: 40001800 .word 0x40001800
- 8003f94: 40001c00 .word 0x40001c00
- 8003f98: 40002000 .word 0x40002000
-
-08003f9c <TIM_OC1_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003f9c: b480 push {r7}
- 8003f9e: b087 sub sp, #28
- 8003fa0: af00 add r7, sp, #0
- 8003fa2: 6078 str r0, [r7, #4]
- 8003fa4: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 8003fa6: 687b ldr r3, [r7, #4]
- 8003fa8: 6a1b ldr r3, [r3, #32]
- 8003faa: f023 0201 bic.w r2, r3, #1
- 8003fae: 687b ldr r3, [r7, #4]
- 8003fb0: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8003fb2: 687b ldr r3, [r7, #4]
- 8003fb4: 6a1b ldr r3, [r3, #32]
- 8003fb6: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8003fb8: 687b ldr r3, [r7, #4]
- 8003fba: 685b ldr r3, [r3, #4]
- 8003fbc: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 8003fbe: 687b ldr r3, [r7, #4]
- 8003fc0: 699b ldr r3, [r3, #24]
- 8003fc2: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- 8003fc4: 68fa ldr r2, [r7, #12]
- 8003fc6: 4b2b ldr r3, [pc, #172] ; (8004074 <TIM_OC1_SetConfig+0xd8>)
- 8003fc8: 4013 ands r3, r2
- 8003fca: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- 8003fcc: 68fb ldr r3, [r7, #12]
- 8003fce: f023 0303 bic.w r3, r3, #3
- 8003fd2: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8003fd4: 683b ldr r3, [r7, #0]
- 8003fd6: 681b ldr r3, [r3, #0]
- 8003fd8: 68fa ldr r2, [r7, #12]
- 8003fda: 4313 orrs r3, r2
- 8003fdc: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- 8003fde: 697b ldr r3, [r7, #20]
- 8003fe0: f023 0302 bic.w r3, r3, #2
- 8003fe4: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
- 8003fe6: 683b ldr r3, [r7, #0]
- 8003fe8: 689b ldr r3, [r3, #8]
- 8003fea: 697a ldr r2, [r7, #20]
- 8003fec: 4313 orrs r3, r2
- 8003fee: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- 8003ff0: 687b ldr r3, [r7, #4]
- 8003ff2: 4a21 ldr r2, [pc, #132] ; (8004078 <TIM_OC1_SetConfig+0xdc>)
- 8003ff4: 4293 cmp r3, r2
- 8003ff6: d003 beq.n 8004000 <TIM_OC1_SetConfig+0x64>
- 8003ff8: 687b ldr r3, [r7, #4]
- 8003ffa: 4a20 ldr r2, [pc, #128] ; (800407c <TIM_OC1_SetConfig+0xe0>)
- 8003ffc: 4293 cmp r3, r2
- 8003ffe: d10c bne.n 800401a <TIM_OC1_SetConfig+0x7e>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- 8004000: 697b ldr r3, [r7, #20]
- 8004002: f023 0308 bic.w r3, r3, #8
- 8004006: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- 8004008: 683b ldr r3, [r7, #0]
- 800400a: 68db ldr r3, [r3, #12]
- 800400c: 697a ldr r2, [r7, #20]
- 800400e: 4313 orrs r3, r2
- 8004010: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- 8004012: 697b ldr r3, [r7, #20]
- 8004014: f023 0304 bic.w r3, r3, #4
- 8004018: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 800401a: 687b ldr r3, [r7, #4]
- 800401c: 4a16 ldr r2, [pc, #88] ; (8004078 <TIM_OC1_SetConfig+0xdc>)
- 800401e: 4293 cmp r3, r2
- 8004020: d003 beq.n 800402a <TIM_OC1_SetConfig+0x8e>
- 8004022: 687b ldr r3, [r7, #4]
- 8004024: 4a15 ldr r2, [pc, #84] ; (800407c <TIM_OC1_SetConfig+0xe0>)
- 8004026: 4293 cmp r3, r2
- 8004028: d111 bne.n 800404e <TIM_OC1_SetConfig+0xb2>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- 800402a: 693b ldr r3, [r7, #16]
- 800402c: f423 7380 bic.w r3, r3, #256 ; 0x100
- 8004030: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS1N;
- 8004032: 693b ldr r3, [r7, #16]
- 8004034: f423 7300 bic.w r3, r3, #512 ; 0x200
- 8004038: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- 800403a: 683b ldr r3, [r7, #0]
- 800403c: 695b ldr r3, [r3, #20]
- 800403e: 693a ldr r2, [r7, #16]
- 8004040: 4313 orrs r3, r2
- 8004042: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- 8004044: 683b ldr r3, [r7, #0]
- 8004046: 699b ldr r3, [r3, #24]
- 8004048: 693a ldr r2, [r7, #16]
- 800404a: 4313 orrs r3, r2
- 800404c: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 800404e: 687b ldr r3, [r7, #4]
- 8004050: 693a ldr r2, [r7, #16]
- 8004052: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 8004054: 687b ldr r3, [r7, #4]
- 8004056: 68fa ldr r2, [r7, #12]
- 8004058: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
- 800405a: 683b ldr r3, [r7, #0]
- 800405c: 685a ldr r2, [r3, #4]
- 800405e: 687b ldr r3, [r7, #4]
- 8004060: 635a str r2, [r3, #52] ; 0x34
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004062: 687b ldr r3, [r7, #4]
- 8004064: 697a ldr r2, [r7, #20]
- 8004066: 621a str r2, [r3, #32]
-}
- 8004068: bf00 nop
- 800406a: 371c adds r7, #28
- 800406c: 46bd mov sp, r7
- 800406e: f85d 7b04 ldr.w r7, [sp], #4
- 8004072: 4770 bx lr
- 8004074: fffeff8f .word 0xfffeff8f
- 8004078: 40010000 .word 0x40010000
- 800407c: 40010400 .word 0x40010400
-
-08004080 <TIM_OC2_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8004080: b480 push {r7}
- 8004082: b087 sub sp, #28
- 8004084: af00 add r7, sp, #0
- 8004086: 6078 str r0, [r7, #4]
- 8004088: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 800408a: 687b ldr r3, [r7, #4]
- 800408c: 6a1b ldr r3, [r3, #32]
- 800408e: f023 0210 bic.w r2, r3, #16
- 8004092: 687b ldr r3, [r7, #4]
- 8004094: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004096: 687b ldr r3, [r7, #4]
- 8004098: 6a1b ldr r3, [r3, #32]
- 800409a: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 800409c: 687b ldr r3, [r7, #4]
- 800409e: 685b ldr r3, [r3, #4]
- 80040a0: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 80040a2: 687b ldr r3, [r7, #4]
- 80040a4: 699b ldr r3, [r3, #24]
- 80040a6: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- 80040a8: 68fa ldr r2, [r7, #12]
- 80040aa: 4b2e ldr r3, [pc, #184] ; (8004164 <TIM_OC2_SetConfig+0xe4>)
- 80040ac: 4013 ands r3, r2
- 80040ae: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC2S;
- 80040b0: 68fb ldr r3, [r7, #12]
- 80040b2: f423 7340 bic.w r3, r3, #768 ; 0x300
- 80040b6: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 80040b8: 683b ldr r3, [r7, #0]
- 80040ba: 681b ldr r3, [r3, #0]
- 80040bc: 021b lsls r3, r3, #8
- 80040be: 68fa ldr r2, [r7, #12]
- 80040c0: 4313 orrs r3, r2
- 80040c2: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- 80040c4: 697b ldr r3, [r7, #20]
- 80040c6: f023 0320 bic.w r3, r3, #32
- 80040ca: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
- 80040cc: 683b ldr r3, [r7, #0]
- 80040ce: 689b ldr r3, [r3, #8]
- 80040d0: 011b lsls r3, r3, #4
- 80040d2: 697a ldr r2, [r7, #20]
- 80040d4: 4313 orrs r3, r2
- 80040d6: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- 80040d8: 687b ldr r3, [r7, #4]
- 80040da: 4a23 ldr r2, [pc, #140] ; (8004168 <TIM_OC2_SetConfig+0xe8>)
- 80040dc: 4293 cmp r3, r2
- 80040de: d003 beq.n 80040e8 <TIM_OC2_SetConfig+0x68>
- 80040e0: 687b ldr r3, [r7, #4]
- 80040e2: 4a22 ldr r2, [pc, #136] ; (800416c <TIM_OC2_SetConfig+0xec>)
- 80040e4: 4293 cmp r3, r2
- 80040e6: d10d bne.n 8004104 <TIM_OC2_SetConfig+0x84>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- 80040e8: 697b ldr r3, [r7, #20]
- 80040ea: f023 0380 bic.w r3, r3, #128 ; 0x80
- 80040ee: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- 80040f0: 683b ldr r3, [r7, #0]
- 80040f2: 68db ldr r3, [r3, #12]
- 80040f4: 011b lsls r3, r3, #4
- 80040f6: 697a ldr r2, [r7, #20]
- 80040f8: 4313 orrs r3, r2
- 80040fa: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
- 80040fc: 697b ldr r3, [r7, #20]
- 80040fe: f023 0340 bic.w r3, r3, #64 ; 0x40
- 8004102: 617b str r3, [r7, #20]
-
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8004104: 687b ldr r3, [r7, #4]
- 8004106: 4a18 ldr r2, [pc, #96] ; (8004168 <TIM_OC2_SetConfig+0xe8>)
- 8004108: 4293 cmp r3, r2
- 800410a: d003 beq.n 8004114 <TIM_OC2_SetConfig+0x94>
- 800410c: 687b ldr r3, [r7, #4]
- 800410e: 4a17 ldr r2, [pc, #92] ; (800416c <TIM_OC2_SetConfig+0xec>)
- 8004110: 4293 cmp r3, r2
- 8004112: d113 bne.n 800413c <TIM_OC2_SetConfig+0xbc>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- 8004114: 693b ldr r3, [r7, #16]
- 8004116: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 800411a: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS2N;
- 800411c: 693b ldr r3, [r7, #16]
- 800411e: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8004122: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- 8004124: 683b ldr r3, [r7, #0]
- 8004126: 695b ldr r3, [r3, #20]
- 8004128: 009b lsls r3, r3, #2
- 800412a: 693a ldr r2, [r7, #16]
- 800412c: 4313 orrs r3, r2
- 800412e: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- 8004130: 683b ldr r3, [r7, #0]
- 8004132: 699b ldr r3, [r3, #24]
- 8004134: 009b lsls r3, r3, #2
- 8004136: 693a ldr r2, [r7, #16]
- 8004138: 4313 orrs r3, r2
- 800413a: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 800413c: 687b ldr r3, [r7, #4]
- 800413e: 693a ldr r2, [r7, #16]
- 8004140: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 8004142: 687b ldr r3, [r7, #4]
- 8004144: 68fa ldr r2, [r7, #12]
- 8004146: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
- 8004148: 683b ldr r3, [r7, #0]
- 800414a: 685a ldr r2, [r3, #4]
- 800414c: 687b ldr r3, [r7, #4]
- 800414e: 639a str r2, [r3, #56] ; 0x38
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004150: 687b ldr r3, [r7, #4]
- 8004152: 697a ldr r2, [r7, #20]
- 8004154: 621a str r2, [r3, #32]
-}
- 8004156: bf00 nop
- 8004158: 371c adds r7, #28
- 800415a: 46bd mov sp, r7
- 800415c: f85d 7b04 ldr.w r7, [sp], #4
- 8004160: 4770 bx lr
- 8004162: bf00 nop
- 8004164: feff8fff .word 0xfeff8fff
- 8004168: 40010000 .word 0x40010000
- 800416c: 40010400 .word 0x40010400
-
-08004170 <TIM_OC3_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8004170: b480 push {r7}
- 8004172: b087 sub sp, #28
- 8004174: af00 add r7, sp, #0
- 8004176: 6078 str r0, [r7, #4]
- 8004178: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- 800417a: 687b ldr r3, [r7, #4]
- 800417c: 6a1b ldr r3, [r3, #32]
- 800417e: f423 7280 bic.w r2, r3, #256 ; 0x100
- 8004182: 687b ldr r3, [r7, #4]
- 8004184: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004186: 687b ldr r3, [r7, #4]
- 8004188: 6a1b ldr r3, [r3, #32]
- 800418a: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 800418c: 687b ldr r3, [r7, #4]
- 800418e: 685b ldr r3, [r3, #4]
- 8004190: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 8004192: 687b ldr r3, [r7, #4]
- 8004194: 69db ldr r3, [r3, #28]
- 8004196: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- 8004198: 68fa ldr r2, [r7, #12]
- 800419a: 4b2d ldr r3, [pc, #180] ; (8004250 <TIM_OC3_SetConfig+0xe0>)
- 800419c: 4013 ands r3, r2
- 800419e: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- 80041a0: 68fb ldr r3, [r7, #12]
- 80041a2: f023 0303 bic.w r3, r3, #3
- 80041a6: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 80041a8: 683b ldr r3, [r7, #0]
- 80041aa: 681b ldr r3, [r3, #0]
- 80041ac: 68fa ldr r2, [r7, #12]
- 80041ae: 4313 orrs r3, r2
- 80041b0: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- 80041b2: 697b ldr r3, [r7, #20]
- 80041b4: f423 7300 bic.w r3, r3, #512 ; 0x200
- 80041b8: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
- 80041ba: 683b ldr r3, [r7, #0]
- 80041bc: 689b ldr r3, [r3, #8]
- 80041be: 021b lsls r3, r3, #8
- 80041c0: 697a ldr r2, [r7, #20]
- 80041c2: 4313 orrs r3, r2
- 80041c4: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- 80041c6: 687b ldr r3, [r7, #4]
- 80041c8: 4a22 ldr r2, [pc, #136] ; (8004254 <TIM_OC3_SetConfig+0xe4>)
- 80041ca: 4293 cmp r3, r2
- 80041cc: d003 beq.n 80041d6 <TIM_OC3_SetConfig+0x66>
- 80041ce: 687b ldr r3, [r7, #4]
- 80041d0: 4a21 ldr r2, [pc, #132] ; (8004258 <TIM_OC3_SetConfig+0xe8>)
- 80041d2: 4293 cmp r3, r2
- 80041d4: d10d bne.n 80041f2 <TIM_OC3_SetConfig+0x82>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- 80041d6: 697b ldr r3, [r7, #20]
- 80041d8: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 80041dc: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- 80041de: 683b ldr r3, [r7, #0]
- 80041e0: 68db ldr r3, [r3, #12]
- 80041e2: 021b lsls r3, r3, #8
- 80041e4: 697a ldr r2, [r7, #20]
- 80041e6: 4313 orrs r3, r2
- 80041e8: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- 80041ea: 697b ldr r3, [r7, #20]
- 80041ec: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 80041f0: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80041f2: 687b ldr r3, [r7, #4]
- 80041f4: 4a17 ldr r2, [pc, #92] ; (8004254 <TIM_OC3_SetConfig+0xe4>)
- 80041f6: 4293 cmp r3, r2
- 80041f8: d003 beq.n 8004202 <TIM_OC3_SetConfig+0x92>
- 80041fa: 687b ldr r3, [r7, #4]
- 80041fc: 4a16 ldr r2, [pc, #88] ; (8004258 <TIM_OC3_SetConfig+0xe8>)
- 80041fe: 4293 cmp r3, r2
- 8004200: d113 bne.n 800422a <TIM_OC3_SetConfig+0xba>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- 8004202: 693b ldr r3, [r7, #16]
- 8004204: f423 5380 bic.w r3, r3, #4096 ; 0x1000
- 8004208: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS3N;
- 800420a: 693b ldr r3, [r7, #16]
- 800420c: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8004210: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- 8004212: 683b ldr r3, [r7, #0]
- 8004214: 695b ldr r3, [r3, #20]
- 8004216: 011b lsls r3, r3, #4
- 8004218: 693a ldr r2, [r7, #16]
- 800421a: 4313 orrs r3, r2
- 800421c: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- 800421e: 683b ldr r3, [r7, #0]
- 8004220: 699b ldr r3, [r3, #24]
- 8004222: 011b lsls r3, r3, #4
- 8004224: 693a ldr r2, [r7, #16]
- 8004226: 4313 orrs r3, r2
- 8004228: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 800422a: 687b ldr r3, [r7, #4]
- 800422c: 693a ldr r2, [r7, #16]
- 800422e: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 8004230: 687b ldr r3, [r7, #4]
- 8004232: 68fa ldr r2, [r7, #12]
- 8004234: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
- 8004236: 683b ldr r3, [r7, #0]
- 8004238: 685a ldr r2, [r3, #4]
- 800423a: 687b ldr r3, [r7, #4]
- 800423c: 63da str r2, [r3, #60] ; 0x3c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 800423e: 687b ldr r3, [r7, #4]
- 8004240: 697a ldr r2, [r7, #20]
- 8004242: 621a str r2, [r3, #32]
-}
- 8004244: bf00 nop
- 8004246: 371c adds r7, #28
- 8004248: 46bd mov sp, r7
- 800424a: f85d 7b04 ldr.w r7, [sp], #4
- 800424e: 4770 bx lr
- 8004250: fffeff8f .word 0xfffeff8f
- 8004254: 40010000 .word 0x40010000
- 8004258: 40010400 .word 0x40010400
-
-0800425c <TIM_OC4_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 800425c: b480 push {r7}
- 800425e: b087 sub sp, #28
- 8004260: af00 add r7, sp, #0
- 8004262: 6078 str r0, [r7, #4]
- 8004264: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- 8004266: 687b ldr r3, [r7, #4]
- 8004268: 6a1b ldr r3, [r3, #32]
- 800426a: f423 5280 bic.w r2, r3, #4096 ; 0x1000
- 800426e: 687b ldr r3, [r7, #4]
- 8004270: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004272: 687b ldr r3, [r7, #4]
- 8004274: 6a1b ldr r3, [r3, #32]
- 8004276: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004278: 687b ldr r3, [r7, #4]
- 800427a: 685b ldr r3, [r3, #4]
- 800427c: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 800427e: 687b ldr r3, [r7, #4]
- 8004280: 69db ldr r3, [r3, #28]
- 8004282: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- 8004284: 68fa ldr r2, [r7, #12]
- 8004286: 4b1e ldr r3, [pc, #120] ; (8004300 <TIM_OC4_SetConfig+0xa4>)
- 8004288: 4013 ands r3, r2
- 800428a: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC4S;
- 800428c: 68fb ldr r3, [r7, #12]
- 800428e: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8004292: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 8004294: 683b ldr r3, [r7, #0]
- 8004296: 681b ldr r3, [r3, #0]
- 8004298: 021b lsls r3, r3, #8
- 800429a: 68fa ldr r2, [r7, #12]
- 800429c: 4313 orrs r3, r2
- 800429e: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- 80042a0: 693b ldr r3, [r7, #16]
- 80042a2: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 80042a6: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
- 80042a8: 683b ldr r3, [r7, #0]
- 80042aa: 689b ldr r3, [r3, #8]
- 80042ac: 031b lsls r3, r3, #12
- 80042ae: 693a ldr r2, [r7, #16]
- 80042b0: 4313 orrs r3, r2
- 80042b2: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80042b4: 687b ldr r3, [r7, #4]
- 80042b6: 4a13 ldr r2, [pc, #76] ; (8004304 <TIM_OC4_SetConfig+0xa8>)
- 80042b8: 4293 cmp r3, r2
- 80042ba: d003 beq.n 80042c4 <TIM_OC4_SetConfig+0x68>
- 80042bc: 687b ldr r3, [r7, #4]
- 80042be: 4a12 ldr r2, [pc, #72] ; (8004308 <TIM_OC4_SetConfig+0xac>)
- 80042c0: 4293 cmp r3, r2
- 80042c2: d109 bne.n 80042d8 <TIM_OC4_SetConfig+0x7c>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- 80042c4: 697b ldr r3, [r7, #20]
- 80042c6: f423 4380 bic.w r3, r3, #16384 ; 0x4000
- 80042ca: 617b str r3, [r7, #20]
-
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- 80042cc: 683b ldr r3, [r7, #0]
- 80042ce: 695b ldr r3, [r3, #20]
- 80042d0: 019b lsls r3, r3, #6
- 80042d2: 697a ldr r2, [r7, #20]
- 80042d4: 4313 orrs r3, r2
- 80042d6: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 80042d8: 687b ldr r3, [r7, #4]
- 80042da: 697a ldr r2, [r7, #20]
- 80042dc: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 80042de: 687b ldr r3, [r7, #4]
- 80042e0: 68fa ldr r2, [r7, #12]
- 80042e2: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
- 80042e4: 683b ldr r3, [r7, #0]
- 80042e6: 685a ldr r2, [r3, #4]
- 80042e8: 687b ldr r3, [r7, #4]
- 80042ea: 641a str r2, [r3, #64] ; 0x40
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 80042ec: 687b ldr r3, [r7, #4]
- 80042ee: 693a ldr r2, [r7, #16]
- 80042f0: 621a str r2, [r3, #32]
-}
- 80042f2: bf00 nop
- 80042f4: 371c adds r7, #28
- 80042f6: 46bd mov sp, r7
- 80042f8: f85d 7b04 ldr.w r7, [sp], #4
- 80042fc: 4770 bx lr
- 80042fe: bf00 nop
- 8004300: feff8fff .word 0xfeff8fff
- 8004304: 40010000 .word 0x40010000
- 8004308: 40010400 .word 0x40010400
-
-0800430c <TIM_OC5_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 800430c: b480 push {r7}
- 800430e: b087 sub sp, #28
- 8004310: af00 add r7, sp, #0
- 8004312: 6078 str r0, [r7, #4]
- 8004314: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
- 8004316: 687b ldr r3, [r7, #4]
- 8004318: 6a1b ldr r3, [r3, #32]
- 800431a: f423 3280 bic.w r2, r3, #65536 ; 0x10000
- 800431e: 687b ldr r3, [r7, #4]
- 8004320: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004322: 687b ldr r3, [r7, #4]
- 8004324: 6a1b ldr r3, [r3, #32]
- 8004326: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004328: 687b ldr r3, [r7, #4]
- 800432a: 685b ldr r3, [r3, #4]
- 800432c: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 800432e: 687b ldr r3, [r7, #4]
- 8004330: 6d5b ldr r3, [r3, #84] ; 0x54
- 8004332: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- 8004334: 68fa ldr r2, [r7, #12]
- 8004336: 4b1b ldr r3, [pc, #108] ; (80043a4 <TIM_OC5_SetConfig+0x98>)
- 8004338: 4013 ands r3, r2
- 800433a: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 800433c: 683b ldr r3, [r7, #0]
- 800433e: 681b ldr r3, [r3, #0]
- 8004340: 68fa ldr r2, [r7, #12]
- 8004342: 4313 orrs r3, r2
- 8004344: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- 8004346: 693b ldr r3, [r7, #16]
- 8004348: f423 3300 bic.w r3, r3, #131072 ; 0x20000
- 800434c: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16U);
- 800434e: 683b ldr r3, [r7, #0]
- 8004350: 689b ldr r3, [r3, #8]
- 8004352: 041b lsls r3, r3, #16
- 8004354: 693a ldr r2, [r7, #16]
- 8004356: 4313 orrs r3, r2
- 8004358: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 800435a: 687b ldr r3, [r7, #4]
- 800435c: 4a12 ldr r2, [pc, #72] ; (80043a8 <TIM_OC5_SetConfig+0x9c>)
- 800435e: 4293 cmp r3, r2
- 8004360: d003 beq.n 800436a <TIM_OC5_SetConfig+0x5e>
- 8004362: 687b ldr r3, [r7, #4]
- 8004364: 4a11 ldr r2, [pc, #68] ; (80043ac <TIM_OC5_SetConfig+0xa0>)
- 8004366: 4293 cmp r3, r2
- 8004368: d109 bne.n 800437e <TIM_OC5_SetConfig+0x72>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- 800436a: 697b ldr r3, [r7, #20]
- 800436c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8004370: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8U);
- 8004372: 683b ldr r3, [r7, #0]
- 8004374: 695b ldr r3, [r3, #20]
- 8004376: 021b lsls r3, r3, #8
- 8004378: 697a ldr r2, [r7, #20]
- 800437a: 4313 orrs r3, r2
- 800437c: 617b str r3, [r7, #20]
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 800437e: 687b ldr r3, [r7, #4]
- 8004380: 697a ldr r2, [r7, #20]
- 8004382: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 8004384: 687b ldr r3, [r7, #4]
- 8004386: 68fa ldr r2, [r7, #12]
- 8004388: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
- 800438a: 683b ldr r3, [r7, #0]
- 800438c: 685a ldr r2, [r3, #4]
- 800438e: 687b ldr r3, [r7, #4]
- 8004390: 659a str r2, [r3, #88] ; 0x58
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004392: 687b ldr r3, [r7, #4]
- 8004394: 693a ldr r2, [r7, #16]
- 8004396: 621a str r2, [r3, #32]
-}
- 8004398: bf00 nop
- 800439a: 371c adds r7, #28
- 800439c: 46bd mov sp, r7
- 800439e: f85d 7b04 ldr.w r7, [sp], #4
- 80043a2: 4770 bx lr
- 80043a4: fffeff8f .word 0xfffeff8f
- 80043a8: 40010000 .word 0x40010000
- 80043ac: 40010400 .word 0x40010400
-
-080043b0 <TIM_OC6_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 80043b0: b480 push {r7}
- 80043b2: b087 sub sp, #28
- 80043b4: af00 add r7, sp, #0
- 80043b6: 6078 str r0, [r7, #4]
- 80043b8: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
- 80043ba: 687b ldr r3, [r7, #4]
- 80043bc: 6a1b ldr r3, [r3, #32]
- 80043be: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
- 80043c2: 687b ldr r3, [r7, #4]
- 80043c4: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 80043c6: 687b ldr r3, [r7, #4]
- 80043c8: 6a1b ldr r3, [r3, #32]
- 80043ca: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 80043cc: 687b ldr r3, [r7, #4]
- 80043ce: 685b ldr r3, [r3, #4]
- 80043d0: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 80043d2: 687b ldr r3, [r7, #4]
- 80043d4: 6d5b ldr r3, [r3, #84] ; 0x54
- 80043d6: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- 80043d8: 68fa ldr r2, [r7, #12]
- 80043da: 4b1c ldr r3, [pc, #112] ; (800444c <TIM_OC6_SetConfig+0x9c>)
- 80043dc: 4013 ands r3, r2
- 80043de: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 80043e0: 683b ldr r3, [r7, #0]
- 80043e2: 681b ldr r3, [r3, #0]
- 80043e4: 021b lsls r3, r3, #8
- 80043e6: 68fa ldr r2, [r7, #12]
- 80043e8: 4313 orrs r3, r2
- 80043ea: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- 80043ec: 693b ldr r3, [r7, #16]
- 80043ee: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
- 80043f2: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20U);
- 80043f4: 683b ldr r3, [r7, #0]
- 80043f6: 689b ldr r3, [r3, #8]
- 80043f8: 051b lsls r3, r3, #20
- 80043fa: 693a ldr r2, [r7, #16]
- 80043fc: 4313 orrs r3, r2
- 80043fe: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8004400: 687b ldr r3, [r7, #4]
- 8004402: 4a13 ldr r2, [pc, #76] ; (8004450 <TIM_OC6_SetConfig+0xa0>)
- 8004404: 4293 cmp r3, r2
- 8004406: d003 beq.n 8004410 <TIM_OC6_SetConfig+0x60>
- 8004408: 687b ldr r3, [r7, #4]
- 800440a: 4a12 ldr r2, [pc, #72] ; (8004454 <TIM_OC6_SetConfig+0xa4>)
- 800440c: 4293 cmp r3, r2
- 800440e: d109 bne.n 8004424 <TIM_OC6_SetConfig+0x74>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- 8004410: 697b ldr r3, [r7, #20]
- 8004412: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8004416: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10U);
- 8004418: 683b ldr r3, [r7, #0]
- 800441a: 695b ldr r3, [r3, #20]
- 800441c: 029b lsls r3, r3, #10
- 800441e: 697a ldr r2, [r7, #20]
- 8004420: 4313 orrs r3, r2
- 8004422: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004424: 687b ldr r3, [r7, #4]
- 8004426: 697a ldr r2, [r7, #20]
- 8004428: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 800442a: 687b ldr r3, [r7, #4]
- 800442c: 68fa ldr r2, [r7, #12]
- 800442e: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
- 8004430: 683b ldr r3, [r7, #0]
- 8004432: 685a ldr r2, [r3, #4]
- 8004434: 687b ldr r3, [r7, #4]
- 8004436: 65da str r2, [r3, #92] ; 0x5c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004438: 687b ldr r3, [r7, #4]
- 800443a: 693a ldr r2, [r7, #16]
- 800443c: 621a str r2, [r3, #32]
-}
- 800443e: bf00 nop
- 8004440: 371c adds r7, #28
- 8004442: 46bd mov sp, r7
- 8004444: f85d 7b04 ldr.w r7, [sp], #4
- 8004448: 4770 bx lr
- 800444a: bf00 nop
- 800444c: feff8fff .word 0xfeff8fff
- 8004450: 40010000 .word 0x40010000
- 8004454: 40010400 .word 0x40010400
-
-08004458 <TIM_TI1_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 8004458: b480 push {r7}
- 800445a: b087 sub sp, #28
- 800445c: af00 add r7, sp, #0
- 800445e: 60f8 str r0, [r7, #12]
- 8004460: 60b9 str r1, [r7, #8]
- 8004462: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- 8004464: 68fb ldr r3, [r7, #12]
- 8004466: 6a1b ldr r3, [r3, #32]
- 8004468: 617b str r3, [r7, #20]
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 800446a: 68fb ldr r3, [r7, #12]
- 800446c: 6a1b ldr r3, [r3, #32]
- 800446e: f023 0201 bic.w r2, r3, #1
- 8004472: 68fb ldr r3, [r7, #12]
- 8004474: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 8004476: 68fb ldr r3, [r7, #12]
- 8004478: 699b ldr r3, [r3, #24]
- 800447a: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 800447c: 693b ldr r3, [r7, #16]
- 800447e: f023 03f0 bic.w r3, r3, #240 ; 0xf0
- 8004482: 613b str r3, [r7, #16]
- tmpccmr1 |= (TIM_ICFilter << 4U);
- 8004484: 687b ldr r3, [r7, #4]
- 8004486: 011b lsls r3, r3, #4
- 8004488: 693a ldr r2, [r7, #16]
- 800448a: 4313 orrs r3, r2
- 800448c: 613b str r3, [r7, #16]
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 800448e: 697b ldr r3, [r7, #20]
- 8004490: f023 030a bic.w r3, r3, #10
- 8004494: 617b str r3, [r7, #20]
- tmpccer |= TIM_ICPolarity;
- 8004496: 697a ldr r2, [r7, #20]
- 8004498: 68bb ldr r3, [r7, #8]
- 800449a: 4313 orrs r3, r2
- 800449c: 617b str r3, [r7, #20]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- 800449e: 68fb ldr r3, [r7, #12]
- 80044a0: 693a ldr r2, [r7, #16]
- 80044a2: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 80044a4: 68fb ldr r3, [r7, #12]
- 80044a6: 697a ldr r2, [r7, #20]
- 80044a8: 621a str r2, [r3, #32]
-}
- 80044aa: bf00 nop
- 80044ac: 371c adds r7, #28
- 80044ae: 46bd mov sp, r7
- 80044b0: f85d 7b04 ldr.w r7, [sp], #4
- 80044b4: 4770 bx lr
-
-080044b6 <TIM_TI2_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 80044b6: b480 push {r7}
- 80044b8: b087 sub sp, #28
- 80044ba: af00 add r7, sp, #0
- 80044bc: 60f8 str r0, [r7, #12]
- 80044be: 60b9 str r1, [r7, #8]
- 80044c0: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 80044c2: 68fb ldr r3, [r7, #12]
- 80044c4: 6a1b ldr r3, [r3, #32]
- 80044c6: f023 0210 bic.w r2, r3, #16
- 80044ca: 68fb ldr r3, [r7, #12]
- 80044cc: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 80044ce: 68fb ldr r3, [r7, #12]
- 80044d0: 699b ldr r3, [r3, #24]
- 80044d2: 617b str r3, [r7, #20]
- tmpccer = TIMx->CCER;
- 80044d4: 68fb ldr r3, [r7, #12]
- 80044d6: 6a1b ldr r3, [r3, #32]
- 80044d8: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 80044da: 697b ldr r3, [r7, #20]
- 80044dc: f423 4370 bic.w r3, r3, #61440 ; 0xf000
- 80044e0: 617b str r3, [r7, #20]
- tmpccmr1 |= (TIM_ICFilter << 12U);
- 80044e2: 687b ldr r3, [r7, #4]
- 80044e4: 031b lsls r3, r3, #12
- 80044e6: 697a ldr r2, [r7, #20]
- 80044e8: 4313 orrs r3, r2
- 80044ea: 617b str r3, [r7, #20]
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 80044ec: 693b ldr r3, [r7, #16]
- 80044ee: f023 03a0 bic.w r3, r3, #160 ; 0xa0
- 80044f2: 613b str r3, [r7, #16]
- tmpccer |= (TIM_ICPolarity << 4U);
- 80044f4: 68bb ldr r3, [r7, #8]
- 80044f6: 011b lsls r3, r3, #4
- 80044f8: 693a ldr r2, [r7, #16]
- 80044fa: 4313 orrs r3, r2
- 80044fc: 613b str r3, [r7, #16]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- 80044fe: 68fb ldr r3, [r7, #12]
- 8004500: 697a ldr r2, [r7, #20]
- 8004502: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 8004504: 68fb ldr r3, [r7, #12]
- 8004506: 693a ldr r2, [r7, #16]
- 8004508: 621a str r2, [r3, #32]
-}
- 800450a: bf00 nop
- 800450c: 371c adds r7, #28
- 800450e: 46bd mov sp, r7
- 8004510: f85d 7b04 ldr.w r7, [sp], #4
- 8004514: 4770 bx lr
-
-08004516 <TIM_ITRx_SetConfig>:
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
- 8004516: b480 push {r7}
- 8004518: b085 sub sp, #20
- 800451a: af00 add r7, sp, #0
- 800451c: 6078 str r0, [r7, #4]
- 800451e: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- 8004520: 687b ldr r3, [r7, #4]
- 8004522: 689b ldr r3, [r3, #8]
- 8004524: 60fb str r3, [r7, #12]
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- 8004526: 68fb ldr r3, [r7, #12]
- 8004528: f023 0370 bic.w r3, r3, #112 ; 0x70
- 800452c: 60fb str r3, [r7, #12]
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 800452e: 683a ldr r2, [r7, #0]
- 8004530: 68fb ldr r3, [r7, #12]
- 8004532: 4313 orrs r3, r2
- 8004534: f043 0307 orr.w r3, r3, #7
- 8004538: 60fb str r3, [r7, #12]
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 800453a: 687b ldr r3, [r7, #4]
- 800453c: 68fa ldr r2, [r7, #12]
- 800453e: 609a str r2, [r3, #8]
-}
- 8004540: bf00 nop
- 8004542: 3714 adds r7, #20
- 8004544: 46bd mov sp, r7
- 8004546: f85d 7b04 ldr.w r7, [sp], #4
- 800454a: 4770 bx lr
-
-0800454c <TIM_ETR_SetConfig>:
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- 800454c: b480 push {r7}
- 800454e: b087 sub sp, #28
- 8004550: af00 add r7, sp, #0
- 8004552: 60f8 str r0, [r7, #12]
- 8004554: 60b9 str r1, [r7, #8]
- 8004556: 607a str r2, [r7, #4]
- 8004558: 603b str r3, [r7, #0]
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
- 800455a: 68fb ldr r3, [r7, #12]
- 800455c: 689b ldr r3, [r3, #8]
- 800455e: 617b str r3, [r7, #20]
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8004560: 697b ldr r3, [r7, #20]
- 8004562: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8004566: 617b str r3, [r7, #20]
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 8004568: 683b ldr r3, [r7, #0]
- 800456a: 021a lsls r2, r3, #8
- 800456c: 687b ldr r3, [r7, #4]
- 800456e: 431a orrs r2, r3
- 8004570: 68bb ldr r3, [r7, #8]
- 8004572: 4313 orrs r3, r2
- 8004574: 697a ldr r2, [r7, #20]
- 8004576: 4313 orrs r3, r2
- 8004578: 617b str r3, [r7, #20]
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 800457a: 68fb ldr r3, [r7, #12]
- 800457c: 697a ldr r2, [r7, #20]
- 800457e: 609a str r2, [r3, #8]
-}
- 8004580: bf00 nop
- 8004582: 371c adds r7, #28
- 8004584: 46bd mov sp, r7
- 8004586: f85d 7b04 ldr.w r7, [sp], #4
- 800458a: 4770 bx lr
-
-0800458c <TIM_CCxChannelCmd>:
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- 800458c: b480 push {r7}
- 800458e: b087 sub sp, #28
- 8004590: af00 add r7, sp, #0
- 8004592: 60f8 str r0, [r7, #12]
- 8004594: 60b9 str r1, [r7, #8]
- 8004596: 607a str r2, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
- 8004598: 68bb ldr r3, [r7, #8]
- 800459a: f003 031f and.w r3, r3, #31
- 800459e: 2201 movs r2, #1
- 80045a0: fa02 f303 lsl.w r3, r2, r3
- 80045a4: 617b str r3, [r7, #20]
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
- 80045a6: 68fb ldr r3, [r7, #12]
- 80045a8: 6a1a ldr r2, [r3, #32]
- 80045aa: 697b ldr r3, [r7, #20]
- 80045ac: 43db mvns r3, r3
- 80045ae: 401a ands r2, r3
- 80045b0: 68fb ldr r3, [r7, #12]
- 80045b2: 621a str r2, [r3, #32]
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
- 80045b4: 68fb ldr r3, [r7, #12]
- 80045b6: 6a1a ldr r2, [r3, #32]
- 80045b8: 68bb ldr r3, [r7, #8]
- 80045ba: f003 031f and.w r3, r3, #31
- 80045be: 6879 ldr r1, [r7, #4]
- 80045c0: fa01 f303 lsl.w r3, r1, r3
- 80045c4: 431a orrs r2, r3
- 80045c6: 68fb ldr r3, [r7, #12]
- 80045c8: 621a str r2, [r3, #32]
-}
- 80045ca: bf00 nop
- 80045cc: 371c adds r7, #28
- 80045ce: 46bd mov sp, r7
- 80045d0: f85d 7b04 ldr.w r7, [sp], #4
- 80045d4: 4770 bx lr
- ...
-
-080045d8 <HAL_TIMEx_MasterConfigSynchronization>:
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
-{
- 80045d8: b480 push {r7}
- 80045da: b085 sub sp, #20
- 80045dc: af00 add r7, sp, #0
- 80045de: 6078 str r0, [r7, #4]
- 80045e0: 6039 str r1, [r7, #0]
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
- 80045e2: 687b ldr r3, [r7, #4]
- 80045e4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 80045e8: 2b01 cmp r3, #1
- 80045ea: d101 bne.n 80045f0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 80045ec: 2302 movs r3, #2
- 80045ee: e045 b.n 800467c <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 80045f0: 687b ldr r3, [r7, #4]
- 80045f2: 2201 movs r2, #1
- 80045f4: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80045f8: 687b ldr r3, [r7, #4]
- 80045fa: 2202 movs r2, #2
- 80045fc: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
- 8004600: 687b ldr r3, [r7, #4]
- 8004602: 681b ldr r3, [r3, #0]
- 8004604: 685b ldr r3, [r3, #4]
- 8004606: 60fb str r3, [r7, #12]
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 8004608: 687b ldr r3, [r7, #4]
- 800460a: 681b ldr r3, [r3, #0]
- 800460c: 689b ldr r3, [r3, #8]
- 800460e: 60bb str r3, [r7, #8]
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 8004610: 687b ldr r3, [r7, #4]
- 8004612: 681b ldr r3, [r3, #0]
- 8004614: 4a1c ldr r2, [pc, #112] ; (8004688 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 8004616: 4293 cmp r3, r2
- 8004618: d004 beq.n 8004624 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 800461a: 687b ldr r3, [r7, #4]
- 800461c: 681b ldr r3, [r3, #0]
- 800461e: 4a1b ldr r2, [pc, #108] ; (800468c <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 8004620: 4293 cmp r3, r2
- 8004622: d108 bne.n 8004636 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- 8004624: 68fb ldr r3, [r7, #12]
- 8004626: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 800462a: 60fb str r3, [r7, #12]
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 800462c: 683b ldr r3, [r7, #0]
- 800462e: 685b ldr r3, [r3, #4]
- 8004630: 68fa ldr r2, [r7, #12]
- 8004632: 4313 orrs r3, r2
- 8004634: 60fb str r3, [r7, #12]
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- 8004636: 68fb ldr r3, [r7, #12]
- 8004638: f023 0370 bic.w r3, r3, #112 ; 0x70
- 800463c: 60fb str r3, [r7, #12]
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 800463e: 683b ldr r3, [r7, #0]
- 8004640: 681b ldr r3, [r3, #0]
- 8004642: 68fa ldr r2, [r7, #12]
- 8004644: 4313 orrs r3, r2
- 8004646: 60fb str r3, [r7, #12]
-
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- 8004648: 68bb ldr r3, [r7, #8]
- 800464a: f023 0380 bic.w r3, r3, #128 ; 0x80
- 800464e: 60bb str r3, [r7, #8]
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 8004650: 683b ldr r3, [r7, #0]
- 8004652: 689b ldr r3, [r3, #8]
- 8004654: 68ba ldr r2, [r7, #8]
- 8004656: 4313 orrs r3, r2
- 8004658: 60bb str r3, [r7, #8]
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
- 800465a: 687b ldr r3, [r7, #4]
- 800465c: 681b ldr r3, [r3, #0]
- 800465e: 68fa ldr r2, [r7, #12]
- 8004660: 605a str r2, [r3, #4]
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 8004662: 687b ldr r3, [r7, #4]
- 8004664: 681b ldr r3, [r3, #0]
- 8004666: 68ba ldr r2, [r7, #8]
- 8004668: 609a str r2, [r3, #8]
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
- 800466a: 687b ldr r3, [r7, #4]
- 800466c: 2201 movs r2, #1
- 800466e: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8004672: 687b ldr r3, [r7, #4]
- 8004674: 2200 movs r2, #0
- 8004676: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 800467a: 2300 movs r3, #0
-}
- 800467c: 4618 mov r0, r3
- 800467e: 3714 adds r7, #20
- 8004680: 46bd mov sp, r7
- 8004682: f85d 7b04 ldr.w r7, [sp], #4
- 8004686: 4770 bx lr
- 8004688: 40010000 .word 0x40010000
- 800468c: 40010400 .word 0x40010400
-
-08004690 <HAL_TIMEx_CommutCallback>:
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- 8004690: b480 push {r7}
- 8004692: b083 sub sp, #12
- 8004694: af00 add r7, sp, #0
- 8004696: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
- 8004698: bf00 nop
- 800469a: 370c adds r7, #12
- 800469c: 46bd mov sp, r7
- 800469e: f85d 7b04 ldr.w r7, [sp], #4
- 80046a2: 4770 bx lr
-
-080046a4 <HAL_TIMEx_BreakCallback>:
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- 80046a4: b480 push {r7}
- 80046a6: b083 sub sp, #12
- 80046a8: af00 add r7, sp, #0
- 80046aa: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
- 80046ac: bf00 nop
- 80046ae: 370c adds r7, #12
- 80046b0: 46bd mov sp, r7
- 80046b2: f85d 7b04 ldr.w r7, [sp], #4
- 80046b6: 4770 bx lr
-
-080046b8 <HAL_TIMEx_Break2Callback>:
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- 80046b8: b480 push {r7}
- 80046ba: b083 sub sp, #12
- 80046bc: af00 add r7, sp, #0
- 80046be: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
- 80046c0: bf00 nop
- 80046c2: 370c adds r7, #12
- 80046c4: 46bd mov sp, r7
- 80046c6: f85d 7b04 ldr.w r7, [sp], #4
- 80046ca: 4770 bx lr
-
-080046cc <HAL_UART_Init>:
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- 80046cc: b580 push {r7, lr}
- 80046ce: b082 sub sp, #8
- 80046d0: af00 add r7, sp, #0
- 80046d2: 6078 str r0, [r7, #4]
- /* Check the UART handle allocation */
- if (huart == NULL)
- 80046d4: 687b ldr r3, [r7, #4]
- 80046d6: 2b00 cmp r3, #0
- 80046d8: d101 bne.n 80046de <HAL_UART_Init+0x12>
- {
- return HAL_ERROR;
- 80046da: 2301 movs r3, #1
- 80046dc: e040 b.n 8004760 <HAL_UART_Init+0x94>
- {
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
- }
-
- if (huart->gState == HAL_UART_STATE_RESET)
- 80046de: 687b ldr r3, [r7, #4]
- 80046e0: 6f5b ldr r3, [r3, #116] ; 0x74
- 80046e2: 2b00 cmp r3, #0
- 80046e4: d106 bne.n 80046f4 <HAL_UART_Init+0x28>
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- 80046e6: 687b ldr r3, [r7, #4]
- 80046e8: 2200 movs r2, #0
- 80046ea: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- 80046ee: 6878 ldr r0, [r7, #4]
- 80046f0: f7fd fa38 bl 8001b64 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
- 80046f4: 687b ldr r3, [r7, #4]
- 80046f6: 2224 movs r2, #36 ; 0x24
- 80046f8: 675a str r2, [r3, #116] ; 0x74
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
- 80046fa: 687b ldr r3, [r7, #4]
- 80046fc: 681b ldr r3, [r3, #0]
- 80046fe: 681a ldr r2, [r3, #0]
- 8004700: 687b ldr r3, [r7, #4]
- 8004702: 681b ldr r3, [r3, #0]
- 8004704: f022 0201 bic.w r2, r2, #1
- 8004708: 601a str r2, [r3, #0]
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- 800470a: 6878 ldr r0, [r7, #4]
- 800470c: f000 fa90 bl 8004c30 <UART_SetConfig>
- 8004710: 4603 mov r3, r0
- 8004712: 2b01 cmp r3, #1
- 8004714: d101 bne.n 800471a <HAL_UART_Init+0x4e>
- {
- return HAL_ERROR;
- 8004716: 2301 movs r3, #1
- 8004718: e022 b.n 8004760 <HAL_UART_Init+0x94>
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 800471a: 687b ldr r3, [r7, #4]
- 800471c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800471e: 2b00 cmp r3, #0
- 8004720: d002 beq.n 8004728 <HAL_UART_Init+0x5c>
- {
- UART_AdvFeatureConfig(huart);
- 8004722: 6878 ldr r0, [r7, #4]
- 8004724: f000 fd28 bl 8005178 <UART_AdvFeatureConfig>
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8004728: 687b ldr r3, [r7, #4]
- 800472a: 681b ldr r3, [r3, #0]
- 800472c: 685a ldr r2, [r3, #4]
- 800472e: 687b ldr r3, [r7, #4]
- 8004730: 681b ldr r3, [r3, #0]
- 8004732: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 8004736: 605a str r2, [r3, #4]
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8004738: 687b ldr r3, [r7, #4]
- 800473a: 681b ldr r3, [r3, #0]
- 800473c: 689a ldr r2, [r3, #8]
- 800473e: 687b ldr r3, [r7, #4]
- 8004740: 681b ldr r3, [r3, #0]
- 8004742: f022 022a bic.w r2, r2, #42 ; 0x2a
- 8004746: 609a str r2, [r3, #8]
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
- 8004748: 687b ldr r3, [r7, #4]
- 800474a: 681b ldr r3, [r3, #0]
- 800474c: 681a ldr r2, [r3, #0]
- 800474e: 687b ldr r3, [r7, #4]
- 8004750: 681b ldr r3, [r3, #0]
- 8004752: f042 0201 orr.w r2, r2, #1
- 8004756: 601a str r2, [r3, #0]
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
- 8004758: 6878 ldr r0, [r7, #4]
- 800475a: f000 fdaf bl 80052bc <UART_CheckIdleState>
- 800475e: 4603 mov r3, r0
-}
- 8004760: 4618 mov r0, r3
- 8004762: 3708 adds r7, #8
- 8004764: 46bd mov sp, r7
- 8004766: bd80 pop {r7, pc}
-
-08004768 <HAL_UART_Transmit>:
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- 8004768: b580 push {r7, lr}
- 800476a: b08a sub sp, #40 ; 0x28
- 800476c: af02 add r7, sp, #8
- 800476e: 60f8 str r0, [r7, #12]
- 8004770: 60b9 str r1, [r7, #8]
- 8004772: 603b str r3, [r7, #0]
- 8004774: 4613 mov r3, r2
- 8004776: 80fb strh r3, [r7, #6]
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
- uint32_t tickstart;
-
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY)
- 8004778: 68fb ldr r3, [r7, #12]
- 800477a: 6f5b ldr r3, [r3, #116] ; 0x74
- 800477c: 2b20 cmp r3, #32
- 800477e: d17f bne.n 8004880 <HAL_UART_Transmit+0x118>
- {
- if ((pData == NULL) || (Size == 0U))
- 8004780: 68bb ldr r3, [r7, #8]
- 8004782: 2b00 cmp r3, #0
- 8004784: d002 beq.n 800478c <HAL_UART_Transmit+0x24>
- 8004786: 88fb ldrh r3, [r7, #6]
- 8004788: 2b00 cmp r3, #0
- 800478a: d101 bne.n 8004790 <HAL_UART_Transmit+0x28>
- {
- return HAL_ERROR;
- 800478c: 2301 movs r3, #1
- 800478e: e078 b.n 8004882 <HAL_UART_Transmit+0x11a>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8004790: 68fb ldr r3, [r7, #12]
- 8004792: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 8004796: 2b01 cmp r3, #1
- 8004798: d101 bne.n 800479e <HAL_UART_Transmit+0x36>
- 800479a: 2302 movs r3, #2
- 800479c: e071 b.n 8004882 <HAL_UART_Transmit+0x11a>
- 800479e: 68fb ldr r3, [r7, #12]
- 80047a0: 2201 movs r2, #1
- 80047a2: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80047a6: 68fb ldr r3, [r7, #12]
- 80047a8: 2200 movs r2, #0
- 80047aa: 67da str r2, [r3, #124] ; 0x7c
- huart->gState = HAL_UART_STATE_BUSY_TX;
- 80047ac: 68fb ldr r3, [r7, #12]
- 80047ae: 2221 movs r2, #33 ; 0x21
- 80047b0: 675a str r2, [r3, #116] ; 0x74
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 80047b2: f7fd fb1f bl 8001df4 <HAL_GetTick>
- 80047b6: 6178 str r0, [r7, #20]
-
- huart->TxXferSize = Size;
- 80047b8: 68fb ldr r3, [r7, #12]
- 80047ba: 88fa ldrh r2, [r7, #6]
- 80047bc: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
- huart->TxXferCount = Size;
- 80047c0: 68fb ldr r3, [r7, #12]
- 80047c2: 88fa ldrh r2, [r7, #6]
- 80047c4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-
- /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 80047c8: 68fb ldr r3, [r7, #12]
- 80047ca: 689b ldr r3, [r3, #8]
- 80047cc: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80047d0: d108 bne.n 80047e4 <HAL_UART_Transmit+0x7c>
- 80047d2: 68fb ldr r3, [r7, #12]
- 80047d4: 691b ldr r3, [r3, #16]
- 80047d6: 2b00 cmp r3, #0
- 80047d8: d104 bne.n 80047e4 <HAL_UART_Transmit+0x7c>
- {
- pdata8bits = NULL;
- 80047da: 2300 movs r3, #0
- 80047dc: 61fb str r3, [r7, #28]
- pdata16bits = (uint16_t *) pData;
- 80047de: 68bb ldr r3, [r7, #8]
- 80047e0: 61bb str r3, [r7, #24]
- 80047e2: e003 b.n 80047ec <HAL_UART_Transmit+0x84>
- }
- else
- {
- pdata8bits = pData;
- 80047e4: 68bb ldr r3, [r7, #8]
- 80047e6: 61fb str r3, [r7, #28]
- pdata16bits = NULL;
- 80047e8: 2300 movs r3, #0
- 80047ea: 61bb str r3, [r7, #24]
- }
-
- while (huart->TxXferCount > 0U)
- 80047ec: e02c b.n 8004848 <HAL_UART_Transmit+0xe0>
- {
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 80047ee: 683b ldr r3, [r7, #0]
- 80047f0: 9300 str r3, [sp, #0]
- 80047f2: 697b ldr r3, [r7, #20]
- 80047f4: 2200 movs r2, #0
- 80047f6: 2180 movs r1, #128 ; 0x80
- 80047f8: 68f8 ldr r0, [r7, #12]
- 80047fa: f000 fd8e bl 800531a <UART_WaitOnFlagUntilTimeout>
- 80047fe: 4603 mov r3, r0
- 8004800: 2b00 cmp r3, #0
- 8004802: d001 beq.n 8004808 <HAL_UART_Transmit+0xa0>
- {
- return HAL_TIMEOUT;
- 8004804: 2303 movs r3, #3
- 8004806: e03c b.n 8004882 <HAL_UART_Transmit+0x11a>
- }
- if (pdata8bits == NULL)
- 8004808: 69fb ldr r3, [r7, #28]
- 800480a: 2b00 cmp r3, #0
- 800480c: d10b bne.n 8004826 <HAL_UART_Transmit+0xbe>
- {
- huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 800480e: 69bb ldr r3, [r7, #24]
- 8004810: 881b ldrh r3, [r3, #0]
- 8004812: 461a mov r2, r3
- 8004814: 68fb ldr r3, [r7, #12]
- 8004816: 681b ldr r3, [r3, #0]
- 8004818: f3c2 0208 ubfx r2, r2, #0, #9
- 800481c: 629a str r2, [r3, #40] ; 0x28
- pdata16bits++;
- 800481e: 69bb ldr r3, [r7, #24]
- 8004820: 3302 adds r3, #2
- 8004822: 61bb str r3, [r7, #24]
- 8004824: e007 b.n 8004836 <HAL_UART_Transmit+0xce>
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 8004826: 69fb ldr r3, [r7, #28]
- 8004828: 781a ldrb r2, [r3, #0]
- 800482a: 68fb ldr r3, [r7, #12]
- 800482c: 681b ldr r3, [r3, #0]
- 800482e: 629a str r2, [r3, #40] ; 0x28
- pdata8bits++;
- 8004830: 69fb ldr r3, [r7, #28]
- 8004832: 3301 adds r3, #1
- 8004834: 61fb str r3, [r7, #28]
- }
- huart->TxXferCount--;
- 8004836: 68fb ldr r3, [r7, #12]
- 8004838: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 800483c: b29b uxth r3, r3
- 800483e: 3b01 subs r3, #1
- 8004840: b29a uxth r2, r3
- 8004842: 68fb ldr r3, [r7, #12]
- 8004844: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
- while (huart->TxXferCount > 0U)
- 8004848: 68fb ldr r3, [r7, #12]
- 800484a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 800484e: b29b uxth r3, r3
- 8004850: 2b00 cmp r3, #0
- 8004852: d1cc bne.n 80047ee <HAL_UART_Transmit+0x86>
- }
-
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 8004854: 683b ldr r3, [r7, #0]
- 8004856: 9300 str r3, [sp, #0]
- 8004858: 697b ldr r3, [r7, #20]
- 800485a: 2200 movs r2, #0
- 800485c: 2140 movs r1, #64 ; 0x40
- 800485e: 68f8 ldr r0, [r7, #12]
- 8004860: f000 fd5b bl 800531a <UART_WaitOnFlagUntilTimeout>
- 8004864: 4603 mov r3, r0
- 8004866: 2b00 cmp r3, #0
- 8004868: d001 beq.n 800486e <HAL_UART_Transmit+0x106>
- {
- return HAL_TIMEOUT;
- 800486a: 2303 movs r3, #3
- 800486c: e009 b.n 8004882 <HAL_UART_Transmit+0x11a>
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 800486e: 68fb ldr r3, [r7, #12]
- 8004870: 2220 movs r2, #32
- 8004872: 675a str r2, [r3, #116] ; 0x74
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8004874: 68fb ldr r3, [r7, #12]
- 8004876: 2200 movs r2, #0
- 8004878: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 800487c: 2300 movs r3, #0
- 800487e: e000 b.n 8004882 <HAL_UART_Transmit+0x11a>
- }
- else
- {
- return HAL_BUSY;
- 8004880: 2302 movs r3, #2
- }
-}
- 8004882: 4618 mov r0, r3
- 8004884: 3720 adds r7, #32
- 8004886: 46bd mov sp, r7
- 8004888: bd80 pop {r7, pc}
- ...
-
-0800488c <HAL_UART_Receive_IT>:
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- 800488c: b480 push {r7}
- 800488e: b085 sub sp, #20
- 8004890: af00 add r7, sp, #0
- 8004892: 60f8 str r0, [r7, #12]
- 8004894: 60b9 str r1, [r7, #8]
- 8004896: 4613 mov r3, r2
- 8004898: 80fb strh r3, [r7, #6]
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY)
- 800489a: 68fb ldr r3, [r7, #12]
- 800489c: 6f9b ldr r3, [r3, #120] ; 0x78
- 800489e: 2b20 cmp r3, #32
- 80048a0: f040 808a bne.w 80049b8 <HAL_UART_Receive_IT+0x12c>
- {
- if ((pData == NULL) || (Size == 0U))
- 80048a4: 68bb ldr r3, [r7, #8]
- 80048a6: 2b00 cmp r3, #0
- 80048a8: d002 beq.n 80048b0 <HAL_UART_Receive_IT+0x24>
- 80048aa: 88fb ldrh r3, [r7, #6]
- 80048ac: 2b00 cmp r3, #0
- 80048ae: d101 bne.n 80048b4 <HAL_UART_Receive_IT+0x28>
- {
- return HAL_ERROR;
- 80048b0: 2301 movs r3, #1
- 80048b2: e082 b.n 80049ba <HAL_UART_Receive_IT+0x12e>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 80048b4: 68fb ldr r3, [r7, #12]
- 80048b6: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 80048ba: 2b01 cmp r3, #1
- 80048bc: d101 bne.n 80048c2 <HAL_UART_Receive_IT+0x36>
- 80048be: 2302 movs r3, #2
- 80048c0: e07b b.n 80049ba <HAL_UART_Receive_IT+0x12e>
- 80048c2: 68fb ldr r3, [r7, #12]
- 80048c4: 2201 movs r2, #1
- 80048c6: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->pRxBuffPtr = pData;
- 80048ca: 68fb ldr r3, [r7, #12]
- 80048cc: 68ba ldr r2, [r7, #8]
- 80048ce: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferSize = Size;
- 80048d0: 68fb ldr r3, [r7, #12]
- 80048d2: 88fa ldrh r2, [r7, #6]
- 80048d4: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
- huart->RxXferCount = Size;
- 80048d8: 68fb ldr r3, [r7, #12]
- 80048da: 88fa ldrh r2, [r7, #6]
- 80048dc: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->RxISR = NULL;
- 80048e0: 68fb ldr r3, [r7, #12]
- 80048e2: 2200 movs r2, #0
- 80048e4: 661a str r2, [r3, #96] ; 0x60
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- 80048e6: 68fb ldr r3, [r7, #12]
- 80048e8: 689b ldr r3, [r3, #8]
- 80048ea: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80048ee: d10e bne.n 800490e <HAL_UART_Receive_IT+0x82>
- 80048f0: 68fb ldr r3, [r7, #12]
- 80048f2: 691b ldr r3, [r3, #16]
- 80048f4: 2b00 cmp r3, #0
- 80048f6: d105 bne.n 8004904 <HAL_UART_Receive_IT+0x78>
- 80048f8: 68fb ldr r3, [r7, #12]
- 80048fa: f240 12ff movw r2, #511 ; 0x1ff
- 80048fe: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004902: e02d b.n 8004960 <HAL_UART_Receive_IT+0xd4>
- 8004904: 68fb ldr r3, [r7, #12]
- 8004906: 22ff movs r2, #255 ; 0xff
- 8004908: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 800490c: e028 b.n 8004960 <HAL_UART_Receive_IT+0xd4>
- 800490e: 68fb ldr r3, [r7, #12]
- 8004910: 689b ldr r3, [r3, #8]
- 8004912: 2b00 cmp r3, #0
- 8004914: d10d bne.n 8004932 <HAL_UART_Receive_IT+0xa6>
- 8004916: 68fb ldr r3, [r7, #12]
- 8004918: 691b ldr r3, [r3, #16]
- 800491a: 2b00 cmp r3, #0
- 800491c: d104 bne.n 8004928 <HAL_UART_Receive_IT+0x9c>
- 800491e: 68fb ldr r3, [r7, #12]
- 8004920: 22ff movs r2, #255 ; 0xff
- 8004922: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004926: e01b b.n 8004960 <HAL_UART_Receive_IT+0xd4>
- 8004928: 68fb ldr r3, [r7, #12]
- 800492a: 227f movs r2, #127 ; 0x7f
- 800492c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004930: e016 b.n 8004960 <HAL_UART_Receive_IT+0xd4>
- 8004932: 68fb ldr r3, [r7, #12]
- 8004934: 689b ldr r3, [r3, #8]
- 8004936: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
- 800493a: d10d bne.n 8004958 <HAL_UART_Receive_IT+0xcc>
- 800493c: 68fb ldr r3, [r7, #12]
- 800493e: 691b ldr r3, [r3, #16]
- 8004940: 2b00 cmp r3, #0
- 8004942: d104 bne.n 800494e <HAL_UART_Receive_IT+0xc2>
- 8004944: 68fb ldr r3, [r7, #12]
- 8004946: 227f movs r2, #127 ; 0x7f
- 8004948: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 800494c: e008 b.n 8004960 <HAL_UART_Receive_IT+0xd4>
- 800494e: 68fb ldr r3, [r7, #12]
- 8004950: 223f movs r2, #63 ; 0x3f
- 8004952: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004956: e003 b.n 8004960 <HAL_UART_Receive_IT+0xd4>
- 8004958: 68fb ldr r3, [r7, #12]
- 800495a: 2200 movs r2, #0
- 800495c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004960: 68fb ldr r3, [r7, #12]
- 8004962: 2200 movs r2, #0
- 8004964: 67da str r2, [r3, #124] ; 0x7c
- huart->RxState = HAL_UART_STATE_BUSY_RX;
- 8004966: 68fb ldr r3, [r7, #12]
- 8004968: 2222 movs r2, #34 ; 0x22
- 800496a: 679a str r2, [r3, #120] ; 0x78
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800496c: 68fb ldr r3, [r7, #12]
- 800496e: 681b ldr r3, [r3, #0]
- 8004970: 689a ldr r2, [r3, #8]
- 8004972: 68fb ldr r3, [r7, #12]
- 8004974: 681b ldr r3, [r3, #0]
- 8004976: f042 0201 orr.w r2, r2, #1
- 800497a: 609a str r2, [r3, #8]
-
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 800497c: 68fb ldr r3, [r7, #12]
- 800497e: 689b ldr r3, [r3, #8]
- 8004980: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004984: d107 bne.n 8004996 <HAL_UART_Receive_IT+0x10a>
- 8004986: 68fb ldr r3, [r7, #12]
- 8004988: 691b ldr r3, [r3, #16]
- 800498a: 2b00 cmp r3, #0
- 800498c: d103 bne.n 8004996 <HAL_UART_Receive_IT+0x10a>
- {
- huart->RxISR = UART_RxISR_16BIT;
- 800498e: 68fb ldr r3, [r7, #12]
- 8004990: 4a0d ldr r2, [pc, #52] ; (80049c8 <HAL_UART_Receive_IT+0x13c>)
- 8004992: 661a str r2, [r3, #96] ; 0x60
- 8004994: e002 b.n 800499c <HAL_UART_Receive_IT+0x110>
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- 8004996: 68fb ldr r3, [r7, #12]
- 8004998: 4a0c ldr r2, [pc, #48] ; (80049cc <HAL_UART_Receive_IT+0x140>)
- 800499a: 661a str r2, [r3, #96] ; 0x60
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 800499c: 68fb ldr r3, [r7, #12]
- 800499e: 2200 movs r2, #0
- 80049a0: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- 80049a4: 68fb ldr r3, [r7, #12]
- 80049a6: 681b ldr r3, [r3, #0]
- 80049a8: 681a ldr r2, [r3, #0]
- 80049aa: 68fb ldr r3, [r7, #12]
- 80049ac: 681b ldr r3, [r3, #0]
- 80049ae: f442 7290 orr.w r2, r2, #288 ; 0x120
- 80049b2: 601a str r2, [r3, #0]
-
- return HAL_OK;
- 80049b4: 2300 movs r3, #0
- 80049b6: e000 b.n 80049ba <HAL_UART_Receive_IT+0x12e>
- }
- else
- {
- return HAL_BUSY;
- 80049b8: 2302 movs r3, #2
- }
-}
- 80049ba: 4618 mov r0, r3
- 80049bc: 3714 adds r7, #20
- 80049be: 46bd mov sp, r7
- 80049c0: f85d 7b04 ldr.w r7, [sp], #4
- 80049c4: 4770 bx lr
- 80049c6: bf00 nop
- 80049c8: 080054ef .word 0x080054ef
- 80049cc: 08005449 .word 0x08005449
-
-080049d0 <HAL_UART_IRQHandler>:
- * @brief Handle UART interrupt request.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- 80049d0: b580 push {r7, lr}
- 80049d2: b088 sub sp, #32
- 80049d4: af00 add r7, sp, #0
- 80049d6: 6078 str r0, [r7, #4]
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- 80049d8: 687b ldr r3, [r7, #4]
- 80049da: 681b ldr r3, [r3, #0]
- 80049dc: 69db ldr r3, [r3, #28]
- 80049de: 61fb str r3, [r7, #28]
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- 80049e0: 687b ldr r3, [r7, #4]
- 80049e2: 681b ldr r3, [r3, #0]
- 80049e4: 681b ldr r3, [r3, #0]
- 80049e6: 61bb str r3, [r7, #24]
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- 80049e8: 687b ldr r3, [r7, #4]
- 80049ea: 681b ldr r3, [r3, #0]
- 80049ec: 689b ldr r3, [r3, #8]
- 80049ee: 617b str r3, [r7, #20]
-
- uint32_t errorflags;
- uint32_t errorcode;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- 80049f0: 69fb ldr r3, [r7, #28]
- 80049f2: f003 030f and.w r3, r3, #15
- 80049f6: 613b str r3, [r7, #16]
- if (errorflags == 0U)
- 80049f8: 693b ldr r3, [r7, #16]
- 80049fa: 2b00 cmp r3, #0
- 80049fc: d113 bne.n 8004a26 <HAL_UART_IRQHandler+0x56>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 80049fe: 69fb ldr r3, [r7, #28]
- 8004a00: f003 0320 and.w r3, r3, #32
- 8004a04: 2b00 cmp r3, #0
- 8004a06: d00e beq.n 8004a26 <HAL_UART_IRQHandler+0x56>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 8004a08: 69bb ldr r3, [r7, #24]
- 8004a0a: f003 0320 and.w r3, r3, #32
- 8004a0e: 2b00 cmp r3, #0
- 8004a10: d009 beq.n 8004a26 <HAL_UART_IRQHandler+0x56>
- {
- if (huart->RxISR != NULL)
- 8004a12: 687b ldr r3, [r7, #4]
- 8004a14: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004a16: 2b00 cmp r3, #0
- 8004a18: f000 80eb beq.w 8004bf2 <HAL_UART_IRQHandler+0x222>
- {
- huart->RxISR(huart);
- 8004a1c: 687b ldr r3, [r7, #4]
- 8004a1e: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004a20: 6878 ldr r0, [r7, #4]
- 8004a22: 4798 blx r3
- }
- return;
- 8004a24: e0e5 b.n 8004bf2 <HAL_UART_IRQHandler+0x222>
- }
- }
-
- /* If some errors occur */
- if ((errorflags != 0U)
- 8004a26: 693b ldr r3, [r7, #16]
- 8004a28: 2b00 cmp r3, #0
- 8004a2a: f000 80c0 beq.w 8004bae <HAL_UART_IRQHandler+0x1de>
- && (((cr3its & USART_CR3_EIE) != 0U)
- 8004a2e: 697b ldr r3, [r7, #20]
- 8004a30: f003 0301 and.w r3, r3, #1
- 8004a34: 2b00 cmp r3, #0
- 8004a36: d105 bne.n 8004a44 <HAL_UART_IRQHandler+0x74>
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
- 8004a38: 69bb ldr r3, [r7, #24]
- 8004a3a: f403 7390 and.w r3, r3, #288 ; 0x120
- 8004a3e: 2b00 cmp r3, #0
- 8004a40: f000 80b5 beq.w 8004bae <HAL_UART_IRQHandler+0x1de>
- {
- /* UART parity error interrupt occurred -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
- 8004a44: 69fb ldr r3, [r7, #28]
- 8004a46: f003 0301 and.w r3, r3, #1
- 8004a4a: 2b00 cmp r3, #0
- 8004a4c: d00e beq.n 8004a6c <HAL_UART_IRQHandler+0x9c>
- 8004a4e: 69bb ldr r3, [r7, #24]
- 8004a50: f403 7380 and.w r3, r3, #256 ; 0x100
- 8004a54: 2b00 cmp r3, #0
- 8004a56: d009 beq.n 8004a6c <HAL_UART_IRQHandler+0x9c>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
- 8004a58: 687b ldr r3, [r7, #4]
- 8004a5a: 681b ldr r3, [r3, #0]
- 8004a5c: 2201 movs r2, #1
- 8004a5e: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- 8004a60: 687b ldr r3, [r7, #4]
- 8004a62: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004a64: f043 0201 orr.w r2, r3, #1
- 8004a68: 687b ldr r3, [r7, #4]
- 8004a6a: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004a6c: 69fb ldr r3, [r7, #28]
- 8004a6e: f003 0302 and.w r3, r3, #2
- 8004a72: 2b00 cmp r3, #0
- 8004a74: d00e beq.n 8004a94 <HAL_UART_IRQHandler+0xc4>
- 8004a76: 697b ldr r3, [r7, #20]
- 8004a78: f003 0301 and.w r3, r3, #1
- 8004a7c: 2b00 cmp r3, #0
- 8004a7e: d009 beq.n 8004a94 <HAL_UART_IRQHandler+0xc4>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
- 8004a80: 687b ldr r3, [r7, #4]
- 8004a82: 681b ldr r3, [r3, #0]
- 8004a84: 2202 movs r2, #2
- 8004a86: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- 8004a88: 687b ldr r3, [r7, #4]
- 8004a8a: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004a8c: f043 0204 orr.w r2, r3, #4
- 8004a90: 687b ldr r3, [r7, #4]
- 8004a92: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004a94: 69fb ldr r3, [r7, #28]
- 8004a96: f003 0304 and.w r3, r3, #4
- 8004a9a: 2b00 cmp r3, #0
- 8004a9c: d00e beq.n 8004abc <HAL_UART_IRQHandler+0xec>
- 8004a9e: 697b ldr r3, [r7, #20]
- 8004aa0: f003 0301 and.w r3, r3, #1
- 8004aa4: 2b00 cmp r3, #0
- 8004aa6: d009 beq.n 8004abc <HAL_UART_IRQHandler+0xec>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
- 8004aa8: 687b ldr r3, [r7, #4]
- 8004aaa: 681b ldr r3, [r3, #0]
- 8004aac: 2204 movs r2, #4
- 8004aae: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- 8004ab0: 687b ldr r3, [r7, #4]
- 8004ab2: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004ab4: f043 0202 orr.w r2, r3, #2
- 8004ab8: 687b ldr r3, [r7, #4]
- 8004aba: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if (((isrflags & USART_ISR_ORE) != 0U)
- 8004abc: 69fb ldr r3, [r7, #28]
- 8004abe: f003 0308 and.w r3, r3, #8
- 8004ac2: 2b00 cmp r3, #0
- 8004ac4: d013 beq.n 8004aee <HAL_UART_IRQHandler+0x11e>
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8004ac6: 69bb ldr r3, [r7, #24]
- 8004ac8: f003 0320 and.w r3, r3, #32
- 8004acc: 2b00 cmp r3, #0
- 8004ace: d104 bne.n 8004ada <HAL_UART_IRQHandler+0x10a>
- ((cr3its & USART_CR3_EIE) != 0U)))
- 8004ad0: 697b ldr r3, [r7, #20]
- 8004ad2: f003 0301 and.w r3, r3, #1
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8004ad6: 2b00 cmp r3, #0
- 8004ad8: d009 beq.n 8004aee <HAL_UART_IRQHandler+0x11e>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 8004ada: 687b ldr r3, [r7, #4]
- 8004adc: 681b ldr r3, [r3, #0]
- 8004ade: 2208 movs r2, #8
- 8004ae0: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 8004ae2: 687b ldr r3, [r7, #4]
- 8004ae4: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004ae6: f043 0208 orr.w r2, r3, #8
- 8004aea: 687b ldr r3, [r7, #4]
- 8004aec: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 8004aee: 687b ldr r3, [r7, #4]
- 8004af0: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004af2: 2b00 cmp r3, #0
- 8004af4: d07f beq.n 8004bf6 <HAL_UART_IRQHandler+0x226>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 8004af6: 69fb ldr r3, [r7, #28]
- 8004af8: f003 0320 and.w r3, r3, #32
- 8004afc: 2b00 cmp r3, #0
- 8004afe: d00c beq.n 8004b1a <HAL_UART_IRQHandler+0x14a>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 8004b00: 69bb ldr r3, [r7, #24]
- 8004b02: f003 0320 and.w r3, r3, #32
- 8004b06: 2b00 cmp r3, #0
- 8004b08: d007 beq.n 8004b1a <HAL_UART_IRQHandler+0x14a>
- {
- if (huart->RxISR != NULL)
- 8004b0a: 687b ldr r3, [r7, #4]
- 8004b0c: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004b0e: 2b00 cmp r3, #0
- 8004b10: d003 beq.n 8004b1a <HAL_UART_IRQHandler+0x14a>
- {
- huart->RxISR(huart);
- 8004b12: 687b ldr r3, [r7, #4]
- 8004b14: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004b16: 6878 ldr r0, [r7, #4]
- 8004b18: 4798 blx r3
- }
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- errorcode = huart->ErrorCode;
- 8004b1a: 687b ldr r3, [r7, #4]
- 8004b1c: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004b1e: 60fb str r3, [r7, #12]
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8004b20: 687b ldr r3, [r7, #4]
- 8004b22: 681b ldr r3, [r3, #0]
- 8004b24: 689b ldr r3, [r3, #8]
- 8004b26: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004b2a: 2b40 cmp r3, #64 ; 0x40
- 8004b2c: d004 beq.n 8004b38 <HAL_UART_IRQHandler+0x168>
- ((errorcode & HAL_UART_ERROR_ORE) != 0U))
- 8004b2e: 68fb ldr r3, [r7, #12]
- 8004b30: f003 0308 and.w r3, r3, #8
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8004b34: 2b00 cmp r3, #0
- 8004b36: d031 beq.n 8004b9c <HAL_UART_IRQHandler+0x1cc>
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
- 8004b38: 6878 ldr r0, [r7, #4]
- 8004b3a: f000 fc36 bl 80053aa <UART_EndRxTransfer>
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b3e: 687b ldr r3, [r7, #4]
- 8004b40: 681b ldr r3, [r3, #0]
- 8004b42: 689b ldr r3, [r3, #8]
- 8004b44: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004b48: 2b40 cmp r3, #64 ; 0x40
- 8004b4a: d123 bne.n 8004b94 <HAL_UART_IRQHandler+0x1c4>
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 8004b4c: 687b ldr r3, [r7, #4]
- 8004b4e: 681b ldr r3, [r3, #0]
- 8004b50: 689a ldr r2, [r3, #8]
- 8004b52: 687b ldr r3, [r7, #4]
- 8004b54: 681b ldr r3, [r3, #0]
- 8004b56: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8004b5a: 609a str r2, [r3, #8]
-
- /* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL)
- 8004b5c: 687b ldr r3, [r7, #4]
- 8004b5e: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b60: 2b00 cmp r3, #0
- 8004b62: d013 beq.n 8004b8c <HAL_UART_IRQHandler+0x1bc>
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8004b64: 687b ldr r3, [r7, #4]
- 8004b66: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b68: 4a26 ldr r2, [pc, #152] ; (8004c04 <HAL_UART_IRQHandler+0x234>)
- 8004b6a: 651a str r2, [r3, #80] ; 0x50
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 8004b6c: 687b ldr r3, [r7, #4]
- 8004b6e: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b70: 4618 mov r0, r3
- 8004b72: f7fd fa5c bl 800202e <HAL_DMA_Abort_IT>
- 8004b76: 4603 mov r3, r0
- 8004b78: 2b00 cmp r3, #0
- 8004b7a: d016 beq.n 8004baa <HAL_UART_IRQHandler+0x1da>
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 8004b7c: 687b ldr r3, [r7, #4]
- 8004b7e: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004b80: 6d1b ldr r3, [r3, #80] ; 0x50
- 8004b82: 687a ldr r2, [r7, #4]
- 8004b84: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 8004b86: 4610 mov r0, r2
- 8004b88: 4798 blx r3
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b8a: e00e b.n 8004baa <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004b8c: 6878 ldr r0, [r7, #4]
- 8004b8e: f000 f845 bl 8004c1c <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b92: e00a b.n 8004baa <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004b94: 6878 ldr r0, [r7, #4]
- 8004b96: f000 f841 bl 8004c1c <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004b9a: e006 b.n 8004baa <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004b9c: 6878 ldr r0, [r7, #4]
- 8004b9e: f000 f83d bl 8004c1c <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004ba2: 687b ldr r3, [r7, #4]
- 8004ba4: 2200 movs r2, #0
- 8004ba6: 67da str r2, [r3, #124] ; 0x7c
- }
- }
- return;
- 8004ba8: e025 b.n 8004bf6 <HAL_UART_IRQHandler+0x226>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004baa: bf00 nop
- return;
- 8004bac: e023 b.n 8004bf6 <HAL_UART_IRQHandler+0x226>
-
- } /* End if some error occurs */
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if (((isrflags & USART_ISR_TXE) != 0U)
- 8004bae: 69fb ldr r3, [r7, #28]
- 8004bb0: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004bb4: 2b00 cmp r3, #0
- 8004bb6: d00d beq.n 8004bd4 <HAL_UART_IRQHandler+0x204>
- && ((cr1its & USART_CR1_TXEIE) != 0U))
- 8004bb8: 69bb ldr r3, [r7, #24]
- 8004bba: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004bbe: 2b00 cmp r3, #0
- 8004bc0: d008 beq.n 8004bd4 <HAL_UART_IRQHandler+0x204>
- {
- if (huart->TxISR != NULL)
- 8004bc2: 687b ldr r3, [r7, #4]
- 8004bc4: 6e5b ldr r3, [r3, #100] ; 0x64
- 8004bc6: 2b00 cmp r3, #0
- 8004bc8: d017 beq.n 8004bfa <HAL_UART_IRQHandler+0x22a>
- {
- huart->TxISR(huart);
- 8004bca: 687b ldr r3, [r7, #4]
- 8004bcc: 6e5b ldr r3, [r3, #100] ; 0x64
- 8004bce: 6878 ldr r0, [r7, #4]
- 8004bd0: 4798 blx r3
- }
- return;
- 8004bd2: e012 b.n 8004bfa <HAL_UART_IRQHandler+0x22a>
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
- 8004bd4: 69fb ldr r3, [r7, #28]
- 8004bd6: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004bda: 2b00 cmp r3, #0
- 8004bdc: d00e beq.n 8004bfc <HAL_UART_IRQHandler+0x22c>
- 8004bde: 69bb ldr r3, [r7, #24]
- 8004be0: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004be4: 2b00 cmp r3, #0
- 8004be6: d009 beq.n 8004bfc <HAL_UART_IRQHandler+0x22c>
- {
- UART_EndTransmit_IT(huart);
- 8004be8: 6878 ldr r0, [r7, #4]
- 8004bea: f000 fc14 bl 8005416 <UART_EndTransmit_IT>
- return;
- 8004bee: bf00 nop
- 8004bf0: e004 b.n 8004bfc <HAL_UART_IRQHandler+0x22c>
- return;
- 8004bf2: bf00 nop
- 8004bf4: e002 b.n 8004bfc <HAL_UART_IRQHandler+0x22c>
- return;
- 8004bf6: bf00 nop
- 8004bf8: e000 b.n 8004bfc <HAL_UART_IRQHandler+0x22c>
- return;
- 8004bfa: bf00 nop
- }
-
-}
- 8004bfc: 3720 adds r7, #32
- 8004bfe: 46bd mov sp, r7
- 8004c00: bd80 pop {r7, pc}
- 8004c02: bf00 nop
- 8004c04: 080053eb .word 0x080053eb
-
-08004c08 <HAL_UART_TxCpltCallback>:
- * @brief Tx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- 8004c08: b480 push {r7}
- 8004c0a: b083 sub sp, #12
- 8004c0c: af00 add r7, sp, #0
- 8004c0e: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
- 8004c10: bf00 nop
- 8004c12: 370c adds r7, #12
- 8004c14: 46bd mov sp, r7
- 8004c16: f85d 7b04 ldr.w r7, [sp], #4
- 8004c1a: 4770 bx lr
-
-08004c1c <HAL_UART_ErrorCallback>:
- * @brief UART error callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- 8004c1c: b480 push {r7}
- 8004c1e: b083 sub sp, #12
- 8004c20: af00 add r7, sp, #0
- 8004c22: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file.
- */
-}
- 8004c24: bf00 nop
- 8004c26: 370c adds r7, #12
- 8004c28: 46bd mov sp, r7
- 8004c2a: f85d 7b04 ldr.w r7, [sp], #4
- 8004c2e: 4770 bx lr
-
-08004c30 <UART_SetConfig>:
- * @brief Configure the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- 8004c30: b580 push {r7, lr}
- 8004c32: b088 sub sp, #32
- 8004c34: af00 add r7, sp, #0
- 8004c36: 6078 str r0, [r7, #4]
- uint32_t tmpreg;
- uint16_t brrtemp;
- UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv = 0x00000000U;
- 8004c38: 2300 movs r3, #0
- 8004c3a: 61bb str r3, [r7, #24]
- HAL_StatusTypeDef ret = HAL_OK;
- 8004c3c: 2300 movs r3, #0
- 8004c3e: 75fb strb r3, [r7, #23]
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 8004c40: 687b ldr r3, [r7, #4]
- 8004c42: 689a ldr r2, [r3, #8]
- 8004c44: 687b ldr r3, [r7, #4]
- 8004c46: 691b ldr r3, [r3, #16]
- 8004c48: 431a orrs r2, r3
- 8004c4a: 687b ldr r3, [r7, #4]
- 8004c4c: 695b ldr r3, [r3, #20]
- 8004c4e: 431a orrs r2, r3
- 8004c50: 687b ldr r3, [r7, #4]
- 8004c52: 69db ldr r3, [r3, #28]
- 8004c54: 4313 orrs r3, r2
- 8004c56: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 8004c58: 687b ldr r3, [r7, #4]
- 8004c5a: 681b ldr r3, [r3, #0]
- 8004c5c: 681a ldr r2, [r3, #0]
- 8004c5e: 4bb1 ldr r3, [pc, #708] ; (8004f24 <UART_SetConfig+0x2f4>)
- 8004c60: 4013 ands r3, r2
- 8004c62: 687a ldr r2, [r7, #4]
- 8004c64: 6812 ldr r2, [r2, #0]
- 8004c66: 6939 ldr r1, [r7, #16]
- 8004c68: 430b orrs r3, r1
- 8004c6a: 6013 str r3, [r2, #0]
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8004c6c: 687b ldr r3, [r7, #4]
- 8004c6e: 681b ldr r3, [r3, #0]
- 8004c70: 685b ldr r3, [r3, #4]
- 8004c72: f423 5140 bic.w r1, r3, #12288 ; 0x3000
- 8004c76: 687b ldr r3, [r7, #4]
- 8004c78: 68da ldr r2, [r3, #12]
- 8004c7a: 687b ldr r3, [r7, #4]
- 8004c7c: 681b ldr r3, [r3, #0]
- 8004c7e: 430a orrs r2, r1
- 8004c80: 605a str r2, [r3, #4]
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling (not applicable to LPUART) */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8004c82: 687b ldr r3, [r7, #4]
- 8004c84: 699b ldr r3, [r3, #24]
- 8004c86: 613b str r3, [r7, #16]
-
- tmpreg |= huart->Init.OneBitSampling;
- 8004c88: 687b ldr r3, [r7, #4]
- 8004c8a: 6a1b ldr r3, [r3, #32]
- 8004c8c: 693a ldr r2, [r7, #16]
- 8004c8e: 4313 orrs r3, r2
- 8004c90: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8004c92: 687b ldr r3, [r7, #4]
- 8004c94: 681b ldr r3, [r3, #0]
- 8004c96: 689b ldr r3, [r3, #8]
- 8004c98: f423 6130 bic.w r1, r3, #2816 ; 0xb00
- 8004c9c: 687b ldr r3, [r7, #4]
- 8004c9e: 681b ldr r3, [r3, #0]
- 8004ca0: 693a ldr r2, [r7, #16]
- 8004ca2: 430a orrs r2, r1
- 8004ca4: 609a str r2, [r3, #8]
-
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
- 8004ca6: 687b ldr r3, [r7, #4]
- 8004ca8: 681b ldr r3, [r3, #0]
- 8004caa: 4a9f ldr r2, [pc, #636] ; (8004f28 <UART_SetConfig+0x2f8>)
- 8004cac: 4293 cmp r3, r2
- 8004cae: d121 bne.n 8004cf4 <UART_SetConfig+0xc4>
- 8004cb0: 4b9e ldr r3, [pc, #632] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004cb2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004cb6: f003 0303 and.w r3, r3, #3
- 8004cba: 2b03 cmp r3, #3
- 8004cbc: d816 bhi.n 8004cec <UART_SetConfig+0xbc>
- 8004cbe: a201 add r2, pc, #4 ; (adr r2, 8004cc4 <UART_SetConfig+0x94>)
- 8004cc0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004cc4: 08004cd5 .word 0x08004cd5
- 8004cc8: 08004ce1 .word 0x08004ce1
- 8004ccc: 08004cdb .word 0x08004cdb
- 8004cd0: 08004ce7 .word 0x08004ce7
- 8004cd4: 2301 movs r3, #1
- 8004cd6: 77fb strb r3, [r7, #31]
- 8004cd8: e151 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004cda: 2302 movs r3, #2
- 8004cdc: 77fb strb r3, [r7, #31]
- 8004cde: e14e b.n 8004f7e <UART_SetConfig+0x34e>
- 8004ce0: 2304 movs r3, #4
- 8004ce2: 77fb strb r3, [r7, #31]
- 8004ce4: e14b b.n 8004f7e <UART_SetConfig+0x34e>
- 8004ce6: 2308 movs r3, #8
- 8004ce8: 77fb strb r3, [r7, #31]
- 8004cea: e148 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004cec: 2310 movs r3, #16
- 8004cee: 77fb strb r3, [r7, #31]
- 8004cf0: bf00 nop
- 8004cf2: e144 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004cf4: 687b ldr r3, [r7, #4]
- 8004cf6: 681b ldr r3, [r3, #0]
- 8004cf8: 4a8d ldr r2, [pc, #564] ; (8004f30 <UART_SetConfig+0x300>)
- 8004cfa: 4293 cmp r3, r2
- 8004cfc: d134 bne.n 8004d68 <UART_SetConfig+0x138>
- 8004cfe: 4b8b ldr r3, [pc, #556] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004d00: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004d04: f003 030c and.w r3, r3, #12
- 8004d08: 2b0c cmp r3, #12
- 8004d0a: d829 bhi.n 8004d60 <UART_SetConfig+0x130>
- 8004d0c: a201 add r2, pc, #4 ; (adr r2, 8004d14 <UART_SetConfig+0xe4>)
- 8004d0e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004d12: bf00 nop
- 8004d14: 08004d49 .word 0x08004d49
- 8004d18: 08004d61 .word 0x08004d61
- 8004d1c: 08004d61 .word 0x08004d61
- 8004d20: 08004d61 .word 0x08004d61
- 8004d24: 08004d55 .word 0x08004d55
- 8004d28: 08004d61 .word 0x08004d61
- 8004d2c: 08004d61 .word 0x08004d61
- 8004d30: 08004d61 .word 0x08004d61
- 8004d34: 08004d4f .word 0x08004d4f
- 8004d38: 08004d61 .word 0x08004d61
- 8004d3c: 08004d61 .word 0x08004d61
- 8004d40: 08004d61 .word 0x08004d61
- 8004d44: 08004d5b .word 0x08004d5b
- 8004d48: 2300 movs r3, #0
- 8004d4a: 77fb strb r3, [r7, #31]
- 8004d4c: e117 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004d4e: 2302 movs r3, #2
- 8004d50: 77fb strb r3, [r7, #31]
- 8004d52: e114 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004d54: 2304 movs r3, #4
- 8004d56: 77fb strb r3, [r7, #31]
- 8004d58: e111 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004d5a: 2308 movs r3, #8
- 8004d5c: 77fb strb r3, [r7, #31]
- 8004d5e: e10e b.n 8004f7e <UART_SetConfig+0x34e>
- 8004d60: 2310 movs r3, #16
- 8004d62: 77fb strb r3, [r7, #31]
- 8004d64: bf00 nop
- 8004d66: e10a b.n 8004f7e <UART_SetConfig+0x34e>
- 8004d68: 687b ldr r3, [r7, #4]
- 8004d6a: 681b ldr r3, [r3, #0]
- 8004d6c: 4a71 ldr r2, [pc, #452] ; (8004f34 <UART_SetConfig+0x304>)
- 8004d6e: 4293 cmp r3, r2
- 8004d70: d120 bne.n 8004db4 <UART_SetConfig+0x184>
- 8004d72: 4b6e ldr r3, [pc, #440] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004d74: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004d78: f003 0330 and.w r3, r3, #48 ; 0x30
- 8004d7c: 2b10 cmp r3, #16
- 8004d7e: d00f beq.n 8004da0 <UART_SetConfig+0x170>
- 8004d80: 2b10 cmp r3, #16
- 8004d82: d802 bhi.n 8004d8a <UART_SetConfig+0x15a>
- 8004d84: 2b00 cmp r3, #0
- 8004d86: d005 beq.n 8004d94 <UART_SetConfig+0x164>
- 8004d88: e010 b.n 8004dac <UART_SetConfig+0x17c>
- 8004d8a: 2b20 cmp r3, #32
- 8004d8c: d005 beq.n 8004d9a <UART_SetConfig+0x16a>
- 8004d8e: 2b30 cmp r3, #48 ; 0x30
- 8004d90: d009 beq.n 8004da6 <UART_SetConfig+0x176>
- 8004d92: e00b b.n 8004dac <UART_SetConfig+0x17c>
- 8004d94: 2300 movs r3, #0
- 8004d96: 77fb strb r3, [r7, #31]
- 8004d98: e0f1 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004d9a: 2302 movs r3, #2
- 8004d9c: 77fb strb r3, [r7, #31]
- 8004d9e: e0ee b.n 8004f7e <UART_SetConfig+0x34e>
- 8004da0: 2304 movs r3, #4
- 8004da2: 77fb strb r3, [r7, #31]
- 8004da4: e0eb b.n 8004f7e <UART_SetConfig+0x34e>
- 8004da6: 2308 movs r3, #8
- 8004da8: 77fb strb r3, [r7, #31]
- 8004daa: e0e8 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004dac: 2310 movs r3, #16
- 8004dae: 77fb strb r3, [r7, #31]
- 8004db0: bf00 nop
- 8004db2: e0e4 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004db4: 687b ldr r3, [r7, #4]
- 8004db6: 681b ldr r3, [r3, #0]
- 8004db8: 4a5f ldr r2, [pc, #380] ; (8004f38 <UART_SetConfig+0x308>)
- 8004dba: 4293 cmp r3, r2
- 8004dbc: d120 bne.n 8004e00 <UART_SetConfig+0x1d0>
- 8004dbe: 4b5b ldr r3, [pc, #364] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004dc0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004dc4: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 8004dc8: 2b40 cmp r3, #64 ; 0x40
- 8004dca: d00f beq.n 8004dec <UART_SetConfig+0x1bc>
- 8004dcc: 2b40 cmp r3, #64 ; 0x40
- 8004dce: d802 bhi.n 8004dd6 <UART_SetConfig+0x1a6>
- 8004dd0: 2b00 cmp r3, #0
- 8004dd2: d005 beq.n 8004de0 <UART_SetConfig+0x1b0>
- 8004dd4: e010 b.n 8004df8 <UART_SetConfig+0x1c8>
- 8004dd6: 2b80 cmp r3, #128 ; 0x80
- 8004dd8: d005 beq.n 8004de6 <UART_SetConfig+0x1b6>
- 8004dda: 2bc0 cmp r3, #192 ; 0xc0
- 8004ddc: d009 beq.n 8004df2 <UART_SetConfig+0x1c2>
- 8004dde: e00b b.n 8004df8 <UART_SetConfig+0x1c8>
- 8004de0: 2300 movs r3, #0
- 8004de2: 77fb strb r3, [r7, #31]
- 8004de4: e0cb b.n 8004f7e <UART_SetConfig+0x34e>
- 8004de6: 2302 movs r3, #2
- 8004de8: 77fb strb r3, [r7, #31]
- 8004dea: e0c8 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004dec: 2304 movs r3, #4
- 8004dee: 77fb strb r3, [r7, #31]
- 8004df0: e0c5 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004df2: 2308 movs r3, #8
- 8004df4: 77fb strb r3, [r7, #31]
- 8004df6: e0c2 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004df8: 2310 movs r3, #16
- 8004dfa: 77fb strb r3, [r7, #31]
- 8004dfc: bf00 nop
- 8004dfe: e0be b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e00: 687b ldr r3, [r7, #4]
- 8004e02: 681b ldr r3, [r3, #0]
- 8004e04: 4a4d ldr r2, [pc, #308] ; (8004f3c <UART_SetConfig+0x30c>)
- 8004e06: 4293 cmp r3, r2
- 8004e08: d124 bne.n 8004e54 <UART_SetConfig+0x224>
- 8004e0a: 4b48 ldr r3, [pc, #288] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004e0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004e10: f403 7340 and.w r3, r3, #768 ; 0x300
- 8004e14: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004e18: d012 beq.n 8004e40 <UART_SetConfig+0x210>
- 8004e1a: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004e1e: d802 bhi.n 8004e26 <UART_SetConfig+0x1f6>
- 8004e20: 2b00 cmp r3, #0
- 8004e22: d007 beq.n 8004e34 <UART_SetConfig+0x204>
- 8004e24: e012 b.n 8004e4c <UART_SetConfig+0x21c>
- 8004e26: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 8004e2a: d006 beq.n 8004e3a <UART_SetConfig+0x20a>
- 8004e2c: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8004e30: d009 beq.n 8004e46 <UART_SetConfig+0x216>
- 8004e32: e00b b.n 8004e4c <UART_SetConfig+0x21c>
- 8004e34: 2300 movs r3, #0
- 8004e36: 77fb strb r3, [r7, #31]
- 8004e38: e0a1 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e3a: 2302 movs r3, #2
- 8004e3c: 77fb strb r3, [r7, #31]
- 8004e3e: e09e b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e40: 2304 movs r3, #4
- 8004e42: 77fb strb r3, [r7, #31]
- 8004e44: e09b b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e46: 2308 movs r3, #8
- 8004e48: 77fb strb r3, [r7, #31]
- 8004e4a: e098 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e4c: 2310 movs r3, #16
- 8004e4e: 77fb strb r3, [r7, #31]
- 8004e50: bf00 nop
- 8004e52: e094 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e54: 687b ldr r3, [r7, #4]
- 8004e56: 681b ldr r3, [r3, #0]
- 8004e58: 4a39 ldr r2, [pc, #228] ; (8004f40 <UART_SetConfig+0x310>)
- 8004e5a: 4293 cmp r3, r2
- 8004e5c: d124 bne.n 8004ea8 <UART_SetConfig+0x278>
- 8004e5e: 4b33 ldr r3, [pc, #204] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004e60: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004e64: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 8004e68: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004e6c: d012 beq.n 8004e94 <UART_SetConfig+0x264>
- 8004e6e: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004e72: d802 bhi.n 8004e7a <UART_SetConfig+0x24a>
- 8004e74: 2b00 cmp r3, #0
- 8004e76: d007 beq.n 8004e88 <UART_SetConfig+0x258>
- 8004e78: e012 b.n 8004ea0 <UART_SetConfig+0x270>
- 8004e7a: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 8004e7e: d006 beq.n 8004e8e <UART_SetConfig+0x25e>
- 8004e80: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 8004e84: d009 beq.n 8004e9a <UART_SetConfig+0x26a>
- 8004e86: e00b b.n 8004ea0 <UART_SetConfig+0x270>
- 8004e88: 2301 movs r3, #1
- 8004e8a: 77fb strb r3, [r7, #31]
- 8004e8c: e077 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e8e: 2302 movs r3, #2
- 8004e90: 77fb strb r3, [r7, #31]
- 8004e92: e074 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e94: 2304 movs r3, #4
- 8004e96: 77fb strb r3, [r7, #31]
- 8004e98: e071 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004e9a: 2308 movs r3, #8
- 8004e9c: 77fb strb r3, [r7, #31]
- 8004e9e: e06e b.n 8004f7e <UART_SetConfig+0x34e>
- 8004ea0: 2310 movs r3, #16
- 8004ea2: 77fb strb r3, [r7, #31]
- 8004ea4: bf00 nop
- 8004ea6: e06a b.n 8004f7e <UART_SetConfig+0x34e>
- 8004ea8: 687b ldr r3, [r7, #4]
- 8004eaa: 681b ldr r3, [r3, #0]
- 8004eac: 4a25 ldr r2, [pc, #148] ; (8004f44 <UART_SetConfig+0x314>)
- 8004eae: 4293 cmp r3, r2
- 8004eb0: d124 bne.n 8004efc <UART_SetConfig+0x2cc>
- 8004eb2: 4b1e ldr r3, [pc, #120] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004eb4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004eb8: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 8004ebc: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004ec0: d012 beq.n 8004ee8 <UART_SetConfig+0x2b8>
- 8004ec2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004ec6: d802 bhi.n 8004ece <UART_SetConfig+0x29e>
- 8004ec8: 2b00 cmp r3, #0
- 8004eca: d007 beq.n 8004edc <UART_SetConfig+0x2ac>
- 8004ecc: e012 b.n 8004ef4 <UART_SetConfig+0x2c4>
- 8004ece: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8004ed2: d006 beq.n 8004ee2 <UART_SetConfig+0x2b2>
- 8004ed4: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 8004ed8: d009 beq.n 8004eee <UART_SetConfig+0x2be>
- 8004eda: e00b b.n 8004ef4 <UART_SetConfig+0x2c4>
- 8004edc: 2300 movs r3, #0
- 8004ede: 77fb strb r3, [r7, #31]
- 8004ee0: e04d b.n 8004f7e <UART_SetConfig+0x34e>
- 8004ee2: 2302 movs r3, #2
- 8004ee4: 77fb strb r3, [r7, #31]
- 8004ee6: e04a b.n 8004f7e <UART_SetConfig+0x34e>
- 8004ee8: 2304 movs r3, #4
- 8004eea: 77fb strb r3, [r7, #31]
- 8004eec: e047 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004eee: 2308 movs r3, #8
- 8004ef0: 77fb strb r3, [r7, #31]
- 8004ef2: e044 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004ef4: 2310 movs r3, #16
- 8004ef6: 77fb strb r3, [r7, #31]
- 8004ef8: bf00 nop
- 8004efa: e040 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004efc: 687b ldr r3, [r7, #4]
- 8004efe: 681b ldr r3, [r3, #0]
- 8004f00: 4a11 ldr r2, [pc, #68] ; (8004f48 <UART_SetConfig+0x318>)
- 8004f02: 4293 cmp r3, r2
- 8004f04: d139 bne.n 8004f7a <UART_SetConfig+0x34a>
- 8004f06: 4b09 ldr r3, [pc, #36] ; (8004f2c <UART_SetConfig+0x2fc>)
- 8004f08: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004f0c: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8004f10: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004f14: d027 beq.n 8004f66 <UART_SetConfig+0x336>
- 8004f16: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004f1a: d817 bhi.n 8004f4c <UART_SetConfig+0x31c>
- 8004f1c: 2b00 cmp r3, #0
- 8004f1e: d01c beq.n 8004f5a <UART_SetConfig+0x32a>
- 8004f20: e027 b.n 8004f72 <UART_SetConfig+0x342>
- 8004f22: bf00 nop
- 8004f24: efff69f3 .word 0xefff69f3
- 8004f28: 40011000 .word 0x40011000
- 8004f2c: 40023800 .word 0x40023800
- 8004f30: 40004400 .word 0x40004400
- 8004f34: 40004800 .word 0x40004800
- 8004f38: 40004c00 .word 0x40004c00
- 8004f3c: 40005000 .word 0x40005000
- 8004f40: 40011400 .word 0x40011400
- 8004f44: 40007800 .word 0x40007800
- 8004f48: 40007c00 .word 0x40007c00
- 8004f4c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004f50: d006 beq.n 8004f60 <UART_SetConfig+0x330>
- 8004f52: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 8004f56: d009 beq.n 8004f6c <UART_SetConfig+0x33c>
- 8004f58: e00b b.n 8004f72 <UART_SetConfig+0x342>
- 8004f5a: 2300 movs r3, #0
- 8004f5c: 77fb strb r3, [r7, #31]
- 8004f5e: e00e b.n 8004f7e <UART_SetConfig+0x34e>
- 8004f60: 2302 movs r3, #2
- 8004f62: 77fb strb r3, [r7, #31]
- 8004f64: e00b b.n 8004f7e <UART_SetConfig+0x34e>
- 8004f66: 2304 movs r3, #4
- 8004f68: 77fb strb r3, [r7, #31]
- 8004f6a: e008 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004f6c: 2308 movs r3, #8
- 8004f6e: 77fb strb r3, [r7, #31]
- 8004f70: e005 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004f72: 2310 movs r3, #16
- 8004f74: 77fb strb r3, [r7, #31]
- 8004f76: bf00 nop
- 8004f78: e001 b.n 8004f7e <UART_SetConfig+0x34e>
- 8004f7a: 2310 movs r3, #16
- 8004f7c: 77fb strb r3, [r7, #31]
-
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8004f7e: 687b ldr r3, [r7, #4]
- 8004f80: 69db ldr r3, [r3, #28]
- 8004f82: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004f86: d17c bne.n 8005082 <UART_SetConfig+0x452>
- {
- switch (clocksource)
- 8004f88: 7ffb ldrb r3, [r7, #31]
- 8004f8a: 2b08 cmp r3, #8
- 8004f8c: d859 bhi.n 8005042 <UART_SetConfig+0x412>
- 8004f8e: a201 add r2, pc, #4 ; (adr r2, 8004f94 <UART_SetConfig+0x364>)
- 8004f90: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004f94: 08004fb9 .word 0x08004fb9
- 8004f98: 08004fd7 .word 0x08004fd7
- 8004f9c: 08004ff5 .word 0x08004ff5
- 8004fa0: 08005043 .word 0x08005043
- 8004fa4: 0800500d .word 0x0800500d
- 8004fa8: 08005043 .word 0x08005043
- 8004fac: 08005043 .word 0x08005043
- 8004fb0: 08005043 .word 0x08005043
- 8004fb4: 0800502b .word 0x0800502b
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004fb8: f7fd fe50 bl 8002c5c <HAL_RCC_GetPCLK1Freq>
- 8004fbc: 4603 mov r3, r0
- 8004fbe: 005a lsls r2, r3, #1
- 8004fc0: 687b ldr r3, [r7, #4]
- 8004fc2: 685b ldr r3, [r3, #4]
- 8004fc4: 085b lsrs r3, r3, #1
- 8004fc6: 441a add r2, r3
- 8004fc8: 687b ldr r3, [r7, #4]
- 8004fca: 685b ldr r3, [r3, #4]
- 8004fcc: fbb2 f3f3 udiv r3, r2, r3
- 8004fd0: b29b uxth r3, r3
- 8004fd2: 61bb str r3, [r7, #24]
- break;
- 8004fd4: e038 b.n 8005048 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004fd6: f7fd fe55 bl 8002c84 <HAL_RCC_GetPCLK2Freq>
- 8004fda: 4603 mov r3, r0
- 8004fdc: 005a lsls r2, r3, #1
- 8004fde: 687b ldr r3, [r7, #4]
- 8004fe0: 685b ldr r3, [r3, #4]
- 8004fe2: 085b lsrs r3, r3, #1
- 8004fe4: 441a add r2, r3
- 8004fe6: 687b ldr r3, [r7, #4]
- 8004fe8: 685b ldr r3, [r3, #4]
- 8004fea: fbb2 f3f3 udiv r3, r2, r3
- 8004fee: b29b uxth r3, r3
- 8004ff0: 61bb str r3, [r7, #24]
- break;
- 8004ff2: e029 b.n 8005048 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8004ff4: 687b ldr r3, [r7, #4]
- 8004ff6: 685b ldr r3, [r3, #4]
- 8004ff8: 085a lsrs r2, r3, #1
- 8004ffa: 4b5d ldr r3, [pc, #372] ; (8005170 <UART_SetConfig+0x540>)
- 8004ffc: 4413 add r3, r2
- 8004ffe: 687a ldr r2, [r7, #4]
- 8005000: 6852 ldr r2, [r2, #4]
- 8005002: fbb3 f3f2 udiv r3, r3, r2
- 8005006: b29b uxth r3, r3
- 8005008: 61bb str r3, [r7, #24]
- break;
- 800500a: e01d b.n 8005048 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 800500c: f7fd fd68 bl 8002ae0 <HAL_RCC_GetSysClockFreq>
- 8005010: 4603 mov r3, r0
- 8005012: 005a lsls r2, r3, #1
- 8005014: 687b ldr r3, [r7, #4]
- 8005016: 685b ldr r3, [r3, #4]
- 8005018: 085b lsrs r3, r3, #1
- 800501a: 441a add r2, r3
- 800501c: 687b ldr r3, [r7, #4]
- 800501e: 685b ldr r3, [r3, #4]
- 8005020: fbb2 f3f3 udiv r3, r2, r3
- 8005024: b29b uxth r3, r3
- 8005026: 61bb str r3, [r7, #24]
- break;
- 8005028: e00e b.n 8005048 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 800502a: 687b ldr r3, [r7, #4]
- 800502c: 685b ldr r3, [r3, #4]
- 800502e: 085b lsrs r3, r3, #1
- 8005030: f503 3280 add.w r2, r3, #65536 ; 0x10000
- 8005034: 687b ldr r3, [r7, #4]
- 8005036: 685b ldr r3, [r3, #4]
- 8005038: fbb2 f3f3 udiv r3, r2, r3
- 800503c: b29b uxth r3, r3
- 800503e: 61bb str r3, [r7, #24]
- break;
- 8005040: e002 b.n 8005048 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8005042: 2301 movs r3, #1
- 8005044: 75fb strb r3, [r7, #23]
- break;
- 8005046: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8005048: 69bb ldr r3, [r7, #24]
- 800504a: 2b0f cmp r3, #15
- 800504c: d916 bls.n 800507c <UART_SetConfig+0x44c>
- 800504e: 69bb ldr r3, [r7, #24]
- 8005050: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8005054: d212 bcs.n 800507c <UART_SetConfig+0x44c>
- {
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 8005056: 69bb ldr r3, [r7, #24]
- 8005058: b29b uxth r3, r3
- 800505a: f023 030f bic.w r3, r3, #15
- 800505e: 81fb strh r3, [r7, #14]
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8005060: 69bb ldr r3, [r7, #24]
- 8005062: 085b lsrs r3, r3, #1
- 8005064: b29b uxth r3, r3
- 8005066: f003 0307 and.w r3, r3, #7
- 800506a: b29a uxth r2, r3
- 800506c: 89fb ldrh r3, [r7, #14]
- 800506e: 4313 orrs r3, r2
- 8005070: 81fb strh r3, [r7, #14]
- huart->Instance->BRR = brrtemp;
- 8005072: 687b ldr r3, [r7, #4]
- 8005074: 681b ldr r3, [r3, #0]
- 8005076: 89fa ldrh r2, [r7, #14]
- 8005078: 60da str r2, [r3, #12]
- 800507a: e06e b.n 800515a <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 800507c: 2301 movs r3, #1
- 800507e: 75fb strb r3, [r7, #23]
- 8005080: e06b b.n 800515a <UART_SetConfig+0x52a>
- }
- }
- else
- {
- switch (clocksource)
- 8005082: 7ffb ldrb r3, [r7, #31]
- 8005084: 2b08 cmp r3, #8
- 8005086: d857 bhi.n 8005138 <UART_SetConfig+0x508>
- 8005088: a201 add r2, pc, #4 ; (adr r2, 8005090 <UART_SetConfig+0x460>)
- 800508a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 800508e: bf00 nop
- 8005090: 080050b5 .word 0x080050b5
- 8005094: 080050d1 .word 0x080050d1
- 8005098: 080050ed .word 0x080050ed
- 800509c: 08005139 .word 0x08005139
- 80050a0: 08005105 .word 0x08005105
- 80050a4: 08005139 .word 0x08005139
- 80050a8: 08005139 .word 0x08005139
- 80050ac: 08005139 .word 0x08005139
- 80050b0: 08005121 .word 0x08005121
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 80050b4: f7fd fdd2 bl 8002c5c <HAL_RCC_GetPCLK1Freq>
- 80050b8: 4602 mov r2, r0
- 80050ba: 687b ldr r3, [r7, #4]
- 80050bc: 685b ldr r3, [r3, #4]
- 80050be: 085b lsrs r3, r3, #1
- 80050c0: 441a add r2, r3
- 80050c2: 687b ldr r3, [r7, #4]
- 80050c4: 685b ldr r3, [r3, #4]
- 80050c6: fbb2 f3f3 udiv r3, r2, r3
- 80050ca: b29b uxth r3, r3
- 80050cc: 61bb str r3, [r7, #24]
- break;
- 80050ce: e036 b.n 800513e <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 80050d0: f7fd fdd8 bl 8002c84 <HAL_RCC_GetPCLK2Freq>
- 80050d4: 4602 mov r2, r0
- 80050d6: 687b ldr r3, [r7, #4]
- 80050d8: 685b ldr r3, [r3, #4]
- 80050da: 085b lsrs r3, r3, #1
- 80050dc: 441a add r2, r3
- 80050de: 687b ldr r3, [r7, #4]
- 80050e0: 685b ldr r3, [r3, #4]
- 80050e2: fbb2 f3f3 udiv r3, r2, r3
- 80050e6: b29b uxth r3, r3
- 80050e8: 61bb str r3, [r7, #24]
- break;
- 80050ea: e028 b.n 800513e <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 80050ec: 687b ldr r3, [r7, #4]
- 80050ee: 685b ldr r3, [r3, #4]
- 80050f0: 085a lsrs r2, r3, #1
- 80050f2: 4b20 ldr r3, [pc, #128] ; (8005174 <UART_SetConfig+0x544>)
- 80050f4: 4413 add r3, r2
- 80050f6: 687a ldr r2, [r7, #4]
- 80050f8: 6852 ldr r2, [r2, #4]
- 80050fa: fbb3 f3f2 udiv r3, r3, r2
- 80050fe: b29b uxth r3, r3
- 8005100: 61bb str r3, [r7, #24]
- break;
- 8005102: e01c b.n 800513e <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8005104: f7fd fcec bl 8002ae0 <HAL_RCC_GetSysClockFreq>
- 8005108: 4602 mov r2, r0
- 800510a: 687b ldr r3, [r7, #4]
- 800510c: 685b ldr r3, [r3, #4]
- 800510e: 085b lsrs r3, r3, #1
- 8005110: 441a add r2, r3
- 8005112: 687b ldr r3, [r7, #4]
- 8005114: 685b ldr r3, [r3, #4]
- 8005116: fbb2 f3f3 udiv r3, r2, r3
- 800511a: b29b uxth r3, r3
- 800511c: 61bb str r3, [r7, #24]
- break;
- 800511e: e00e b.n 800513e <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 8005120: 687b ldr r3, [r7, #4]
- 8005122: 685b ldr r3, [r3, #4]
- 8005124: 085b lsrs r3, r3, #1
- 8005126: f503 4200 add.w r2, r3, #32768 ; 0x8000
- 800512a: 687b ldr r3, [r7, #4]
- 800512c: 685b ldr r3, [r3, #4]
- 800512e: fbb2 f3f3 udiv r3, r2, r3
- 8005132: b29b uxth r3, r3
- 8005134: 61bb str r3, [r7, #24]
- break;
- 8005136: e002 b.n 800513e <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8005138: 2301 movs r3, #1
- 800513a: 75fb strb r3, [r7, #23]
- break;
- 800513c: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 800513e: 69bb ldr r3, [r7, #24]
- 8005140: 2b0f cmp r3, #15
- 8005142: d908 bls.n 8005156 <UART_SetConfig+0x526>
- 8005144: 69bb ldr r3, [r7, #24]
- 8005146: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800514a: d204 bcs.n 8005156 <UART_SetConfig+0x526>
- {
- huart->Instance->BRR = usartdiv;
- 800514c: 687b ldr r3, [r7, #4]
- 800514e: 681b ldr r3, [r3, #0]
- 8005150: 69ba ldr r2, [r7, #24]
- 8005152: 60da str r2, [r3, #12]
- 8005154: e001 b.n 800515a <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 8005156: 2301 movs r3, #1
- 8005158: 75fb strb r3, [r7, #23]
- }
- }
-
-
- /* Clear ISR function pointers */
- huart->RxISR = NULL;
- 800515a: 687b ldr r3, [r7, #4]
- 800515c: 2200 movs r2, #0
- 800515e: 661a str r2, [r3, #96] ; 0x60
- huart->TxISR = NULL;
- 8005160: 687b ldr r3, [r7, #4]
- 8005162: 2200 movs r2, #0
- 8005164: 665a str r2, [r3, #100] ; 0x64
-
- return ret;
- 8005166: 7dfb ldrb r3, [r7, #23]
-}
- 8005168: 4618 mov r0, r3
- 800516a: 3720 adds r7, #32
- 800516c: 46bd mov sp, r7
- 800516e: bd80 pop {r7, pc}
- 8005170: 01e84800 .word 0x01e84800
- 8005174: 00f42400 .word 0x00f42400
-
-08005178 <UART_AdvFeatureConfig>:
- * @brief Configure the UART peripheral advanced features.
- * @param huart UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- 8005178: b480 push {r7}
- 800517a: b083 sub sp, #12
- 800517c: af00 add r7, sp, #0
- 800517e: 6078 str r0, [r7, #4]
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 8005180: 687b ldr r3, [r7, #4]
- 8005182: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005184: f003 0301 and.w r3, r3, #1
- 8005188: 2b00 cmp r3, #0
- 800518a: d00a beq.n 80051a2 <UART_AdvFeatureConfig+0x2a>
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 800518c: 687b ldr r3, [r7, #4]
- 800518e: 681b ldr r3, [r3, #0]
- 8005190: 685b ldr r3, [r3, #4]
- 8005192: f423 3100 bic.w r1, r3, #131072 ; 0x20000
- 8005196: 687b ldr r3, [r7, #4]
- 8005198: 6a9a ldr r2, [r3, #40] ; 0x28
- 800519a: 687b ldr r3, [r7, #4]
- 800519c: 681b ldr r3, [r3, #0]
- 800519e: 430a orrs r2, r1
- 80051a0: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 80051a2: 687b ldr r3, [r7, #4]
- 80051a4: 6a5b ldr r3, [r3, #36] ; 0x24
- 80051a6: f003 0302 and.w r3, r3, #2
- 80051aa: 2b00 cmp r3, #0
- 80051ac: d00a beq.n 80051c4 <UART_AdvFeatureConfig+0x4c>
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 80051ae: 687b ldr r3, [r7, #4]
- 80051b0: 681b ldr r3, [r3, #0]
- 80051b2: 685b ldr r3, [r3, #4]
- 80051b4: f423 3180 bic.w r1, r3, #65536 ; 0x10000
- 80051b8: 687b ldr r3, [r7, #4]
- 80051ba: 6ada ldr r2, [r3, #44] ; 0x2c
- 80051bc: 687b ldr r3, [r7, #4]
- 80051be: 681b ldr r3, [r3, #0]
- 80051c0: 430a orrs r2, r1
- 80051c2: 605a str r2, [r3, #4]
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 80051c4: 687b ldr r3, [r7, #4]
- 80051c6: 6a5b ldr r3, [r3, #36] ; 0x24
- 80051c8: f003 0304 and.w r3, r3, #4
- 80051cc: 2b00 cmp r3, #0
- 80051ce: d00a beq.n 80051e6 <UART_AdvFeatureConfig+0x6e>
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 80051d0: 687b ldr r3, [r7, #4]
- 80051d2: 681b ldr r3, [r3, #0]
- 80051d4: 685b ldr r3, [r3, #4]
- 80051d6: f423 2180 bic.w r1, r3, #262144 ; 0x40000
- 80051da: 687b ldr r3, [r7, #4]
- 80051dc: 6b1a ldr r2, [r3, #48] ; 0x30
- 80051de: 687b ldr r3, [r7, #4]
- 80051e0: 681b ldr r3, [r3, #0]
- 80051e2: 430a orrs r2, r1
- 80051e4: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 80051e6: 687b ldr r3, [r7, #4]
- 80051e8: 6a5b ldr r3, [r3, #36] ; 0x24
- 80051ea: f003 0308 and.w r3, r3, #8
- 80051ee: 2b00 cmp r3, #0
- 80051f0: d00a beq.n 8005208 <UART_AdvFeatureConfig+0x90>
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 80051f2: 687b ldr r3, [r7, #4]
- 80051f4: 681b ldr r3, [r3, #0]
- 80051f6: 685b ldr r3, [r3, #4]
- 80051f8: f423 4100 bic.w r1, r3, #32768 ; 0x8000
- 80051fc: 687b ldr r3, [r7, #4]
- 80051fe: 6b5a ldr r2, [r3, #52] ; 0x34
- 8005200: 687b ldr r3, [r7, #4]
- 8005202: 681b ldr r3, [r3, #0]
- 8005204: 430a orrs r2, r1
- 8005206: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 8005208: 687b ldr r3, [r7, #4]
- 800520a: 6a5b ldr r3, [r3, #36] ; 0x24
- 800520c: f003 0310 and.w r3, r3, #16
- 8005210: 2b00 cmp r3, #0
- 8005212: d00a beq.n 800522a <UART_AdvFeatureConfig+0xb2>
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 8005214: 687b ldr r3, [r7, #4]
- 8005216: 681b ldr r3, [r3, #0]
- 8005218: 689b ldr r3, [r3, #8]
- 800521a: f423 5180 bic.w r1, r3, #4096 ; 0x1000
- 800521e: 687b ldr r3, [r7, #4]
- 8005220: 6b9a ldr r2, [r3, #56] ; 0x38
- 8005222: 687b ldr r3, [r7, #4]
- 8005224: 681b ldr r3, [r3, #0]
- 8005226: 430a orrs r2, r1
- 8005228: 609a str r2, [r3, #8]
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 800522a: 687b ldr r3, [r7, #4]
- 800522c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800522e: f003 0320 and.w r3, r3, #32
- 8005232: 2b00 cmp r3, #0
- 8005234: d00a beq.n 800524c <UART_AdvFeatureConfig+0xd4>
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 8005236: 687b ldr r3, [r7, #4]
- 8005238: 681b ldr r3, [r3, #0]
- 800523a: 689b ldr r3, [r3, #8]
- 800523c: f423 5100 bic.w r1, r3, #8192 ; 0x2000
- 8005240: 687b ldr r3, [r7, #4]
- 8005242: 6bda ldr r2, [r3, #60] ; 0x3c
- 8005244: 687b ldr r3, [r7, #4]
- 8005246: 681b ldr r3, [r3, #0]
- 8005248: 430a orrs r2, r1
- 800524a: 609a str r2, [r3, #8]
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 800524c: 687b ldr r3, [r7, #4]
- 800524e: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005250: f003 0340 and.w r3, r3, #64 ; 0x40
- 8005254: 2b00 cmp r3, #0
- 8005256: d01a beq.n 800528e <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 8005258: 687b ldr r3, [r7, #4]
- 800525a: 681b ldr r3, [r3, #0]
- 800525c: 685b ldr r3, [r3, #4]
- 800525e: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
- 8005262: 687b ldr r3, [r7, #4]
- 8005264: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005266: 687b ldr r3, [r7, #4]
- 8005268: 681b ldr r3, [r3, #0]
- 800526a: 430a orrs r2, r1
- 800526c: 605a str r2, [r3, #4]
- /* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 800526e: 687b ldr r3, [r7, #4]
- 8005270: 6c1b ldr r3, [r3, #64] ; 0x40
- 8005272: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8005276: d10a bne.n 800528e <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8005278: 687b ldr r3, [r7, #4]
- 800527a: 681b ldr r3, [r3, #0]
- 800527c: 685b ldr r3, [r3, #4]
- 800527e: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
- 8005282: 687b ldr r3, [r7, #4]
- 8005284: 6c5a ldr r2, [r3, #68] ; 0x44
- 8005286: 687b ldr r3, [r7, #4]
- 8005288: 681b ldr r3, [r3, #0]
- 800528a: 430a orrs r2, r1
- 800528c: 605a str r2, [r3, #4]
- }
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 800528e: 687b ldr r3, [r7, #4]
- 8005290: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005292: f003 0380 and.w r3, r3, #128 ; 0x80
- 8005296: 2b00 cmp r3, #0
- 8005298: d00a beq.n 80052b0 <UART_AdvFeatureConfig+0x138>
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 800529a: 687b ldr r3, [r7, #4]
- 800529c: 681b ldr r3, [r3, #0]
- 800529e: 685b ldr r3, [r3, #4]
- 80052a0: f423 2100 bic.w r1, r3, #524288 ; 0x80000
- 80052a4: 687b ldr r3, [r7, #4]
- 80052a6: 6c9a ldr r2, [r3, #72] ; 0x48
- 80052a8: 687b ldr r3, [r7, #4]
- 80052aa: 681b ldr r3, [r3, #0]
- 80052ac: 430a orrs r2, r1
- 80052ae: 605a str r2, [r3, #4]
- }
-}
- 80052b0: bf00 nop
- 80052b2: 370c adds r7, #12
- 80052b4: 46bd mov sp, r7
- 80052b6: f85d 7b04 ldr.w r7, [sp], #4
- 80052ba: 4770 bx lr
-
-080052bc <UART_CheckIdleState>:
- * @brief Check the UART Idle State.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- 80052bc: b580 push {r7, lr}
- 80052be: b086 sub sp, #24
- 80052c0: af02 add r7, sp, #8
- 80052c2: 6078 str r0, [r7, #4]
- uint32_t tickstart;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80052c4: 687b ldr r3, [r7, #4]
- 80052c6: 2200 movs r2, #0
- 80052c8: 67da str r2, [r3, #124] ; 0x7c
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 80052ca: f7fc fd93 bl 8001df4 <HAL_GetTick>
- 80052ce: 60f8 str r0, [r7, #12]
-
- /* Check if the Transmitter is enabled */
- if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 80052d0: 687b ldr r3, [r7, #4]
- 80052d2: 681b ldr r3, [r3, #0]
- 80052d4: 681b ldr r3, [r3, #0]
- 80052d6: f003 0308 and.w r3, r3, #8
- 80052da: 2b08 cmp r3, #8
- 80052dc: d10e bne.n 80052fc <UART_CheckIdleState+0x40>
- {
- /* Wait until TEACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 80052de: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
- 80052e2: 9300 str r3, [sp, #0]
- 80052e4: 68fb ldr r3, [r7, #12]
- 80052e6: 2200 movs r2, #0
- 80052e8: f44f 1100 mov.w r1, #2097152 ; 0x200000
- 80052ec: 6878 ldr r0, [r7, #4]
- 80052ee: f000 f814 bl 800531a <UART_WaitOnFlagUntilTimeout>
- 80052f2: 4603 mov r3, r0
- 80052f4: 2b00 cmp r3, #0
- 80052f6: d001 beq.n 80052fc <UART_CheckIdleState+0x40>
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- 80052f8: 2303 movs r3, #3
- 80052fa: e00a b.n 8005312 <UART_CheckIdleState+0x56>
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- 80052fc: 687b ldr r3, [r7, #4]
- 80052fe: 2220 movs r2, #32
- 8005300: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 8005302: 687b ldr r3, [r7, #4]
- 8005304: 2220 movs r2, #32
- 8005306: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8005308: 687b ldr r3, [r7, #4]
- 800530a: 2200 movs r2, #0
- 800530c: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 8005310: 2300 movs r3, #0
-}
- 8005312: 4618 mov r0, r3
- 8005314: 3710 adds r7, #16
- 8005316: 46bd mov sp, r7
- 8005318: bd80 pop {r7, pc}
-
-0800531a <UART_WaitOnFlagUntilTimeout>:
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- 800531a: b580 push {r7, lr}
- 800531c: b084 sub sp, #16
- 800531e: af00 add r7, sp, #0
- 8005320: 60f8 str r0, [r7, #12]
- 8005322: 60b9 str r1, [r7, #8]
- 8005324: 603b str r3, [r7, #0]
- 8005326: 4613 mov r3, r2
- 8005328: 71fb strb r3, [r7, #7]
- /* Wait until flag is set */
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 800532a: e02a b.n 8005382 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- 800532c: 69bb ldr r3, [r7, #24]
- 800532e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 8005332: d026 beq.n 8005382 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8005334: f7fc fd5e bl 8001df4 <HAL_GetTick>
- 8005338: 4602 mov r2, r0
- 800533a: 683b ldr r3, [r7, #0]
- 800533c: 1ad3 subs r3, r2, r3
- 800533e: 69ba ldr r2, [r7, #24]
- 8005340: 429a cmp r2, r3
- 8005342: d302 bcc.n 800534a <UART_WaitOnFlagUntilTimeout+0x30>
- 8005344: 69bb ldr r3, [r7, #24]
- 8005346: 2b00 cmp r3, #0
- 8005348: d11b bne.n 8005382 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 800534a: 68fb ldr r3, [r7, #12]
- 800534c: 681b ldr r3, [r3, #0]
- 800534e: 681a ldr r2, [r3, #0]
- 8005350: 68fb ldr r3, [r7, #12]
- 8005352: 681b ldr r3, [r3, #0]
- 8005354: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 8005358: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800535a: 68fb ldr r3, [r7, #12]
- 800535c: 681b ldr r3, [r3, #0]
- 800535e: 689a ldr r2, [r3, #8]
- 8005360: 68fb ldr r3, [r7, #12]
- 8005362: 681b ldr r3, [r3, #0]
- 8005364: f022 0201 bic.w r2, r2, #1
- 8005368: 609a str r2, [r3, #8]
-
- huart->gState = HAL_UART_STATE_READY;
- 800536a: 68fb ldr r3, [r7, #12]
- 800536c: 2220 movs r2, #32
- 800536e: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 8005370: 68fb ldr r3, [r7, #12]
- 8005372: 2220 movs r2, #32
- 8005374: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8005376: 68fb ldr r3, [r7, #12]
- 8005378: 2200 movs r2, #0
- 800537a: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_TIMEOUT;
- 800537e: 2303 movs r3, #3
- 8005380: e00f b.n 80053a2 <UART_WaitOnFlagUntilTimeout+0x88>
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8005382: 68fb ldr r3, [r7, #12]
- 8005384: 681b ldr r3, [r3, #0]
- 8005386: 69da ldr r2, [r3, #28]
- 8005388: 68bb ldr r3, [r7, #8]
- 800538a: 4013 ands r3, r2
- 800538c: 68ba ldr r2, [r7, #8]
- 800538e: 429a cmp r2, r3
- 8005390: bf0c ite eq
- 8005392: 2301 moveq r3, #1
- 8005394: 2300 movne r3, #0
- 8005396: b2db uxtb r3, r3
- 8005398: 461a mov r2, r3
- 800539a: 79fb ldrb r3, [r7, #7]
- 800539c: 429a cmp r2, r3
- 800539e: d0c5 beq.n 800532c <UART_WaitOnFlagUntilTimeout+0x12>
- }
- }
- }
- return HAL_OK;
- 80053a0: 2300 movs r3, #0
-}
- 80053a2: 4618 mov r0, r3
- 80053a4: 3710 adds r7, #16
- 80053a6: 46bd mov sp, r7
- 80053a8: bd80 pop {r7, pc}
-
-080053aa <UART_EndRxTransfer>:
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- 80053aa: b480 push {r7}
- 80053ac: b083 sub sp, #12
- 80053ae: af00 add r7, sp, #0
- 80053b0: 6078 str r0, [r7, #4]
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 80053b2: 687b ldr r3, [r7, #4]
- 80053b4: 681b ldr r3, [r3, #0]
- 80053b6: 681a ldr r2, [r3, #0]
- 80053b8: 687b ldr r3, [r7, #4]
- 80053ba: 681b ldr r3, [r3, #0]
- 80053bc: f422 7290 bic.w r2, r2, #288 ; 0x120
- 80053c0: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80053c2: 687b ldr r3, [r7, #4]
- 80053c4: 681b ldr r3, [r3, #0]
- 80053c6: 689a ldr r2, [r3, #8]
- 80053c8: 687b ldr r3, [r7, #4]
- 80053ca: 681b ldr r3, [r3, #0]
- 80053cc: f022 0201 bic.w r2, r2, #1
- 80053d0: 609a str r2, [r3, #8]
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 80053d2: 687b ldr r3, [r7, #4]
- 80053d4: 2220 movs r2, #32
- 80053d6: 679a str r2, [r3, #120] ; 0x78
-
- /* Reset RxIsr function pointer */
- huart->RxISR = NULL;
- 80053d8: 687b ldr r3, [r7, #4]
- 80053da: 2200 movs r2, #0
- 80053dc: 661a str r2, [r3, #96] ; 0x60
-}
- 80053de: bf00 nop
- 80053e0: 370c adds r7, #12
- 80053e2: 46bd mov sp, r7
- 80053e4: f85d 7b04 ldr.w r7, [sp], #4
- 80053e8: 4770 bx lr
-
-080053ea <UART_DMAAbortOnError>:
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- 80053ea: b580 push {r7, lr}
- 80053ec: b084 sub sp, #16
- 80053ee: af00 add r7, sp, #0
- 80053f0: 6078 str r0, [r7, #4]
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 80053f2: 687b ldr r3, [r7, #4]
- 80053f4: 6b9b ldr r3, [r3, #56] ; 0x38
- 80053f6: 60fb str r3, [r7, #12]
- huart->RxXferCount = 0U;
- 80053f8: 68fb ldr r3, [r7, #12]
- 80053fa: 2200 movs r2, #0
- 80053fc: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->TxXferCount = 0U;
- 8005400: 68fb ldr r3, [r7, #12]
- 8005402: 2200 movs r2, #0
- 8005404: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8005408: 68f8 ldr r0, [r7, #12]
- 800540a: f7ff fc07 bl 8004c1c <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 800540e: bf00 nop
- 8005410: 3710 adds r7, #16
- 8005412: 46bd mov sp, r7
- 8005414: bd80 pop {r7, pc}
-
-08005416 <UART_EndTransmit_IT>:
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- 8005416: b580 push {r7, lr}
- 8005418: b082 sub sp, #8
- 800541a: af00 add r7, sp, #0
- 800541c: 6078 str r0, [r7, #4]
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- 800541e: 687b ldr r3, [r7, #4]
- 8005420: 681b ldr r3, [r3, #0]
- 8005422: 681a ldr r2, [r3, #0]
- 8005424: 687b ldr r3, [r7, #4]
- 8005426: 681b ldr r3, [r3, #0]
- 8005428: f022 0240 bic.w r2, r2, #64 ; 0x40
- 800542c: 601a str r2, [r3, #0]
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 800542e: 687b ldr r3, [r7, #4]
- 8005430: 2220 movs r2, #32
- 8005432: 675a str r2, [r3, #116] ; 0x74
-
- /* Cleat TxISR function pointer */
- huart->TxISR = NULL;
- 8005434: 687b ldr r3, [r7, #4]
- 8005436: 2200 movs r2, #0
- 8005438: 665a str r2, [r3, #100] ; 0x64
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx complete callback*/
- huart->TxCpltCallback(huart);
-#else
- /*Call legacy weak Tx complete callback*/
- HAL_UART_TxCpltCallback(huart);
- 800543a: 6878 ldr r0, [r7, #4]
- 800543c: f7ff fbe4 bl 8004c08 <HAL_UART_TxCpltCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 8005440: bf00 nop
- 8005442: 3708 adds r7, #8
- 8005444: 46bd mov sp, r7
- 8005446: bd80 pop {r7, pc}
-
-08005448 <UART_RxISR_8BIT>:
- * @brief RX interrrupt handler for 7 or 8 bits data word length .
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
-{
- 8005448: b580 push {r7, lr}
- 800544a: b084 sub sp, #16
- 800544c: af00 add r7, sp, #0
- 800544e: 6078 str r0, [r7, #4]
- uint16_t uhMask = huart->Mask;
- 8005450: 687b ldr r3, [r7, #4]
- 8005452: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 8005456: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 8005458: 687b ldr r3, [r7, #4]
- 800545a: 6f9b ldr r3, [r3, #120] ; 0x78
- 800545c: 2b22 cmp r3, #34 ; 0x22
- 800545e: d13a bne.n 80054d6 <UART_RxISR_8BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 8005460: 687b ldr r3, [r7, #4]
- 8005462: 681b ldr r3, [r3, #0]
- 8005464: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005466: 81bb strh r3, [r7, #12]
- *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
- 8005468: 89bb ldrh r3, [r7, #12]
- 800546a: b2d9 uxtb r1, r3
- 800546c: 89fb ldrh r3, [r7, #14]
- 800546e: b2da uxtb r2, r3
- 8005470: 687b ldr r3, [r7, #4]
- 8005472: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005474: 400a ands r2, r1
- 8005476: b2d2 uxtb r2, r2
- 8005478: 701a strb r2, [r3, #0]
- huart->pRxBuffPtr++;
- 800547a: 687b ldr r3, [r7, #4]
- 800547c: 6d5b ldr r3, [r3, #84] ; 0x54
- 800547e: 1c5a adds r2, r3, #1
- 8005480: 687b ldr r3, [r7, #4]
- 8005482: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 8005484: 687b ldr r3, [r7, #4]
- 8005486: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 800548a: b29b uxth r3, r3
- 800548c: 3b01 subs r3, #1
- 800548e: b29a uxth r2, r3
- 8005490: 687b ldr r3, [r7, #4]
- 8005492: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 8005496: 687b ldr r3, [r7, #4]
- 8005498: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 800549c: b29b uxth r3, r3
- 800549e: 2b00 cmp r3, #0
- 80054a0: d121 bne.n 80054e6 <UART_RxISR_8BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 80054a2: 687b ldr r3, [r7, #4]
- 80054a4: 681b ldr r3, [r3, #0]
- 80054a6: 681a ldr r2, [r3, #0]
- 80054a8: 687b ldr r3, [r7, #4]
- 80054aa: 681b ldr r3, [r3, #0]
- 80054ac: f422 7290 bic.w r2, r2, #288 ; 0x120
- 80054b0: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80054b2: 687b ldr r3, [r7, #4]
- 80054b4: 681b ldr r3, [r3, #0]
- 80054b6: 689a ldr r2, [r3, #8]
- 80054b8: 687b ldr r3, [r7, #4]
- 80054ba: 681b ldr r3, [r3, #0]
- 80054bc: f022 0201 bic.w r2, r2, #1
- 80054c0: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 80054c2: 687b ldr r3, [r7, #4]
- 80054c4: 2220 movs r2, #32
- 80054c6: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 80054c8: 687b ldr r3, [r7, #4]
- 80054ca: 2200 movs r2, #0
- 80054cc: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 80054ce: 6878 ldr r0, [r7, #4]
- 80054d0: f7fc f85a bl 8001588 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 80054d4: e007 b.n 80054e6 <UART_RxISR_8BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 80054d6: 687b ldr r3, [r7, #4]
- 80054d8: 681b ldr r3, [r3, #0]
- 80054da: 699a ldr r2, [r3, #24]
- 80054dc: 687b ldr r3, [r7, #4]
- 80054de: 681b ldr r3, [r3, #0]
- 80054e0: f042 0208 orr.w r2, r2, #8
- 80054e4: 619a str r2, [r3, #24]
-}
- 80054e6: bf00 nop
- 80054e8: 3710 adds r7, #16
- 80054ea: 46bd mov sp, r7
- 80054ec: bd80 pop {r7, pc}
-
-080054ee <UART_RxISR_16BIT>:
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
-{
- 80054ee: b580 push {r7, lr}
- 80054f0: b084 sub sp, #16
- 80054f2: af00 add r7, sp, #0
- 80054f4: 6078 str r0, [r7, #4]
- uint16_t *tmp;
- uint16_t uhMask = huart->Mask;
- 80054f6: 687b ldr r3, [r7, #4]
- 80054f8: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 80054fc: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 80054fe: 687b ldr r3, [r7, #4]
- 8005500: 6f9b ldr r3, [r3, #120] ; 0x78
- 8005502: 2b22 cmp r3, #34 ; 0x22
- 8005504: d13a bne.n 800557c <UART_RxISR_16BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 8005506: 687b ldr r3, [r7, #4]
- 8005508: 681b ldr r3, [r3, #0]
- 800550a: 6a5b ldr r3, [r3, #36] ; 0x24
- 800550c: 81bb strh r3, [r7, #12]
- tmp = (uint16_t *) huart->pRxBuffPtr ;
- 800550e: 687b ldr r3, [r7, #4]
- 8005510: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005512: 60bb str r3, [r7, #8]
- *tmp = (uint16_t)(uhdata & uhMask);
- 8005514: 89ba ldrh r2, [r7, #12]
- 8005516: 89fb ldrh r3, [r7, #14]
- 8005518: 4013 ands r3, r2
- 800551a: b29a uxth r2, r3
- 800551c: 68bb ldr r3, [r7, #8]
- 800551e: 801a strh r2, [r3, #0]
- huart->pRxBuffPtr += 2U;
- 8005520: 687b ldr r3, [r7, #4]
- 8005522: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005524: 1c9a adds r2, r3, #2
- 8005526: 687b ldr r3, [r7, #4]
- 8005528: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 800552a: 687b ldr r3, [r7, #4]
- 800552c: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8005530: b29b uxth r3, r3
- 8005532: 3b01 subs r3, #1
- 8005534: b29a uxth r2, r3
- 8005536: 687b ldr r3, [r7, #4]
- 8005538: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 800553c: 687b ldr r3, [r7, #4]
- 800553e: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8005542: b29b uxth r3, r3
- 8005544: 2b00 cmp r3, #0
- 8005546: d121 bne.n 800558c <UART_RxISR_16BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8005548: 687b ldr r3, [r7, #4]
- 800554a: 681b ldr r3, [r3, #0]
- 800554c: 681a ldr r2, [r3, #0]
- 800554e: 687b ldr r3, [r7, #4]
- 8005550: 681b ldr r3, [r3, #0]
- 8005552: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8005556: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8005558: 687b ldr r3, [r7, #4]
- 800555a: 681b ldr r3, [r3, #0]
- 800555c: 689a ldr r2, [r3, #8]
- 800555e: 687b ldr r3, [r7, #4]
- 8005560: 681b ldr r3, [r3, #0]
- 8005562: f022 0201 bic.w r2, r2, #1
- 8005566: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 8005568: 687b ldr r3, [r7, #4]
- 800556a: 2220 movs r2, #32
- 800556c: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 800556e: 687b ldr r3, [r7, #4]
- 8005570: 2200 movs r2, #0
- 8005572: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 8005574: 6878 ldr r0, [r7, #4]
- 8005576: f7fc f807 bl 8001588 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 800557a: e007 b.n 800558c <UART_RxISR_16BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 800557c: 687b ldr r3, [r7, #4]
- 800557e: 681b ldr r3, [r3, #0]
- 8005580: 699a ldr r2, [r3, #24]
- 8005582: 687b ldr r3, [r7, #4]
- 8005584: 681b ldr r3, [r3, #0]
- 8005586: f042 0208 orr.w r2, r2, #8
- 800558a: 619a str r2, [r3, #24]
-}
- 800558c: bf00 nop
- 800558e: 3710 adds r7, #16
- 8005590: 46bd mov sp, r7
- 8005592: bd80 pop {r7, pc}
-
-08005594 <__libc_init_array>:
- 8005594: b570 push {r4, r5, r6, lr}
- 8005596: 4e0d ldr r6, [pc, #52] ; (80055cc <__libc_init_array+0x38>)
- 8005598: 4c0d ldr r4, [pc, #52] ; (80055d0 <__libc_init_array+0x3c>)
- 800559a: 1ba4 subs r4, r4, r6
- 800559c: 10a4 asrs r4, r4, #2
- 800559e: 2500 movs r5, #0
- 80055a0: 42a5 cmp r5, r4
- 80055a2: d109 bne.n 80055b8 <__libc_init_array+0x24>
- 80055a4: 4e0b ldr r6, [pc, #44] ; (80055d4 <__libc_init_array+0x40>)
- 80055a6: 4c0c ldr r4, [pc, #48] ; (80055d8 <__libc_init_array+0x44>)
- 80055a8: f000 f820 bl 80055ec <_init>
- 80055ac: 1ba4 subs r4, r4, r6
- 80055ae: 10a4 asrs r4, r4, #2
- 80055b0: 2500 movs r5, #0
- 80055b2: 42a5 cmp r5, r4
- 80055b4: d105 bne.n 80055c2 <__libc_init_array+0x2e>
- 80055b6: bd70 pop {r4, r5, r6, pc}
- 80055b8: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 80055bc: 4798 blx r3
- 80055be: 3501 adds r5, #1
- 80055c0: e7ee b.n 80055a0 <__libc_init_array+0xc>
- 80055c2: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 80055c6: 4798 blx r3
- 80055c8: 3501 adds r5, #1
- 80055ca: e7f2 b.n 80055b2 <__libc_init_array+0x1e>
- 80055cc: 08005624 .word 0x08005624
- 80055d0: 08005624 .word 0x08005624
- 80055d4: 08005624 .word 0x08005624
- 80055d8: 0800562c .word 0x0800562c
-
-080055dc <memset>:
- 80055dc: 4402 add r2, r0
- 80055de: 4603 mov r3, r0
- 80055e0: 4293 cmp r3, r2
- 80055e2: d100 bne.n 80055e6 <memset+0xa>
- 80055e4: 4770 bx lr
- 80055e6: f803 1b01 strb.w r1, [r3], #1
- 80055ea: e7f9 b.n 80055e0 <memset+0x4>
-
-080055ec <_init>:
- 80055ec: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80055ee: bf00 nop
- 80055f0: bcf8 pop {r3, r4, r5, r6, r7}
- 80055f2: bc08 pop {r3}
- 80055f4: 469e mov lr, r3
- 80055f6: 4770 bx lr
-
-080055f8 <_fini>:
- 80055f8: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80055fa: bf00 nop
- 80055fc: bcf8 pop {r3, r4, r5, r6, r7}
- 80055fe: bc08 pop {r3}
- 8005600: 469e mov lr, r3
- 8005602: 4770 bx lr
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-ELF_SRCS :=
-C_UPPER_SRCS :=
-CXX_SRCS :=
-C++_SRCS :=
-OBJ_SRCS :=
-S_SRCS :=
-CC_SRCS :=
-C_SRCS :=
-CPP_SRCS :=
-S_UPPER_SRCS :=
-O_SRCS :=
-CC_DEPS :=
-SIZE_OUTPUT :=
-OBJDUMP_LIST :=
-C++_DEPS :=
-EXECUTABLES :=
-OBJS :=
-C_UPPER_DEPS :=
-CXX_DEPS :=
-C_DEPS :=
-CPP_DEPS :=
-
-# Every subdirectory with source files must be described here
-SUBDIRS := \
-Core/Src \
-Core/Startup \
-Drivers/STM32F7xx_HAL_Driver/Src \
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Core/Src/stm32f7xx_hal_msp.c \
-../Core/Src/stm32f7xx_it.c \
-../Core/Src/syscalls.c \
-../Core/Src/sysmem.c \
-../Core/Src/system_stm32f7xx.c
-
-CPP_SRCS += \
-../Core/Src/encoder.cpp \
-../Core/Src/main.cpp
-
-OBJS += \
-./Core/Src/encoder.o \
-./Core/Src/main.o \
-./Core/Src/stm32f7xx_hal_msp.o \
-./Core/Src/stm32f7xx_it.o \
-./Core/Src/syscalls.o \
-./Core/Src/sysmem.o \
-./Core/Src/system_stm32f7xx.o
-
-C_DEPS += \
-./Core/Src/stm32f7xx_hal_msp.d \
-./Core/Src/stm32f7xx_it.d \
-./Core/Src/syscalls.d \
-./Core/Src/sysmem.d \
-./Core/Src/system_stm32f7xx.d
-
-CPP_DEPS += \
-./Core/Src/encoder.d \
-./Core/Src/main.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Src/encoder.o: ../Core/Src/encoder.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/encoder.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/main.o: ../Core/Src/main.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/syscalls.o: ../Core/Src/syscalls.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/sysmem.o: ../Core/Src/sysmem.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-S_SRCS += \
-../Core/Startup/startup_stm32f767zitx.s
-
-OBJS += \
-./Core/Startup/startup_stm32f767zitx.o
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Startup/%.o: ../Core/Startup/%.s
- arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
-
-OBJS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o
-
-C_DEPS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F767xx -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
--include ../makefile.init
-
-RM := rm -rf
-
-# All of the sources participating in the build are defined here
--include sources.mk
--include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk
--include Core/Startup/subdir.mk
--include Core/Src/subdir.mk
--include subdir.mk
--include objects.mk
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(CC_DEPS)),)
--include $(CC_DEPS)
-endif
-ifneq ($(strip $(C++_DEPS)),)
--include $(C++_DEPS)
-endif
-ifneq ($(strip $(C_UPPER_DEPS)),)
--include $(C_UPPER_DEPS)
-endif
-ifneq ($(strip $(CXX_DEPS)),)
--include $(CXX_DEPS)
-endif
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-ifneq ($(strip $(CPP_DEPS)),)
--include $(CPP_DEPS)
-endif
-endif
-
--include ../makefile.defs
-
-# Add inputs and outputs from these tool invocations to the build variables
-EXECUTABLES += \
-otto_ticks_calibration.elf \
-
-SIZE_OUTPUT += \
-default.size.stdout \
-
-OBJDUMP_LIST += \
-otto_ticks_calibration.list \
-
-
-# All Target
-all: otto_ticks_calibration.elf secondary-outputs
-
-# Tool invocations
-otto_ticks_calibration.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/STM32F767ZITX_FLASH.ld
- arm-none-eabi-g++ -o "otto_ticks_calibration.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/utils/ticks_calibration/otto_ticks_calibration/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_ticks_calibration.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
- @echo 'Finished building target: $@'
- @echo ' '
-
-default.size.stdout: $(EXECUTABLES)
- arm-none-eabi-size $(EXECUTABLES)
- @echo 'Finished building: $@'
- @echo ' '
-
-otto_ticks_calibration.list: $(EXECUTABLES)
- arm-none-eabi-objdump -h -S $(EXECUTABLES) > "otto_ticks_calibration.list"
- @echo 'Finished building: $@'
- @echo ' '
-
-# Other Targets
-clean:
- -$(RM) *
- -@echo ' '
-
-secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
-
-.PHONY: all clean dependents
-.SECONDARY:
-
--include ../makefile.targets
+++ /dev/null
-"Core/Src/encoder.o"
-"Core/Src/main.o"
-"Core/Src/stm32f7xx_hal_msp.o"
-"Core/Src/stm32f7xx_it.o"
-"Core/Src/syscalls.o"
-"Core/Src/sysmem.o"
-"Core/Src/system_stm32f7xx.o"
-"Core/Startup/startup_stm32f767zitx.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o"
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-USER_OBJS :=
-
-LIBS :=
-
+++ /dev/null
-
-otto_ticks_calibration.elf: file format elf32-littlearm
-
-Sections:
-Idx Name Size VMA LMA File off Algn
- 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 000052e8 080001f8 080001f8 000101f8 2**3
- CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000018 080054e0 080054e0 000154e0 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 080054f8 080054f8 00020010 2**0
- CONTENTS
- 4 .ARM 00000008 080054f8 080054f8 000154f8 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 08005500 08005500 00020010 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000008 08005500 08005500 00015500 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 08005508 08005508 00015508 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 8 .data 00000010 20000000 0800550c 00020000 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 000002fc 20000010 0800551c 00020010 2**2
- ALLOC
- 10 ._user_heap_stack 00000604 2000030c 0800551c 0002030c 2**0
- ALLOC
- 11 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0
- CONTENTS, READONLY
- 12 .debug_info 0000dc03 00000000 00000000 0002003e 2**0
- CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00001e34 00000000 00000000 0002dc41 2**0
- CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000d70 00000000 00000000 0002fa78 2**3
- CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000c88 00000000 00000000 000307e8 2**3
- CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 00028243 00000000 00000000 00031470 2**0
- CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 00009a7e 00000000 00000000 000596b3 2**0
- CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000f1e32 00000000 00000000 00063131 2**0
- CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 00154f63 2**0
- CONTENTS, READONLY
- 20 .debug_frame 00003884 00000000 00000000 00154fe0 2**2
- CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-080001f8 <__do_global_dtors_aux>:
- 80001f8: b510 push {r4, lr}
- 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
- 80001fc: 7823 ldrb r3, [r4, #0]
- 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
- 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
- 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
- 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
- 8000206: f3af 8000 nop.w
- 800020a: 2301 movs r3, #1
- 800020c: 7023 strb r3, [r4, #0]
- 800020e: bd10 pop {r4, pc}
- 8000210: 20000010 .word 0x20000010
- 8000214: 00000000 .word 0x00000000
- 8000218: 080054c8 .word 0x080054c8
-
-0800021c <frame_dummy>:
- 800021c: b508 push {r3, lr}
- 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
- 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
- 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
- 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
- 8000226: f3af 8000 nop.w
- 800022a: bd08 pop {r3, pc}
- 800022c: 00000000 .word 0x00000000
- 8000230: 20000014 .word 0x20000014
- 8000234: 080054c8 .word 0x080054c8
-
-08000238 <__aeabi_uldivmod>:
- 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
- 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
- 800023c: 2900 cmp r1, #0
- 800023e: bf08 it eq
- 8000240: 2800 cmpeq r0, #0
- 8000242: bf1c itt ne
- 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
- 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
- 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0>
- 8000250: f1ad 0c08 sub.w ip, sp, #8
- 8000254: e96d ce04 strd ip, lr, [sp, #-16]!
- 8000258: f000 f806 bl 8000268 <__udivmoddi4>
- 800025c: f8dd e004 ldr.w lr, [sp, #4]
- 8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
- 8000264: b004 add sp, #16
- 8000266: 4770 bx lr
-
-08000268 <__udivmoddi4>:
- 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 800026c: 9e08 ldr r6, [sp, #32]
- 800026e: 4604 mov r4, r0
- 8000270: 4688 mov r8, r1
- 8000272: 2b00 cmp r3, #0
- 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6>
- 8000276: 428a cmp r2, r1
- 8000278: 4615 mov r5, r2
- 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4>
- 800027c: fab2 f282 clz r2, r2
- 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e>
- 8000282: f1c2 0720 rsb r7, r2, #32
- 8000286: fa01 f302 lsl.w r3, r1, r2
- 800028a: fa20 f707 lsr.w r7, r0, r7
- 800028e: 4095 lsls r5, r2
- 8000290: ea47 0803 orr.w r8, r7, r3
- 8000294: 4094 lsls r4, r2
- 8000296: ea4f 4e15 mov.w lr, r5, lsr #16
- 800029a: 0c23 lsrs r3, r4, #16
- 800029c: fbb8 f7fe udiv r7, r8, lr
- 80002a0: fa1f fc85 uxth.w ip, r5
- 80002a4: fb0e 8817 mls r8, lr, r7, r8
- 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16
- 80002ac: fb07 f10c mul.w r1, r7, ip
- 80002b0: 4299 cmp r1, r3
- 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60>
- 80002b4: 18eb adds r3, r5, r3
- 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
- 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c>
- 80002be: 4299 cmp r1, r3
- 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c>
- 80002c4: 3f02 subs r7, #2
- 80002c6: 442b add r3, r5
- 80002c8: 1a5b subs r3, r3, r1
- 80002ca: b2a4 uxth r4, r4
- 80002cc: fbb3 f0fe udiv r0, r3, lr
- 80002d0: fb0e 3310 mls r3, lr, r0, r3
- 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16
- 80002d8: fb00 fc0c mul.w ip, r0, ip
- 80002dc: 45a4 cmp ip, r4
- 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c>
- 80002e0: 192c adds r4, r5, r4
- 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290>
- 80002ea: 45a4 cmp ip, r4
- 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290>
- 80002f0: 3802 subs r0, #2
- 80002f2: 442c add r4, r5
- 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16
- 80002f8: eba4 040c sub.w r4, r4, ip
- 80002fc: 2700 movs r7, #0
- 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0>
- 8000300: 40d4 lsrs r4, r2
- 8000302: 2300 movs r3, #0
- 8000304: e9c6 4300 strd r4, r3, [r6]
- 8000308: 4639 mov r1, r7
- 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 800030e: 428b cmp r3, r1
- 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe>
- 8000312: 2e00 cmp r6, #0
- 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286>
- 8000318: 2700 movs r7, #0
- 800031a: e9c6 0100 strd r0, r1, [r6]
- 800031e: 4638 mov r0, r7
- 8000320: 4639 mov r1, r7
- 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000326: fab3 f783 clz r7, r3
- 800032a: 2f00 cmp r7, #0
- 800032c: d147 bne.n 80003be <__udivmoddi4+0x156>
- 800032e: 428b cmp r3, r1
- 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0>
- 8000332: 4282 cmp r2, r0
- 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4>
- 8000338: 1a84 subs r4, r0, r2
- 800033a: eb61 0303 sbc.w r3, r1, r3
- 800033e: 2001 movs r0, #1
- 8000340: 4698 mov r8, r3
- 8000342: 2e00 cmp r6, #0
- 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0>
- 8000346: e9c6 4800 strd r4, r8, [r6]
- 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0>
- 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8>
- 800034e: deff udf #255 ; 0xff
- 8000350: fab2 f282 clz r2, r2
- 8000354: 2a00 cmp r2, #0
- 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210>
- 800035a: 1b49 subs r1, r1, r5
- 800035c: ea4f 4e15 mov.w lr, r5, lsr #16
- 8000360: fa1f f885 uxth.w r8, r5
- 8000364: 2701 movs r7, #1
- 8000366: fbb1 fcfe udiv ip, r1, lr
- 800036a: 0c23 lsrs r3, r4, #16
- 800036c: fb0e 111c mls r1, lr, ip, r1
- 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16
- 8000374: fb08 f10c mul.w r1, r8, ip
- 8000378: 4299 cmp r1, r3
- 800037a: d907 bls.n 800038c <__udivmoddi4+0x124>
- 800037c: 18eb adds r3, r5, r3
- 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
- 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122>
- 8000384: 4299 cmp r1, r3
- 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc>
- 800038a: 4684 mov ip, r0
- 800038c: 1a59 subs r1, r3, r1
- 800038e: b2a3 uxth r3, r4
- 8000390: fbb1 f0fe udiv r0, r1, lr
- 8000394: fb0e 1410 mls r4, lr, r0, r1
- 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16
- 800039c: fb08 f800 mul.w r8, r8, r0
- 80003a0: 45a0 cmp r8, r4
- 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c>
- 80003a4: 192c adds r4, r5, r4
- 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a>
- 80003ac: 45a0 cmp r8, r4
- 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6>
- 80003b2: 4618 mov r0, r3
- 80003b4: eba4 0408 sub.w r4, r4, r8
- 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16
- 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96>
- 80003be: f1c7 0c20 rsb ip, r7, #32
- 80003c2: 40bb lsls r3, r7
- 80003c4: fa22 fe0c lsr.w lr, r2, ip
- 80003c8: ea4e 0e03 orr.w lr, lr, r3
- 80003cc: fa01 f407 lsl.w r4, r1, r7
- 80003d0: fa20 f50c lsr.w r5, r0, ip
- 80003d4: fa21 f30c lsr.w r3, r1, ip
- 80003d8: ea4f 481e mov.w r8, lr, lsr #16
- 80003dc: 4325 orrs r5, r4
- 80003de: fbb3 f9f8 udiv r9, r3, r8
- 80003e2: 0c2c lsrs r4, r5, #16
- 80003e4: fb08 3319 mls r3, r8, r9, r3
- 80003e8: fa1f fa8e uxth.w sl, lr
- 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16
- 80003f0: fb09 f40a mul.w r4, r9, sl
- 80003f4: 429c cmp r4, r3
- 80003f6: fa02 f207 lsl.w r2, r2, r7
- 80003fa: fa00 f107 lsl.w r1, r0, r7
- 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0>
- 8000400: eb1e 0303 adds.w r3, lr, r3
- 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
- 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2>
- 800040c: 429c cmp r4, r3
- 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2>
- 8000412: f1a9 0902 sub.w r9, r9, #2
- 8000416: 4473 add r3, lr
- 8000418: 1b1b subs r3, r3, r4
- 800041a: b2ad uxth r5, r5
- 800041c: fbb3 f0f8 udiv r0, r3, r8
- 8000420: fb08 3310 mls r3, r8, r0, r3
- 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16
- 8000428: fb00 fa0a mul.w sl, r0, sl
- 800042c: 45a2 cmp sl, r4
- 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da>
- 8000430: eb1e 0404 adds.w r4, lr, r4
- 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa>
- 800043a: 45a2 cmp sl, r4
- 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa>
- 800043e: 3802 subs r0, #2
- 8000440: 4474 add r4, lr
- 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16
- 8000446: fba0 8902 umull r8, r9, r0, r2
- 800044a: eba4 040a sub.w r4, r4, sl
- 800044e: 454c cmp r4, r9
- 8000450: 46c2 mov sl, r8
- 8000452: 464b mov r3, r9
- 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298>
- 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294>
- 8000458: 2e00 cmp r6, #0
- 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8>
- 800045c: ebb1 050a subs.w r5, r1, sl
- 8000460: eb64 0403 sbc.w r4, r4, r3
- 8000464: fa04 fc0c lsl.w ip, r4, ip
- 8000468: 40fd lsrs r5, r7
- 800046a: 40fc lsrs r4, r7
- 800046c: ea4c 0505 orr.w r5, ip, r5
- 8000470: e9c6 5400 strd r5, r4, [r6]
- 8000474: 2700 movs r7, #0
- 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0>
- 8000478: f1c2 0320 rsb r3, r2, #32
- 800047c: fa20 f703 lsr.w r7, r0, r3
- 8000480: 4095 lsls r5, r2
- 8000482: fa01 f002 lsl.w r0, r1, r2
- 8000486: fa21 f303 lsr.w r3, r1, r3
- 800048a: ea4f 4e15 mov.w lr, r5, lsr #16
- 800048e: 4338 orrs r0, r7
- 8000490: 0c01 lsrs r1, r0, #16
- 8000492: fbb3 f7fe udiv r7, r3, lr
- 8000496: fa1f f885 uxth.w r8, r5
- 800049a: fb0e 3317 mls r3, lr, r7, r3
- 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004a2: fb07 f308 mul.w r3, r7, r8
- 80004a6: 428b cmp r3, r1
- 80004a8: fa04 f402 lsl.w r4, r4, r2
- 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256>
- 80004ae: 1869 adds r1, r5, r1
- 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
- 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae>
- 80004b6: 428b cmp r3, r1
- 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae>
- 80004ba: 3f02 subs r7, #2
- 80004bc: 4429 add r1, r5
- 80004be: 1acb subs r3, r1, r3
- 80004c0: b281 uxth r1, r0
- 80004c2: fbb3 f0fe udiv r0, r3, lr
- 80004c6: fb0e 3310 mls r3, lr, r0, r3
- 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004ce: fb00 f308 mul.w r3, r0, r8
- 80004d2: 428b cmp r3, r1
- 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e>
- 80004d6: 1869 adds r1, r5, r1
- 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
- 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6>
- 80004de: 428b cmp r3, r1
- 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6>
- 80004e2: 3802 subs r0, #2
- 80004e4: 4429 add r1, r5
- 80004e6: 1ac9 subs r1, r1, r3
- 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16
- 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe>
- 80004ee: 4637 mov r7, r6
- 80004f0: 4630 mov r0, r6
- 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0>
- 80004f4: 4607 mov r7, r0
- 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60>
- 80004f8: 4618 mov r0, r3
- 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c>
- 80004fc: 4541 cmp r1, r8
- 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0>
- 8000500: ebb8 0a02 subs.w sl, r8, r2
- 8000504: eb69 020e sbc.w r2, r9, lr
- 8000508: 3801 subs r0, #1
- 800050a: 4613 mov r3, r2
- 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0>
- 800050e: 4660 mov r0, ip
- 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e>
- 8000512: 4618 mov r0, r3
- 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da>
- 8000516: 4667 mov r7, ip
- 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256>
- 800051a: 4681 mov r9, r0
- 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0>
- 800051e: 3802 subs r0, #2
- 8000520: 442c add r4, r5
- 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c>
- 8000524: f1ac 0c02 sub.w ip, ip, #2
- 8000528: 442b add r3, r5
- 800052a: e72f b.n 800038c <__udivmoddi4+0x124>
- 800052c: 4638 mov r0, r7
- 800052e: e708 b.n 8000342 <__udivmoddi4+0xda>
- 8000530: 4637 mov r7, r6
- 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0>
-
-08000534 <__aeabi_idiv0>:
- 8000534: 4770 bx lr
- 8000536: bf00 nop
-
-08000538 <_ZN7Encoder8GetCountEv>:
- Encoder(TIM_HandleTypeDef *timer, int ticks_per_meters);
-
-
- void Setup();
-
- int GetCount() {
- 8000538: b480 push {r7}
- 800053a: b085 sub sp, #20
- 800053c: af00 add r7, sp, #0
- 800053e: 6078 str r0, [r7, #4]
- int count = ((int) __HAL_TIM_GET_COUNTER(this->timer_)
- 8000540: 687b ldr r3, [r7, #4]
- 8000542: 681b ldr r3, [r3, #0]
- 8000544: 681b ldr r3, [r3, #0]
- 8000546: 6a5a ldr r2, [r3, #36] ; 0x24
- - ((this->timer_->Init.Period) / 2));
- 8000548: 687b ldr r3, [r7, #4]
- 800054a: 681b ldr r3, [r3, #0]
- 800054c: 68db ldr r3, [r3, #12]
- 800054e: 085b lsrs r3, r3, #1
- 8000550: 1ad3 subs r3, r2, r3
- 8000552: 60fb str r3, [r7, #12]
- return count;
- 8000554: 68fb ldr r3, [r7, #12]
- }
- 8000556: 4618 mov r0, r3
- 8000558: 3714 adds r7, #20
- 800055a: 46bd mov sp, r7
- 800055c: f85d 7b04 ldr.w r7, [sp], #4
- 8000560: 4770 bx lr
-
-08000562 <_ZN7Encoder10ResetCountEv>:
-
- void ResetCount() {
- 8000562: b480 push {r7}
- 8000564: b083 sub sp, #12
- 8000566: af00 add r7, sp, #0
- 8000568: 6078 str r0, [r7, #4]
- //set counter to half its maximum value
- __HAL_TIM_SET_COUNTER(timer_, (timer_->Init.Period / 2));
- 800056a: 687b ldr r3, [r7, #4]
- 800056c: 681b ldr r3, [r3, #0]
- 800056e: 68da ldr r2, [r3, #12]
- 8000570: 687b ldr r3, [r7, #4]
- 8000572: 681b ldr r3, [r3, #0]
- 8000574: 681b ldr r3, [r3, #0]
- 8000576: 0852 lsrs r2, r2, #1
- 8000578: 625a str r2, [r3, #36] ; 0x24
- }
- 800057a: bf00 nop
- 800057c: 370c adds r7, #12
- 800057e: 46bd mov sp, r7
- 8000580: f85d 7b04 ldr.w r7, [sp], #4
- 8000584: 4770 bx lr
-
-08000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>:
-// timer_ = timer;
-// wheel_circumference_ = wheel_circ;
-//
-//}
-
-Encoder::Encoder(TIM_HandleTypeDef *timer, int ticks_per_meter) {
- 8000586: b480 push {r7}
- 8000588: b085 sub sp, #20
- 800058a: af00 add r7, sp, #0
- 800058c: 60f8 str r0, [r7, #12]
- 800058e: 60b9 str r1, [r7, #8]
- 8000590: 607a str r2, [r7, #4]
- timer_ = timer;
- 8000592: 68fb ldr r3, [r7, #12]
- 8000594: 68ba ldr r2, [r7, #8]
- 8000596: 601a str r2, [r3, #0]
- ticks_per_meter_ = ticks_per_meter;
- 8000598: 68fb ldr r3, [r7, #12]
- 800059a: 687a ldr r2, [r7, #4]
- 800059c: 615a str r2, [r3, #20]
-
-}
- 800059e: 68fb ldr r3, [r7, #12]
- 80005a0: 4618 mov r0, r3
- 80005a2: 3714 adds r7, #20
- 80005a4: 46bd mov sp, r7
- 80005a6: f85d 7b04 ldr.w r7, [sp], #4
- 80005aa: 4770 bx lr
-
-080005ac <_ZN7Encoder5SetupEv>:
-
-void Encoder::Setup() {
- 80005ac: b580 push {r7, lr}
- 80005ae: b082 sub sp, #8
- 80005b0: af00 add r7, sp, #0
- 80005b2: 6078 str r0, [r7, #4]
- HAL_TIM_Encoder_Start(timer_, TIM_CHANNEL_ALL);
- 80005b4: 687b ldr r3, [r7, #4]
- 80005b6: 681b ldr r3, [r3, #0]
- 80005b8: 213c movs r1, #60 ; 0x3c
- 80005ba: 4618 mov r0, r3
- 80005bc: f003 f86c bl 8003698 <HAL_TIM_Encoder_Start>
- this->ResetCount();
- 80005c0: 6878 ldr r0, [r7, #4]
- 80005c2: f7ff ffce bl 8000562 <_ZN7Encoder10ResetCountEv>
- this->previous_millis_ = 0;
- 80005c6: 687b ldr r3, [r7, #4]
- 80005c8: 2200 movs r2, #0
- 80005ca: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005cc: f001 fb80 bl 8001cd0 <HAL_GetTick>
- 80005d0: 4602 mov r2, r0
- 80005d2: 687b ldr r3, [r7, #4]
- 80005d4: 609a str r2, [r3, #8]
-}
- 80005d6: bf00 nop
- 80005d8: 3708 adds r7, #8
- 80005da: 46bd mov sp, r7
- 80005dc: bd80 pop {r7, pc}
-
-080005de <_ZN7Encoder12UpdateValuesEv>:
-
-void Encoder::UpdateValues() {
- 80005de: b580 push {r7, lr}
- 80005e0: b082 sub sp, #8
- 80005e2: af00 add r7, sp, #0
- 80005e4: 6078 str r0, [r7, #4]
- this->previous_millis_ = this->current_millis_;
- 80005e6: 687b ldr r3, [r7, #4]
- 80005e8: 689a ldr r2, [r3, #8]
- 80005ea: 687b ldr r3, [r7, #4]
- 80005ec: 605a str r2, [r3, #4]
- this->current_millis_ = HAL_GetTick();
- 80005ee: f001 fb6f bl 8001cd0 <HAL_GetTick>
- 80005f2: 4602 mov r2, r0
- 80005f4: 687b ldr r3, [r7, #4]
- 80005f6: 609a str r2, [r3, #8]
- this->ticks_ = this->GetCount();
- 80005f8: 6878 ldr r0, [r7, #4]
- 80005fa: f7ff ff9d bl 8000538 <_ZN7Encoder8GetCountEv>
- 80005fe: 4602 mov r2, r0
- 8000600: 687b ldr r3, [r7, #4]
- 8000602: 60da str r2, [r3, #12]
- this->ResetCount();
- 8000604: 6878 ldr r0, [r7, #4]
- 8000606: f7ff ffac bl 8000562 <_ZN7Encoder10ResetCountEv>
-}
- 800060a: bf00 nop
- 800060c: 3708 adds r7, #8
- 800060e: 46bd mov sp, r7
- 8000610: bd80 pop {r7, pc}
-
-08000612 <_ZN7Encoder9GetMetersEv>:
-// float meters = ((float) this->ticks_ * this->wheel_circumference_)
-// / TICKS_PER_REVOLUTION;
-// return meters;
-//}
-
-float Encoder::GetMeters() {
- 8000612: b480 push {r7}
- 8000614: b085 sub sp, #20
- 8000616: af00 add r7, sp, #0
- 8000618: 6078 str r0, [r7, #4]
- float meters = (((float) this->ticks_) / this->ticks_per_meter_);
- 800061a: 687b ldr r3, [r7, #4]
- 800061c: 68db ldr r3, [r3, #12]
- 800061e: ee07 3a90 vmov s15, r3
- 8000622: eef8 6ae7 vcvt.f32.s32 s13, s15
- 8000626: 687b ldr r3, [r7, #4]
- 8000628: 695b ldr r3, [r3, #20]
- 800062a: ee07 3a90 vmov s15, r3
- 800062e: eeb8 7ae7 vcvt.f32.s32 s14, s15
- 8000632: eec6 7a87 vdiv.f32 s15, s13, s14
- 8000636: edc7 7a03 vstr s15, [r7, #12]
- return meters;
- 800063a: 68fb ldr r3, [r7, #12]
- 800063c: ee07 3a90 vmov s15, r3
-}
- 8000640: eeb0 0a67 vmov.f32 s0, s15
- 8000644: 3714 adds r7, #20
- 8000646: 46bd mov sp, r7
- 8000648: f85d 7b04 ldr.w r7, [sp], #4
- 800064c: 4770 bx lr
- ...
-
-08000650 <_ZN7Encoder17GetLinearVelocityEv>:
-
-
-float Encoder::GetLinearVelocity() {
- 8000650: b580 push {r7, lr}
- 8000652: b086 sub sp, #24
- 8000654: af00 add r7, sp, #0
- 8000656: 6078 str r0, [r7, #4]
- this->UpdateValues();
- 8000658: 6878 ldr r0, [r7, #4]
- 800065a: f7ff ffc0 bl 80005de <_ZN7Encoder12UpdateValuesEv>
- float meters = this->GetMeters();
- 800065e: 6878 ldr r0, [r7, #4]
- 8000660: f7ff ffd7 bl 8000612 <_ZN7Encoder9GetMetersEv>
- 8000664: ed87 0a05 vstr s0, [r7, #20]
- float deltaTime = this->current_millis_ - this->previous_millis_;
- 8000668: 687b ldr r3, [r7, #4]
- 800066a: 689a ldr r2, [r3, #8]
- 800066c: 687b ldr r3, [r7, #4]
- 800066e: 685b ldr r3, [r3, #4]
- 8000670: 1ad3 subs r3, r2, r3
- 8000672: ee07 3a90 vmov s15, r3
- 8000676: eef8 7a67 vcvt.f32.u32 s15, s15
- 800067a: edc7 7a04 vstr s15, [r7, #16]
- if (deltaTime == 0)
- 800067e: edd7 7a04 vldr s15, [r7, #16]
- 8000682: eef5 7a40 vcmp.f32 s15, #0.0
- 8000686: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800068a: d102 bne.n 8000692 <_ZN7Encoder17GetLinearVelocityEv+0x42>
- return 0;
- 800068c: f04f 0300 mov.w r3, #0
- 8000690: e00c b.n 80006ac <_ZN7Encoder17GetLinearVelocityEv+0x5c>
- float linear_velocity = (meters / (deltaTime / 1000));
- 8000692: edd7 7a04 vldr s15, [r7, #16]
- 8000696: eddf 6a09 vldr s13, [pc, #36] ; 80006bc <_ZN7Encoder17GetLinearVelocityEv+0x6c>
- 800069a: ee87 7aa6 vdiv.f32 s14, s15, s13
- 800069e: edd7 6a05 vldr s13, [r7, #20]
- 80006a2: eec6 7a87 vdiv.f32 s15, s13, s14
- 80006a6: edc7 7a03 vstr s15, [r7, #12]
- return linear_velocity;
- 80006aa: 68fb ldr r3, [r7, #12]
- 80006ac: ee07 3a90 vmov s15, r3
-}
- 80006b0: eeb0 0a67 vmov.f32 s0, s15
- 80006b4: 3718 adds r7, #24
- 80006b6: 46bd mov sp, r7
- 80006b8: bd80 pop {r7, pc}
- 80006ba: bf00 nop
- 80006bc: 447a0000 .word 0x447a0000
-
-080006c0 <_ZN8OdometryC1Ev>:
- float left_velocity_;
- float right_velocity_;
-
-
- public:
- Odometry() {
- 80006c0: b480 push {r7}
- 80006c2: b083 sub sp, #12
- 80006c4: af00 add r7, sp, #0
- 80006c6: 6078 str r0, [r7, #4]
- left_velocity_ = 0;
- 80006c8: 687b ldr r3, [r7, #4]
- 80006ca: f04f 0200 mov.w r2, #0
- 80006ce: 601a str r2, [r3, #0]
- right_velocity_ = 0;
- 80006d0: 687b ldr r3, [r7, #4]
- 80006d2: f04f 0200 mov.w r2, #0
- 80006d6: 605a str r2, [r3, #4]
- }
- 80006d8: 687b ldr r3, [r7, #4]
- 80006da: 4618 mov r0, r3
- 80006dc: 370c adds r7, #12
- 80006de: 46bd mov sp, r7
- 80006e0: f85d 7b04 ldr.w r7, [sp], #4
- 80006e4: 4770 bx lr
- ...
-
-080006e8 <_ZN8Odometry12UpdateValuesEff>:
-
- void UpdateValues(float linear_vel, float angular_vel) {
- 80006e8: b480 push {r7}
- 80006ea: b085 sub sp, #20
- 80006ec: af00 add r7, sp, #0
- 80006ee: 60f8 str r0, [r7, #12]
- 80006f0: ed87 0a02 vstr s0, [r7, #8]
- 80006f4: edc7 0a01 vstr s1, [r7, #4]
- left_velocity_ = linear_vel - (BASELINE * angular_vel)/2;
- 80006f8: edd7 7a02 vldr s15, [r7, #8]
- 80006fc: eeb7 6ae7 vcvt.f64.f32 d6, s15
- 8000700: edd7 7a01 vldr s15, [r7, #4]
- 8000704: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 8000708: ed9f 5b15 vldr d5, [pc, #84] ; 8000760 <_ZN8Odometry12UpdateValuesEff+0x78>
- 800070c: ee27 5b05 vmul.f64 d5, d7, d5
- 8000710: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 8000714: ee85 7b04 vdiv.f64 d7, d5, d4
- 8000718: ee36 7b47 vsub.f64 d7, d6, d7
- 800071c: eef7 7bc7 vcvt.f32.f64 s15, d7
- 8000720: 68fb ldr r3, [r7, #12]
- 8000722: edc3 7a00 vstr s15, [r3]
- right_velocity_ = linear_vel + (BASELINE * angular_vel)/2;
- 8000726: edd7 7a02 vldr s15, [r7, #8]
- 800072a: eeb7 6ae7 vcvt.f64.f32 d6, s15
- 800072e: edd7 7a01 vldr s15, [r7, #4]
- 8000732: eeb7 7ae7 vcvt.f64.f32 d7, s15
- 8000736: ed9f 5b0a vldr d5, [pc, #40] ; 8000760 <_ZN8Odometry12UpdateValuesEff+0x78>
- 800073a: ee27 5b05 vmul.f64 d5, d7, d5
- 800073e: eeb0 4b00 vmov.f64 d4, #0 ; 0x40000000 2.0
- 8000742: ee85 7b04 vdiv.f64 d7, d5, d4
- 8000746: ee36 7b07 vadd.f64 d7, d6, d7
- 800074a: eef7 7bc7 vcvt.f32.f64 s15, d7
- 800074e: 68fb ldr r3, [r7, #12]
- 8000750: edc3 7a01 vstr s15, [r3, #4]
- }
- 8000754: bf00 nop
- 8000756: 3714 adds r7, #20
- 8000758: 46bd mov sp, r7
- 800075a: f85d 7b04 ldr.w r7, [sp], #4
- 800075e: 4770 bx lr
- 8000760: 33333333 .word 0x33333333
- 8000764: 3fd33333 .word 0x3fd33333
-
-08000768 <_ZN8Odometry15GetLeftVelocityEv>:
-
- float GetLeftVelocity(){
- 8000768: b480 push {r7}
- 800076a: b083 sub sp, #12
- 800076c: af00 add r7, sp, #0
- 800076e: 6078 str r0, [r7, #4]
- return left_velocity_;
- 8000770: 687b ldr r3, [r7, #4]
- 8000772: 681b ldr r3, [r3, #0]
- 8000774: ee07 3a90 vmov s15, r3
- }
- 8000778: eeb0 0a67 vmov.f32 s0, s15
- 800077c: 370c adds r7, #12
- 800077e: 46bd mov sp, r7
- 8000780: f85d 7b04 ldr.w r7, [sp], #4
- 8000784: 4770 bx lr
-
-08000786 <_ZN8Odometry16GetRightVelocityEv>:
- float GetRightVelocity(){
- 8000786: b480 push {r7}
- 8000788: b083 sub sp, #12
- 800078a: af00 add r7, sp, #0
- 800078c: 6078 str r0, [r7, #4]
- return right_velocity_;
- 800078e: 687b ldr r3, [r7, #4]
- 8000790: 685b ldr r3, [r3, #4]
- 8000792: ee07 3a90 vmov s15, r3
- }
- 8000796: eeb0 0a67 vmov.f32 s0, s15
- 800079a: 370c adds r7, #12
- 800079c: 46bd mov sp, r7
- 800079e: f85d 7b04 ldr.w r7, [sp], #4
- 80007a2: 4770 bx lr
-
-080007a4 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>:
- GPIO_TypeDef *dir_gpio_port_;
- uint16_t dir_pin_;
- TIM_HandleTypeDef *pwm_timer_;
- uint32_t pwm_channel_;
-
- MotorController(GPIO_TypeDef *sleep_gpio_port, uint16_t sleep_pin,
- 80007a4: b480 push {r7}
- 80007a6: b085 sub sp, #20
- 80007a8: af00 add r7, sp, #0
- 80007aa: 60f8 str r0, [r7, #12]
- 80007ac: 60b9 str r1, [r7, #8]
- 80007ae: 603b str r3, [r7, #0]
- 80007b0: 4613 mov r3, r2
- 80007b2: 80fb strh r3, [r7, #6]
- GPIO_TypeDef *dir_gpio_port, uint16_t dir_pin,
- TIM_HandleTypeDef *pwm_timer, uint32_t pwm_channel) {
- this->sleep_gpio_port_ = sleep_gpio_port;
- 80007b4: 68fb ldr r3, [r7, #12]
- 80007b6: 68ba ldr r2, [r7, #8]
- 80007b8: 601a str r2, [r3, #0]
- this->sleep_pin_ = sleep_pin;
- 80007ba: 68fb ldr r3, [r7, #12]
- 80007bc: 88fa ldrh r2, [r7, #6]
- 80007be: 809a strh r2, [r3, #4]
- this->dir_gpio_port_ = dir_gpio_port;
- 80007c0: 68fb ldr r3, [r7, #12]
- 80007c2: 683a ldr r2, [r7, #0]
- 80007c4: 609a str r2, [r3, #8]
- this->dir_pin_ = dir_pin;
- 80007c6: 68fb ldr r3, [r7, #12]
- 80007c8: 8b3a ldrh r2, [r7, #24]
- 80007ca: 819a strh r2, [r3, #12]
- this->pwm_timer_ = pwm_timer;
- 80007cc: 68fb ldr r3, [r7, #12]
- 80007ce: 69fa ldr r2, [r7, #28]
- 80007d0: 611a str r2, [r3, #16]
- this->pwm_channel_ = pwm_channel;
- 80007d2: 68fb ldr r3, [r7, #12]
- 80007d4: 6a3a ldr r2, [r7, #32]
- 80007d6: 615a str r2, [r3, #20]
- }
- 80007d8: 68fb ldr r3, [r7, #12]
- 80007da: 4618 mov r0, r3
- 80007dc: 3714 adds r7, #20
- 80007de: 46bd mov sp, r7
- 80007e0: f85d 7b04 ldr.w r7, [sp], #4
- 80007e4: 4770 bx lr
-
-080007e6 <_ZN15MotorController5setupEv>:
-
- void setup() {
- 80007e6: b580 push {r7, lr}
- 80007e8: b082 sub sp, #8
- 80007ea: af00 add r7, sp, #0
- 80007ec: 6078 str r0, [r7, #4]
- HAL_TIM_PWM_Start(pwm_timer_, pwm_channel_);
- 80007ee: 687b ldr r3, [r7, #4]
- 80007f0: 691a ldr r2, [r3, #16]
- 80007f2: 687b ldr r3, [r7, #4]
- 80007f4: 695b ldr r3, [r3, #20]
- 80007f6: 4619 mov r1, r3
- 80007f8: 4610 mov r0, r2
- 80007fa: f002 fe77 bl 80034ec <HAL_TIM_PWM_Start>
- }
- 80007fe: bf00 nop
- 8000800: 3708 adds r7, #8
- 8000802: 46bd mov sp, r7
- 8000804: bd80 pop {r7, pc}
- ...
-
-08000808 <_ZN15MotorController9set_speedEi>:
-
- void set_speed(int duty_cycle) {
- 8000808: b580 push {r7, lr}
- 800080a: b082 sub sp, #8
- 800080c: af00 add r7, sp, #0
- 800080e: 6078 str r0, [r7, #4]
- 8000810: 6039 str r1, [r7, #0]
- if (duty_cycle >= 0) {
- 8000812: 683b ldr r3, [r7, #0]
- 8000814: 2b00 cmp r3, #0
- 8000816: f2c0 8083 blt.w 8000920 <_ZN15MotorController9set_speedEi+0x118>
- //set direction to forward
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
- 800081a: 687b ldr r3, [r7, #4]
- 800081c: 6898 ldr r0, [r3, #8]
- 800081e: 687b ldr r3, [r7, #4]
- 8000820: 899b ldrh r3, [r3, #12]
- 8000822: 2201 movs r2, #1
- 8000824: 4619 mov r1, r3
- 8000826: f001 fd3d bl 80022a4 <HAL_GPIO_WritePin>
-
- //check if duty_cycle exceeds maximum
- if (duty_cycle > MAX_DUTY_CYCLE)
- 800082a: 683b ldr r3, [r7, #0]
- 800082c: f240 3216 movw r2, #790 ; 0x316
- 8000830: 4293 cmp r3, r2
- 8000832: dd3d ble.n 80008b0 <_ZN15MotorController9set_speedEi+0xa8>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 8000834: 687b ldr r3, [r7, #4]
- 8000836: 695b ldr r3, [r3, #20]
- 8000838: 2b00 cmp r3, #0
- 800083a: d106 bne.n 800084a <_ZN15MotorController9set_speedEi+0x42>
- 800083c: 687b ldr r3, [r7, #4]
- 800083e: 691b ldr r3, [r3, #16]
- 8000840: 681b ldr r3, [r3, #0]
- 8000842: f240 3216 movw r2, #790 ; 0x316
- 8000846: 635a str r2, [r3, #52] ; 0x34
- 8000848: e0f5 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 800084a: 687b ldr r3, [r7, #4]
- 800084c: 695b ldr r3, [r3, #20]
- 800084e: 2b04 cmp r3, #4
- 8000850: d106 bne.n 8000860 <_ZN15MotorController9set_speedEi+0x58>
- 8000852: 687b ldr r3, [r7, #4]
- 8000854: 691b ldr r3, [r3, #16]
- 8000856: 681b ldr r3, [r3, #0]
- 8000858: f240 3216 movw r2, #790 ; 0x316
- 800085c: 639a str r2, [r3, #56] ; 0x38
- 800085e: e0ea b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000860: 687b ldr r3, [r7, #4]
- 8000862: 695b ldr r3, [r3, #20]
- 8000864: 2b08 cmp r3, #8
- 8000866: d106 bne.n 8000876 <_ZN15MotorController9set_speedEi+0x6e>
- 8000868: 687b ldr r3, [r7, #4]
- 800086a: 691b ldr r3, [r3, #16]
- 800086c: 681b ldr r3, [r3, #0]
- 800086e: f240 3216 movw r2, #790 ; 0x316
- 8000872: 63da str r2, [r3, #60] ; 0x3c
- 8000874: e0df b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000876: 687b ldr r3, [r7, #4]
- 8000878: 695b ldr r3, [r3, #20]
- 800087a: 2b0c cmp r3, #12
- 800087c: d106 bne.n 800088c <_ZN15MotorController9set_speedEi+0x84>
- 800087e: 687b ldr r3, [r7, #4]
- 8000880: 691b ldr r3, [r3, #16]
- 8000882: 681b ldr r3, [r3, #0]
- 8000884: f240 3216 movw r2, #790 ; 0x316
- 8000888: 641a str r2, [r3, #64] ; 0x40
- 800088a: e0d4 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 800088c: 687b ldr r3, [r7, #4]
- 800088e: 695b ldr r3, [r3, #20]
- 8000890: 2b10 cmp r3, #16
- 8000892: d106 bne.n 80008a2 <_ZN15MotorController9set_speedEi+0x9a>
- 8000894: 687b ldr r3, [r7, #4]
- 8000896: 691b ldr r3, [r3, #16]
- 8000898: 681b ldr r3, [r3, #0]
- 800089a: f240 3216 movw r2, #790 ; 0x316
- 800089e: 659a str r2, [r3, #88] ; 0x58
- 80008a0: e0c9 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008a2: 687b ldr r3, [r7, #4]
- 80008a4: 691b ldr r3, [r3, #16]
- 80008a6: 681b ldr r3, [r3, #0]
- 80008a8: f240 3216 movw r2, #790 ; 0x316
- 80008ac: 65da str r2, [r3, #92] ; 0x5c
- 80008ae: e0c2 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- else
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 80008b0: 687b ldr r3, [r7, #4]
- 80008b2: 695b ldr r3, [r3, #20]
- 80008b4: 2b00 cmp r3, #0
- 80008b6: d105 bne.n 80008c4 <_ZN15MotorController9set_speedEi+0xbc>
- 80008b8: 683a ldr r2, [r7, #0]
- 80008ba: 687b ldr r3, [r7, #4]
- 80008bc: 691b ldr r3, [r3, #16]
- 80008be: 681b ldr r3, [r3, #0]
- 80008c0: 635a str r2, [r3, #52] ; 0x34
- 80008c2: e0b8 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008c4: 687b ldr r3, [r7, #4]
- 80008c6: 695b ldr r3, [r3, #20]
- 80008c8: 2b04 cmp r3, #4
- 80008ca: d105 bne.n 80008d8 <_ZN15MotorController9set_speedEi+0xd0>
- 80008cc: 683a ldr r2, [r7, #0]
- 80008ce: 687b ldr r3, [r7, #4]
- 80008d0: 691b ldr r3, [r3, #16]
- 80008d2: 681b ldr r3, [r3, #0]
- 80008d4: 639a str r2, [r3, #56] ; 0x38
- 80008d6: e0ae b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008d8: 687b ldr r3, [r7, #4]
- 80008da: 695b ldr r3, [r3, #20]
- 80008dc: 2b08 cmp r3, #8
- 80008de: d105 bne.n 80008ec <_ZN15MotorController9set_speedEi+0xe4>
- 80008e0: 683a ldr r2, [r7, #0]
- 80008e2: 687b ldr r3, [r7, #4]
- 80008e4: 691b ldr r3, [r3, #16]
- 80008e6: 681b ldr r3, [r3, #0]
- 80008e8: 63da str r2, [r3, #60] ; 0x3c
- 80008ea: e0a4 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80008ec: 687b ldr r3, [r7, #4]
- 80008ee: 695b ldr r3, [r3, #20]
- 80008f0: 2b0c cmp r3, #12
- 80008f2: d105 bne.n 8000900 <_ZN15MotorController9set_speedEi+0xf8>
- 80008f4: 683a ldr r2, [r7, #0]
- 80008f6: 687b ldr r3, [r7, #4]
- 80008f8: 691b ldr r3, [r3, #16]
- 80008fa: 681b ldr r3, [r3, #0]
- 80008fc: 641a str r2, [r3, #64] ; 0x40
- 80008fe: e09a b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000900: 687b ldr r3, [r7, #4]
- 8000902: 695b ldr r3, [r3, #20]
- 8000904: 2b10 cmp r3, #16
- 8000906: d105 bne.n 8000914 <_ZN15MotorController9set_speedEi+0x10c>
- 8000908: 683a ldr r2, [r7, #0]
- 800090a: 687b ldr r3, [r7, #4]
- 800090c: 691b ldr r3, [r3, #16]
- 800090e: 681b ldr r3, [r3, #0]
- 8000910: 659a str r2, [r3, #88] ; 0x58
- 8000912: e090 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000914: 683a ldr r2, [r7, #0]
- 8000916: 687b ldr r3, [r7, #4]
- 8000918: 691b ldr r3, [r3, #16]
- 800091a: 681b ldr r3, [r3, #0]
- 800091c: 65da str r2, [r3, #92] ; 0x5c
- 800091e: e08a b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
-
- } else if (duty_cycle < 0){
- 8000920: 683b ldr r3, [r7, #0]
- 8000922: 2b00 cmp r3, #0
- 8000924: f280 8087 bge.w 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- //set direction to backwards
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET);
- 8000928: 687b ldr r3, [r7, #4]
- 800092a: 6898 ldr r0, [r3, #8]
- 800092c: 687b ldr r3, [r7, #4]
- 800092e: 899b ldrh r3, [r3, #12]
- 8000930: 2200 movs r2, #0
- 8000932: 4619 mov r1, r3
- 8000934: f001 fcb6 bl 80022a4 <HAL_GPIO_WritePin>
-
- //check if duty_cycle is lower than minimum
- if (duty_cycle < -MAX_DUTY_CYCLE)
- 8000938: 683b ldr r3, [r7, #0]
- 800093a: 4a45 ldr r2, [pc, #276] ; (8000a50 <_ZN15MotorController9set_speedEi+0x248>)
- 800093c: 4293 cmp r3, r2
- 800093e: da3d bge.n 80009bc <_ZN15MotorController9set_speedEi+0x1b4>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, MAX_DUTY_CYCLE);
- 8000940: 687b ldr r3, [r7, #4]
- 8000942: 695b ldr r3, [r3, #20]
- 8000944: 2b00 cmp r3, #0
- 8000946: d106 bne.n 8000956 <_ZN15MotorController9set_speedEi+0x14e>
- 8000948: 687b ldr r3, [r7, #4]
- 800094a: 691b ldr r3, [r3, #16]
- 800094c: 681b ldr r3, [r3, #0]
- 800094e: f240 3216 movw r2, #790 ; 0x316
- 8000952: 635a str r2, [r3, #52] ; 0x34
- 8000954: e06f b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000956: 687b ldr r3, [r7, #4]
- 8000958: 695b ldr r3, [r3, #20]
- 800095a: 2b04 cmp r3, #4
- 800095c: d106 bne.n 800096c <_ZN15MotorController9set_speedEi+0x164>
- 800095e: 687b ldr r3, [r7, #4]
- 8000960: 691b ldr r3, [r3, #16]
- 8000962: 681b ldr r3, [r3, #0]
- 8000964: f240 3216 movw r2, #790 ; 0x316
- 8000968: 639a str r2, [r3, #56] ; 0x38
- 800096a: e064 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 800096c: 687b ldr r3, [r7, #4]
- 800096e: 695b ldr r3, [r3, #20]
- 8000970: 2b08 cmp r3, #8
- 8000972: d106 bne.n 8000982 <_ZN15MotorController9set_speedEi+0x17a>
- 8000974: 687b ldr r3, [r7, #4]
- 8000976: 691b ldr r3, [r3, #16]
- 8000978: 681b ldr r3, [r3, #0]
- 800097a: f240 3216 movw r2, #790 ; 0x316
- 800097e: 63da str r2, [r3, #60] ; 0x3c
- 8000980: e059 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000982: 687b ldr r3, [r7, #4]
- 8000984: 695b ldr r3, [r3, #20]
- 8000986: 2b0c cmp r3, #12
- 8000988: d106 bne.n 8000998 <_ZN15MotorController9set_speedEi+0x190>
- 800098a: 687b ldr r3, [r7, #4]
- 800098c: 691b ldr r3, [r3, #16]
- 800098e: 681b ldr r3, [r3, #0]
- 8000990: f240 3216 movw r2, #790 ; 0x316
- 8000994: 641a str r2, [r3, #64] ; 0x40
- 8000996: e04e b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000998: 687b ldr r3, [r7, #4]
- 800099a: 695b ldr r3, [r3, #20]
- 800099c: 2b10 cmp r3, #16
- 800099e: d106 bne.n 80009ae <_ZN15MotorController9set_speedEi+0x1a6>
- 80009a0: 687b ldr r3, [r7, #4]
- 80009a2: 691b ldr r3, [r3, #16]
- 80009a4: 681b ldr r3, [r3, #0]
- 80009a6: f240 3216 movw r2, #790 ; 0x316
- 80009aa: 659a str r2, [r3, #88] ; 0x58
- 80009ac: e043 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009ae: 687b ldr r3, [r7, #4]
- 80009b0: 691b ldr r3, [r3, #16]
- 80009b2: 681b ldr r3, [r3, #0]
- 80009b4: f240 3216 movw r2, #790 ; 0x316
- 80009b8: 65da str r2, [r3, #92] ; 0x5c
- 80009ba: e03c b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- else
- //invert sign to make duty_cycle positive
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 80009bc: 687b ldr r3, [r7, #4]
- 80009be: 695b ldr r3, [r3, #20]
- 80009c0: 2b00 cmp r3, #0
- 80009c2: d106 bne.n 80009d2 <_ZN15MotorController9set_speedEi+0x1ca>
- 80009c4: 683b ldr r3, [r7, #0]
- 80009c6: 425a negs r2, r3
- 80009c8: 687b ldr r3, [r7, #4]
- 80009ca: 691b ldr r3, [r3, #16]
- 80009cc: 681b ldr r3, [r3, #0]
- 80009ce: 635a str r2, [r3, #52] ; 0x34
- 80009d0: e031 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009d2: 687b ldr r3, [r7, #4]
- 80009d4: 695b ldr r3, [r3, #20]
- 80009d6: 2b04 cmp r3, #4
- 80009d8: d106 bne.n 80009e8 <_ZN15MotorController9set_speedEi+0x1e0>
- 80009da: 683b ldr r3, [r7, #0]
- 80009dc: 425a negs r2, r3
- 80009de: 687b ldr r3, [r7, #4]
- 80009e0: 691b ldr r3, [r3, #16]
- 80009e2: 681b ldr r3, [r3, #0]
- 80009e4: 639a str r2, [r3, #56] ; 0x38
- 80009e6: e026 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009e8: 687b ldr r3, [r7, #4]
- 80009ea: 695b ldr r3, [r3, #20]
- 80009ec: 2b08 cmp r3, #8
- 80009ee: d106 bne.n 80009fe <_ZN15MotorController9set_speedEi+0x1f6>
- 80009f0: 683b ldr r3, [r7, #0]
- 80009f2: 425a negs r2, r3
- 80009f4: 687b ldr r3, [r7, #4]
- 80009f6: 691b ldr r3, [r3, #16]
- 80009f8: 681b ldr r3, [r3, #0]
- 80009fa: 63da str r2, [r3, #60] ; 0x3c
- 80009fc: e01b b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 80009fe: 687b ldr r3, [r7, #4]
- 8000a00: 695b ldr r3, [r3, #20]
- 8000a02: 2b0c cmp r3, #12
- 8000a04: d106 bne.n 8000a14 <_ZN15MotorController9set_speedEi+0x20c>
- 8000a06: 683b ldr r3, [r7, #0]
- 8000a08: 425a negs r2, r3
- 8000a0a: 687b ldr r3, [r7, #4]
- 8000a0c: 691b ldr r3, [r3, #16]
- 8000a0e: 681b ldr r3, [r3, #0]
- 8000a10: 641a str r2, [r3, #64] ; 0x40
- 8000a12: e010 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000a14: 687b ldr r3, [r7, #4]
- 8000a16: 695b ldr r3, [r3, #20]
- 8000a18: 2b10 cmp r3, #16
- 8000a1a: d106 bne.n 8000a2a <_ZN15MotorController9set_speedEi+0x222>
- 8000a1c: 683b ldr r3, [r7, #0]
- 8000a1e: 425a negs r2, r3
- 8000a20: 687b ldr r3, [r7, #4]
- 8000a22: 691b ldr r3, [r3, #16]
- 8000a24: 681b ldr r3, [r3, #0]
- 8000a26: 659a str r2, [r3, #88] ; 0x58
- 8000a28: e005 b.n 8000a36 <_ZN15MotorController9set_speedEi+0x22e>
- 8000a2a: 683b ldr r3, [r7, #0]
- 8000a2c: 425a negs r2, r3
- 8000a2e: 687b ldr r3, [r7, #4]
- 8000a30: 691b ldr r3, [r3, #16]
- 8000a32: 681b ldr r3, [r3, #0]
- 8000a34: 65da str r2, [r3, #92] ; 0x5c
- }
-
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- 8000a36: 687b ldr r3, [r7, #4]
- 8000a38: 6818 ldr r0, [r3, #0]
- 8000a3a: 687b ldr r3, [r7, #4]
- 8000a3c: 889b ldrh r3, [r3, #4]
- 8000a3e: 2201 movs r2, #1
- 8000a40: 4619 mov r1, r3
- 8000a42: f001 fc2f bl 80022a4 <HAL_GPIO_WritePin>
-
- }
- 8000a46: bf00 nop
- 8000a48: 3708 adds r7, #8
- 8000a4a: 46bd mov sp, r7
- 8000a4c: bd80 pop {r7, pc}
- 8000a4e: bf00 nop
- 8000a50: fffffcea .word 0xfffffcea
-
-08000a54 <_ZN15MotorController5coastEv>:
- void brake() {
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- }
-
- void coast() {
- 8000a54: b580 push {r7, lr}
- 8000a56: b082 sub sp, #8
- 8000a58: af00 add r7, sp, #0
- 8000a5a: 6078 str r0, [r7, #4]
- HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_RESET);
- 8000a5c: 687b ldr r3, [r7, #4]
- 8000a5e: 6818 ldr r0, [r3, #0]
- 8000a60: 687b ldr r3, [r7, #4]
- 8000a62: 889b ldrh r3, [r3, #4]
- 8000a64: 2200 movs r2, #0
- 8000a66: 4619 mov r1, r3
- 8000a68: f001 fc1c bl 80022a4 <HAL_GPIO_WritePin>
- }
- 8000a6c: bf00 nop
- 8000a6e: 3708 adds r7, #8
- 8000a70: 46bd mov sp, r7
- 8000a72: bd80 pop {r7, pc}
-
-08000a74 <_ZN3PidC1Efff>:
- float previous_error_;
-
- int min_;
- int max_;
-
- Pid(float kp, float ki, float kd) {
- 8000a74: b480 push {r7}
- 8000a76: b085 sub sp, #20
- 8000a78: af00 add r7, sp, #0
- 8000a7a: 60f8 str r0, [r7, #12]
- 8000a7c: ed87 0a02 vstr s0, [r7, #8]
- 8000a80: edc7 0a01 vstr s1, [r7, #4]
- 8000a84: ed87 1a00 vstr s2, [r7]
- this->kp_ = kp;
- 8000a88: 68fb ldr r3, [r7, #12]
- 8000a8a: 68ba ldr r2, [r7, #8]
- 8000a8c: 601a str r2, [r3, #0]
- this->ki_ = ki;
- 8000a8e: 68fb ldr r3, [r7, #12]
- 8000a90: 687a ldr r2, [r7, #4]
- 8000a92: 605a str r2, [r3, #4]
- this->kd_ = kd;
- 8000a94: 68fb ldr r3, [r7, #12]
- 8000a96: 683a ldr r2, [r7, #0]
- 8000a98: 609a str r2, [r3, #8]
-
- this->error_ = 0;
- 8000a9a: 68fb ldr r3, [r7, #12]
- 8000a9c: f04f 0200 mov.w r2, #0
- 8000aa0: 60da str r2, [r3, #12]
- this->setpoint_ = 0;
- 8000aa2: 68fb ldr r3, [r7, #12]
- 8000aa4: f04f 0200 mov.w r2, #0
- 8000aa8: 611a str r2, [r3, #16]
-
- this->previous_error_ = 0;
- 8000aaa: 68fb ldr r3, [r7, #12]
- 8000aac: f04f 0200 mov.w r2, #0
- 8000ab0: 619a str r2, [r3, #24]
- this->error_sum_ = 0;
- 8000ab2: 68fb ldr r3, [r7, #12]
- 8000ab4: f04f 0200 mov.w r2, #0
- 8000ab8: 615a str r2, [r3, #20]
-
- this->min_ = -MAX_DUTY_CYCLE;
- 8000aba: 68fb ldr r3, [r7, #12]
- 8000abc: 4a06 ldr r2, [pc, #24] ; (8000ad8 <_ZN3PidC1Efff+0x64>)
- 8000abe: 61da str r2, [r3, #28]
- this->max_ = MAX_DUTY_CYCLE;
- 8000ac0: 68fb ldr r3, [r7, #12]
- 8000ac2: f240 3216 movw r2, #790 ; 0x316
- 8000ac6: 621a str r2, [r3, #32]
-
- }
- 8000ac8: 68fb ldr r3, [r7, #12]
- 8000aca: 4618 mov r0, r3
- 8000acc: 3714 adds r7, #20
- 8000ace: 46bd mov sp, r7
- 8000ad0: f85d 7b04 ldr.w r7, [sp], #4
- 8000ad4: 4770 bx lr
- 8000ad6: bf00 nop
- 8000ad8: fffffcea .word 0xfffffcea
-
-08000adc <_ZN3Pid6configEfff>:
-
- void config(float kp, float ki, float kd) {
- 8000adc: b480 push {r7}
- 8000ade: b085 sub sp, #20
- 8000ae0: af00 add r7, sp, #0
- 8000ae2: 60f8 str r0, [r7, #12]
- 8000ae4: ed87 0a02 vstr s0, [r7, #8]
- 8000ae8: edc7 0a01 vstr s1, [r7, #4]
- 8000aec: ed87 1a00 vstr s2, [r7]
- this->kp_ = kp;
- 8000af0: 68fb ldr r3, [r7, #12]
- 8000af2: 68ba ldr r2, [r7, #8]
- 8000af4: 601a str r2, [r3, #0]
- this->ki_ = ki;
- 8000af6: 68fb ldr r3, [r7, #12]
- 8000af8: 687a ldr r2, [r7, #4]
- 8000afa: 605a str r2, [r3, #4]
- this->kd_ = kd;
- 8000afc: 68fb ldr r3, [r7, #12]
- 8000afe: 683a ldr r2, [r7, #0]
- 8000b00: 609a str r2, [r3, #8]
-
- this->error_ = 0;
- 8000b02: 68fb ldr r3, [r7, #12]
- 8000b04: f04f 0200 mov.w r2, #0
- 8000b08: 60da str r2, [r3, #12]
- this->setpoint_ = 0;
- 8000b0a: 68fb ldr r3, [r7, #12]
- 8000b0c: f04f 0200 mov.w r2, #0
- 8000b10: 611a str r2, [r3, #16]
-
- this->previous_error_ = 0;
- 8000b12: 68fb ldr r3, [r7, #12]
- 8000b14: f04f 0200 mov.w r2, #0
- 8000b18: 619a str r2, [r3, #24]
- this->error_sum_ = 0;
- 8000b1a: 68fb ldr r3, [r7, #12]
- 8000b1c: f04f 0200 mov.w r2, #0
- 8000b20: 615a str r2, [r3, #20]
-
- }
- 8000b22: bf00 nop
- 8000b24: 3714 adds r7, #20
- 8000b26: 46bd mov sp, r7
- 8000b28: f85d 7b04 ldr.w r7, [sp], #4
- 8000b2c: 4770 bx lr
-
-08000b2e <_ZN3Pid3setEf>:
-
- void set(float setpoint) {
- 8000b2e: b480 push {r7}
- 8000b30: b083 sub sp, #12
- 8000b32: af00 add r7, sp, #0
- 8000b34: 6078 str r0, [r7, #4]
- 8000b36: ed87 0a00 vstr s0, [r7]
- this->setpoint_ = setpoint;
- 8000b3a: 687b ldr r3, [r7, #4]
- 8000b3c: 683a ldr r2, [r7, #0]
- 8000b3e: 611a str r2, [r3, #16]
- }
- 8000b40: bf00 nop
- 8000b42: 370c adds r7, #12
- 8000b44: 46bd mov sp, r7
- 8000b46: f85d 7b04 ldr.w r7, [sp], #4
- 8000b4a: 4770 bx lr
-
-08000b4c <_ZN3Pid6updateEf>:
-
- int update(float measure) {
- 8000b4c: b480 push {r7}
- 8000b4e: b085 sub sp, #20
- 8000b50: af00 add r7, sp, #0
- 8000b52: 6078 str r0, [r7, #4]
- 8000b54: ed87 0a00 vstr s0, [r7]
-
- this->error_ = this->setpoint_ - measure;
- 8000b58: 687b ldr r3, [r7, #4]
- 8000b5a: ed93 7a04 vldr s14, [r3, #16]
- 8000b5e: edd7 7a00 vldr s15, [r7]
- 8000b62: ee77 7a67 vsub.f32 s15, s14, s15
- 8000b66: 687b ldr r3, [r7, #4]
- 8000b68: edc3 7a03 vstr s15, [r3, #12]
-
- //proportional term
- float output = this->error_ * this->kp_;
- 8000b6c: 687b ldr r3, [r7, #4]
- 8000b6e: ed93 7a03 vldr s14, [r3, #12]
- 8000b72: 687b ldr r3, [r7, #4]
- 8000b74: edd3 7a00 vldr s15, [r3]
- 8000b78: ee67 7a27 vmul.f32 s15, s14, s15
- 8000b7c: edc7 7a03 vstr s15, [r7, #12]
-
- //integral term without windup
- error_sum_ += this->error_;
- 8000b80: 687b ldr r3, [r7, #4]
- 8000b82: ed93 7a05 vldr s14, [r3, #20]
- 8000b86: 687b ldr r3, [r7, #4]
- 8000b88: edd3 7a03 vldr s15, [r3, #12]
- 8000b8c: ee77 7a27 vadd.f32 s15, s14, s15
- 8000b90: 687b ldr r3, [r7, #4]
- 8000b92: edc3 7a05 vstr s15, [r3, #20]
- output += error_sum_ * this->ki_;
- 8000b96: 687b ldr r3, [r7, #4]
- 8000b98: ed93 7a05 vldr s14, [r3, #20]
- 8000b9c: 687b ldr r3, [r7, #4]
- 8000b9e: edd3 7a01 vldr s15, [r3, #4]
- 8000ba2: ee67 7a27 vmul.f32 s15, s14, s15
- 8000ba6: ed97 7a03 vldr s14, [r7, #12]
- 8000baa: ee77 7a27 vadd.f32 s15, s14, s15
- 8000bae: edc7 7a03 vstr s15, [r7, #12]
-
- //derivative term
- output += (this->error_ - this->previous_error_) * kd_;
- 8000bb2: 687b ldr r3, [r7, #4]
- 8000bb4: ed93 7a03 vldr s14, [r3, #12]
- 8000bb8: 687b ldr r3, [r7, #4]
- 8000bba: edd3 7a06 vldr s15, [r3, #24]
- 8000bbe: ee37 7a67 vsub.f32 s14, s14, s15
- 8000bc2: 687b ldr r3, [r7, #4]
- 8000bc4: edd3 7a02 vldr s15, [r3, #8]
- 8000bc8: ee67 7a27 vmul.f32 s15, s14, s15
- 8000bcc: ed97 7a03 vldr s14, [r7, #12]
- 8000bd0: ee77 7a27 vadd.f32 s15, s14, s15
- 8000bd4: edc7 7a03 vstr s15, [r7, #12]
- this->previous_error_ = this->error_;
- 8000bd8: 687b ldr r3, [r7, #4]
- 8000bda: 68da ldr r2, [r3, #12]
- 8000bdc: 687b ldr r3, [r7, #4]
- 8000bde: 619a str r2, [r3, #24]
-
- int integer_output = static_cast<int> (output);
- 8000be0: edd7 7a03 vldr s15, [r7, #12]
- 8000be4: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8000be8: ee17 3a90 vmov r3, s15
- 8000bec: 60bb str r3, [r7, #8]
-// if(integer_output > this->max_)
-// integer_output = this->max_;
-// else if (integer_output < this->min_)
-// integer_output = this->min_;
-
- return integer_output;
- 8000bee: 68bb ldr r3, [r7, #8]
-
- }
- 8000bf0: 4618 mov r0, r3
- 8000bf2: 3714 adds r7, #20
- 8000bf4: 46bd mov sp, r7
- 8000bf6: f85d 7b04 ldr.w r7, [sp], #4
- 8000bfa: 4770 bx lr
-
-08000bfc <main>:
-/**
- * @brief The application entry point.
- * @retval int
- */
-int main(void)
-{
- 8000bfc: b580 push {r7, lr}
- 8000bfe: af00 add r7, sp, #0
-
-
- /* MCU Configuration--------------------------------------------------------*/
-
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
- 8000c00: f001 f815 bl 8001c2e <HAL_Init>
- /* USER CODE BEGIN Init */
-
- /* USER CODE END Init */
-
- /* Configure the system clock */
- SystemClock_Config();
- 8000c04: f000 f874 bl 8000cf0 <_Z18SystemClock_Configv>
- /* USER CODE BEGIN SysInit */
-
- /* USER CODE END SysInit */
-
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- 8000c08: f000 fb4a bl 80012a0 <_ZL12MX_GPIO_Initv>
- MX_TIM2_Init();
- 8000c0c: f000 f916 bl 8000e3c <_ZL12MX_TIM2_Initv>
- MX_TIM3_Init();
- 8000c10: f000 f972 bl 8000ef8 <_ZL12MX_TIM3_Initv>
- MX_TIM4_Init();
- 8000c14: f000 f9ce bl 8000fb4 <_ZL12MX_TIM4_Initv>
- MX_TIM5_Init();
- 8000c18: f000 fa6c bl 80010f4 <_ZL12MX_TIM5_Initv>
- MX_USART6_UART_Init();
- 8000c1c: f000 fb0c bl 8001238 <_ZL19MX_USART6_UART_Initv>
- MX_TIM6_Init();
- 8000c20: f000 fac8 bl 80011b4 <_ZL12MX_TIM6_Initv>
-
- /* Initialize interrupts */
- MX_NVIC_Init();
- 8000c24: f000 f8ee bl 8000e04 <_ZL12MX_NVIC_Initv>
- /* USER CODE BEGIN 2 */
-
- left_encoder.Setup();
- 8000c28: 481e ldr r0, [pc, #120] ; (8000ca4 <main+0xa8>)
- 8000c2a: f7ff fcbf bl 80005ac <_ZN7Encoder5SetupEv>
- right_encoder.Setup();
- 8000c2e: 481e ldr r0, [pc, #120] ; (8000ca8 <main+0xac>)
- 8000c30: f7ff fcbc bl 80005ac <_ZN7Encoder5SetupEv>
-
- left_motor.setup();
- 8000c34: 481d ldr r0, [pc, #116] ; (8000cac <main+0xb0>)
- 8000c36: f7ff fdd6 bl 80007e6 <_ZN15MotorController5setupEv>
- right_motor.setup();
- 8000c3a: 481d ldr r0, [pc, #116] ; (8000cb0 <main+0xb4>)
- 8000c3c: f7ff fdd3 bl 80007e6 <_ZN15MotorController5setupEv>
- left_motor.coast();
- 8000c40: 481a ldr r0, [pc, #104] ; (8000cac <main+0xb0>)
- 8000c42: f7ff ff07 bl 8000a54 <_ZN15MotorController5coastEv>
- right_motor.coast();
- 8000c46: 481a ldr r0, [pc, #104] ; (8000cb0 <main+0xb4>)
- 8000c48: f7ff ff04 bl 8000a54 <_ZN15MotorController5coastEv>
-
- left_pid.config(180, 200, 0);
- 8000c4c: ed9f 1a19 vldr s2, [pc, #100] ; 8000cb4 <main+0xb8>
- 8000c50: eddf 0a19 vldr s1, [pc, #100] ; 8000cb8 <main+0xbc>
- 8000c54: ed9f 0a19 vldr s0, [pc, #100] ; 8000cbc <main+0xc0>
- 8000c58: 4819 ldr r0, [pc, #100] ; (8000cc0 <main+0xc4>)
- 8000c5a: f7ff ff3f bl 8000adc <_ZN3Pid6configEfff>
- right_pid.config(185, 195, 0);
- 8000c5e: ed9f 1a15 vldr s2, [pc, #84] ; 8000cb4 <main+0xb8>
- 8000c62: eddf 0a18 vldr s1, [pc, #96] ; 8000cc4 <main+0xc8>
- 8000c66: ed9f 0a18 vldr s0, [pc, #96] ; 8000cc8 <main+0xcc>
- 8000c6a: 4818 ldr r0, [pc, #96] ; (8000ccc <main+0xd0>)
- 8000c6c: f7ff ff36 bl 8000adc <_ZN3Pid6configEfff>
- cross_pid.config(50, 20, 0);
- 8000c70: ed9f 1a10 vldr s2, [pc, #64] ; 8000cb4 <main+0xb8>
- 8000c74: eef3 0a04 vmov.f32 s1, #52 ; 0x41a00000 20.0
- 8000c78: ed9f 0a15 vldr s0, [pc, #84] ; 8000cd0 <main+0xd4>
- 8000c7c: 4815 ldr r0, [pc, #84] ; (8000cd4 <main+0xd8>)
- 8000c7e: f7ff ff2d bl 8000adc <_ZN3Pid6configEfff>
-
- tx_buffer = (uint8_t*) &output_msg;
- 8000c82: 4b15 ldr r3, [pc, #84] ; (8000cd8 <main+0xdc>)
- 8000c84: 4a15 ldr r2, [pc, #84] ; (8000cdc <main+0xe0>)
- 8000c86: 601a str r2, [r3, #0]
- rx_buffer = (uint8_t*) &input_msg;
- 8000c88: 4b15 ldr r3, [pc, #84] ; (8000ce0 <main+0xe4>)
- 8000c8a: 4a16 ldr r2, [pc, #88] ; (8000ce4 <main+0xe8>)
- 8000c8c: 601a str r2, [r3, #0]
-
- //Enables UART RX interrupt
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
- 8000c8e: 4b14 ldr r3, [pc, #80] ; (8000ce0 <main+0xe4>)
- 8000c90: 681b ldr r3, [r3, #0]
- 8000c92: 2208 movs r2, #8
- 8000c94: 4619 mov r1, r3
- 8000c96: 4814 ldr r0, [pc, #80] ; (8000ce8 <main+0xec>)
- 8000c98: f003 fd66 bl 8004768 <HAL_UART_Receive_IT>
- HAL_TIM_Base_Start_IT(&htim6);
- 8000c9c: 4813 ldr r0, [pc, #76] ; (8000cec <main+0xf0>)
- 8000c9e: f002 fbc5 bl 800342c <HAL_TIM_Base_Start_IT>
- /* USER CODE END 2 */
-
- /* Infinite loop */
- /* USER CODE BEGIN WHILE */
- while (1) {
- 8000ca2: e7fe b.n 8000ca2 <main+0xa6>
- 8000ca4: 20000204 .word 0x20000204
- 8000ca8: 200001ec .word 0x200001ec
- 8000cac: 200002c4 .word 0x200002c4
- 8000cb0: 200002ac .word 0x200002ac
- 8000cb4: 00000000 .word 0x00000000
- 8000cb8: 43480000 .word 0x43480000
- 8000cbc: 43340000 .word 0x43340000
- 8000cc0: 2000022c .word 0x2000022c
- 8000cc4: 43430000 .word 0x43430000
- 8000cc8: 43390000 .word 0x43390000
- 8000ccc: 20000250 .word 0x20000250
- 8000cd0: 42480000 .word 0x42480000
- 8000cd4: 20000274 .word 0x20000274
- 8000cd8: 200002dc .word 0x200002dc
- 8000cdc: 200002ec .word 0x200002ec
- 8000ce0: 200002e0 .word 0x200002e0
- 8000ce4: 200002e4 .word 0x200002e4
- 8000ce8: 2000016c .word 0x2000016c
- 8000cec: 2000012c .word 0x2000012c
-
-08000cf0 <_Z18SystemClock_Configv>:
-/**
- * @brief System Clock Configuration
- * @retval Nonewheel_circumference_
- */
-void SystemClock_Config(void)
-{
- 8000cf0: b580 push {r7, lr}
- 8000cf2: b0b8 sub sp, #224 ; 0xe0
- 8000cf4: af00 add r7, sp, #0
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 8000cf6: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000cfa: 2234 movs r2, #52 ; 0x34
- 8000cfc: 2100 movs r1, #0
- 8000cfe: 4618 mov r0, r3
- 8000d00: f004 fbda bl 80054b8 <memset>
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 8000d04: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000d08: 2200 movs r2, #0
- 8000d0a: 601a str r2, [r3, #0]
- 8000d0c: 605a str r2, [r3, #4]
- 8000d0e: 609a str r2, [r3, #8]
- 8000d10: 60da str r2, [r3, #12]
- 8000d12: 611a str r2, [r3, #16]
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
- 8000d14: f107 0308 add.w r3, r7, #8
- 8000d18: 2290 movs r2, #144 ; 0x90
- 8000d1a: 2100 movs r1, #0
- 8000d1c: 4618 mov r0, r3
- 8000d1e: f004 fbcb bl 80054b8 <memset>
-
- /** Configure the main internal regulator output voltage
- */
- __HAL_RCC_PWR_CLK_ENABLE();
- 8000d22: 4b36 ldr r3, [pc, #216] ; (8000dfc <_Z18SystemClock_Configv+0x10c>)
- 8000d24: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000d26: 4a35 ldr r2, [pc, #212] ; (8000dfc <_Z18SystemClock_Configv+0x10c>)
- 8000d28: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8000d2c: 6413 str r3, [r2, #64] ; 0x40
- 8000d2e: 4b33 ldr r3, [pc, #204] ; (8000dfc <_Z18SystemClock_Configv+0x10c>)
- 8000d30: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000d32: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000d36: 607b str r3, [r7, #4]
- 8000d38: 687b ldr r3, [r7, #4]
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 8000d3a: 4b31 ldr r3, [pc, #196] ; (8000e00 <_Z18SystemClock_Configv+0x110>)
- 8000d3c: 681b ldr r3, [r3, #0]
- 8000d3e: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 8000d42: 4a2f ldr r2, [pc, #188] ; (8000e00 <_Z18SystemClock_Configv+0x110>)
- 8000d44: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000d48: 6013 str r3, [r2, #0]
- 8000d4a: 4b2d ldr r3, [pc, #180] ; (8000e00 <_Z18SystemClock_Configv+0x110>)
- 8000d4c: 681b ldr r3, [r3, #0]
- 8000d4e: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8000d52: 603b str r3, [r7, #0]
- 8000d54: 683b ldr r3, [r7, #0]
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8000d56: 2302 movs r3, #2
- 8000d58: f8c7 30ac str.w r3, [r7, #172] ; 0xac
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000d5c: 2301 movs r3, #1
- 8000d5e: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000d62: 2310 movs r3, #16
- 8000d64: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8000d68: 2300 movs r3, #0
- 8000d6a: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 8000d6e: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000d72: 4618 mov r0, r3
- 8000d74: f001 fac8 bl 8002308 <HAL_RCC_OscConfig>
- 8000d78: 4603 mov r3, r0
- 8000d7a: 2b00 cmp r3, #0
- 8000d7c: bf14 ite ne
- 8000d7e: 2301 movne r3, #1
- 8000d80: 2300 moveq r3, #0
- 8000d82: b2db uxtb r3, r3
- 8000d84: 2b00 cmp r3, #0
- 8000d86: d001 beq.n 8000d8c <_Z18SystemClock_Configv+0x9c>
- {
- Error_Handler();
- 8000d88: f000 fca2 bl 80016d0 <Error_Handler>
- }
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 8000d8c: 230f movs r3, #15
- 8000d8e: f8c7 3098 str.w r3, [r7, #152] ; 0x98
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 8000d92: 2300 movs r3, #0
- 8000d94: f8c7 309c str.w r3, [r7, #156] ; 0x9c
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000d98: 2300 movs r3, #0
- 8000d9a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8000d9e: 2300 movs r3, #0
- 8000da0: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8000da4: 2300 movs r3, #0
- 8000da6: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
-
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 8000daa: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000dae: 2100 movs r1, #0
- 8000db0: 4618 mov r0, r3
- 8000db2: f001 fd1b bl 80027ec <HAL_RCC_ClockConfig>
- 8000db6: 4603 mov r3, r0
- 8000db8: 2b00 cmp r3, #0
- 8000dba: bf14 ite ne
- 8000dbc: 2301 movne r3, #1
- 8000dbe: 2300 moveq r3, #0
- 8000dc0: b2db uxtb r3, r3
- 8000dc2: 2b00 cmp r3, #0
- 8000dc4: d001 beq.n 8000dca <_Z18SystemClock_Configv+0xda>
- {
- Error_Handler();
- 8000dc6: f000 fc83 bl 80016d0 <Error_Handler>
- }
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
- 8000dca: f44f 6300 mov.w r3, #2048 ; 0x800
- 8000dce: 60bb str r3, [r7, #8]
- PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
- 8000dd0: 2300 movs r3, #0
- 8000dd2: 663b str r3, [r7, #96] ; 0x60
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
- 8000dd4: f107 0308 add.w r3, r7, #8
- 8000dd8: 4618 mov r0, r3
- 8000dda: f001 fed5 bl 8002b88 <HAL_RCCEx_PeriphCLKConfig>
- 8000dde: 4603 mov r3, r0
- 8000de0: 2b00 cmp r3, #0
- 8000de2: bf14 ite ne
- 8000de4: 2301 movne r3, #1
- 8000de6: 2300 moveq r3, #0
- 8000de8: b2db uxtb r3, r3
- 8000dea: 2b00 cmp r3, #0
- 8000dec: d001 beq.n 8000df2 <_Z18SystemClock_Configv+0x102>
- {
- Error_Handler();
- 8000dee: f000 fc6f bl 80016d0 <Error_Handler>
- }
-}
- 8000df2: bf00 nop
- 8000df4: 37e0 adds r7, #224 ; 0xe0
- 8000df6: 46bd mov sp, r7
- 8000df8: bd80 pop {r7, pc}
- 8000dfa: bf00 nop
- 8000dfc: 40023800 .word 0x40023800
- 8000e00: 40007000 .word 0x40007000
-
-08000e04 <_ZL12MX_NVIC_Initv>:
-/**
- * @brief NVIC Configuration.
- * @retval None
- */
-static void MX_NVIC_Init(void)
-{
- 8000e04: b580 push {r7, lr}
- 8000e06: af00 add r7, sp, #0
- /* TIM3_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1);
- 8000e08: 2201 movs r2, #1
- 8000e0a: 2102 movs r1, #2
- 8000e0c: 201d movs r0, #29
- 8000e0e: f001 f846 bl 8001e9e <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM3_IRQn);
- 8000e12: 201d movs r0, #29
- 8000e14: f001 f85f bl 8001ed6 <HAL_NVIC_EnableIRQ>
- /* TIM6_DAC_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2);
- 8000e18: 2202 movs r2, #2
- 8000e1a: 2102 movs r1, #2
- 8000e1c: 2036 movs r0, #54 ; 0x36
- 8000e1e: f001 f83e bl 8001e9e <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
- 8000e22: 2036 movs r0, #54 ; 0x36
- 8000e24: f001 f857 bl 8001ed6 <HAL_NVIC_EnableIRQ>
- /* USART6_IRQn interrupt configuration */
- HAL_NVIC_SetPriority(USART6_IRQn, 1, 0);
- 8000e28: 2200 movs r2, #0
- 8000e2a: 2101 movs r1, #1
- 8000e2c: 2047 movs r0, #71 ; 0x47
- 8000e2e: f001 f836 bl 8001e9e <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(USART6_IRQn);
- 8000e32: 2047 movs r0, #71 ; 0x47
- 8000e34: f001 f84f bl 8001ed6 <HAL_NVIC_EnableIRQ>
-}
- 8000e38: bf00 nop
- 8000e3a: bd80 pop {r7, pc}
-
-08000e3c <_ZL12MX_TIM2_Initv>:
- * @brief TIM2 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM2_Init(void)
-{
- 8000e3c: b580 push {r7, lr}
- 8000e3e: b08c sub sp, #48 ; 0x30
- 8000e40: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM2_Init 0 */
-
- /* USER CODE END TIM2_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = {0};
- 8000e42: f107 030c add.w r3, r7, #12
- 8000e46: 2224 movs r2, #36 ; 0x24
- 8000e48: 2100 movs r1, #0
- 8000e4a: 4618 mov r0, r3
- 8000e4c: f004 fb34 bl 80054b8 <memset>
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8000e50: 463b mov r3, r7
- 8000e52: 2200 movs r2, #0
- 8000e54: 601a str r2, [r3, #0]
- 8000e56: 605a str r2, [r3, #4]
- 8000e58: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM2_Init 1 */
-
- /* USER CODE END TIM2_Init 1 */
- htim2.Instance = TIM2;
- 8000e5a: 4b26 ldr r3, [pc, #152] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e5c: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
- 8000e60: 601a str r2, [r3, #0]
- htim2.Init.Prescaler = 0;
- 8000e62: 4b24 ldr r3, [pc, #144] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e64: 2200 movs r2, #0
- 8000e66: 605a str r2, [r3, #4]
- htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000e68: 4b22 ldr r3, [pc, #136] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e6a: 2200 movs r2, #0
- 8000e6c: 609a str r2, [r3, #8]
- htim2.Init.Period = 4294967295;
- 8000e6e: 4b21 ldr r3, [pc, #132] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e70: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000e74: 60da str r2, [r3, #12]
- htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000e76: 4b1f ldr r3, [pc, #124] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e78: 2200 movs r2, #0
- 8000e7a: 611a str r2, [r3, #16]
- htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000e7c: 4b1d ldr r3, [pc, #116] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000e7e: 2200 movs r2, #0
- 8000e80: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8000e82: 2303 movs r3, #3
- 8000e84: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8000e86: 2300 movs r3, #0
- 8000e88: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8000e8a: 2301 movs r3, #1
- 8000e8c: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8000e8e: 2300 movs r3, #0
- 8000e90: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 8000e92: 2300 movs r3, #0
- 8000e94: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8000e96: 2300 movs r3, #0
- 8000e98: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8000e9a: 2301 movs r3, #1
- 8000e9c: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8000e9e: 2300 movs r3, #0
- 8000ea0: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 8000ea2: 2300 movs r3, #0
- 8000ea4: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)
- 8000ea6: f107 030c add.w r3, r7, #12
- 8000eaa: 4619 mov r1, r3
- 8000eac: 4811 ldr r0, [pc, #68] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000eae: f002 fb61 bl 8003574 <HAL_TIM_Encoder_Init>
- 8000eb2: 4603 mov r3, r0
- 8000eb4: 2b00 cmp r3, #0
- 8000eb6: bf14 ite ne
- 8000eb8: 2301 movne r3, #1
- 8000eba: 2300 moveq r3, #0
- 8000ebc: b2db uxtb r3, r3
- 8000ebe: 2b00 cmp r3, #0
- 8000ec0: d001 beq.n 8000ec6 <_ZL12MX_TIM2_Initv+0x8a>
- {
- Error_Handler();
- 8000ec2: f000 fc05 bl 80016d0 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000ec6: 2300 movs r3, #0
- 8000ec8: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000eca: 2300 movs r3, #0
- 8000ecc: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
- 8000ece: 463b mov r3, r7
- 8000ed0: 4619 mov r1, r3
- 8000ed2: 4808 ldr r0, [pc, #32] ; (8000ef4 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000ed4: f003 faee bl 80044b4 <HAL_TIMEx_MasterConfigSynchronization>
- 8000ed8: 4603 mov r3, r0
- 8000eda: 2b00 cmp r3, #0
- 8000edc: bf14 ite ne
- 8000ede: 2301 movne r3, #1
- 8000ee0: 2300 moveq r3, #0
- 8000ee2: b2db uxtb r3, r3
- 8000ee4: 2b00 cmp r3, #0
- 8000ee6: d001 beq.n 8000eec <_ZL12MX_TIM2_Initv+0xb0>
- {
- Error_Handler();
- 8000ee8: f000 fbf2 bl 80016d0 <Error_Handler>
- }
- /* USER CODE BEGIN TIM2_Init 2 */
-
- /* USER CODE END TIM2_Init 2 */
-
-}
- 8000eec: bf00 nop
- 8000eee: 3730 adds r7, #48 ; 0x30
- 8000ef0: 46bd mov sp, r7
- 8000ef2: bd80 pop {r7, pc}
- 8000ef4: 2000002c .word 0x2000002c
-
-08000ef8 <_ZL12MX_TIM3_Initv>:
- * @brief TIM3 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM3_Init(void)
-{
- 8000ef8: b580 push {r7, lr}
- 8000efa: b088 sub sp, #32
- 8000efc: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM3_Init 0 */
-
- /* USER CODE END TIM3_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 8000efe: f107 0310 add.w r3, r7, #16
- 8000f02: 2200 movs r2, #0
- 8000f04: 601a str r2, [r3, #0]
- 8000f06: 605a str r2, [r3, #4]
- 8000f08: 609a str r2, [r3, #8]
- 8000f0a: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8000f0c: 1d3b adds r3, r7, #4
- 8000f0e: 2200 movs r2, #0
- 8000f10: 601a str r2, [r3, #0]
- 8000f12: 605a str r2, [r3, #4]
- 8000f14: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM3_Init 1 */
-
- /* USER CODE END TIM3_Init 1 */
- htim3.Instance = TIM3;
- 8000f16: 4b25 ldr r3, [pc, #148] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f18: 4a25 ldr r2, [pc, #148] ; (8000fb0 <_ZL12MX_TIM3_Initv+0xb8>)
- 8000f1a: 601a str r2, [r3, #0]
- htim3.Init.Prescaler = 999;
- 8000f1c: 4b23 ldr r3, [pc, #140] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f1e: f240 32e7 movw r2, #999 ; 0x3e7
- 8000f22: 605a str r2, [r3, #4]
- htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000f24: 4b21 ldr r3, [pc, #132] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f26: 2200 movs r2, #0
- 8000f28: 609a str r2, [r3, #8]
- htim3.Init.Period = 159;
- 8000f2a: 4b20 ldr r3, [pc, #128] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f2c: 229f movs r2, #159 ; 0x9f
- 8000f2e: 60da str r2, [r3, #12]
- htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000f30: 4b1e ldr r3, [pc, #120] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f32: 2200 movs r2, #0
- 8000f34: 611a str r2, [r3, #16]
- htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000f36: 4b1d ldr r3, [pc, #116] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f38: 2200 movs r2, #0
- 8000f3a: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
- 8000f3c: 481b ldr r0, [pc, #108] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f3e: f002 fa49 bl 80033d4 <HAL_TIM_Base_Init>
- 8000f42: 4603 mov r3, r0
- 8000f44: 2b00 cmp r3, #0
- 8000f46: bf14 ite ne
- 8000f48: 2301 movne r3, #1
- 8000f4a: 2300 moveq r3, #0
- 8000f4c: b2db uxtb r3, r3
- 8000f4e: 2b00 cmp r3, #0
- 8000f50: d001 beq.n 8000f56 <_ZL12MX_TIM3_Initv+0x5e>
- {
- Error_Handler();
- 8000f52: f000 fbbd bl 80016d0 <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000f56: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000f5a: 613b str r3, [r7, #16]
- if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
- 8000f5c: f107 0310 add.w r3, r7, #16
- 8000f60: 4619 mov r1, r3
- 8000f62: 4812 ldr r0, [pc, #72] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f64: f002 fe06 bl 8003b74 <HAL_TIM_ConfigClockSource>
- 8000f68: 4603 mov r3, r0
- 8000f6a: 2b00 cmp r3, #0
- 8000f6c: bf14 ite ne
- 8000f6e: 2301 movne r3, #1
- 8000f70: 2300 moveq r3, #0
- 8000f72: b2db uxtb r3, r3
- 8000f74: 2b00 cmp r3, #0
- 8000f76: d001 beq.n 8000f7c <_ZL12MX_TIM3_Initv+0x84>
- {
- Error_Handler();
- 8000f78: f000 fbaa bl 80016d0 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000f7c: 2300 movs r3, #0
- 8000f7e: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000f80: 2300 movs r3, #0
- 8000f82: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
- 8000f84: 1d3b adds r3, r7, #4
- 8000f86: 4619 mov r1, r3
- 8000f88: 4808 ldr r0, [pc, #32] ; (8000fac <_ZL12MX_TIM3_Initv+0xb4>)
- 8000f8a: f003 fa93 bl 80044b4 <HAL_TIMEx_MasterConfigSynchronization>
- 8000f8e: 4603 mov r3, r0
- 8000f90: 2b00 cmp r3, #0
- 8000f92: bf14 ite ne
- 8000f94: 2301 movne r3, #1
- 8000f96: 2300 moveq r3, #0
- 8000f98: b2db uxtb r3, r3
- 8000f9a: 2b00 cmp r3, #0
- 8000f9c: d001 beq.n 8000fa2 <_ZL12MX_TIM3_Initv+0xaa>
- {
- Error_Handler();
- 8000f9e: f000 fb97 bl 80016d0 <Error_Handler>
- }
- /* USER CODE BEGIN TIM3_Init 2 */
-
- /* USER CODE END TIM3_Init 2 */
-
-}
- 8000fa2: bf00 nop
- 8000fa4: 3720 adds r7, #32
- 8000fa6: 46bd mov sp, r7
- 8000fa8: bd80 pop {r7, pc}
- 8000faa: bf00 nop
- 8000fac: 2000006c .word 0x2000006c
- 8000fb0: 40000400 .word 0x40000400
-
-08000fb4 <_ZL12MX_TIM4_Initv>:
- * @brief TIM4 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM4_Init(void)
-{
- 8000fb4: b580 push {r7, lr}
- 8000fb6: b08e sub sp, #56 ; 0x38
- 8000fb8: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM4_Init 0 */
-
- /* USER CODE END TIM4_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 8000fba: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000fbe: 2200 movs r2, #0
- 8000fc0: 601a str r2, [r3, #0]
- 8000fc2: 605a str r2, [r3, #4]
- 8000fc4: 609a str r2, [r3, #8]
- 8000fc6: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8000fc8: f107 031c add.w r3, r7, #28
- 8000fcc: 2200 movs r2, #0
- 8000fce: 601a str r2, [r3, #0]
- 8000fd0: 605a str r2, [r3, #4]
- 8000fd2: 609a str r2, [r3, #8]
- TIM_OC_InitTypeDef sConfigOC = {0};
- 8000fd4: 463b mov r3, r7
- 8000fd6: 2200 movs r2, #0
- 8000fd8: 601a str r2, [r3, #0]
- 8000fda: 605a str r2, [r3, #4]
- 8000fdc: 609a str r2, [r3, #8]
- 8000fde: 60da str r2, [r3, #12]
- 8000fe0: 611a str r2, [r3, #16]
- 8000fe2: 615a str r2, [r3, #20]
- 8000fe4: 619a str r2, [r3, #24]
-
- /* USER CODE BEGIN TIM4_Init 1 */
-
- /* USER CODE END TIM4_Init 1 */
- htim4.Instance = TIM4;
- 8000fe6: 4b41 ldr r3, [pc, #260] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8000fe8: 4a41 ldr r2, [pc, #260] ; (80010f0 <_ZL12MX_TIM4_Initv+0x13c>)
- 8000fea: 601a str r2, [r3, #0]
- htim4.Init.Prescaler = 0;
- 8000fec: 4b3f ldr r3, [pc, #252] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8000fee: 2200 movs r2, #0
- 8000ff0: 605a str r2, [r3, #4]
- htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000ff2: 4b3e ldr r3, [pc, #248] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8000ff4: 2200 movs r2, #0
- 8000ff6: 609a str r2, [r3, #8]
- htim4.Init.Period = 799;
- 8000ff8: 4b3c ldr r3, [pc, #240] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8000ffa: f240 321f movw r2, #799 ; 0x31f
- 8000ffe: 60da str r2, [r3, #12]
- htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8001000: 4b3a ldr r3, [pc, #232] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8001002: 2200 movs r2, #0
- 8001004: 611a str r2, [r3, #16]
- htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001006: 4b39 ldr r3, [pc, #228] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8001008: 2200 movs r2, #0
- 800100a: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
- 800100c: 4837 ldr r0, [pc, #220] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 800100e: f002 f9e1 bl 80033d4 <HAL_TIM_Base_Init>
- 8001012: 4603 mov r3, r0
- 8001014: 2b00 cmp r3, #0
- 8001016: bf14 ite ne
- 8001018: 2301 movne r3, #1
- 800101a: 2300 moveq r3, #0
- 800101c: b2db uxtb r3, r3
- 800101e: 2b00 cmp r3, #0
- 8001020: d001 beq.n 8001026 <_ZL12MX_TIM4_Initv+0x72>
- {
- Error_Handler();
- 8001022: f000 fb55 bl 80016d0 <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8001026: f44f 5380 mov.w r3, #4096 ; 0x1000
- 800102a: 62bb str r3, [r7, #40] ; 0x28
- if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
- 800102c: f107 0328 add.w r3, r7, #40 ; 0x28
- 8001030: 4619 mov r1, r3
- 8001032: 482e ldr r0, [pc, #184] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8001034: f002 fd9e bl 8003b74 <HAL_TIM_ConfigClockSource>
- 8001038: 4603 mov r3, r0
- 800103a: 2b00 cmp r3, #0
- 800103c: bf14 ite ne
- 800103e: 2301 movne r3, #1
- 8001040: 2300 moveq r3, #0
- 8001042: b2db uxtb r3, r3
- 8001044: 2b00 cmp r3, #0
- 8001046: d001 beq.n 800104c <_ZL12MX_TIM4_Initv+0x98>
- {
- Error_Handler();
- 8001048: f000 fb42 bl 80016d0 <Error_Handler>
- }
- if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
- 800104c: 4827 ldr r0, [pc, #156] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 800104e: f002 fa17 bl 8003480 <HAL_TIM_PWM_Init>
- 8001052: 4603 mov r3, r0
- 8001054: 2b00 cmp r3, #0
- 8001056: bf14 ite ne
- 8001058: 2301 movne r3, #1
- 800105a: 2300 moveq r3, #0
- 800105c: b2db uxtb r3, r3
- 800105e: 2b00 cmp r3, #0
- 8001060: d001 beq.n 8001066 <_ZL12MX_TIM4_Initv+0xb2>
- {
- Error_Handler();
- 8001062: f000 fb35 bl 80016d0 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001066: 2300 movs r3, #0
- 8001068: 61fb str r3, [r7, #28]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 800106a: 2300 movs r3, #0
- 800106c: 627b str r3, [r7, #36] ; 0x24
- if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
- 800106e: f107 031c add.w r3, r7, #28
- 8001072: 4619 mov r1, r3
- 8001074: 481d ldr r0, [pc, #116] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 8001076: f003 fa1d bl 80044b4 <HAL_TIMEx_MasterConfigSynchronization>
- 800107a: 4603 mov r3, r0
- 800107c: 2b00 cmp r3, #0
- 800107e: bf14 ite ne
- 8001080: 2301 movne r3, #1
- 8001082: 2300 moveq r3, #0
- 8001084: b2db uxtb r3, r3
- 8001086: 2b00 cmp r3, #0
- 8001088: d001 beq.n 800108e <_ZL12MX_TIM4_Initv+0xda>
- {
- Error_Handler();
- 800108a: f000 fb21 bl 80016d0 <Error_Handler>
- }
- sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 800108e: 2360 movs r3, #96 ; 0x60
- 8001090: 603b str r3, [r7, #0]
- sConfigOC.Pulse = 0;
- 8001092: 2300 movs r3, #0
- 8001094: 607b str r3, [r7, #4]
- sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 8001096: 2300 movs r3, #0
- 8001098: 60bb str r3, [r7, #8]
- sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 800109a: 2300 movs r3, #0
- 800109c: 613b str r3, [r7, #16]
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
- 800109e: 463b mov r3, r7
- 80010a0: 2208 movs r2, #8
- 80010a2: 4619 mov r1, r3
- 80010a4: 4811 ldr r0, [pc, #68] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 80010a6: f002 fc4d bl 8003944 <HAL_TIM_PWM_ConfigChannel>
- 80010aa: 4603 mov r3, r0
- 80010ac: 2b00 cmp r3, #0
- 80010ae: bf14 ite ne
- 80010b0: 2301 movne r3, #1
- 80010b2: 2300 moveq r3, #0
- 80010b4: b2db uxtb r3, r3
- 80010b6: 2b00 cmp r3, #0
- 80010b8: d001 beq.n 80010be <_ZL12MX_TIM4_Initv+0x10a>
- {
- Error_Handler();
- 80010ba: f000 fb09 bl 80016d0 <Error_Handler>
- }
- if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
- 80010be: 463b mov r3, r7
- 80010c0: 220c movs r2, #12
- 80010c2: 4619 mov r1, r3
- 80010c4: 4809 ldr r0, [pc, #36] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 80010c6: f002 fc3d bl 8003944 <HAL_TIM_PWM_ConfigChannel>
- 80010ca: 4603 mov r3, r0
- 80010cc: 2b00 cmp r3, #0
- 80010ce: bf14 ite ne
- 80010d0: 2301 movne r3, #1
- 80010d2: 2300 moveq r3, #0
- 80010d4: b2db uxtb r3, r3
- 80010d6: 2b00 cmp r3, #0
- 80010d8: d001 beq.n 80010de <_ZL12MX_TIM4_Initv+0x12a>
- {
- Error_Handler();
- 80010da: f000 faf9 bl 80016d0 <Error_Handler>
- }
- /* USER CODE BEGIN TIM4_Init 2 */
-
- /* USER CODE END TIM4_Init 2 */
- HAL_TIM_MspPostInit(&htim4);
- 80010de: 4803 ldr r0, [pc, #12] ; (80010ec <_ZL12MX_TIM4_Initv+0x138>)
- 80010e0: f000 fc76 bl 80019d0 <HAL_TIM_MspPostInit>
-
-}
- 80010e4: bf00 nop
- 80010e6: 3738 adds r7, #56 ; 0x38
- 80010e8: 46bd mov sp, r7
- 80010ea: bd80 pop {r7, pc}
- 80010ec: 200000ac .word 0x200000ac
- 80010f0: 40000800 .word 0x40000800
-
-080010f4 <_ZL12MX_TIM5_Initv>:
- * @brief TIM5 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM5_Init(void)
-{
- 80010f4: b580 push {r7, lr}
- 80010f6: b08c sub sp, #48 ; 0x30
- 80010f8: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM5_Init 0 */
-
- /* USER CODE END TIM5_Init 0 */
-
- TIM_Encoder_InitTypeDef sConfig = {0};
- 80010fa: f107 030c add.w r3, r7, #12
- 80010fe: 2224 movs r2, #36 ; 0x24
- 8001100: 2100 movs r1, #0
- 8001102: 4618 mov r0, r3
- 8001104: f004 f9d8 bl 80054b8 <memset>
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8001108: 463b mov r3, r7
- 800110a: 2200 movs r2, #0
- 800110c: 601a str r2, [r3, #0]
- 800110e: 605a str r2, [r3, #4]
- 8001110: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM5_Init 1 */
-
- /* USER CODE END TIM5_Init 1 */
- htim5.Instance = TIM5;
- 8001112: 4b26 ldr r3, [pc, #152] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 8001114: 4a26 ldr r2, [pc, #152] ; (80011b0 <_ZL12MX_TIM5_Initv+0xbc>)
- 8001116: 601a str r2, [r3, #0]
- htim5.Init.Prescaler = 0;
- 8001118: 4b24 ldr r3, [pc, #144] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 800111a: 2200 movs r2, #0
- 800111c: 605a str r2, [r3, #4]
- htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
- 800111e: 4b23 ldr r3, [pc, #140] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 8001120: 2200 movs r2, #0
- 8001122: 609a str r2, [r3, #8]
- htim5.Init.Period = 4294967295;
- 8001124: 4b21 ldr r3, [pc, #132] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 8001126: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 800112a: 60da str r2, [r3, #12]
- htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 800112c: 4b1f ldr r3, [pc, #124] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 800112e: 2200 movs r2, #0
- 8001130: 611a str r2, [r3, #16]
- htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001132: 4b1e ldr r3, [pc, #120] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 8001134: 2200 movs r2, #0
- 8001136: 619a str r2, [r3, #24]
- sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8001138: 2303 movs r3, #3
- 800113a: 60fb str r3, [r7, #12]
- sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 800113c: 2300 movs r3, #0
- 800113e: 613b str r3, [r7, #16]
- sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8001140: 2301 movs r3, #1
- 8001142: 617b str r3, [r7, #20]
- sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8001144: 2300 movs r3, #0
- 8001146: 61bb str r3, [r7, #24]
- sConfig.IC1Filter = 0;
- 8001148: 2300 movs r3, #0
- 800114a: 61fb str r3, [r7, #28]
- sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 800114c: 2300 movs r3, #0
- 800114e: 623b str r3, [r7, #32]
- sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8001150: 2301 movs r3, #1
- 8001152: 627b str r3, [r7, #36] ; 0x24
- sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8001154: 2300 movs r3, #0
- 8001156: 62bb str r3, [r7, #40] ; 0x28
- sConfig.IC2Filter = 0;
- 8001158: 2300 movs r3, #0
- 800115a: 62fb str r3, [r7, #44] ; 0x2c
- if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK)
- 800115c: f107 030c add.w r3, r7, #12
- 8001160: 4619 mov r1, r3
- 8001162: 4812 ldr r0, [pc, #72] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 8001164: f002 fa06 bl 8003574 <HAL_TIM_Encoder_Init>
- 8001168: 4603 mov r3, r0
- 800116a: 2b00 cmp r3, #0
- 800116c: bf14 ite ne
- 800116e: 2301 movne r3, #1
- 8001170: 2300 moveq r3, #0
- 8001172: b2db uxtb r3, r3
- 8001174: 2b00 cmp r3, #0
- 8001176: d001 beq.n 800117c <_ZL12MX_TIM5_Initv+0x88>
- {
- Error_Handler();
- 8001178: f000 faaa bl 80016d0 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 800117c: 2300 movs r3, #0
- 800117e: 603b str r3, [r7, #0]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8001180: 2300 movs r3, #0
- 8001182: 60bb str r3, [r7, #8]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
- 8001184: 463b mov r3, r7
- 8001186: 4619 mov r1, r3
- 8001188: 4808 ldr r0, [pc, #32] ; (80011ac <_ZL12MX_TIM5_Initv+0xb8>)
- 800118a: f003 f993 bl 80044b4 <HAL_TIMEx_MasterConfigSynchronization>
- 800118e: 4603 mov r3, r0
- 8001190: 2b00 cmp r3, #0
- 8001192: bf14 ite ne
- 8001194: 2301 movne r3, #1
- 8001196: 2300 moveq r3, #0
- 8001198: b2db uxtb r3, r3
- 800119a: 2b00 cmp r3, #0
- 800119c: d001 beq.n 80011a2 <_ZL12MX_TIM5_Initv+0xae>
- {
- Error_Handler();
- 800119e: f000 fa97 bl 80016d0 <Error_Handler>
- }
- /* USER CODE BEGIN TIM5_Init 2 */
-
- /* USER CODE END TIM5_Init 2 */
-
-}
- 80011a2: bf00 nop
- 80011a4: 3730 adds r7, #48 ; 0x30
- 80011a6: 46bd mov sp, r7
- 80011a8: bd80 pop {r7, pc}
- 80011aa: bf00 nop
- 80011ac: 200000ec .word 0x200000ec
- 80011b0: 40000c00 .word 0x40000c00
-
-080011b4 <_ZL12MX_TIM6_Initv>:
- * @brief TIM6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM6_Init(void)
-{
- 80011b4: b580 push {r7, lr}
- 80011b6: b084 sub sp, #16
- 80011b8: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM6_Init 0 */
-
- /* USER CODE END TIM6_Init 0 */
-
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 80011ba: 1d3b adds r3, r7, #4
- 80011bc: 2200 movs r2, #0
- 80011be: 601a str r2, [r3, #0]
- 80011c0: 605a str r2, [r3, #4]
- 80011c2: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM6_Init 1 */
-
- /* USER CODE END TIM6_Init 1 */
- htim6.Instance = TIM6;
- 80011c4: 4b1a ldr r3, [pc, #104] ; (8001230 <_ZL12MX_TIM6_Initv+0x7c>)
- 80011c6: 4a1b ldr r2, [pc, #108] ; (8001234 <_ZL12MX_TIM6_Initv+0x80>)
- 80011c8: 601a str r2, [r3, #0]
- htim6.Init.Prescaler = 9999;
- 80011ca: 4b19 ldr r3, [pc, #100] ; (8001230 <_ZL12MX_TIM6_Initv+0x7c>)
- 80011cc: f242 720f movw r2, #9999 ; 0x270f
- 80011d0: 605a str r2, [r3, #4]
- htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
- 80011d2: 4b17 ldr r3, [pc, #92] ; (8001230 <_ZL12MX_TIM6_Initv+0x7c>)
- 80011d4: 2200 movs r2, #0
- 80011d6: 609a str r2, [r3, #8]
- htim6.Init.Period = 799;
- 80011d8: 4b15 ldr r3, [pc, #84] ; (8001230 <_ZL12MX_TIM6_Initv+0x7c>)
- 80011da: f240 321f movw r2, #799 ; 0x31f
- 80011de: 60da str r2, [r3, #12]
- htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 80011e0: 4b13 ldr r3, [pc, #76] ; (8001230 <_ZL12MX_TIM6_Initv+0x7c>)
- 80011e2: 2200 movs r2, #0
- 80011e4: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
- 80011e6: 4812 ldr r0, [pc, #72] ; (8001230 <_ZL12MX_TIM6_Initv+0x7c>)
- 80011e8: f002 f8f4 bl 80033d4 <HAL_TIM_Base_Init>
- 80011ec: 4603 mov r3, r0
- 80011ee: 2b00 cmp r3, #0
- 80011f0: bf14 ite ne
- 80011f2: 2301 movne r3, #1
- 80011f4: 2300 moveq r3, #0
- 80011f6: b2db uxtb r3, r3
- 80011f8: 2b00 cmp r3, #0
- 80011fa: d001 beq.n 8001200 <_ZL12MX_TIM6_Initv+0x4c>
- {
- Error_Handler();
- 80011fc: f000 fa68 bl 80016d0 <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001200: 2300 movs r3, #0
- 8001202: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8001204: 2300 movs r3, #0
- 8001206: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
- 8001208: 1d3b adds r3, r7, #4
- 800120a: 4619 mov r1, r3
- 800120c: 4808 ldr r0, [pc, #32] ; (8001230 <_ZL12MX_TIM6_Initv+0x7c>)
- 800120e: f003 f951 bl 80044b4 <HAL_TIMEx_MasterConfigSynchronization>
- 8001212: 4603 mov r3, r0
- 8001214: 2b00 cmp r3, #0
- 8001216: bf14 ite ne
- 8001218: 2301 movne r3, #1
- 800121a: 2300 moveq r3, #0
- 800121c: b2db uxtb r3, r3
- 800121e: 2b00 cmp r3, #0
- 8001220: d001 beq.n 8001226 <_ZL12MX_TIM6_Initv+0x72>
- {
- Error_Handler();
- 8001222: f000 fa55 bl 80016d0 <Error_Handler>
- }
- /* USER CODE BEGIN TIM6_Init 2 */
-
- /* USER CODE END TIM6_Init 2 */
-
-}
- 8001226: bf00 nop
- 8001228: 3710 adds r7, #16
- 800122a: 46bd mov sp, r7
- 800122c: bd80 pop {r7, pc}
- 800122e: bf00 nop
- 8001230: 2000012c .word 0x2000012c
- 8001234: 40001000 .word 0x40001000
-
-08001238 <_ZL19MX_USART6_UART_Initv>:
- * @brief USART6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_USART6_UART_Init(void)
-{
- 8001238: b580 push {r7, lr}
- 800123a: af00 add r7, sp, #0
- /* USER CODE END USART6_Init 0 */
-
- /* USER CODE BEGIN USART6_Init 1 */
-
- /* USER CODE END USART6_Init 1 */
- huart6.Instance = USART6;
- 800123c: 4b16 ldr r3, [pc, #88] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800123e: 4a17 ldr r2, [pc, #92] ; (800129c <_ZL19MX_USART6_UART_Initv+0x64>)
- 8001240: 601a str r2, [r3, #0]
- huart6.Init.BaudRate = 115200;
- 8001242: 4b15 ldr r3, [pc, #84] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001244: f44f 32e1 mov.w r2, #115200 ; 0x1c200
- 8001248: 605a str r2, [r3, #4]
- huart6.Init.WordLength = UART_WORDLENGTH_8B;
- 800124a: 4b13 ldr r3, [pc, #76] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800124c: 2200 movs r2, #0
- 800124e: 609a str r2, [r3, #8]
- huart6.Init.StopBits = UART_STOPBITS_1;
- 8001250: 4b11 ldr r3, [pc, #68] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001252: 2200 movs r2, #0
- 8001254: 60da str r2, [r3, #12]
- huart6.Init.Parity = UART_PARITY_NONE;
- 8001256: 4b10 ldr r3, [pc, #64] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001258: 2200 movs r2, #0
- 800125a: 611a str r2, [r3, #16]
- huart6.Init.Mode = UART_MODE_TX_RX;
- 800125c: 4b0e ldr r3, [pc, #56] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800125e: 220c movs r2, #12
- 8001260: 615a str r2, [r3, #20]
- huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 8001262: 4b0d ldr r3, [pc, #52] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001264: 2200 movs r2, #0
- 8001266: 619a str r2, [r3, #24]
- huart6.Init.OverSampling = UART_OVERSAMPLING_16;
- 8001268: 4b0b ldr r3, [pc, #44] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800126a: 2200 movs r2, #0
- 800126c: 61da str r2, [r3, #28]
- huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 800126e: 4b0a ldr r3, [pc, #40] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001270: 2200 movs r2, #0
- 8001272: 621a str r2, [r3, #32]
- huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 8001274: 4b08 ldr r3, [pc, #32] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 8001276: 2200 movs r2, #0
- 8001278: 625a str r2, [r3, #36] ; 0x24
- if (HAL_UART_Init(&huart6) != HAL_OK)
- 800127a: 4807 ldr r0, [pc, #28] ; (8001298 <_ZL19MX_USART6_UART_Initv+0x60>)
- 800127c: f003 f994 bl 80045a8 <HAL_UART_Init>
- 8001280: 4603 mov r3, r0
- 8001282: 2b00 cmp r3, #0
- 8001284: bf14 ite ne
- 8001286: 2301 movne r3, #1
- 8001288: 2300 moveq r3, #0
- 800128a: b2db uxtb r3, r3
- 800128c: 2b00 cmp r3, #0
- 800128e: d001 beq.n 8001294 <_ZL19MX_USART6_UART_Initv+0x5c>
- {
- Error_Handler();
- 8001290: f000 fa1e bl 80016d0 <Error_Handler>
- }
- /* USER CODE BEGIN USART6_Init 2 */
-
- /* USER CODE END USART6_Init 2 */
-
-}
- 8001294: bf00 nop
- 8001296: bd80 pop {r7, pc}
- 8001298: 2000016c .word 0x2000016c
- 800129c: 40011400 .word 0x40011400
-
-080012a0 <_ZL12MX_GPIO_Initv>:
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void)
-{
- 80012a0: b580 push {r7, lr}
- 80012a2: b08c sub sp, #48 ; 0x30
- 80012a4: af00 add r7, sp, #0
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80012a6: f107 031c add.w r3, r7, #28
- 80012aa: 2200 movs r2, #0
- 80012ac: 601a str r2, [r3, #0]
- 80012ae: 605a str r2, [r3, #4]
- 80012b0: 609a str r2, [r3, #8]
- 80012b2: 60da str r2, [r3, #12]
- 80012b4: 611a str r2, [r3, #16]
-
- /* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 80012b6: 4b5e ldr r3, [pc, #376] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012b8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80012ba: 4a5d ldr r2, [pc, #372] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012bc: f043 0304 orr.w r3, r3, #4
- 80012c0: 6313 str r3, [r2, #48] ; 0x30
- 80012c2: 4b5b ldr r3, [pc, #364] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012c4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80012c6: f003 0304 and.w r3, r3, #4
- 80012ca: 61bb str r3, [r7, #24]
- 80012cc: 69bb ldr r3, [r7, #24]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 80012ce: 4b58 ldr r3, [pc, #352] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012d0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80012d2: 4a57 ldr r2, [pc, #348] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012d4: f043 0301 orr.w r3, r3, #1
- 80012d8: 6313 str r3, [r2, #48] ; 0x30
- 80012da: 4b55 ldr r3, [pc, #340] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012dc: 6b1b ldr r3, [r3, #48] ; 0x30
- 80012de: f003 0301 and.w r3, r3, #1
- 80012e2: 617b str r3, [r7, #20]
- 80012e4: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOF_CLK_ENABLE();
- 80012e6: 4b52 ldr r3, [pc, #328] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012e8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80012ea: 4a51 ldr r2, [pc, #324] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012ec: f043 0320 orr.w r3, r3, #32
- 80012f0: 6313 str r3, [r2, #48] ; 0x30
- 80012f2: 4b4f ldr r3, [pc, #316] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 80012f4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80012f6: f003 0320 and.w r3, r3, #32
- 80012fa: 613b str r3, [r7, #16]
- 80012fc: 693b ldr r3, [r7, #16]
- __HAL_RCC_GPIOE_CLK_ENABLE();
- 80012fe: 4b4c ldr r3, [pc, #304] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 8001300: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001302: 4a4b ldr r2, [pc, #300] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 8001304: f043 0310 orr.w r3, r3, #16
- 8001308: 6313 str r3, [r2, #48] ; 0x30
- 800130a: 4b49 ldr r3, [pc, #292] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 800130c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800130e: f003 0310 and.w r3, r3, #16
- 8001312: 60fb str r3, [r7, #12]
- 8001314: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 8001316: 4b46 ldr r3, [pc, #280] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 8001318: 6b1b ldr r3, [r3, #48] ; 0x30
- 800131a: 4a45 ldr r2, [pc, #276] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 800131c: f043 0308 orr.w r3, r3, #8
- 8001320: 6313 str r3, [r2, #48] ; 0x30
- 8001322: 4b43 ldr r3, [pc, #268] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 8001324: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001326: f003 0308 and.w r3, r3, #8
- 800132a: 60bb str r3, [r7, #8]
- 800132c: 68bb ldr r3, [r7, #8]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 800132e: 4b40 ldr r3, [pc, #256] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 8001330: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001332: 4a3f ldr r2, [pc, #252] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 8001334: f043 0302 orr.w r3, r3, #2
- 8001338: 6313 str r3, [r2, #48] ; 0x30
- 800133a: 4b3d ldr r3, [pc, #244] ; (8001430 <_ZL12MX_GPIO_Initv+0x190>)
- 800133c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800133e: f003 0302 and.w r3, r3, #2
- 8001342: 607b str r3, [r7, #4]
- 8001344: 687b ldr r3, [r7, #4]
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, dir2_Pin|dir1_Pin, GPIO_PIN_RESET);
- 8001346: 2200 movs r2, #0
- 8001348: f44f 5140 mov.w r1, #12288 ; 0x3000
- 800134c: 4839 ldr r0, [pc, #228] ; (8001434 <_ZL12MX_GPIO_Initv+0x194>)
- 800134e: f000 ffa9 bl 80022a4 <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(GPIOF, sleep2_Pin|sleep1_Pin, GPIO_PIN_SET);
- 8001352: 2201 movs r2, #1
- 8001354: f44f 4140 mov.w r1, #49152 ; 0xc000
- 8001358: 4836 ldr r0, [pc, #216] ; (8001434 <_ZL12MX_GPIO_Initv+0x194>)
- 800135a: f000 ffa3 bl 80022a4 <HAL_GPIO_WritePin>
-
- /*Configure GPIO pin : user_button_Pin */
- GPIO_InitStruct.Pin = user_button_Pin;
- 800135e: f44f 5300 mov.w r3, #8192 ; 0x2000
- 8001362: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
- 8001364: 4b34 ldr r3, [pc, #208] ; (8001438 <_ZL12MX_GPIO_Initv+0x198>)
- 8001366: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001368: 2300 movs r3, #0
- 800136a: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct);
- 800136c: f107 031c add.w r3, r7, #28
- 8001370: 4619 mov r1, r3
- 8001372: 4832 ldr r0, [pc, #200] ; (800143c <_ZL12MX_GPIO_Initv+0x19c>)
- 8001374: f000 fdec bl 8001f50 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current2_Pin */
- GPIO_InitStruct.Pin = current2_Pin;
- 8001378: 2301 movs r3, #1
- 800137a: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 800137c: 2303 movs r3, #3
- 800137e: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001380: 2300 movs r3, #0
- 8001382: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct);
- 8001384: f107 031c add.w r3, r7, #28
- 8001388: 4619 mov r1, r3
- 800138a: 482c ldr r0, [pc, #176] ; (800143c <_ZL12MX_GPIO_Initv+0x19c>)
- 800138c: f000 fde0 bl 8001f50 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current1_Pin */
- GPIO_InitStruct.Pin = current1_Pin;
- 8001390: 2308 movs r3, #8
- 8001392: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 8001394: 2303 movs r3, #3
- 8001396: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001398: 2300 movs r3, #0
- 800139a: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct);
- 800139c: f107 031c add.w r3, r7, #28
- 80013a0: 4619 mov r1, r3
- 80013a2: 4827 ldr r0, [pc, #156] ; (8001440 <_ZL12MX_GPIO_Initv+0x1a0>)
- 80013a4: f000 fdd4 bl 8001f50 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault2_Pin */
- GPIO_InitStruct.Pin = fault2_Pin;
- 80013a8: 2340 movs r3, #64 ; 0x40
- 80013aa: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 80013ac: 2300 movs r3, #0
- 80013ae: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80013b0: 2300 movs r3, #0
- 80013b2: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct);
- 80013b4: f107 031c add.w r3, r7, #28
- 80013b8: 4619 mov r1, r3
- 80013ba: 4821 ldr r0, [pc, #132] ; (8001440 <_ZL12MX_GPIO_Initv+0x1a0>)
- 80013bc: f000 fdc8 bl 8001f50 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : dir2_Pin dir1_Pin */
- GPIO_InitStruct.Pin = dir2_Pin|dir1_Pin;
- 80013c0: f44f 5340 mov.w r3, #12288 ; 0x3000
- 80013c4: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 80013c6: 2301 movs r3, #1
- 80013c8: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80013ca: 2300 movs r3, #0
- 80013cc: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80013ce: 2300 movs r3, #0
- 80013d0: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 80013d2: f107 031c add.w r3, r7, #28
- 80013d6: 4619 mov r1, r3
- 80013d8: 4816 ldr r0, [pc, #88] ; (8001434 <_ZL12MX_GPIO_Initv+0x194>)
- 80013da: f000 fdb9 bl 8001f50 <HAL_GPIO_Init>
-
- /*Configure GPIO pins : sleep2_Pin sleep1_Pin */
- GPIO_InitStruct.Pin = sleep2_Pin|sleep1_Pin;
- 80013de: f44f 4340 mov.w r3, #49152 ; 0xc000
- 80013e2: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 80013e4: 2301 movs r3, #1
- 80013e6: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- 80013e8: 2301 movs r3, #1
- 80013ea: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80013ec: 2300 movs r3, #0
- 80013ee: 62bb str r3, [r7, #40] ; 0x28
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 80013f0: f107 031c add.w r3, r7, #28
- 80013f4: 4619 mov r1, r3
- 80013f6: 480f ldr r0, [pc, #60] ; (8001434 <_ZL12MX_GPIO_Initv+0x194>)
- 80013f8: f000 fdaa bl 8001f50 <HAL_GPIO_Init>
-
- /*Configure GPIO pin : fault1_Pin */
- GPIO_InitStruct.Pin = fault1_Pin;
- 80013fc: f44f 7300 mov.w r3, #512 ; 0x200
- 8001400: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001402: 2300 movs r3, #0
- 8001404: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001406: 2300 movs r3, #0
- 8001408: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct);
- 800140a: f107 031c add.w r3, r7, #28
- 800140e: 4619 mov r1, r3
- 8001410: 480c ldr r0, [pc, #48] ; (8001444 <_ZL12MX_GPIO_Initv+0x1a4>)
- 8001412: f000 fd9d bl 8001f50 <HAL_GPIO_Init>
-
- /* EXTI interrupt init*/
- HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
- 8001416: 2200 movs r2, #0
- 8001418: 2100 movs r1, #0
- 800141a: 2028 movs r0, #40 ; 0x28
- 800141c: f000 fd3f bl 8001e9e <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
- 8001420: 2028 movs r0, #40 ; 0x28
- 8001422: f000 fd58 bl 8001ed6 <HAL_NVIC_EnableIRQ>
-
-}
- 8001426: bf00 nop
- 8001428: 3730 adds r7, #48 ; 0x30
- 800142a: 46bd mov sp, r7
- 800142c: bd80 pop {r7, pc}
- 800142e: bf00 nop
- 8001430: 40023800 .word 0x40023800
- 8001434: 40021400 .word 0x40021400
- 8001438: 10110000 .word 0x10110000
- 800143c: 40020800 .word 0x40020800
- 8001440: 40020000 .word 0x40020000
- 8001444: 40021000 .word 0x40021000
-
-08001448 <HAL_TIM_PeriodElapsedCallback>:
-
-/* USER CODE BEGIN 4 */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
- 8001448: b580 push {r7, lr}
- 800144a: b084 sub sp, #16
- 800144c: af00 add r7, sp, #0
- 800144e: 6078 str r0, [r7, #4]
-
- //TIMER 100Hz PID control
- if (htim->Instance == TIM3) {
- 8001450: 687b ldr r3, [r7, #4]
- 8001452: 681b ldr r3, [r3, #0]
- 8001454: 4a2a ldr r2, [pc, #168] ; (8001500 <HAL_TIM_PeriodElapsedCallback+0xb8>)
- 8001456: 4293 cmp r3, r2
- 8001458: d14d bne.n 80014f6 <HAL_TIM_PeriodElapsedCallback+0xae>
-
- left_velocity = left_encoder.GetLinearVelocity();
- 800145a: 482a ldr r0, [pc, #168] ; (8001504 <HAL_TIM_PeriodElapsedCallback+0xbc>)
- 800145c: f7ff f8f8 bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 8001460: eef0 7a40 vmov.f32 s15, s0
- 8001464: 4b28 ldr r3, [pc, #160] ; (8001508 <HAL_TIM_PeriodElapsedCallback+0xc0>)
- 8001466: edc3 7a00 vstr s15, [r3]
- left_dutycycle = left_pid.update(left_velocity);
- 800146a: 4b27 ldr r3, [pc, #156] ; (8001508 <HAL_TIM_PeriodElapsedCallback+0xc0>)
- 800146c: edd3 7a00 vldr s15, [r3]
- 8001470: eeb0 0a67 vmov.f32 s0, s15
- 8001474: 4825 ldr r0, [pc, #148] ; (800150c <HAL_TIM_PeriodElapsedCallback+0xc4>)
- 8001476: f7ff fb69 bl 8000b4c <_ZN3Pid6updateEf>
- 800147a: 4602 mov r2, r0
- 800147c: 4b24 ldr r3, [pc, #144] ; (8001510 <HAL_TIM_PeriodElapsedCallback+0xc8>)
- 800147e: 601a str r2, [r3, #0]
- left_motor.set_speed(left_dutycycle);
- 8001480: 4b23 ldr r3, [pc, #140] ; (8001510 <HAL_TIM_PeriodElapsedCallback+0xc8>)
- 8001482: 681b ldr r3, [r3, #0]
- 8001484: 4619 mov r1, r3
- 8001486: 4823 ldr r0, [pc, #140] ; (8001514 <HAL_TIM_PeriodElapsedCallback+0xcc>)
- 8001488: f7ff f9be bl 8000808 <_ZN15MotorController9set_speedEi>
-
- right_velocity = right_encoder.GetLinearVelocity();
- 800148c: 4822 ldr r0, [pc, #136] ; (8001518 <HAL_TIM_PeriodElapsedCallback+0xd0>)
- 800148e: f7ff f8df bl 8000650 <_ZN7Encoder17GetLinearVelocityEv>
- 8001492: eef0 7a40 vmov.f32 s15, s0
- 8001496: 4b21 ldr r3, [pc, #132] ; (800151c <HAL_TIM_PeriodElapsedCallback+0xd4>)
- 8001498: edc3 7a00 vstr s15, [r3]
- right_dutycycle = right_pid.update(right_velocity);
- 800149c: 4b1f ldr r3, [pc, #124] ; (800151c <HAL_TIM_PeriodElapsedCallback+0xd4>)
- 800149e: edd3 7a00 vldr s15, [r3]
- 80014a2: eeb0 0a67 vmov.f32 s0, s15
- 80014a6: 481e ldr r0, [pc, #120] ; (8001520 <HAL_TIM_PeriodElapsedCallback+0xd8>)
- 80014a8: f7ff fb50 bl 8000b4c <_ZN3Pid6updateEf>
- 80014ac: 4602 mov r2, r0
- 80014ae: 4b1d ldr r3, [pc, #116] ; (8001524 <HAL_TIM_PeriodElapsedCallback+0xdc>)
- 80014b0: 601a str r2, [r3, #0]
- right_motor.set_speed(right_dutycycle);
- 80014b2: 4b1c ldr r3, [pc, #112] ; (8001524 <HAL_TIM_PeriodElapsedCallback+0xdc>)
- 80014b4: 681b ldr r3, [r3, #0]
- 80014b6: 4619 mov r1, r3
- 80014b8: 481b ldr r0, [pc, #108] ; (8001528 <HAL_TIM_PeriodElapsedCallback+0xe0>)
- 80014ba: f7ff f9a5 bl 8000808 <_ZN15MotorController9set_speedEi>
-
- float difference = left_velocity - right_velocity;
- 80014be: 4b12 ldr r3, [pc, #72] ; (8001508 <HAL_TIM_PeriodElapsedCallback+0xc0>)
- 80014c0: ed93 7a00 vldr s14, [r3]
- 80014c4: 4b15 ldr r3, [pc, #84] ; (800151c <HAL_TIM_PeriodElapsedCallback+0xd4>)
- 80014c6: edd3 7a00 vldr s15, [r3]
- 80014ca: ee77 7a67 vsub.f32 s15, s14, s15
- 80014ce: edc7 7a03 vstr s15, [r7, #12]
-
- int cross_dutycycle = cross_pid.update(difference);
- 80014d2: ed97 0a03 vldr s0, [r7, #12]
- 80014d6: 4815 ldr r0, [pc, #84] ; (800152c <HAL_TIM_PeriodElapsedCallback+0xe4>)
- 80014d8: f7ff fb38 bl 8000b4c <_ZN3Pid6updateEf>
- 80014dc: 60b8 str r0, [r7, #8]
-
- left_dutycycle += cross_dutycycle;
- 80014de: 4b0c ldr r3, [pc, #48] ; (8001510 <HAL_TIM_PeriodElapsedCallback+0xc8>)
- 80014e0: 681a ldr r2, [r3, #0]
- 80014e2: 68bb ldr r3, [r7, #8]
- 80014e4: 4413 add r3, r2
- 80014e6: 4a0a ldr r2, [pc, #40] ; (8001510 <HAL_TIM_PeriodElapsedCallback+0xc8>)
- 80014e8: 6013 str r3, [r2, #0]
- right_dutycycle -= cross_dutycycle;
- 80014ea: 4b0e ldr r3, [pc, #56] ; (8001524 <HAL_TIM_PeriodElapsedCallback+0xdc>)
- 80014ec: 681a ldr r2, [r3, #0]
- 80014ee: 68bb ldr r3, [r7, #8]
- 80014f0: 1ad3 subs r3, r2, r3
- 80014f2: 4a0c ldr r2, [pc, #48] ; (8001524 <HAL_TIM_PeriodElapsedCallback+0xdc>)
- 80014f4: 6013 str r3, [r2, #0]
- //TIMER 2Hz Transmit
- if (htim->Instance == TIM6) {
-// left_ticks = left_encoder.GetMeters();
-// right_ticks = right_encoder.GetMeters();
- }
-}
- 80014f6: bf00 nop
- 80014f8: 3710 adds r7, #16
- 80014fa: 46bd mov sp, r7
- 80014fc: bd80 pop {r7, pc}
- 80014fe: bf00 nop
- 8001500: 40000400 .word 0x40000400
- 8001504: 20000204 .word 0x20000204
- 8001508: 20000224 .word 0x20000224
- 800150c: 2000022c .word 0x2000022c
- 8001510: 200002a4 .word 0x200002a4
- 8001514: 200002c4 .word 0x200002c4
- 8001518: 200001ec .word 0x200001ec
- 800151c: 20000228 .word 0x20000228
- 8001520: 20000250 .word 0x20000250
- 8001524: 200002a8 .word 0x200002a8
- 8001528: 200002ac .word 0x200002ac
- 800152c: 20000274 .word 0x20000274
-
-08001530 <HAL_UART_RxCpltCallback>:
-
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {
- 8001530: b580 push {r7, lr}
- 8001532: b082 sub sp, #8
- 8001534: af00 add r7, sp, #0
- 8001536: 6078 str r0, [r7, #4]
-
- odom.UpdateValues(input_msg.linear_velocity, input_msg.angular_velocity);
- 8001538: 4b25 ldr r3, [pc, #148] ; (80015d0 <HAL_UART_RxCpltCallback+0xa0>)
- 800153a: edd3 7a00 vldr s15, [r3]
- 800153e: 4b24 ldr r3, [pc, #144] ; (80015d0 <HAL_UART_RxCpltCallback+0xa0>)
- 8001540: ed93 7a01 vldr s14, [r3, #4]
- 8001544: eef0 0a47 vmov.f32 s1, s14
- 8001548: eeb0 0a67 vmov.f32 s0, s15
- 800154c: 4821 ldr r0, [pc, #132] ; (80015d4 <HAL_UART_RxCpltCallback+0xa4>)
- 800154e: f7ff f8cb bl 80006e8 <_ZN8Odometry12UpdateValuesEff>
-
- left_setpoint = odom.GetLeftVelocity();
- 8001552: 4820 ldr r0, [pc, #128] ; (80015d4 <HAL_UART_RxCpltCallback+0xa4>)
- 8001554: f7ff f908 bl 8000768 <_ZN8Odometry15GetLeftVelocityEv>
- 8001558: eef0 7a40 vmov.f32 s15, s0
- 800155c: 4b1e ldr r3, [pc, #120] ; (80015d8 <HAL_UART_RxCpltCallback+0xa8>)
- 800155e: edc3 7a00 vstr s15, [r3]
- right_setpoint = odom.GetRightVelocity();
- 8001562: 481c ldr r0, [pc, #112] ; (80015d4 <HAL_UART_RxCpltCallback+0xa4>)
- 8001564: f7ff f90f bl 8000786 <_ZN8Odometry16GetRightVelocityEv>
- 8001568: eef0 7a40 vmov.f32 s15, s0
- 800156c: 4b1b ldr r3, [pc, #108] ; (80015dc <HAL_UART_RxCpltCallback+0xac>)
- 800156e: edc3 7a00 vstr s15, [r3]
-
- left_pid.set(left_setpoint);
- 8001572: 4b19 ldr r3, [pc, #100] ; (80015d8 <HAL_UART_RxCpltCallback+0xa8>)
- 8001574: edd3 7a00 vldr s15, [r3]
- 8001578: eeb0 0a67 vmov.f32 s0, s15
- 800157c: 4818 ldr r0, [pc, #96] ; (80015e0 <HAL_UART_RxCpltCallback+0xb0>)
- 800157e: f7ff fad6 bl 8000b2e <_ZN3Pid3setEf>
- right_pid.set(right_setpoint);
- 8001582: 4b16 ldr r3, [pc, #88] ; (80015dc <HAL_UART_RxCpltCallback+0xac>)
- 8001584: edd3 7a00 vldr s15, [r3]
- 8001588: eeb0 0a67 vmov.f32 s0, s15
- 800158c: 4815 ldr r0, [pc, #84] ; (80015e4 <HAL_UART_RxCpltCallback+0xb4>)
- 800158e: f7ff face bl 8000b2e <_ZN3Pid3setEf>
-
- cross_setpoint = left_setpoint - right_setpoint;
- 8001592: 4b11 ldr r3, [pc, #68] ; (80015d8 <HAL_UART_RxCpltCallback+0xa8>)
- 8001594: ed93 7a00 vldr s14, [r3]
- 8001598: 4b10 ldr r3, [pc, #64] ; (80015dc <HAL_UART_RxCpltCallback+0xac>)
- 800159a: edd3 7a00 vldr s15, [r3]
- 800159e: ee77 7a67 vsub.f32 s15, s14, s15
- 80015a2: 4b11 ldr r3, [pc, #68] ; (80015e8 <HAL_UART_RxCpltCallback+0xb8>)
- 80015a4: edc3 7a00 vstr s15, [r3]
- cross_pid.set(cross_setpoint);
- 80015a8: 4b0f ldr r3, [pc, #60] ; (80015e8 <HAL_UART_RxCpltCallback+0xb8>)
- 80015aa: edd3 7a00 vldr s15, [r3]
- 80015ae: eeb0 0a67 vmov.f32 s0, s15
- 80015b2: 480e ldr r0, [pc, #56] ; (80015ec <HAL_UART_RxCpltCallback+0xbc>)
- 80015b4: f7ff fabb bl 8000b2e <_ZN3Pid3setEf>
-
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
- 80015b8: 4b0d ldr r3, [pc, #52] ; (80015f0 <HAL_UART_RxCpltCallback+0xc0>)
- 80015ba: 681b ldr r3, [r3, #0]
- 80015bc: 2208 movs r2, #8
- 80015be: 4619 mov r1, r3
- 80015c0: 480c ldr r0, [pc, #48] ; (80015f4 <HAL_UART_RxCpltCallback+0xc4>)
- 80015c2: f003 f8d1 bl 8004768 <HAL_UART_Receive_IT>
-
-}
- 80015c6: bf00 nop
- 80015c8: 3708 adds r7, #8
- 80015ca: 46bd mov sp, r7
- 80015cc: bd80 pop {r7, pc}
- 80015ce: bf00 nop
- 80015d0: 200002e4 .word 0x200002e4
- 80015d4: 2000021c .word 0x2000021c
- 80015d8: 20000298 .word 0x20000298
- 80015dc: 2000029c .word 0x2000029c
- 80015e0: 2000022c .word 0x2000022c
- 80015e4: 20000250 .word 0x20000250
- 80015e8: 200002a0 .word 0x200002a0
- 80015ec: 20000274 .word 0x20000274
- 80015f0: 200002e0 .word 0x200002e0
- 80015f4: 2000016c .word 0x2000016c
-
-080015f8 <HAL_GPIO_EXTI_Callback>:
-
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
- 80015f8: b580 push {r7, lr}
- 80015fa: b082 sub sp, #8
- 80015fc: af00 add r7, sp, #0
- 80015fe: 4603 mov r3, r0
- 8001600: 80fb strh r3, [r7, #6]
- //Blue user button
- if (GPIO_Pin == GPIO_PIN_13) {
- 8001602: 88fb ldrh r3, [r7, #6]
- 8001604: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8001608: d149 bne.n 800169e <HAL_GPIO_EXTI_Callback+0xa6>
- previous_millis = current_millis;
- 800160a: 4b27 ldr r3, [pc, #156] ; (80016a8 <HAL_GPIO_EXTI_Callback+0xb0>)
- 800160c: 681b ldr r3, [r3, #0]
- 800160e: 4a27 ldr r2, [pc, #156] ; (80016ac <HAL_GPIO_EXTI_Callback+0xb4>)
- 8001610: 6013 str r3, [r2, #0]
- current_millis = HAL_GetTick();
- 8001612: f000 fb5d bl 8001cd0 <HAL_GetTick>
- 8001616: 4603 mov r3, r0
- 8001618: 461a mov r2, r3
- 800161a: 4b23 ldr r3, [pc, #140] ; (80016a8 <HAL_GPIO_EXTI_Callback+0xb0>)
- 800161c: 601a str r2, [r3, #0]
- if (current_millis - previous_millis < 500)
- 800161e: 4b22 ldr r3, [pc, #136] ; (80016a8 <HAL_GPIO_EXTI_Callback+0xb0>)
- 8001620: 681a ldr r2, [r3, #0]
- 8001622: 4b22 ldr r3, [pc, #136] ; (80016ac <HAL_GPIO_EXTI_Callback+0xb4>)
- 8001624: 681b ldr r3, [r3, #0]
- 8001626: 1ad3 subs r3, r2, r3
- 8001628: f5b3 7ffa cmp.w r3, #500 ; 0x1f4
- 800162c: da03 bge.n 8001636 <HAL_GPIO_EXTI_Callback+0x3e>
- debounce = false;
- 800162e: 4b20 ldr r3, [pc, #128] ; (80016b0 <HAL_GPIO_EXTI_Callback+0xb8>)
- 8001630: 2200 movs r2, #0
- 8001632: 701a strb r2, [r3, #0]
- 8001634: e002 b.n 800163c <HAL_GPIO_EXTI_Callback+0x44>
- else
- debounce = true;
- 8001636: 4b1e ldr r3, [pc, #120] ; (80016b0 <HAL_GPIO_EXTI_Callback+0xb8>)
- 8001638: 2201 movs r2, #1
- 800163a: 701a strb r2, [r3, #0]
- if (mode == 0 && debounce) {
- 800163c: 4b1d ldr r3, [pc, #116] ; (80016b4 <HAL_GPIO_EXTI_Callback+0xbc>)
- 800163e: edd3 7a00 vldr s15, [r3]
- 8001642: eef5 7a40 vcmp.f32 s15, #0.0
- 8001646: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800164a: d10b bne.n 8001664 <HAL_GPIO_EXTI_Callback+0x6c>
- 800164c: 4b18 ldr r3, [pc, #96] ; (80016b0 <HAL_GPIO_EXTI_Callback+0xb8>)
- 800164e: 781b ldrb r3, [r3, #0]
- 8001650: 2b00 cmp r3, #0
- 8001652: d007 beq.n 8001664 <HAL_GPIO_EXTI_Callback+0x6c>
- mode = 1;
- 8001654: 4b17 ldr r3, [pc, #92] ; (80016b4 <HAL_GPIO_EXTI_Callback+0xbc>)
- 8001656: f04f 527e mov.w r2, #1065353216 ; 0x3f800000
- 800165a: 601a str r2, [r3, #0]
- //Enables TIM3 interrupt (used for PID control)
- HAL_TIM_Base_Start_IT(&htim3);
- 800165c: 4816 ldr r0, [pc, #88] ; (80016b8 <HAL_GPIO_EXTI_Callback+0xc0>)
- 800165e: f001 fee5 bl 800342c <HAL_TIM_Base_Start_IT>
- HAL_UART_Transmit(&huart6, tx_buffer, 8, 100);
- output_msg.left_ticks = 0;
- output_msg.right_ticks = 0;
- }
- }
-}
- 8001662: e01c b.n 800169e <HAL_GPIO_EXTI_Callback+0xa6>
- } else if (debounce){
- 8001664: 4b12 ldr r3, [pc, #72] ; (80016b0 <HAL_GPIO_EXTI_Callback+0xb8>)
- 8001666: 781b ldrb r3, [r3, #0]
- 8001668: 2b00 cmp r3, #0
- 800166a: d018 beq.n 800169e <HAL_GPIO_EXTI_Callback+0xa6>
- mode = 2;
- 800166c: 4b11 ldr r3, [pc, #68] ; (80016b4 <HAL_GPIO_EXTI_Callback+0xbc>)
- 800166e: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
- 8001672: 601a str r2, [r3, #0]
- output_msg.left_ticks = left_ticks;
- 8001674: 4b11 ldr r3, [pc, #68] ; (80016bc <HAL_GPIO_EXTI_Callback+0xc4>)
- 8001676: 681b ldr r3, [r3, #0]
- 8001678: 4a11 ldr r2, [pc, #68] ; (80016c0 <HAL_GPIO_EXTI_Callback+0xc8>)
- 800167a: 6013 str r3, [r2, #0]
- output_msg.right_ticks = right_ticks;
- 800167c: 4b11 ldr r3, [pc, #68] ; (80016c4 <HAL_GPIO_EXTI_Callback+0xcc>)
- 800167e: 681b ldr r3, [r3, #0]
- 8001680: 4a0f ldr r2, [pc, #60] ; (80016c0 <HAL_GPIO_EXTI_Callback+0xc8>)
- 8001682: 6053 str r3, [r2, #4]
- HAL_UART_Transmit(&huart6, tx_buffer, 8, 100);
- 8001684: 4b10 ldr r3, [pc, #64] ; (80016c8 <HAL_GPIO_EXTI_Callback+0xd0>)
- 8001686: 6819 ldr r1, [r3, #0]
- 8001688: 2364 movs r3, #100 ; 0x64
- 800168a: 2208 movs r2, #8
- 800168c: 480f ldr r0, [pc, #60] ; (80016cc <HAL_GPIO_EXTI_Callback+0xd4>)
- 800168e: f002 ffd9 bl 8004644 <HAL_UART_Transmit>
- output_msg.left_ticks = 0;
- 8001692: 4b0b ldr r3, [pc, #44] ; (80016c0 <HAL_GPIO_EXTI_Callback+0xc8>)
- 8001694: 2200 movs r2, #0
- 8001696: 601a str r2, [r3, #0]
- output_msg.right_ticks = 0;
- 8001698: 4b09 ldr r3, [pc, #36] ; (80016c0 <HAL_GPIO_EXTI_Callback+0xc8>)
- 800169a: 2200 movs r2, #0
- 800169c: 605a str r2, [r3, #4]
-}
- 800169e: bf00 nop
- 80016a0: 3708 adds r7, #8
- 80016a2: 46bd mov sp, r7
- 80016a4: bd80 pop {r7, pc}
- 80016a6: bf00 nop
- 80016a8: 200002f8 .word 0x200002f8
- 80016ac: 200002f4 .word 0x200002f4
- 80016b0: 20000000 .word 0x20000000
- 80016b4: 200002fc .word 0x200002fc
- 80016b8: 2000006c .word 0x2000006c
- 80016bc: 20000300 .word 0x20000300
- 80016c0: 200002ec .word 0x200002ec
- 80016c4: 20000304 .word 0x20000304
- 80016c8: 200002dc .word 0x200002dc
- 80016cc: 2000016c .word 0x2000016c
-
-080016d0 <Error_Handler>:
-/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void)
-{
- 80016d0: b480 push {r7}
- 80016d2: af00 add r7, sp, #0
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
-
- /* USER CODE END Error_Handler_Debug */
-}
- 80016d4: bf00 nop
- 80016d6: 46bd mov sp, r7
- 80016d8: f85d 7b04 ldr.w r7, [sp], #4
- 80016dc: 4770 bx lr
- ...
-
-080016e0 <_Z41__static_initialization_and_destruction_0ii>:
- 80016e0: b580 push {r7, lr}
- 80016e2: b086 sub sp, #24
- 80016e4: af04 add r7, sp, #16
- 80016e6: 6078 str r0, [r7, #4]
- 80016e8: 6039 str r1, [r7, #0]
- 80016ea: 687b ldr r3, [r7, #4]
- 80016ec: 2b01 cmp r3, #1
- 80016ee: d148 bne.n 8001782 <_Z41__static_initialization_and_destruction_0ii+0xa2>
- 80016f0: 683b ldr r3, [r7, #0]
- 80016f2: f64f 72ff movw r2, #65535 ; 0xffff
- 80016f6: 4293 cmp r3, r2
- 80016f8: d143 bne.n 8001782 <_Z41__static_initialization_and_destruction_0ii+0xa2>
-Encoder right_encoder = Encoder(&htim5, RIGHT_TICKS_PER_METER);
- 80016fa: 4a24 ldr r2, [pc, #144] ; (800178c <_Z41__static_initialization_and_destruction_0ii+0xac>)
- 80016fc: 4924 ldr r1, [pc, #144] ; (8001790 <_Z41__static_initialization_and_destruction_0ii+0xb0>)
- 80016fe: 4825 ldr r0, [pc, #148] ; (8001794 <_Z41__static_initialization_and_destruction_0ii+0xb4>)
- 8001700: f7fe ff41 bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>
-Encoder left_encoder = Encoder(&htim2, LEFT_TICKS_PER_METER);
- 8001704: 4a24 ldr r2, [pc, #144] ; (8001798 <_Z41__static_initialization_and_destruction_0ii+0xb8>)
- 8001706: 4925 ldr r1, [pc, #148] ; (800179c <_Z41__static_initialization_and_destruction_0ii+0xbc>)
- 8001708: 4825 ldr r0, [pc, #148] ; (80017a0 <_Z41__static_initialization_and_destruction_0ii+0xc0>)
- 800170a: f7fe ff3c bl 8000586 <_ZN7EncoderC1EP17TIM_HandleTypeDefi>
-Odometry odom = Odometry();
- 800170e: 4825 ldr r0, [pc, #148] ; (80017a4 <_Z41__static_initialization_and_destruction_0ii+0xc4>)
- 8001710: f7fe ffd6 bl 80006c0 <_ZN8OdometryC1Ev>
-Pid left_pid(0, 0, 0);
- 8001714: ed9f 1a24 vldr s2, [pc, #144] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 8001718: eddf 0a23 vldr s1, [pc, #140] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 800171c: ed9f 0a22 vldr s0, [pc, #136] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 8001720: 4822 ldr r0, [pc, #136] ; (80017ac <_Z41__static_initialization_and_destruction_0ii+0xcc>)
- 8001722: f7ff f9a7 bl 8000a74 <_ZN3PidC1Efff>
-Pid right_pid(0, 0, 0);
- 8001726: ed9f 1a20 vldr s2, [pc, #128] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 800172a: eddf 0a1f vldr s1, [pc, #124] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 800172e: ed9f 0a1e vldr s0, [pc, #120] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 8001732: 481f ldr r0, [pc, #124] ; (80017b0 <_Z41__static_initialization_and_destruction_0ii+0xd0>)
- 8001734: f7ff f99e bl 8000a74 <_ZN3PidC1Efff>
-Pid cross_pid(0, 0, 0);
- 8001738: ed9f 1a1b vldr s2, [pc, #108] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 800173c: eddf 0a1a vldr s1, [pc, #104] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 8001740: ed9f 0a19 vldr s0, [pc, #100] ; 80017a8 <_Z41__static_initialization_and_destruction_0ii+0xc8>
- 8001744: 481b ldr r0, [pc, #108] ; (80017b4 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 8001746: f7ff f995 bl 8000a74 <_ZN3PidC1Efff>
- TIM_CHANNEL_4);
- 800174a: 230c movs r3, #12
- 800174c: 9302 str r3, [sp, #8]
- 800174e: 4b1a ldr r3, [pc, #104] ; (80017b8 <_Z41__static_initialization_and_destruction_0ii+0xd8>)
- 8001750: 9301 str r3, [sp, #4]
- 8001752: f44f 5300 mov.w r3, #8192 ; 0x2000
- 8001756: 9300 str r3, [sp, #0]
- 8001758: 4b18 ldr r3, [pc, #96] ; (80017bc <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 800175a: f44f 4200 mov.w r2, #32768 ; 0x8000
- 800175e: 4917 ldr r1, [pc, #92] ; (80017bc <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 8001760: 4817 ldr r0, [pc, #92] ; (80017c0 <_Z41__static_initialization_and_destruction_0ii+0xe0>)
- 8001762: f7ff f81f bl 80007a4 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
- TIM_CHANNEL_3);
- 8001766: 2308 movs r3, #8
- 8001768: 9302 str r3, [sp, #8]
- 800176a: 4b13 ldr r3, [pc, #76] ; (80017b8 <_Z41__static_initialization_and_destruction_0ii+0xd8>)
- 800176c: 9301 str r3, [sp, #4]
- 800176e: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8001772: 9300 str r3, [sp, #0]
- 8001774: 4b11 ldr r3, [pc, #68] ; (80017bc <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 8001776: f44f 4280 mov.w r2, #16384 ; 0x4000
- 800177a: 4910 ldr r1, [pc, #64] ; (80017bc <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 800177c: 4811 ldr r0, [pc, #68] ; (80017c4 <_Z41__static_initialization_and_destruction_0ii+0xe4>)
- 800177e: f7ff f811 bl 80007a4 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
-}
- 8001782: bf00 nop
- 8001784: 3708 adds r7, #8
- 8001786: 46bd mov sp, r7
- 8001788: bd80 pop {r7, pc}
- 800178a: bf00 nop
- 800178c: 000300dd .word 0x000300dd
- 8001790: 200000ec .word 0x200000ec
- 8001794: 200001ec .word 0x200001ec
- 8001798: 0002fccc .word 0x0002fccc
- 800179c: 2000002c .word 0x2000002c
- 80017a0: 20000204 .word 0x20000204
- 80017a4: 2000021c .word 0x2000021c
- 80017a8: 00000000 .word 0x00000000
- 80017ac: 2000022c .word 0x2000022c
- 80017b0: 20000250 .word 0x20000250
- 80017b4: 20000274 .word 0x20000274
- 80017b8: 200000ac .word 0x200000ac
- 80017bc: 40021400 .word 0x40021400
- 80017c0: 200002ac .word 0x200002ac
- 80017c4: 200002c4 .word 0x200002c4
-
-080017c8 <_GLOBAL__sub_I_htim2>:
- 80017c8: b580 push {r7, lr}
- 80017ca: af00 add r7, sp, #0
- 80017cc: f64f 71ff movw r1, #65535 ; 0xffff
- 80017d0: 2001 movs r0, #1
- 80017d2: f7ff ff85 bl 80016e0 <_Z41__static_initialization_and_destruction_0ii>
- 80017d6: bd80 pop {r7, pc}
-
-080017d8 <HAL_MspInit>:
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
- /**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- 80017d8: b480 push {r7}
- 80017da: b083 sub sp, #12
- 80017dc: af00 add r7, sp, #0
- /* USER CODE BEGIN MspInit 0 */
-
- /* USER CODE END MspInit 0 */
-
- __HAL_RCC_PWR_CLK_ENABLE();
- 80017de: 4b0f ldr r3, [pc, #60] ; (800181c <HAL_MspInit+0x44>)
- 80017e0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80017e2: 4a0e ldr r2, [pc, #56] ; (800181c <HAL_MspInit+0x44>)
- 80017e4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80017e8: 6413 str r3, [r2, #64] ; 0x40
- 80017ea: 4b0c ldr r3, [pc, #48] ; (800181c <HAL_MspInit+0x44>)
- 80017ec: 6c1b ldr r3, [r3, #64] ; 0x40
- 80017ee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80017f2: 607b str r3, [r7, #4]
- 80017f4: 687b ldr r3, [r7, #4]
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80017f6: 4b09 ldr r3, [pc, #36] ; (800181c <HAL_MspInit+0x44>)
- 80017f8: 6c5b ldr r3, [r3, #68] ; 0x44
- 80017fa: 4a08 ldr r2, [pc, #32] ; (800181c <HAL_MspInit+0x44>)
- 80017fc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8001800: 6453 str r3, [r2, #68] ; 0x44
- 8001802: 4b06 ldr r3, [pc, #24] ; (800181c <HAL_MspInit+0x44>)
- 8001804: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001806: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 800180a: 603b str r3, [r7, #0]
- 800180c: 683b ldr r3, [r7, #0]
- /* System interrupt init*/
-
- /* USER CODE BEGIN MspInit 1 */
-
- /* USER CODE END MspInit 1 */
-}
- 800180e: bf00 nop
- 8001810: 370c adds r7, #12
- 8001812: 46bd mov sp, r7
- 8001814: f85d 7b04 ldr.w r7, [sp], #4
- 8001818: 4770 bx lr
- 800181a: bf00 nop
- 800181c: 40023800 .word 0x40023800
-
-08001820 <HAL_TIM_Encoder_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_encoder: TIM_Encoder handle pointer
-* @retval None
-*/
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
-{
- 8001820: b580 push {r7, lr}
- 8001822: b08c sub sp, #48 ; 0x30
- 8001824: af00 add r7, sp, #0
- 8001826: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001828: f107 031c add.w r3, r7, #28
- 800182c: 2200 movs r2, #0
- 800182e: 601a str r2, [r3, #0]
- 8001830: 605a str r2, [r3, #4]
- 8001832: 609a str r2, [r3, #8]
- 8001834: 60da str r2, [r3, #12]
- 8001836: 611a str r2, [r3, #16]
- if(htim_encoder->Instance==TIM2)
- 8001838: 687b ldr r3, [r7, #4]
- 800183a: 681b ldr r3, [r3, #0]
- 800183c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8001840: d144 bne.n 80018cc <HAL_TIM_Encoder_MspInit+0xac>
- {
- /* USER CODE BEGIN TIM2_MspInit 0 */
-
- /* USER CODE END TIM2_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM2_CLK_ENABLE();
- 8001842: 4b3b ldr r3, [pc, #236] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001844: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001846: 4a3a ldr r2, [pc, #232] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001848: f043 0301 orr.w r3, r3, #1
- 800184c: 6413 str r3, [r2, #64] ; 0x40
- 800184e: 4b38 ldr r3, [pc, #224] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001850: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001852: f003 0301 and.w r3, r3, #1
- 8001856: 61bb str r3, [r7, #24]
- 8001858: 69bb ldr r3, [r7, #24]
-
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 800185a: 4b35 ldr r3, [pc, #212] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 800185c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800185e: 4a34 ldr r2, [pc, #208] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001860: f043 0301 orr.w r3, r3, #1
- 8001864: 6313 str r3, [r2, #48] ; 0x30
- 8001866: 4b32 ldr r3, [pc, #200] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001868: 6b1b ldr r3, [r3, #48] ; 0x30
- 800186a: f003 0301 and.w r3, r3, #1
- 800186e: 617b str r3, [r7, #20]
- 8001870: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 8001872: 4b2f ldr r3, [pc, #188] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001874: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001876: 4a2e ldr r2, [pc, #184] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001878: f043 0302 orr.w r3, r3, #2
- 800187c: 6313 str r3, [r2, #48] ; 0x30
- 800187e: 4b2c ldr r3, [pc, #176] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 8001880: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001882: f003 0302 and.w r3, r3, #2
- 8001886: 613b str r3, [r7, #16]
- 8001888: 693b ldr r3, [r7, #16]
- /**TIM2 GPIO Configuration
- PA5 ------> TIM2_CH1
- PB3 ------> TIM2_CH2
- */
- GPIO_InitStruct.Pin = encoder_sx1_Pin;
- 800188a: 2320 movs r3, #32
- 800188c: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800188e: 2302 movs r3, #2
- 8001890: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001892: 2300 movs r3, #0
- 8001894: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001896: 2300 movs r3, #0
- 8001898: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 800189a: 2301 movs r3, #1
- 800189c: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx1_GPIO_Port, &GPIO_InitStruct);
- 800189e: f107 031c add.w r3, r7, #28
- 80018a2: 4619 mov r1, r3
- 80018a4: 4823 ldr r0, [pc, #140] ; (8001934 <HAL_TIM_Encoder_MspInit+0x114>)
- 80018a6: f000 fb53 bl 8001f50 <HAL_GPIO_Init>
-
- GPIO_InitStruct.Pin = encoder_sx2_Pin;
- 80018aa: 2308 movs r3, #8
- 80018ac: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80018ae: 2302 movs r3, #2
- 80018b0: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80018b2: 2300 movs r3, #0
- 80018b4: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80018b6: 2300 movs r3, #0
- 80018b8: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 80018ba: 2301 movs r3, #1
- 80018bc: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(encoder_sx2_GPIO_Port, &GPIO_InitStruct);
- 80018be: f107 031c add.w r3, r7, #28
- 80018c2: 4619 mov r1, r3
- 80018c4: 481c ldr r0, [pc, #112] ; (8001938 <HAL_TIM_Encoder_MspInit+0x118>)
- 80018c6: f000 fb43 bl 8001f50 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM5_MspInit 1 */
-
- /* USER CODE END TIM5_MspInit 1 */
- }
-
-}
- 80018ca: e02c b.n 8001926 <HAL_TIM_Encoder_MspInit+0x106>
- else if(htim_encoder->Instance==TIM5)
- 80018cc: 687b ldr r3, [r7, #4]
- 80018ce: 681b ldr r3, [r3, #0]
- 80018d0: 4a1a ldr r2, [pc, #104] ; (800193c <HAL_TIM_Encoder_MspInit+0x11c>)
- 80018d2: 4293 cmp r3, r2
- 80018d4: d127 bne.n 8001926 <HAL_TIM_Encoder_MspInit+0x106>
- __HAL_RCC_TIM5_CLK_ENABLE();
- 80018d6: 4b16 ldr r3, [pc, #88] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 80018d8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80018da: 4a15 ldr r2, [pc, #84] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 80018dc: f043 0308 orr.w r3, r3, #8
- 80018e0: 6413 str r3, [r2, #64] ; 0x40
- 80018e2: 4b13 ldr r3, [pc, #76] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 80018e4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80018e6: f003 0308 and.w r3, r3, #8
- 80018ea: 60fb str r3, [r7, #12]
- 80018ec: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 80018ee: 4b10 ldr r3, [pc, #64] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 80018f0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80018f2: 4a0f ldr r2, [pc, #60] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 80018f4: f043 0301 orr.w r3, r3, #1
- 80018f8: 6313 str r3, [r2, #48] ; 0x30
- 80018fa: 4b0d ldr r3, [pc, #52] ; (8001930 <HAL_TIM_Encoder_MspInit+0x110>)
- 80018fc: 6b1b ldr r3, [r3, #48] ; 0x30
- 80018fe: f003 0301 and.w r3, r3, #1
- 8001902: 60bb str r3, [r7, #8]
- 8001904: 68bb ldr r3, [r7, #8]
- GPIO_InitStruct.Pin = encoder_dx1_Pin|encoder_dx2_Pin;
- 8001906: 2303 movs r3, #3
- 8001908: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800190a: 2302 movs r3, #2
- 800190c: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800190e: 2300 movs r3, #0
- 8001910: 627b str r3, [r7, #36] ; 0x24
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001912: 2300 movs r3, #0
- 8001914: 62bb str r3, [r7, #40] ; 0x28
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
- 8001916: 2302 movs r3, #2
- 8001918: 62fb str r3, [r7, #44] ; 0x2c
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 800191a: f107 031c add.w r3, r7, #28
- 800191e: 4619 mov r1, r3
- 8001920: 4804 ldr r0, [pc, #16] ; (8001934 <HAL_TIM_Encoder_MspInit+0x114>)
- 8001922: f000 fb15 bl 8001f50 <HAL_GPIO_Init>
-}
- 8001926: bf00 nop
- 8001928: 3730 adds r7, #48 ; 0x30
- 800192a: 46bd mov sp, r7
- 800192c: bd80 pop {r7, pc}
- 800192e: bf00 nop
- 8001930: 40023800 .word 0x40023800
- 8001934: 40020000 .word 0x40020000
- 8001938: 40020400 .word 0x40020400
- 800193c: 40000c00 .word 0x40000c00
-
-08001940 <HAL_TIM_Base_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
- 8001940: b480 push {r7}
- 8001942: b087 sub sp, #28
- 8001944: af00 add r7, sp, #0
- 8001946: 6078 str r0, [r7, #4]
- if(htim_base->Instance==TIM3)
- 8001948: 687b ldr r3, [r7, #4]
- 800194a: 681b ldr r3, [r3, #0]
- 800194c: 4a1c ldr r2, [pc, #112] ; (80019c0 <HAL_TIM_Base_MspInit+0x80>)
- 800194e: 4293 cmp r3, r2
- 8001950: d10c bne.n 800196c <HAL_TIM_Base_MspInit+0x2c>
- {
- /* USER CODE BEGIN TIM3_MspInit 0 */
-
- /* USER CODE END TIM3_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM3_CLK_ENABLE();
- 8001952: 4b1c ldr r3, [pc, #112] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 8001954: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001956: 4a1b ldr r2, [pc, #108] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 8001958: f043 0302 orr.w r3, r3, #2
- 800195c: 6413 str r3, [r2, #64] ; 0x40
- 800195e: 4b19 ldr r3, [pc, #100] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 8001960: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001962: f003 0302 and.w r3, r3, #2
- 8001966: 617b str r3, [r7, #20]
- 8001968: 697b ldr r3, [r7, #20]
- /* USER CODE BEGIN TIM6_MspInit 1 */
-
- /* USER CODE END TIM6_MspInit 1 */
- }
-
-}
- 800196a: e022 b.n 80019b2 <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM4)
- 800196c: 687b ldr r3, [r7, #4]
- 800196e: 681b ldr r3, [r3, #0]
- 8001970: 4a15 ldr r2, [pc, #84] ; (80019c8 <HAL_TIM_Base_MspInit+0x88>)
- 8001972: 4293 cmp r3, r2
- 8001974: d10c bne.n 8001990 <HAL_TIM_Base_MspInit+0x50>
- __HAL_RCC_TIM4_CLK_ENABLE();
- 8001976: 4b13 ldr r3, [pc, #76] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 8001978: 6c1b ldr r3, [r3, #64] ; 0x40
- 800197a: 4a12 ldr r2, [pc, #72] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 800197c: f043 0304 orr.w r3, r3, #4
- 8001980: 6413 str r3, [r2, #64] ; 0x40
- 8001982: 4b10 ldr r3, [pc, #64] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 8001984: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001986: f003 0304 and.w r3, r3, #4
- 800198a: 613b str r3, [r7, #16]
- 800198c: 693b ldr r3, [r7, #16]
-}
- 800198e: e010 b.n 80019b2 <HAL_TIM_Base_MspInit+0x72>
- else if(htim_base->Instance==TIM6)
- 8001990: 687b ldr r3, [r7, #4]
- 8001992: 681b ldr r3, [r3, #0]
- 8001994: 4a0d ldr r2, [pc, #52] ; (80019cc <HAL_TIM_Base_MspInit+0x8c>)
- 8001996: 4293 cmp r3, r2
- 8001998: d10b bne.n 80019b2 <HAL_TIM_Base_MspInit+0x72>
- __HAL_RCC_TIM6_CLK_ENABLE();
- 800199a: 4b0a ldr r3, [pc, #40] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 800199c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800199e: 4a09 ldr r2, [pc, #36] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 80019a0: f043 0310 orr.w r3, r3, #16
- 80019a4: 6413 str r3, [r2, #64] ; 0x40
- 80019a6: 4b07 ldr r3, [pc, #28] ; (80019c4 <HAL_TIM_Base_MspInit+0x84>)
- 80019a8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80019aa: f003 0310 and.w r3, r3, #16
- 80019ae: 60fb str r3, [r7, #12]
- 80019b0: 68fb ldr r3, [r7, #12]
-}
- 80019b2: bf00 nop
- 80019b4: 371c adds r7, #28
- 80019b6: 46bd mov sp, r7
- 80019b8: f85d 7b04 ldr.w r7, [sp], #4
- 80019bc: 4770 bx lr
- 80019be: bf00 nop
- 80019c0: 40000400 .word 0x40000400
- 80019c4: 40023800 .word 0x40023800
- 80019c8: 40000800 .word 0x40000800
- 80019cc: 40001000 .word 0x40001000
-
-080019d0 <HAL_TIM_MspPostInit>:
-
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
-{
- 80019d0: b580 push {r7, lr}
- 80019d2: b088 sub sp, #32
- 80019d4: af00 add r7, sp, #0
- 80019d6: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80019d8: f107 030c add.w r3, r7, #12
- 80019dc: 2200 movs r2, #0
- 80019de: 601a str r2, [r3, #0]
- 80019e0: 605a str r2, [r3, #4]
- 80019e2: 609a str r2, [r3, #8]
- 80019e4: 60da str r2, [r3, #12]
- 80019e6: 611a str r2, [r3, #16]
- if(htim->Instance==TIM4)
- 80019e8: 687b ldr r3, [r7, #4]
- 80019ea: 681b ldr r3, [r3, #0]
- 80019ec: 4a11 ldr r2, [pc, #68] ; (8001a34 <HAL_TIM_MspPostInit+0x64>)
- 80019ee: 4293 cmp r3, r2
- 80019f0: d11c bne.n 8001a2c <HAL_TIM_MspPostInit+0x5c>
- {
- /* USER CODE BEGIN TIM4_MspPostInit 0 */
-
- /* USER CODE END TIM4_MspPostInit 0 */
-
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 80019f2: 4b11 ldr r3, [pc, #68] ; (8001a38 <HAL_TIM_MspPostInit+0x68>)
- 80019f4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80019f6: 4a10 ldr r2, [pc, #64] ; (8001a38 <HAL_TIM_MspPostInit+0x68>)
- 80019f8: f043 0308 orr.w r3, r3, #8
- 80019fc: 6313 str r3, [r2, #48] ; 0x30
- 80019fe: 4b0e ldr r3, [pc, #56] ; (8001a38 <HAL_TIM_MspPostInit+0x68>)
- 8001a00: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001a02: f003 0308 and.w r3, r3, #8
- 8001a06: 60bb str r3, [r7, #8]
- 8001a08: 68bb ldr r3, [r7, #8]
- /**TIM4 GPIO Configuration
- PD14 ------> TIM4_CH3
- PD15 ------> TIM4_CH4
- */
- GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin;
- 8001a0a: f44f 4340 mov.w r3, #49152 ; 0xc000
- 8001a0e: 60fb str r3, [r7, #12]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001a10: 2302 movs r3, #2
- 8001a12: 613b str r3, [r7, #16]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001a14: 2300 movs r3, #0
- 8001a16: 617b str r3, [r7, #20]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001a18: 2300 movs r3, #0
- 8001a1a: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
- 8001a1c: 2302 movs r3, #2
- 8001a1e: 61fb str r3, [r7, #28]
- HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
- 8001a20: f107 030c add.w r3, r7, #12
- 8001a24: 4619 mov r1, r3
- 8001a26: 4805 ldr r0, [pc, #20] ; (8001a3c <HAL_TIM_MspPostInit+0x6c>)
- 8001a28: f000 fa92 bl 8001f50 <HAL_GPIO_Init>
- /* USER CODE BEGIN TIM4_MspPostInit 1 */
-
- /* USER CODE END TIM4_MspPostInit 1 */
- }
-
-}
- 8001a2c: bf00 nop
- 8001a2e: 3720 adds r7, #32
- 8001a30: 46bd mov sp, r7
- 8001a32: bd80 pop {r7, pc}
- 8001a34: 40000800 .word 0x40000800
- 8001a38: 40023800 .word 0x40023800
- 8001a3c: 40020c00 .word 0x40020c00
-
-08001a40 <HAL_UART_MspInit>:
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
- 8001a40: b580 push {r7, lr}
- 8001a42: b08a sub sp, #40 ; 0x28
- 8001a44: af00 add r7, sp, #0
- 8001a46: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001a48: f107 0314 add.w r3, r7, #20
- 8001a4c: 2200 movs r2, #0
- 8001a4e: 601a str r2, [r3, #0]
- 8001a50: 605a str r2, [r3, #4]
- 8001a52: 609a str r2, [r3, #8]
- 8001a54: 60da str r2, [r3, #12]
- 8001a56: 611a str r2, [r3, #16]
- if(huart->Instance==USART6)
- 8001a58: 687b ldr r3, [r7, #4]
- 8001a5a: 681b ldr r3, [r3, #0]
- 8001a5c: 4a17 ldr r2, [pc, #92] ; (8001abc <HAL_UART_MspInit+0x7c>)
- 8001a5e: 4293 cmp r3, r2
- 8001a60: d127 bne.n 8001ab2 <HAL_UART_MspInit+0x72>
- {
- /* USER CODE BEGIN USART6_MspInit 0 */
-
- /* USER CODE END USART6_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_USART6_CLK_ENABLE();
- 8001a62: 4b17 ldr r3, [pc, #92] ; (8001ac0 <HAL_UART_MspInit+0x80>)
- 8001a64: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001a66: 4a16 ldr r2, [pc, #88] ; (8001ac0 <HAL_UART_MspInit+0x80>)
- 8001a68: f043 0320 orr.w r3, r3, #32
- 8001a6c: 6453 str r3, [r2, #68] ; 0x44
- 8001a6e: 4b14 ldr r3, [pc, #80] ; (8001ac0 <HAL_UART_MspInit+0x80>)
- 8001a70: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001a72: f003 0320 and.w r3, r3, #32
- 8001a76: 613b str r3, [r7, #16]
- 8001a78: 693b ldr r3, [r7, #16]
-
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 8001a7a: 4b11 ldr r3, [pc, #68] ; (8001ac0 <HAL_UART_MspInit+0x80>)
- 8001a7c: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001a7e: 4a10 ldr r2, [pc, #64] ; (8001ac0 <HAL_UART_MspInit+0x80>)
- 8001a80: f043 0304 orr.w r3, r3, #4
- 8001a84: 6313 str r3, [r2, #48] ; 0x30
- 8001a86: 4b0e ldr r3, [pc, #56] ; (8001ac0 <HAL_UART_MspInit+0x80>)
- 8001a88: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001a8a: f003 0304 and.w r3, r3, #4
- 8001a8e: 60fb str r3, [r7, #12]
- 8001a90: 68fb ldr r3, [r7, #12]
- /**USART6 GPIO Configuration
- PC6 ------> USART6_TX
- PC7 ------> USART6_RX
- */
- GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 8001a92: 23c0 movs r3, #192 ; 0xc0
- 8001a94: 617b str r3, [r7, #20]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001a96: 2302 movs r3, #2
- 8001a98: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001a9a: 2300 movs r3, #0
- 8001a9c: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8001a9e: 2303 movs r3, #3
- 8001aa0: 623b str r3, [r7, #32]
- GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
- 8001aa2: 2308 movs r3, #8
- 8001aa4: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8001aa6: f107 0314 add.w r3, r7, #20
- 8001aaa: 4619 mov r1, r3
- 8001aac: 4805 ldr r0, [pc, #20] ; (8001ac4 <HAL_UART_MspInit+0x84>)
- 8001aae: f000 fa4f bl 8001f50 <HAL_GPIO_Init>
- /* USER CODE BEGIN USART6_MspInit 1 */
-
- /* USER CODE END USART6_MspInit 1 */
- }
-
-}
- 8001ab2: bf00 nop
- 8001ab4: 3728 adds r7, #40 ; 0x28
- 8001ab6: 46bd mov sp, r7
- 8001ab8: bd80 pop {r7, pc}
- 8001aba: bf00 nop
- 8001abc: 40011400 .word 0x40011400
- 8001ac0: 40023800 .word 0x40023800
- 8001ac4: 40020800 .word 0x40020800
-
-08001ac8 <NMI_Handler>:
-/******************************************************************************/
-/**
- * @brief This function handles Non maskable interrupt.
- */
-void NMI_Handler(void)
-{
- 8001ac8: b480 push {r7}
- 8001aca: af00 add r7, sp, #0
-
- /* USER CODE END NonMaskableInt_IRQn 0 */
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
- /* USER CODE END NonMaskableInt_IRQn 1 */
-}
- 8001acc: bf00 nop
- 8001ace: 46bd mov sp, r7
- 8001ad0: f85d 7b04 ldr.w r7, [sp], #4
- 8001ad4: 4770 bx lr
-
-08001ad6 <HardFault_Handler>:
-
-/**
- * @brief This function handles Hard fault interrupt.
- */
-void HardFault_Handler(void)
-{
- 8001ad6: b480 push {r7}
- 8001ad8: af00 add r7, sp, #0
- /* USER CODE BEGIN HardFault_IRQn 0 */
-
- /* USER CODE END HardFault_IRQn 0 */
- while (1)
- 8001ada: e7fe b.n 8001ada <HardFault_Handler+0x4>
-
-08001adc <MemManage_Handler>:
-
-/**
- * @brief This function handles Memory management fault.
- */
-void MemManage_Handler(void)
-{
- 8001adc: b480 push {r7}
- 8001ade: af00 add r7, sp, #0
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
- /* USER CODE END MemoryManagement_IRQn 0 */
- while (1)
- 8001ae0: e7fe b.n 8001ae0 <MemManage_Handler+0x4>
-
-08001ae2 <BusFault_Handler>:
-
-/**
- * @brief This function handles Pre-fetch fault, memory access fault.
- */
-void BusFault_Handler(void)
-{
- 8001ae2: b480 push {r7}
- 8001ae4: af00 add r7, sp, #0
- /* USER CODE BEGIN BusFault_IRQn 0 */
-
- /* USER CODE END BusFault_IRQn 0 */
- while (1)
- 8001ae6: e7fe b.n 8001ae6 <BusFault_Handler+0x4>
-
-08001ae8 <UsageFault_Handler>:
-
-/**
- * @brief This function handles Undefined instruction or illegal state.
- */
-void UsageFault_Handler(void)
-{
- 8001ae8: b480 push {r7}
- 8001aea: af00 add r7, sp, #0
- /* USER CODE BEGIN UsageFault_IRQn 0 */
-
- /* USER CODE END UsageFault_IRQn 0 */
- while (1)
- 8001aec: e7fe b.n 8001aec <UsageFault_Handler+0x4>
-
-08001aee <SVC_Handler>:
-
-/**
- * @brief This function handles System service call via SWI instruction.
- */
-void SVC_Handler(void)
-{
- 8001aee: b480 push {r7}
- 8001af0: af00 add r7, sp, #0
-
- /* USER CODE END SVCall_IRQn 0 */
- /* USER CODE BEGIN SVCall_IRQn 1 */
-
- /* USER CODE END SVCall_IRQn 1 */
-}
- 8001af2: bf00 nop
- 8001af4: 46bd mov sp, r7
- 8001af6: f85d 7b04 ldr.w r7, [sp], #4
- 8001afa: 4770 bx lr
-
-08001afc <DebugMon_Handler>:
-
-/**
- * @brief This function handles Debug monitor.
- */
-void DebugMon_Handler(void)
-{
- 8001afc: b480 push {r7}
- 8001afe: af00 add r7, sp, #0
-
- /* USER CODE END DebugMonitor_IRQn 0 */
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
- /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 8001b00: bf00 nop
- 8001b02: 46bd mov sp, r7
- 8001b04: f85d 7b04 ldr.w r7, [sp], #4
- 8001b08: 4770 bx lr
-
-08001b0a <PendSV_Handler>:
-
-/**
- * @brief This function handles Pendable request for system service.
- */
-void PendSV_Handler(void)
-{
- 8001b0a: b480 push {r7}
- 8001b0c: af00 add r7, sp, #0
-
- /* USER CODE END PendSV_IRQn 0 */
- /* USER CODE BEGIN PendSV_IRQn 1 */
-
- /* USER CODE END PendSV_IRQn 1 */
-}
- 8001b0e: bf00 nop
- 8001b10: 46bd mov sp, r7
- 8001b12: f85d 7b04 ldr.w r7, [sp], #4
- 8001b16: 4770 bx lr
-
-08001b18 <SysTick_Handler>:
-
-/**
- * @brief This function handles System tick timer.
- */
-void SysTick_Handler(void)
-{
- 8001b18: b580 push {r7, lr}
- 8001b1a: af00 add r7, sp, #0
- /* USER CODE BEGIN SysTick_IRQn 0 */
-
- /* USER CODE END SysTick_IRQn 0 */
- HAL_IncTick();
- 8001b1c: f000 f8c4 bl 8001ca8 <HAL_IncTick>
- /* USER CODE BEGIN SysTick_IRQn 1 */
-
- /* USER CODE END SysTick_IRQn 1 */
-}
- 8001b20: bf00 nop
- 8001b22: bd80 pop {r7, pc}
-
-08001b24 <TIM3_IRQHandler>:
-
-/**
- * @brief This function handles TIM3 global interrupt.
- */
-void TIM3_IRQHandler(void)
-{
- 8001b24: b580 push {r7, lr}
- 8001b26: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM3_IRQn 0 */
-
- /* USER CODE END TIM3_IRQn 0 */
- HAL_TIM_IRQHandler(&htim3);
- 8001b28: 4802 ldr r0, [pc, #8] ; (8001b34 <TIM3_IRQHandler+0x10>)
- 8001b2a: f001 fdec bl 8003706 <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM3_IRQn 1 */
-
- /* USER CODE END TIM3_IRQn 1 */
-}
- 8001b2e: bf00 nop
- 8001b30: bd80 pop {r7, pc}
- 8001b32: bf00 nop
- 8001b34: 2000006c .word 0x2000006c
-
-08001b38 <EXTI15_10_IRQHandler>:
-
-/**
- * @brief This function handles EXTI line[15:10] interrupts.
- */
-void EXTI15_10_IRQHandler(void)
-{
- 8001b38: b580 push {r7, lr}
- 8001b3a: af00 add r7, sp, #0
- /* USER CODE BEGIN EXTI15_10_IRQn 0 */
-
- /* USER CODE END EXTI15_10_IRQn 0 */
- HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
- 8001b3c: f44f 5000 mov.w r0, #8192 ; 0x2000
- 8001b40: f000 fbca bl 80022d8 <HAL_GPIO_EXTI_IRQHandler>
- /* USER CODE BEGIN EXTI15_10_IRQn 1 */
-
- /* USER CODE END EXTI15_10_IRQn 1 */
-}
- 8001b44: bf00 nop
- 8001b46: bd80 pop {r7, pc}
-
-08001b48 <TIM6_DAC_IRQHandler>:
-
-/**
- * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
- */
-void TIM6_DAC_IRQHandler(void)
-{
- 8001b48: b580 push {r7, lr}
- 8001b4a: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM6_DAC_IRQn 0 */
-
- /* USER CODE END TIM6_DAC_IRQn 0 */
- HAL_TIM_IRQHandler(&htim6);
- 8001b4c: 4802 ldr r0, [pc, #8] ; (8001b58 <TIM6_DAC_IRQHandler+0x10>)
- 8001b4e: f001 fdda bl 8003706 <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM6_DAC_IRQn 1 */
-
- /* USER CODE END TIM6_DAC_IRQn 1 */
-}
- 8001b52: bf00 nop
- 8001b54: bd80 pop {r7, pc}
- 8001b56: bf00 nop
- 8001b58: 2000012c .word 0x2000012c
-
-08001b5c <USART6_IRQHandler>:
-
-/**
- * @brief This function handles USART6 global interrupt.
- */
-void USART6_IRQHandler(void)
-{
- 8001b5c: b580 push {r7, lr}
- 8001b5e: af00 add r7, sp, #0
- /* USER CODE BEGIN USART6_IRQn 0 */
-
- /* USER CODE END USART6_IRQn 0 */
- HAL_UART_IRQHandler(&huart6);
- 8001b60: 4802 ldr r0, [pc, #8] ; (8001b6c <USART6_IRQHandler+0x10>)
- 8001b62: f002 fea3 bl 80048ac <HAL_UART_IRQHandler>
- /* USER CODE BEGIN USART6_IRQn 1 */
-
- /* USER CODE END USART6_IRQn 1 */
-}
- 8001b66: bf00 nop
- 8001b68: bd80 pop {r7, pc}
- 8001b6a: bf00 nop
- 8001b6c: 2000016c .word 0x2000016c
-
-08001b70 <SystemInit>:
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- 8001b70: b480 push {r7}
- 8001b72: af00 add r7, sp, #0
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 8001b74: 4b15 ldr r3, [pc, #84] ; (8001bcc <SystemInit+0x5c>)
- 8001b76: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001b7a: 4a14 ldr r2, [pc, #80] ; (8001bcc <SystemInit+0x5c>)
- 8001b7c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 8001b80: f8c2 3088 str.w r3, [r2, #136] ; 0x88
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
- 8001b84: 4b12 ldr r3, [pc, #72] ; (8001bd0 <SystemInit+0x60>)
- 8001b86: 681b ldr r3, [r3, #0]
- 8001b88: 4a11 ldr r2, [pc, #68] ; (8001bd0 <SystemInit+0x60>)
- 8001b8a: f043 0301 orr.w r3, r3, #1
- 8001b8e: 6013 str r3, [r2, #0]
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
- 8001b90: 4b0f ldr r3, [pc, #60] ; (8001bd0 <SystemInit+0x60>)
- 8001b92: 2200 movs r2, #0
- 8001b94: 609a str r2, [r3, #8]
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8001b96: 4b0e ldr r3, [pc, #56] ; (8001bd0 <SystemInit+0x60>)
- 8001b98: 681a ldr r2, [r3, #0]
- 8001b9a: 490d ldr r1, [pc, #52] ; (8001bd0 <SystemInit+0x60>)
- 8001b9c: 4b0d ldr r3, [pc, #52] ; (8001bd4 <SystemInit+0x64>)
- 8001b9e: 4013 ands r3, r2
- 8001ba0: 600b str r3, [r1, #0]
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
- 8001ba2: 4b0b ldr r3, [pc, #44] ; (8001bd0 <SystemInit+0x60>)
- 8001ba4: 4a0c ldr r2, [pc, #48] ; (8001bd8 <SystemInit+0x68>)
- 8001ba6: 605a str r2, [r3, #4]
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
- 8001ba8: 4b09 ldr r3, [pc, #36] ; (8001bd0 <SystemInit+0x60>)
- 8001baa: 681b ldr r3, [r3, #0]
- 8001bac: 4a08 ldr r2, [pc, #32] ; (8001bd0 <SystemInit+0x60>)
- 8001bae: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8001bb2: 6013 str r3, [r2, #0]
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
- 8001bb4: 4b06 ldr r3, [pc, #24] ; (8001bd0 <SystemInit+0x60>)
- 8001bb6: 2200 movs r2, #0
- 8001bb8: 60da str r2, [r3, #12]
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8001bba: 4b04 ldr r3, [pc, #16] ; (8001bcc <SystemInit+0x5c>)
- 8001bbc: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 8001bc0: 609a str r2, [r3, #8]
-#endif
-}
- 8001bc2: bf00 nop
- 8001bc4: 46bd mov sp, r7
- 8001bc6: f85d 7b04 ldr.w r7, [sp], #4
- 8001bca: 4770 bx lr
- 8001bcc: e000ed00 .word 0xe000ed00
- 8001bd0: 40023800 .word 0x40023800
- 8001bd4: fef6ffff .word 0xfef6ffff
- 8001bd8: 24003010 .word 0x24003010
-
-08001bdc <Reset_Handler>:
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
- 8001bdc: f8df d034 ldr.w sp, [pc, #52] ; 8001c14 <LoopFillZerobss+0x14>
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- 8001be0: 2100 movs r1, #0
- b LoopCopyDataInit
- 8001be2: e003 b.n 8001bec <LoopCopyDataInit>
-
-08001be4 <CopyDataInit>:
-
-CopyDataInit:
- ldr r3, =_sidata
- 8001be4: 4b0c ldr r3, [pc, #48] ; (8001c18 <LoopFillZerobss+0x18>)
- ldr r3, [r3, r1]
- 8001be6: 585b ldr r3, [r3, r1]
- str r3, [r0, r1]
- 8001be8: 5043 str r3, [r0, r1]
- adds r1, r1, #4
- 8001bea: 3104 adds r1, #4
-
-08001bec <LoopCopyDataInit>:
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- 8001bec: 480b ldr r0, [pc, #44] ; (8001c1c <LoopFillZerobss+0x1c>)
- ldr r3, =_edata
- 8001bee: 4b0c ldr r3, [pc, #48] ; (8001c20 <LoopFillZerobss+0x20>)
- adds r2, r0, r1
- 8001bf0: 1842 adds r2, r0, r1
- cmp r2, r3
- 8001bf2: 429a cmp r2, r3
- bcc CopyDataInit
- 8001bf4: d3f6 bcc.n 8001be4 <CopyDataInit>
- ldr r2, =_sbss
- 8001bf6: 4a0b ldr r2, [pc, #44] ; (8001c24 <LoopFillZerobss+0x24>)
- b LoopFillZerobss
- 8001bf8: e002 b.n 8001c00 <LoopFillZerobss>
-
-08001bfa <FillZerobss>:
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- 8001bfa: 2300 movs r3, #0
- str r3, [r2], #4
- 8001bfc: f842 3b04 str.w r3, [r2], #4
-
-08001c00 <LoopFillZerobss>:
-
-LoopFillZerobss:
- ldr r3, = _ebss
- 8001c00: 4b09 ldr r3, [pc, #36] ; (8001c28 <LoopFillZerobss+0x28>)
- cmp r2, r3
- 8001c02: 429a cmp r2, r3
- bcc FillZerobss
- 8001c04: d3f9 bcc.n 8001bfa <FillZerobss>
-
-/* Call the clock system initialization function.*/
- bl SystemInit
- 8001c06: f7ff ffb3 bl 8001b70 <SystemInit>
-/* Call static constructors */
- bl __libc_init_array
- 8001c0a: f003 fc31 bl 8005470 <__libc_init_array>
-/* Call the application's entry point.*/
- bl main
- 8001c0e: f7fe fff5 bl 8000bfc <main>
- bx lr
- 8001c12: 4770 bx lr
- ldr sp, =_estack /* set stack pointer */
- 8001c14: 20080000 .word 0x20080000
- ldr r3, =_sidata
- 8001c18: 0800550c .word 0x0800550c
- ldr r0, =_sdata
- 8001c1c: 20000000 .word 0x20000000
- ldr r3, =_edata
- 8001c20: 20000010 .word 0x20000010
- ldr r2, =_sbss
- 8001c24: 20000010 .word 0x20000010
- ldr r3, = _ebss
- 8001c28: 2000030c .word 0x2000030c
-
-08001c2c <ADC_IRQHandler>:
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- 8001c2c: e7fe b.n 8001c2c <ADC_IRQHandler>
-
-08001c2e <HAL_Init>:
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8001c2e: b580 push {r7, lr}
- 8001c30: af00 add r7, sp, #0
-#if (PREFETCH_ENABLE != 0U)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8001c32: 2003 movs r0, #3
- 8001c34: f000 f928 bl 8001e88 <HAL_NVIC_SetPriorityGrouping>
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
- 8001c38: 2000 movs r0, #0
- 8001c3a: f000 f805 bl 8001c48 <HAL_InitTick>
-
- /* Init the low level hardware */
- HAL_MspInit();
- 8001c3e: f7ff fdcb bl 80017d8 <HAL_MspInit>
-
- /* Return function status */
- return HAL_OK;
- 8001c42: 2300 movs r3, #0
-}
- 8001c44: 4618 mov r0, r3
- 8001c46: bd80 pop {r7, pc}
-
-08001c48 <HAL_InitTick>:
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- 8001c48: b580 push {r7, lr}
- 8001c4a: b082 sub sp, #8
- 8001c4c: af00 add r7, sp, #0
- 8001c4e: 6078 str r0, [r7, #4]
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8001c50: 4b12 ldr r3, [pc, #72] ; (8001c9c <HAL_InitTick+0x54>)
- 8001c52: 681a ldr r2, [r3, #0]
- 8001c54: 4b12 ldr r3, [pc, #72] ; (8001ca0 <HAL_InitTick+0x58>)
- 8001c56: 781b ldrb r3, [r3, #0]
- 8001c58: 4619 mov r1, r3
- 8001c5a: f44f 737a mov.w r3, #1000 ; 0x3e8
- 8001c5e: fbb3 f3f1 udiv r3, r3, r1
- 8001c62: fbb2 f3f3 udiv r3, r2, r3
- 8001c66: 4618 mov r0, r3
- 8001c68: f000 f943 bl 8001ef2 <HAL_SYSTICK_Config>
- 8001c6c: 4603 mov r3, r0
- 8001c6e: 2b00 cmp r3, #0
- 8001c70: d001 beq.n 8001c76 <HAL_InitTick+0x2e>
- {
- return HAL_ERROR;
- 8001c72: 2301 movs r3, #1
- 8001c74: e00e b.n 8001c94 <HAL_InitTick+0x4c>
- }
-
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8001c76: 687b ldr r3, [r7, #4]
- 8001c78: 2b0f cmp r3, #15
- 8001c7a: d80a bhi.n 8001c92 <HAL_InitTick+0x4a>
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8001c7c: 2200 movs r2, #0
- 8001c7e: 6879 ldr r1, [r7, #4]
- 8001c80: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001c84: f000 f90b bl 8001e9e <HAL_NVIC_SetPriority>
- uwTickPrio = TickPriority;
- 8001c88: 4a06 ldr r2, [pc, #24] ; (8001ca4 <HAL_InitTick+0x5c>)
- 8001c8a: 687b ldr r3, [r7, #4]
- 8001c8c: 6013 str r3, [r2, #0]
- {
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
- 8001c8e: 2300 movs r3, #0
- 8001c90: e000 b.n 8001c94 <HAL_InitTick+0x4c>
- return HAL_ERROR;
- 8001c92: 2301 movs r3, #1
-}
- 8001c94: 4618 mov r0, r3
- 8001c96: 3708 adds r7, #8
- 8001c98: 46bd mov sp, r7
- 8001c9a: bd80 pop {r7, pc}
- 8001c9c: 20000004 .word 0x20000004
- 8001ca0: 2000000c .word 0x2000000c
- 8001ca4: 20000008 .word 0x20000008
-
-08001ca8 <HAL_IncTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- 8001ca8: b480 push {r7}
- 8001caa: af00 add r7, sp, #0
- uwTick += uwTickFreq;
- 8001cac: 4b06 ldr r3, [pc, #24] ; (8001cc8 <HAL_IncTick+0x20>)
- 8001cae: 781b ldrb r3, [r3, #0]
- 8001cb0: 461a mov r2, r3
- 8001cb2: 4b06 ldr r3, [pc, #24] ; (8001ccc <HAL_IncTick+0x24>)
- 8001cb4: 681b ldr r3, [r3, #0]
- 8001cb6: 4413 add r3, r2
- 8001cb8: 4a04 ldr r2, [pc, #16] ; (8001ccc <HAL_IncTick+0x24>)
- 8001cba: 6013 str r3, [r2, #0]
-}
- 8001cbc: bf00 nop
- 8001cbe: 46bd mov sp, r7
- 8001cc0: f85d 7b04 ldr.w r7, [sp], #4
- 8001cc4: 4770 bx lr
- 8001cc6: bf00 nop
- 8001cc8: 2000000c .word 0x2000000c
- 8001ccc: 20000308 .word 0x20000308
-
-08001cd0 <HAL_GetTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- 8001cd0: b480 push {r7}
- 8001cd2: af00 add r7, sp, #0
- return uwTick;
- 8001cd4: 4b03 ldr r3, [pc, #12] ; (8001ce4 <HAL_GetTick+0x14>)
- 8001cd6: 681b ldr r3, [r3, #0]
-}
- 8001cd8: 4618 mov r0, r3
- 8001cda: 46bd mov sp, r7
- 8001cdc: f85d 7b04 ldr.w r7, [sp], #4
- 8001ce0: 4770 bx lr
- 8001ce2: bf00 nop
- 8001ce4: 20000308 .word 0x20000308
-
-08001ce8 <__NVIC_SetPriorityGrouping>:
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001ce8: b480 push {r7}
- 8001cea: b085 sub sp, #20
- 8001cec: af00 add r7, sp, #0
- 8001cee: 6078 str r0, [r7, #4]
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001cf0: 687b ldr r3, [r7, #4]
- 8001cf2: f003 0307 and.w r3, r3, #7
- 8001cf6: 60fb str r3, [r7, #12]
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- 8001cf8: 4b0b ldr r3, [pc, #44] ; (8001d28 <__NVIC_SetPriorityGrouping+0x40>)
- 8001cfa: 68db ldr r3, [r3, #12]
- 8001cfc: 60bb str r3, [r7, #8]
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 8001cfe: 68ba ldr r2, [r7, #8]
- 8001d00: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8001d04: 4013 ands r3, r2
- 8001d06: 60bb str r3, [r7, #8]
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8001d08: 68fb ldr r3, [r7, #12]
- 8001d0a: 021a lsls r2, r3, #8
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8001d0c: 68bb ldr r3, [r7, #8]
- 8001d0e: 431a orrs r2, r3
- reg_value = (reg_value |
- 8001d10: 4b06 ldr r3, [pc, #24] ; (8001d2c <__NVIC_SetPriorityGrouping+0x44>)
- 8001d12: 4313 orrs r3, r2
- 8001d14: 60bb str r3, [r7, #8]
- SCB->AIRCR = reg_value;
- 8001d16: 4a04 ldr r2, [pc, #16] ; (8001d28 <__NVIC_SetPriorityGrouping+0x40>)
- 8001d18: 68bb ldr r3, [r7, #8]
- 8001d1a: 60d3 str r3, [r2, #12]
-}
- 8001d1c: bf00 nop
- 8001d1e: 3714 adds r7, #20
- 8001d20: 46bd mov sp, r7
- 8001d22: f85d 7b04 ldr.w r7, [sp], #4
- 8001d26: 4770 bx lr
- 8001d28: e000ed00 .word 0xe000ed00
- 8001d2c: 05fa0000 .word 0x05fa0000
-
-08001d30 <__NVIC_GetPriorityGrouping>:
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- 8001d30: b480 push {r7}
- 8001d32: af00 add r7, sp, #0
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8001d34: 4b04 ldr r3, [pc, #16] ; (8001d48 <__NVIC_GetPriorityGrouping+0x18>)
- 8001d36: 68db ldr r3, [r3, #12]
- 8001d38: 0a1b lsrs r3, r3, #8
- 8001d3a: f003 0307 and.w r3, r3, #7
-}
- 8001d3e: 4618 mov r0, r3
- 8001d40: 46bd mov sp, r7
- 8001d42: f85d 7b04 ldr.w r7, [sp], #4
- 8001d46: 4770 bx lr
- 8001d48: e000ed00 .word 0xe000ed00
-
-08001d4c <__NVIC_EnableIRQ>:
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001d4c: b480 push {r7}
- 8001d4e: b083 sub sp, #12
- 8001d50: af00 add r7, sp, #0
- 8001d52: 4603 mov r3, r0
- 8001d54: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001d56: f997 3007 ldrsb.w r3, [r7, #7]
- 8001d5a: 2b00 cmp r3, #0
- 8001d5c: db0b blt.n 8001d76 <__NVIC_EnableIRQ+0x2a>
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 8001d5e: 79fb ldrb r3, [r7, #7]
- 8001d60: f003 021f and.w r2, r3, #31
- 8001d64: 4907 ldr r1, [pc, #28] ; (8001d84 <__NVIC_EnableIRQ+0x38>)
- 8001d66: f997 3007 ldrsb.w r3, [r7, #7]
- 8001d6a: 095b lsrs r3, r3, #5
- 8001d6c: 2001 movs r0, #1
- 8001d6e: fa00 f202 lsl.w r2, r0, r2
- 8001d72: f841 2023 str.w r2, [r1, r3, lsl #2]
- }
-}
- 8001d76: bf00 nop
- 8001d78: 370c adds r7, #12
- 8001d7a: 46bd mov sp, r7
- 8001d7c: f85d 7b04 ldr.w r7, [sp], #4
- 8001d80: 4770 bx lr
- 8001d82: bf00 nop
- 8001d84: e000e100 .word 0xe000e100
-
-08001d88 <__NVIC_SetPriority>:
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- 8001d88: b480 push {r7}
- 8001d8a: b083 sub sp, #12
- 8001d8c: af00 add r7, sp, #0
- 8001d8e: 4603 mov r3, r0
- 8001d90: 6039 str r1, [r7, #0]
- 8001d92: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8001d94: f997 3007 ldrsb.w r3, [r7, #7]
- 8001d98: 2b00 cmp r3, #0
- 8001d9a: db0a blt.n 8001db2 <__NVIC_SetPriority+0x2a>
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001d9c: 683b ldr r3, [r7, #0]
- 8001d9e: b2da uxtb r2, r3
- 8001da0: 490c ldr r1, [pc, #48] ; (8001dd4 <__NVIC_SetPriority+0x4c>)
- 8001da2: f997 3007 ldrsb.w r3, [r7, #7]
- 8001da6: 0112 lsls r2, r2, #4
- 8001da8: b2d2 uxtb r2, r2
- 8001daa: 440b add r3, r1
- 8001dac: f883 2300 strb.w r2, [r3, #768] ; 0x300
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
- 8001db0: e00a b.n 8001dc8 <__NVIC_SetPriority+0x40>
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001db2: 683b ldr r3, [r7, #0]
- 8001db4: b2da uxtb r2, r3
- 8001db6: 4908 ldr r1, [pc, #32] ; (8001dd8 <__NVIC_SetPriority+0x50>)
- 8001db8: 79fb ldrb r3, [r7, #7]
- 8001dba: f003 030f and.w r3, r3, #15
- 8001dbe: 3b04 subs r3, #4
- 8001dc0: 0112 lsls r2, r2, #4
- 8001dc2: b2d2 uxtb r2, r2
- 8001dc4: 440b add r3, r1
- 8001dc6: 761a strb r2, [r3, #24]
-}
- 8001dc8: bf00 nop
- 8001dca: 370c adds r7, #12
- 8001dcc: 46bd mov sp, r7
- 8001dce: f85d 7b04 ldr.w r7, [sp], #4
- 8001dd2: 4770 bx lr
- 8001dd4: e000e100 .word 0xe000e100
- 8001dd8: e000ed00 .word 0xe000ed00
-
-08001ddc <NVIC_EncodePriority>:
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001ddc: b480 push {r7}
- 8001dde: b089 sub sp, #36 ; 0x24
- 8001de0: af00 add r7, sp, #0
- 8001de2: 60f8 str r0, [r7, #12]
- 8001de4: 60b9 str r1, [r7, #8]
- 8001de6: 607a str r2, [r7, #4]
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001de8: 68fb ldr r3, [r7, #12]
- 8001dea: f003 0307 and.w r3, r3, #7
- 8001dee: 61fb str r3, [r7, #28]
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8001df0: 69fb ldr r3, [r7, #28]
- 8001df2: f1c3 0307 rsb r3, r3, #7
- 8001df6: 2b04 cmp r3, #4
- 8001df8: bf28 it cs
- 8001dfa: 2304 movcs r3, #4
- 8001dfc: 61bb str r3, [r7, #24]
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8001dfe: 69fb ldr r3, [r7, #28]
- 8001e00: 3304 adds r3, #4
- 8001e02: 2b06 cmp r3, #6
- 8001e04: d902 bls.n 8001e0c <NVIC_EncodePriority+0x30>
- 8001e06: 69fb ldr r3, [r7, #28]
- 8001e08: 3b03 subs r3, #3
- 8001e0a: e000 b.n 8001e0e <NVIC_EncodePriority+0x32>
- 8001e0c: 2300 movs r3, #0
- 8001e0e: 617b str r3, [r7, #20]
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001e10: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8001e14: 69bb ldr r3, [r7, #24]
- 8001e16: fa02 f303 lsl.w r3, r2, r3
- 8001e1a: 43da mvns r2, r3
- 8001e1c: 68bb ldr r3, [r7, #8]
- 8001e1e: 401a ands r2, r3
- 8001e20: 697b ldr r3, [r7, #20]
- 8001e22: 409a lsls r2, r3
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8001e24: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 8001e28: 697b ldr r3, [r7, #20]
- 8001e2a: fa01 f303 lsl.w r3, r1, r3
- 8001e2e: 43d9 mvns r1, r3
- 8001e30: 687b ldr r3, [r7, #4]
- 8001e32: 400b ands r3, r1
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001e34: 4313 orrs r3, r2
- );
-}
- 8001e36: 4618 mov r0, r3
- 8001e38: 3724 adds r7, #36 ; 0x24
- 8001e3a: 46bd mov sp, r7
- 8001e3c: f85d 7b04 ldr.w r7, [sp], #4
- 8001e40: 4770 bx lr
- ...
-
-08001e44 <SysTick_Config>:
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 8001e44: b580 push {r7, lr}
- 8001e46: b082 sub sp, #8
- 8001e48: af00 add r7, sp, #0
- 8001e4a: 6078 str r0, [r7, #4]
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8001e4c: 687b ldr r3, [r7, #4]
- 8001e4e: 3b01 subs r3, #1
- 8001e50: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8001e54: d301 bcc.n 8001e5a <SysTick_Config+0x16>
- {
- return (1UL); /* Reload value impossible */
- 8001e56: 2301 movs r3, #1
- 8001e58: e00f b.n 8001e7a <SysTick_Config+0x36>
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8001e5a: 4a0a ldr r2, [pc, #40] ; (8001e84 <SysTick_Config+0x40>)
- 8001e5c: 687b ldr r3, [r7, #4]
- 8001e5e: 3b01 subs r3, #1
- 8001e60: 6053 str r3, [r2, #4]
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8001e62: 210f movs r1, #15
- 8001e64: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001e68: f7ff ff8e bl 8001d88 <__NVIC_SetPriority>
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8001e6c: 4b05 ldr r3, [pc, #20] ; (8001e84 <SysTick_Config+0x40>)
- 8001e6e: 2200 movs r2, #0
- 8001e70: 609a str r2, [r3, #8]
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001e72: 4b04 ldr r3, [pc, #16] ; (8001e84 <SysTick_Config+0x40>)
- 8001e74: 2207 movs r2, #7
- 8001e76: 601a str r2, [r3, #0]
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
- 8001e78: 2300 movs r3, #0
-}
- 8001e7a: 4618 mov r0, r3
- 8001e7c: 3708 adds r7, #8
- 8001e7e: 46bd mov sp, r7
- 8001e80: bd80 pop {r7, pc}
- 8001e82: bf00 nop
- 8001e84: e000e010 .word 0xe000e010
-
-08001e88 <HAL_NVIC_SetPriorityGrouping>:
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001e88: b580 push {r7, lr}
- 8001e8a: b082 sub sp, #8
- 8001e8c: af00 add r7, sp, #0
- 8001e8e: 6078 str r0, [r7, #4]
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
- 8001e90: 6878 ldr r0, [r7, #4]
- 8001e92: f7ff ff29 bl 8001ce8 <__NVIC_SetPriorityGrouping>
-}
- 8001e96: bf00 nop
- 8001e98: 3708 adds r7, #8
- 8001e9a: 46bd mov sp, r7
- 8001e9c: bd80 pop {r7, pc}
-
-08001e9e <HAL_NVIC_SetPriority>:
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8001e9e: b580 push {r7, lr}
- 8001ea0: b086 sub sp, #24
- 8001ea2: af00 add r7, sp, #0
- 8001ea4: 4603 mov r3, r0
- 8001ea6: 60b9 str r1, [r7, #8]
- 8001ea8: 607a str r2, [r7, #4]
- 8001eaa: 73fb strb r3, [r7, #15]
- uint32_t prioritygroup = 0x00;
- 8001eac: 2300 movs r3, #0
- 8001eae: 617b str r3, [r7, #20]
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
- 8001eb0: f7ff ff3e bl 8001d30 <__NVIC_GetPriorityGrouping>
- 8001eb4: 6178 str r0, [r7, #20]
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8001eb6: 687a ldr r2, [r7, #4]
- 8001eb8: 68b9 ldr r1, [r7, #8]
- 8001eba: 6978 ldr r0, [r7, #20]
- 8001ebc: f7ff ff8e bl 8001ddc <NVIC_EncodePriority>
- 8001ec0: 4602 mov r2, r0
- 8001ec2: f997 300f ldrsb.w r3, [r7, #15]
- 8001ec6: 4611 mov r1, r2
- 8001ec8: 4618 mov r0, r3
- 8001eca: f7ff ff5d bl 8001d88 <__NVIC_SetPriority>
-}
- 8001ece: bf00 nop
- 8001ed0: 3718 adds r7, #24
- 8001ed2: 46bd mov sp, r7
- 8001ed4: bd80 pop {r7, pc}
-
-08001ed6 <HAL_NVIC_EnableIRQ>:
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8001ed6: b580 push {r7, lr}
- 8001ed8: b082 sub sp, #8
- 8001eda: af00 add r7, sp, #0
- 8001edc: 4603 mov r3, r0
- 8001ede: 71fb strb r3, [r7, #7]
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
- 8001ee0: f997 3007 ldrsb.w r3, [r7, #7]
- 8001ee4: 4618 mov r0, r3
- 8001ee6: f7ff ff31 bl 8001d4c <__NVIC_EnableIRQ>
-}
- 8001eea: bf00 nop
- 8001eec: 3708 adds r7, #8
- 8001eee: 46bd mov sp, r7
- 8001ef0: bd80 pop {r7, pc}
-
-08001ef2 <HAL_SYSTICK_Config>:
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 8001ef2: b580 push {r7, lr}
- 8001ef4: b082 sub sp, #8
- 8001ef6: af00 add r7, sp, #0
- 8001ef8: 6078 str r0, [r7, #4]
- return SysTick_Config(TicksNumb);
- 8001efa: 6878 ldr r0, [r7, #4]
- 8001efc: f7ff ffa2 bl 8001e44 <SysTick_Config>
- 8001f00: 4603 mov r3, r0
-}
- 8001f02: 4618 mov r0, r3
- 8001f04: 3708 adds r7, #8
- 8001f06: 46bd mov sp, r7
- 8001f08: bd80 pop {r7, pc}
-
-08001f0a <HAL_DMA_Abort_IT>:
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- 8001f0a: b480 push {r7}
- 8001f0c: b083 sub sp, #12
- 8001f0e: af00 add r7, sp, #0
- 8001f10: 6078 str r0, [r7, #4]
- if(hdma->State != HAL_DMA_STATE_BUSY)
- 8001f12: 687b ldr r3, [r7, #4]
- 8001f14: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
- 8001f18: b2db uxtb r3, r3
- 8001f1a: 2b02 cmp r3, #2
- 8001f1c: d004 beq.n 8001f28 <HAL_DMA_Abort_IT+0x1e>
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 8001f1e: 687b ldr r3, [r7, #4]
- 8001f20: 2280 movs r2, #128 ; 0x80
- 8001f22: 655a str r2, [r3, #84] ; 0x54
- return HAL_ERROR;
- 8001f24: 2301 movs r3, #1
- 8001f26: e00c b.n 8001f42 <HAL_DMA_Abort_IT+0x38>
- }
- else
- {
- /* Set Abort State */
- hdma->State = HAL_DMA_STATE_ABORT;
- 8001f28: 687b ldr r3, [r7, #4]
- 8001f2a: 2205 movs r2, #5
- 8001f2c: f883 2035 strb.w r2, [r3, #53] ; 0x35
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
- 8001f30: 687b ldr r3, [r7, #4]
- 8001f32: 681b ldr r3, [r3, #0]
- 8001f34: 681a ldr r2, [r3, #0]
- 8001f36: 687b ldr r3, [r7, #4]
- 8001f38: 681b ldr r3, [r3, #0]
- 8001f3a: f022 0201 bic.w r2, r2, #1
- 8001f3e: 601a str r2, [r3, #0]
- }
-
- return HAL_OK;
- 8001f40: 2300 movs r3, #0
-}
- 8001f42: 4618 mov r0, r3
- 8001f44: 370c adds r7, #12
- 8001f46: 46bd mov sp, r7
- 8001f48: f85d 7b04 ldr.w r7, [sp], #4
- 8001f4c: 4770 bx lr
- ...
-
-08001f50 <HAL_GPIO_Init>:
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8001f50: b480 push {r7}
- 8001f52: b089 sub sp, #36 ; 0x24
- 8001f54: af00 add r7, sp, #0
- 8001f56: 6078 str r0, [r7, #4]
- 8001f58: 6039 str r1, [r7, #0]
- uint32_t position = 0x00;
- 8001f5a: 2300 movs r3, #0
- 8001f5c: 61fb str r3, [r7, #28]
- uint32_t ioposition = 0x00;
- 8001f5e: 2300 movs r3, #0
- 8001f60: 617b str r3, [r7, #20]
- uint32_t iocurrent = 0x00;
- 8001f62: 2300 movs r3, #0
- 8001f64: 613b str r3, [r7, #16]
- uint32_t temp = 0x00;
- 8001f66: 2300 movs r3, #0
- 8001f68: 61bb str r3, [r7, #24]
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
- 8001f6a: 2300 movs r3, #0
- 8001f6c: 61fb str r3, [r7, #28]
- 8001f6e: e175 b.n 800225c <HAL_GPIO_Init+0x30c>
- {
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- 8001f70: 2201 movs r2, #1
- 8001f72: 69fb ldr r3, [r7, #28]
- 8001f74: fa02 f303 lsl.w r3, r2, r3
- 8001f78: 617b str r3, [r7, #20]
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8001f7a: 683b ldr r3, [r7, #0]
- 8001f7c: 681b ldr r3, [r3, #0]
- 8001f7e: 697a ldr r2, [r7, #20]
- 8001f80: 4013 ands r3, r2
- 8001f82: 613b str r3, [r7, #16]
-
- if(iocurrent == ioposition)
- 8001f84: 693a ldr r2, [r7, #16]
- 8001f86: 697b ldr r3, [r7, #20]
- 8001f88: 429a cmp r2, r3
- 8001f8a: f040 8164 bne.w 8002256 <HAL_GPIO_Init+0x306>
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8001f8e: 683b ldr r3, [r7, #0]
- 8001f90: 685b ldr r3, [r3, #4]
- 8001f92: 2b02 cmp r3, #2
- 8001f94: d003 beq.n 8001f9e <HAL_GPIO_Init+0x4e>
- 8001f96: 683b ldr r3, [r7, #0]
- 8001f98: 685b ldr r3, [r3, #4]
- 8001f9a: 2b12 cmp r3, #18
- 8001f9c: d123 bne.n 8001fe6 <HAL_GPIO_Init+0x96>
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- 8001f9e: 69fb ldr r3, [r7, #28]
- 8001fa0: 08da lsrs r2, r3, #3
- 8001fa2: 687b ldr r3, [r7, #4]
- 8001fa4: 3208 adds r2, #8
- 8001fa6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 8001faa: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 8001fac: 69fb ldr r3, [r7, #28]
- 8001fae: f003 0307 and.w r3, r3, #7
- 8001fb2: 009b lsls r3, r3, #2
- 8001fb4: 220f movs r2, #15
- 8001fb6: fa02 f303 lsl.w r3, r2, r3
- 8001fba: 43db mvns r3, r3
- 8001fbc: 69ba ldr r2, [r7, #24]
- 8001fbe: 4013 ands r3, r2
- 8001fc0: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 8001fc2: 683b ldr r3, [r7, #0]
- 8001fc4: 691a ldr r2, [r3, #16]
- 8001fc6: 69fb ldr r3, [r7, #28]
- 8001fc8: f003 0307 and.w r3, r3, #7
- 8001fcc: 009b lsls r3, r3, #2
- 8001fce: fa02 f303 lsl.w r3, r2, r3
- 8001fd2: 69ba ldr r2, [r7, #24]
- 8001fd4: 4313 orrs r3, r2
- 8001fd6: 61bb str r3, [r7, #24]
- GPIOx->AFR[position >> 3] = temp;
- 8001fd8: 69fb ldr r3, [r7, #28]
- 8001fda: 08da lsrs r2, r3, #3
- 8001fdc: 687b ldr r3, [r7, #4]
- 8001fde: 3208 adds r2, #8
- 8001fe0: 69b9 ldr r1, [r7, #24]
- 8001fe2: f843 1022 str.w r1, [r3, r2, lsl #2]
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- 8001fe6: 687b ldr r3, [r7, #4]
- 8001fe8: 681b ldr r3, [r3, #0]
- 8001fea: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 8001fec: 69fb ldr r3, [r7, #28]
- 8001fee: 005b lsls r3, r3, #1
- 8001ff0: 2203 movs r2, #3
- 8001ff2: fa02 f303 lsl.w r3, r2, r3
- 8001ff6: 43db mvns r3, r3
- 8001ff8: 69ba ldr r2, [r7, #24]
- 8001ffa: 4013 ands r3, r2
- 8001ffc: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 8001ffe: 683b ldr r3, [r7, #0]
- 8002000: 685b ldr r3, [r3, #4]
- 8002002: f003 0203 and.w r2, r3, #3
- 8002006: 69fb ldr r3, [r7, #28]
- 8002008: 005b lsls r3, r3, #1
- 800200a: fa02 f303 lsl.w r3, r2, r3
- 800200e: 69ba ldr r2, [r7, #24]
- 8002010: 4313 orrs r3, r2
- 8002012: 61bb str r3, [r7, #24]
- GPIOx->MODER = temp;
- 8002014: 687b ldr r3, [r7, #4]
- 8002016: 69ba ldr r2, [r7, #24]
- 8002018: 601a str r2, [r3, #0]
-
- /* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 800201a: 683b ldr r3, [r7, #0]
- 800201c: 685b ldr r3, [r3, #4]
- 800201e: 2b01 cmp r3, #1
- 8002020: d00b beq.n 800203a <HAL_GPIO_Init+0xea>
- 8002022: 683b ldr r3, [r7, #0]
- 8002024: 685b ldr r3, [r3, #4]
- 8002026: 2b02 cmp r3, #2
- 8002028: d007 beq.n 800203a <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 800202a: 683b ldr r3, [r7, #0]
- 800202c: 685b ldr r3, [r3, #4]
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 800202e: 2b11 cmp r3, #17
- 8002030: d003 beq.n 800203a <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8002032: 683b ldr r3, [r7, #0]
- 8002034: 685b ldr r3, [r3, #4]
- 8002036: 2b12 cmp r3, #18
- 8002038: d130 bne.n 800209c <HAL_GPIO_Init+0x14c>
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- 800203a: 687b ldr r3, [r7, #4]
- 800203c: 689b ldr r3, [r3, #8]
- 800203e: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8002040: 69fb ldr r3, [r7, #28]
- 8002042: 005b lsls r3, r3, #1
- 8002044: 2203 movs r2, #3
- 8002046: fa02 f303 lsl.w r3, r2, r3
- 800204a: 43db mvns r3, r3
- 800204c: 69ba ldr r2, [r7, #24]
- 800204e: 4013 ands r3, r2
- 8002050: 61bb str r3, [r7, #24]
- temp |= (GPIO_Init->Speed << (position * 2));
- 8002052: 683b ldr r3, [r7, #0]
- 8002054: 68da ldr r2, [r3, #12]
- 8002056: 69fb ldr r3, [r7, #28]
- 8002058: 005b lsls r3, r3, #1
- 800205a: fa02 f303 lsl.w r3, r2, r3
- 800205e: 69ba ldr r2, [r7, #24]
- 8002060: 4313 orrs r3, r2
- 8002062: 61bb str r3, [r7, #24]
- GPIOx->OSPEEDR = temp;
- 8002064: 687b ldr r3, [r7, #4]
- 8002066: 69ba ldr r2, [r7, #24]
- 8002068: 609a str r2, [r3, #8]
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- 800206a: 687b ldr r3, [r7, #4]
- 800206c: 685b ldr r3, [r3, #4]
- 800206e: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8002070: 2201 movs r2, #1
- 8002072: 69fb ldr r3, [r7, #28]
- 8002074: fa02 f303 lsl.w r3, r2, r3
- 8002078: 43db mvns r3, r3
- 800207a: 69ba ldr r2, [r7, #24]
- 800207c: 4013 ands r3, r2
- 800207e: 61bb str r3, [r7, #24]
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 8002080: 683b ldr r3, [r7, #0]
- 8002082: 685b ldr r3, [r3, #4]
- 8002084: 091b lsrs r3, r3, #4
- 8002086: f003 0201 and.w r2, r3, #1
- 800208a: 69fb ldr r3, [r7, #28]
- 800208c: fa02 f303 lsl.w r3, r2, r3
- 8002090: 69ba ldr r2, [r7, #24]
- 8002092: 4313 orrs r3, r2
- 8002094: 61bb str r3, [r7, #24]
- GPIOx->OTYPER = temp;
- 8002096: 687b ldr r3, [r7, #4]
- 8002098: 69ba ldr r2, [r7, #24]
- 800209a: 605a str r2, [r3, #4]
- }
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- 800209c: 687b ldr r3, [r7, #4]
- 800209e: 68db ldr r3, [r3, #12]
- 80020a0: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 80020a2: 69fb ldr r3, [r7, #28]
- 80020a4: 005b lsls r3, r3, #1
- 80020a6: 2203 movs r2, #3
- 80020a8: fa02 f303 lsl.w r3, r2, r3
- 80020ac: 43db mvns r3, r3
- 80020ae: 69ba ldr r2, [r7, #24]
- 80020b0: 4013 ands r3, r2
- 80020b2: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Pull) << (position * 2));
- 80020b4: 683b ldr r3, [r7, #0]
- 80020b6: 689a ldr r2, [r3, #8]
- 80020b8: 69fb ldr r3, [r7, #28]
- 80020ba: 005b lsls r3, r3, #1
- 80020bc: fa02 f303 lsl.w r3, r2, r3
- 80020c0: 69ba ldr r2, [r7, #24]
- 80020c2: 4313 orrs r3, r2
- 80020c4: 61bb str r3, [r7, #24]
- GPIOx->PUPDR = temp;
- 80020c6: 687b ldr r3, [r7, #4]
- 80020c8: 69ba ldr r2, [r7, #24]
- 80020ca: 60da str r2, [r3, #12]
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 80020cc: 683b ldr r3, [r7, #0]
- 80020ce: 685b ldr r3, [r3, #4]
- 80020d0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80020d4: 2b00 cmp r3, #0
- 80020d6: f000 80be beq.w 8002256 <HAL_GPIO_Init+0x306>
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80020da: 4b65 ldr r3, [pc, #404] ; (8002270 <HAL_GPIO_Init+0x320>)
- 80020dc: 6c5b ldr r3, [r3, #68] ; 0x44
- 80020de: 4a64 ldr r2, [pc, #400] ; (8002270 <HAL_GPIO_Init+0x320>)
- 80020e0: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 80020e4: 6453 str r3, [r2, #68] ; 0x44
- 80020e6: 4b62 ldr r3, [pc, #392] ; (8002270 <HAL_GPIO_Init+0x320>)
- 80020e8: 6c5b ldr r3, [r3, #68] ; 0x44
- 80020ea: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 80020ee: 60fb str r3, [r7, #12]
- 80020f0: 68fb ldr r3, [r7, #12]
-
- temp = SYSCFG->EXTICR[position >> 2];
- 80020f2: 4a60 ldr r2, [pc, #384] ; (8002274 <HAL_GPIO_Init+0x324>)
- 80020f4: 69fb ldr r3, [r7, #28]
- 80020f6: 089b lsrs r3, r3, #2
- 80020f8: 3302 adds r3, #2
- 80020fa: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 80020fe: 61bb str r3, [r7, #24]
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 8002100: 69fb ldr r3, [r7, #28]
- 8002102: f003 0303 and.w r3, r3, #3
- 8002106: 009b lsls r3, r3, #2
- 8002108: 220f movs r2, #15
- 800210a: fa02 f303 lsl.w r3, r2, r3
- 800210e: 43db mvns r3, r3
- 8002110: 69ba ldr r2, [r7, #24]
- 8002112: 4013 ands r3, r2
- 8002114: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 8002116: 687b ldr r3, [r7, #4]
- 8002118: 4a57 ldr r2, [pc, #348] ; (8002278 <HAL_GPIO_Init+0x328>)
- 800211a: 4293 cmp r3, r2
- 800211c: d037 beq.n 800218e <HAL_GPIO_Init+0x23e>
- 800211e: 687b ldr r3, [r7, #4]
- 8002120: 4a56 ldr r2, [pc, #344] ; (800227c <HAL_GPIO_Init+0x32c>)
- 8002122: 4293 cmp r3, r2
- 8002124: d031 beq.n 800218a <HAL_GPIO_Init+0x23a>
- 8002126: 687b ldr r3, [r7, #4]
- 8002128: 4a55 ldr r2, [pc, #340] ; (8002280 <HAL_GPIO_Init+0x330>)
- 800212a: 4293 cmp r3, r2
- 800212c: d02b beq.n 8002186 <HAL_GPIO_Init+0x236>
- 800212e: 687b ldr r3, [r7, #4]
- 8002130: 4a54 ldr r2, [pc, #336] ; (8002284 <HAL_GPIO_Init+0x334>)
- 8002132: 4293 cmp r3, r2
- 8002134: d025 beq.n 8002182 <HAL_GPIO_Init+0x232>
- 8002136: 687b ldr r3, [r7, #4]
- 8002138: 4a53 ldr r2, [pc, #332] ; (8002288 <HAL_GPIO_Init+0x338>)
- 800213a: 4293 cmp r3, r2
- 800213c: d01f beq.n 800217e <HAL_GPIO_Init+0x22e>
- 800213e: 687b ldr r3, [r7, #4]
- 8002140: 4a52 ldr r2, [pc, #328] ; (800228c <HAL_GPIO_Init+0x33c>)
- 8002142: 4293 cmp r3, r2
- 8002144: d019 beq.n 800217a <HAL_GPIO_Init+0x22a>
- 8002146: 687b ldr r3, [r7, #4]
- 8002148: 4a51 ldr r2, [pc, #324] ; (8002290 <HAL_GPIO_Init+0x340>)
- 800214a: 4293 cmp r3, r2
- 800214c: d013 beq.n 8002176 <HAL_GPIO_Init+0x226>
- 800214e: 687b ldr r3, [r7, #4]
- 8002150: 4a50 ldr r2, [pc, #320] ; (8002294 <HAL_GPIO_Init+0x344>)
- 8002152: 4293 cmp r3, r2
- 8002154: d00d beq.n 8002172 <HAL_GPIO_Init+0x222>
- 8002156: 687b ldr r3, [r7, #4]
- 8002158: 4a4f ldr r2, [pc, #316] ; (8002298 <HAL_GPIO_Init+0x348>)
- 800215a: 4293 cmp r3, r2
- 800215c: d007 beq.n 800216e <HAL_GPIO_Init+0x21e>
- 800215e: 687b ldr r3, [r7, #4]
- 8002160: 4a4e ldr r2, [pc, #312] ; (800229c <HAL_GPIO_Init+0x34c>)
- 8002162: 4293 cmp r3, r2
- 8002164: d101 bne.n 800216a <HAL_GPIO_Init+0x21a>
- 8002166: 2309 movs r3, #9
- 8002168: e012 b.n 8002190 <HAL_GPIO_Init+0x240>
- 800216a: 230a movs r3, #10
- 800216c: e010 b.n 8002190 <HAL_GPIO_Init+0x240>
- 800216e: 2308 movs r3, #8
- 8002170: e00e b.n 8002190 <HAL_GPIO_Init+0x240>
- 8002172: 2307 movs r3, #7
- 8002174: e00c b.n 8002190 <HAL_GPIO_Init+0x240>
- 8002176: 2306 movs r3, #6
- 8002178: e00a b.n 8002190 <HAL_GPIO_Init+0x240>
- 800217a: 2305 movs r3, #5
- 800217c: e008 b.n 8002190 <HAL_GPIO_Init+0x240>
- 800217e: 2304 movs r3, #4
- 8002180: e006 b.n 8002190 <HAL_GPIO_Init+0x240>
- 8002182: 2303 movs r3, #3
- 8002184: e004 b.n 8002190 <HAL_GPIO_Init+0x240>
- 8002186: 2302 movs r3, #2
- 8002188: e002 b.n 8002190 <HAL_GPIO_Init+0x240>
- 800218a: 2301 movs r3, #1
- 800218c: e000 b.n 8002190 <HAL_GPIO_Init+0x240>
- 800218e: 2300 movs r3, #0
- 8002190: 69fa ldr r2, [r7, #28]
- 8002192: f002 0203 and.w r2, r2, #3
- 8002196: 0092 lsls r2, r2, #2
- 8002198: 4093 lsls r3, r2
- 800219a: 69ba ldr r2, [r7, #24]
- 800219c: 4313 orrs r3, r2
- 800219e: 61bb str r3, [r7, #24]
- SYSCFG->EXTICR[position >> 2] = temp;
- 80021a0: 4934 ldr r1, [pc, #208] ; (8002274 <HAL_GPIO_Init+0x324>)
- 80021a2: 69fb ldr r3, [r7, #28]
- 80021a4: 089b lsrs r3, r3, #2
- 80021a6: 3302 adds r3, #2
- 80021a8: 69ba ldr r2, [r7, #24]
- 80021aa: f841 2023 str.w r2, [r1, r3, lsl #2]
-
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- 80021ae: 4b3c ldr r3, [pc, #240] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 80021b0: 681b ldr r3, [r3, #0]
- 80021b2: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80021b4: 693b ldr r3, [r7, #16]
- 80021b6: 43db mvns r3, r3
- 80021b8: 69ba ldr r2, [r7, #24]
- 80021ba: 4013 ands r3, r2
- 80021bc: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 80021be: 683b ldr r3, [r7, #0]
- 80021c0: 685b ldr r3, [r3, #4]
- 80021c2: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 80021c6: 2b00 cmp r3, #0
- 80021c8: d003 beq.n 80021d2 <HAL_GPIO_Init+0x282>
- {
- temp |= iocurrent;
- 80021ca: 69ba ldr r2, [r7, #24]
- 80021cc: 693b ldr r3, [r7, #16]
- 80021ce: 4313 orrs r3, r2
- 80021d0: 61bb str r3, [r7, #24]
- }
- EXTI->IMR = temp;
- 80021d2: 4a33 ldr r2, [pc, #204] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 80021d4: 69bb ldr r3, [r7, #24]
- 80021d6: 6013 str r3, [r2, #0]
-
- temp = EXTI->EMR;
- 80021d8: 4b31 ldr r3, [pc, #196] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 80021da: 685b ldr r3, [r3, #4]
- 80021dc: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80021de: 693b ldr r3, [r7, #16]
- 80021e0: 43db mvns r3, r3
- 80021e2: 69ba ldr r2, [r7, #24]
- 80021e4: 4013 ands r3, r2
- 80021e6: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 80021e8: 683b ldr r3, [r7, #0]
- 80021ea: 685b ldr r3, [r3, #4]
- 80021ec: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80021f0: 2b00 cmp r3, #0
- 80021f2: d003 beq.n 80021fc <HAL_GPIO_Init+0x2ac>
- {
- temp |= iocurrent;
- 80021f4: 69ba ldr r2, [r7, #24]
- 80021f6: 693b ldr r3, [r7, #16]
- 80021f8: 4313 orrs r3, r2
- 80021fa: 61bb str r3, [r7, #24]
- }
- EXTI->EMR = temp;
- 80021fc: 4a28 ldr r2, [pc, #160] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 80021fe: 69bb ldr r3, [r7, #24]
- 8002200: 6053 str r3, [r2, #4]
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR;
- 8002202: 4b27 ldr r3, [pc, #156] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 8002204: 689b ldr r3, [r3, #8]
- 8002206: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8002208: 693b ldr r3, [r7, #16]
- 800220a: 43db mvns r3, r3
- 800220c: 69ba ldr r2, [r7, #24]
- 800220e: 4013 ands r3, r2
- 8002210: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 8002212: 683b ldr r3, [r7, #0]
- 8002214: 685b ldr r3, [r3, #4]
- 8002216: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 800221a: 2b00 cmp r3, #0
- 800221c: d003 beq.n 8002226 <HAL_GPIO_Init+0x2d6>
- {
- temp |= iocurrent;
- 800221e: 69ba ldr r2, [r7, #24]
- 8002220: 693b ldr r3, [r7, #16]
- 8002222: 4313 orrs r3, r2
- 8002224: 61bb str r3, [r7, #24]
- }
- EXTI->RTSR = temp;
- 8002226: 4a1e ldr r2, [pc, #120] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 8002228: 69bb ldr r3, [r7, #24]
- 800222a: 6093 str r3, [r2, #8]
-
- temp = EXTI->FTSR;
- 800222c: 4b1c ldr r3, [pc, #112] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 800222e: 68db ldr r3, [r3, #12]
- 8002230: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8002232: 693b ldr r3, [r7, #16]
- 8002234: 43db mvns r3, r3
- 8002236: 69ba ldr r2, [r7, #24]
- 8002238: 4013 ands r3, r2
- 800223a: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 800223c: 683b ldr r3, [r7, #0]
- 800223e: 685b ldr r3, [r3, #4]
- 8002240: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8002244: 2b00 cmp r3, #0
- 8002246: d003 beq.n 8002250 <HAL_GPIO_Init+0x300>
- {
- temp |= iocurrent;
- 8002248: 69ba ldr r2, [r7, #24]
- 800224a: 693b ldr r3, [r7, #16]
- 800224c: 4313 orrs r3, r2
- 800224e: 61bb str r3, [r7, #24]
- }
- EXTI->FTSR = temp;
- 8002250: 4a13 ldr r2, [pc, #76] ; (80022a0 <HAL_GPIO_Init+0x350>)
- 8002252: 69bb ldr r3, [r7, #24]
- 8002254: 60d3 str r3, [r2, #12]
- for(position = 0; position < GPIO_NUMBER; position++)
- 8002256: 69fb ldr r3, [r7, #28]
- 8002258: 3301 adds r3, #1
- 800225a: 61fb str r3, [r7, #28]
- 800225c: 69fb ldr r3, [r7, #28]
- 800225e: 2b0f cmp r3, #15
- 8002260: f67f ae86 bls.w 8001f70 <HAL_GPIO_Init+0x20>
- }
- }
- }
-}
- 8002264: bf00 nop
- 8002266: 3724 adds r7, #36 ; 0x24
- 8002268: 46bd mov sp, r7
- 800226a: f85d 7b04 ldr.w r7, [sp], #4
- 800226e: 4770 bx lr
- 8002270: 40023800 .word 0x40023800
- 8002274: 40013800 .word 0x40013800
- 8002278: 40020000 .word 0x40020000
- 800227c: 40020400 .word 0x40020400
- 8002280: 40020800 .word 0x40020800
- 8002284: 40020c00 .word 0x40020c00
- 8002288: 40021000 .word 0x40021000
- 800228c: 40021400 .word 0x40021400
- 8002290: 40021800 .word 0x40021800
- 8002294: 40021c00 .word 0x40021c00
- 8002298: 40022000 .word 0x40022000
- 800229c: 40022400 .word 0x40022400
- 80022a0: 40013c00 .word 0x40013c00
-
-080022a4 <HAL_GPIO_WritePin>:
- * @arg GPIO_PIN_RESET: to clear the port pin
- * @arg GPIO_PIN_SET: to set the port pin
- * @retval None
- */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- 80022a4: b480 push {r7}
- 80022a6: b083 sub sp, #12
- 80022a8: af00 add r7, sp, #0
- 80022aa: 6078 str r0, [r7, #4]
- 80022ac: 460b mov r3, r1
- 80022ae: 807b strh r3, [r7, #2]
- 80022b0: 4613 mov r3, r2
- 80022b2: 707b strb r3, [r7, #1]
- /* Check the parameters */
- assert_param(IS_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_PIN_ACTION(PinState));
-
- if(PinState != GPIO_PIN_RESET)
- 80022b4: 787b ldrb r3, [r7, #1]
- 80022b6: 2b00 cmp r3, #0
- 80022b8: d003 beq.n 80022c2 <HAL_GPIO_WritePin+0x1e>
- {
- GPIOx->BSRR = GPIO_Pin;
- 80022ba: 887a ldrh r2, [r7, #2]
- 80022bc: 687b ldr r3, [r7, #4]
- 80022be: 619a str r2, [r3, #24]
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- }
-}
- 80022c0: e003 b.n 80022ca <HAL_GPIO_WritePin+0x26>
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- 80022c2: 887b ldrh r3, [r7, #2]
- 80022c4: 041a lsls r2, r3, #16
- 80022c6: 687b ldr r3, [r7, #4]
- 80022c8: 619a str r2, [r3, #24]
-}
- 80022ca: bf00 nop
- 80022cc: 370c adds r7, #12
- 80022ce: 46bd mov sp, r7
- 80022d0: f85d 7b04 ldr.w r7, [sp], #4
- 80022d4: 4770 bx lr
- ...
-
-080022d8 <HAL_GPIO_EXTI_IRQHandler>:
- * @brief This function handles EXTI interrupt request.
- * @param GPIO_Pin Specifies the pins connected EXTI line
- * @retval None
- */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- 80022d8: b580 push {r7, lr}
- 80022da: b082 sub sp, #8
- 80022dc: af00 add r7, sp, #0
- 80022de: 4603 mov r3, r0
- 80022e0: 80fb strh r3, [r7, #6]
- /* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- 80022e2: 4b08 ldr r3, [pc, #32] ; (8002304 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80022e4: 695a ldr r2, [r3, #20]
- 80022e6: 88fb ldrh r3, [r7, #6]
- 80022e8: 4013 ands r3, r2
- 80022ea: 2b00 cmp r3, #0
- 80022ec: d006 beq.n 80022fc <HAL_GPIO_EXTI_IRQHandler+0x24>
- {
- __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- 80022ee: 4a05 ldr r2, [pc, #20] ; (8002304 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 80022f0: 88fb ldrh r3, [r7, #6]
- 80022f2: 6153 str r3, [r2, #20]
- HAL_GPIO_EXTI_Callback(GPIO_Pin);
- 80022f4: 88fb ldrh r3, [r7, #6]
- 80022f6: 4618 mov r0, r3
- 80022f8: f7ff f97e bl 80015f8 <HAL_GPIO_EXTI_Callback>
- }
-}
- 80022fc: bf00 nop
- 80022fe: 3708 adds r7, #8
- 8002300: 46bd mov sp, r7
- 8002302: bd80 pop {r7, pc}
- 8002304: 40013c00 .word 0x40013c00
-
-08002308 <HAL_RCC_OscConfig>:
- * supported by this function. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- 8002308: b580 push {r7, lr}
- 800230a: b086 sub sp, #24
- 800230c: af00 add r7, sp, #0
- 800230e: 6078 str r0, [r7, #4]
- uint32_t tickstart;
- FlagStatus pwrclkchanged = RESET;
- 8002310: 2300 movs r3, #0
- 8002312: 75fb strb r3, [r7, #23]
-
- /* Check Null pointer */
- if(RCC_OscInitStruct == NULL)
- 8002314: 687b ldr r3, [r7, #4]
- 8002316: 2b00 cmp r3, #0
- 8002318: d101 bne.n 800231e <HAL_RCC_OscConfig+0x16>
- {
- return HAL_ERROR;
- 800231a: 2301 movs r3, #1
- 800231c: e25e b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 800231e: 687b ldr r3, [r7, #4]
- 8002320: 681b ldr r3, [r3, #0]
- 8002322: f003 0301 and.w r3, r3, #1
- 8002326: 2b00 cmp r3, #0
- 8002328: f000 8087 beq.w 800243a <HAL_RCC_OscConfig+0x132>
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 800232c: 4b96 ldr r3, [pc, #600] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 800232e: 689b ldr r3, [r3, #8]
- 8002330: f003 030c and.w r3, r3, #12
- 8002334: 2b04 cmp r3, #4
- 8002336: d00c beq.n 8002352 <HAL_RCC_OscConfig+0x4a>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 8002338: 4b93 ldr r3, [pc, #588] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 800233a: 689b ldr r3, [r3, #8]
- 800233c: f003 030c and.w r3, r3, #12
- 8002340: 2b08 cmp r3, #8
- 8002342: d112 bne.n 800236a <HAL_RCC_OscConfig+0x62>
- 8002344: 4b90 ldr r3, [pc, #576] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002346: 685b ldr r3, [r3, #4]
- 8002348: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800234c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002350: d10b bne.n 800236a <HAL_RCC_OscConfig+0x62>
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8002352: 4b8d ldr r3, [pc, #564] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002354: 681b ldr r3, [r3, #0]
- 8002356: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800235a: 2b00 cmp r3, #0
- 800235c: d06c beq.n 8002438 <HAL_RCC_OscConfig+0x130>
- 800235e: 687b ldr r3, [r7, #4]
- 8002360: 685b ldr r3, [r3, #4]
- 8002362: 2b00 cmp r3, #0
- 8002364: d168 bne.n 8002438 <HAL_RCC_OscConfig+0x130>
- {
- return HAL_ERROR;
- 8002366: 2301 movs r3, #1
- 8002368: e238 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 800236a: 687b ldr r3, [r7, #4]
- 800236c: 685b ldr r3, [r3, #4]
- 800236e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8002372: d106 bne.n 8002382 <HAL_RCC_OscConfig+0x7a>
- 8002374: 4b84 ldr r3, [pc, #528] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002376: 681b ldr r3, [r3, #0]
- 8002378: 4a83 ldr r2, [pc, #524] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 800237a: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 800237e: 6013 str r3, [r2, #0]
- 8002380: e02e b.n 80023e0 <HAL_RCC_OscConfig+0xd8>
- 8002382: 687b ldr r3, [r7, #4]
- 8002384: 685b ldr r3, [r3, #4]
- 8002386: 2b00 cmp r3, #0
- 8002388: d10c bne.n 80023a4 <HAL_RCC_OscConfig+0x9c>
- 800238a: 4b7f ldr r3, [pc, #508] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 800238c: 681b ldr r3, [r3, #0]
- 800238e: 4a7e ldr r2, [pc, #504] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002390: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002394: 6013 str r3, [r2, #0]
- 8002396: 4b7c ldr r3, [pc, #496] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002398: 681b ldr r3, [r3, #0]
- 800239a: 4a7b ldr r2, [pc, #492] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 800239c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80023a0: 6013 str r3, [r2, #0]
- 80023a2: e01d b.n 80023e0 <HAL_RCC_OscConfig+0xd8>
- 80023a4: 687b ldr r3, [r7, #4]
- 80023a6: 685b ldr r3, [r3, #4]
- 80023a8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 80023ac: d10c bne.n 80023c8 <HAL_RCC_OscConfig+0xc0>
- 80023ae: 4b76 ldr r3, [pc, #472] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023b0: 681b ldr r3, [r3, #0]
- 80023b2: 4a75 ldr r2, [pc, #468] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023b4: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 80023b8: 6013 str r3, [r2, #0]
- 80023ba: 4b73 ldr r3, [pc, #460] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023bc: 681b ldr r3, [r3, #0]
- 80023be: 4a72 ldr r2, [pc, #456] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023c0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 80023c4: 6013 str r3, [r2, #0]
- 80023c6: e00b b.n 80023e0 <HAL_RCC_OscConfig+0xd8>
- 80023c8: 4b6f ldr r3, [pc, #444] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023ca: 681b ldr r3, [r3, #0]
- 80023cc: 4a6e ldr r2, [pc, #440] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023ce: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 80023d2: 6013 str r3, [r2, #0]
- 80023d4: 4b6c ldr r3, [pc, #432] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023d6: 681b ldr r3, [r3, #0]
- 80023d8: 4a6b ldr r2, [pc, #428] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80023da: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80023de: 6013 str r3, [r2, #0]
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 80023e0: 687b ldr r3, [r7, #4]
- 80023e2: 685b ldr r3, [r3, #4]
- 80023e4: 2b00 cmp r3, #0
- 80023e6: d013 beq.n 8002410 <HAL_RCC_OscConfig+0x108>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80023e8: f7ff fc72 bl 8001cd0 <HAL_GetTick>
- 80023ec: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80023ee: e008 b.n 8002402 <HAL_RCC_OscConfig+0xfa>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 80023f0: f7ff fc6e bl 8001cd0 <HAL_GetTick>
- 80023f4: 4602 mov r2, r0
- 80023f6: 693b ldr r3, [r7, #16]
- 80023f8: 1ad3 subs r3, r2, r3
- 80023fa: 2b64 cmp r3, #100 ; 0x64
- 80023fc: d901 bls.n 8002402 <HAL_RCC_OscConfig+0xfa>
- {
- return HAL_TIMEOUT;
- 80023fe: 2303 movs r3, #3
- 8002400: e1ec b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8002402: 4b61 ldr r3, [pc, #388] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002404: 681b ldr r3, [r3, #0]
- 8002406: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800240a: 2b00 cmp r3, #0
- 800240c: d0f0 beq.n 80023f0 <HAL_RCC_OscConfig+0xe8>
- 800240e: e014 b.n 800243a <HAL_RCC_OscConfig+0x132>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002410: f7ff fc5e bl 8001cd0 <HAL_GetTick>
- 8002414: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8002416: e008 b.n 800242a <HAL_RCC_OscConfig+0x122>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8002418: f7ff fc5a bl 8001cd0 <HAL_GetTick>
- 800241c: 4602 mov r2, r0
- 800241e: 693b ldr r3, [r7, #16]
- 8002420: 1ad3 subs r3, r2, r3
- 8002422: 2b64 cmp r3, #100 ; 0x64
- 8002424: d901 bls.n 800242a <HAL_RCC_OscConfig+0x122>
- {
- return HAL_TIMEOUT;
- 8002426: 2303 movs r3, #3
- 8002428: e1d8 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 800242a: 4b57 ldr r3, [pc, #348] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 800242c: 681b ldr r3, [r3, #0]
- 800242e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002432: 2b00 cmp r3, #0
- 8002434: d1f0 bne.n 8002418 <HAL_RCC_OscConfig+0x110>
- 8002436: e000 b.n 800243a <HAL_RCC_OscConfig+0x132>
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8002438: bf00 nop
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 800243a: 687b ldr r3, [r7, #4]
- 800243c: 681b ldr r3, [r3, #0]
- 800243e: f003 0302 and.w r3, r3, #2
- 8002442: 2b00 cmp r3, #0
- 8002444: d069 beq.n 800251a <HAL_RCC_OscConfig+0x212>
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 8002446: 4b50 ldr r3, [pc, #320] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002448: 689b ldr r3, [r3, #8]
- 800244a: f003 030c and.w r3, r3, #12
- 800244e: 2b00 cmp r3, #0
- 8002450: d00b beq.n 800246a <HAL_RCC_OscConfig+0x162>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 8002452: 4b4d ldr r3, [pc, #308] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002454: 689b ldr r3, [r3, #8]
- 8002456: f003 030c and.w r3, r3, #12
- 800245a: 2b08 cmp r3, #8
- 800245c: d11c bne.n 8002498 <HAL_RCC_OscConfig+0x190>
- 800245e: 4b4a ldr r3, [pc, #296] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002460: 685b ldr r3, [r3, #4]
- 8002462: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002466: 2b00 cmp r3, #0
- 8002468: d116 bne.n 8002498 <HAL_RCC_OscConfig+0x190>
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 800246a: 4b47 ldr r3, [pc, #284] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 800246c: 681b ldr r3, [r3, #0]
- 800246e: f003 0302 and.w r3, r3, #2
- 8002472: 2b00 cmp r3, #0
- 8002474: d005 beq.n 8002482 <HAL_RCC_OscConfig+0x17a>
- 8002476: 687b ldr r3, [r7, #4]
- 8002478: 68db ldr r3, [r3, #12]
- 800247a: 2b01 cmp r3, #1
- 800247c: d001 beq.n 8002482 <HAL_RCC_OscConfig+0x17a>
- {
- return HAL_ERROR;
- 800247e: 2301 movs r3, #1
- 8002480: e1ac b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8002482: 4b41 ldr r3, [pc, #260] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002484: 681b ldr r3, [r3, #0]
- 8002486: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 800248a: 687b ldr r3, [r7, #4]
- 800248c: 691b ldr r3, [r3, #16]
- 800248e: 00db lsls r3, r3, #3
- 8002490: 493d ldr r1, [pc, #244] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002492: 4313 orrs r3, r2
- 8002494: 600b str r3, [r1, #0]
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8002496: e040 b.n 800251a <HAL_RCC_OscConfig+0x212>
- }
- }
- else
- {
- /* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 8002498: 687b ldr r3, [r7, #4]
- 800249a: 68db ldr r3, [r3, #12]
- 800249c: 2b00 cmp r3, #0
- 800249e: d023 beq.n 80024e8 <HAL_RCC_OscConfig+0x1e0>
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
- 80024a0: 4b39 ldr r3, [pc, #228] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80024a2: 681b ldr r3, [r3, #0]
- 80024a4: 4a38 ldr r2, [pc, #224] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80024a6: f043 0301 orr.w r3, r3, #1
- 80024aa: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80024ac: f7ff fc10 bl 8001cd0 <HAL_GetTick>
- 80024b0: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80024b2: e008 b.n 80024c6 <HAL_RCC_OscConfig+0x1be>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80024b4: f7ff fc0c bl 8001cd0 <HAL_GetTick>
- 80024b8: 4602 mov r2, r0
- 80024ba: 693b ldr r3, [r7, #16]
- 80024bc: 1ad3 subs r3, r2, r3
- 80024be: 2b02 cmp r3, #2
- 80024c0: d901 bls.n 80024c6 <HAL_RCC_OscConfig+0x1be>
- {
- return HAL_TIMEOUT;
- 80024c2: 2303 movs r3, #3
- 80024c4: e18a b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80024c6: 4b30 ldr r3, [pc, #192] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80024c8: 681b ldr r3, [r3, #0]
- 80024ca: f003 0302 and.w r3, r3, #2
- 80024ce: 2b00 cmp r3, #0
- 80024d0: d0f0 beq.n 80024b4 <HAL_RCC_OscConfig+0x1ac>
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80024d2: 4b2d ldr r3, [pc, #180] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80024d4: 681b ldr r3, [r3, #0]
- 80024d6: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 80024da: 687b ldr r3, [r7, #4]
- 80024dc: 691b ldr r3, [r3, #16]
- 80024de: 00db lsls r3, r3, #3
- 80024e0: 4929 ldr r1, [pc, #164] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80024e2: 4313 orrs r3, r2
- 80024e4: 600b str r3, [r1, #0]
- 80024e6: e018 b.n 800251a <HAL_RCC_OscConfig+0x212>
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
- 80024e8: 4b27 ldr r3, [pc, #156] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80024ea: 681b ldr r3, [r3, #0]
- 80024ec: 4a26 ldr r2, [pc, #152] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 80024ee: f023 0301 bic.w r3, r3, #1
- 80024f2: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80024f4: f7ff fbec bl 8001cd0 <HAL_GetTick>
- 80024f8: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 80024fa: e008 b.n 800250e <HAL_RCC_OscConfig+0x206>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80024fc: f7ff fbe8 bl 8001cd0 <HAL_GetTick>
- 8002500: 4602 mov r2, r0
- 8002502: 693b ldr r3, [r7, #16]
- 8002504: 1ad3 subs r3, r2, r3
- 8002506: 2b02 cmp r3, #2
- 8002508: d901 bls.n 800250e <HAL_RCC_OscConfig+0x206>
- {
- return HAL_TIMEOUT;
- 800250a: 2303 movs r3, #3
- 800250c: e166 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 800250e: 4b1e ldr r3, [pc, #120] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002510: 681b ldr r3, [r3, #0]
- 8002512: f003 0302 and.w r3, r3, #2
- 8002516: 2b00 cmp r3, #0
- 8002518: d1f0 bne.n 80024fc <HAL_RCC_OscConfig+0x1f4>
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 800251a: 687b ldr r3, [r7, #4]
- 800251c: 681b ldr r3, [r3, #0]
- 800251e: f003 0308 and.w r3, r3, #8
- 8002522: 2b00 cmp r3, #0
- 8002524: d038 beq.n 8002598 <HAL_RCC_OscConfig+0x290>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 8002526: 687b ldr r3, [r7, #4]
- 8002528: 695b ldr r3, [r3, #20]
- 800252a: 2b00 cmp r3, #0
- 800252c: d019 beq.n 8002562 <HAL_RCC_OscConfig+0x25a>
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
- 800252e: 4b16 ldr r3, [pc, #88] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002530: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002532: 4a15 ldr r2, [pc, #84] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002534: f043 0301 orr.w r3, r3, #1
- 8002538: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800253a: f7ff fbc9 bl 8001cd0 <HAL_GetTick>
- 800253e: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8002540: e008 b.n 8002554 <HAL_RCC_OscConfig+0x24c>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8002542: f7ff fbc5 bl 8001cd0 <HAL_GetTick>
- 8002546: 4602 mov r2, r0
- 8002548: 693b ldr r3, [r7, #16]
- 800254a: 1ad3 subs r3, r2, r3
- 800254c: 2b02 cmp r3, #2
- 800254e: d901 bls.n 8002554 <HAL_RCC_OscConfig+0x24c>
- {
- return HAL_TIMEOUT;
- 8002550: 2303 movs r3, #3
- 8002552: e143 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8002554: 4b0c ldr r3, [pc, #48] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002556: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002558: f003 0302 and.w r3, r3, #2
- 800255c: 2b00 cmp r3, #0
- 800255e: d0f0 beq.n 8002542 <HAL_RCC_OscConfig+0x23a>
- 8002560: e01a b.n 8002598 <HAL_RCC_OscConfig+0x290>
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
- 8002562: 4b09 ldr r3, [pc, #36] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002564: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002566: 4a08 ldr r2, [pc, #32] ; (8002588 <HAL_RCC_OscConfig+0x280>)
- 8002568: f023 0301 bic.w r3, r3, #1
- 800256c: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800256e: f7ff fbaf bl 8001cd0 <HAL_GetTick>
- 8002572: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8002574: e00a b.n 800258c <HAL_RCC_OscConfig+0x284>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8002576: f7ff fbab bl 8001cd0 <HAL_GetTick>
- 800257a: 4602 mov r2, r0
- 800257c: 693b ldr r3, [r7, #16]
- 800257e: 1ad3 subs r3, r2, r3
- 8002580: 2b02 cmp r3, #2
- 8002582: d903 bls.n 800258c <HAL_RCC_OscConfig+0x284>
- {
- return HAL_TIMEOUT;
- 8002584: 2303 movs r3, #3
- 8002586: e129 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- 8002588: 40023800 .word 0x40023800
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 800258c: 4b95 ldr r3, [pc, #596] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800258e: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002590: f003 0302 and.w r3, r3, #2
- 8002594: 2b00 cmp r3, #0
- 8002596: d1ee bne.n 8002576 <HAL_RCC_OscConfig+0x26e>
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 8002598: 687b ldr r3, [r7, #4]
- 800259a: 681b ldr r3, [r3, #0]
- 800259c: f003 0304 and.w r3, r3, #4
- 80025a0: 2b00 cmp r3, #0
- 80025a2: f000 80a4 beq.w 80026ee <HAL_RCC_OscConfig+0x3e6>
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80025a6: 4b8f ldr r3, [pc, #572] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80025a8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80025aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80025ae: 2b00 cmp r3, #0
- 80025b0: d10d bne.n 80025ce <HAL_RCC_OscConfig+0x2c6>
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 80025b2: 4b8c ldr r3, [pc, #560] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80025b4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80025b6: 4a8b ldr r2, [pc, #556] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80025b8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80025bc: 6413 str r3, [r2, #64] ; 0x40
- 80025be: 4b89 ldr r3, [pc, #548] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80025c0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80025c2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80025c6: 60fb str r3, [r7, #12]
- 80025c8: 68fb ldr r3, [r7, #12]
- pwrclkchanged = SET;
- 80025ca: 2301 movs r3, #1
- 80025cc: 75fb strb r3, [r7, #23]
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80025ce: 4b86 ldr r3, [pc, #536] ; (80027e8 <HAL_RCC_OscConfig+0x4e0>)
- 80025d0: 681b ldr r3, [r3, #0]
- 80025d2: f403 7380 and.w r3, r3, #256 ; 0x100
- 80025d6: 2b00 cmp r3, #0
- 80025d8: d118 bne.n 800260c <HAL_RCC_OscConfig+0x304>
- {
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 80025da: 4b83 ldr r3, [pc, #524] ; (80027e8 <HAL_RCC_OscConfig+0x4e0>)
- 80025dc: 681b ldr r3, [r3, #0]
- 80025de: 4a82 ldr r2, [pc, #520] ; (80027e8 <HAL_RCC_OscConfig+0x4e0>)
- 80025e0: f443 7380 orr.w r3, r3, #256 ; 0x100
- 80025e4: 6013 str r3, [r2, #0]
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
- 80025e6: f7ff fb73 bl 8001cd0 <HAL_GetTick>
- 80025ea: 6138 str r0, [r7, #16]
-
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80025ec: e008 b.n 8002600 <HAL_RCC_OscConfig+0x2f8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 80025ee: f7ff fb6f bl 8001cd0 <HAL_GetTick>
- 80025f2: 4602 mov r2, r0
- 80025f4: 693b ldr r3, [r7, #16]
- 80025f6: 1ad3 subs r3, r2, r3
- 80025f8: 2b64 cmp r3, #100 ; 0x64
- 80025fa: d901 bls.n 8002600 <HAL_RCC_OscConfig+0x2f8>
- {
- return HAL_TIMEOUT;
- 80025fc: 2303 movs r3, #3
- 80025fe: e0ed b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8002600: 4b79 ldr r3, [pc, #484] ; (80027e8 <HAL_RCC_OscConfig+0x4e0>)
- 8002602: 681b ldr r3, [r3, #0]
- 8002604: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002608: 2b00 cmp r3, #0
- 800260a: d0f0 beq.n 80025ee <HAL_RCC_OscConfig+0x2e6>
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 800260c: 687b ldr r3, [r7, #4]
- 800260e: 689b ldr r3, [r3, #8]
- 8002610: 2b01 cmp r3, #1
- 8002612: d106 bne.n 8002622 <HAL_RCC_OscConfig+0x31a>
- 8002614: 4b73 ldr r3, [pc, #460] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002616: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002618: 4a72 ldr r2, [pc, #456] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800261a: f043 0301 orr.w r3, r3, #1
- 800261e: 6713 str r3, [r2, #112] ; 0x70
- 8002620: e02d b.n 800267e <HAL_RCC_OscConfig+0x376>
- 8002622: 687b ldr r3, [r7, #4]
- 8002624: 689b ldr r3, [r3, #8]
- 8002626: 2b00 cmp r3, #0
- 8002628: d10c bne.n 8002644 <HAL_RCC_OscConfig+0x33c>
- 800262a: 4b6e ldr r3, [pc, #440] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800262c: 6f1b ldr r3, [r3, #112] ; 0x70
- 800262e: 4a6d ldr r2, [pc, #436] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002630: f023 0301 bic.w r3, r3, #1
- 8002634: 6713 str r3, [r2, #112] ; 0x70
- 8002636: 4b6b ldr r3, [pc, #428] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002638: 6f1b ldr r3, [r3, #112] ; 0x70
- 800263a: 4a6a ldr r2, [pc, #424] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800263c: f023 0304 bic.w r3, r3, #4
- 8002640: 6713 str r3, [r2, #112] ; 0x70
- 8002642: e01c b.n 800267e <HAL_RCC_OscConfig+0x376>
- 8002644: 687b ldr r3, [r7, #4]
- 8002646: 689b ldr r3, [r3, #8]
- 8002648: 2b05 cmp r3, #5
- 800264a: d10c bne.n 8002666 <HAL_RCC_OscConfig+0x35e>
- 800264c: 4b65 ldr r3, [pc, #404] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800264e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002650: 4a64 ldr r2, [pc, #400] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002652: f043 0304 orr.w r3, r3, #4
- 8002656: 6713 str r3, [r2, #112] ; 0x70
- 8002658: 4b62 ldr r3, [pc, #392] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800265a: 6f1b ldr r3, [r3, #112] ; 0x70
- 800265c: 4a61 ldr r2, [pc, #388] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800265e: f043 0301 orr.w r3, r3, #1
- 8002662: 6713 str r3, [r2, #112] ; 0x70
- 8002664: e00b b.n 800267e <HAL_RCC_OscConfig+0x376>
- 8002666: 4b5f ldr r3, [pc, #380] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002668: 6f1b ldr r3, [r3, #112] ; 0x70
- 800266a: 4a5e ldr r2, [pc, #376] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800266c: f023 0301 bic.w r3, r3, #1
- 8002670: 6713 str r3, [r2, #112] ; 0x70
- 8002672: 4b5c ldr r3, [pc, #368] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002674: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002676: 4a5b ldr r2, [pc, #364] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002678: f023 0304 bic.w r3, r3, #4
- 800267c: 6713 str r3, [r2, #112] ; 0x70
- /* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 800267e: 687b ldr r3, [r7, #4]
- 8002680: 689b ldr r3, [r3, #8]
- 8002682: 2b00 cmp r3, #0
- 8002684: d015 beq.n 80026b2 <HAL_RCC_OscConfig+0x3aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002686: f7ff fb23 bl 8001cd0 <HAL_GetTick>
- 800268a: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 800268c: e00a b.n 80026a4 <HAL_RCC_OscConfig+0x39c>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 800268e: f7ff fb1f bl 8001cd0 <HAL_GetTick>
- 8002692: 4602 mov r2, r0
- 8002694: 693b ldr r3, [r7, #16]
- 8002696: 1ad3 subs r3, r2, r3
- 8002698: f241 3288 movw r2, #5000 ; 0x1388
- 800269c: 4293 cmp r3, r2
- 800269e: d901 bls.n 80026a4 <HAL_RCC_OscConfig+0x39c>
- {
- return HAL_TIMEOUT;
- 80026a0: 2303 movs r3, #3
- 80026a2: e09b b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80026a4: 4b4f ldr r3, [pc, #316] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80026a6: 6f1b ldr r3, [r3, #112] ; 0x70
- 80026a8: f003 0302 and.w r3, r3, #2
- 80026ac: 2b00 cmp r3, #0
- 80026ae: d0ee beq.n 800268e <HAL_RCC_OscConfig+0x386>
- 80026b0: e014 b.n 80026dc <HAL_RCC_OscConfig+0x3d4>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80026b2: f7ff fb0d bl 8001cd0 <HAL_GetTick>
- 80026b6: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80026b8: e00a b.n 80026d0 <HAL_RCC_OscConfig+0x3c8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80026ba: f7ff fb09 bl 8001cd0 <HAL_GetTick>
- 80026be: 4602 mov r2, r0
- 80026c0: 693b ldr r3, [r7, #16]
- 80026c2: 1ad3 subs r3, r2, r3
- 80026c4: f241 3288 movw r2, #5000 ; 0x1388
- 80026c8: 4293 cmp r3, r2
- 80026ca: d901 bls.n 80026d0 <HAL_RCC_OscConfig+0x3c8>
- {
- return HAL_TIMEOUT;
- 80026cc: 2303 movs r3, #3
- 80026ce: e085 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80026d0: 4b44 ldr r3, [pc, #272] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80026d2: 6f1b ldr r3, [r3, #112] ; 0x70
- 80026d4: f003 0302 and.w r3, r3, #2
- 80026d8: 2b00 cmp r3, #0
- 80026da: d1ee bne.n 80026ba <HAL_RCC_OscConfig+0x3b2>
- }
- }
- }
-
- /* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
- 80026dc: 7dfb ldrb r3, [r7, #23]
- 80026de: 2b01 cmp r3, #1
- 80026e0: d105 bne.n 80026ee <HAL_RCC_OscConfig+0x3e6>
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- 80026e2: 4b40 ldr r3, [pc, #256] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80026e4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80026e6: 4a3f ldr r2, [pc, #252] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80026e8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 80026ec: 6413 str r3, [r2, #64] ; 0x40
- }
- }
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 80026ee: 687b ldr r3, [r7, #4]
- 80026f0: 699b ldr r3, [r3, #24]
- 80026f2: 2b00 cmp r3, #0
- 80026f4: d071 beq.n 80027da <HAL_RCC_OscConfig+0x4d2>
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 80026f6: 4b3b ldr r3, [pc, #236] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80026f8: 689b ldr r3, [r3, #8]
- 80026fa: f003 030c and.w r3, r3, #12
- 80026fe: 2b08 cmp r3, #8
- 8002700: d069 beq.n 80027d6 <HAL_RCC_OscConfig+0x4ce>
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8002702: 687b ldr r3, [r7, #4]
- 8002704: 699b ldr r3, [r3, #24]
- 8002706: 2b02 cmp r3, #2
- 8002708: d14b bne.n 80027a2 <HAL_RCC_OscConfig+0x49a>
-#if defined (RCC_PLLCFGR_PLLR)
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-#endif
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 800270a: 4b36 ldr r3, [pc, #216] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800270c: 681b ldr r3, [r3, #0]
- 800270e: 4a35 ldr r2, [pc, #212] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002710: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002714: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002716: f7ff fadb bl 8001cd0 <HAL_GetTick>
- 800271a: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 800271c: e008 b.n 8002730 <HAL_RCC_OscConfig+0x428>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 800271e: f7ff fad7 bl 8001cd0 <HAL_GetTick>
- 8002722: 4602 mov r2, r0
- 8002724: 693b ldr r3, [r7, #16]
- 8002726: 1ad3 subs r3, r2, r3
- 8002728: 2b02 cmp r3, #2
- 800272a: d901 bls.n 8002730 <HAL_RCC_OscConfig+0x428>
- {
- return HAL_TIMEOUT;
- 800272c: 2303 movs r3, #3
- 800272e: e055 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002730: 4b2c ldr r3, [pc, #176] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002732: 681b ldr r3, [r3, #0]
- 8002734: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002738: 2b00 cmp r3, #0
- 800273a: d1f0 bne.n 800271e <HAL_RCC_OscConfig+0x416>
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
-#if defined (RCC_PLLCFGR_PLLR)
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 800273c: 687b ldr r3, [r7, #4]
- 800273e: 69da ldr r2, [r3, #28]
- 8002740: 687b ldr r3, [r7, #4]
- 8002742: 6a1b ldr r3, [r3, #32]
- 8002744: 431a orrs r2, r3
- 8002746: 687b ldr r3, [r7, #4]
- 8002748: 6a5b ldr r3, [r3, #36] ; 0x24
- 800274a: 019b lsls r3, r3, #6
- 800274c: 431a orrs r2, r3
- 800274e: 687b ldr r3, [r7, #4]
- 8002750: 6a9b ldr r3, [r3, #40] ; 0x28
- 8002752: 085b lsrs r3, r3, #1
- 8002754: 3b01 subs r3, #1
- 8002756: 041b lsls r3, r3, #16
- 8002758: 431a orrs r2, r3
- 800275a: 687b ldr r3, [r7, #4]
- 800275c: 6adb ldr r3, [r3, #44] ; 0x2c
- 800275e: 061b lsls r3, r3, #24
- 8002760: 431a orrs r2, r3
- 8002762: 687b ldr r3, [r7, #4]
- 8002764: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002766: 071b lsls r3, r3, #28
- 8002768: 491e ldr r1, [pc, #120] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 800276a: 4313 orrs r3, r2
- 800276c: 604b str r3, [r1, #4]
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
-#endif
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
- 800276e: 4b1d ldr r3, [pc, #116] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002770: 681b ldr r3, [r3, #0]
- 8002772: 4a1c ldr r2, [pc, #112] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002774: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 8002778: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800277a: f7ff faa9 bl 8001cd0 <HAL_GetTick>
- 800277e: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8002780: e008 b.n 8002794 <HAL_RCC_OscConfig+0x48c>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8002782: f7ff faa5 bl 8001cd0 <HAL_GetTick>
- 8002786: 4602 mov r2, r0
- 8002788: 693b ldr r3, [r7, #16]
- 800278a: 1ad3 subs r3, r2, r3
- 800278c: 2b02 cmp r3, #2
- 800278e: d901 bls.n 8002794 <HAL_RCC_OscConfig+0x48c>
- {
- return HAL_TIMEOUT;
- 8002790: 2303 movs r3, #3
- 8002792: e023 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8002794: 4b13 ldr r3, [pc, #76] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 8002796: 681b ldr r3, [r3, #0]
- 8002798: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 800279c: 2b00 cmp r3, #0
- 800279e: d0f0 beq.n 8002782 <HAL_RCC_OscConfig+0x47a>
- 80027a0: e01b b.n 80027da <HAL_RCC_OscConfig+0x4d2>
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 80027a2: 4b10 ldr r3, [pc, #64] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80027a4: 681b ldr r3, [r3, #0]
- 80027a6: 4a0f ldr r2, [pc, #60] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80027a8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80027ac: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80027ae: f7ff fa8f bl 8001cd0 <HAL_GetTick>
- 80027b2: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80027b4: e008 b.n 80027c8 <HAL_RCC_OscConfig+0x4c0>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80027b6: f7ff fa8b bl 8001cd0 <HAL_GetTick>
- 80027ba: 4602 mov r2, r0
- 80027bc: 693b ldr r3, [r7, #16]
- 80027be: 1ad3 subs r3, r2, r3
- 80027c0: 2b02 cmp r3, #2
- 80027c2: d901 bls.n 80027c8 <HAL_RCC_OscConfig+0x4c0>
- {
- return HAL_TIMEOUT;
- 80027c4: 2303 movs r3, #3
- 80027c6: e009 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80027c8: 4b06 ldr r3, [pc, #24] ; (80027e4 <HAL_RCC_OscConfig+0x4dc>)
- 80027ca: 681b ldr r3, [r3, #0]
- 80027cc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80027d0: 2b00 cmp r3, #0
- 80027d2: d1f0 bne.n 80027b6 <HAL_RCC_OscConfig+0x4ae>
- 80027d4: e001 b.n 80027da <HAL_RCC_OscConfig+0x4d2>
- }
- }
- }
- else
- {
- return HAL_ERROR;
- 80027d6: 2301 movs r3, #1
- 80027d8: e000 b.n 80027dc <HAL_RCC_OscConfig+0x4d4>
- }
- }
- return HAL_OK;
- 80027da: 2300 movs r3, #0
-}
- 80027dc: 4618 mov r0, r3
- 80027de: 3718 adds r7, #24
- 80027e0: 46bd mov sp, r7
- 80027e2: bd80 pop {r7, pc}
- 80027e4: 40023800 .word 0x40023800
- 80027e8: 40007000 .word 0x40007000
-
-080027ec <HAL_RCC_ClockConfig>:
- * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 80027ec: b580 push {r7, lr}
- 80027ee: b084 sub sp, #16
- 80027f0: af00 add r7, sp, #0
- 80027f2: 6078 str r0, [r7, #4]
- 80027f4: 6039 str r1, [r7, #0]
- uint32_t tickstart = 0;
- 80027f6: 2300 movs r3, #0
- 80027f8: 60fb str r3, [r7, #12]
-
- /* Check Null pointer */
- if(RCC_ClkInitStruct == NULL)
- 80027fa: 687b ldr r3, [r7, #4]
- 80027fc: 2b00 cmp r3, #0
- 80027fe: d101 bne.n 8002804 <HAL_RCC_ClockConfig+0x18>
- {
- return HAL_ERROR;
- 8002800: 2301 movs r3, #1
- 8002802: e0ce b.n 80029a2 <HAL_RCC_ClockConfig+0x1b6>
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
- /* Increasing the CPU frequency */
- if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8002804: 4b69 ldr r3, [pc, #420] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 8002806: 681b ldr r3, [r3, #0]
- 8002808: f003 030f and.w r3, r3, #15
- 800280c: 683a ldr r2, [r7, #0]
- 800280e: 429a cmp r2, r3
- 8002810: d910 bls.n 8002834 <HAL_RCC_ClockConfig+0x48>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 8002812: 4b66 ldr r3, [pc, #408] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 8002814: 681b ldr r3, [r3, #0]
- 8002816: f023 020f bic.w r2, r3, #15
- 800281a: 4964 ldr r1, [pc, #400] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 800281c: 683b ldr r3, [r7, #0]
- 800281e: 4313 orrs r3, r2
- 8002820: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002822: 4b62 ldr r3, [pc, #392] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 8002824: 681b ldr r3, [r3, #0]
- 8002826: f003 030f and.w r3, r3, #15
- 800282a: 683a ldr r2, [r7, #0]
- 800282c: 429a cmp r2, r3
- 800282e: d001 beq.n 8002834 <HAL_RCC_ClockConfig+0x48>
- {
- return HAL_ERROR;
- 8002830: 2301 movs r3, #1
- 8002832: e0b6 b.n 80029a2 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8002834: 687b ldr r3, [r7, #4]
- 8002836: 681b ldr r3, [r3, #0]
- 8002838: f003 0302 and.w r3, r3, #2
- 800283c: 2b00 cmp r3, #0
- 800283e: d020 beq.n 8002882 <HAL_RCC_ClockConfig+0x96>
- {
- /* Set the highest APBx dividers in order to ensure that we do not go through
- a non-spec phase whatever we decrease or increase HCLK. */
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002840: 687b ldr r3, [r7, #4]
- 8002842: 681b ldr r3, [r3, #0]
- 8002844: f003 0304 and.w r3, r3, #4
- 8002848: 2b00 cmp r3, #0
- 800284a: d005 beq.n 8002858 <HAL_RCC_ClockConfig+0x6c>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 800284c: 4b58 ldr r3, [pc, #352] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 800284e: 689b ldr r3, [r3, #8]
- 8002850: 4a57 ldr r2, [pc, #348] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 8002852: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 8002856: 6093 str r3, [r2, #8]
- }
-
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8002858: 687b ldr r3, [r7, #4]
- 800285a: 681b ldr r3, [r3, #0]
- 800285c: f003 0308 and.w r3, r3, #8
- 8002860: 2b00 cmp r3, #0
- 8002862: d005 beq.n 8002870 <HAL_RCC_ClockConfig+0x84>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 8002864: 4b52 ldr r3, [pc, #328] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 8002866: 689b ldr r3, [r3, #8]
- 8002868: 4a51 ldr r2, [pc, #324] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 800286a: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 800286e: 6093 str r3, [r2, #8]
- }
-
- /* Set the new HCLK clock divider */
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8002870: 4b4f ldr r3, [pc, #316] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 8002872: 689b ldr r3, [r3, #8]
- 8002874: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 8002878: 687b ldr r3, [r7, #4]
- 800287a: 689b ldr r3, [r3, #8]
- 800287c: 494c ldr r1, [pc, #304] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 800287e: 4313 orrs r3, r2
- 8002880: 608b str r3, [r1, #8]
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8002882: 687b ldr r3, [r7, #4]
- 8002884: 681b ldr r3, [r3, #0]
- 8002886: f003 0301 and.w r3, r3, #1
- 800288a: 2b00 cmp r3, #0
- 800288c: d040 beq.n 8002910 <HAL_RCC_ClockConfig+0x124>
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 800288e: 687b ldr r3, [r7, #4]
- 8002890: 685b ldr r3, [r3, #4]
- 8002892: 2b01 cmp r3, #1
- 8002894: d107 bne.n 80028a6 <HAL_RCC_ClockConfig+0xba>
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8002896: 4b46 ldr r3, [pc, #280] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 8002898: 681b ldr r3, [r3, #0]
- 800289a: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800289e: 2b00 cmp r3, #0
- 80028a0: d115 bne.n 80028ce <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80028a2: 2301 movs r3, #1
- 80028a4: e07d b.n 80029a2 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 80028a6: 687b ldr r3, [r7, #4]
- 80028a8: 685b ldr r3, [r3, #4]
- 80028aa: 2b02 cmp r3, #2
- 80028ac: d107 bne.n 80028be <HAL_RCC_ClockConfig+0xd2>
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80028ae: 4b40 ldr r3, [pc, #256] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 80028b0: 681b ldr r3, [r3, #0]
- 80028b2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80028b6: 2b00 cmp r3, #0
- 80028b8: d109 bne.n 80028ce <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80028ba: 2301 movs r3, #1
- 80028bc: e071 b.n 80029a2 <HAL_RCC_ClockConfig+0x1b6>
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80028be: 4b3c ldr r3, [pc, #240] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 80028c0: 681b ldr r3, [r3, #0]
- 80028c2: f003 0302 and.w r3, r3, #2
- 80028c6: 2b00 cmp r3, #0
- 80028c8: d101 bne.n 80028ce <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80028ca: 2301 movs r3, #1
- 80028cc: e069 b.n 80029a2 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 80028ce: 4b38 ldr r3, [pc, #224] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 80028d0: 689b ldr r3, [r3, #8]
- 80028d2: f023 0203 bic.w r2, r3, #3
- 80028d6: 687b ldr r3, [r7, #4]
- 80028d8: 685b ldr r3, [r3, #4]
- 80028da: 4935 ldr r1, [pc, #212] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 80028dc: 4313 orrs r3, r2
- 80028de: 608b str r3, [r1, #8]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80028e0: f7ff f9f6 bl 8001cd0 <HAL_GetTick>
- 80028e4: 60f8 str r0, [r7, #12]
-
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 80028e6: e00a b.n 80028fe <HAL_RCC_ClockConfig+0x112>
- {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 80028e8: f7ff f9f2 bl 8001cd0 <HAL_GetTick>
- 80028ec: 4602 mov r2, r0
- 80028ee: 68fb ldr r3, [r7, #12]
- 80028f0: 1ad3 subs r3, r2, r3
- 80028f2: f241 3288 movw r2, #5000 ; 0x1388
- 80028f6: 4293 cmp r3, r2
- 80028f8: d901 bls.n 80028fe <HAL_RCC_ClockConfig+0x112>
- {
- return HAL_TIMEOUT;
- 80028fa: 2303 movs r3, #3
- 80028fc: e051 b.n 80029a2 <HAL_RCC_ClockConfig+0x1b6>
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 80028fe: 4b2c ldr r3, [pc, #176] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 8002900: 689b ldr r3, [r3, #8]
- 8002902: f003 020c and.w r2, r3, #12
- 8002906: 687b ldr r3, [r7, #4]
- 8002908: 685b ldr r3, [r3, #4]
- 800290a: 009b lsls r3, r3, #2
- 800290c: 429a cmp r2, r3
- 800290e: d1eb bne.n 80028e8 <HAL_RCC_ClockConfig+0xfc>
- }
- }
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8002910: 4b26 ldr r3, [pc, #152] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 8002912: 681b ldr r3, [r3, #0]
- 8002914: f003 030f and.w r3, r3, #15
- 8002918: 683a ldr r2, [r7, #0]
- 800291a: 429a cmp r2, r3
- 800291c: d210 bcs.n 8002940 <HAL_RCC_ClockConfig+0x154>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 800291e: 4b23 ldr r3, [pc, #140] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 8002920: 681b ldr r3, [r3, #0]
- 8002922: f023 020f bic.w r2, r3, #15
- 8002926: 4921 ldr r1, [pc, #132] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 8002928: 683b ldr r3, [r7, #0]
- 800292a: 4313 orrs r3, r2
- 800292c: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800292e: 4b1f ldr r3, [pc, #124] ; (80029ac <HAL_RCC_ClockConfig+0x1c0>)
- 8002930: 681b ldr r3, [r3, #0]
- 8002932: f003 030f and.w r3, r3, #15
- 8002936: 683a ldr r2, [r7, #0]
- 8002938: 429a cmp r2, r3
- 800293a: d001 beq.n 8002940 <HAL_RCC_ClockConfig+0x154>
- {
- return HAL_ERROR;
- 800293c: 2301 movs r3, #1
- 800293e: e030 b.n 80029a2 <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002940: 687b ldr r3, [r7, #4]
- 8002942: 681b ldr r3, [r3, #0]
- 8002944: f003 0304 and.w r3, r3, #4
- 8002948: 2b00 cmp r3, #0
- 800294a: d008 beq.n 800295e <HAL_RCC_ClockConfig+0x172>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 800294c: 4b18 ldr r3, [pc, #96] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 800294e: 689b ldr r3, [r3, #8]
- 8002950: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 8002954: 687b ldr r3, [r7, #4]
- 8002956: 68db ldr r3, [r3, #12]
- 8002958: 4915 ldr r1, [pc, #84] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 800295a: 4313 orrs r3, r2
- 800295c: 608b str r3, [r1, #8]
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 800295e: 687b ldr r3, [r7, #4]
- 8002960: 681b ldr r3, [r3, #0]
- 8002962: f003 0308 and.w r3, r3, #8
- 8002966: 2b00 cmp r3, #0
- 8002968: d009 beq.n 800297e <HAL_RCC_ClockConfig+0x192>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 800296a: 4b11 ldr r3, [pc, #68] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 800296c: 689b ldr r3, [r3, #8]
- 800296e: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 8002972: 687b ldr r3, [r7, #4]
- 8002974: 691b ldr r3, [r3, #16]
- 8002976: 00db lsls r3, r3, #3
- 8002978: 490d ldr r1, [pc, #52] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 800297a: 4313 orrs r3, r2
- 800297c: 608b str r3, [r1, #8]
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 800297e: f000 f81d bl 80029bc <HAL_RCC_GetSysClockFreq>
- 8002982: 4601 mov r1, r0
- 8002984: 4b0a ldr r3, [pc, #40] ; (80029b0 <HAL_RCC_ClockConfig+0x1c4>)
- 8002986: 689b ldr r3, [r3, #8]
- 8002988: 091b lsrs r3, r3, #4
- 800298a: f003 030f and.w r3, r3, #15
- 800298e: 4a09 ldr r2, [pc, #36] ; (80029b4 <HAL_RCC_ClockConfig+0x1c8>)
- 8002990: 5cd3 ldrb r3, [r2, r3]
- 8002992: fa21 f303 lsr.w r3, r1, r3
- 8002996: 4a08 ldr r2, [pc, #32] ; (80029b8 <HAL_RCC_ClockConfig+0x1cc>)
- 8002998: 6013 str r3, [r2, #0]
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
- 800299a: 2000 movs r0, #0
- 800299c: f7ff f954 bl 8001c48 <HAL_InitTick>
-
- return HAL_OK;
- 80029a0: 2300 movs r3, #0
-}
- 80029a2: 4618 mov r0, r3
- 80029a4: 3710 adds r7, #16
- 80029a6: 46bd mov sp, r7
- 80029a8: bd80 pop {r7, pc}
- 80029aa: bf00 nop
- 80029ac: 40023c00 .word 0x40023c00
- 80029b0: 40023800 .word 0x40023800
- 80029b4: 080054e0 .word 0x080054e0
- 80029b8: 20000004 .word 0x20000004
-
-080029bc <HAL_RCC_GetSysClockFreq>:
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- 80029bc: b5f0 push {r4, r5, r6, r7, lr}
- 80029be: b085 sub sp, #20
- 80029c0: af00 add r7, sp, #0
- uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 80029c2: 2300 movs r3, #0
- 80029c4: 607b str r3, [r7, #4]
- 80029c6: 2300 movs r3, #0
- 80029c8: 60fb str r3, [r7, #12]
- 80029ca: 2300 movs r3, #0
- 80029cc: 603b str r3, [r7, #0]
- uint32_t sysclockfreq = 0;
- 80029ce: 2300 movs r3, #0
- 80029d0: 60bb str r3, [r7, #8]
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (RCC->CFGR & RCC_CFGR_SWS)
- 80029d2: 4b50 ldr r3, [pc, #320] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x158>)
- 80029d4: 689b ldr r3, [r3, #8]
- 80029d6: f003 030c and.w r3, r3, #12
- 80029da: 2b04 cmp r3, #4
- 80029dc: d007 beq.n 80029ee <HAL_RCC_GetSysClockFreq+0x32>
- 80029de: 2b08 cmp r3, #8
- 80029e0: d008 beq.n 80029f4 <HAL_RCC_GetSysClockFreq+0x38>
- 80029e2: 2b00 cmp r3, #0
- 80029e4: f040 808d bne.w 8002b02 <HAL_RCC_GetSysClockFreq+0x146>
- {
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- {
- sysclockfreq = HSI_VALUE;
- 80029e8: 4b4b ldr r3, [pc, #300] ; (8002b18 <HAL_RCC_GetSysClockFreq+0x15c>)
- 80029ea: 60bb str r3, [r7, #8]
- break;
- 80029ec: e08c b.n 8002b08 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- {
- sysclockfreq = HSE_VALUE;
- 80029ee: 4b4b ldr r3, [pc, #300] ; (8002b1c <HAL_RCC_GetSysClockFreq+0x160>)
- 80029f0: 60bb str r3, [r7, #8]
- break;
- 80029f2: e089 b.n 8002b08 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
- {
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP */
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 80029f4: 4b47 ldr r3, [pc, #284] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x158>)
- 80029f6: 685b ldr r3, [r3, #4]
- 80029f8: f003 033f and.w r3, r3, #63 ; 0x3f
- 80029fc: 607b str r3, [r7, #4]
- if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 80029fe: 4b45 ldr r3, [pc, #276] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002a00: 685b ldr r3, [r3, #4]
- 8002a02: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002a06: 2b00 cmp r3, #0
- 8002a08: d023 beq.n 8002a52 <HAL_RCC_GetSysClockFreq+0x96>
- {
- /* HSE used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002a0a: 4b42 ldr r3, [pc, #264] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002a0c: 685b ldr r3, [r3, #4]
- 8002a0e: 099b lsrs r3, r3, #6
- 8002a10: f04f 0400 mov.w r4, #0
- 8002a14: f240 11ff movw r1, #511 ; 0x1ff
- 8002a18: f04f 0200 mov.w r2, #0
- 8002a1c: ea03 0501 and.w r5, r3, r1
- 8002a20: ea04 0602 and.w r6, r4, r2
- 8002a24: 4a3d ldr r2, [pc, #244] ; (8002b1c <HAL_RCC_GetSysClockFreq+0x160>)
- 8002a26: fb02 f106 mul.w r1, r2, r6
- 8002a2a: 2200 movs r2, #0
- 8002a2c: fb02 f205 mul.w r2, r2, r5
- 8002a30: 440a add r2, r1
- 8002a32: 493a ldr r1, [pc, #232] ; (8002b1c <HAL_RCC_GetSysClockFreq+0x160>)
- 8002a34: fba5 0101 umull r0, r1, r5, r1
- 8002a38: 1853 adds r3, r2, r1
- 8002a3a: 4619 mov r1, r3
- 8002a3c: 687b ldr r3, [r7, #4]
- 8002a3e: f04f 0400 mov.w r4, #0
- 8002a42: 461a mov r2, r3
- 8002a44: 4623 mov r3, r4
- 8002a46: f7fd fbf7 bl 8000238 <__aeabi_uldivmod>
- 8002a4a: 4603 mov r3, r0
- 8002a4c: 460c mov r4, r1
- 8002a4e: 60fb str r3, [r7, #12]
- 8002a50: e049 b.n 8002ae6 <HAL_RCC_GetSysClockFreq+0x12a>
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002a52: 4b30 ldr r3, [pc, #192] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002a54: 685b ldr r3, [r3, #4]
- 8002a56: 099b lsrs r3, r3, #6
- 8002a58: f04f 0400 mov.w r4, #0
- 8002a5c: f240 11ff movw r1, #511 ; 0x1ff
- 8002a60: f04f 0200 mov.w r2, #0
- 8002a64: ea03 0501 and.w r5, r3, r1
- 8002a68: ea04 0602 and.w r6, r4, r2
- 8002a6c: 4629 mov r1, r5
- 8002a6e: 4632 mov r2, r6
- 8002a70: f04f 0300 mov.w r3, #0
- 8002a74: f04f 0400 mov.w r4, #0
- 8002a78: 0154 lsls r4, r2, #5
- 8002a7a: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 8002a7e: 014b lsls r3, r1, #5
- 8002a80: 4619 mov r1, r3
- 8002a82: 4622 mov r2, r4
- 8002a84: 1b49 subs r1, r1, r5
- 8002a86: eb62 0206 sbc.w r2, r2, r6
- 8002a8a: f04f 0300 mov.w r3, #0
- 8002a8e: f04f 0400 mov.w r4, #0
- 8002a92: 0194 lsls r4, r2, #6
- 8002a94: ea44 6491 orr.w r4, r4, r1, lsr #26
- 8002a98: 018b lsls r3, r1, #6
- 8002a9a: 1a5b subs r3, r3, r1
- 8002a9c: eb64 0402 sbc.w r4, r4, r2
- 8002aa0: f04f 0100 mov.w r1, #0
- 8002aa4: f04f 0200 mov.w r2, #0
- 8002aa8: 00e2 lsls r2, r4, #3
- 8002aaa: ea42 7253 orr.w r2, r2, r3, lsr #29
- 8002aae: 00d9 lsls r1, r3, #3
- 8002ab0: 460b mov r3, r1
- 8002ab2: 4614 mov r4, r2
- 8002ab4: 195b adds r3, r3, r5
- 8002ab6: eb44 0406 adc.w r4, r4, r6
- 8002aba: f04f 0100 mov.w r1, #0
- 8002abe: f04f 0200 mov.w r2, #0
- 8002ac2: 02a2 lsls r2, r4, #10
- 8002ac4: ea42 5293 orr.w r2, r2, r3, lsr #22
- 8002ac8: 0299 lsls r1, r3, #10
- 8002aca: 460b mov r3, r1
- 8002acc: 4614 mov r4, r2
- 8002ace: 4618 mov r0, r3
- 8002ad0: 4621 mov r1, r4
- 8002ad2: 687b ldr r3, [r7, #4]
- 8002ad4: f04f 0400 mov.w r4, #0
- 8002ad8: 461a mov r2, r3
- 8002ada: 4623 mov r3, r4
- 8002adc: f7fd fbac bl 8000238 <__aeabi_uldivmod>
- 8002ae0: 4603 mov r3, r0
- 8002ae2: 460c mov r4, r1
- 8002ae4: 60fb str r3, [r7, #12]
- }
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 8002ae6: 4b0b ldr r3, [pc, #44] ; (8002b14 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002ae8: 685b ldr r3, [r3, #4]
- 8002aea: 0c1b lsrs r3, r3, #16
- 8002aec: f003 0303 and.w r3, r3, #3
- 8002af0: 3301 adds r3, #1
- 8002af2: 005b lsls r3, r3, #1
- 8002af4: 603b str r3, [r7, #0]
-
- sysclockfreq = pllvco/pllp;
- 8002af6: 68fa ldr r2, [r7, #12]
- 8002af8: 683b ldr r3, [r7, #0]
- 8002afa: fbb2 f3f3 udiv r3, r2, r3
- 8002afe: 60bb str r3, [r7, #8]
- break;
- 8002b00: e002 b.n 8002b08 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- default:
- {
- sysclockfreq = HSI_VALUE;
- 8002b02: 4b05 ldr r3, [pc, #20] ; (8002b18 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8002b04: 60bb str r3, [r7, #8]
- break;
- 8002b06: bf00 nop
- }
- }
- return sysclockfreq;
- 8002b08: 68bb ldr r3, [r7, #8]
-}
- 8002b0a: 4618 mov r0, r3
- 8002b0c: 3714 adds r7, #20
- 8002b0e: 46bd mov sp, r7
- 8002b10: bdf0 pop {r4, r5, r6, r7, pc}
- 8002b12: bf00 nop
- 8002b14: 40023800 .word 0x40023800
- 8002b18: 00f42400 .word 0x00f42400
- 8002b1c: 017d7840 .word 0x017d7840
-
-08002b20 <HAL_RCC_GetHCLKFreq>:
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- 8002b20: b480 push {r7}
- 8002b22: af00 add r7, sp, #0
- return SystemCoreClock;
- 8002b24: 4b03 ldr r3, [pc, #12] ; (8002b34 <HAL_RCC_GetHCLKFreq+0x14>)
- 8002b26: 681b ldr r3, [r3, #0]
-}
- 8002b28: 4618 mov r0, r3
- 8002b2a: 46bd mov sp, r7
- 8002b2c: f85d 7b04 ldr.w r7, [sp], #4
- 8002b30: 4770 bx lr
- 8002b32: bf00 nop
- 8002b34: 20000004 .word 0x20000004
-
-08002b38 <HAL_RCC_GetPCLK1Freq>:
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- 8002b38: b580 push {r7, lr}
- 8002b3a: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 8002b3c: f7ff fff0 bl 8002b20 <HAL_RCC_GetHCLKFreq>
- 8002b40: 4601 mov r1, r0
- 8002b42: 4b05 ldr r3, [pc, #20] ; (8002b58 <HAL_RCC_GetPCLK1Freq+0x20>)
- 8002b44: 689b ldr r3, [r3, #8]
- 8002b46: 0a9b lsrs r3, r3, #10
- 8002b48: f003 0307 and.w r3, r3, #7
- 8002b4c: 4a03 ldr r2, [pc, #12] ; (8002b5c <HAL_RCC_GetPCLK1Freq+0x24>)
- 8002b4e: 5cd3 ldrb r3, [r2, r3]
- 8002b50: fa21 f303 lsr.w r3, r1, r3
-}
- 8002b54: 4618 mov r0, r3
- 8002b56: bd80 pop {r7, pc}
- 8002b58: 40023800 .word 0x40023800
- 8002b5c: 080054f0 .word 0x080054f0
-
-08002b60 <HAL_RCC_GetPCLK2Freq>:
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- 8002b60: b580 push {r7, lr}
- 8002b62: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 8002b64: f7ff ffdc bl 8002b20 <HAL_RCC_GetHCLKFreq>
- 8002b68: 4601 mov r1, r0
- 8002b6a: 4b05 ldr r3, [pc, #20] ; (8002b80 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8002b6c: 689b ldr r3, [r3, #8]
- 8002b6e: 0b5b lsrs r3, r3, #13
- 8002b70: f003 0307 and.w r3, r3, #7
- 8002b74: 4a03 ldr r2, [pc, #12] ; (8002b84 <HAL_RCC_GetPCLK2Freq+0x24>)
- 8002b76: 5cd3 ldrb r3, [r2, r3]
- 8002b78: fa21 f303 lsr.w r3, r1, r3
-}
- 8002b7c: 4618 mov r0, r3
- 8002b7e: bd80 pop {r7, pc}
- 8002b80: 40023800 .word 0x40023800
- 8002b84: 080054f0 .word 0x080054f0
-
-08002b88 <HAL_RCCEx_PeriphCLKConfig>:
- * the backup registers) are set to their reset values.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- 8002b88: b580 push {r7, lr}
- 8002b8a: b088 sub sp, #32
- 8002b8c: af00 add r7, sp, #0
- 8002b8e: 6078 str r0, [r7, #4]
- uint32_t tickstart = 0;
- 8002b90: 2300 movs r3, #0
- 8002b92: 617b str r3, [r7, #20]
- uint32_t tmpreg0 = 0;
- 8002b94: 2300 movs r3, #0
- 8002b96: 613b str r3, [r7, #16]
- uint32_t tmpreg1 = 0;
- 8002b98: 2300 movs r3, #0
- 8002b9a: 60fb str r3, [r7, #12]
- uint32_t plli2sused = 0;
- 8002b9c: 2300 movs r3, #0
- 8002b9e: 61fb str r3, [r7, #28]
- uint32_t pllsaiused = 0;
- 8002ba0: 2300 movs r3, #0
- 8002ba2: 61bb str r3, [r7, #24]
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*----------------------------------- I2S configuration ----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 8002ba4: 687b ldr r3, [r7, #4]
- 8002ba6: 681b ldr r3, [r3, #0]
- 8002ba8: f003 0301 and.w r3, r3, #1
- 8002bac: 2b00 cmp r3, #0
- 8002bae: d012 beq.n 8002bd6 <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure I2S Clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 8002bb0: 4b69 ldr r3, [pc, #420] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bb2: 689b ldr r3, [r3, #8]
- 8002bb4: 4a68 ldr r2, [pc, #416] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bb6: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
- 8002bba: 6093 str r3, [r2, #8]
- 8002bbc: 4b66 ldr r3, [pc, #408] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bbe: 689a ldr r2, [r3, #8]
- 8002bc0: 687b ldr r3, [r7, #4]
- 8002bc2: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002bc4: 4964 ldr r1, [pc, #400] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bc6: 4313 orrs r3, r2
- 8002bc8: 608b str r3, [r1, #8]
-
- /* Enable the PLLI2S when it's used as clock source for I2S */
- if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 8002bca: 687b ldr r3, [r7, #4]
- 8002bcc: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002bce: 2b00 cmp r3, #0
- 8002bd0: d101 bne.n 8002bd6 <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- plli2sused = 1;
- 8002bd2: 2301 movs r3, #1
- 8002bd4: 61fb str r3, [r7, #28]
- }
- }
-
- /*------------------------------------ SAI1 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 8002bd6: 687b ldr r3, [r7, #4]
- 8002bd8: 681b ldr r3, [r3, #0]
- 8002bda: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002bde: 2b00 cmp r3, #0
- 8002be0: d017 beq.n 8002c12 <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
- /* Configure SAI1 Clock source */
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 8002be2: 4b5d ldr r3, [pc, #372] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002be4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002be8: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002bec: 687b ldr r3, [r7, #4]
- 8002bee: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002bf0: 4959 ldr r1, [pc, #356] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002bf2: 4313 orrs r3, r2
- 8002bf4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8002bf8: 687b ldr r3, [r7, #4]
- 8002bfa: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002bfc: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8002c00: d101 bne.n 8002c06 <HAL_RCCEx_PeriphCLKConfig+0x7e>
- {
- plli2sused = 1;
- 8002c02: 2301 movs r3, #1
- 8002c04: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 8002c06: 687b ldr r3, [r7, #4]
- 8002c08: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002c0a: 2b00 cmp r3, #0
- 8002c0c: d101 bne.n 8002c12 <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- pllsaiused = 1;
- 8002c0e: 2301 movs r3, #1
- 8002c10: 61bb str r3, [r7, #24]
- }
- }
-
- /*------------------------------------ SAI2 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 8002c12: 687b ldr r3, [r7, #4]
- 8002c14: 681b ldr r3, [r3, #0]
- 8002c16: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8002c1a: 2b00 cmp r3, #0
- 8002c1c: d017 beq.n 8002c4e <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
- /* Configure SAI2 Clock source */
- __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 8002c1e: 4b4e ldr r3, [pc, #312] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002c20: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002c24: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002c28: 687b ldr r3, [r7, #4]
- 8002c2a: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002c2c: 494a ldr r1, [pc, #296] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002c2e: 4313 orrs r3, r2
- 8002c30: f8c1 308c str.w r3, [r1, #140] ; 0x8c
-
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 8002c34: 687b ldr r3, [r7, #4]
- 8002c36: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002c38: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002c3c: d101 bne.n 8002c42 <HAL_RCCEx_PeriphCLKConfig+0xba>
- {
- plli2sused = 1;
- 8002c3e: 2301 movs r3, #1
- 8002c40: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 8002c42: 687b ldr r3, [r7, #4]
- 8002c44: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002c46: 2b00 cmp r3, #0
- 8002c48: d101 bne.n 8002c4e <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- pllsaiused = 1;
- 8002c4a: 2301 movs r3, #1
- 8002c4c: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8002c4e: 687b ldr r3, [r7, #4]
- 8002c50: 681b ldr r3, [r3, #0]
- 8002c52: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8002c56: 2b00 cmp r3, #0
- 8002c58: d001 beq.n 8002c5e <HAL_RCCEx_PeriphCLKConfig+0xd6>
- {
- plli2sused = 1;
- 8002c5a: 2301 movs r3, #1
- 8002c5c: 61fb str r3, [r7, #28]
- }
-
- /*------------------------------------ RTC configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 8002c5e: 687b ldr r3, [r7, #4]
- 8002c60: 681b ldr r3, [r3, #0]
- 8002c62: f003 0320 and.w r3, r3, #32
- 8002c66: 2b00 cmp r3, #0
- 8002c68: f000 808b beq.w 8002d82 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
- {
- /* Check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 8002c6c: 4b3a ldr r3, [pc, #232] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002c6e: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002c70: 4a39 ldr r2, [pc, #228] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002c72: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8002c76: 6413 str r3, [r2, #64] ; 0x40
- 8002c78: 4b37 ldr r3, [pc, #220] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002c7a: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002c7c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002c80: 60bb str r3, [r7, #8]
- 8002c82: 68bb ldr r3, [r7, #8]
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 8002c84: 4b35 ldr r3, [pc, #212] ; (8002d5c <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002c86: 681b ldr r3, [r3, #0]
- 8002c88: 4a34 ldr r2, [pc, #208] ; (8002d5c <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002c8a: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8002c8e: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002c90: f7ff f81e bl 8001cd0 <HAL_GetTick>
- 8002c94: 6178 str r0, [r7, #20]
-
- /* Wait for Backup domain Write protection disable */
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002c96: e008 b.n 8002caa <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8002c98: f7ff f81a bl 8001cd0 <HAL_GetTick>
- 8002c9c: 4602 mov r2, r0
- 8002c9e: 697b ldr r3, [r7, #20]
- 8002ca0: 1ad3 subs r3, r2, r3
- 8002ca2: 2b64 cmp r3, #100 ; 0x64
- 8002ca4: d901 bls.n 8002caa <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- return HAL_TIMEOUT;
- 8002ca6: 2303 movs r3, #3
- 8002ca8: e38d b.n 80033c6 <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002caa: 4b2c ldr r3, [pc, #176] ; (8002d5c <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002cac: 681b ldr r3, [r3, #0]
- 8002cae: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002cb2: 2b00 cmp r3, #0
- 8002cb4: d0f0 beq.n 8002c98 <HAL_RCCEx_PeriphCLKConfig+0x110>
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8002cb6: 4b28 ldr r3, [pc, #160] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cb8: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002cba: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002cbe: 613b str r3, [r7, #16]
-
- if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8002cc0: 693b ldr r3, [r7, #16]
- 8002cc2: 2b00 cmp r3, #0
- 8002cc4: d035 beq.n 8002d32 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8002cc6: 687b ldr r3, [r7, #4]
- 8002cc8: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002cca: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002cce: 693a ldr r2, [r7, #16]
- 8002cd0: 429a cmp r2, r3
- 8002cd2: d02e beq.n 8002d32 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8002cd4: 4b20 ldr r3, [pc, #128] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cd6: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002cd8: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8002cdc: 613b str r3, [r7, #16]
-
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- 8002cde: 4b1e ldr r3, [pc, #120] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ce0: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002ce2: 4a1d ldr r2, [pc, #116] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002ce4: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002ce8: 6713 str r3, [r2, #112] ; 0x70
- __HAL_RCC_BACKUPRESET_RELEASE();
- 8002cea: 4b1b ldr r3, [pc, #108] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cec: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002cee: 4a1a ldr r2, [pc, #104] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cf0: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002cf4: 6713 str r3, [r2, #112] ; 0x70
-
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg0;
- 8002cf6: 4a18 ldr r2, [pc, #96] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cf8: 693b ldr r3, [r7, #16]
- 8002cfa: 6713 str r3, [r2, #112] ; 0x70
-
- /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
- if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8002cfc: 4b16 ldr r3, [pc, #88] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002cfe: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002d00: f003 0301 and.w r3, r3, #1
- 8002d04: 2b01 cmp r3, #1
- 8002d06: d114 bne.n 8002d32 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002d08: f7fe ffe2 bl 8001cd0 <HAL_GetTick>
- 8002d0c: 6178 str r0, [r7, #20]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002d0e: e00a b.n 8002d26 <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002d10: f7fe ffde bl 8001cd0 <HAL_GetTick>
- 8002d14: 4602 mov r2, r0
- 8002d16: 697b ldr r3, [r7, #20]
- 8002d18: 1ad3 subs r3, r2, r3
- 8002d1a: f241 3288 movw r2, #5000 ; 0x1388
- 8002d1e: 4293 cmp r3, r2
- 8002d20: d901 bls.n 8002d26 <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- return HAL_TIMEOUT;
- 8002d22: 2303 movs r3, #3
- 8002d24: e34f b.n 80033c6 <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002d26: 4b0c ldr r3, [pc, #48] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d28: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002d2a: f003 0302 and.w r3, r3, #2
- 8002d2e: 2b00 cmp r3, #0
- 8002d30: d0ee beq.n 8002d10 <HAL_RCCEx_PeriphCLKConfig+0x188>
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8002d32: 687b ldr r3, [r7, #4]
- 8002d34: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002d36: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002d3a: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8002d3e: d111 bne.n 8002d64 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8002d40: 4b05 ldr r3, [pc, #20] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d42: 689b ldr r3, [r3, #8]
- 8002d44: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
- 8002d48: 687b ldr r3, [r7, #4]
- 8002d4a: 6b19 ldr r1, [r3, #48] ; 0x30
- 8002d4c: 4b04 ldr r3, [pc, #16] ; (8002d60 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8002d4e: 400b ands r3, r1
- 8002d50: 4901 ldr r1, [pc, #4] ; (8002d58 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002d52: 4313 orrs r3, r2
- 8002d54: 608b str r3, [r1, #8]
- 8002d56: e00b b.n 8002d70 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8002d58: 40023800 .word 0x40023800
- 8002d5c: 40007000 .word 0x40007000
- 8002d60: 0ffffcff .word 0x0ffffcff
- 8002d64: 4bb3 ldr r3, [pc, #716] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d66: 689b ldr r3, [r3, #8]
- 8002d68: 4ab2 ldr r2, [pc, #712] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d6a: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
- 8002d6e: 6093 str r3, [r2, #8]
- 8002d70: 4bb0 ldr r3, [pc, #704] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d72: 6f1a ldr r2, [r3, #112] ; 0x70
- 8002d74: 687b ldr r3, [r7, #4]
- 8002d76: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002d78: f3c3 030b ubfx r3, r3, #0, #12
- 8002d7c: 49ad ldr r1, [pc, #692] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d7e: 4313 orrs r3, r2
- 8002d80: 670b str r3, [r1, #112] ; 0x70
- }
-
- /*------------------------------------ TIM configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 8002d82: 687b ldr r3, [r7, #4]
- 8002d84: 681b ldr r3, [r3, #0]
- 8002d86: f003 0310 and.w r3, r3, #16
- 8002d8a: 2b00 cmp r3, #0
- 8002d8c: d010 beq.n 8002db0 <HAL_RCCEx_PeriphCLKConfig+0x228>
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
-
- /* Configure Timer Prescaler */
- __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 8002d8e: 4ba9 ldr r3, [pc, #676] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d90: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002d94: 4aa7 ldr r2, [pc, #668] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d96: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002d9a: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 8002d9e: 4ba5 ldr r3, [pc, #660] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002da0: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
- 8002da4: 687b ldr r3, [r7, #4]
- 8002da6: 6b9b ldr r3, [r3, #56] ; 0x38
- 8002da8: 49a2 ldr r1, [pc, #648] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002daa: 4313 orrs r3, r2
- 8002dac: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*-------------------------------------- I2C1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 8002db0: 687b ldr r3, [r7, #4]
- 8002db2: 681b ldr r3, [r3, #0]
- 8002db4: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8002db8: 2b00 cmp r3, #0
- 8002dba: d00a beq.n 8002dd2 <HAL_RCCEx_PeriphCLKConfig+0x24a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8002dbc: 4b9d ldr r3, [pc, #628] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002dbe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002dc2: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8002dc6: 687b ldr r3, [r7, #4]
- 8002dc8: 6e5b ldr r3, [r3, #100] ; 0x64
- 8002dca: 499a ldr r1, [pc, #616] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002dcc: 4313 orrs r3, r2
- 8002dce: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 8002dd2: 687b ldr r3, [r7, #4]
- 8002dd4: 681b ldr r3, [r3, #0]
- 8002dd6: f403 4300 and.w r3, r3, #32768 ; 0x8000
- 8002dda: 2b00 cmp r3, #0
- 8002ddc: d00a beq.n 8002df4 <HAL_RCCEx_PeriphCLKConfig+0x26c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8002dde: 4b95 ldr r3, [pc, #596] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002de0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002de4: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
- 8002de8: 687b ldr r3, [r7, #4]
- 8002dea: 6e9b ldr r3, [r3, #104] ; 0x68
- 8002dec: 4991 ldr r1, [pc, #580] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002dee: 4313 orrs r3, r2
- 8002df0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8002df4: 687b ldr r3, [r7, #4]
- 8002df6: 681b ldr r3, [r3, #0]
- 8002df8: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8002dfc: 2b00 cmp r3, #0
- 8002dfe: d00a beq.n 8002e16 <HAL_RCCEx_PeriphCLKConfig+0x28e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8002e00: 4b8c ldr r3, [pc, #560] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e02: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e06: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002e0a: 687b ldr r3, [r7, #4]
- 8002e0c: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002e0e: 4989 ldr r1, [pc, #548] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e10: 4313 orrs r3, r2
- 8002e12: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8002e16: 687b ldr r3, [r7, #4]
- 8002e18: 681b ldr r3, [r3, #0]
- 8002e1a: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002e1e: 2b00 cmp r3, #0
- 8002e20: d00a beq.n 8002e38 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- /* Configure the I2C4 clock source */
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8002e22: 4b84 ldr r3, [pc, #528] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e24: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e28: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002e2c: 687b ldr r3, [r7, #4]
- 8002e2e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002e30: 4980 ldr r1, [pc, #512] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e32: 4313 orrs r3, r2
- 8002e34: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8002e38: 687b ldr r3, [r7, #4]
- 8002e3a: 681b ldr r3, [r3, #0]
- 8002e3c: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002e40: 2b00 cmp r3, #0
- 8002e42: d00a beq.n 8002e5a <HAL_RCCEx_PeriphCLKConfig+0x2d2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8002e44: 4b7b ldr r3, [pc, #492] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e46: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e4a: f023 0203 bic.w r2, r3, #3
- 8002e4e: 687b ldr r3, [r7, #4]
- 8002e50: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002e52: 4978 ldr r1, [pc, #480] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e54: 4313 orrs r3, r2
- 8002e56: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8002e5a: 687b ldr r3, [r7, #4]
- 8002e5c: 681b ldr r3, [r3, #0]
- 8002e5e: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002e62: 2b00 cmp r3, #0
- 8002e64: d00a beq.n 8002e7c <HAL_RCCEx_PeriphCLKConfig+0x2f4>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8002e66: 4b73 ldr r3, [pc, #460] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e68: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e6c: f023 020c bic.w r2, r3, #12
- 8002e70: 687b ldr r3, [r7, #4]
- 8002e72: 6c9b ldr r3, [r3, #72] ; 0x48
- 8002e74: 496f ldr r1, [pc, #444] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e76: 4313 orrs r3, r2
- 8002e78: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8002e7c: 687b ldr r3, [r7, #4]
- 8002e7e: 681b ldr r3, [r3, #0]
- 8002e80: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002e84: 2b00 cmp r3, #0
- 8002e86: d00a beq.n 8002e9e <HAL_RCCEx_PeriphCLKConfig+0x316>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8002e88: 4b6a ldr r3, [pc, #424] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e8a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002e8e: f023 0230 bic.w r2, r3, #48 ; 0x30
- 8002e92: 687b ldr r3, [r7, #4]
- 8002e94: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8002e96: 4967 ldr r1, [pc, #412] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002e98: 4313 orrs r3, r2
- 8002e9a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8002e9e: 687b ldr r3, [r7, #4]
- 8002ea0: 681b ldr r3, [r3, #0]
- 8002ea2: f403 7300 and.w r3, r3, #512 ; 0x200
- 8002ea6: 2b00 cmp r3, #0
- 8002ea8: d00a beq.n 8002ec0 <HAL_RCCEx_PeriphCLKConfig+0x338>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8002eaa: 4b62 ldr r3, [pc, #392] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002eac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002eb0: f023 02c0 bic.w r2, r3, #192 ; 0xc0
- 8002eb4: 687b ldr r3, [r7, #4]
- 8002eb6: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002eb8: 495e ldr r1, [pc, #376] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002eba: 4313 orrs r3, r2
- 8002ebc: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART5 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8002ec0: 687b ldr r3, [r7, #4]
- 8002ec2: 681b ldr r3, [r3, #0]
- 8002ec4: f403 6380 and.w r3, r3, #1024 ; 0x400
- 8002ec8: 2b00 cmp r3, #0
- 8002eca: d00a beq.n 8002ee2 <HAL_RCCEx_PeriphCLKConfig+0x35a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8002ecc: 4b59 ldr r3, [pc, #356] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ece: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ed2: f423 7240 bic.w r2, r3, #768 ; 0x300
- 8002ed6: 687b ldr r3, [r7, #4]
- 8002ed8: 6d5b ldr r3, [r3, #84] ; 0x54
- 8002eda: 4956 ldr r1, [pc, #344] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002edc: 4313 orrs r3, r2
- 8002ede: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART6 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8002ee2: 687b ldr r3, [r7, #4]
- 8002ee4: 681b ldr r3, [r3, #0]
- 8002ee6: f403 6300 and.w r3, r3, #2048 ; 0x800
- 8002eea: 2b00 cmp r3, #0
- 8002eec: d00a beq.n 8002f04 <HAL_RCCEx_PeriphCLKConfig+0x37c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
-
- /* Configure the USART6 clock source */
- __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8002eee: 4b51 ldr r3, [pc, #324] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ef0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ef4: f423 6240 bic.w r2, r3, #3072 ; 0xc00
- 8002ef8: 687b ldr r3, [r7, #4]
- 8002efa: 6d9b ldr r3, [r3, #88] ; 0x58
- 8002efc: 494d ldr r1, [pc, #308] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002efe: 4313 orrs r3, r2
- 8002f00: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART7 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8002f04: 687b ldr r3, [r7, #4]
- 8002f06: 681b ldr r3, [r3, #0]
- 8002f08: f403 5380 and.w r3, r3, #4096 ; 0x1000
- 8002f0c: 2b00 cmp r3, #0
- 8002f0e: d00a beq.n 8002f26 <HAL_RCCEx_PeriphCLKConfig+0x39e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
-
- /* Configure the UART7 clock source */
- __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8002f10: 4b48 ldr r3, [pc, #288] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f12: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f16: f423 5240 bic.w r2, r3, #12288 ; 0x3000
- 8002f1a: 687b ldr r3, [r7, #4]
- 8002f1c: 6ddb ldr r3, [r3, #92] ; 0x5c
- 8002f1e: 4945 ldr r1, [pc, #276] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f20: 4313 orrs r3, r2
- 8002f22: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART8 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 8002f26: 687b ldr r3, [r7, #4]
- 8002f28: 681b ldr r3, [r3, #0]
- 8002f2a: f403 5300 and.w r3, r3, #8192 ; 0x2000
- 8002f2e: 2b00 cmp r3, #0
- 8002f30: d00a beq.n 8002f48 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
-
- /* Configure the UART8 clock source */
- __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 8002f32: 4b40 ldr r3, [pc, #256] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f34: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f38: f423 4240 bic.w r2, r3, #49152 ; 0xc000
- 8002f3c: 687b ldr r3, [r7, #4]
- 8002f3e: 6e1b ldr r3, [r3, #96] ; 0x60
- 8002f40: 493c ldr r1, [pc, #240] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f42: 4313 orrs r3, r2
- 8002f44: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*--------------------------------------- CEC Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 8002f48: 687b ldr r3, [r7, #4]
- 8002f4a: 681b ldr r3, [r3, #0]
- 8002f4c: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002f50: 2b00 cmp r3, #0
- 8002f52: d00a beq.n 8002f6a <HAL_RCCEx_PeriphCLKConfig+0x3e2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 8002f54: 4b37 ldr r3, [pc, #220] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f56: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f5a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8002f5e: 687b ldr r3, [r7, #4]
- 8002f60: 6f9b ldr r3, [r3, #120] ; 0x78
- 8002f62: 4934 ldr r1, [pc, #208] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f64: 4313 orrs r3, r2
- 8002f66: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- CK48 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 8002f6a: 687b ldr r3, [r7, #4]
- 8002f6c: 681b ldr r3, [r3, #0]
- 8002f6e: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8002f72: 2b00 cmp r3, #0
- 8002f74: d011 beq.n 8002f9a <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
-
- /* Configure the CLK48 source */
- __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 8002f76: 4b2f ldr r3, [pc, #188] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f78: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002f7c: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
- 8002f80: 687b ldr r3, [r7, #4]
- 8002f82: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002f84: 492b ldr r1, [pc, #172] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002f86: 4313 orrs r3, r2
- 8002f88: f8c1 3090 str.w r3, [r1, #144] ; 0x90
-
- /* Enable the PLLSAI when it's used as clock source for CK48 */
- if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 8002f8c: 687b ldr r3, [r7, #4]
- 8002f8e: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002f90: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8002f94: d101 bne.n 8002f9a <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- pllsaiused = 1;
- 8002f96: 2301 movs r3, #1
- 8002f98: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- LTDC Configuration -----------------------------------*/
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 8002f9a: 687b ldr r3, [r7, #4]
- 8002f9c: 681b ldr r3, [r3, #0]
- 8002f9e: f003 0308 and.w r3, r3, #8
- 8002fa2: 2b00 cmp r3, #0
- 8002fa4: d001 beq.n 8002faa <HAL_RCCEx_PeriphCLKConfig+0x422>
- {
- pllsaiused = 1;
- 8002fa6: 2301 movs r3, #1
- 8002fa8: 61bb str r3, [r7, #24]
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 8002faa: 687b ldr r3, [r7, #4]
- 8002fac: 681b ldr r3, [r3, #0]
- 8002fae: f403 2380 and.w r3, r3, #262144 ; 0x40000
- 8002fb2: 2b00 cmp r3, #0
- 8002fb4: d00a beq.n 8002fcc <HAL_RCCEx_PeriphCLKConfig+0x444>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
-
- /* Configure the LTPIM1 clock source */
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 8002fb6: 4b1f ldr r3, [pc, #124] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fb8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fbc: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
- 8002fc0: 687b ldr r3, [r7, #4]
- 8002fc2: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002fc4: 491b ldr r1, [pc, #108] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fc6: 4313 orrs r3, r2
- 8002fc8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 8002fcc: 687b ldr r3, [r7, #4]
- 8002fce: 681b ldr r3, [r3, #0]
- 8002fd0: f403 0300 and.w r3, r3, #8388608 ; 0x800000
- 8002fd4: 2b00 cmp r3, #0
- 8002fd6: d00b beq.n 8002ff0 <HAL_RCCEx_PeriphCLKConfig+0x468>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
-
- /* Configure the SDMMC1 clock source */
- __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 8002fd8: 4b16 ldr r3, [pc, #88] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fda: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fde: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
- 8002fe2: 687b ldr r3, [r7, #4]
- 8002fe4: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
- 8002fe8: 4912 ldr r1, [pc, #72] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002fea: 4313 orrs r3, r2
- 8002fec: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
- /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 8002ff0: 687b ldr r3, [r7, #4]
- 8002ff2: 681b ldr r3, [r3, #0]
- 8002ff4: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
- 8002ff8: 2b00 cmp r3, #0
- 8002ffa: d00b beq.n 8003014 <HAL_RCCEx_PeriphCLKConfig+0x48c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
-
- /* Configure the SDMMC2 clock source */
- __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 8002ffc: 4b0d ldr r3, [pc, #52] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ffe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003002: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
- 8003006: 687b ldr r3, [r7, #4]
- 8003008: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 800300c: 4909 ldr r1, [pc, #36] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800300e: 4313 orrs r3, r2
- 8003010: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 8003014: 687b ldr r3, [r7, #4]
- 8003016: 681b ldr r3, [r3, #0]
- 8003018: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 800301c: 2b00 cmp r3, #0
- 800301e: d00f beq.n 8003040 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
- /* Configure the DFSDM1 interface clock source */
- __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8003020: 4b04 ldr r3, [pc, #16] ; (8003034 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8003022: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003026: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
- 800302a: 687b ldr r3, [r7, #4]
- 800302c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003030: e002 b.n 8003038 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 8003032: bf00 nop
- 8003034: 40023800 .word 0x40023800
- 8003038: 4985 ldr r1, [pc, #532] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800303a: 4313 orrs r3, r2
- 800303c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8003040: 687b ldr r3, [r7, #4]
- 8003042: 681b ldr r3, [r3, #0]
- 8003044: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8003048: 2b00 cmp r3, #0
- 800304a: d00b beq.n 8003064 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
- /* Configure the DFSDM interface clock source */
- __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 800304c: 4b80 ldr r3, [pc, #512] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800304e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003052: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8003056: 687b ldr r3, [r7, #4]
- 8003058: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800305c: 497c ldr r1, [pc, #496] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800305e: 4313 orrs r3, r2
- 8003060: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
- /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
- /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
- if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 8003064: 69fb ldr r3, [r7, #28]
- 8003066: 2b01 cmp r3, #1
- 8003068: d005 beq.n 8003076 <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 800306a: 687b ldr r3, [r7, #4]
- 800306c: 681b ldr r3, [r3, #0]
- 800306e: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 8003072: f040 80d6 bne.w 8003222 <HAL_RCCEx_PeriphCLKConfig+0x69a>
- {
- /* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
- 8003076: 4b76 ldr r3, [pc, #472] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003078: 681b ldr r3, [r3, #0]
- 800307a: 4a75 ldr r2, [pc, #468] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800307c: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
- 8003080: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8003082: f7fe fe25 bl 8001cd0 <HAL_GetTick>
- 8003086: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8003088: e008 b.n 800309c <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 800308a: f7fe fe21 bl 8001cd0 <HAL_GetTick>
- 800308e: 4602 mov r2, r0
- 8003090: 697b ldr r3, [r7, #20]
- 8003092: 1ad3 subs r3, r2, r3
- 8003094: 2b64 cmp r3, #100 ; 0x64
- 8003096: d901 bls.n 800309c <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003098: 2303 movs r3, #3
- 800309a: e194 b.n 80033c6 <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 800309c: 4b6c ldr r3, [pc, #432] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800309e: 681b ldr r3, [r3, #0]
- 80030a0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 80030a4: 2b00 cmp r3, #0
- 80030a6: d1f0 bne.n 800308a <HAL_RCCEx_PeriphCLKConfig+0x502>
-
- /* check for common PLLI2S Parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
- /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 80030a8: 687b ldr r3, [r7, #4]
- 80030aa: 681b ldr r3, [r3, #0]
- 80030ac: f003 0301 and.w r3, r3, #1
- 80030b0: 2b00 cmp r3, #0
- 80030b2: d021 beq.n 80030f8 <HAL_RCCEx_PeriphCLKConfig+0x570>
- 80030b4: 687b ldr r3, [r7, #4]
- 80030b6: 6b5b ldr r3, [r3, #52] ; 0x34
- 80030b8: 2b00 cmp r3, #0
- 80030ba: d11d bne.n 80030f8 <HAL_RCCEx_PeriphCLKConfig+0x570>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
- /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 80030bc: 4b64 ldr r3, [pc, #400] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030be: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80030c2: 0c1b lsrs r3, r3, #16
- 80030c4: f003 0303 and.w r3, r3, #3
- 80030c8: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 80030ca: 4b61 ldr r3, [pc, #388] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030cc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 80030d0: 0e1b lsrs r3, r3, #24
- 80030d2: f003 030f and.w r3, r3, #15
- 80030d6: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 80030d8: 687b ldr r3, [r7, #4]
- 80030da: 685b ldr r3, [r3, #4]
- 80030dc: 019a lsls r2, r3, #6
- 80030de: 693b ldr r3, [r7, #16]
- 80030e0: 041b lsls r3, r3, #16
- 80030e2: 431a orrs r2, r3
- 80030e4: 68fb ldr r3, [r7, #12]
- 80030e6: 061b lsls r3, r3, #24
- 80030e8: 431a orrs r2, r3
- 80030ea: 687b ldr r3, [r7, #4]
- 80030ec: 689b ldr r3, [r3, #8]
- 80030ee: 071b lsls r3, r3, #28
- 80030f0: 4957 ldr r1, [pc, #348] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80030f2: 4313 orrs r3, r2
- 80030f4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 80030f8: 687b ldr r3, [r7, #4]
- 80030fa: 681b ldr r3, [r3, #0]
- 80030fc: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8003100: 2b00 cmp r3, #0
- 8003102: d004 beq.n 800310e <HAL_RCCEx_PeriphCLKConfig+0x586>
- 8003104: 687b ldr r3, [r7, #4]
- 8003106: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8003108: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 800310c: d00a beq.n 8003124 <HAL_RCCEx_PeriphCLKConfig+0x59c>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 800310e: 687b ldr r3, [r7, #4]
- 8003110: 681b ldr r3, [r3, #0]
- 8003112: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8003116: 2b00 cmp r3, #0
- 8003118: d02e beq.n 8003178 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 800311a: 687b ldr r3, [r7, #4]
- 800311c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800311e: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8003122: d129 bne.n 8003178 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
- /* Check for PLLI2S/DIVQ parameters */
- assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
- /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8003124: 4b4a ldr r3, [pc, #296] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003126: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 800312a: 0c1b lsrs r3, r3, #16
- 800312c: f003 0303 and.w r3, r3, #3
- 8003130: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8003132: 4b47 ldr r3, [pc, #284] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003134: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003138: 0f1b lsrs r3, r3, #28
- 800313a: f003 0307 and.w r3, r3, #7
- 800313e: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
- /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
- /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8003140: 687b ldr r3, [r7, #4]
- 8003142: 685b ldr r3, [r3, #4]
- 8003144: 019a lsls r2, r3, #6
- 8003146: 693b ldr r3, [r7, #16]
- 8003148: 041b lsls r3, r3, #16
- 800314a: 431a orrs r2, r3
- 800314c: 687b ldr r3, [r7, #4]
- 800314e: 68db ldr r3, [r3, #12]
- 8003150: 061b lsls r3, r3, #24
- 8003152: 431a orrs r2, r3
- 8003154: 68fb ldr r3, [r7, #12]
- 8003156: 071b lsls r3, r3, #28
- 8003158: 493d ldr r1, [pc, #244] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800315a: 4313 orrs r3, r2
- 800315c: f8c1 3084 str.w r3, [r1, #132] ; 0x84
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8003160: 4b3b ldr r3, [pc, #236] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003162: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003166: f023 021f bic.w r2, r3, #31
- 800316a: 687b ldr r3, [r7, #4]
- 800316c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800316e: 3b01 subs r3, #1
- 8003170: 4937 ldr r1, [pc, #220] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003172: 4313 orrs r3, r2
- 8003174: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8003178: 687b ldr r3, [r7, #4]
- 800317a: 681b ldr r3, [r3, #0]
- 800317c: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8003180: 2b00 cmp r3, #0
- 8003182: d01d beq.n 80031c0 <HAL_RCCEx_PeriphCLKConfig+0x638>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-
- /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8003184: 4b32 ldr r3, [pc, #200] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003186: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 800318a: 0e1b lsrs r3, r3, #24
- 800318c: f003 030f and.w r3, r3, #15
- 8003190: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8003192: 4b2f ldr r3, [pc, #188] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003194: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8003198: 0f1b lsrs r3, r3, #28
- 800319a: f003 0307 and.w r3, r3, #7
- 800319e: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 80031a0: 687b ldr r3, [r7, #4]
- 80031a2: 685b ldr r3, [r3, #4]
- 80031a4: 019a lsls r2, r3, #6
- 80031a6: 687b ldr r3, [r7, #4]
- 80031a8: 691b ldr r3, [r3, #16]
- 80031aa: 041b lsls r3, r3, #16
- 80031ac: 431a orrs r2, r3
- 80031ae: 693b ldr r3, [r7, #16]
- 80031b0: 061b lsls r3, r3, #24
- 80031b2: 431a orrs r2, r3
- 80031b4: 68fb ldr r3, [r7, #12]
- 80031b6: 071b lsls r3, r3, #28
- 80031b8: 4925 ldr r1, [pc, #148] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031ba: 4313 orrs r3, r2
- 80031bc: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is just selected -----------------*/
- if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 80031c0: 687b ldr r3, [r7, #4]
- 80031c2: 681b ldr r3, [r3, #0]
- 80031c4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80031c8: 2b00 cmp r3, #0
- 80031ca: d011 beq.n 80031f0 <HAL_RCCEx_PeriphCLKConfig+0x668>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
- /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 80031cc: 687b ldr r3, [r7, #4]
- 80031ce: 685b ldr r3, [r3, #4]
- 80031d0: 019a lsls r2, r3, #6
- 80031d2: 687b ldr r3, [r7, #4]
- 80031d4: 691b ldr r3, [r3, #16]
- 80031d6: 041b lsls r3, r3, #16
- 80031d8: 431a orrs r2, r3
- 80031da: 687b ldr r3, [r7, #4]
- 80031dc: 68db ldr r3, [r3, #12]
- 80031de: 061b lsls r3, r3, #24
- 80031e0: 431a orrs r2, r3
- 80031e2: 687b ldr r3, [r7, #4]
- 80031e4: 689b ldr r3, [r3, #8]
- 80031e6: 071b lsls r3, r3, #28
- 80031e8: 4919 ldr r1, [pc, #100] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031ea: 4313 orrs r3, r2
- 80031ec: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /* Enable the PLLI2S */
- __HAL_RCC_PLLI2S_ENABLE();
- 80031f0: 4b17 ldr r3, [pc, #92] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031f2: 681b ldr r3, [r3, #0]
- 80031f4: 4a16 ldr r2, [pc, #88] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 80031f6: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
- 80031fa: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80031fc: f7fe fd68 bl 8001cd0 <HAL_GetTick>
- 8003200: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 8003202: e008 b.n 8003216 <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8003204: f7fe fd64 bl 8001cd0 <HAL_GetTick>
- 8003208: 4602 mov r2, r0
- 800320a: 697b ldr r3, [r7, #20]
- 800320c: 1ad3 subs r3, r2, r3
- 800320e: 2b64 cmp r3, #100 ; 0x64
- 8003210: d901 bls.n 8003216 <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8003212: 2303 movs r3, #3
- 8003214: e0d7 b.n 80033c6 <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 8003216: 4b0e ldr r3, [pc, #56] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003218: 681b ldr r3, [r3, #0]
- 800321a: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 800321e: 2b00 cmp r3, #0
- 8003220: d0f0 beq.n 8003204 <HAL_RCCEx_PeriphCLKConfig+0x67c>
- }
- }
-
- /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
- /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
- if(pllsaiused == 1)
- 8003222: 69bb ldr r3, [r7, #24]
- 8003224: 2b01 cmp r3, #1
- 8003226: f040 80cd bne.w 80033c4 <HAL_RCCEx_PeriphCLKConfig+0x83c>
- {
- /* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
- 800322a: 4b09 ldr r3, [pc, #36] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800322c: 681b ldr r3, [r3, #0]
- 800322e: 4a08 ldr r2, [pc, #32] ; (8003250 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8003230: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8003234: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8003236: f7fe fd4b bl 8001cd0 <HAL_GetTick>
- 800323a: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is disabled */
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 800323c: e00a b.n 8003254 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 800323e: f7fe fd47 bl 8001cd0 <HAL_GetTick>
- 8003242: 4602 mov r2, r0
- 8003244: 697b ldr r3, [r7, #20]
- 8003246: 1ad3 subs r3, r2, r3
- 8003248: 2b64 cmp r3, #100 ; 0x64
- 800324a: d903 bls.n 8003254 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 800324c: 2303 movs r3, #3
- 800324e: e0ba b.n 80033c6 <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 8003250: 40023800 .word 0x40023800
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8003254: 4b5e ldr r3, [pc, #376] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003256: 681b ldr r3, [r3, #0]
- 8003258: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 800325c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8003260: d0ed beq.n 800323e <HAL_RCCEx_PeriphCLKConfig+0x6b6>
-
- /* Check the PLLSAI division factors */
- assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
- /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8003262: 687b ldr r3, [r7, #4]
- 8003264: 681b ldr r3, [r3, #0]
- 8003266: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 800326a: 2b00 cmp r3, #0
- 800326c: d003 beq.n 8003276 <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 800326e: 687b ldr r3, [r7, #4]
- 8003270: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8003272: 2b00 cmp r3, #0
- 8003274: d009 beq.n 800328a <HAL_RCCEx_PeriphCLKConfig+0x702>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 8003276: 687b ldr r3, [r7, #4]
- 8003278: 681b ldr r3, [r3, #0]
- 800327a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 800327e: 2b00 cmp r3, #0
- 8003280: d02e beq.n 80032e0 <HAL_RCCEx_PeriphCLKConfig+0x758>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 8003282: 687b ldr r3, [r7, #4]
- 8003284: 6c1b ldr r3, [r3, #64] ; 0x40
- 8003286: 2b00 cmp r3, #0
- 8003288: d12a bne.n 80032e0 <HAL_RCCEx_PeriphCLKConfig+0x758>
- assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
- /* check for PLLSAI/DIVQ Parameter */
- assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
- /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 800328a: 4b51 ldr r3, [pc, #324] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800328c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003290: 0c1b lsrs r3, r3, #16
- 8003292: f003 0303 and.w r3, r3, #3
- 8003296: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8003298: 4b4d ldr r3, [pc, #308] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800329a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800329e: 0f1b lsrs r3, r3, #28
- 80032a0: f003 0307 and.w r3, r3, #7
- 80032a4: 60fb str r3, [r7, #12]
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 80032a6: 687b ldr r3, [r7, #4]
- 80032a8: 695b ldr r3, [r3, #20]
- 80032aa: 019a lsls r2, r3, #6
- 80032ac: 693b ldr r3, [r7, #16]
- 80032ae: 041b lsls r3, r3, #16
- 80032b0: 431a orrs r2, r3
- 80032b2: 687b ldr r3, [r7, #4]
- 80032b4: 699b ldr r3, [r3, #24]
- 80032b6: 061b lsls r3, r3, #24
- 80032b8: 431a orrs r2, r3
- 80032ba: 68fb ldr r3, [r7, #12]
- 80032bc: 071b lsls r3, r3, #28
- 80032be: 4944 ldr r1, [pc, #272] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80032c0: 4313 orrs r3, r2
- 80032c2: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 80032c6: 4b42 ldr r3, [pc, #264] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80032c8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80032cc: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
- 80032d0: 687b ldr r3, [r7, #4]
- 80032d2: 6a9b ldr r3, [r3, #40] ; 0x28
- 80032d4: 3b01 subs r3, #1
- 80032d6: 021b lsls r3, r3, #8
- 80032d8: 493d ldr r1, [pc, #244] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80032da: 4313 orrs r3, r2
- 80032dc: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
- /* In Case of PLLI2S is selected as source clock for CK48 */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 80032e0: 687b ldr r3, [r7, #4]
- 80032e2: 681b ldr r3, [r3, #0]
- 80032e4: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 80032e8: 2b00 cmp r3, #0
- 80032ea: d022 beq.n 8003332 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 80032ec: 687b ldr r3, [r7, #4]
- 80032ee: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80032f0: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 80032f4: d11d bne.n 8003332 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
- /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 80032f6: 4b36 ldr r3, [pc, #216] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80032f8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80032fc: 0e1b lsrs r3, r3, #24
- 80032fe: f003 030f and.w r3, r3, #15
- 8003302: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8003304: 4b32 ldr r3, [pc, #200] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003306: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800330a: 0f1b lsrs r3, r3, #28
- 800330c: f003 0307 and.w r3, r3, #7
- 8003310: 60fb str r3, [r7, #12]
-
- /* Configure the PLLSAI division factors */
- /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
- /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 8003312: 687b ldr r3, [r7, #4]
- 8003314: 695b ldr r3, [r3, #20]
- 8003316: 019a lsls r2, r3, #6
- 8003318: 687b ldr r3, [r7, #4]
- 800331a: 6a1b ldr r3, [r3, #32]
- 800331c: 041b lsls r3, r3, #16
- 800331e: 431a orrs r2, r3
- 8003320: 693b ldr r3, [r7, #16]
- 8003322: 061b lsls r3, r3, #24
- 8003324: 431a orrs r2, r3
- 8003326: 68fb ldr r3, [r7, #12]
- 8003328: 071b lsls r3, r3, #28
- 800332a: 4929 ldr r1, [pc, #164] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800332c: 4313 orrs r3, r2
- 800332e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
- }
-
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- /*---------------------------- LTDC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 8003332: 687b ldr r3, [r7, #4]
- 8003334: 681b ldr r3, [r3, #0]
- 8003336: f003 0308 and.w r3, r3, #8
- 800333a: 2b00 cmp r3, #0
- 800333c: d028 beq.n 8003390 <HAL_RCCEx_PeriphCLKConfig+0x808>
- {
- assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
- assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
- /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 800333e: 4b24 ldr r3, [pc, #144] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003340: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003344: 0e1b lsrs r3, r3, #24
- 8003346: f003 030f and.w r3, r3, #15
- 800334a: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 800334c: 4b20 ldr r3, [pc, #128] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800334e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003352: 0c1b lsrs r3, r3, #16
- 8003354: f003 0303 and.w r3, r3, #3
- 8003358: 60fb str r3, [r7, #12]
-
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 800335a: 687b ldr r3, [r7, #4]
- 800335c: 695b ldr r3, [r3, #20]
- 800335e: 019a lsls r2, r3, #6
- 8003360: 68fb ldr r3, [r7, #12]
- 8003362: 041b lsls r3, r3, #16
- 8003364: 431a orrs r2, r3
- 8003366: 693b ldr r3, [r7, #16]
- 8003368: 061b lsls r3, r3, #24
- 800336a: 431a orrs r2, r3
- 800336c: 687b ldr r3, [r7, #4]
- 800336e: 69db ldr r3, [r3, #28]
- 8003370: 071b lsls r3, r3, #28
- 8003372: 4917 ldr r1, [pc, #92] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003374: 4313 orrs r3, r2
- 8003376: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 800337a: 4b15 ldr r3, [pc, #84] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800337c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003380: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8003384: 687b ldr r3, [r7, #4]
- 8003386: 6adb ldr r3, [r3, #44] ; 0x2c
- 8003388: 4911 ldr r1, [pc, #68] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800338a: 4313 orrs r3, r2
- 800338c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /* Enable PLLSAI Clock */
- __HAL_RCC_PLLSAI_ENABLE();
- 8003390: 4b0f ldr r3, [pc, #60] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003392: 681b ldr r3, [r3, #0]
- 8003394: 4a0e ldr r2, [pc, #56] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003396: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 800339a: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800339c: f7fe fc98 bl 8001cd0 <HAL_GetTick>
- 80033a0: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is ready */
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 80033a2: e008 b.n 80033b6 <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 80033a4: f7fe fc94 bl 8001cd0 <HAL_GetTick>
- 80033a8: 4602 mov r2, r0
- 80033aa: 697b ldr r3, [r7, #20]
- 80033ac: 1ad3 subs r3, r2, r3
- 80033ae: 2b64 cmp r3, #100 ; 0x64
- 80033b0: d901 bls.n 80033b6 <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 80033b2: 2303 movs r3, #3
- 80033b4: e007 b.n 80033c6 <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 80033b6: 4b06 ldr r3, [pc, #24] ; (80033d0 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80033b8: 681b ldr r3, [r3, #0]
- 80033ba: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 80033be: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 80033c2: d1ef bne.n 80033a4 <HAL_RCCEx_PeriphCLKConfig+0x81c>
- }
- }
- }
- return HAL_OK;
- 80033c4: 2300 movs r3, #0
-}
- 80033c6: 4618 mov r0, r3
- 80033c8: 3720 adds r7, #32
- 80033ca: 46bd mov sp, r7
- 80033cc: bd80 pop {r7, pc}
- 80033ce: bf00 nop
- 80033d0: 40023800 .word 0x40023800
-
-080033d4 <HAL_TIM_Base_Init>:
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- 80033d4: b580 push {r7, lr}
- 80033d6: b082 sub sp, #8
- 80033d8: af00 add r7, sp, #0
- 80033da: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 80033dc: 687b ldr r3, [r7, #4]
- 80033de: 2b00 cmp r3, #0
- 80033e0: d101 bne.n 80033e6 <HAL_TIM_Base_Init+0x12>
- {
- return HAL_ERROR;
- 80033e2: 2301 movs r3, #1
- 80033e4: e01d b.n 8003422 <HAL_TIM_Base_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 80033e6: 687b ldr r3, [r7, #4]
- 80033e8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 80033ec: b2db uxtb r3, r3
- 80033ee: 2b00 cmp r3, #0
- 80033f0: d106 bne.n 8003400 <HAL_TIM_Base_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 80033f2: 687b ldr r3, [r7, #4]
- 80033f4: 2200 movs r2, #0
- 80033f6: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- 80033fa: 6878 ldr r0, [r7, #4]
- 80033fc: f7fe faa0 bl 8001940 <HAL_TIM_Base_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 8003400: 687b ldr r3, [r7, #4]
- 8003402: 2202 movs r2, #2
- 8003404: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003408: 687b ldr r3, [r7, #4]
- 800340a: 681a ldr r2, [r3, #0]
- 800340c: 687b ldr r3, [r7, #4]
- 800340e: 3304 adds r3, #4
- 8003410: 4619 mov r1, r3
- 8003412: 4610 mov r0, r2
- 8003414: f000 fc90 bl 8003d38 <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 8003418: 687b ldr r3, [r7, #4]
- 800341a: 2201 movs r2, #1
- 800341c: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 8003420: 2300 movs r3, #0
-}
- 8003422: 4618 mov r0, r3
- 8003424: 3708 adds r7, #8
- 8003426: 46bd mov sp, r7
- 8003428: bd80 pop {r7, pc}
- ...
-
-0800342c <HAL_TIM_Base_Start_IT>:
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- 800342c: b480 push {r7}
- 800342e: b085 sub sp, #20
- 8003430: af00 add r7, sp, #0
- 8003432: 6078 str r0, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- 8003434: 687b ldr r3, [r7, #4]
- 8003436: 681b ldr r3, [r3, #0]
- 8003438: 68da ldr r2, [r3, #12]
- 800343a: 687b ldr r3, [r7, #4]
- 800343c: 681b ldr r3, [r3, #0]
- 800343e: f042 0201 orr.w r2, r2, #1
- 8003442: 60da str r2, [r3, #12]
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 8003444: 687b ldr r3, [r7, #4]
- 8003446: 681b ldr r3, [r3, #0]
- 8003448: 689a ldr r2, [r3, #8]
- 800344a: 4b0c ldr r3, [pc, #48] ; (800347c <HAL_TIM_Base_Start_IT+0x50>)
- 800344c: 4013 ands r3, r2
- 800344e: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8003450: 68fb ldr r3, [r7, #12]
- 8003452: 2b06 cmp r3, #6
- 8003454: d00b beq.n 800346e <HAL_TIM_Base_Start_IT+0x42>
- 8003456: 68fb ldr r3, [r7, #12]
- 8003458: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800345c: d007 beq.n 800346e <HAL_TIM_Base_Start_IT+0x42>
- {
- __HAL_TIM_ENABLE(htim);
- 800345e: 687b ldr r3, [r7, #4]
- 8003460: 681b ldr r3, [r3, #0]
- 8003462: 681a ldr r2, [r3, #0]
- 8003464: 687b ldr r3, [r7, #4]
- 8003466: 681b ldr r3, [r3, #0]
- 8003468: f042 0201 orr.w r2, r2, #1
- 800346c: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 800346e: 2300 movs r3, #0
-}
- 8003470: 4618 mov r0, r3
- 8003472: 3714 adds r7, #20
- 8003474: 46bd mov sp, r7
- 8003476: f85d 7b04 ldr.w r7, [sp], #4
- 800347a: 4770 bx lr
- 800347c: 00010007 .word 0x00010007
-
-08003480 <HAL_TIM_PWM_Init>:
- * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
- * @param htim TIM PWM handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- 8003480: b580 push {r7, lr}
- 8003482: b082 sub sp, #8
- 8003484: af00 add r7, sp, #0
- 8003486: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 8003488: 687b ldr r3, [r7, #4]
- 800348a: 2b00 cmp r3, #0
- 800348c: d101 bne.n 8003492 <HAL_TIM_PWM_Init+0x12>
- {
- return HAL_ERROR;
- 800348e: 2301 movs r3, #1
- 8003490: e01d b.n 80034ce <HAL_TIM_PWM_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 8003492: 687b ldr r3, [r7, #4]
- 8003494: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8003498: b2db uxtb r3, r3
- 800349a: 2b00 cmp r3, #0
- 800349c: d106 bne.n 80034ac <HAL_TIM_PWM_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 800349e: 687b ldr r3, [r7, #4]
- 80034a0: 2200 movs r2, #0
- 80034a2: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->PWM_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_PWM_MspInit(htim);
- 80034a6: 6878 ldr r0, [r7, #4]
- 80034a8: f000 f815 bl 80034d6 <HAL_TIM_PWM_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80034ac: 687b ldr r3, [r7, #4]
- 80034ae: 2202 movs r2, #2
- 80034b0: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80034b4: 687b ldr r3, [r7, #4]
- 80034b6: 681a ldr r2, [r3, #0]
- 80034b8: 687b ldr r3, [r7, #4]
- 80034ba: 3304 adds r3, #4
- 80034bc: 4619 mov r1, r3
- 80034be: 4610 mov r0, r2
- 80034c0: f000 fc3a bl 8003d38 <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 80034c4: 687b ldr r3, [r7, #4]
- 80034c6: 2201 movs r2, #1
- 80034c8: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 80034cc: 2300 movs r3, #0
-}
- 80034ce: 4618 mov r0, r3
- 80034d0: 3708 adds r7, #8
- 80034d2: 46bd mov sp, r7
- 80034d4: bd80 pop {r7, pc}
-
-080034d6 <HAL_TIM_PWM_MspInit>:
- * @brief Initializes the TIM PWM MSP.
- * @param htim TIM PWM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- 80034d6: b480 push {r7}
- 80034d8: b083 sub sp, #12
- 80034da: af00 add r7, sp, #0
- 80034dc: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_MspInit could be implemented in the user file
- */
-}
- 80034de: bf00 nop
- 80034e0: 370c adds r7, #12
- 80034e2: 46bd mov sp, r7
- 80034e4: f85d 7b04 ldr.w r7, [sp], #4
- 80034e8: 4770 bx lr
- ...
-
-080034ec <HAL_TIM_PWM_Start>:
- * @arg TIM_CHANNEL_5: TIM Channel 5 selected
- * @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 80034ec: b580 push {r7, lr}
- 80034ee: b084 sub sp, #16
- 80034f0: af00 add r7, sp, #0
- 80034f2: 6078 str r0, [r7, #4]
- 80034f4: 6039 str r1, [r7, #0]
-
- /* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- 80034f6: 687b ldr r3, [r7, #4]
- 80034f8: 681b ldr r3, [r3, #0]
- 80034fa: 2201 movs r2, #1
- 80034fc: 6839 ldr r1, [r7, #0]
- 80034fe: 4618 mov r0, r3
- 8003500: f000 ffb2 bl 8004468 <TIM_CCxChannelCmd>
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- 8003504: 687b ldr r3, [r7, #4]
- 8003506: 681b ldr r3, [r3, #0]
- 8003508: 4a17 ldr r2, [pc, #92] ; (8003568 <HAL_TIM_PWM_Start+0x7c>)
- 800350a: 4293 cmp r3, r2
- 800350c: d004 beq.n 8003518 <HAL_TIM_PWM_Start+0x2c>
- 800350e: 687b ldr r3, [r7, #4]
- 8003510: 681b ldr r3, [r3, #0]
- 8003512: 4a16 ldr r2, [pc, #88] ; (800356c <HAL_TIM_PWM_Start+0x80>)
- 8003514: 4293 cmp r3, r2
- 8003516: d101 bne.n 800351c <HAL_TIM_PWM_Start+0x30>
- 8003518: 2301 movs r3, #1
- 800351a: e000 b.n 800351e <HAL_TIM_PWM_Start+0x32>
- 800351c: 2300 movs r3, #0
- 800351e: 2b00 cmp r3, #0
- 8003520: d007 beq.n 8003532 <HAL_TIM_PWM_Start+0x46>
- {
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- 8003522: 687b ldr r3, [r7, #4]
- 8003524: 681b ldr r3, [r3, #0]
- 8003526: 6c5a ldr r2, [r3, #68] ; 0x44
- 8003528: 687b ldr r3, [r7, #4]
- 800352a: 681b ldr r3, [r3, #0]
- 800352c: f442 4200 orr.w r2, r2, #32768 ; 0x8000
- 8003530: 645a str r2, [r3, #68] ; 0x44
- }
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 8003532: 687b ldr r3, [r7, #4]
- 8003534: 681b ldr r3, [r3, #0]
- 8003536: 689a ldr r2, [r3, #8]
- 8003538: 4b0d ldr r3, [pc, #52] ; (8003570 <HAL_TIM_PWM_Start+0x84>)
- 800353a: 4013 ands r3, r2
- 800353c: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 800353e: 68fb ldr r3, [r7, #12]
- 8003540: 2b06 cmp r3, #6
- 8003542: d00b beq.n 800355c <HAL_TIM_PWM_Start+0x70>
- 8003544: 68fb ldr r3, [r7, #12]
- 8003546: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800354a: d007 beq.n 800355c <HAL_TIM_PWM_Start+0x70>
- {
- __HAL_TIM_ENABLE(htim);
- 800354c: 687b ldr r3, [r7, #4]
- 800354e: 681b ldr r3, [r3, #0]
- 8003550: 681a ldr r2, [r3, #0]
- 8003552: 687b ldr r3, [r7, #4]
- 8003554: 681b ldr r3, [r3, #0]
- 8003556: f042 0201 orr.w r2, r2, #1
- 800355a: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 800355c: 2300 movs r3, #0
-}
- 800355e: 4618 mov r0, r3
- 8003560: 3710 adds r7, #16
- 8003562: 46bd mov sp, r7
- 8003564: bd80 pop {r7, pc}
- 8003566: bf00 nop
- 8003568: 40010000 .word 0x40010000
- 800356c: 40010400 .word 0x40010400
- 8003570: 00010007 .word 0x00010007
-
-08003574 <HAL_TIM_Encoder_Init>:
- * @param htim TIM Encoder Interface handle
- * @param sConfig TIM Encoder Interface configuration structure
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
-{
- 8003574: b580 push {r7, lr}
- 8003576: b086 sub sp, #24
- 8003578: af00 add r7, sp, #0
- 800357a: 6078 str r0, [r7, #4]
- 800357c: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 800357e: 687b ldr r3, [r7, #4]
- 8003580: 2b00 cmp r3, #0
- 8003582: d101 bne.n 8003588 <HAL_TIM_Encoder_Init+0x14>
- {
- return HAL_ERROR;
- 8003584: 2301 movs r3, #1
- 8003586: e07b b.n 8003680 <HAL_TIM_Encoder_Init+0x10c>
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
- assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 8003588: 687b ldr r3, [r7, #4]
- 800358a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 800358e: b2db uxtb r3, r3
- 8003590: 2b00 cmp r3, #0
- 8003592: d106 bne.n 80035a2 <HAL_TIM_Encoder_Init+0x2e>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 8003594: 687b ldr r3, [r7, #4]
- 8003596: 2200 movs r2, #0
- 8003598: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Encoder_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIM_Encoder_MspInit(htim);
- 800359c: 6878 ldr r0, [r7, #4]
- 800359e: f7fe f93f bl 8001820 <HAL_TIM_Encoder_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80035a2: 687b ldr r3, [r7, #4]
- 80035a4: 2202 movs r2, #2
- 80035a6: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Reset the SMS and ECE bits */
- htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
- 80035aa: 687b ldr r3, [r7, #4]
- 80035ac: 681b ldr r3, [r3, #0]
- 80035ae: 6899 ldr r1, [r3, #8]
- 80035b0: 687b ldr r3, [r7, #4]
- 80035b2: 681a ldr r2, [r3, #0]
- 80035b4: 4b34 ldr r3, [pc, #208] ; (8003688 <HAL_TIM_Encoder_Init+0x114>)
- 80035b6: 400b ands r3, r1
- 80035b8: 6093 str r3, [r2, #8]
-
- /* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80035ba: 687b ldr r3, [r7, #4]
- 80035bc: 681a ldr r2, [r3, #0]
- 80035be: 687b ldr r3, [r7, #4]
- 80035c0: 3304 adds r3, #4
- 80035c2: 4619 mov r1, r3
- 80035c4: 4610 mov r0, r2
- 80035c6: f000 fbb7 bl 8003d38 <TIM_Base_SetConfig>
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 80035ca: 687b ldr r3, [r7, #4]
- 80035cc: 681b ldr r3, [r3, #0]
- 80035ce: 689b ldr r3, [r3, #8]
- 80035d0: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = htim->Instance->CCMR1;
- 80035d2: 687b ldr r3, [r7, #4]
- 80035d4: 681b ldr r3, [r3, #0]
- 80035d6: 699b ldr r3, [r3, #24]
- 80035d8: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCER register value */
- tmpccer = htim->Instance->CCER;
- 80035da: 687b ldr r3, [r7, #4]
- 80035dc: 681b ldr r3, [r3, #0]
- 80035de: 6a1b ldr r3, [r3, #32]
- 80035e0: 60fb str r3, [r7, #12]
-
- /* Set the encoder Mode */
- tmpsmcr |= sConfig->EncoderMode;
- 80035e2: 683b ldr r3, [r7, #0]
- 80035e4: 681b ldr r3, [r3, #0]
- 80035e6: 697a ldr r2, [r7, #20]
- 80035e8: 4313 orrs r3, r2
- 80035ea: 617b str r3, [r7, #20]
-
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- 80035ec: 693a ldr r2, [r7, #16]
- 80035ee: 4b27 ldr r3, [pc, #156] ; (800368c <HAL_TIM_Encoder_Init+0x118>)
- 80035f0: 4013 ands r3, r2
- 80035f2: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- 80035f4: 683b ldr r3, [r7, #0]
- 80035f6: 689a ldr r2, [r3, #8]
- 80035f8: 683b ldr r3, [r7, #0]
- 80035fa: 699b ldr r3, [r3, #24]
- 80035fc: 021b lsls r3, r3, #8
- 80035fe: 4313 orrs r3, r2
- 8003600: 693a ldr r2, [r7, #16]
- 8003602: 4313 orrs r3, r2
- 8003604: 613b str r3, [r7, #16]
-
- /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
- tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- 8003606: 693a ldr r2, [r7, #16]
- 8003608: 4b21 ldr r3, [pc, #132] ; (8003690 <HAL_TIM_Encoder_Init+0x11c>)
- 800360a: 4013 ands r3, r2
- 800360c: 613b str r3, [r7, #16]
- tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- 800360e: 693a ldr r2, [r7, #16]
- 8003610: 4b20 ldr r3, [pc, #128] ; (8003694 <HAL_TIM_Encoder_Init+0x120>)
- 8003612: 4013 ands r3, r2
- 8003614: 613b str r3, [r7, #16]
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- 8003616: 683b ldr r3, [r7, #0]
- 8003618: 68da ldr r2, [r3, #12]
- 800361a: 683b ldr r3, [r7, #0]
- 800361c: 69db ldr r3, [r3, #28]
- 800361e: 021b lsls r3, r3, #8
- 8003620: 4313 orrs r3, r2
- 8003622: 693a ldr r2, [r7, #16]
- 8003624: 4313 orrs r3, r2
- 8003626: 613b str r3, [r7, #16]
- tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
- 8003628: 683b ldr r3, [r7, #0]
- 800362a: 691b ldr r3, [r3, #16]
- 800362c: 011a lsls r2, r3, #4
- 800362e: 683b ldr r3, [r7, #0]
- 8003630: 6a1b ldr r3, [r3, #32]
- 8003632: 031b lsls r3, r3, #12
- 8003634: 4313 orrs r3, r2
- 8003636: 693a ldr r2, [r7, #16]
- 8003638: 4313 orrs r3, r2
- 800363a: 613b str r3, [r7, #16]
-
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- 800363c: 68fb ldr r3, [r7, #12]
- 800363e: f023 0322 bic.w r3, r3, #34 ; 0x22
- 8003642: 60fb str r3, [r7, #12]
- tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- 8003644: 68fb ldr r3, [r7, #12]
- 8003646: f023 0388 bic.w r3, r3, #136 ; 0x88
- 800364a: 60fb str r3, [r7, #12]
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
- 800364c: 683b ldr r3, [r7, #0]
- 800364e: 685a ldr r2, [r3, #4]
- 8003650: 683b ldr r3, [r7, #0]
- 8003652: 695b ldr r3, [r3, #20]
- 8003654: 011b lsls r3, r3, #4
- 8003656: 4313 orrs r3, r2
- 8003658: 68fa ldr r2, [r7, #12]
- 800365a: 4313 orrs r3, r2
- 800365c: 60fb str r3, [r7, #12]
-
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 800365e: 687b ldr r3, [r7, #4]
- 8003660: 681b ldr r3, [r3, #0]
- 8003662: 697a ldr r2, [r7, #20]
- 8003664: 609a str r2, [r3, #8]
-
- /* Write to TIMx CCMR1 */
- htim->Instance->CCMR1 = tmpccmr1;
- 8003666: 687b ldr r3, [r7, #4]
- 8003668: 681b ldr r3, [r3, #0]
- 800366a: 693a ldr r2, [r7, #16]
- 800366c: 619a str r2, [r3, #24]
-
- /* Write to TIMx CCER */
- htim->Instance->CCER = tmpccer;
- 800366e: 687b ldr r3, [r7, #4]
- 8003670: 681b ldr r3, [r3, #0]
- 8003672: 68fa ldr r2, [r7, #12]
- 8003674: 621a str r2, [r3, #32]
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 8003676: 687b ldr r3, [r7, #4]
- 8003678: 2201 movs r2, #1
- 800367a: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 800367e: 2300 movs r3, #0
-}
- 8003680: 4618 mov r0, r3
- 8003682: 3718 adds r7, #24
- 8003684: 46bd mov sp, r7
- 8003686: bd80 pop {r7, pc}
- 8003688: fffebff8 .word 0xfffebff8
- 800368c: fffffcfc .word 0xfffffcfc
- 8003690: fffff3f3 .word 0xfffff3f3
- 8003694: ffff0f0f .word 0xffff0f0f
-
-08003698 <HAL_TIM_Encoder_Start>:
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 8003698: b580 push {r7, lr}
- 800369a: b082 sub sp, #8
- 800369c: af00 add r7, sp, #0
- 800369e: 6078 str r0, [r7, #4]
- 80036a0: 6039 str r1, [r7, #0]
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Enable the encoder interface channels */
- switch (Channel)
- 80036a2: 683b ldr r3, [r7, #0]
- 80036a4: 2b00 cmp r3, #0
- 80036a6: d002 beq.n 80036ae <HAL_TIM_Encoder_Start+0x16>
- 80036a8: 2b04 cmp r3, #4
- 80036aa: d008 beq.n 80036be <HAL_TIM_Encoder_Start+0x26>
- 80036ac: e00f b.n 80036ce <HAL_TIM_Encoder_Start+0x36>
- {
- case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 80036ae: 687b ldr r3, [r7, #4]
- 80036b0: 681b ldr r3, [r3, #0]
- 80036b2: 2201 movs r2, #1
- 80036b4: 2100 movs r1, #0
- 80036b6: 4618 mov r0, r3
- 80036b8: f000 fed6 bl 8004468 <TIM_CCxChannelCmd>
- break;
- 80036bc: e016 b.n 80036ec <HAL_TIM_Encoder_Start+0x54>
- }
-
- case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 80036be: 687b ldr r3, [r7, #4]
- 80036c0: 681b ldr r3, [r3, #0]
- 80036c2: 2201 movs r2, #1
- 80036c4: 2104 movs r1, #4
- 80036c6: 4618 mov r0, r3
- 80036c8: f000 fece bl 8004468 <TIM_CCxChannelCmd>
- break;
- 80036cc: e00e b.n 80036ec <HAL_TIM_Encoder_Start+0x54>
- }
-
- default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 80036ce: 687b ldr r3, [r7, #4]
- 80036d0: 681b ldr r3, [r3, #0]
- 80036d2: 2201 movs r2, #1
- 80036d4: 2100 movs r1, #0
- 80036d6: 4618 mov r0, r3
- 80036d8: f000 fec6 bl 8004468 <TIM_CCxChannelCmd>
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 80036dc: 687b ldr r3, [r7, #4]
- 80036de: 681b ldr r3, [r3, #0]
- 80036e0: 2201 movs r2, #1
- 80036e2: 2104 movs r1, #4
- 80036e4: 4618 mov r0, r3
- 80036e6: f000 febf bl 8004468 <TIM_CCxChannelCmd>
- break;
- 80036ea: bf00 nop
- }
- }
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
- 80036ec: 687b ldr r3, [r7, #4]
- 80036ee: 681b ldr r3, [r3, #0]
- 80036f0: 681a ldr r2, [r3, #0]
- 80036f2: 687b ldr r3, [r7, #4]
- 80036f4: 681b ldr r3, [r3, #0]
- 80036f6: f042 0201 orr.w r2, r2, #1
- 80036fa: 601a str r2, [r3, #0]
-
- /* Return function status */
- return HAL_OK;
- 80036fc: 2300 movs r3, #0
-}
- 80036fe: 4618 mov r0, r3
- 8003700: 3708 adds r7, #8
- 8003702: 46bd mov sp, r7
- 8003704: bd80 pop {r7, pc}
-
-08003706 <HAL_TIM_IRQHandler>:
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- 8003706: b580 push {r7, lr}
- 8003708: b082 sub sp, #8
- 800370a: af00 add r7, sp, #0
- 800370c: 6078 str r0, [r7, #4]
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- 800370e: 687b ldr r3, [r7, #4]
- 8003710: 681b ldr r3, [r3, #0]
- 8003712: 691b ldr r3, [r3, #16]
- 8003714: f003 0302 and.w r3, r3, #2
- 8003718: 2b02 cmp r3, #2
- 800371a: d122 bne.n 8003762 <HAL_TIM_IRQHandler+0x5c>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- 800371c: 687b ldr r3, [r7, #4]
- 800371e: 681b ldr r3, [r3, #0]
- 8003720: 68db ldr r3, [r3, #12]
- 8003722: f003 0302 and.w r3, r3, #2
- 8003726: 2b02 cmp r3, #2
- 8003728: d11b bne.n 8003762 <HAL_TIM_IRQHandler+0x5c>
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- 800372a: 687b ldr r3, [r7, #4]
- 800372c: 681b ldr r3, [r3, #0]
- 800372e: f06f 0202 mvn.w r2, #2
- 8003732: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- 8003734: 687b ldr r3, [r7, #4]
- 8003736: 2201 movs r2, #1
- 8003738: 771a strb r2, [r3, #28]
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- 800373a: 687b ldr r3, [r7, #4]
- 800373c: 681b ldr r3, [r3, #0]
- 800373e: 699b ldr r3, [r3, #24]
- 8003740: f003 0303 and.w r3, r3, #3
- 8003744: 2b00 cmp r3, #0
- 8003746: d003 beq.n 8003750 <HAL_TIM_IRQHandler+0x4a>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003748: 6878 ldr r0, [r7, #4]
- 800374a: f000 fad7 bl 8003cfc <HAL_TIM_IC_CaptureCallback>
- 800374e: e005 b.n 800375c <HAL_TIM_IRQHandler+0x56>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003750: 6878 ldr r0, [r7, #4]
- 8003752: f000 fac9 bl 8003ce8 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8003756: 6878 ldr r0, [r7, #4]
- 8003758: f000 fada bl 8003d10 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 800375c: 687b ldr r3, [r7, #4]
- 800375e: 2200 movs r2, #0
- 8003760: 771a strb r2, [r3, #28]
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- 8003762: 687b ldr r3, [r7, #4]
- 8003764: 681b ldr r3, [r3, #0]
- 8003766: 691b ldr r3, [r3, #16]
- 8003768: f003 0304 and.w r3, r3, #4
- 800376c: 2b04 cmp r3, #4
- 800376e: d122 bne.n 80037b6 <HAL_TIM_IRQHandler+0xb0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- 8003770: 687b ldr r3, [r7, #4]
- 8003772: 681b ldr r3, [r3, #0]
- 8003774: 68db ldr r3, [r3, #12]
- 8003776: f003 0304 and.w r3, r3, #4
- 800377a: 2b04 cmp r3, #4
- 800377c: d11b bne.n 80037b6 <HAL_TIM_IRQHandler+0xb0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- 800377e: 687b ldr r3, [r7, #4]
- 8003780: 681b ldr r3, [r3, #0]
- 8003782: f06f 0204 mvn.w r2, #4
- 8003786: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- 8003788: 687b ldr r3, [r7, #4]
- 800378a: 2202 movs r2, #2
- 800378c: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- 800378e: 687b ldr r3, [r7, #4]
- 8003790: 681b ldr r3, [r3, #0]
- 8003792: 699b ldr r3, [r3, #24]
- 8003794: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003798: 2b00 cmp r3, #0
- 800379a: d003 beq.n 80037a4 <HAL_TIM_IRQHandler+0x9e>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 800379c: 6878 ldr r0, [r7, #4]
- 800379e: f000 faad bl 8003cfc <HAL_TIM_IC_CaptureCallback>
- 80037a2: e005 b.n 80037b0 <HAL_TIM_IRQHandler+0xaa>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 80037a4: 6878 ldr r0, [r7, #4]
- 80037a6: f000 fa9f bl 8003ce8 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80037aa: 6878 ldr r0, [r7, #4]
- 80037ac: f000 fab0 bl 8003d10 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80037b0: 687b ldr r3, [r7, #4]
- 80037b2: 2200 movs r2, #0
- 80037b4: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- 80037b6: 687b ldr r3, [r7, #4]
- 80037b8: 681b ldr r3, [r3, #0]
- 80037ba: 691b ldr r3, [r3, #16]
- 80037bc: f003 0308 and.w r3, r3, #8
- 80037c0: 2b08 cmp r3, #8
- 80037c2: d122 bne.n 800380a <HAL_TIM_IRQHandler+0x104>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- 80037c4: 687b ldr r3, [r7, #4]
- 80037c6: 681b ldr r3, [r3, #0]
- 80037c8: 68db ldr r3, [r3, #12]
- 80037ca: f003 0308 and.w r3, r3, #8
- 80037ce: 2b08 cmp r3, #8
- 80037d0: d11b bne.n 800380a <HAL_TIM_IRQHandler+0x104>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- 80037d2: 687b ldr r3, [r7, #4]
- 80037d4: 681b ldr r3, [r3, #0]
- 80037d6: f06f 0208 mvn.w r2, #8
- 80037da: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- 80037dc: 687b ldr r3, [r7, #4]
- 80037de: 2204 movs r2, #4
- 80037e0: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- 80037e2: 687b ldr r3, [r7, #4]
- 80037e4: 681b ldr r3, [r3, #0]
- 80037e6: 69db ldr r3, [r3, #28]
- 80037e8: f003 0303 and.w r3, r3, #3
- 80037ec: 2b00 cmp r3, #0
- 80037ee: d003 beq.n 80037f8 <HAL_TIM_IRQHandler+0xf2>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 80037f0: 6878 ldr r0, [r7, #4]
- 80037f2: f000 fa83 bl 8003cfc <HAL_TIM_IC_CaptureCallback>
- 80037f6: e005 b.n 8003804 <HAL_TIM_IRQHandler+0xfe>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 80037f8: 6878 ldr r0, [r7, #4]
- 80037fa: f000 fa75 bl 8003ce8 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80037fe: 6878 ldr r0, [r7, #4]
- 8003800: f000 fa86 bl 8003d10 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003804: 687b ldr r3, [r7, #4]
- 8003806: 2200 movs r2, #0
- 8003808: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- 800380a: 687b ldr r3, [r7, #4]
- 800380c: 681b ldr r3, [r3, #0]
- 800380e: 691b ldr r3, [r3, #16]
- 8003810: f003 0310 and.w r3, r3, #16
- 8003814: 2b10 cmp r3, #16
- 8003816: d122 bne.n 800385e <HAL_TIM_IRQHandler+0x158>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- 8003818: 687b ldr r3, [r7, #4]
- 800381a: 681b ldr r3, [r3, #0]
- 800381c: 68db ldr r3, [r3, #12]
- 800381e: f003 0310 and.w r3, r3, #16
- 8003822: 2b10 cmp r3, #16
- 8003824: d11b bne.n 800385e <HAL_TIM_IRQHandler+0x158>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- 8003826: 687b ldr r3, [r7, #4]
- 8003828: 681b ldr r3, [r3, #0]
- 800382a: f06f 0210 mvn.w r2, #16
- 800382e: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- 8003830: 687b ldr r3, [r7, #4]
- 8003832: 2208 movs r2, #8
- 8003834: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- 8003836: 687b ldr r3, [r7, #4]
- 8003838: 681b ldr r3, [r3, #0]
- 800383a: 69db ldr r3, [r3, #28]
- 800383c: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003840: 2b00 cmp r3, #0
- 8003842: d003 beq.n 800384c <HAL_TIM_IRQHandler+0x146>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8003844: 6878 ldr r0, [r7, #4]
- 8003846: f000 fa59 bl 8003cfc <HAL_TIM_IC_CaptureCallback>
- 800384a: e005 b.n 8003858 <HAL_TIM_IRQHandler+0x152>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 800384c: 6878 ldr r0, [r7, #4]
- 800384e: f000 fa4b bl 8003ce8 <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8003852: 6878 ldr r0, [r7, #4]
- 8003854: f000 fa5c bl 8003d10 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003858: 687b ldr r3, [r7, #4]
- 800385a: 2200 movs r2, #0
- 800385c: 771a strb r2, [r3, #28]
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- 800385e: 687b ldr r3, [r7, #4]
- 8003860: 681b ldr r3, [r3, #0]
- 8003862: 691b ldr r3, [r3, #16]
- 8003864: f003 0301 and.w r3, r3, #1
- 8003868: 2b01 cmp r3, #1
- 800386a: d10e bne.n 800388a <HAL_TIM_IRQHandler+0x184>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- 800386c: 687b ldr r3, [r7, #4]
- 800386e: 681b ldr r3, [r3, #0]
- 8003870: 68db ldr r3, [r3, #12]
- 8003872: f003 0301 and.w r3, r3, #1
- 8003876: 2b01 cmp r3, #1
- 8003878: d107 bne.n 800388a <HAL_TIM_IRQHandler+0x184>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- 800387a: 687b ldr r3, [r7, #4]
- 800387c: 681b ldr r3, [r3, #0]
- 800387e: f06f 0201 mvn.w r2, #1
- 8003882: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
- 8003884: 6878 ldr r0, [r7, #4]
- 8003886: f7fd fddf bl 8001448 <HAL_TIM_PeriodElapsedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- 800388a: 687b ldr r3, [r7, #4]
- 800388c: 681b ldr r3, [r3, #0]
- 800388e: 691b ldr r3, [r3, #16]
- 8003890: f003 0380 and.w r3, r3, #128 ; 0x80
- 8003894: 2b80 cmp r3, #128 ; 0x80
- 8003896: d10e bne.n 80038b6 <HAL_TIM_IRQHandler+0x1b0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 8003898: 687b ldr r3, [r7, #4]
- 800389a: 681b ldr r3, [r3, #0]
- 800389c: 68db ldr r3, [r3, #12]
- 800389e: f003 0380 and.w r3, r3, #128 ; 0x80
- 80038a2: 2b80 cmp r3, #128 ; 0x80
- 80038a4: d107 bne.n 80038b6 <HAL_TIM_IRQHandler+0x1b0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- 80038a6: 687b ldr r3, [r7, #4]
- 80038a8: 681b ldr r3, [r3, #0]
- 80038aa: f06f 0280 mvn.w r2, #128 ; 0x80
- 80038ae: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
- 80038b0: 6878 ldr r0, [r7, #4]
- 80038b2: f000 fe65 bl 8004580 <HAL_TIMEx_BreakCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- 80038b6: 687b ldr r3, [r7, #4]
- 80038b8: 681b ldr r3, [r3, #0]
- 80038ba: 691b ldr r3, [r3, #16]
- 80038bc: f403 7380 and.w r3, r3, #256 ; 0x100
- 80038c0: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 80038c4: d10e bne.n 80038e4 <HAL_TIM_IRQHandler+0x1de>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 80038c6: 687b ldr r3, [r7, #4]
- 80038c8: 681b ldr r3, [r3, #0]
- 80038ca: 68db ldr r3, [r3, #12]
- 80038cc: f003 0380 and.w r3, r3, #128 ; 0x80
- 80038d0: 2b80 cmp r3, #128 ; 0x80
- 80038d2: d107 bne.n 80038e4 <HAL_TIM_IRQHandler+0x1de>
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- 80038d4: 687b ldr r3, [r7, #4]
- 80038d6: 681b ldr r3, [r3, #0]
- 80038d8: f46f 7280 mvn.w r2, #256 ; 0x100
- 80038dc: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->Break2Callback(htim);
-#else
- HAL_TIMEx_Break2Callback(htim);
- 80038de: 6878 ldr r0, [r7, #4]
- 80038e0: f000 fe58 bl 8004594 <HAL_TIMEx_Break2Callback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- 80038e4: 687b ldr r3, [r7, #4]
- 80038e6: 681b ldr r3, [r3, #0]
- 80038e8: 691b ldr r3, [r3, #16]
- 80038ea: f003 0340 and.w r3, r3, #64 ; 0x40
- 80038ee: 2b40 cmp r3, #64 ; 0x40
- 80038f0: d10e bne.n 8003910 <HAL_TIM_IRQHandler+0x20a>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- 80038f2: 687b ldr r3, [r7, #4]
- 80038f4: 681b ldr r3, [r3, #0]
- 80038f6: 68db ldr r3, [r3, #12]
- 80038f8: f003 0340 and.w r3, r3, #64 ; 0x40
- 80038fc: 2b40 cmp r3, #64 ; 0x40
- 80038fe: d107 bne.n 8003910 <HAL_TIM_IRQHandler+0x20a>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- 8003900: 687b ldr r3, [r7, #4]
- 8003902: 681b ldr r3, [r3, #0]
- 8003904: f06f 0240 mvn.w r2, #64 ; 0x40
- 8003908: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
- 800390a: 6878 ldr r0, [r7, #4]
- 800390c: f000 fa0a bl 8003d24 <HAL_TIM_TriggerCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- 8003910: 687b ldr r3, [r7, #4]
- 8003912: 681b ldr r3, [r3, #0]
- 8003914: 691b ldr r3, [r3, #16]
- 8003916: f003 0320 and.w r3, r3, #32
- 800391a: 2b20 cmp r3, #32
- 800391c: d10e bne.n 800393c <HAL_TIM_IRQHandler+0x236>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- 800391e: 687b ldr r3, [r7, #4]
- 8003920: 681b ldr r3, [r3, #0]
- 8003922: 68db ldr r3, [r3, #12]
- 8003924: f003 0320 and.w r3, r3, #32
- 8003928: 2b20 cmp r3, #32
- 800392a: d107 bne.n 800393c <HAL_TIM_IRQHandler+0x236>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- 800392c: 687b ldr r3, [r7, #4]
- 800392e: 681b ldr r3, [r3, #0]
- 8003930: f06f 0220 mvn.w r2, #32
- 8003934: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
- 8003936: 6878 ldr r0, [r7, #4]
- 8003938: f000 fe18 bl 800456c <HAL_TIMEx_CommutCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
- 800393c: bf00 nop
- 800393e: 3708 adds r7, #8
- 8003940: 46bd mov sp, r7
- 8003942: bd80 pop {r7, pc}
-
-08003944 <HAL_TIM_PWM_ConfigChannel>:
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
- TIM_OC_InitTypeDef *sConfig,
- uint32_t Channel)
-{
- 8003944: b580 push {r7, lr}
- 8003946: b084 sub sp, #16
- 8003948: af00 add r7, sp, #0
- 800394a: 60f8 str r0, [r7, #12]
- 800394c: 60b9 str r1, [r7, #8]
- 800394e: 607a str r2, [r7, #4]
- assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
- assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003950: 68fb ldr r3, [r7, #12]
- 8003952: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8003956: 2b01 cmp r3, #1
- 8003958: d101 bne.n 800395e <HAL_TIM_PWM_ConfigChannel+0x1a>
- 800395a: 2302 movs r3, #2
- 800395c: e105 b.n 8003b6a <HAL_TIM_PWM_ConfigChannel+0x226>
- 800395e: 68fb ldr r3, [r7, #12]
- 8003960: 2201 movs r2, #1
- 8003962: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8003966: 68fb ldr r3, [r7, #12]
- 8003968: 2202 movs r2, #2
- 800396a: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- switch (Channel)
- 800396e: 687b ldr r3, [r7, #4]
- 8003970: 2b14 cmp r3, #20
- 8003972: f200 80f0 bhi.w 8003b56 <HAL_TIM_PWM_ConfigChannel+0x212>
- 8003976: a201 add r2, pc, #4 ; (adr r2, 800397c <HAL_TIM_PWM_ConfigChannel+0x38>)
- 8003978: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 800397c: 080039d1 .word 0x080039d1
- 8003980: 08003b57 .word 0x08003b57
- 8003984: 08003b57 .word 0x08003b57
- 8003988: 08003b57 .word 0x08003b57
- 800398c: 08003a11 .word 0x08003a11
- 8003990: 08003b57 .word 0x08003b57
- 8003994: 08003b57 .word 0x08003b57
- 8003998: 08003b57 .word 0x08003b57
- 800399c: 08003a53 .word 0x08003a53
- 80039a0: 08003b57 .word 0x08003b57
- 80039a4: 08003b57 .word 0x08003b57
- 80039a8: 08003b57 .word 0x08003b57
- 80039ac: 08003a93 .word 0x08003a93
- 80039b0: 08003b57 .word 0x08003b57
- 80039b4: 08003b57 .word 0x08003b57
- 80039b8: 08003b57 .word 0x08003b57
- 80039bc: 08003ad5 .word 0x08003ad5
- 80039c0: 08003b57 .word 0x08003b57
- 80039c4: 08003b57 .word 0x08003b57
- 80039c8: 08003b57 .word 0x08003b57
- 80039cc: 08003b15 .word 0x08003b15
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- /* Configure the Channel 1 in PWM mode */
- TIM_OC1_SetConfig(htim->Instance, sConfig);
- 80039d0: 68fb ldr r3, [r7, #12]
- 80039d2: 681b ldr r3, [r3, #0]
- 80039d4: 68b9 ldr r1, [r7, #8]
- 80039d6: 4618 mov r0, r3
- 80039d8: f000 fa4e bl 8003e78 <TIM_OC1_SetConfig>
-
- /* Set the Preload enable bit for channel1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 80039dc: 68fb ldr r3, [r7, #12]
- 80039de: 681b ldr r3, [r3, #0]
- 80039e0: 699a ldr r2, [r3, #24]
- 80039e2: 68fb ldr r3, [r7, #12]
- 80039e4: 681b ldr r3, [r3, #0]
- 80039e6: f042 0208 orr.w r2, r2, #8
- 80039ea: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- 80039ec: 68fb ldr r3, [r7, #12]
- 80039ee: 681b ldr r3, [r3, #0]
- 80039f0: 699a ldr r2, [r3, #24]
- 80039f2: 68fb ldr r3, [r7, #12]
- 80039f4: 681b ldr r3, [r3, #0]
- 80039f6: f022 0204 bic.w r2, r2, #4
- 80039fa: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
- 80039fc: 68fb ldr r3, [r7, #12]
- 80039fe: 681b ldr r3, [r3, #0]
- 8003a00: 6999 ldr r1, [r3, #24]
- 8003a02: 68bb ldr r3, [r7, #8]
- 8003a04: 691a ldr r2, [r3, #16]
- 8003a06: 68fb ldr r3, [r7, #12]
- 8003a08: 681b ldr r3, [r3, #0]
- 8003a0a: 430a orrs r2, r1
- 8003a0c: 619a str r2, [r3, #24]
- break;
- 8003a0e: e0a3 b.n 8003b58 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- /* Configure the Channel 2 in PWM mode */
- TIM_OC2_SetConfig(htim->Instance, sConfig);
- 8003a10: 68fb ldr r3, [r7, #12]
- 8003a12: 681b ldr r3, [r3, #0]
- 8003a14: 68b9 ldr r1, [r7, #8]
- 8003a16: 4618 mov r0, r3
- 8003a18: f000 faa0 bl 8003f5c <TIM_OC2_SetConfig>
-
- /* Set the Preload enable bit for channel2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 8003a1c: 68fb ldr r3, [r7, #12]
- 8003a1e: 681b ldr r3, [r3, #0]
- 8003a20: 699a ldr r2, [r3, #24]
- 8003a22: 68fb ldr r3, [r7, #12]
- 8003a24: 681b ldr r3, [r3, #0]
- 8003a26: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003a2a: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 8003a2c: 68fb ldr r3, [r7, #12]
- 8003a2e: 681b ldr r3, [r3, #0]
- 8003a30: 699a ldr r2, [r3, #24]
- 8003a32: 68fb ldr r3, [r7, #12]
- 8003a34: 681b ldr r3, [r3, #0]
- 8003a36: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003a3a: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- 8003a3c: 68fb ldr r3, [r7, #12]
- 8003a3e: 681b ldr r3, [r3, #0]
- 8003a40: 6999 ldr r1, [r3, #24]
- 8003a42: 68bb ldr r3, [r7, #8]
- 8003a44: 691b ldr r3, [r3, #16]
- 8003a46: 021a lsls r2, r3, #8
- 8003a48: 68fb ldr r3, [r7, #12]
- 8003a4a: 681b ldr r3, [r3, #0]
- 8003a4c: 430a orrs r2, r1
- 8003a4e: 619a str r2, [r3, #24]
- break;
- 8003a50: e082 b.n 8003b58 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- /* Configure the Channel 3 in PWM mode */
- TIM_OC3_SetConfig(htim->Instance, sConfig);
- 8003a52: 68fb ldr r3, [r7, #12]
- 8003a54: 681b ldr r3, [r3, #0]
- 8003a56: 68b9 ldr r1, [r7, #8]
- 8003a58: 4618 mov r0, r3
- 8003a5a: f000 faf7 bl 800404c <TIM_OC3_SetConfig>
-
- /* Set the Preload enable bit for channel3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 8003a5e: 68fb ldr r3, [r7, #12]
- 8003a60: 681b ldr r3, [r3, #0]
- 8003a62: 69da ldr r2, [r3, #28]
- 8003a64: 68fb ldr r3, [r7, #12]
- 8003a66: 681b ldr r3, [r3, #0]
- 8003a68: f042 0208 orr.w r2, r2, #8
- 8003a6c: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- 8003a6e: 68fb ldr r3, [r7, #12]
- 8003a70: 681b ldr r3, [r3, #0]
- 8003a72: 69da ldr r2, [r3, #28]
- 8003a74: 68fb ldr r3, [r7, #12]
- 8003a76: 681b ldr r3, [r3, #0]
- 8003a78: f022 0204 bic.w r2, r2, #4
- 8003a7c: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
- 8003a7e: 68fb ldr r3, [r7, #12]
- 8003a80: 681b ldr r3, [r3, #0]
- 8003a82: 69d9 ldr r1, [r3, #28]
- 8003a84: 68bb ldr r3, [r7, #8]
- 8003a86: 691a ldr r2, [r3, #16]
- 8003a88: 68fb ldr r3, [r7, #12]
- 8003a8a: 681b ldr r3, [r3, #0]
- 8003a8c: 430a orrs r2, r1
- 8003a8e: 61da str r2, [r3, #28]
- break;
- 8003a90: e062 b.n 8003b58 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- /* Configure the Channel 4 in PWM mode */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
- 8003a92: 68fb ldr r3, [r7, #12]
- 8003a94: 681b ldr r3, [r3, #0]
- 8003a96: 68b9 ldr r1, [r7, #8]
- 8003a98: 4618 mov r0, r3
- 8003a9a: f000 fb4d bl 8004138 <TIM_OC4_SetConfig>
-
- /* Set the Preload enable bit for channel4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 8003a9e: 68fb ldr r3, [r7, #12]
- 8003aa0: 681b ldr r3, [r3, #0]
- 8003aa2: 69da ldr r2, [r3, #28]
- 8003aa4: 68fb ldr r3, [r7, #12]
- 8003aa6: 681b ldr r3, [r3, #0]
- 8003aa8: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003aac: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 8003aae: 68fb ldr r3, [r7, #12]
- 8003ab0: 681b ldr r3, [r3, #0]
- 8003ab2: 69da ldr r2, [r3, #28]
- 8003ab4: 68fb ldr r3, [r7, #12]
- 8003ab6: 681b ldr r3, [r3, #0]
- 8003ab8: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003abc: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- 8003abe: 68fb ldr r3, [r7, #12]
- 8003ac0: 681b ldr r3, [r3, #0]
- 8003ac2: 69d9 ldr r1, [r3, #28]
- 8003ac4: 68bb ldr r3, [r7, #8]
- 8003ac6: 691b ldr r3, [r3, #16]
- 8003ac8: 021a lsls r2, r3, #8
- 8003aca: 68fb ldr r3, [r7, #12]
- 8003acc: 681b ldr r3, [r3, #0]
- 8003ace: 430a orrs r2, r1
- 8003ad0: 61da str r2, [r3, #28]
- break;
- 8003ad2: e041 b.n 8003b58 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
- /* Configure the Channel 5 in PWM mode */
- TIM_OC5_SetConfig(htim->Instance, sConfig);
- 8003ad4: 68fb ldr r3, [r7, #12]
- 8003ad6: 681b ldr r3, [r3, #0]
- 8003ad8: 68b9 ldr r1, [r7, #8]
- 8003ada: 4618 mov r0, r3
- 8003adc: f000 fb84 bl 80041e8 <TIM_OC5_SetConfig>
-
- /* Set the Preload enable bit for channel5*/
- htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
- 8003ae0: 68fb ldr r3, [r7, #12]
- 8003ae2: 681b ldr r3, [r3, #0]
- 8003ae4: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003ae6: 68fb ldr r3, [r7, #12]
- 8003ae8: 681b ldr r3, [r3, #0]
- 8003aea: f042 0208 orr.w r2, r2, #8
- 8003aee: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- 8003af0: 68fb ldr r3, [r7, #12]
- 8003af2: 681b ldr r3, [r3, #0]
- 8003af4: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003af6: 68fb ldr r3, [r7, #12]
- 8003af8: 681b ldr r3, [r3, #0]
- 8003afa: f022 0204 bic.w r2, r2, #4
- 8003afe: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode;
- 8003b00: 68fb ldr r3, [r7, #12]
- 8003b02: 681b ldr r3, [r3, #0]
- 8003b04: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003b06: 68bb ldr r3, [r7, #8]
- 8003b08: 691a ldr r2, [r3, #16]
- 8003b0a: 68fb ldr r3, [r7, #12]
- 8003b0c: 681b ldr r3, [r3, #0]
- 8003b0e: 430a orrs r2, r1
- 8003b10: 655a str r2, [r3, #84] ; 0x54
- break;
- 8003b12: e021 b.n 8003b58 <HAL_TIM_PWM_ConfigChannel+0x214>
- {
- /* Check the parameters */
- assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
- /* Configure the Channel 6 in PWM mode */
- TIM_OC6_SetConfig(htim->Instance, sConfig);
- 8003b14: 68fb ldr r3, [r7, #12]
- 8003b16: 681b ldr r3, [r3, #0]
- 8003b18: 68b9 ldr r1, [r7, #8]
- 8003b1a: 4618 mov r0, r3
- 8003b1c: f000 fbb6 bl 800428c <TIM_OC6_SetConfig>
-
- /* Set the Preload enable bit for channel6 */
- htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
- 8003b20: 68fb ldr r3, [r7, #12]
- 8003b22: 681b ldr r3, [r3, #0]
- 8003b24: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003b26: 68fb ldr r3, [r7, #12]
- 8003b28: 681b ldr r3, [r3, #0]
- 8003b2a: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003b2e: 655a str r2, [r3, #84] ; 0x54
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- 8003b30: 68fb ldr r3, [r7, #12]
- 8003b32: 681b ldr r3, [r3, #0]
- 8003b34: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003b36: 68fb ldr r3, [r7, #12]
- 8003b38: 681b ldr r3, [r3, #0]
- 8003b3a: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003b3e: 655a str r2, [r3, #84] ; 0x54
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- 8003b40: 68fb ldr r3, [r7, #12]
- 8003b42: 681b ldr r3, [r3, #0]
- 8003b44: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003b46: 68bb ldr r3, [r7, #8]
- 8003b48: 691b ldr r3, [r3, #16]
- 8003b4a: 021a lsls r2, r3, #8
- 8003b4c: 68fb ldr r3, [r7, #12]
- 8003b4e: 681b ldr r3, [r3, #0]
- 8003b50: 430a orrs r2, r1
- 8003b52: 655a str r2, [r3, #84] ; 0x54
- break;
- 8003b54: e000 b.n 8003b58 <HAL_TIM_PWM_ConfigChannel+0x214>
- }
-
- default:
- break;
- 8003b56: bf00 nop
- }
-
- htim->State = HAL_TIM_STATE_READY;
- 8003b58: 68fb ldr r3, [r7, #12]
- 8003b5a: 2201 movs r2, #1
- 8003b5c: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003b60: 68fb ldr r3, [r7, #12]
- 8003b62: 2200 movs r2, #0
- 8003b64: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003b68: 2300 movs r3, #0
-}
- 8003b6a: 4618 mov r0, r3
- 8003b6c: 3710 adds r7, #16
- 8003b6e: 46bd mov sp, r7
- 8003b70: bd80 pop {r7, pc}
- 8003b72: bf00 nop
-
-08003b74 <HAL_TIM_ConfigClockSource>:
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- 8003b74: b580 push {r7, lr}
- 8003b76: b084 sub sp, #16
- 8003b78: af00 add r7, sp, #0
- 8003b7a: 6078 str r0, [r7, #4]
- 8003b7c: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 8003b7e: 687b ldr r3, [r7, #4]
- 8003b80: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8003b84: 2b01 cmp r3, #1
- 8003b86: d101 bne.n 8003b8c <HAL_TIM_ConfigClockSource+0x18>
- 8003b88: 2302 movs r3, #2
- 8003b8a: e0a6 b.n 8003cda <HAL_TIM_ConfigClockSource+0x166>
- 8003b8c: 687b ldr r3, [r7, #4]
- 8003b8e: 2201 movs r2, #1
- 8003b90: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8003b94: 687b ldr r3, [r7, #4]
- 8003b96: 2202 movs r2, #2
- 8003b98: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- 8003b9c: 687b ldr r3, [r7, #4]
- 8003b9e: 681b ldr r3, [r3, #0]
- 8003ba0: 689b ldr r3, [r3, #8]
- 8003ba2: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 8003ba4: 68fa ldr r2, [r7, #12]
- 8003ba6: 4b4f ldr r3, [pc, #316] ; (8003ce4 <HAL_TIM_ConfigClockSource+0x170>)
- 8003ba8: 4013 ands r3, r2
- 8003baa: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8003bac: 68fb ldr r3, [r7, #12]
- 8003bae: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8003bb2: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003bb4: 687b ldr r3, [r7, #4]
- 8003bb6: 681b ldr r3, [r3, #0]
- 8003bb8: 68fa ldr r2, [r7, #12]
- 8003bba: 609a str r2, [r3, #8]
-
- switch (sClockSourceConfig->ClockSource)
- 8003bbc: 683b ldr r3, [r7, #0]
- 8003bbe: 681b ldr r3, [r3, #0]
- 8003bc0: 2b40 cmp r3, #64 ; 0x40
- 8003bc2: d067 beq.n 8003c94 <HAL_TIM_ConfigClockSource+0x120>
- 8003bc4: 2b40 cmp r3, #64 ; 0x40
- 8003bc6: d80b bhi.n 8003be0 <HAL_TIM_ConfigClockSource+0x6c>
- 8003bc8: 2b10 cmp r3, #16
- 8003bca: d073 beq.n 8003cb4 <HAL_TIM_ConfigClockSource+0x140>
- 8003bcc: 2b10 cmp r3, #16
- 8003bce: d802 bhi.n 8003bd6 <HAL_TIM_ConfigClockSource+0x62>
- 8003bd0: 2b00 cmp r3, #0
- 8003bd2: d06f beq.n 8003cb4 <HAL_TIM_ConfigClockSource+0x140>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- break;
- 8003bd4: e078 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003bd6: 2b20 cmp r3, #32
- 8003bd8: d06c beq.n 8003cb4 <HAL_TIM_ConfigClockSource+0x140>
- 8003bda: 2b30 cmp r3, #48 ; 0x30
- 8003bdc: d06a beq.n 8003cb4 <HAL_TIM_ConfigClockSource+0x140>
- break;
- 8003bde: e073 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003be0: 2b70 cmp r3, #112 ; 0x70
- 8003be2: d00d beq.n 8003c00 <HAL_TIM_ConfigClockSource+0x8c>
- 8003be4: 2b70 cmp r3, #112 ; 0x70
- 8003be6: d804 bhi.n 8003bf2 <HAL_TIM_ConfigClockSource+0x7e>
- 8003be8: 2b50 cmp r3, #80 ; 0x50
- 8003bea: d033 beq.n 8003c54 <HAL_TIM_ConfigClockSource+0xe0>
- 8003bec: 2b60 cmp r3, #96 ; 0x60
- 8003bee: d041 beq.n 8003c74 <HAL_TIM_ConfigClockSource+0x100>
- break;
- 8003bf0: e06a b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8003bf2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8003bf6: d066 beq.n 8003cc6 <HAL_TIM_ConfigClockSource+0x152>
- 8003bf8: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8003bfc: d017 beq.n 8003c2e <HAL_TIM_ConfigClockSource+0xba>
- break;
- 8003bfe: e063 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003c00: 687b ldr r3, [r7, #4]
- 8003c02: 6818 ldr r0, [r3, #0]
- 8003c04: 683b ldr r3, [r7, #0]
- 8003c06: 6899 ldr r1, [r3, #8]
- 8003c08: 683b ldr r3, [r7, #0]
- 8003c0a: 685a ldr r2, [r3, #4]
- 8003c0c: 683b ldr r3, [r7, #0]
- 8003c0e: 68db ldr r3, [r3, #12]
- 8003c10: f000 fc0a bl 8004428 <TIM_ETR_SetConfig>
- tmpsmcr = htim->Instance->SMCR;
- 8003c14: 687b ldr r3, [r7, #4]
- 8003c16: 681b ldr r3, [r3, #0]
- 8003c18: 689b ldr r3, [r3, #8]
- 8003c1a: 60fb str r3, [r7, #12]
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8003c1c: 68fb ldr r3, [r7, #12]
- 8003c1e: f043 0377 orr.w r3, r3, #119 ; 0x77
- 8003c22: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8003c24: 687b ldr r3, [r7, #4]
- 8003c26: 681b ldr r3, [r3, #0]
- 8003c28: 68fa ldr r2, [r7, #12]
- 8003c2a: 609a str r2, [r3, #8]
- break;
- 8003c2c: e04c b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8003c2e: 687b ldr r3, [r7, #4]
- 8003c30: 6818 ldr r0, [r3, #0]
- 8003c32: 683b ldr r3, [r7, #0]
- 8003c34: 6899 ldr r1, [r3, #8]
- 8003c36: 683b ldr r3, [r7, #0]
- 8003c38: 685a ldr r2, [r3, #4]
- 8003c3a: 683b ldr r3, [r7, #0]
- 8003c3c: 68db ldr r3, [r3, #12]
- 8003c3e: f000 fbf3 bl 8004428 <TIM_ETR_SetConfig>
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- 8003c42: 687b ldr r3, [r7, #4]
- 8003c44: 681b ldr r3, [r3, #0]
- 8003c46: 689a ldr r2, [r3, #8]
- 8003c48: 687b ldr r3, [r7, #4]
- 8003c4a: 681b ldr r3, [r3, #0]
- 8003c4c: f442 4280 orr.w r2, r2, #16384 ; 0x4000
- 8003c50: 609a str r2, [r3, #8]
- break;
- 8003c52: e039 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003c54: 687b ldr r3, [r7, #4]
- 8003c56: 6818 ldr r0, [r3, #0]
- 8003c58: 683b ldr r3, [r7, #0]
- 8003c5a: 6859 ldr r1, [r3, #4]
- 8003c5c: 683b ldr r3, [r7, #0]
- 8003c5e: 68db ldr r3, [r3, #12]
- 8003c60: 461a mov r2, r3
- 8003c62: f000 fb67 bl 8004334 <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 8003c66: 687b ldr r3, [r7, #4]
- 8003c68: 681b ldr r3, [r3, #0]
- 8003c6a: 2150 movs r1, #80 ; 0x50
- 8003c6c: 4618 mov r0, r3
- 8003c6e: f000 fbc0 bl 80043f2 <TIM_ITRx_SetConfig>
- break;
- 8003c72: e029 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI2_ConfigInputStage(htim->Instance,
- 8003c74: 687b ldr r3, [r7, #4]
- 8003c76: 6818 ldr r0, [r3, #0]
- 8003c78: 683b ldr r3, [r7, #0]
- 8003c7a: 6859 ldr r1, [r3, #4]
- 8003c7c: 683b ldr r3, [r7, #0]
- 8003c7e: 68db ldr r3, [r3, #12]
- 8003c80: 461a mov r2, r3
- 8003c82: f000 fb86 bl 8004392 <TIM_TI2_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 8003c86: 687b ldr r3, [r7, #4]
- 8003c88: 681b ldr r3, [r3, #0]
- 8003c8a: 2160 movs r1, #96 ; 0x60
- 8003c8c: 4618 mov r0, r3
- 8003c8e: f000 fbb0 bl 80043f2 <TIM_ITRx_SetConfig>
- break;
- 8003c92: e019 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8003c94: 687b ldr r3, [r7, #4]
- 8003c96: 6818 ldr r0, [r3, #0]
- 8003c98: 683b ldr r3, [r7, #0]
- 8003c9a: 6859 ldr r1, [r3, #4]
- 8003c9c: 683b ldr r3, [r7, #0]
- 8003c9e: 68db ldr r3, [r3, #12]
- 8003ca0: 461a mov r2, r3
- 8003ca2: f000 fb47 bl 8004334 <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 8003ca6: 687b ldr r3, [r7, #4]
- 8003ca8: 681b ldr r3, [r3, #0]
- 8003caa: 2140 movs r1, #64 ; 0x40
- 8003cac: 4618 mov r0, r3
- 8003cae: f000 fba0 bl 80043f2 <TIM_ITRx_SetConfig>
- break;
- 8003cb2: e009 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 8003cb4: 687b ldr r3, [r7, #4]
- 8003cb6: 681a ldr r2, [r3, #0]
- 8003cb8: 683b ldr r3, [r7, #0]
- 8003cba: 681b ldr r3, [r3, #0]
- 8003cbc: 4619 mov r1, r3
- 8003cbe: 4610 mov r0, r2
- 8003cc0: f000 fb97 bl 80043f2 <TIM_ITRx_SetConfig>
- break;
- 8003cc4: e000 b.n 8003cc8 <HAL_TIM_ConfigClockSource+0x154>
- break;
- 8003cc6: bf00 nop
- }
- htim->State = HAL_TIM_STATE_READY;
- 8003cc8: 687b ldr r3, [r7, #4]
- 8003cca: 2201 movs r2, #1
- 8003ccc: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8003cd0: 687b ldr r3, [r7, #4]
- 8003cd2: 2200 movs r2, #0
- 8003cd4: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8003cd8: 2300 movs r3, #0
-}
- 8003cda: 4618 mov r0, r3
- 8003cdc: 3710 adds r7, #16
- 8003cde: 46bd mov sp, r7
- 8003ce0: bd80 pop {r7, pc}
- 8003ce2: bf00 nop
- 8003ce4: fffeff88 .word 0xfffeff88
-
-08003ce8 <HAL_TIM_OC_DelayElapsedCallback>:
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- 8003ce8: b480 push {r7}
- 8003cea: b083 sub sp, #12
- 8003cec: af00 add r7, sp, #0
- 8003cee: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
- 8003cf0: bf00 nop
- 8003cf2: 370c adds r7, #12
- 8003cf4: 46bd mov sp, r7
- 8003cf6: f85d 7b04 ldr.w r7, [sp], #4
- 8003cfa: 4770 bx lr
-
-08003cfc <HAL_TIM_IC_CaptureCallback>:
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- 8003cfc: b480 push {r7}
- 8003cfe: b083 sub sp, #12
- 8003d00: af00 add r7, sp, #0
- 8003d02: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
- 8003d04: bf00 nop
- 8003d06: 370c adds r7, #12
- 8003d08: 46bd mov sp, r7
- 8003d0a: f85d 7b04 ldr.w r7, [sp], #4
- 8003d0e: 4770 bx lr
-
-08003d10 <HAL_TIM_PWM_PulseFinishedCallback>:
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- 8003d10: b480 push {r7}
- 8003d12: b083 sub sp, #12
- 8003d14: af00 add r7, sp, #0
- 8003d16: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
- 8003d18: bf00 nop
- 8003d1a: 370c adds r7, #12
- 8003d1c: 46bd mov sp, r7
- 8003d1e: f85d 7b04 ldr.w r7, [sp], #4
- 8003d22: 4770 bx lr
-
-08003d24 <HAL_TIM_TriggerCallback>:
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- 8003d24: b480 push {r7}
- 8003d26: b083 sub sp, #12
- 8003d28: af00 add r7, sp, #0
- 8003d2a: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
- 8003d2c: bf00 nop
- 8003d2e: 370c adds r7, #12
- 8003d30: 46bd mov sp, r7
- 8003d32: f85d 7b04 ldr.w r7, [sp], #4
- 8003d36: 4770 bx lr
-
-08003d38 <TIM_Base_SetConfig>:
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- 8003d38: b480 push {r7}
- 8003d3a: b085 sub sp, #20
- 8003d3c: af00 add r7, sp, #0
- 8003d3e: 6078 str r0, [r7, #4]
- 8003d40: 6039 str r1, [r7, #0]
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
- 8003d42: 687b ldr r3, [r7, #4]
- 8003d44: 681b ldr r3, [r3, #0]
- 8003d46: 60fb str r3, [r7, #12]
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8003d48: 687b ldr r3, [r7, #4]
- 8003d4a: 4a40 ldr r2, [pc, #256] ; (8003e4c <TIM_Base_SetConfig+0x114>)
- 8003d4c: 4293 cmp r3, r2
- 8003d4e: d013 beq.n 8003d78 <TIM_Base_SetConfig+0x40>
- 8003d50: 687b ldr r3, [r7, #4]
- 8003d52: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003d56: d00f beq.n 8003d78 <TIM_Base_SetConfig+0x40>
- 8003d58: 687b ldr r3, [r7, #4]
- 8003d5a: 4a3d ldr r2, [pc, #244] ; (8003e50 <TIM_Base_SetConfig+0x118>)
- 8003d5c: 4293 cmp r3, r2
- 8003d5e: d00b beq.n 8003d78 <TIM_Base_SetConfig+0x40>
- 8003d60: 687b ldr r3, [r7, #4]
- 8003d62: 4a3c ldr r2, [pc, #240] ; (8003e54 <TIM_Base_SetConfig+0x11c>)
- 8003d64: 4293 cmp r3, r2
- 8003d66: d007 beq.n 8003d78 <TIM_Base_SetConfig+0x40>
- 8003d68: 687b ldr r3, [r7, #4]
- 8003d6a: 4a3b ldr r2, [pc, #236] ; (8003e58 <TIM_Base_SetConfig+0x120>)
- 8003d6c: 4293 cmp r3, r2
- 8003d6e: d003 beq.n 8003d78 <TIM_Base_SetConfig+0x40>
- 8003d70: 687b ldr r3, [r7, #4]
- 8003d72: 4a3a ldr r2, [pc, #232] ; (8003e5c <TIM_Base_SetConfig+0x124>)
- 8003d74: 4293 cmp r3, r2
- 8003d76: d108 bne.n 8003d8a <TIM_Base_SetConfig+0x52>
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 8003d78: 68fb ldr r3, [r7, #12]
- 8003d7a: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8003d7e: 60fb str r3, [r7, #12]
- tmpcr1 |= Structure->CounterMode;
- 8003d80: 683b ldr r3, [r7, #0]
- 8003d82: 685b ldr r3, [r3, #4]
- 8003d84: 68fa ldr r2, [r7, #12]
- 8003d86: 4313 orrs r3, r2
- 8003d88: 60fb str r3, [r7, #12]
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 8003d8a: 687b ldr r3, [r7, #4]
- 8003d8c: 4a2f ldr r2, [pc, #188] ; (8003e4c <TIM_Base_SetConfig+0x114>)
- 8003d8e: 4293 cmp r3, r2
- 8003d90: d02b beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003d92: 687b ldr r3, [r7, #4]
- 8003d94: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003d98: d027 beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003d9a: 687b ldr r3, [r7, #4]
- 8003d9c: 4a2c ldr r2, [pc, #176] ; (8003e50 <TIM_Base_SetConfig+0x118>)
- 8003d9e: 4293 cmp r3, r2
- 8003da0: d023 beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003da2: 687b ldr r3, [r7, #4]
- 8003da4: 4a2b ldr r2, [pc, #172] ; (8003e54 <TIM_Base_SetConfig+0x11c>)
- 8003da6: 4293 cmp r3, r2
- 8003da8: d01f beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003daa: 687b ldr r3, [r7, #4]
- 8003dac: 4a2a ldr r2, [pc, #168] ; (8003e58 <TIM_Base_SetConfig+0x120>)
- 8003dae: 4293 cmp r3, r2
- 8003db0: d01b beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003db2: 687b ldr r3, [r7, #4]
- 8003db4: 4a29 ldr r2, [pc, #164] ; (8003e5c <TIM_Base_SetConfig+0x124>)
- 8003db6: 4293 cmp r3, r2
- 8003db8: d017 beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003dba: 687b ldr r3, [r7, #4]
- 8003dbc: 4a28 ldr r2, [pc, #160] ; (8003e60 <TIM_Base_SetConfig+0x128>)
- 8003dbe: 4293 cmp r3, r2
- 8003dc0: d013 beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003dc2: 687b ldr r3, [r7, #4]
- 8003dc4: 4a27 ldr r2, [pc, #156] ; (8003e64 <TIM_Base_SetConfig+0x12c>)
- 8003dc6: 4293 cmp r3, r2
- 8003dc8: d00f beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003dca: 687b ldr r3, [r7, #4]
- 8003dcc: 4a26 ldr r2, [pc, #152] ; (8003e68 <TIM_Base_SetConfig+0x130>)
- 8003dce: 4293 cmp r3, r2
- 8003dd0: d00b beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003dd2: 687b ldr r3, [r7, #4]
- 8003dd4: 4a25 ldr r2, [pc, #148] ; (8003e6c <TIM_Base_SetConfig+0x134>)
- 8003dd6: 4293 cmp r3, r2
- 8003dd8: d007 beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003dda: 687b ldr r3, [r7, #4]
- 8003ddc: 4a24 ldr r2, [pc, #144] ; (8003e70 <TIM_Base_SetConfig+0x138>)
- 8003dde: 4293 cmp r3, r2
- 8003de0: d003 beq.n 8003dea <TIM_Base_SetConfig+0xb2>
- 8003de2: 687b ldr r3, [r7, #4]
- 8003de4: 4a23 ldr r2, [pc, #140] ; (8003e74 <TIM_Base_SetConfig+0x13c>)
- 8003de6: 4293 cmp r3, r2
- 8003de8: d108 bne.n 8003dfc <TIM_Base_SetConfig+0xc4>
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- 8003dea: 68fb ldr r3, [r7, #12]
- 8003dec: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003df0: 60fb str r3, [r7, #12]
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 8003df2: 683b ldr r3, [r7, #0]
- 8003df4: 68db ldr r3, [r3, #12]
- 8003df6: 68fa ldr r2, [r7, #12]
- 8003df8: 4313 orrs r3, r2
- 8003dfa: 60fb str r3, [r7, #12]
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8003dfc: 68fb ldr r3, [r7, #12]
- 8003dfe: f023 0280 bic.w r2, r3, #128 ; 0x80
- 8003e02: 683b ldr r3, [r7, #0]
- 8003e04: 695b ldr r3, [r3, #20]
- 8003e06: 4313 orrs r3, r2
- 8003e08: 60fb str r3, [r7, #12]
-
- TIMx->CR1 = tmpcr1;
- 8003e0a: 687b ldr r3, [r7, #4]
- 8003e0c: 68fa ldr r2, [r7, #12]
- 8003e0e: 601a str r2, [r3, #0]
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
- 8003e10: 683b ldr r3, [r7, #0]
- 8003e12: 689a ldr r2, [r3, #8]
- 8003e14: 687b ldr r3, [r7, #4]
- 8003e16: 62da str r2, [r3, #44] ; 0x2c
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
- 8003e18: 683b ldr r3, [r7, #0]
- 8003e1a: 681a ldr r2, [r3, #0]
- 8003e1c: 687b ldr r3, [r7, #4]
- 8003e1e: 629a str r2, [r3, #40] ; 0x28
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8003e20: 687b ldr r3, [r7, #4]
- 8003e22: 4a0a ldr r2, [pc, #40] ; (8003e4c <TIM_Base_SetConfig+0x114>)
- 8003e24: 4293 cmp r3, r2
- 8003e26: d003 beq.n 8003e30 <TIM_Base_SetConfig+0xf8>
- 8003e28: 687b ldr r3, [r7, #4]
- 8003e2a: 4a0c ldr r2, [pc, #48] ; (8003e5c <TIM_Base_SetConfig+0x124>)
- 8003e2c: 4293 cmp r3, r2
- 8003e2e: d103 bne.n 8003e38 <TIM_Base_SetConfig+0x100>
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- 8003e30: 683b ldr r3, [r7, #0]
- 8003e32: 691a ldr r2, [r3, #16]
- 8003e34: 687b ldr r3, [r7, #4]
- 8003e36: 631a str r2, [r3, #48] ; 0x30
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
- 8003e38: 687b ldr r3, [r7, #4]
- 8003e3a: 2201 movs r2, #1
- 8003e3c: 615a str r2, [r3, #20]
-}
- 8003e3e: bf00 nop
- 8003e40: 3714 adds r7, #20
- 8003e42: 46bd mov sp, r7
- 8003e44: f85d 7b04 ldr.w r7, [sp], #4
- 8003e48: 4770 bx lr
- 8003e4a: bf00 nop
- 8003e4c: 40010000 .word 0x40010000
- 8003e50: 40000400 .word 0x40000400
- 8003e54: 40000800 .word 0x40000800
- 8003e58: 40000c00 .word 0x40000c00
- 8003e5c: 40010400 .word 0x40010400
- 8003e60: 40014000 .word 0x40014000
- 8003e64: 40014400 .word 0x40014400
- 8003e68: 40014800 .word 0x40014800
- 8003e6c: 40001800 .word 0x40001800
- 8003e70: 40001c00 .word 0x40001c00
- 8003e74: 40002000 .word 0x40002000
-
-08003e78 <TIM_OC1_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003e78: b480 push {r7}
- 8003e7a: b087 sub sp, #28
- 8003e7c: af00 add r7, sp, #0
- 8003e7e: 6078 str r0, [r7, #4]
- 8003e80: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 8003e82: 687b ldr r3, [r7, #4]
- 8003e84: 6a1b ldr r3, [r3, #32]
- 8003e86: f023 0201 bic.w r2, r3, #1
- 8003e8a: 687b ldr r3, [r7, #4]
- 8003e8c: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8003e8e: 687b ldr r3, [r7, #4]
- 8003e90: 6a1b ldr r3, [r3, #32]
- 8003e92: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8003e94: 687b ldr r3, [r7, #4]
- 8003e96: 685b ldr r3, [r3, #4]
- 8003e98: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 8003e9a: 687b ldr r3, [r7, #4]
- 8003e9c: 699b ldr r3, [r3, #24]
- 8003e9e: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~TIM_CCMR1_OC1M;
- 8003ea0: 68fa ldr r2, [r7, #12]
- 8003ea2: 4b2b ldr r3, [pc, #172] ; (8003f50 <TIM_OC1_SetConfig+0xd8>)
- 8003ea4: 4013 ands r3, r2
- 8003ea6: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC1S;
- 8003ea8: 68fb ldr r3, [r7, #12]
- 8003eaa: f023 0303 bic.w r3, r3, #3
- 8003eae: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8003eb0: 683b ldr r3, [r7, #0]
- 8003eb2: 681b ldr r3, [r3, #0]
- 8003eb4: 68fa ldr r2, [r7, #12]
- 8003eb6: 4313 orrs r3, r2
- 8003eb8: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC1P;
- 8003eba: 697b ldr r3, [r7, #20]
- 8003ebc: f023 0302 bic.w r3, r3, #2
- 8003ec0: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= OC_Config->OCPolarity;
- 8003ec2: 683b ldr r3, [r7, #0]
- 8003ec4: 689b ldr r3, [r3, #8]
- 8003ec6: 697a ldr r2, [r7, #20]
- 8003ec8: 4313 orrs r3, r2
- 8003eca: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- 8003ecc: 687b ldr r3, [r7, #4]
- 8003ece: 4a21 ldr r2, [pc, #132] ; (8003f54 <TIM_OC1_SetConfig+0xdc>)
- 8003ed0: 4293 cmp r3, r2
- 8003ed2: d003 beq.n 8003edc <TIM_OC1_SetConfig+0x64>
- 8003ed4: 687b ldr r3, [r7, #4]
- 8003ed6: 4a20 ldr r2, [pc, #128] ; (8003f58 <TIM_OC1_SetConfig+0xe0>)
- 8003ed8: 4293 cmp r3, r2
- 8003eda: d10c bne.n 8003ef6 <TIM_OC1_SetConfig+0x7e>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC1NP;
- 8003edc: 697b ldr r3, [r7, #20]
- 8003ede: f023 0308 bic.w r3, r3, #8
- 8003ee2: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= OC_Config->OCNPolarity;
- 8003ee4: 683b ldr r3, [r7, #0]
- 8003ee6: 68db ldr r3, [r3, #12]
- 8003ee8: 697a ldr r2, [r7, #20]
- 8003eea: 4313 orrs r3, r2
- 8003eec: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC1NE;
- 8003eee: 697b ldr r3, [r7, #20]
- 8003ef0: f023 0304 bic.w r3, r3, #4
- 8003ef4: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003ef6: 687b ldr r3, [r7, #4]
- 8003ef8: 4a16 ldr r2, [pc, #88] ; (8003f54 <TIM_OC1_SetConfig+0xdc>)
- 8003efa: 4293 cmp r3, r2
- 8003efc: d003 beq.n 8003f06 <TIM_OC1_SetConfig+0x8e>
- 8003efe: 687b ldr r3, [r7, #4]
- 8003f00: 4a15 ldr r2, [pc, #84] ; (8003f58 <TIM_OC1_SetConfig+0xe0>)
- 8003f02: 4293 cmp r3, r2
- 8003f04: d111 bne.n 8003f2a <TIM_OC1_SetConfig+0xb2>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS1;
- 8003f06: 693b ldr r3, [r7, #16]
- 8003f08: f423 7380 bic.w r3, r3, #256 ; 0x100
- 8003f0c: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS1N;
- 8003f0e: 693b ldr r3, [r7, #16]
- 8003f10: f423 7300 bic.w r3, r3, #512 ; 0x200
- 8003f14: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= OC_Config->OCIdleState;
- 8003f16: 683b ldr r3, [r7, #0]
- 8003f18: 695b ldr r3, [r3, #20]
- 8003f1a: 693a ldr r2, [r7, #16]
- 8003f1c: 4313 orrs r3, r2
- 8003f1e: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= OC_Config->OCNIdleState;
- 8003f20: 683b ldr r3, [r7, #0]
- 8003f22: 699b ldr r3, [r3, #24]
- 8003f24: 693a ldr r2, [r7, #16]
- 8003f26: 4313 orrs r3, r2
- 8003f28: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8003f2a: 687b ldr r3, [r7, #4]
- 8003f2c: 693a ldr r2, [r7, #16]
- 8003f2e: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 8003f30: 687b ldr r3, [r7, #4]
- 8003f32: 68fa ldr r2, [r7, #12]
- 8003f34: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = OC_Config->Pulse;
- 8003f36: 683b ldr r3, [r7, #0]
- 8003f38: 685a ldr r2, [r3, #4]
- 8003f3a: 687b ldr r3, [r7, #4]
- 8003f3c: 635a str r2, [r3, #52] ; 0x34
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8003f3e: 687b ldr r3, [r7, #4]
- 8003f40: 697a ldr r2, [r7, #20]
- 8003f42: 621a str r2, [r3, #32]
-}
- 8003f44: bf00 nop
- 8003f46: 371c adds r7, #28
- 8003f48: 46bd mov sp, r7
- 8003f4a: f85d 7b04 ldr.w r7, [sp], #4
- 8003f4e: 4770 bx lr
- 8003f50: fffeff8f .word 0xfffeff8f
- 8003f54: 40010000 .word 0x40010000
- 8003f58: 40010400 .word 0x40010400
-
-08003f5c <TIM_OC2_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8003f5c: b480 push {r7}
- 8003f5e: b087 sub sp, #28
- 8003f60: af00 add r7, sp, #0
- 8003f62: 6078 str r0, [r7, #4]
- 8003f64: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 8003f66: 687b ldr r3, [r7, #4]
- 8003f68: 6a1b ldr r3, [r3, #32]
- 8003f6a: f023 0210 bic.w r2, r3, #16
- 8003f6e: 687b ldr r3, [r7, #4]
- 8003f70: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8003f72: 687b ldr r3, [r7, #4]
- 8003f74: 6a1b ldr r3, [r3, #32]
- 8003f76: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8003f78: 687b ldr r3, [r7, #4]
- 8003f7a: 685b ldr r3, [r3, #4]
- 8003f7c: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
- 8003f7e: 687b ldr r3, [r7, #4]
- 8003f80: 699b ldr r3, [r3, #24]
- 8003f82: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- 8003f84: 68fa ldr r2, [r7, #12]
- 8003f86: 4b2e ldr r3, [pc, #184] ; (8004040 <TIM_OC2_SetConfig+0xe4>)
- 8003f88: 4013 ands r3, r2
- 8003f8a: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR1_CC2S;
- 8003f8c: 68fb ldr r3, [r7, #12]
- 8003f8e: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003f92: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 8003f94: 683b ldr r3, [r7, #0]
- 8003f96: 681b ldr r3, [r3, #0]
- 8003f98: 021b lsls r3, r3, #8
- 8003f9a: 68fa ldr r2, [r7, #12]
- 8003f9c: 4313 orrs r3, r2
- 8003f9e: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- 8003fa0: 697b ldr r3, [r7, #20]
- 8003fa2: f023 0320 bic.w r3, r3, #32
- 8003fa6: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
- 8003fa8: 683b ldr r3, [r7, #0]
- 8003faa: 689b ldr r3, [r3, #8]
- 8003fac: 011b lsls r3, r3, #4
- 8003fae: 697a ldr r2, [r7, #20]
- 8003fb0: 4313 orrs r3, r2
- 8003fb2: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- 8003fb4: 687b ldr r3, [r7, #4]
- 8003fb6: 4a23 ldr r2, [pc, #140] ; (8004044 <TIM_OC2_SetConfig+0xe8>)
- 8003fb8: 4293 cmp r3, r2
- 8003fba: d003 beq.n 8003fc4 <TIM_OC2_SetConfig+0x68>
- 8003fbc: 687b ldr r3, [r7, #4]
- 8003fbe: 4a22 ldr r2, [pc, #136] ; (8004048 <TIM_OC2_SetConfig+0xec>)
- 8003fc0: 4293 cmp r3, r2
- 8003fc2: d10d bne.n 8003fe0 <TIM_OC2_SetConfig+0x84>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- 8003fc4: 697b ldr r3, [r7, #20]
- 8003fc6: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8003fca: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- 8003fcc: 683b ldr r3, [r7, #0]
- 8003fce: 68db ldr r3, [r3, #12]
- 8003fd0: 011b lsls r3, r3, #4
- 8003fd2: 697a ldr r2, [r7, #20]
- 8003fd4: 4313 orrs r3, r2
- 8003fd6: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
- 8003fd8: 697b ldr r3, [r7, #20]
- 8003fda: f023 0340 bic.w r3, r3, #64 ; 0x40
- 8003fde: 617b str r3, [r7, #20]
-
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003fe0: 687b ldr r3, [r7, #4]
- 8003fe2: 4a18 ldr r2, [pc, #96] ; (8004044 <TIM_OC2_SetConfig+0xe8>)
- 8003fe4: 4293 cmp r3, r2
- 8003fe6: d003 beq.n 8003ff0 <TIM_OC2_SetConfig+0x94>
- 8003fe8: 687b ldr r3, [r7, #4]
- 8003fea: 4a17 ldr r2, [pc, #92] ; (8004048 <TIM_OC2_SetConfig+0xec>)
- 8003fec: 4293 cmp r3, r2
- 8003fee: d113 bne.n 8004018 <TIM_OC2_SetConfig+0xbc>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- 8003ff0: 693b ldr r3, [r7, #16]
- 8003ff2: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 8003ff6: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS2N;
- 8003ff8: 693b ldr r3, [r7, #16]
- 8003ffa: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8003ffe: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- 8004000: 683b ldr r3, [r7, #0]
- 8004002: 695b ldr r3, [r3, #20]
- 8004004: 009b lsls r3, r3, #2
- 8004006: 693a ldr r2, [r7, #16]
- 8004008: 4313 orrs r3, r2
- 800400a: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- 800400c: 683b ldr r3, [r7, #0]
- 800400e: 699b ldr r3, [r3, #24]
- 8004010: 009b lsls r3, r3, #2
- 8004012: 693a ldr r2, [r7, #16]
- 8004014: 4313 orrs r3, r2
- 8004016: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004018: 687b ldr r3, [r7, #4]
- 800401a: 693a ldr r2, [r7, #16]
- 800401c: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
- 800401e: 687b ldr r3, [r7, #4]
- 8004020: 68fa ldr r2, [r7, #12]
- 8004022: 619a str r2, [r3, #24]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
- 8004024: 683b ldr r3, [r7, #0]
- 8004026: 685a ldr r2, [r3, #4]
- 8004028: 687b ldr r3, [r7, #4]
- 800402a: 639a str r2, [r3, #56] ; 0x38
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 800402c: 687b ldr r3, [r7, #4]
- 800402e: 697a ldr r2, [r7, #20]
- 8004030: 621a str r2, [r3, #32]
-}
- 8004032: bf00 nop
- 8004034: 371c adds r7, #28
- 8004036: 46bd mov sp, r7
- 8004038: f85d 7b04 ldr.w r7, [sp], #4
- 800403c: 4770 bx lr
- 800403e: bf00 nop
- 8004040: feff8fff .word 0xfeff8fff
- 8004044: 40010000 .word 0x40010000
- 8004048: 40010400 .word 0x40010400
-
-0800404c <TIM_OC3_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 800404c: b480 push {r7}
- 800404e: b087 sub sp, #28
- 8004050: af00 add r7, sp, #0
- 8004052: 6078 str r0, [r7, #4]
- 8004054: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 3: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC3E;
- 8004056: 687b ldr r3, [r7, #4]
- 8004058: 6a1b ldr r3, [r3, #32]
- 800405a: f423 7280 bic.w r2, r3, #256 ; 0x100
- 800405e: 687b ldr r3, [r7, #4]
- 8004060: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 8004062: 687b ldr r3, [r7, #4]
- 8004064: 6a1b ldr r3, [r3, #32]
- 8004066: 617b str r3, [r7, #20]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004068: 687b ldr r3, [r7, #4]
- 800406a: 685b ldr r3, [r3, #4]
- 800406c: 613b str r3, [r7, #16]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 800406e: 687b ldr r3, [r7, #4]
- 8004070: 69db ldr r3, [r3, #28]
- 8004072: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC3M;
- 8004074: 68fa ldr r2, [r7, #12]
- 8004076: 4b2d ldr r3, [pc, #180] ; (800412c <TIM_OC3_SetConfig+0xe0>)
- 8004078: 4013 ands r3, r2
- 800407a: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC3S;
- 800407c: 68fb ldr r3, [r7, #12]
- 800407e: f023 0303 bic.w r3, r3, #3
- 8004082: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8004084: 683b ldr r3, [r7, #0]
- 8004086: 681b ldr r3, [r3, #0]
- 8004088: 68fa ldr r2, [r7, #12]
- 800408a: 4313 orrs r3, r2
- 800408c: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC3P;
- 800408e: 697b ldr r3, [r7, #20]
- 8004090: f423 7300 bic.w r3, r3, #512 ; 0x200
- 8004094: 617b str r3, [r7, #20]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8U);
- 8004096: 683b ldr r3, [r7, #0]
- 8004098: 689b ldr r3, [r3, #8]
- 800409a: 021b lsls r3, r3, #8
- 800409c: 697a ldr r2, [r7, #20]
- 800409e: 4313 orrs r3, r2
- 80040a0: 617b str r3, [r7, #20]
-
- if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- 80040a2: 687b ldr r3, [r7, #4]
- 80040a4: 4a22 ldr r2, [pc, #136] ; (8004130 <TIM_OC3_SetConfig+0xe4>)
- 80040a6: 4293 cmp r3, r2
- 80040a8: d003 beq.n 80040b2 <TIM_OC3_SetConfig+0x66>
- 80040aa: 687b ldr r3, [r7, #4]
- 80040ac: 4a21 ldr r2, [pc, #132] ; (8004134 <TIM_OC3_SetConfig+0xe8>)
- 80040ae: 4293 cmp r3, r2
- 80040b0: d10d bne.n 80040ce <TIM_OC3_SetConfig+0x82>
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC3NP;
- 80040b2: 697b ldr r3, [r7, #20]
- 80040b4: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 80040b8: 617b str r3, [r7, #20]
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8U);
- 80040ba: 683b ldr r3, [r7, #0]
- 80040bc: 68db ldr r3, [r3, #12]
- 80040be: 021b lsls r3, r3, #8
- 80040c0: 697a ldr r2, [r7, #20]
- 80040c2: 4313 orrs r3, r2
- 80040c4: 617b str r3, [r7, #20]
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC3NE;
- 80040c6: 697b ldr r3, [r7, #20]
- 80040c8: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 80040cc: 617b str r3, [r7, #20]
- }
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80040ce: 687b ldr r3, [r7, #4]
- 80040d0: 4a17 ldr r2, [pc, #92] ; (8004130 <TIM_OC3_SetConfig+0xe4>)
- 80040d2: 4293 cmp r3, r2
- 80040d4: d003 beq.n 80040de <TIM_OC3_SetConfig+0x92>
- 80040d6: 687b ldr r3, [r7, #4]
- 80040d8: 4a16 ldr r2, [pc, #88] ; (8004134 <TIM_OC3_SetConfig+0xe8>)
- 80040da: 4293 cmp r3, r2
- 80040dc: d113 bne.n 8004106 <TIM_OC3_SetConfig+0xba>
- /* Check parameters */
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS3;
- 80040de: 693b ldr r3, [r7, #16]
- 80040e0: f423 5380 bic.w r3, r3, #4096 ; 0x1000
- 80040e4: 613b str r3, [r7, #16]
- tmpcr2 &= ~TIM_CR2_OIS3N;
- 80040e6: 693b ldr r3, [r7, #16]
- 80040e8: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 80040ec: 613b str r3, [r7, #16]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4U);
- 80040ee: 683b ldr r3, [r7, #0]
- 80040f0: 695b ldr r3, [r3, #20]
- 80040f2: 011b lsls r3, r3, #4
- 80040f4: 693a ldr r2, [r7, #16]
- 80040f6: 4313 orrs r3, r2
- 80040f8: 613b str r3, [r7, #16]
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- 80040fa: 683b ldr r3, [r7, #0]
- 80040fc: 699b ldr r3, [r3, #24]
- 80040fe: 011b lsls r3, r3, #4
- 8004100: 693a ldr r2, [r7, #16]
- 8004102: 4313 orrs r3, r2
- 8004104: 613b str r3, [r7, #16]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004106: 687b ldr r3, [r7, #4]
- 8004108: 693a ldr r2, [r7, #16]
- 800410a: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 800410c: 687b ldr r3, [r7, #4]
- 800410e: 68fa ldr r2, [r7, #12]
- 8004110: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = OC_Config->Pulse;
- 8004112: 683b ldr r3, [r7, #0]
- 8004114: 685a ldr r2, [r3, #4]
- 8004116: 687b ldr r3, [r7, #4]
- 8004118: 63da str r2, [r3, #60] ; 0x3c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 800411a: 687b ldr r3, [r7, #4]
- 800411c: 697a ldr r2, [r7, #20]
- 800411e: 621a str r2, [r3, #32]
-}
- 8004120: bf00 nop
- 8004122: 371c adds r7, #28
- 8004124: 46bd mov sp, r7
- 8004126: f85d 7b04 ldr.w r7, [sp], #4
- 800412a: 4770 bx lr
- 800412c: fffeff8f .word 0xfffeff8f
- 8004130: 40010000 .word 0x40010000
- 8004134: 40010400 .word 0x40010400
-
-08004138 <TIM_OC4_SetConfig>:
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- 8004138: b480 push {r7}
- 800413a: b087 sub sp, #28
- 800413c: af00 add r7, sp, #0
- 800413e: 6078 str r0, [r7, #4]
- 8004140: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= ~TIM_CCER_CC4E;
- 8004142: 687b ldr r3, [r7, #4]
- 8004144: 6a1b ldr r3, [r3, #32]
- 8004146: f423 5280 bic.w r2, r3, #4096 ; 0x1000
- 800414a: 687b ldr r3, [r7, #4]
- 800414c: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 800414e: 687b ldr r3, [r7, #4]
- 8004150: 6a1b ldr r3, [r3, #32]
- 8004152: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004154: 687b ldr r3, [r7, #4]
- 8004156: 685b ldr r3, [r3, #4]
- 8004158: 617b str r3, [r7, #20]
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
- 800415a: 687b ldr r3, [r7, #4]
- 800415c: 69db ldr r3, [r3, #28]
- 800415e: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR2_OC4M;
- 8004160: 68fa ldr r2, [r7, #12]
- 8004162: 4b1e ldr r3, [pc, #120] ; (80041dc <TIM_OC4_SetConfig+0xa4>)
- 8004164: 4013 ands r3, r2
- 8004166: 60fb str r3, [r7, #12]
- tmpccmrx &= ~TIM_CCMR2_CC4S;
- 8004168: 68fb ldr r3, [r7, #12]
- 800416a: f423 7340 bic.w r3, r3, #768 ; 0x300
- 800416e: 60fb str r3, [r7, #12]
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 8004170: 683b ldr r3, [r7, #0]
- 8004172: 681b ldr r3, [r3, #0]
- 8004174: 021b lsls r3, r3, #8
- 8004176: 68fa ldr r2, [r7, #12]
- 8004178: 4313 orrs r3, r2
- 800417a: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC4P;
- 800417c: 693b ldr r3, [r7, #16]
- 800417e: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8004182: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12U);
- 8004184: 683b ldr r3, [r7, #0]
- 8004186: 689b ldr r3, [r3, #8]
- 8004188: 031b lsls r3, r3, #12
- 800418a: 693a ldr r2, [r7, #16]
- 800418c: 4313 orrs r3, r2
- 800418e: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8004190: 687b ldr r3, [r7, #4]
- 8004192: 4a13 ldr r2, [pc, #76] ; (80041e0 <TIM_OC4_SetConfig+0xa8>)
- 8004194: 4293 cmp r3, r2
- 8004196: d003 beq.n 80041a0 <TIM_OC4_SetConfig+0x68>
- 8004198: 687b ldr r3, [r7, #4]
- 800419a: 4a12 ldr r2, [pc, #72] ; (80041e4 <TIM_OC4_SetConfig+0xac>)
- 800419c: 4293 cmp r3, r2
- 800419e: d109 bne.n 80041b4 <TIM_OC4_SetConfig+0x7c>
- {
- /* Check parameters */
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS4;
- 80041a0: 697b ldr r3, [r7, #20]
- 80041a2: f423 4380 bic.w r3, r3, #16384 ; 0x4000
- 80041a6: 617b str r3, [r7, #20]
-
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6U);
- 80041a8: 683b ldr r3, [r7, #0]
- 80041aa: 695b ldr r3, [r3, #20]
- 80041ac: 019b lsls r3, r3, #6
- 80041ae: 697a ldr r2, [r7, #20]
- 80041b0: 4313 orrs r3, r2
- 80041b2: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 80041b4: 687b ldr r3, [r7, #4]
- 80041b6: 697a ldr r2, [r7, #20]
- 80041b8: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
- 80041ba: 687b ldr r3, [r7, #4]
- 80041bc: 68fa ldr r2, [r7, #12]
- 80041be: 61da str r2, [r3, #28]
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = OC_Config->Pulse;
- 80041c0: 683b ldr r3, [r7, #0]
- 80041c2: 685a ldr r2, [r3, #4]
- 80041c4: 687b ldr r3, [r7, #4]
- 80041c6: 641a str r2, [r3, #64] ; 0x40
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 80041c8: 687b ldr r3, [r7, #4]
- 80041ca: 693a ldr r2, [r7, #16]
- 80041cc: 621a str r2, [r3, #32]
-}
- 80041ce: bf00 nop
- 80041d0: 371c adds r7, #28
- 80041d2: 46bd mov sp, r7
- 80041d4: f85d 7b04 ldr.w r7, [sp], #4
- 80041d8: 4770 bx lr
- 80041da: bf00 nop
- 80041dc: feff8fff .word 0xfeff8fff
- 80041e0: 40010000 .word 0x40010000
- 80041e4: 40010400 .word 0x40010400
-
-080041e8 <TIM_OC5_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 80041e8: b480 push {r7}
- 80041ea: b087 sub sp, #28
- 80041ec: af00 add r7, sp, #0
- 80041ee: 6078 str r0, [r7, #4]
- 80041f0: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC5E;
- 80041f2: 687b ldr r3, [r7, #4]
- 80041f4: 6a1b ldr r3, [r3, #32]
- 80041f6: f423 3280 bic.w r2, r3, #65536 ; 0x10000
- 80041fa: 687b ldr r3, [r7, #4]
- 80041fc: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 80041fe: 687b ldr r3, [r7, #4]
- 8004200: 6a1b ldr r3, [r3, #32]
- 8004202: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 8004204: 687b ldr r3, [r7, #4]
- 8004206: 685b ldr r3, [r3, #4]
- 8004208: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 800420a: 687b ldr r3, [r7, #4]
- 800420c: 6d5b ldr r3, [r3, #84] ; 0x54
- 800420e: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC5M);
- 8004210: 68fa ldr r2, [r7, #12]
- 8004212: 4b1b ldr r3, [pc, #108] ; (8004280 <TIM_OC5_SetConfig+0x98>)
- 8004214: 4013 ands r3, r2
- 8004216: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= OC_Config->OCMode;
- 8004218: 683b ldr r3, [r7, #0]
- 800421a: 681b ldr r3, [r3, #0]
- 800421c: 68fa ldr r2, [r7, #12]
- 800421e: 4313 orrs r3, r2
- 8004220: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC5P;
- 8004222: 693b ldr r3, [r7, #16]
- 8004224: f423 3300 bic.w r3, r3, #131072 ; 0x20000
- 8004228: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16U);
- 800422a: 683b ldr r3, [r7, #0]
- 800422c: 689b ldr r3, [r3, #8]
- 800422e: 041b lsls r3, r3, #16
- 8004230: 693a ldr r2, [r7, #16]
- 8004232: 4313 orrs r3, r2
- 8004234: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8004236: 687b ldr r3, [r7, #4]
- 8004238: 4a12 ldr r2, [pc, #72] ; (8004284 <TIM_OC5_SetConfig+0x9c>)
- 800423a: 4293 cmp r3, r2
- 800423c: d003 beq.n 8004246 <TIM_OC5_SetConfig+0x5e>
- 800423e: 687b ldr r3, [r7, #4]
- 8004240: 4a11 ldr r2, [pc, #68] ; (8004288 <TIM_OC5_SetConfig+0xa0>)
- 8004242: 4293 cmp r3, r2
- 8004244: d109 bne.n 800425a <TIM_OC5_SetConfig+0x72>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS5;
- 8004246: 697b ldr r3, [r7, #20]
- 8004248: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 800424c: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8U);
- 800424e: 683b ldr r3, [r7, #0]
- 8004250: 695b ldr r3, [r3, #20]
- 8004252: 021b lsls r3, r3, #8
- 8004254: 697a ldr r2, [r7, #20]
- 8004256: 4313 orrs r3, r2
- 8004258: 617b str r3, [r7, #20]
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 800425a: 687b ldr r3, [r7, #4]
- 800425c: 697a ldr r2, [r7, #20]
- 800425e: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 8004260: 687b ldr r3, [r7, #4]
- 8004262: 68fa ldr r2, [r7, #12]
- 8004264: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR5 = OC_Config->Pulse;
- 8004266: 683b ldr r3, [r7, #0]
- 8004268: 685a ldr r2, [r3, #4]
- 800426a: 687b ldr r3, [r7, #4]
- 800426c: 659a str r2, [r3, #88] ; 0x58
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 800426e: 687b ldr r3, [r7, #4]
- 8004270: 693a ldr r2, [r7, #16]
- 8004272: 621a str r2, [r3, #32]
-}
- 8004274: bf00 nop
- 8004276: 371c adds r7, #28
- 8004278: 46bd mov sp, r7
- 800427a: f85d 7b04 ldr.w r7, [sp], #4
- 800427e: 4770 bx lr
- 8004280: fffeff8f .word 0xfffeff8f
- 8004284: 40010000 .word 0x40010000
- 8004288: 40010400 .word 0x40010400
-
-0800428c <TIM_OC6_SetConfig>:
- * @param OC_Config The ouput configuration structure
- * @retval None
- */
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
- TIM_OC_InitTypeDef *OC_Config)
-{
- 800428c: b480 push {r7}
- 800428e: b087 sub sp, #28
- 8004290: af00 add r7, sp, #0
- 8004292: 6078 str r0, [r7, #4]
- 8004294: 6039 str r1, [r7, #0]
- uint32_t tmpccmrx;
- uint32_t tmpccer;
- uint32_t tmpcr2;
-
- /* Disable the output: Reset the CCxE Bit */
- TIMx->CCER &= ~TIM_CCER_CC6E;
- 8004296: 687b ldr r3, [r7, #4]
- 8004298: 6a1b ldr r3, [r3, #32]
- 800429a: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
- 800429e: 687b ldr r3, [r7, #4]
- 80042a0: 621a str r2, [r3, #32]
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- 80042a2: 687b ldr r3, [r7, #4]
- 80042a4: 6a1b ldr r3, [r3, #32]
- 80042a6: 613b str r3, [r7, #16]
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
- 80042a8: 687b ldr r3, [r7, #4]
- 80042aa: 685b ldr r3, [r3, #4]
- 80042ac: 617b str r3, [r7, #20]
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR3;
- 80042ae: 687b ldr r3, [r7, #4]
- 80042b0: 6d5b ldr r3, [r3, #84] ; 0x54
- 80042b2: 60fb str r3, [r7, #12]
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= ~(TIM_CCMR3_OC6M);
- 80042b4: 68fa ldr r2, [r7, #12]
- 80042b6: 4b1c ldr r3, [pc, #112] ; (8004328 <TIM_OC6_SetConfig+0x9c>)
- 80042b8: 4013 ands r3, r2
- 80042ba: 60fb str r3, [r7, #12]
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
- 80042bc: 683b ldr r3, [r7, #0]
- 80042be: 681b ldr r3, [r3, #0]
- 80042c0: 021b lsls r3, r3, #8
- 80042c2: 68fa ldr r2, [r7, #12]
- 80042c4: 4313 orrs r3, r2
- 80042c6: 60fb str r3, [r7, #12]
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- 80042c8: 693b ldr r3, [r7, #16]
- 80042ca: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
- 80042ce: 613b str r3, [r7, #16]
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20U);
- 80042d0: 683b ldr r3, [r7, #0]
- 80042d2: 689b ldr r3, [r3, #8]
- 80042d4: 051b lsls r3, r3, #20
- 80042d6: 693a ldr r2, [r7, #16]
- 80042d8: 4313 orrs r3, r2
- 80042da: 613b str r3, [r7, #16]
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80042dc: 687b ldr r3, [r7, #4]
- 80042de: 4a13 ldr r2, [pc, #76] ; (800432c <TIM_OC6_SetConfig+0xa0>)
- 80042e0: 4293 cmp r3, r2
- 80042e2: d003 beq.n 80042ec <TIM_OC6_SetConfig+0x60>
- 80042e4: 687b ldr r3, [r7, #4]
- 80042e6: 4a12 ldr r2, [pc, #72] ; (8004330 <TIM_OC6_SetConfig+0xa4>)
- 80042e8: 4293 cmp r3, r2
- 80042ea: d109 bne.n 8004300 <TIM_OC6_SetConfig+0x74>
- {
- /* Reset the Output Compare IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS6;
- 80042ec: 697b ldr r3, [r7, #20]
- 80042ee: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80042f2: 617b str r3, [r7, #20]
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10U);
- 80042f4: 683b ldr r3, [r7, #0]
- 80042f6: 695b ldr r3, [r3, #20]
- 80042f8: 029b lsls r3, r3, #10
- 80042fa: 697a ldr r2, [r7, #20]
- 80042fc: 4313 orrs r3, r2
- 80042fe: 617b str r3, [r7, #20]
- }
-
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
- 8004300: 687b ldr r3, [r7, #4]
- 8004302: 697a ldr r2, [r7, #20]
- 8004304: 605a str r2, [r3, #4]
-
- /* Write to TIMx CCMR3 */
- TIMx->CCMR3 = tmpccmrx;
- 8004306: 687b ldr r3, [r7, #4]
- 8004308: 68fa ldr r2, [r7, #12]
- 800430a: 655a str r2, [r3, #84] ; 0x54
-
- /* Set the Capture Compare Register value */
- TIMx->CCR6 = OC_Config->Pulse;
- 800430c: 683b ldr r3, [r7, #0]
- 800430e: 685a ldr r2, [r3, #4]
- 8004310: 687b ldr r3, [r7, #4]
- 8004312: 65da str r2, [r3, #92] ; 0x5c
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
- 8004314: 687b ldr r3, [r7, #4]
- 8004316: 693a ldr r2, [r7, #16]
- 8004318: 621a str r2, [r3, #32]
-}
- 800431a: bf00 nop
- 800431c: 371c adds r7, #28
- 800431e: 46bd mov sp, r7
- 8004320: f85d 7b04 ldr.w r7, [sp], #4
- 8004324: 4770 bx lr
- 8004326: bf00 nop
- 8004328: feff8fff .word 0xfeff8fff
- 800432c: 40010000 .word 0x40010000
- 8004330: 40010400 .word 0x40010400
-
-08004334 <TIM_TI1_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 8004334: b480 push {r7}
- 8004336: b087 sub sp, #28
- 8004338: af00 add r7, sp, #0
- 800433a: 60f8 str r0, [r7, #12]
- 800433c: 60b9 str r1, [r7, #8]
- 800433e: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- 8004340: 68fb ldr r3, [r7, #12]
- 8004342: 6a1b ldr r3, [r3, #32]
- 8004344: 617b str r3, [r7, #20]
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 8004346: 68fb ldr r3, [r7, #12]
- 8004348: 6a1b ldr r3, [r3, #32]
- 800434a: f023 0201 bic.w r2, r3, #1
- 800434e: 68fb ldr r3, [r7, #12]
- 8004350: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 8004352: 68fb ldr r3, [r7, #12]
- 8004354: 699b ldr r3, [r3, #24]
- 8004356: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 8004358: 693b ldr r3, [r7, #16]
- 800435a: f023 03f0 bic.w r3, r3, #240 ; 0xf0
- 800435e: 613b str r3, [r7, #16]
- tmpccmr1 |= (TIM_ICFilter << 4U);
- 8004360: 687b ldr r3, [r7, #4]
- 8004362: 011b lsls r3, r3, #4
- 8004364: 693a ldr r2, [r7, #16]
- 8004366: 4313 orrs r3, r2
- 8004368: 613b str r3, [r7, #16]
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 800436a: 697b ldr r3, [r7, #20]
- 800436c: f023 030a bic.w r3, r3, #10
- 8004370: 617b str r3, [r7, #20]
- tmpccer |= TIM_ICPolarity;
- 8004372: 697a ldr r2, [r7, #20]
- 8004374: 68bb ldr r3, [r7, #8]
- 8004376: 4313 orrs r3, r2
- 8004378: 617b str r3, [r7, #20]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- 800437a: 68fb ldr r3, [r7, #12]
- 800437c: 693a ldr r2, [r7, #16]
- 800437e: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 8004380: 68fb ldr r3, [r7, #12]
- 8004382: 697a ldr r2, [r7, #20]
- 8004384: 621a str r2, [r3, #32]
-}
- 8004386: bf00 nop
- 8004388: 371c adds r7, #28
- 800438a: 46bd mov sp, r7
- 800438c: f85d 7b04 ldr.w r7, [sp], #4
- 8004390: 4770 bx lr
-
-08004392 <TIM_TI2_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 8004392: b480 push {r7}
- 8004394: b087 sub sp, #28
- 8004396: af00 add r7, sp, #0
- 8004398: 60f8 str r0, [r7, #12]
- 800439a: 60b9 str r1, [r7, #8]
- 800439c: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 800439e: 68fb ldr r3, [r7, #12]
- 80043a0: 6a1b ldr r3, [r3, #32]
- 80043a2: f023 0210 bic.w r2, r3, #16
- 80043a6: 68fb ldr r3, [r7, #12]
- 80043a8: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 80043aa: 68fb ldr r3, [r7, #12]
- 80043ac: 699b ldr r3, [r3, #24]
- 80043ae: 617b str r3, [r7, #20]
- tmpccer = TIMx->CCER;
- 80043b0: 68fb ldr r3, [r7, #12]
- 80043b2: 6a1b ldr r3, [r3, #32]
- 80043b4: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 80043b6: 697b ldr r3, [r7, #20]
- 80043b8: f423 4370 bic.w r3, r3, #61440 ; 0xf000
- 80043bc: 617b str r3, [r7, #20]
- tmpccmr1 |= (TIM_ICFilter << 12U);
- 80043be: 687b ldr r3, [r7, #4]
- 80043c0: 031b lsls r3, r3, #12
- 80043c2: 697a ldr r2, [r7, #20]
- 80043c4: 4313 orrs r3, r2
- 80043c6: 617b str r3, [r7, #20]
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 80043c8: 693b ldr r3, [r7, #16]
- 80043ca: f023 03a0 bic.w r3, r3, #160 ; 0xa0
- 80043ce: 613b str r3, [r7, #16]
- tmpccer |= (TIM_ICPolarity << 4U);
- 80043d0: 68bb ldr r3, [r7, #8]
- 80043d2: 011b lsls r3, r3, #4
- 80043d4: 693a ldr r2, [r7, #16]
- 80043d6: 4313 orrs r3, r2
- 80043d8: 613b str r3, [r7, #16]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- 80043da: 68fb ldr r3, [r7, #12]
- 80043dc: 697a ldr r2, [r7, #20]
- 80043de: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 80043e0: 68fb ldr r3, [r7, #12]
- 80043e2: 693a ldr r2, [r7, #16]
- 80043e4: 621a str r2, [r3, #32]
-}
- 80043e6: bf00 nop
- 80043e8: 371c adds r7, #28
- 80043ea: 46bd mov sp, r7
- 80043ec: f85d 7b04 ldr.w r7, [sp], #4
- 80043f0: 4770 bx lr
-
-080043f2 <TIM_ITRx_SetConfig>:
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
- 80043f2: b480 push {r7}
- 80043f4: b085 sub sp, #20
- 80043f6: af00 add r7, sp, #0
- 80043f8: 6078 str r0, [r7, #4]
- 80043fa: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- 80043fc: 687b ldr r3, [r7, #4]
- 80043fe: 689b ldr r3, [r3, #8]
- 8004400: 60fb str r3, [r7, #12]
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- 8004402: 68fb ldr r3, [r7, #12]
- 8004404: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8004408: 60fb str r3, [r7, #12]
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 800440a: 683a ldr r2, [r7, #0]
- 800440c: 68fb ldr r3, [r7, #12]
- 800440e: 4313 orrs r3, r2
- 8004410: f043 0307 orr.w r3, r3, #7
- 8004414: 60fb str r3, [r7, #12]
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 8004416: 687b ldr r3, [r7, #4]
- 8004418: 68fa ldr r2, [r7, #12]
- 800441a: 609a str r2, [r3, #8]
-}
- 800441c: bf00 nop
- 800441e: 3714 adds r7, #20
- 8004420: 46bd mov sp, r7
- 8004422: f85d 7b04 ldr.w r7, [sp], #4
- 8004426: 4770 bx lr
-
-08004428 <TIM_ETR_SetConfig>:
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- 8004428: b480 push {r7}
- 800442a: b087 sub sp, #28
- 800442c: af00 add r7, sp, #0
- 800442e: 60f8 str r0, [r7, #12]
- 8004430: 60b9 str r1, [r7, #8]
- 8004432: 607a str r2, [r7, #4]
- 8004434: 603b str r3, [r7, #0]
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
- 8004436: 68fb ldr r3, [r7, #12]
- 8004438: 689b ldr r3, [r3, #8]
- 800443a: 617b str r3, [r7, #20]
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 800443c: 697b ldr r3, [r7, #20]
- 800443e: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8004442: 617b str r3, [r7, #20]
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 8004444: 683b ldr r3, [r7, #0]
- 8004446: 021a lsls r2, r3, #8
- 8004448: 687b ldr r3, [r7, #4]
- 800444a: 431a orrs r2, r3
- 800444c: 68bb ldr r3, [r7, #8]
- 800444e: 4313 orrs r3, r2
- 8004450: 697a ldr r2, [r7, #20]
- 8004452: 4313 orrs r3, r2
- 8004454: 617b str r3, [r7, #20]
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 8004456: 68fb ldr r3, [r7, #12]
- 8004458: 697a ldr r2, [r7, #20]
- 800445a: 609a str r2, [r3, #8]
-}
- 800445c: bf00 nop
- 800445e: 371c adds r7, #28
- 8004460: 46bd mov sp, r7
- 8004462: f85d 7b04 ldr.w r7, [sp], #4
- 8004466: 4770 bx lr
-
-08004468 <TIM_CCxChannelCmd>:
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
- * @retval None
- */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- 8004468: b480 push {r7}
- 800446a: b087 sub sp, #28
- 800446c: af00 add r7, sp, #0
- 800446e: 60f8 str r0, [r7, #12]
- 8004470: 60b9 str r1, [r7, #8]
- 8004472: 607a str r2, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
- 8004474: 68bb ldr r3, [r7, #8]
- 8004476: f003 031f and.w r3, r3, #31
- 800447a: 2201 movs r2, #1
- 800447c: fa02 f303 lsl.w r3, r2, r3
- 8004480: 617b str r3, [r7, #20]
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
- 8004482: 68fb ldr r3, [r7, #12]
- 8004484: 6a1a ldr r2, [r3, #32]
- 8004486: 697b ldr r3, [r7, #20]
- 8004488: 43db mvns r3, r3
- 800448a: 401a ands r2, r3
- 800448c: 68fb ldr r3, [r7, #12]
- 800448e: 621a str r2, [r3, #32]
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
- 8004490: 68fb ldr r3, [r7, #12]
- 8004492: 6a1a ldr r2, [r3, #32]
- 8004494: 68bb ldr r3, [r7, #8]
- 8004496: f003 031f and.w r3, r3, #31
- 800449a: 6879 ldr r1, [r7, #4]
- 800449c: fa01 f303 lsl.w r3, r1, r3
- 80044a0: 431a orrs r2, r3
- 80044a2: 68fb ldr r3, [r7, #12]
- 80044a4: 621a str r2, [r3, #32]
-}
- 80044a6: bf00 nop
- 80044a8: 371c adds r7, #28
- 80044aa: 46bd mov sp, r7
- 80044ac: f85d 7b04 ldr.w r7, [sp], #4
- 80044b0: 4770 bx lr
- ...
-
-080044b4 <HAL_TIMEx_MasterConfigSynchronization>:
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
-{
- 80044b4: b480 push {r7}
- 80044b6: b085 sub sp, #20
- 80044b8: af00 add r7, sp, #0
- 80044ba: 6078 str r0, [r7, #4]
- 80044bc: 6039 str r1, [r7, #0]
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
- 80044be: 687b ldr r3, [r7, #4]
- 80044c0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 80044c4: 2b01 cmp r3, #1
- 80044c6: d101 bne.n 80044cc <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 80044c8: 2302 movs r3, #2
- 80044ca: e045 b.n 8004558 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 80044cc: 687b ldr r3, [r7, #4]
- 80044ce: 2201 movs r2, #1
- 80044d0: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
- 80044d4: 687b ldr r3, [r7, #4]
- 80044d6: 2202 movs r2, #2
- 80044d8: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
- 80044dc: 687b ldr r3, [r7, #4]
- 80044de: 681b ldr r3, [r3, #0]
- 80044e0: 685b ldr r3, [r3, #4]
- 80044e2: 60fb str r3, [r7, #12]
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 80044e4: 687b ldr r3, [r7, #4]
- 80044e6: 681b ldr r3, [r3, #0]
- 80044e8: 689b ldr r3, [r3, #8]
- 80044ea: 60bb str r3, [r7, #8]
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 80044ec: 687b ldr r3, [r7, #4]
- 80044ee: 681b ldr r3, [r3, #0]
- 80044f0: 4a1c ldr r2, [pc, #112] ; (8004564 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 80044f2: 4293 cmp r3, r2
- 80044f4: d004 beq.n 8004500 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 80044f6: 687b ldr r3, [r7, #4]
- 80044f8: 681b ldr r3, [r3, #0]
- 80044fa: 4a1b ldr r2, [pc, #108] ; (8004568 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 80044fc: 4293 cmp r3, r2
- 80044fe: d108 bne.n 8004512 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- 8004500: 68fb ldr r3, [r7, #12]
- 8004502: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 8004506: 60fb str r3, [r7, #12]
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 8004508: 683b ldr r3, [r7, #0]
- 800450a: 685b ldr r3, [r3, #4]
- 800450c: 68fa ldr r2, [r7, #12]
- 800450e: 4313 orrs r3, r2
- 8004510: 60fb str r3, [r7, #12]
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- 8004512: 68fb ldr r3, [r7, #12]
- 8004514: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8004518: 60fb str r3, [r7, #12]
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 800451a: 683b ldr r3, [r7, #0]
- 800451c: 681b ldr r3, [r3, #0]
- 800451e: 68fa ldr r2, [r7, #12]
- 8004520: 4313 orrs r3, r2
- 8004522: 60fb str r3, [r7, #12]
-
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- 8004524: 68bb ldr r3, [r7, #8]
- 8004526: f023 0380 bic.w r3, r3, #128 ; 0x80
- 800452a: 60bb str r3, [r7, #8]
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 800452c: 683b ldr r3, [r7, #0]
- 800452e: 689b ldr r3, [r3, #8]
- 8004530: 68ba ldr r2, [r7, #8]
- 8004532: 4313 orrs r3, r2
- 8004534: 60bb str r3, [r7, #8]
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
- 8004536: 687b ldr r3, [r7, #4]
- 8004538: 681b ldr r3, [r3, #0]
- 800453a: 68fa ldr r2, [r7, #12]
- 800453c: 605a str r2, [r3, #4]
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 800453e: 687b ldr r3, [r7, #4]
- 8004540: 681b ldr r3, [r3, #0]
- 8004542: 68ba ldr r2, [r7, #8]
- 8004544: 609a str r2, [r3, #8]
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
- 8004546: 687b ldr r3, [r7, #4]
- 8004548: 2201 movs r2, #1
- 800454a: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 800454e: 687b ldr r3, [r7, #4]
- 8004550: 2200 movs r2, #0
- 8004552: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 8004556: 2300 movs r3, #0
-}
- 8004558: 4618 mov r0, r3
- 800455a: 3714 adds r7, #20
- 800455c: 46bd mov sp, r7
- 800455e: f85d 7b04 ldr.w r7, [sp], #4
- 8004562: 4770 bx lr
- 8004564: 40010000 .word 0x40010000
- 8004568: 40010400 .word 0x40010400
-
-0800456c <HAL_TIMEx_CommutCallback>:
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- 800456c: b480 push {r7}
- 800456e: b083 sub sp, #12
- 8004570: af00 add r7, sp, #0
- 8004572: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
- 8004574: bf00 nop
- 8004576: 370c adds r7, #12
- 8004578: 46bd mov sp, r7
- 800457a: f85d 7b04 ldr.w r7, [sp], #4
- 800457e: 4770 bx lr
-
-08004580 <HAL_TIMEx_BreakCallback>:
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- 8004580: b480 push {r7}
- 8004582: b083 sub sp, #12
- 8004584: af00 add r7, sp, #0
- 8004586: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
- 8004588: bf00 nop
- 800458a: 370c adds r7, #12
- 800458c: 46bd mov sp, r7
- 800458e: f85d 7b04 ldr.w r7, [sp], #4
- 8004592: 4770 bx lr
-
-08004594 <HAL_TIMEx_Break2Callback>:
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- 8004594: b480 push {r7}
- 8004596: b083 sub sp, #12
- 8004598: af00 add r7, sp, #0
- 800459a: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
- 800459c: bf00 nop
- 800459e: 370c adds r7, #12
- 80045a0: 46bd mov sp, r7
- 80045a2: f85d 7b04 ldr.w r7, [sp], #4
- 80045a6: 4770 bx lr
-
-080045a8 <HAL_UART_Init>:
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- 80045a8: b580 push {r7, lr}
- 80045aa: b082 sub sp, #8
- 80045ac: af00 add r7, sp, #0
- 80045ae: 6078 str r0, [r7, #4]
- /* Check the UART handle allocation */
- if (huart == NULL)
- 80045b0: 687b ldr r3, [r7, #4]
- 80045b2: 2b00 cmp r3, #0
- 80045b4: d101 bne.n 80045ba <HAL_UART_Init+0x12>
- {
- return HAL_ERROR;
- 80045b6: 2301 movs r3, #1
- 80045b8: e040 b.n 800463c <HAL_UART_Init+0x94>
- {
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
- }
-
- if (huart->gState == HAL_UART_STATE_RESET)
- 80045ba: 687b ldr r3, [r7, #4]
- 80045bc: 6f5b ldr r3, [r3, #116] ; 0x74
- 80045be: 2b00 cmp r3, #0
- 80045c0: d106 bne.n 80045d0 <HAL_UART_Init+0x28>
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- 80045c2: 687b ldr r3, [r7, #4]
- 80045c4: 2200 movs r2, #0
- 80045c6: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- 80045ca: 6878 ldr r0, [r7, #4]
- 80045cc: f7fd fa38 bl 8001a40 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
- 80045d0: 687b ldr r3, [r7, #4]
- 80045d2: 2224 movs r2, #36 ; 0x24
- 80045d4: 675a str r2, [r3, #116] ; 0x74
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
- 80045d6: 687b ldr r3, [r7, #4]
- 80045d8: 681b ldr r3, [r3, #0]
- 80045da: 681a ldr r2, [r3, #0]
- 80045dc: 687b ldr r3, [r7, #4]
- 80045de: 681b ldr r3, [r3, #0]
- 80045e0: f022 0201 bic.w r2, r2, #1
- 80045e4: 601a str r2, [r3, #0]
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- 80045e6: 6878 ldr r0, [r7, #4]
- 80045e8: f000 fa90 bl 8004b0c <UART_SetConfig>
- 80045ec: 4603 mov r3, r0
- 80045ee: 2b01 cmp r3, #1
- 80045f0: d101 bne.n 80045f6 <HAL_UART_Init+0x4e>
- {
- return HAL_ERROR;
- 80045f2: 2301 movs r3, #1
- 80045f4: e022 b.n 800463c <HAL_UART_Init+0x94>
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 80045f6: 687b ldr r3, [r7, #4]
- 80045f8: 6a5b ldr r3, [r3, #36] ; 0x24
- 80045fa: 2b00 cmp r3, #0
- 80045fc: d002 beq.n 8004604 <HAL_UART_Init+0x5c>
- {
- UART_AdvFeatureConfig(huart);
- 80045fe: 6878 ldr r0, [r7, #4]
- 8004600: f000 fd28 bl 8005054 <UART_AdvFeatureConfig>
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8004604: 687b ldr r3, [r7, #4]
- 8004606: 681b ldr r3, [r3, #0]
- 8004608: 685a ldr r2, [r3, #4]
- 800460a: 687b ldr r3, [r7, #4]
- 800460c: 681b ldr r3, [r3, #0]
- 800460e: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 8004612: 605a str r2, [r3, #4]
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8004614: 687b ldr r3, [r7, #4]
- 8004616: 681b ldr r3, [r3, #0]
- 8004618: 689a ldr r2, [r3, #8]
- 800461a: 687b ldr r3, [r7, #4]
- 800461c: 681b ldr r3, [r3, #0]
- 800461e: f022 022a bic.w r2, r2, #42 ; 0x2a
- 8004622: 609a str r2, [r3, #8]
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
- 8004624: 687b ldr r3, [r7, #4]
- 8004626: 681b ldr r3, [r3, #0]
- 8004628: 681a ldr r2, [r3, #0]
- 800462a: 687b ldr r3, [r7, #4]
- 800462c: 681b ldr r3, [r3, #0]
- 800462e: f042 0201 orr.w r2, r2, #1
- 8004632: 601a str r2, [r3, #0]
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
- 8004634: 6878 ldr r0, [r7, #4]
- 8004636: f000 fdaf bl 8005198 <UART_CheckIdleState>
- 800463a: 4603 mov r3, r0
-}
- 800463c: 4618 mov r0, r3
- 800463e: 3708 adds r7, #8
- 8004640: 46bd mov sp, r7
- 8004642: bd80 pop {r7, pc}
-
-08004644 <HAL_UART_Transmit>:
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- 8004644: b580 push {r7, lr}
- 8004646: b08a sub sp, #40 ; 0x28
- 8004648: af02 add r7, sp, #8
- 800464a: 60f8 str r0, [r7, #12]
- 800464c: 60b9 str r1, [r7, #8]
- 800464e: 603b str r3, [r7, #0]
- 8004650: 4613 mov r3, r2
- 8004652: 80fb strh r3, [r7, #6]
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
- uint32_t tickstart;
-
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY)
- 8004654: 68fb ldr r3, [r7, #12]
- 8004656: 6f5b ldr r3, [r3, #116] ; 0x74
- 8004658: 2b20 cmp r3, #32
- 800465a: d17f bne.n 800475c <HAL_UART_Transmit+0x118>
- {
- if ((pData == NULL) || (Size == 0U))
- 800465c: 68bb ldr r3, [r7, #8]
- 800465e: 2b00 cmp r3, #0
- 8004660: d002 beq.n 8004668 <HAL_UART_Transmit+0x24>
- 8004662: 88fb ldrh r3, [r7, #6]
- 8004664: 2b00 cmp r3, #0
- 8004666: d101 bne.n 800466c <HAL_UART_Transmit+0x28>
- {
- return HAL_ERROR;
- 8004668: 2301 movs r3, #1
- 800466a: e078 b.n 800475e <HAL_UART_Transmit+0x11a>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 800466c: 68fb ldr r3, [r7, #12]
- 800466e: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 8004672: 2b01 cmp r3, #1
- 8004674: d101 bne.n 800467a <HAL_UART_Transmit+0x36>
- 8004676: 2302 movs r3, #2
- 8004678: e071 b.n 800475e <HAL_UART_Transmit+0x11a>
- 800467a: 68fb ldr r3, [r7, #12]
- 800467c: 2201 movs r2, #1
- 800467e: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004682: 68fb ldr r3, [r7, #12]
- 8004684: 2200 movs r2, #0
- 8004686: 67da str r2, [r3, #124] ; 0x7c
- huart->gState = HAL_UART_STATE_BUSY_TX;
- 8004688: 68fb ldr r3, [r7, #12]
- 800468a: 2221 movs r2, #33 ; 0x21
- 800468c: 675a str r2, [r3, #116] ; 0x74
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 800468e: f7fd fb1f bl 8001cd0 <HAL_GetTick>
- 8004692: 6178 str r0, [r7, #20]
-
- huart->TxXferSize = Size;
- 8004694: 68fb ldr r3, [r7, #12]
- 8004696: 88fa ldrh r2, [r7, #6]
- 8004698: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
- huart->TxXferCount = Size;
- 800469c: 68fb ldr r3, [r7, #12]
- 800469e: 88fa ldrh r2, [r7, #6]
- 80046a0: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-
- /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 80046a4: 68fb ldr r3, [r7, #12]
- 80046a6: 689b ldr r3, [r3, #8]
- 80046a8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80046ac: d108 bne.n 80046c0 <HAL_UART_Transmit+0x7c>
- 80046ae: 68fb ldr r3, [r7, #12]
- 80046b0: 691b ldr r3, [r3, #16]
- 80046b2: 2b00 cmp r3, #0
- 80046b4: d104 bne.n 80046c0 <HAL_UART_Transmit+0x7c>
- {
- pdata8bits = NULL;
- 80046b6: 2300 movs r3, #0
- 80046b8: 61fb str r3, [r7, #28]
- pdata16bits = (uint16_t *) pData;
- 80046ba: 68bb ldr r3, [r7, #8]
- 80046bc: 61bb str r3, [r7, #24]
- 80046be: e003 b.n 80046c8 <HAL_UART_Transmit+0x84>
- }
- else
- {
- pdata8bits = pData;
- 80046c0: 68bb ldr r3, [r7, #8]
- 80046c2: 61fb str r3, [r7, #28]
- pdata16bits = NULL;
- 80046c4: 2300 movs r3, #0
- 80046c6: 61bb str r3, [r7, #24]
- }
-
- while (huart->TxXferCount > 0U)
- 80046c8: e02c b.n 8004724 <HAL_UART_Transmit+0xe0>
- {
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 80046ca: 683b ldr r3, [r7, #0]
- 80046cc: 9300 str r3, [sp, #0]
- 80046ce: 697b ldr r3, [r7, #20]
- 80046d0: 2200 movs r2, #0
- 80046d2: 2180 movs r1, #128 ; 0x80
- 80046d4: 68f8 ldr r0, [r7, #12]
- 80046d6: f000 fd8e bl 80051f6 <UART_WaitOnFlagUntilTimeout>
- 80046da: 4603 mov r3, r0
- 80046dc: 2b00 cmp r3, #0
- 80046de: d001 beq.n 80046e4 <HAL_UART_Transmit+0xa0>
- {
- return HAL_TIMEOUT;
- 80046e0: 2303 movs r3, #3
- 80046e2: e03c b.n 800475e <HAL_UART_Transmit+0x11a>
- }
- if (pdata8bits == NULL)
- 80046e4: 69fb ldr r3, [r7, #28]
- 80046e6: 2b00 cmp r3, #0
- 80046e8: d10b bne.n 8004702 <HAL_UART_Transmit+0xbe>
- {
- huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 80046ea: 69bb ldr r3, [r7, #24]
- 80046ec: 881b ldrh r3, [r3, #0]
- 80046ee: 461a mov r2, r3
- 80046f0: 68fb ldr r3, [r7, #12]
- 80046f2: 681b ldr r3, [r3, #0]
- 80046f4: f3c2 0208 ubfx r2, r2, #0, #9
- 80046f8: 629a str r2, [r3, #40] ; 0x28
- pdata16bits++;
- 80046fa: 69bb ldr r3, [r7, #24]
- 80046fc: 3302 adds r3, #2
- 80046fe: 61bb str r3, [r7, #24]
- 8004700: e007 b.n 8004712 <HAL_UART_Transmit+0xce>
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 8004702: 69fb ldr r3, [r7, #28]
- 8004704: 781a ldrb r2, [r3, #0]
- 8004706: 68fb ldr r3, [r7, #12]
- 8004708: 681b ldr r3, [r3, #0]
- 800470a: 629a str r2, [r3, #40] ; 0x28
- pdata8bits++;
- 800470c: 69fb ldr r3, [r7, #28]
- 800470e: 3301 adds r3, #1
- 8004710: 61fb str r3, [r7, #28]
- }
- huart->TxXferCount--;
- 8004712: 68fb ldr r3, [r7, #12]
- 8004714: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 8004718: b29b uxth r3, r3
- 800471a: 3b01 subs r3, #1
- 800471c: b29a uxth r2, r3
- 800471e: 68fb ldr r3, [r7, #12]
- 8004720: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
- while (huart->TxXferCount > 0U)
- 8004724: 68fb ldr r3, [r7, #12]
- 8004726: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 800472a: b29b uxth r3, r3
- 800472c: 2b00 cmp r3, #0
- 800472e: d1cc bne.n 80046ca <HAL_UART_Transmit+0x86>
- }
-
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 8004730: 683b ldr r3, [r7, #0]
- 8004732: 9300 str r3, [sp, #0]
- 8004734: 697b ldr r3, [r7, #20]
- 8004736: 2200 movs r2, #0
- 8004738: 2140 movs r1, #64 ; 0x40
- 800473a: 68f8 ldr r0, [r7, #12]
- 800473c: f000 fd5b bl 80051f6 <UART_WaitOnFlagUntilTimeout>
- 8004740: 4603 mov r3, r0
- 8004742: 2b00 cmp r3, #0
- 8004744: d001 beq.n 800474a <HAL_UART_Transmit+0x106>
- {
- return HAL_TIMEOUT;
- 8004746: 2303 movs r3, #3
- 8004748: e009 b.n 800475e <HAL_UART_Transmit+0x11a>
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 800474a: 68fb ldr r3, [r7, #12]
- 800474c: 2220 movs r2, #32
- 800474e: 675a str r2, [r3, #116] ; 0x74
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8004750: 68fb ldr r3, [r7, #12]
- 8004752: 2200 movs r2, #0
- 8004754: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 8004758: 2300 movs r3, #0
- 800475a: e000 b.n 800475e <HAL_UART_Transmit+0x11a>
- }
- else
- {
- return HAL_BUSY;
- 800475c: 2302 movs r3, #2
- }
-}
- 800475e: 4618 mov r0, r3
- 8004760: 3720 adds r7, #32
- 8004762: 46bd mov sp, r7
- 8004764: bd80 pop {r7, pc}
- ...
-
-08004768 <HAL_UART_Receive_IT>:
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- 8004768: b480 push {r7}
- 800476a: b085 sub sp, #20
- 800476c: af00 add r7, sp, #0
- 800476e: 60f8 str r0, [r7, #12]
- 8004770: 60b9 str r1, [r7, #8]
- 8004772: 4613 mov r3, r2
- 8004774: 80fb strh r3, [r7, #6]
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY)
- 8004776: 68fb ldr r3, [r7, #12]
- 8004778: 6f9b ldr r3, [r3, #120] ; 0x78
- 800477a: 2b20 cmp r3, #32
- 800477c: f040 808a bne.w 8004894 <HAL_UART_Receive_IT+0x12c>
- {
- if ((pData == NULL) || (Size == 0U))
- 8004780: 68bb ldr r3, [r7, #8]
- 8004782: 2b00 cmp r3, #0
- 8004784: d002 beq.n 800478c <HAL_UART_Receive_IT+0x24>
- 8004786: 88fb ldrh r3, [r7, #6]
- 8004788: 2b00 cmp r3, #0
- 800478a: d101 bne.n 8004790 <HAL_UART_Receive_IT+0x28>
- {
- return HAL_ERROR;
- 800478c: 2301 movs r3, #1
- 800478e: e082 b.n 8004896 <HAL_UART_Receive_IT+0x12e>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8004790: 68fb ldr r3, [r7, #12]
- 8004792: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 8004796: 2b01 cmp r3, #1
- 8004798: d101 bne.n 800479e <HAL_UART_Receive_IT+0x36>
- 800479a: 2302 movs r3, #2
- 800479c: e07b b.n 8004896 <HAL_UART_Receive_IT+0x12e>
- 800479e: 68fb ldr r3, [r7, #12]
- 80047a0: 2201 movs r2, #1
- 80047a2: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->pRxBuffPtr = pData;
- 80047a6: 68fb ldr r3, [r7, #12]
- 80047a8: 68ba ldr r2, [r7, #8]
- 80047aa: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferSize = Size;
- 80047ac: 68fb ldr r3, [r7, #12]
- 80047ae: 88fa ldrh r2, [r7, #6]
- 80047b0: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
- huart->RxXferCount = Size;
- 80047b4: 68fb ldr r3, [r7, #12]
- 80047b6: 88fa ldrh r2, [r7, #6]
- 80047b8: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->RxISR = NULL;
- 80047bc: 68fb ldr r3, [r7, #12]
- 80047be: 2200 movs r2, #0
- 80047c0: 661a str r2, [r3, #96] ; 0x60
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- 80047c2: 68fb ldr r3, [r7, #12]
- 80047c4: 689b ldr r3, [r3, #8]
- 80047c6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80047ca: d10e bne.n 80047ea <HAL_UART_Receive_IT+0x82>
- 80047cc: 68fb ldr r3, [r7, #12]
- 80047ce: 691b ldr r3, [r3, #16]
- 80047d0: 2b00 cmp r3, #0
- 80047d2: d105 bne.n 80047e0 <HAL_UART_Receive_IT+0x78>
- 80047d4: 68fb ldr r3, [r7, #12]
- 80047d6: f240 12ff movw r2, #511 ; 0x1ff
- 80047da: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80047de: e02d b.n 800483c <HAL_UART_Receive_IT+0xd4>
- 80047e0: 68fb ldr r3, [r7, #12]
- 80047e2: 22ff movs r2, #255 ; 0xff
- 80047e4: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 80047e8: e028 b.n 800483c <HAL_UART_Receive_IT+0xd4>
- 80047ea: 68fb ldr r3, [r7, #12]
- 80047ec: 689b ldr r3, [r3, #8]
- 80047ee: 2b00 cmp r3, #0
- 80047f0: d10d bne.n 800480e <HAL_UART_Receive_IT+0xa6>
- 80047f2: 68fb ldr r3, [r7, #12]
- 80047f4: 691b ldr r3, [r3, #16]
- 80047f6: 2b00 cmp r3, #0
- 80047f8: d104 bne.n 8004804 <HAL_UART_Receive_IT+0x9c>
- 80047fa: 68fb ldr r3, [r7, #12]
- 80047fc: 22ff movs r2, #255 ; 0xff
- 80047fe: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004802: e01b b.n 800483c <HAL_UART_Receive_IT+0xd4>
- 8004804: 68fb ldr r3, [r7, #12]
- 8004806: 227f movs r2, #127 ; 0x7f
- 8004808: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 800480c: e016 b.n 800483c <HAL_UART_Receive_IT+0xd4>
- 800480e: 68fb ldr r3, [r7, #12]
- 8004810: 689b ldr r3, [r3, #8]
- 8004812: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
- 8004816: d10d bne.n 8004834 <HAL_UART_Receive_IT+0xcc>
- 8004818: 68fb ldr r3, [r7, #12]
- 800481a: 691b ldr r3, [r3, #16]
- 800481c: 2b00 cmp r3, #0
- 800481e: d104 bne.n 800482a <HAL_UART_Receive_IT+0xc2>
- 8004820: 68fb ldr r3, [r7, #12]
- 8004822: 227f movs r2, #127 ; 0x7f
- 8004824: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004828: e008 b.n 800483c <HAL_UART_Receive_IT+0xd4>
- 800482a: 68fb ldr r3, [r7, #12]
- 800482c: 223f movs r2, #63 ; 0x3f
- 800482e: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8004832: e003 b.n 800483c <HAL_UART_Receive_IT+0xd4>
- 8004834: 68fb ldr r3, [r7, #12]
- 8004836: 2200 movs r2, #0
- 8004838: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 800483c: 68fb ldr r3, [r7, #12]
- 800483e: 2200 movs r2, #0
- 8004840: 67da str r2, [r3, #124] ; 0x7c
- huart->RxState = HAL_UART_STATE_BUSY_RX;
- 8004842: 68fb ldr r3, [r7, #12]
- 8004844: 2222 movs r2, #34 ; 0x22
- 8004846: 679a str r2, [r3, #120] ; 0x78
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8004848: 68fb ldr r3, [r7, #12]
- 800484a: 681b ldr r3, [r3, #0]
- 800484c: 689a ldr r2, [r3, #8]
- 800484e: 68fb ldr r3, [r7, #12]
- 8004850: 681b ldr r3, [r3, #0]
- 8004852: f042 0201 orr.w r2, r2, #1
- 8004856: 609a str r2, [r3, #8]
-
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8004858: 68fb ldr r3, [r7, #12]
- 800485a: 689b ldr r3, [r3, #8]
- 800485c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004860: d107 bne.n 8004872 <HAL_UART_Receive_IT+0x10a>
- 8004862: 68fb ldr r3, [r7, #12]
- 8004864: 691b ldr r3, [r3, #16]
- 8004866: 2b00 cmp r3, #0
- 8004868: d103 bne.n 8004872 <HAL_UART_Receive_IT+0x10a>
- {
- huart->RxISR = UART_RxISR_16BIT;
- 800486a: 68fb ldr r3, [r7, #12]
- 800486c: 4a0d ldr r2, [pc, #52] ; (80048a4 <HAL_UART_Receive_IT+0x13c>)
- 800486e: 661a str r2, [r3, #96] ; 0x60
- 8004870: e002 b.n 8004878 <HAL_UART_Receive_IT+0x110>
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- 8004872: 68fb ldr r3, [r7, #12]
- 8004874: 4a0c ldr r2, [pc, #48] ; (80048a8 <HAL_UART_Receive_IT+0x140>)
- 8004876: 661a str r2, [r3, #96] ; 0x60
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8004878: 68fb ldr r3, [r7, #12]
- 800487a: 2200 movs r2, #0
- 800487c: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- 8004880: 68fb ldr r3, [r7, #12]
- 8004882: 681b ldr r3, [r3, #0]
- 8004884: 681a ldr r2, [r3, #0]
- 8004886: 68fb ldr r3, [r7, #12]
- 8004888: 681b ldr r3, [r3, #0]
- 800488a: f442 7290 orr.w r2, r2, #288 ; 0x120
- 800488e: 601a str r2, [r3, #0]
-
- return HAL_OK;
- 8004890: 2300 movs r3, #0
- 8004892: e000 b.n 8004896 <HAL_UART_Receive_IT+0x12e>
- }
- else
- {
- return HAL_BUSY;
- 8004894: 2302 movs r3, #2
- }
-}
- 8004896: 4618 mov r0, r3
- 8004898: 3714 adds r7, #20
- 800489a: 46bd mov sp, r7
- 800489c: f85d 7b04 ldr.w r7, [sp], #4
- 80048a0: 4770 bx lr
- 80048a2: bf00 nop
- 80048a4: 080053cb .word 0x080053cb
- 80048a8: 08005325 .word 0x08005325
-
-080048ac <HAL_UART_IRQHandler>:
- * @brief Handle UART interrupt request.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- 80048ac: b580 push {r7, lr}
- 80048ae: b088 sub sp, #32
- 80048b0: af00 add r7, sp, #0
- 80048b2: 6078 str r0, [r7, #4]
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- 80048b4: 687b ldr r3, [r7, #4]
- 80048b6: 681b ldr r3, [r3, #0]
- 80048b8: 69db ldr r3, [r3, #28]
- 80048ba: 61fb str r3, [r7, #28]
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- 80048bc: 687b ldr r3, [r7, #4]
- 80048be: 681b ldr r3, [r3, #0]
- 80048c0: 681b ldr r3, [r3, #0]
- 80048c2: 61bb str r3, [r7, #24]
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- 80048c4: 687b ldr r3, [r7, #4]
- 80048c6: 681b ldr r3, [r3, #0]
- 80048c8: 689b ldr r3, [r3, #8]
- 80048ca: 617b str r3, [r7, #20]
-
- uint32_t errorflags;
- uint32_t errorcode;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- 80048cc: 69fb ldr r3, [r7, #28]
- 80048ce: f003 030f and.w r3, r3, #15
- 80048d2: 613b str r3, [r7, #16]
- if (errorflags == 0U)
- 80048d4: 693b ldr r3, [r7, #16]
- 80048d6: 2b00 cmp r3, #0
- 80048d8: d113 bne.n 8004902 <HAL_UART_IRQHandler+0x56>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 80048da: 69fb ldr r3, [r7, #28]
- 80048dc: f003 0320 and.w r3, r3, #32
- 80048e0: 2b00 cmp r3, #0
- 80048e2: d00e beq.n 8004902 <HAL_UART_IRQHandler+0x56>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 80048e4: 69bb ldr r3, [r7, #24]
- 80048e6: f003 0320 and.w r3, r3, #32
- 80048ea: 2b00 cmp r3, #0
- 80048ec: d009 beq.n 8004902 <HAL_UART_IRQHandler+0x56>
- {
- if (huart->RxISR != NULL)
- 80048ee: 687b ldr r3, [r7, #4]
- 80048f0: 6e1b ldr r3, [r3, #96] ; 0x60
- 80048f2: 2b00 cmp r3, #0
- 80048f4: f000 80eb beq.w 8004ace <HAL_UART_IRQHandler+0x222>
- {
- huart->RxISR(huart);
- 80048f8: 687b ldr r3, [r7, #4]
- 80048fa: 6e1b ldr r3, [r3, #96] ; 0x60
- 80048fc: 6878 ldr r0, [r7, #4]
- 80048fe: 4798 blx r3
- }
- return;
- 8004900: e0e5 b.n 8004ace <HAL_UART_IRQHandler+0x222>
- }
- }
-
- /* If some errors occur */
- if ((errorflags != 0U)
- 8004902: 693b ldr r3, [r7, #16]
- 8004904: 2b00 cmp r3, #0
- 8004906: f000 80c0 beq.w 8004a8a <HAL_UART_IRQHandler+0x1de>
- && (((cr3its & USART_CR3_EIE) != 0U)
- 800490a: 697b ldr r3, [r7, #20]
- 800490c: f003 0301 and.w r3, r3, #1
- 8004910: 2b00 cmp r3, #0
- 8004912: d105 bne.n 8004920 <HAL_UART_IRQHandler+0x74>
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
- 8004914: 69bb ldr r3, [r7, #24]
- 8004916: f403 7390 and.w r3, r3, #288 ; 0x120
- 800491a: 2b00 cmp r3, #0
- 800491c: f000 80b5 beq.w 8004a8a <HAL_UART_IRQHandler+0x1de>
- {
- /* UART parity error interrupt occurred -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
- 8004920: 69fb ldr r3, [r7, #28]
- 8004922: f003 0301 and.w r3, r3, #1
- 8004926: 2b00 cmp r3, #0
- 8004928: d00e beq.n 8004948 <HAL_UART_IRQHandler+0x9c>
- 800492a: 69bb ldr r3, [r7, #24]
- 800492c: f403 7380 and.w r3, r3, #256 ; 0x100
- 8004930: 2b00 cmp r3, #0
- 8004932: d009 beq.n 8004948 <HAL_UART_IRQHandler+0x9c>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
- 8004934: 687b ldr r3, [r7, #4]
- 8004936: 681b ldr r3, [r3, #0]
- 8004938: 2201 movs r2, #1
- 800493a: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- 800493c: 687b ldr r3, [r7, #4]
- 800493e: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004940: f043 0201 orr.w r2, r3, #1
- 8004944: 687b ldr r3, [r7, #4]
- 8004946: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004948: 69fb ldr r3, [r7, #28]
- 800494a: f003 0302 and.w r3, r3, #2
- 800494e: 2b00 cmp r3, #0
- 8004950: d00e beq.n 8004970 <HAL_UART_IRQHandler+0xc4>
- 8004952: 697b ldr r3, [r7, #20]
- 8004954: f003 0301 and.w r3, r3, #1
- 8004958: 2b00 cmp r3, #0
- 800495a: d009 beq.n 8004970 <HAL_UART_IRQHandler+0xc4>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
- 800495c: 687b ldr r3, [r7, #4]
- 800495e: 681b ldr r3, [r3, #0]
- 8004960: 2202 movs r2, #2
- 8004962: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- 8004964: 687b ldr r3, [r7, #4]
- 8004966: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004968: f043 0204 orr.w r2, r3, #4
- 800496c: 687b ldr r3, [r7, #4]
- 800496e: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004970: 69fb ldr r3, [r7, #28]
- 8004972: f003 0304 and.w r3, r3, #4
- 8004976: 2b00 cmp r3, #0
- 8004978: d00e beq.n 8004998 <HAL_UART_IRQHandler+0xec>
- 800497a: 697b ldr r3, [r7, #20]
- 800497c: f003 0301 and.w r3, r3, #1
- 8004980: 2b00 cmp r3, #0
- 8004982: d009 beq.n 8004998 <HAL_UART_IRQHandler+0xec>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
- 8004984: 687b ldr r3, [r7, #4]
- 8004986: 681b ldr r3, [r3, #0]
- 8004988: 2204 movs r2, #4
- 800498a: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- 800498c: 687b ldr r3, [r7, #4]
- 800498e: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004990: f043 0202 orr.w r2, r3, #2
- 8004994: 687b ldr r3, [r7, #4]
- 8004996: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if (((isrflags & USART_ISR_ORE) != 0U)
- 8004998: 69fb ldr r3, [r7, #28]
- 800499a: f003 0308 and.w r3, r3, #8
- 800499e: 2b00 cmp r3, #0
- 80049a0: d013 beq.n 80049ca <HAL_UART_IRQHandler+0x11e>
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 80049a2: 69bb ldr r3, [r7, #24]
- 80049a4: f003 0320 and.w r3, r3, #32
- 80049a8: 2b00 cmp r3, #0
- 80049aa: d104 bne.n 80049b6 <HAL_UART_IRQHandler+0x10a>
- ((cr3its & USART_CR3_EIE) != 0U)))
- 80049ac: 697b ldr r3, [r7, #20]
- 80049ae: f003 0301 and.w r3, r3, #1
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 80049b2: 2b00 cmp r3, #0
- 80049b4: d009 beq.n 80049ca <HAL_UART_IRQHandler+0x11e>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 80049b6: 687b ldr r3, [r7, #4]
- 80049b8: 681b ldr r3, [r3, #0]
- 80049ba: 2208 movs r2, #8
- 80049bc: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 80049be: 687b ldr r3, [r7, #4]
- 80049c0: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80049c2: f043 0208 orr.w r2, r3, #8
- 80049c6: 687b ldr r3, [r7, #4]
- 80049c8: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 80049ca: 687b ldr r3, [r7, #4]
- 80049cc: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80049ce: 2b00 cmp r3, #0
- 80049d0: d07f beq.n 8004ad2 <HAL_UART_IRQHandler+0x226>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 80049d2: 69fb ldr r3, [r7, #28]
- 80049d4: f003 0320 and.w r3, r3, #32
- 80049d8: 2b00 cmp r3, #0
- 80049da: d00c beq.n 80049f6 <HAL_UART_IRQHandler+0x14a>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 80049dc: 69bb ldr r3, [r7, #24]
- 80049de: f003 0320 and.w r3, r3, #32
- 80049e2: 2b00 cmp r3, #0
- 80049e4: d007 beq.n 80049f6 <HAL_UART_IRQHandler+0x14a>
- {
- if (huart->RxISR != NULL)
- 80049e6: 687b ldr r3, [r7, #4]
- 80049e8: 6e1b ldr r3, [r3, #96] ; 0x60
- 80049ea: 2b00 cmp r3, #0
- 80049ec: d003 beq.n 80049f6 <HAL_UART_IRQHandler+0x14a>
- {
- huart->RxISR(huart);
- 80049ee: 687b ldr r3, [r7, #4]
- 80049f0: 6e1b ldr r3, [r3, #96] ; 0x60
- 80049f2: 6878 ldr r0, [r7, #4]
- 80049f4: 4798 blx r3
- }
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- errorcode = huart->ErrorCode;
- 80049f6: 687b ldr r3, [r7, #4]
- 80049f8: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80049fa: 60fb str r3, [r7, #12]
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 80049fc: 687b ldr r3, [r7, #4]
- 80049fe: 681b ldr r3, [r3, #0]
- 8004a00: 689b ldr r3, [r3, #8]
- 8004a02: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004a06: 2b40 cmp r3, #64 ; 0x40
- 8004a08: d004 beq.n 8004a14 <HAL_UART_IRQHandler+0x168>
- ((errorcode & HAL_UART_ERROR_ORE) != 0U))
- 8004a0a: 68fb ldr r3, [r7, #12]
- 8004a0c: f003 0308 and.w r3, r3, #8
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8004a10: 2b00 cmp r3, #0
- 8004a12: d031 beq.n 8004a78 <HAL_UART_IRQHandler+0x1cc>
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
- 8004a14: 6878 ldr r0, [r7, #4]
- 8004a16: f000 fc36 bl 8005286 <UART_EndRxTransfer>
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004a1a: 687b ldr r3, [r7, #4]
- 8004a1c: 681b ldr r3, [r3, #0]
- 8004a1e: 689b ldr r3, [r3, #8]
- 8004a20: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004a24: 2b40 cmp r3, #64 ; 0x40
- 8004a26: d123 bne.n 8004a70 <HAL_UART_IRQHandler+0x1c4>
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 8004a28: 687b ldr r3, [r7, #4]
- 8004a2a: 681b ldr r3, [r3, #0]
- 8004a2c: 689a ldr r2, [r3, #8]
- 8004a2e: 687b ldr r3, [r7, #4]
- 8004a30: 681b ldr r3, [r3, #0]
- 8004a32: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8004a36: 609a str r2, [r3, #8]
-
- /* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL)
- 8004a38: 687b ldr r3, [r7, #4]
- 8004a3a: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004a3c: 2b00 cmp r3, #0
- 8004a3e: d013 beq.n 8004a68 <HAL_UART_IRQHandler+0x1bc>
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8004a40: 687b ldr r3, [r7, #4]
- 8004a42: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004a44: 4a26 ldr r2, [pc, #152] ; (8004ae0 <HAL_UART_IRQHandler+0x234>)
- 8004a46: 651a str r2, [r3, #80] ; 0x50
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 8004a48: 687b ldr r3, [r7, #4]
- 8004a4a: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004a4c: 4618 mov r0, r3
- 8004a4e: f7fd fa5c bl 8001f0a <HAL_DMA_Abort_IT>
- 8004a52: 4603 mov r3, r0
- 8004a54: 2b00 cmp r3, #0
- 8004a56: d016 beq.n 8004a86 <HAL_UART_IRQHandler+0x1da>
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 8004a58: 687b ldr r3, [r7, #4]
- 8004a5a: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004a5c: 6d1b ldr r3, [r3, #80] ; 0x50
- 8004a5e: 687a ldr r2, [r7, #4]
- 8004a60: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 8004a62: 4610 mov r0, r2
- 8004a64: 4798 blx r3
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004a66: e00e b.n 8004a86 <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004a68: 6878 ldr r0, [r7, #4]
- 8004a6a: f000 f845 bl 8004af8 <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004a6e: e00a b.n 8004a86 <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004a70: 6878 ldr r0, [r7, #4]
- 8004a72: f000 f841 bl 8004af8 <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004a76: e006 b.n 8004a86 <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8004a78: 6878 ldr r0, [r7, #4]
- 8004a7a: f000 f83d bl 8004af8 <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004a7e: 687b ldr r3, [r7, #4]
- 8004a80: 2200 movs r2, #0
- 8004a82: 67da str r2, [r3, #124] ; 0x7c
- }
- }
- return;
- 8004a84: e025 b.n 8004ad2 <HAL_UART_IRQHandler+0x226>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004a86: bf00 nop
- return;
- 8004a88: e023 b.n 8004ad2 <HAL_UART_IRQHandler+0x226>
-
- } /* End if some error occurs */
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if (((isrflags & USART_ISR_TXE) != 0U)
- 8004a8a: 69fb ldr r3, [r7, #28]
- 8004a8c: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004a90: 2b00 cmp r3, #0
- 8004a92: d00d beq.n 8004ab0 <HAL_UART_IRQHandler+0x204>
- && ((cr1its & USART_CR1_TXEIE) != 0U))
- 8004a94: 69bb ldr r3, [r7, #24]
- 8004a96: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004a9a: 2b00 cmp r3, #0
- 8004a9c: d008 beq.n 8004ab0 <HAL_UART_IRQHandler+0x204>
- {
- if (huart->TxISR != NULL)
- 8004a9e: 687b ldr r3, [r7, #4]
- 8004aa0: 6e5b ldr r3, [r3, #100] ; 0x64
- 8004aa2: 2b00 cmp r3, #0
- 8004aa4: d017 beq.n 8004ad6 <HAL_UART_IRQHandler+0x22a>
- {
- huart->TxISR(huart);
- 8004aa6: 687b ldr r3, [r7, #4]
- 8004aa8: 6e5b ldr r3, [r3, #100] ; 0x64
- 8004aaa: 6878 ldr r0, [r7, #4]
- 8004aac: 4798 blx r3
- }
- return;
- 8004aae: e012 b.n 8004ad6 <HAL_UART_IRQHandler+0x22a>
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
- 8004ab0: 69fb ldr r3, [r7, #28]
- 8004ab2: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004ab6: 2b00 cmp r3, #0
- 8004ab8: d00e beq.n 8004ad8 <HAL_UART_IRQHandler+0x22c>
- 8004aba: 69bb ldr r3, [r7, #24]
- 8004abc: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004ac0: 2b00 cmp r3, #0
- 8004ac2: d009 beq.n 8004ad8 <HAL_UART_IRQHandler+0x22c>
- {
- UART_EndTransmit_IT(huart);
- 8004ac4: 6878 ldr r0, [r7, #4]
- 8004ac6: f000 fc14 bl 80052f2 <UART_EndTransmit_IT>
- return;
- 8004aca: bf00 nop
- 8004acc: e004 b.n 8004ad8 <HAL_UART_IRQHandler+0x22c>
- return;
- 8004ace: bf00 nop
- 8004ad0: e002 b.n 8004ad8 <HAL_UART_IRQHandler+0x22c>
- return;
- 8004ad2: bf00 nop
- 8004ad4: e000 b.n 8004ad8 <HAL_UART_IRQHandler+0x22c>
- return;
- 8004ad6: bf00 nop
- }
-
-}
- 8004ad8: 3720 adds r7, #32
- 8004ada: 46bd mov sp, r7
- 8004adc: bd80 pop {r7, pc}
- 8004ade: bf00 nop
- 8004ae0: 080052c7 .word 0x080052c7
-
-08004ae4 <HAL_UART_TxCpltCallback>:
- * @brief Tx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- 8004ae4: b480 push {r7}
- 8004ae6: b083 sub sp, #12
- 8004ae8: af00 add r7, sp, #0
- 8004aea: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
- 8004aec: bf00 nop
- 8004aee: 370c adds r7, #12
- 8004af0: 46bd mov sp, r7
- 8004af2: f85d 7b04 ldr.w r7, [sp], #4
- 8004af6: 4770 bx lr
-
-08004af8 <HAL_UART_ErrorCallback>:
- * @brief UART error callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- 8004af8: b480 push {r7}
- 8004afa: b083 sub sp, #12
- 8004afc: af00 add r7, sp, #0
- 8004afe: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file.
- */
-}
- 8004b00: bf00 nop
- 8004b02: 370c adds r7, #12
- 8004b04: 46bd mov sp, r7
- 8004b06: f85d 7b04 ldr.w r7, [sp], #4
- 8004b0a: 4770 bx lr
-
-08004b0c <UART_SetConfig>:
- * @brief Configure the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- 8004b0c: b580 push {r7, lr}
- 8004b0e: b088 sub sp, #32
- 8004b10: af00 add r7, sp, #0
- 8004b12: 6078 str r0, [r7, #4]
- uint32_t tmpreg;
- uint16_t brrtemp;
- UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv = 0x00000000U;
- 8004b14: 2300 movs r3, #0
- 8004b16: 61bb str r3, [r7, #24]
- HAL_StatusTypeDef ret = HAL_OK;
- 8004b18: 2300 movs r3, #0
- 8004b1a: 75fb strb r3, [r7, #23]
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 8004b1c: 687b ldr r3, [r7, #4]
- 8004b1e: 689a ldr r2, [r3, #8]
- 8004b20: 687b ldr r3, [r7, #4]
- 8004b22: 691b ldr r3, [r3, #16]
- 8004b24: 431a orrs r2, r3
- 8004b26: 687b ldr r3, [r7, #4]
- 8004b28: 695b ldr r3, [r3, #20]
- 8004b2a: 431a orrs r2, r3
- 8004b2c: 687b ldr r3, [r7, #4]
- 8004b2e: 69db ldr r3, [r3, #28]
- 8004b30: 4313 orrs r3, r2
- 8004b32: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 8004b34: 687b ldr r3, [r7, #4]
- 8004b36: 681b ldr r3, [r3, #0]
- 8004b38: 681a ldr r2, [r3, #0]
- 8004b3a: 4bb1 ldr r3, [pc, #708] ; (8004e00 <UART_SetConfig+0x2f4>)
- 8004b3c: 4013 ands r3, r2
- 8004b3e: 687a ldr r2, [r7, #4]
- 8004b40: 6812 ldr r2, [r2, #0]
- 8004b42: 6939 ldr r1, [r7, #16]
- 8004b44: 430b orrs r3, r1
- 8004b46: 6013 str r3, [r2, #0]
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8004b48: 687b ldr r3, [r7, #4]
- 8004b4a: 681b ldr r3, [r3, #0]
- 8004b4c: 685b ldr r3, [r3, #4]
- 8004b4e: f423 5140 bic.w r1, r3, #12288 ; 0x3000
- 8004b52: 687b ldr r3, [r7, #4]
- 8004b54: 68da ldr r2, [r3, #12]
- 8004b56: 687b ldr r3, [r7, #4]
- 8004b58: 681b ldr r3, [r3, #0]
- 8004b5a: 430a orrs r2, r1
- 8004b5c: 605a str r2, [r3, #4]
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling (not applicable to LPUART) */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8004b5e: 687b ldr r3, [r7, #4]
- 8004b60: 699b ldr r3, [r3, #24]
- 8004b62: 613b str r3, [r7, #16]
-
- tmpreg |= huart->Init.OneBitSampling;
- 8004b64: 687b ldr r3, [r7, #4]
- 8004b66: 6a1b ldr r3, [r3, #32]
- 8004b68: 693a ldr r2, [r7, #16]
- 8004b6a: 4313 orrs r3, r2
- 8004b6c: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8004b6e: 687b ldr r3, [r7, #4]
- 8004b70: 681b ldr r3, [r3, #0]
- 8004b72: 689b ldr r3, [r3, #8]
- 8004b74: f423 6130 bic.w r1, r3, #2816 ; 0xb00
- 8004b78: 687b ldr r3, [r7, #4]
- 8004b7a: 681b ldr r3, [r3, #0]
- 8004b7c: 693a ldr r2, [r7, #16]
- 8004b7e: 430a orrs r2, r1
- 8004b80: 609a str r2, [r3, #8]
-
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
- 8004b82: 687b ldr r3, [r7, #4]
- 8004b84: 681b ldr r3, [r3, #0]
- 8004b86: 4a9f ldr r2, [pc, #636] ; (8004e04 <UART_SetConfig+0x2f8>)
- 8004b88: 4293 cmp r3, r2
- 8004b8a: d121 bne.n 8004bd0 <UART_SetConfig+0xc4>
- 8004b8c: 4b9e ldr r3, [pc, #632] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004b8e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004b92: f003 0303 and.w r3, r3, #3
- 8004b96: 2b03 cmp r3, #3
- 8004b98: d816 bhi.n 8004bc8 <UART_SetConfig+0xbc>
- 8004b9a: a201 add r2, pc, #4 ; (adr r2, 8004ba0 <UART_SetConfig+0x94>)
- 8004b9c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004ba0: 08004bb1 .word 0x08004bb1
- 8004ba4: 08004bbd .word 0x08004bbd
- 8004ba8: 08004bb7 .word 0x08004bb7
- 8004bac: 08004bc3 .word 0x08004bc3
- 8004bb0: 2301 movs r3, #1
- 8004bb2: 77fb strb r3, [r7, #31]
- 8004bb4: e151 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004bb6: 2302 movs r3, #2
- 8004bb8: 77fb strb r3, [r7, #31]
- 8004bba: e14e b.n 8004e5a <UART_SetConfig+0x34e>
- 8004bbc: 2304 movs r3, #4
- 8004bbe: 77fb strb r3, [r7, #31]
- 8004bc0: e14b b.n 8004e5a <UART_SetConfig+0x34e>
- 8004bc2: 2308 movs r3, #8
- 8004bc4: 77fb strb r3, [r7, #31]
- 8004bc6: e148 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004bc8: 2310 movs r3, #16
- 8004bca: 77fb strb r3, [r7, #31]
- 8004bcc: bf00 nop
- 8004bce: e144 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004bd0: 687b ldr r3, [r7, #4]
- 8004bd2: 681b ldr r3, [r3, #0]
- 8004bd4: 4a8d ldr r2, [pc, #564] ; (8004e0c <UART_SetConfig+0x300>)
- 8004bd6: 4293 cmp r3, r2
- 8004bd8: d134 bne.n 8004c44 <UART_SetConfig+0x138>
- 8004bda: 4b8b ldr r3, [pc, #556] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004bdc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004be0: f003 030c and.w r3, r3, #12
- 8004be4: 2b0c cmp r3, #12
- 8004be6: d829 bhi.n 8004c3c <UART_SetConfig+0x130>
- 8004be8: a201 add r2, pc, #4 ; (adr r2, 8004bf0 <UART_SetConfig+0xe4>)
- 8004bea: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004bee: bf00 nop
- 8004bf0: 08004c25 .word 0x08004c25
- 8004bf4: 08004c3d .word 0x08004c3d
- 8004bf8: 08004c3d .word 0x08004c3d
- 8004bfc: 08004c3d .word 0x08004c3d
- 8004c00: 08004c31 .word 0x08004c31
- 8004c04: 08004c3d .word 0x08004c3d
- 8004c08: 08004c3d .word 0x08004c3d
- 8004c0c: 08004c3d .word 0x08004c3d
- 8004c10: 08004c2b .word 0x08004c2b
- 8004c14: 08004c3d .word 0x08004c3d
- 8004c18: 08004c3d .word 0x08004c3d
- 8004c1c: 08004c3d .word 0x08004c3d
- 8004c20: 08004c37 .word 0x08004c37
- 8004c24: 2300 movs r3, #0
- 8004c26: 77fb strb r3, [r7, #31]
- 8004c28: e117 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c2a: 2302 movs r3, #2
- 8004c2c: 77fb strb r3, [r7, #31]
- 8004c2e: e114 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c30: 2304 movs r3, #4
- 8004c32: 77fb strb r3, [r7, #31]
- 8004c34: e111 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c36: 2308 movs r3, #8
- 8004c38: 77fb strb r3, [r7, #31]
- 8004c3a: e10e b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c3c: 2310 movs r3, #16
- 8004c3e: 77fb strb r3, [r7, #31]
- 8004c40: bf00 nop
- 8004c42: e10a b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c44: 687b ldr r3, [r7, #4]
- 8004c46: 681b ldr r3, [r3, #0]
- 8004c48: 4a71 ldr r2, [pc, #452] ; (8004e10 <UART_SetConfig+0x304>)
- 8004c4a: 4293 cmp r3, r2
- 8004c4c: d120 bne.n 8004c90 <UART_SetConfig+0x184>
- 8004c4e: 4b6e ldr r3, [pc, #440] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004c50: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004c54: f003 0330 and.w r3, r3, #48 ; 0x30
- 8004c58: 2b10 cmp r3, #16
- 8004c5a: d00f beq.n 8004c7c <UART_SetConfig+0x170>
- 8004c5c: 2b10 cmp r3, #16
- 8004c5e: d802 bhi.n 8004c66 <UART_SetConfig+0x15a>
- 8004c60: 2b00 cmp r3, #0
- 8004c62: d005 beq.n 8004c70 <UART_SetConfig+0x164>
- 8004c64: e010 b.n 8004c88 <UART_SetConfig+0x17c>
- 8004c66: 2b20 cmp r3, #32
- 8004c68: d005 beq.n 8004c76 <UART_SetConfig+0x16a>
- 8004c6a: 2b30 cmp r3, #48 ; 0x30
- 8004c6c: d009 beq.n 8004c82 <UART_SetConfig+0x176>
- 8004c6e: e00b b.n 8004c88 <UART_SetConfig+0x17c>
- 8004c70: 2300 movs r3, #0
- 8004c72: 77fb strb r3, [r7, #31]
- 8004c74: e0f1 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c76: 2302 movs r3, #2
- 8004c78: 77fb strb r3, [r7, #31]
- 8004c7a: e0ee b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c7c: 2304 movs r3, #4
- 8004c7e: 77fb strb r3, [r7, #31]
- 8004c80: e0eb b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c82: 2308 movs r3, #8
- 8004c84: 77fb strb r3, [r7, #31]
- 8004c86: e0e8 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c88: 2310 movs r3, #16
- 8004c8a: 77fb strb r3, [r7, #31]
- 8004c8c: bf00 nop
- 8004c8e: e0e4 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004c90: 687b ldr r3, [r7, #4]
- 8004c92: 681b ldr r3, [r3, #0]
- 8004c94: 4a5f ldr r2, [pc, #380] ; (8004e14 <UART_SetConfig+0x308>)
- 8004c96: 4293 cmp r3, r2
- 8004c98: d120 bne.n 8004cdc <UART_SetConfig+0x1d0>
- 8004c9a: 4b5b ldr r3, [pc, #364] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004c9c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004ca0: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 8004ca4: 2b40 cmp r3, #64 ; 0x40
- 8004ca6: d00f beq.n 8004cc8 <UART_SetConfig+0x1bc>
- 8004ca8: 2b40 cmp r3, #64 ; 0x40
- 8004caa: d802 bhi.n 8004cb2 <UART_SetConfig+0x1a6>
- 8004cac: 2b00 cmp r3, #0
- 8004cae: d005 beq.n 8004cbc <UART_SetConfig+0x1b0>
- 8004cb0: e010 b.n 8004cd4 <UART_SetConfig+0x1c8>
- 8004cb2: 2b80 cmp r3, #128 ; 0x80
- 8004cb4: d005 beq.n 8004cc2 <UART_SetConfig+0x1b6>
- 8004cb6: 2bc0 cmp r3, #192 ; 0xc0
- 8004cb8: d009 beq.n 8004cce <UART_SetConfig+0x1c2>
- 8004cba: e00b b.n 8004cd4 <UART_SetConfig+0x1c8>
- 8004cbc: 2300 movs r3, #0
- 8004cbe: 77fb strb r3, [r7, #31]
- 8004cc0: e0cb b.n 8004e5a <UART_SetConfig+0x34e>
- 8004cc2: 2302 movs r3, #2
- 8004cc4: 77fb strb r3, [r7, #31]
- 8004cc6: e0c8 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004cc8: 2304 movs r3, #4
- 8004cca: 77fb strb r3, [r7, #31]
- 8004ccc: e0c5 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004cce: 2308 movs r3, #8
- 8004cd0: 77fb strb r3, [r7, #31]
- 8004cd2: e0c2 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004cd4: 2310 movs r3, #16
- 8004cd6: 77fb strb r3, [r7, #31]
- 8004cd8: bf00 nop
- 8004cda: e0be b.n 8004e5a <UART_SetConfig+0x34e>
- 8004cdc: 687b ldr r3, [r7, #4]
- 8004cde: 681b ldr r3, [r3, #0]
- 8004ce0: 4a4d ldr r2, [pc, #308] ; (8004e18 <UART_SetConfig+0x30c>)
- 8004ce2: 4293 cmp r3, r2
- 8004ce4: d124 bne.n 8004d30 <UART_SetConfig+0x224>
- 8004ce6: 4b48 ldr r3, [pc, #288] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004ce8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004cec: f403 7340 and.w r3, r3, #768 ; 0x300
- 8004cf0: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004cf4: d012 beq.n 8004d1c <UART_SetConfig+0x210>
- 8004cf6: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004cfa: d802 bhi.n 8004d02 <UART_SetConfig+0x1f6>
- 8004cfc: 2b00 cmp r3, #0
- 8004cfe: d007 beq.n 8004d10 <UART_SetConfig+0x204>
- 8004d00: e012 b.n 8004d28 <UART_SetConfig+0x21c>
- 8004d02: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 8004d06: d006 beq.n 8004d16 <UART_SetConfig+0x20a>
- 8004d08: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8004d0c: d009 beq.n 8004d22 <UART_SetConfig+0x216>
- 8004d0e: e00b b.n 8004d28 <UART_SetConfig+0x21c>
- 8004d10: 2300 movs r3, #0
- 8004d12: 77fb strb r3, [r7, #31]
- 8004d14: e0a1 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d16: 2302 movs r3, #2
- 8004d18: 77fb strb r3, [r7, #31]
- 8004d1a: e09e b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d1c: 2304 movs r3, #4
- 8004d1e: 77fb strb r3, [r7, #31]
- 8004d20: e09b b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d22: 2308 movs r3, #8
- 8004d24: 77fb strb r3, [r7, #31]
- 8004d26: e098 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d28: 2310 movs r3, #16
- 8004d2a: 77fb strb r3, [r7, #31]
- 8004d2c: bf00 nop
- 8004d2e: e094 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d30: 687b ldr r3, [r7, #4]
- 8004d32: 681b ldr r3, [r3, #0]
- 8004d34: 4a39 ldr r2, [pc, #228] ; (8004e1c <UART_SetConfig+0x310>)
- 8004d36: 4293 cmp r3, r2
- 8004d38: d124 bne.n 8004d84 <UART_SetConfig+0x278>
- 8004d3a: 4b33 ldr r3, [pc, #204] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004d3c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004d40: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 8004d44: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004d48: d012 beq.n 8004d70 <UART_SetConfig+0x264>
- 8004d4a: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004d4e: d802 bhi.n 8004d56 <UART_SetConfig+0x24a>
- 8004d50: 2b00 cmp r3, #0
- 8004d52: d007 beq.n 8004d64 <UART_SetConfig+0x258>
- 8004d54: e012 b.n 8004d7c <UART_SetConfig+0x270>
- 8004d56: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 8004d5a: d006 beq.n 8004d6a <UART_SetConfig+0x25e>
- 8004d5c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 8004d60: d009 beq.n 8004d76 <UART_SetConfig+0x26a>
- 8004d62: e00b b.n 8004d7c <UART_SetConfig+0x270>
- 8004d64: 2301 movs r3, #1
- 8004d66: 77fb strb r3, [r7, #31]
- 8004d68: e077 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d6a: 2302 movs r3, #2
- 8004d6c: 77fb strb r3, [r7, #31]
- 8004d6e: e074 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d70: 2304 movs r3, #4
- 8004d72: 77fb strb r3, [r7, #31]
- 8004d74: e071 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d76: 2308 movs r3, #8
- 8004d78: 77fb strb r3, [r7, #31]
- 8004d7a: e06e b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d7c: 2310 movs r3, #16
- 8004d7e: 77fb strb r3, [r7, #31]
- 8004d80: bf00 nop
- 8004d82: e06a b.n 8004e5a <UART_SetConfig+0x34e>
- 8004d84: 687b ldr r3, [r7, #4]
- 8004d86: 681b ldr r3, [r3, #0]
- 8004d88: 4a25 ldr r2, [pc, #148] ; (8004e20 <UART_SetConfig+0x314>)
- 8004d8a: 4293 cmp r3, r2
- 8004d8c: d124 bne.n 8004dd8 <UART_SetConfig+0x2cc>
- 8004d8e: 4b1e ldr r3, [pc, #120] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004d90: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004d94: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 8004d98: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004d9c: d012 beq.n 8004dc4 <UART_SetConfig+0x2b8>
- 8004d9e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004da2: d802 bhi.n 8004daa <UART_SetConfig+0x29e>
- 8004da4: 2b00 cmp r3, #0
- 8004da6: d007 beq.n 8004db8 <UART_SetConfig+0x2ac>
- 8004da8: e012 b.n 8004dd0 <UART_SetConfig+0x2c4>
- 8004daa: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8004dae: d006 beq.n 8004dbe <UART_SetConfig+0x2b2>
- 8004db0: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 8004db4: d009 beq.n 8004dca <UART_SetConfig+0x2be>
- 8004db6: e00b b.n 8004dd0 <UART_SetConfig+0x2c4>
- 8004db8: 2300 movs r3, #0
- 8004dba: 77fb strb r3, [r7, #31]
- 8004dbc: e04d b.n 8004e5a <UART_SetConfig+0x34e>
- 8004dbe: 2302 movs r3, #2
- 8004dc0: 77fb strb r3, [r7, #31]
- 8004dc2: e04a b.n 8004e5a <UART_SetConfig+0x34e>
- 8004dc4: 2304 movs r3, #4
- 8004dc6: 77fb strb r3, [r7, #31]
- 8004dc8: e047 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004dca: 2308 movs r3, #8
- 8004dcc: 77fb strb r3, [r7, #31]
- 8004dce: e044 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004dd0: 2310 movs r3, #16
- 8004dd2: 77fb strb r3, [r7, #31]
- 8004dd4: bf00 nop
- 8004dd6: e040 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004dd8: 687b ldr r3, [r7, #4]
- 8004dda: 681b ldr r3, [r3, #0]
- 8004ddc: 4a11 ldr r2, [pc, #68] ; (8004e24 <UART_SetConfig+0x318>)
- 8004dde: 4293 cmp r3, r2
- 8004de0: d139 bne.n 8004e56 <UART_SetConfig+0x34a>
- 8004de2: 4b09 ldr r3, [pc, #36] ; (8004e08 <UART_SetConfig+0x2fc>)
- 8004de4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004de8: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8004dec: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004df0: d027 beq.n 8004e42 <UART_SetConfig+0x336>
- 8004df2: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004df6: d817 bhi.n 8004e28 <UART_SetConfig+0x31c>
- 8004df8: 2b00 cmp r3, #0
- 8004dfa: d01c beq.n 8004e36 <UART_SetConfig+0x32a>
- 8004dfc: e027 b.n 8004e4e <UART_SetConfig+0x342>
- 8004dfe: bf00 nop
- 8004e00: efff69f3 .word 0xefff69f3
- 8004e04: 40011000 .word 0x40011000
- 8004e08: 40023800 .word 0x40023800
- 8004e0c: 40004400 .word 0x40004400
- 8004e10: 40004800 .word 0x40004800
- 8004e14: 40004c00 .word 0x40004c00
- 8004e18: 40005000 .word 0x40005000
- 8004e1c: 40011400 .word 0x40011400
- 8004e20: 40007800 .word 0x40007800
- 8004e24: 40007c00 .word 0x40007c00
- 8004e28: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004e2c: d006 beq.n 8004e3c <UART_SetConfig+0x330>
- 8004e2e: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 8004e32: d009 beq.n 8004e48 <UART_SetConfig+0x33c>
- 8004e34: e00b b.n 8004e4e <UART_SetConfig+0x342>
- 8004e36: 2300 movs r3, #0
- 8004e38: 77fb strb r3, [r7, #31]
- 8004e3a: e00e b.n 8004e5a <UART_SetConfig+0x34e>
- 8004e3c: 2302 movs r3, #2
- 8004e3e: 77fb strb r3, [r7, #31]
- 8004e40: e00b b.n 8004e5a <UART_SetConfig+0x34e>
- 8004e42: 2304 movs r3, #4
- 8004e44: 77fb strb r3, [r7, #31]
- 8004e46: e008 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004e48: 2308 movs r3, #8
- 8004e4a: 77fb strb r3, [r7, #31]
- 8004e4c: e005 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004e4e: 2310 movs r3, #16
- 8004e50: 77fb strb r3, [r7, #31]
- 8004e52: bf00 nop
- 8004e54: e001 b.n 8004e5a <UART_SetConfig+0x34e>
- 8004e56: 2310 movs r3, #16
- 8004e58: 77fb strb r3, [r7, #31]
-
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8004e5a: 687b ldr r3, [r7, #4]
- 8004e5c: 69db ldr r3, [r3, #28]
- 8004e5e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004e62: d17c bne.n 8004f5e <UART_SetConfig+0x452>
- {
- switch (clocksource)
- 8004e64: 7ffb ldrb r3, [r7, #31]
- 8004e66: 2b08 cmp r3, #8
- 8004e68: d859 bhi.n 8004f1e <UART_SetConfig+0x412>
- 8004e6a: a201 add r2, pc, #4 ; (adr r2, 8004e70 <UART_SetConfig+0x364>)
- 8004e6c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004e70: 08004e95 .word 0x08004e95
- 8004e74: 08004eb3 .word 0x08004eb3
- 8004e78: 08004ed1 .word 0x08004ed1
- 8004e7c: 08004f1f .word 0x08004f1f
- 8004e80: 08004ee9 .word 0x08004ee9
- 8004e84: 08004f1f .word 0x08004f1f
- 8004e88: 08004f1f .word 0x08004f1f
- 8004e8c: 08004f1f .word 0x08004f1f
- 8004e90: 08004f07 .word 0x08004f07
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004e94: f7fd fe50 bl 8002b38 <HAL_RCC_GetPCLK1Freq>
- 8004e98: 4603 mov r3, r0
- 8004e9a: 005a lsls r2, r3, #1
- 8004e9c: 687b ldr r3, [r7, #4]
- 8004e9e: 685b ldr r3, [r3, #4]
- 8004ea0: 085b lsrs r3, r3, #1
- 8004ea2: 441a add r2, r3
- 8004ea4: 687b ldr r3, [r7, #4]
- 8004ea6: 685b ldr r3, [r3, #4]
- 8004ea8: fbb2 f3f3 udiv r3, r2, r3
- 8004eac: b29b uxth r3, r3
- 8004eae: 61bb str r3, [r7, #24]
- break;
- 8004eb0: e038 b.n 8004f24 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004eb2: f7fd fe55 bl 8002b60 <HAL_RCC_GetPCLK2Freq>
- 8004eb6: 4603 mov r3, r0
- 8004eb8: 005a lsls r2, r3, #1
- 8004eba: 687b ldr r3, [r7, #4]
- 8004ebc: 685b ldr r3, [r3, #4]
- 8004ebe: 085b lsrs r3, r3, #1
- 8004ec0: 441a add r2, r3
- 8004ec2: 687b ldr r3, [r7, #4]
- 8004ec4: 685b ldr r3, [r3, #4]
- 8004ec6: fbb2 f3f3 udiv r3, r2, r3
- 8004eca: b29b uxth r3, r3
- 8004ecc: 61bb str r3, [r7, #24]
- break;
- 8004ece: e029 b.n 8004f24 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8004ed0: 687b ldr r3, [r7, #4]
- 8004ed2: 685b ldr r3, [r3, #4]
- 8004ed4: 085a lsrs r2, r3, #1
- 8004ed6: 4b5d ldr r3, [pc, #372] ; (800504c <UART_SetConfig+0x540>)
- 8004ed8: 4413 add r3, r2
- 8004eda: 687a ldr r2, [r7, #4]
- 8004edc: 6852 ldr r2, [r2, #4]
- 8004ede: fbb3 f3f2 udiv r3, r3, r2
- 8004ee2: b29b uxth r3, r3
- 8004ee4: 61bb str r3, [r7, #24]
- break;
- 8004ee6: e01d b.n 8004f24 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8004ee8: f7fd fd68 bl 80029bc <HAL_RCC_GetSysClockFreq>
- 8004eec: 4603 mov r3, r0
- 8004eee: 005a lsls r2, r3, #1
- 8004ef0: 687b ldr r3, [r7, #4]
- 8004ef2: 685b ldr r3, [r3, #4]
- 8004ef4: 085b lsrs r3, r3, #1
- 8004ef6: 441a add r2, r3
- 8004ef8: 687b ldr r3, [r7, #4]
- 8004efa: 685b ldr r3, [r3, #4]
- 8004efc: fbb2 f3f3 udiv r3, r2, r3
- 8004f00: b29b uxth r3, r3
- 8004f02: 61bb str r3, [r7, #24]
- break;
- 8004f04: e00e b.n 8004f24 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 8004f06: 687b ldr r3, [r7, #4]
- 8004f08: 685b ldr r3, [r3, #4]
- 8004f0a: 085b lsrs r3, r3, #1
- 8004f0c: f503 3280 add.w r2, r3, #65536 ; 0x10000
- 8004f10: 687b ldr r3, [r7, #4]
- 8004f12: 685b ldr r3, [r3, #4]
- 8004f14: fbb2 f3f3 udiv r3, r2, r3
- 8004f18: b29b uxth r3, r3
- 8004f1a: 61bb str r3, [r7, #24]
- break;
- 8004f1c: e002 b.n 8004f24 <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8004f1e: 2301 movs r3, #1
- 8004f20: 75fb strb r3, [r7, #23]
- break;
- 8004f22: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8004f24: 69bb ldr r3, [r7, #24]
- 8004f26: 2b0f cmp r3, #15
- 8004f28: d916 bls.n 8004f58 <UART_SetConfig+0x44c>
- 8004f2a: 69bb ldr r3, [r7, #24]
- 8004f2c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8004f30: d212 bcs.n 8004f58 <UART_SetConfig+0x44c>
- {
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 8004f32: 69bb ldr r3, [r7, #24]
- 8004f34: b29b uxth r3, r3
- 8004f36: f023 030f bic.w r3, r3, #15
- 8004f3a: 81fb strh r3, [r7, #14]
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8004f3c: 69bb ldr r3, [r7, #24]
- 8004f3e: 085b lsrs r3, r3, #1
- 8004f40: b29b uxth r3, r3
- 8004f42: f003 0307 and.w r3, r3, #7
- 8004f46: b29a uxth r2, r3
- 8004f48: 89fb ldrh r3, [r7, #14]
- 8004f4a: 4313 orrs r3, r2
- 8004f4c: 81fb strh r3, [r7, #14]
- huart->Instance->BRR = brrtemp;
- 8004f4e: 687b ldr r3, [r7, #4]
- 8004f50: 681b ldr r3, [r3, #0]
- 8004f52: 89fa ldrh r2, [r7, #14]
- 8004f54: 60da str r2, [r3, #12]
- 8004f56: e06e b.n 8005036 <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 8004f58: 2301 movs r3, #1
- 8004f5a: 75fb strb r3, [r7, #23]
- 8004f5c: e06b b.n 8005036 <UART_SetConfig+0x52a>
- }
- }
- else
- {
- switch (clocksource)
- 8004f5e: 7ffb ldrb r3, [r7, #31]
- 8004f60: 2b08 cmp r3, #8
- 8004f62: d857 bhi.n 8005014 <UART_SetConfig+0x508>
- 8004f64: a201 add r2, pc, #4 ; (adr r2, 8004f6c <UART_SetConfig+0x460>)
- 8004f66: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004f6a: bf00 nop
- 8004f6c: 08004f91 .word 0x08004f91
- 8004f70: 08004fad .word 0x08004fad
- 8004f74: 08004fc9 .word 0x08004fc9
- 8004f78: 08005015 .word 0x08005015
- 8004f7c: 08004fe1 .word 0x08004fe1
- 8004f80: 08005015 .word 0x08005015
- 8004f84: 08005015 .word 0x08005015
- 8004f88: 08005015 .word 0x08005015
- 8004f8c: 08004ffd .word 0x08004ffd
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004f90: f7fd fdd2 bl 8002b38 <HAL_RCC_GetPCLK1Freq>
- 8004f94: 4602 mov r2, r0
- 8004f96: 687b ldr r3, [r7, #4]
- 8004f98: 685b ldr r3, [r3, #4]
- 8004f9a: 085b lsrs r3, r3, #1
- 8004f9c: 441a add r2, r3
- 8004f9e: 687b ldr r3, [r7, #4]
- 8004fa0: 685b ldr r3, [r3, #4]
- 8004fa2: fbb2 f3f3 udiv r3, r2, r3
- 8004fa6: b29b uxth r3, r3
- 8004fa8: 61bb str r3, [r7, #24]
- break;
- 8004faa: e036 b.n 800501a <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004fac: f7fd fdd8 bl 8002b60 <HAL_RCC_GetPCLK2Freq>
- 8004fb0: 4602 mov r2, r0
- 8004fb2: 687b ldr r3, [r7, #4]
- 8004fb4: 685b ldr r3, [r3, #4]
- 8004fb6: 085b lsrs r3, r3, #1
- 8004fb8: 441a add r2, r3
- 8004fba: 687b ldr r3, [r7, #4]
- 8004fbc: 685b ldr r3, [r3, #4]
- 8004fbe: fbb2 f3f3 udiv r3, r2, r3
- 8004fc2: b29b uxth r3, r3
- 8004fc4: 61bb str r3, [r7, #24]
- break;
- 8004fc6: e028 b.n 800501a <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 8004fc8: 687b ldr r3, [r7, #4]
- 8004fca: 685b ldr r3, [r3, #4]
- 8004fcc: 085a lsrs r2, r3, #1
- 8004fce: 4b20 ldr r3, [pc, #128] ; (8005050 <UART_SetConfig+0x544>)
- 8004fd0: 4413 add r3, r2
- 8004fd2: 687a ldr r2, [r7, #4]
- 8004fd4: 6852 ldr r2, [r2, #4]
- 8004fd6: fbb3 f3f2 udiv r3, r3, r2
- 8004fda: b29b uxth r3, r3
- 8004fdc: 61bb str r3, [r7, #24]
- break;
- 8004fde: e01c b.n 800501a <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8004fe0: f7fd fcec bl 80029bc <HAL_RCC_GetSysClockFreq>
- 8004fe4: 4602 mov r2, r0
- 8004fe6: 687b ldr r3, [r7, #4]
- 8004fe8: 685b ldr r3, [r3, #4]
- 8004fea: 085b lsrs r3, r3, #1
- 8004fec: 441a add r2, r3
- 8004fee: 687b ldr r3, [r7, #4]
- 8004ff0: 685b ldr r3, [r3, #4]
- 8004ff2: fbb2 f3f3 udiv r3, r2, r3
- 8004ff6: b29b uxth r3, r3
- 8004ff8: 61bb str r3, [r7, #24]
- break;
- 8004ffa: e00e b.n 800501a <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 8004ffc: 687b ldr r3, [r7, #4]
- 8004ffe: 685b ldr r3, [r3, #4]
- 8005000: 085b lsrs r3, r3, #1
- 8005002: f503 4200 add.w r2, r3, #32768 ; 0x8000
- 8005006: 687b ldr r3, [r7, #4]
- 8005008: 685b ldr r3, [r3, #4]
- 800500a: fbb2 f3f3 udiv r3, r2, r3
- 800500e: b29b uxth r3, r3
- 8005010: 61bb str r3, [r7, #24]
- break;
- 8005012: e002 b.n 800501a <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8005014: 2301 movs r3, #1
- 8005016: 75fb strb r3, [r7, #23]
- break;
- 8005018: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 800501a: 69bb ldr r3, [r7, #24]
- 800501c: 2b0f cmp r3, #15
- 800501e: d908 bls.n 8005032 <UART_SetConfig+0x526>
- 8005020: 69bb ldr r3, [r7, #24]
- 8005022: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8005026: d204 bcs.n 8005032 <UART_SetConfig+0x526>
- {
- huart->Instance->BRR = usartdiv;
- 8005028: 687b ldr r3, [r7, #4]
- 800502a: 681b ldr r3, [r3, #0]
- 800502c: 69ba ldr r2, [r7, #24]
- 800502e: 60da str r2, [r3, #12]
- 8005030: e001 b.n 8005036 <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 8005032: 2301 movs r3, #1
- 8005034: 75fb strb r3, [r7, #23]
- }
- }
-
-
- /* Clear ISR function pointers */
- huart->RxISR = NULL;
- 8005036: 687b ldr r3, [r7, #4]
- 8005038: 2200 movs r2, #0
- 800503a: 661a str r2, [r3, #96] ; 0x60
- huart->TxISR = NULL;
- 800503c: 687b ldr r3, [r7, #4]
- 800503e: 2200 movs r2, #0
- 8005040: 665a str r2, [r3, #100] ; 0x64
-
- return ret;
- 8005042: 7dfb ldrb r3, [r7, #23]
-}
- 8005044: 4618 mov r0, r3
- 8005046: 3720 adds r7, #32
- 8005048: 46bd mov sp, r7
- 800504a: bd80 pop {r7, pc}
- 800504c: 01e84800 .word 0x01e84800
- 8005050: 00f42400 .word 0x00f42400
-
-08005054 <UART_AdvFeatureConfig>:
- * @brief Configure the UART peripheral advanced features.
- * @param huart UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- 8005054: b480 push {r7}
- 8005056: b083 sub sp, #12
- 8005058: af00 add r7, sp, #0
- 800505a: 6078 str r0, [r7, #4]
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 800505c: 687b ldr r3, [r7, #4]
- 800505e: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005060: f003 0301 and.w r3, r3, #1
- 8005064: 2b00 cmp r3, #0
- 8005066: d00a beq.n 800507e <UART_AdvFeatureConfig+0x2a>
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8005068: 687b ldr r3, [r7, #4]
- 800506a: 681b ldr r3, [r3, #0]
- 800506c: 685b ldr r3, [r3, #4]
- 800506e: f423 3100 bic.w r1, r3, #131072 ; 0x20000
- 8005072: 687b ldr r3, [r7, #4]
- 8005074: 6a9a ldr r2, [r3, #40] ; 0x28
- 8005076: 687b ldr r3, [r7, #4]
- 8005078: 681b ldr r3, [r3, #0]
- 800507a: 430a orrs r2, r1
- 800507c: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 800507e: 687b ldr r3, [r7, #4]
- 8005080: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005082: f003 0302 and.w r3, r3, #2
- 8005086: 2b00 cmp r3, #0
- 8005088: d00a beq.n 80050a0 <UART_AdvFeatureConfig+0x4c>
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 800508a: 687b ldr r3, [r7, #4]
- 800508c: 681b ldr r3, [r3, #0]
- 800508e: 685b ldr r3, [r3, #4]
- 8005090: f423 3180 bic.w r1, r3, #65536 ; 0x10000
- 8005094: 687b ldr r3, [r7, #4]
- 8005096: 6ada ldr r2, [r3, #44] ; 0x2c
- 8005098: 687b ldr r3, [r7, #4]
- 800509a: 681b ldr r3, [r3, #0]
- 800509c: 430a orrs r2, r1
- 800509e: 605a str r2, [r3, #4]
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 80050a0: 687b ldr r3, [r7, #4]
- 80050a2: 6a5b ldr r3, [r3, #36] ; 0x24
- 80050a4: f003 0304 and.w r3, r3, #4
- 80050a8: 2b00 cmp r3, #0
- 80050aa: d00a beq.n 80050c2 <UART_AdvFeatureConfig+0x6e>
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 80050ac: 687b ldr r3, [r7, #4]
- 80050ae: 681b ldr r3, [r3, #0]
- 80050b0: 685b ldr r3, [r3, #4]
- 80050b2: f423 2180 bic.w r1, r3, #262144 ; 0x40000
- 80050b6: 687b ldr r3, [r7, #4]
- 80050b8: 6b1a ldr r2, [r3, #48] ; 0x30
- 80050ba: 687b ldr r3, [r7, #4]
- 80050bc: 681b ldr r3, [r3, #0]
- 80050be: 430a orrs r2, r1
- 80050c0: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 80050c2: 687b ldr r3, [r7, #4]
- 80050c4: 6a5b ldr r3, [r3, #36] ; 0x24
- 80050c6: f003 0308 and.w r3, r3, #8
- 80050ca: 2b00 cmp r3, #0
- 80050cc: d00a beq.n 80050e4 <UART_AdvFeatureConfig+0x90>
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 80050ce: 687b ldr r3, [r7, #4]
- 80050d0: 681b ldr r3, [r3, #0]
- 80050d2: 685b ldr r3, [r3, #4]
- 80050d4: f423 4100 bic.w r1, r3, #32768 ; 0x8000
- 80050d8: 687b ldr r3, [r7, #4]
- 80050da: 6b5a ldr r2, [r3, #52] ; 0x34
- 80050dc: 687b ldr r3, [r7, #4]
- 80050de: 681b ldr r3, [r3, #0]
- 80050e0: 430a orrs r2, r1
- 80050e2: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 80050e4: 687b ldr r3, [r7, #4]
- 80050e6: 6a5b ldr r3, [r3, #36] ; 0x24
- 80050e8: f003 0310 and.w r3, r3, #16
- 80050ec: 2b00 cmp r3, #0
- 80050ee: d00a beq.n 8005106 <UART_AdvFeatureConfig+0xb2>
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 80050f0: 687b ldr r3, [r7, #4]
- 80050f2: 681b ldr r3, [r3, #0]
- 80050f4: 689b ldr r3, [r3, #8]
- 80050f6: f423 5180 bic.w r1, r3, #4096 ; 0x1000
- 80050fa: 687b ldr r3, [r7, #4]
- 80050fc: 6b9a ldr r2, [r3, #56] ; 0x38
- 80050fe: 687b ldr r3, [r7, #4]
- 8005100: 681b ldr r3, [r3, #0]
- 8005102: 430a orrs r2, r1
- 8005104: 609a str r2, [r3, #8]
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 8005106: 687b ldr r3, [r7, #4]
- 8005108: 6a5b ldr r3, [r3, #36] ; 0x24
- 800510a: f003 0320 and.w r3, r3, #32
- 800510e: 2b00 cmp r3, #0
- 8005110: d00a beq.n 8005128 <UART_AdvFeatureConfig+0xd4>
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 8005112: 687b ldr r3, [r7, #4]
- 8005114: 681b ldr r3, [r3, #0]
- 8005116: 689b ldr r3, [r3, #8]
- 8005118: f423 5100 bic.w r1, r3, #8192 ; 0x2000
- 800511c: 687b ldr r3, [r7, #4]
- 800511e: 6bda ldr r2, [r3, #60] ; 0x3c
- 8005120: 687b ldr r3, [r7, #4]
- 8005122: 681b ldr r3, [r3, #0]
- 8005124: 430a orrs r2, r1
- 8005126: 609a str r2, [r3, #8]
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 8005128: 687b ldr r3, [r7, #4]
- 800512a: 6a5b ldr r3, [r3, #36] ; 0x24
- 800512c: f003 0340 and.w r3, r3, #64 ; 0x40
- 8005130: 2b00 cmp r3, #0
- 8005132: d01a beq.n 800516a <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 8005134: 687b ldr r3, [r7, #4]
- 8005136: 681b ldr r3, [r3, #0]
- 8005138: 685b ldr r3, [r3, #4]
- 800513a: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
- 800513e: 687b ldr r3, [r7, #4]
- 8005140: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005142: 687b ldr r3, [r7, #4]
- 8005144: 681b ldr r3, [r3, #0]
- 8005146: 430a orrs r2, r1
- 8005148: 605a str r2, [r3, #4]
- /* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 800514a: 687b ldr r3, [r7, #4]
- 800514c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800514e: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8005152: d10a bne.n 800516a <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8005154: 687b ldr r3, [r7, #4]
- 8005156: 681b ldr r3, [r3, #0]
- 8005158: 685b ldr r3, [r3, #4]
- 800515a: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
- 800515e: 687b ldr r3, [r7, #4]
- 8005160: 6c5a ldr r2, [r3, #68] ; 0x44
- 8005162: 687b ldr r3, [r7, #4]
- 8005164: 681b ldr r3, [r3, #0]
- 8005166: 430a orrs r2, r1
- 8005168: 605a str r2, [r3, #4]
- }
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 800516a: 687b ldr r3, [r7, #4]
- 800516c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800516e: f003 0380 and.w r3, r3, #128 ; 0x80
- 8005172: 2b00 cmp r3, #0
- 8005174: d00a beq.n 800518c <UART_AdvFeatureConfig+0x138>
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 8005176: 687b ldr r3, [r7, #4]
- 8005178: 681b ldr r3, [r3, #0]
- 800517a: 685b ldr r3, [r3, #4]
- 800517c: f423 2100 bic.w r1, r3, #524288 ; 0x80000
- 8005180: 687b ldr r3, [r7, #4]
- 8005182: 6c9a ldr r2, [r3, #72] ; 0x48
- 8005184: 687b ldr r3, [r7, #4]
- 8005186: 681b ldr r3, [r3, #0]
- 8005188: 430a orrs r2, r1
- 800518a: 605a str r2, [r3, #4]
- }
-}
- 800518c: bf00 nop
- 800518e: 370c adds r7, #12
- 8005190: 46bd mov sp, r7
- 8005192: f85d 7b04 ldr.w r7, [sp], #4
- 8005196: 4770 bx lr
-
-08005198 <UART_CheckIdleState>:
- * @brief Check the UART Idle State.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- 8005198: b580 push {r7, lr}
- 800519a: b086 sub sp, #24
- 800519c: af02 add r7, sp, #8
- 800519e: 6078 str r0, [r7, #4]
- uint32_t tickstart;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80051a0: 687b ldr r3, [r7, #4]
- 80051a2: 2200 movs r2, #0
- 80051a4: 67da str r2, [r3, #124] ; 0x7c
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 80051a6: f7fc fd93 bl 8001cd0 <HAL_GetTick>
- 80051aa: 60f8 str r0, [r7, #12]
-
- /* Check if the Transmitter is enabled */
- if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 80051ac: 687b ldr r3, [r7, #4]
- 80051ae: 681b ldr r3, [r3, #0]
- 80051b0: 681b ldr r3, [r3, #0]
- 80051b2: f003 0308 and.w r3, r3, #8
- 80051b6: 2b08 cmp r3, #8
- 80051b8: d10e bne.n 80051d8 <UART_CheckIdleState+0x40>
- {
- /* Wait until TEACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 80051ba: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
- 80051be: 9300 str r3, [sp, #0]
- 80051c0: 68fb ldr r3, [r7, #12]
- 80051c2: 2200 movs r2, #0
- 80051c4: f44f 1100 mov.w r1, #2097152 ; 0x200000
- 80051c8: 6878 ldr r0, [r7, #4]
- 80051ca: f000 f814 bl 80051f6 <UART_WaitOnFlagUntilTimeout>
- 80051ce: 4603 mov r3, r0
- 80051d0: 2b00 cmp r3, #0
- 80051d2: d001 beq.n 80051d8 <UART_CheckIdleState+0x40>
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- 80051d4: 2303 movs r3, #3
- 80051d6: e00a b.n 80051ee <UART_CheckIdleState+0x56>
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- 80051d8: 687b ldr r3, [r7, #4]
- 80051da: 2220 movs r2, #32
- 80051dc: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 80051de: 687b ldr r3, [r7, #4]
- 80051e0: 2220 movs r2, #32
- 80051e2: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 80051e4: 687b ldr r3, [r7, #4]
- 80051e6: 2200 movs r2, #0
- 80051e8: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 80051ec: 2300 movs r3, #0
-}
- 80051ee: 4618 mov r0, r3
- 80051f0: 3710 adds r7, #16
- 80051f2: 46bd mov sp, r7
- 80051f4: bd80 pop {r7, pc}
-
-080051f6 <UART_WaitOnFlagUntilTimeout>:
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- 80051f6: b580 push {r7, lr}
- 80051f8: b084 sub sp, #16
- 80051fa: af00 add r7, sp, #0
- 80051fc: 60f8 str r0, [r7, #12]
- 80051fe: 60b9 str r1, [r7, #8]
- 8005200: 603b str r3, [r7, #0]
- 8005202: 4613 mov r3, r2
- 8005204: 71fb strb r3, [r7, #7]
- /* Wait until flag is set */
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8005206: e02a b.n 800525e <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- 8005208: 69bb ldr r3, [r7, #24]
- 800520a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 800520e: d026 beq.n 800525e <UART_WaitOnFlagUntilTimeout+0x68>
- {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8005210: f7fc fd5e bl 8001cd0 <HAL_GetTick>
- 8005214: 4602 mov r2, r0
- 8005216: 683b ldr r3, [r7, #0]
- 8005218: 1ad3 subs r3, r2, r3
- 800521a: 69ba ldr r2, [r7, #24]
- 800521c: 429a cmp r2, r3
- 800521e: d302 bcc.n 8005226 <UART_WaitOnFlagUntilTimeout+0x30>
- 8005220: 69bb ldr r3, [r7, #24]
- 8005222: 2b00 cmp r3, #0
- 8005224: d11b bne.n 800525e <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 8005226: 68fb ldr r3, [r7, #12]
- 8005228: 681b ldr r3, [r3, #0]
- 800522a: 681a ldr r2, [r3, #0]
- 800522c: 68fb ldr r3, [r7, #12]
- 800522e: 681b ldr r3, [r3, #0]
- 8005230: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 8005234: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8005236: 68fb ldr r3, [r7, #12]
- 8005238: 681b ldr r3, [r3, #0]
- 800523a: 689a ldr r2, [r3, #8]
- 800523c: 68fb ldr r3, [r7, #12]
- 800523e: 681b ldr r3, [r3, #0]
- 8005240: f022 0201 bic.w r2, r2, #1
- 8005244: 609a str r2, [r3, #8]
-
- huart->gState = HAL_UART_STATE_READY;
- 8005246: 68fb ldr r3, [r7, #12]
- 8005248: 2220 movs r2, #32
- 800524a: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 800524c: 68fb ldr r3, [r7, #12]
- 800524e: 2220 movs r2, #32
- 8005250: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8005252: 68fb ldr r3, [r7, #12]
- 8005254: 2200 movs r2, #0
- 8005256: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_TIMEOUT;
- 800525a: 2303 movs r3, #3
- 800525c: e00f b.n 800527e <UART_WaitOnFlagUntilTimeout+0x88>
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 800525e: 68fb ldr r3, [r7, #12]
- 8005260: 681b ldr r3, [r3, #0]
- 8005262: 69da ldr r2, [r3, #28]
- 8005264: 68bb ldr r3, [r7, #8]
- 8005266: 4013 ands r3, r2
- 8005268: 68ba ldr r2, [r7, #8]
- 800526a: 429a cmp r2, r3
- 800526c: bf0c ite eq
- 800526e: 2301 moveq r3, #1
- 8005270: 2300 movne r3, #0
- 8005272: b2db uxtb r3, r3
- 8005274: 461a mov r2, r3
- 8005276: 79fb ldrb r3, [r7, #7]
- 8005278: 429a cmp r2, r3
- 800527a: d0c5 beq.n 8005208 <UART_WaitOnFlagUntilTimeout+0x12>
- }
- }
- }
- return HAL_OK;
- 800527c: 2300 movs r3, #0
-}
- 800527e: 4618 mov r0, r3
- 8005280: 3710 adds r7, #16
- 8005282: 46bd mov sp, r7
- 8005284: bd80 pop {r7, pc}
-
-08005286 <UART_EndRxTransfer>:
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- 8005286: b480 push {r7}
- 8005288: b083 sub sp, #12
- 800528a: af00 add r7, sp, #0
- 800528c: 6078 str r0, [r7, #4]
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 800528e: 687b ldr r3, [r7, #4]
- 8005290: 681b ldr r3, [r3, #0]
- 8005292: 681a ldr r2, [r3, #0]
- 8005294: 687b ldr r3, [r7, #4]
- 8005296: 681b ldr r3, [r3, #0]
- 8005298: f422 7290 bic.w r2, r2, #288 ; 0x120
- 800529c: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800529e: 687b ldr r3, [r7, #4]
- 80052a0: 681b ldr r3, [r3, #0]
- 80052a2: 689a ldr r2, [r3, #8]
- 80052a4: 687b ldr r3, [r7, #4]
- 80052a6: 681b ldr r3, [r3, #0]
- 80052a8: f022 0201 bic.w r2, r2, #1
- 80052ac: 609a str r2, [r3, #8]
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 80052ae: 687b ldr r3, [r7, #4]
- 80052b0: 2220 movs r2, #32
- 80052b2: 679a str r2, [r3, #120] ; 0x78
-
- /* Reset RxIsr function pointer */
- huart->RxISR = NULL;
- 80052b4: 687b ldr r3, [r7, #4]
- 80052b6: 2200 movs r2, #0
- 80052b8: 661a str r2, [r3, #96] ; 0x60
-}
- 80052ba: bf00 nop
- 80052bc: 370c adds r7, #12
- 80052be: 46bd mov sp, r7
- 80052c0: f85d 7b04 ldr.w r7, [sp], #4
- 80052c4: 4770 bx lr
-
-080052c6 <UART_DMAAbortOnError>:
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- 80052c6: b580 push {r7, lr}
- 80052c8: b084 sub sp, #16
- 80052ca: af00 add r7, sp, #0
- 80052cc: 6078 str r0, [r7, #4]
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 80052ce: 687b ldr r3, [r7, #4]
- 80052d0: 6b9b ldr r3, [r3, #56] ; 0x38
- 80052d2: 60fb str r3, [r7, #12]
- huart->RxXferCount = 0U;
- 80052d4: 68fb ldr r3, [r7, #12]
- 80052d6: 2200 movs r2, #0
- 80052d8: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->TxXferCount = 0U;
- 80052dc: 68fb ldr r3, [r7, #12]
- 80052de: 2200 movs r2, #0
- 80052e0: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 80052e4: 68f8 ldr r0, [r7, #12]
- 80052e6: f7ff fc07 bl 8004af8 <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 80052ea: bf00 nop
- 80052ec: 3710 adds r7, #16
- 80052ee: 46bd mov sp, r7
- 80052f0: bd80 pop {r7, pc}
-
-080052f2 <UART_EndTransmit_IT>:
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- 80052f2: b580 push {r7, lr}
- 80052f4: b082 sub sp, #8
- 80052f6: af00 add r7, sp, #0
- 80052f8: 6078 str r0, [r7, #4]
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- 80052fa: 687b ldr r3, [r7, #4]
- 80052fc: 681b ldr r3, [r3, #0]
- 80052fe: 681a ldr r2, [r3, #0]
- 8005300: 687b ldr r3, [r7, #4]
- 8005302: 681b ldr r3, [r3, #0]
- 8005304: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8005308: 601a str r2, [r3, #0]
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 800530a: 687b ldr r3, [r7, #4]
- 800530c: 2220 movs r2, #32
- 800530e: 675a str r2, [r3, #116] ; 0x74
-
- /* Cleat TxISR function pointer */
- huart->TxISR = NULL;
- 8005310: 687b ldr r3, [r7, #4]
- 8005312: 2200 movs r2, #0
- 8005314: 665a str r2, [r3, #100] ; 0x64
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx complete callback*/
- huart->TxCpltCallback(huart);
-#else
- /*Call legacy weak Tx complete callback*/
- HAL_UART_TxCpltCallback(huart);
- 8005316: 6878 ldr r0, [r7, #4]
- 8005318: f7ff fbe4 bl 8004ae4 <HAL_UART_TxCpltCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 800531c: bf00 nop
- 800531e: 3708 adds r7, #8
- 8005320: 46bd mov sp, r7
- 8005322: bd80 pop {r7, pc}
-
-08005324 <UART_RxISR_8BIT>:
- * @brief RX interrrupt handler for 7 or 8 bits data word length .
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
-{
- 8005324: b580 push {r7, lr}
- 8005326: b084 sub sp, #16
- 8005328: af00 add r7, sp, #0
- 800532a: 6078 str r0, [r7, #4]
- uint16_t uhMask = huart->Mask;
- 800532c: 687b ldr r3, [r7, #4]
- 800532e: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 8005332: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 8005334: 687b ldr r3, [r7, #4]
- 8005336: 6f9b ldr r3, [r3, #120] ; 0x78
- 8005338: 2b22 cmp r3, #34 ; 0x22
- 800533a: d13a bne.n 80053b2 <UART_RxISR_8BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 800533c: 687b ldr r3, [r7, #4]
- 800533e: 681b ldr r3, [r3, #0]
- 8005340: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005342: 81bb strh r3, [r7, #12]
- *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
- 8005344: 89bb ldrh r3, [r7, #12]
- 8005346: b2d9 uxtb r1, r3
- 8005348: 89fb ldrh r3, [r7, #14]
- 800534a: b2da uxtb r2, r3
- 800534c: 687b ldr r3, [r7, #4]
- 800534e: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005350: 400a ands r2, r1
- 8005352: b2d2 uxtb r2, r2
- 8005354: 701a strb r2, [r3, #0]
- huart->pRxBuffPtr++;
- 8005356: 687b ldr r3, [r7, #4]
- 8005358: 6d5b ldr r3, [r3, #84] ; 0x54
- 800535a: 1c5a adds r2, r3, #1
- 800535c: 687b ldr r3, [r7, #4]
- 800535e: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 8005360: 687b ldr r3, [r7, #4]
- 8005362: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8005366: b29b uxth r3, r3
- 8005368: 3b01 subs r3, #1
- 800536a: b29a uxth r2, r3
- 800536c: 687b ldr r3, [r7, #4]
- 800536e: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 8005372: 687b ldr r3, [r7, #4]
- 8005374: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8005378: b29b uxth r3, r3
- 800537a: 2b00 cmp r3, #0
- 800537c: d121 bne.n 80053c2 <UART_RxISR_8BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 800537e: 687b ldr r3, [r7, #4]
- 8005380: 681b ldr r3, [r3, #0]
- 8005382: 681a ldr r2, [r3, #0]
- 8005384: 687b ldr r3, [r7, #4]
- 8005386: 681b ldr r3, [r3, #0]
- 8005388: f422 7290 bic.w r2, r2, #288 ; 0x120
- 800538c: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800538e: 687b ldr r3, [r7, #4]
- 8005390: 681b ldr r3, [r3, #0]
- 8005392: 689a ldr r2, [r3, #8]
- 8005394: 687b ldr r3, [r7, #4]
- 8005396: 681b ldr r3, [r3, #0]
- 8005398: f022 0201 bic.w r2, r2, #1
- 800539c: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 800539e: 687b ldr r3, [r7, #4]
- 80053a0: 2220 movs r2, #32
- 80053a2: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 80053a4: 687b ldr r3, [r7, #4]
- 80053a6: 2200 movs r2, #0
- 80053a8: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 80053aa: 6878 ldr r0, [r7, #4]
- 80053ac: f7fc f8c0 bl 8001530 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 80053b0: e007 b.n 80053c2 <UART_RxISR_8BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 80053b2: 687b ldr r3, [r7, #4]
- 80053b4: 681b ldr r3, [r3, #0]
- 80053b6: 699a ldr r2, [r3, #24]
- 80053b8: 687b ldr r3, [r7, #4]
- 80053ba: 681b ldr r3, [r3, #0]
- 80053bc: f042 0208 orr.w r2, r2, #8
- 80053c0: 619a str r2, [r3, #24]
-}
- 80053c2: bf00 nop
- 80053c4: 3710 adds r7, #16
- 80053c6: 46bd mov sp, r7
- 80053c8: bd80 pop {r7, pc}
-
-080053ca <UART_RxISR_16BIT>:
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
-{
- 80053ca: b580 push {r7, lr}
- 80053cc: b084 sub sp, #16
- 80053ce: af00 add r7, sp, #0
- 80053d0: 6078 str r0, [r7, #4]
- uint16_t *tmp;
- uint16_t uhMask = huart->Mask;
- 80053d2: 687b ldr r3, [r7, #4]
- 80053d4: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 80053d8: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 80053da: 687b ldr r3, [r7, #4]
- 80053dc: 6f9b ldr r3, [r3, #120] ; 0x78
- 80053de: 2b22 cmp r3, #34 ; 0x22
- 80053e0: d13a bne.n 8005458 <UART_RxISR_16BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 80053e2: 687b ldr r3, [r7, #4]
- 80053e4: 681b ldr r3, [r3, #0]
- 80053e6: 6a5b ldr r3, [r3, #36] ; 0x24
- 80053e8: 81bb strh r3, [r7, #12]
- tmp = (uint16_t *) huart->pRxBuffPtr ;
- 80053ea: 687b ldr r3, [r7, #4]
- 80053ec: 6d5b ldr r3, [r3, #84] ; 0x54
- 80053ee: 60bb str r3, [r7, #8]
- *tmp = (uint16_t)(uhdata & uhMask);
- 80053f0: 89ba ldrh r2, [r7, #12]
- 80053f2: 89fb ldrh r3, [r7, #14]
- 80053f4: 4013 ands r3, r2
- 80053f6: b29a uxth r2, r3
- 80053f8: 68bb ldr r3, [r7, #8]
- 80053fa: 801a strh r2, [r3, #0]
- huart->pRxBuffPtr += 2U;
- 80053fc: 687b ldr r3, [r7, #4]
- 80053fe: 6d5b ldr r3, [r3, #84] ; 0x54
- 8005400: 1c9a adds r2, r3, #2
- 8005402: 687b ldr r3, [r7, #4]
- 8005404: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 8005406: 687b ldr r3, [r7, #4]
- 8005408: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 800540c: b29b uxth r3, r3
- 800540e: 3b01 subs r3, #1
- 8005410: b29a uxth r2, r3
- 8005412: 687b ldr r3, [r7, #4]
- 8005414: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 8005418: 687b ldr r3, [r7, #4]
- 800541a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 800541e: b29b uxth r3, r3
- 8005420: 2b00 cmp r3, #0
- 8005422: d121 bne.n 8005468 <UART_RxISR_16BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8005424: 687b ldr r3, [r7, #4]
- 8005426: 681b ldr r3, [r3, #0]
- 8005428: 681a ldr r2, [r3, #0]
- 800542a: 687b ldr r3, [r7, #4]
- 800542c: 681b ldr r3, [r3, #0]
- 800542e: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8005432: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8005434: 687b ldr r3, [r7, #4]
- 8005436: 681b ldr r3, [r3, #0]
- 8005438: 689a ldr r2, [r3, #8]
- 800543a: 687b ldr r3, [r7, #4]
- 800543c: 681b ldr r3, [r3, #0]
- 800543e: f022 0201 bic.w r2, r2, #1
- 8005442: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 8005444: 687b ldr r3, [r7, #4]
- 8005446: 2220 movs r2, #32
- 8005448: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 800544a: 687b ldr r3, [r7, #4]
- 800544c: 2200 movs r2, #0
- 800544e: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 8005450: 6878 ldr r0, [r7, #4]
- 8005452: f7fc f86d bl 8001530 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 8005456: e007 b.n 8005468 <UART_RxISR_16BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 8005458: 687b ldr r3, [r7, #4]
- 800545a: 681b ldr r3, [r3, #0]
- 800545c: 699a ldr r2, [r3, #24]
- 800545e: 687b ldr r3, [r7, #4]
- 8005460: 681b ldr r3, [r3, #0]
- 8005462: f042 0208 orr.w r2, r2, #8
- 8005466: 619a str r2, [r3, #24]
-}
- 8005468: bf00 nop
- 800546a: 3710 adds r7, #16
- 800546c: 46bd mov sp, r7
- 800546e: bd80 pop {r7, pc}
-
-08005470 <__libc_init_array>:
- 8005470: b570 push {r4, r5, r6, lr}
- 8005472: 4e0d ldr r6, [pc, #52] ; (80054a8 <__libc_init_array+0x38>)
- 8005474: 4c0d ldr r4, [pc, #52] ; (80054ac <__libc_init_array+0x3c>)
- 8005476: 1ba4 subs r4, r4, r6
- 8005478: 10a4 asrs r4, r4, #2
- 800547a: 2500 movs r5, #0
- 800547c: 42a5 cmp r5, r4
- 800547e: d109 bne.n 8005494 <__libc_init_array+0x24>
- 8005480: 4e0b ldr r6, [pc, #44] ; (80054b0 <__libc_init_array+0x40>)
- 8005482: 4c0c ldr r4, [pc, #48] ; (80054b4 <__libc_init_array+0x44>)
- 8005484: f000 f820 bl 80054c8 <_init>
- 8005488: 1ba4 subs r4, r4, r6
- 800548a: 10a4 asrs r4, r4, #2
- 800548c: 2500 movs r5, #0
- 800548e: 42a5 cmp r5, r4
- 8005490: d105 bne.n 800549e <__libc_init_array+0x2e>
- 8005492: bd70 pop {r4, r5, r6, pc}
- 8005494: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8005498: 4798 blx r3
- 800549a: 3501 adds r5, #1
- 800549c: e7ee b.n 800547c <__libc_init_array+0xc>
- 800549e: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 80054a2: 4798 blx r3
- 80054a4: 3501 adds r5, #1
- 80054a6: e7f2 b.n 800548e <__libc_init_array+0x1e>
- 80054a8: 08005500 .word 0x08005500
- 80054ac: 08005500 .word 0x08005500
- 80054b0: 08005500 .word 0x08005500
- 80054b4: 08005508 .word 0x08005508
-
-080054b8 <memset>:
- 80054b8: 4402 add r2, r0
- 80054ba: 4603 mov r3, r0
- 80054bc: 4293 cmp r3, r2
- 80054be: d100 bne.n 80054c2 <memset+0xa>
- 80054c0: 4770 bx lr
- 80054c2: f803 1b01 strb.w r1, [r3], #1
- 80054c6: e7f9 b.n 80054bc <memset+0x4>
-
-080054c8 <_init>:
- 80054c8: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80054ca: bf00 nop
- 80054cc: bcf8 pop {r3, r4, r5, r6, r7}
- 80054ce: bc08 pop {r3}
- 80054d0: 469e mov lr, r3
- 80054d2: 4770 bx lr
-
-080054d4 <_fini>:
- 80054d4: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80054d6: bf00 nop
- 80054d8: bcf8 pop {r3, r4, r5, r6, r7}
- 80054da: bc08 pop {r3}
- 80054dc: 469e mov lr, r3
- 80054de: 4770 bx lr
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-ELF_SRCS :=
-C_UPPER_SRCS :=
-CXX_SRCS :=
-C++_SRCS :=
-OBJ_SRCS :=
-S_SRCS :=
-CC_SRCS :=
-C_SRCS :=
-CPP_SRCS :=
-S_UPPER_SRCS :=
-O_SRCS :=
-CC_DEPS :=
-SIZE_OUTPUT :=
-OBJDUMP_LIST :=
-C++_DEPS :=
-EXECUTABLES :=
-OBJS :=
-C_UPPER_DEPS :=
-CXX_DEPS :=
-C_DEPS :=
-CPP_DEPS :=
-
-# Every subdirectory with source files must be described here
-SUBDIRS := \
-Core/Src \
-Core/Startup \
-Drivers/STM32F7xx_HAL_Driver/Src \
-
projects / pioneer-stm32 / commitdiff