# otto
Material regarding my stage with Iralab, designing and realizing a 2 wheeled robot
+The main program is located in otto_controller_source[https://github.com/iralabdisco/otto/otto_controller_source].
+
+You can find various useful tools inside the utils[https://github.com/iralabdisco/otto/utils] folder.
+
See the [wiki](https://github.com/iralabdisco/otto/wiki) for more info about this projects
Follow [Google C++ guideline](https://google.github.io/styleguide/cppguide.html) while working on the project
if (duty_cycle >= 0) {
// HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET);
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
+ if (duty_cycle > 790)
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ else
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
} else {
// HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
+ if (duty_cycle < 790)
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ else
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
}
\r
//PID\r
\r
-Pid left_pid(100, 10, 0.0);\r
-Pid right_pid(300, 50, 0.0);\r
+Pid left_pid(690, 0, 0);\r
+Pid right_pid(650, 100, 0.0);\r
Pid cross_pid(1, 0.1, 0.0);\r
\r
int left_dutycycle;\r
int right_dutycycle;\r
+int *address;\r
\r
//MotorController\r
MotorController left_motor(sleep1_GPIO_Port,\r
- sleep1_Pin,\r
- dir1_GPIO_Port,\r
- dir1_Pin,\r
- &htim4,\r
- TIM_CHANNEL_4);\r
+sleep1_Pin,\r
+ dir1_GPIO_Port,\r
+ dir1_Pin,\r
+ &htim4,\r
+ TIM_CHANNEL_4);\r
MotorController right_motor(sleep2_GPIO_Port,\r
- sleep2_Pin,\r
- dir2_GPIO_Port,\r
- dir2_Pin,\r
- &htim4,\r
- TIM_CHANNEL_3);\r
+sleep2_Pin,\r
+ dir2_GPIO_Port,\r
+ dir2_Pin,\r
+ &htim4,\r
+ TIM_CHANNEL_3);\r
\r
//Communication\r
uint8_t *tx_buffer;\r
\r
//test stuff\r
bool flag = true;\r
+int time;\r
+int new_time;\r
+float rx_test;\r
+int state = 1; //0 si muove, 1 si ferma\r
\r
/* USER CODE END PV */\r
\r
tx_buffer = (uint8_t*) &odom_msg;\r
rx_buffer = (uint8_t*) &vel_msg;\r
\r
+ address = &left_dutycycle;\r
+\r
//Enables UART RX interrupt\r
// HAL_UART_Receive_IT(&huart6, rx_buffer, 8);\r
\r
+ //test plot stuff\r
+ HAL_UART_Receive_IT(&huart6, (uint8_t*) &rx_test, 4);\r
+\r
//Enables TIM3 interrupt (used for PID control)\r
-// HAL_TIM_Base_Start_IT(&htim3);\r
+ HAL_TIM_Base_Start_IT(&htim3);\r
\r
//Enables TIM6 interrupt (used for periodic transmission)\r
- HAL_TIM_Base_Start_IT(&htim6);\r
+// HAL_TIM_Base_Start_IT(&htim6);\r
\r
/* USER CODE END 2 */\r
\r
/* Infinite loop */\r
/* USER CODE BEGIN WHILE */\r
while (1) {\r
-\r
/* USER CODE END WHILE */\r
\r
/* USER CODE BEGIN 3 */\r
\r
/* USER CODE END TIM3_Init 1 */\r
htim3.Instance = TIM3;\r
- htim3.Init.Prescaler = 9999;\r
+ htim3.Init.Prescaler = 999;\r
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;\r
htim3.Init.Period = 159;\r
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\r
/* USER CODE BEGIN 4 */\r
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {\r
\r
- //TIMER 10Hz PID control\r
+ //TIMER 100Hz PID control\r
if (htim->Instance == TIM3) {\r
\r
-// left_pid.set(1.0);\r
- right_pid.set(-0.5);\r
-\r
+// left_pid.set(0.5);\r
+// right_pid.set(2);\r
+//\r
// left_velocity = left_encoder.GetLinearVelocity();\r
- right_velocity = right_encoder.GetLinearVelocity();\r
+// right_velocity = right_encoder.GetLinearVelocity();\r
// left_dutycycle = left_pid.update(left_velocity);\r
- right_dutycycle = right_pid.update(right_velocity);\r
-\r
+// right_dutycycle = right_pid.update(right_velocity);\r
+//\r
// left_motor.set_speed(left_dutycycle);\r
- right_motor.set_speed(right_dutycycle);\r
+// right_motor.set_speed(right_dutycycle);\r
+//\r
+// new_time = HAL_GetTick();\r
+\r
+ if (state == 0) {\r
+ left_velocity += 0.01;\r
+ right_velocity += 0.1;\r
+ HAL_UART_Transmit(&huart6, (uint8_t*) &rx_test, 4, 100);\r
+ }\r
+\r
}\r
\r
//TIMER 2Hz Transmit\r
if (htim->Instance == TIM6) {\r
- if(left_dutycycle >= 790){\r
+ if (left_dutycycle >= 790) {\r
flag = false;\r
- } else if(left_dutycycle <= -790){\r
+ } else if (left_dutycycle <= -790) {\r
flag = true;\r
}\r
\r
}\r
\r
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {\r
- float left_setpoint;\r
- float right_setpoint;\r
-\r
- left_setpoint = -(vel_msg.angular_velocity * baseline)\r
- + vel_msg.linear_velocity;\r
- right_setpoint = vel_msg.linear_velocity * 2 - left_setpoint;\r
-\r
- left_pid.set(left_setpoint);\r
- right_pid.set(right_setpoint);\r
+// float left_setpoint;\r
+// float right_setpoint;\r
+//\r
+// left_setpoint = -(vel_msg.angular_velocity * baseline)\r
+// + vel_msg.linear_velocity;\r
+// right_setpoint = vel_msg.linear_velocity * 2 - left_setpoint;\r
+//\r
+// left_pid.set(left_setpoint);\r
+// right_pid.set(right_setpoint);\r
\r
//TODO cross pid\r
\r
//abilita interrupt nuovamente\r
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);\r
+// HAL_UART_Receive_IT(&huart6, rx_buffer, 8);\r
+\r
+ //test plot\r
+ HAL_UART_Receive_IT(&huart6, (uint8_t*) &rx_test, 4);\r
\r
}\r
\r
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {\r
if (GPIO_Pin == GPIO_PIN_13) {\r
- left_motor.brake();\r
- right_motor.brake();\r
- while(1){\r
+ if (state == 0) {\r
+ state = 1;\r
+ left_motor.brake();\r
+ right_motor.brake();\r
+ }\r
\r
+ else if (state == 1) {\r
+ state = 0;\r
}\r
+\r
}\r
}\r
/* USER CODE END 4 */\r
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 00004dc4 080001f8 080001f8 000101f8 2**2
+ 1 .text 000050d0 080001f8 080001f8 000101f8 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000018 08004fbc 08004fbc 00014fbc 2**2
+ 2 .rodata 00000018 080052c8 080052c8 000152c8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 08004fd4 08004fd4 00020010 2**0
+ 3 .ARM.extab 00000000 080052e0 080052e0 00020014 2**0
CONTENTS
- 4 .ARM 00000008 08004fd4 08004fd4 00014fd4 2**2
+ 4 .ARM 00000008 080052e0 080052e0 000152e0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 08004fdc 08004fdc 00020010 2**0
+ 5 .preinit_array 00000000 080052e8 080052e8 00020014 2**0
CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000008 08004fdc 08004fdc 00014fdc 2**2
+ 6 .init_array 00000008 080052e8 080052e8 000152e8 2**2
CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 08004fe4 08004fe4 00014fe4 2**2
+ 7 .fini_array 00000004 080052f0 080052f0 000152f0 2**2
CONTENTS, ALLOC, LOAD, DATA
- 8 .data 00000010 20000000 08004fe8 00020000 2**2
+ 8 .data 00000014 20000000 080052f4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 00000384 20000010 08004ff8 00020010 2**2
+ 9 .bss 0000038c 20000014 08005308 00020014 2**2
ALLOC
- 10 ._user_heap_stack 00000604 20000394 08004ff8 00020394 2**0
+ 10 ._user_heap_stack 00000600 200003a0 08005308 000203a0 2**0
ALLOC
- 11 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0
+ 11 .ARM.attributes 0000002e 00000000 00000000 00020014 2**0
CONTENTS, READONLY
- 12 .debug_info 0000db58 00000000 00000000 0002003e 2**0
+ 12 .debug_info 0000daea 00000000 00000000 00020042 2**0
CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00001e8f 00000000 00000000 0002db96 2**0
+ 13 .debug_abbrev 00001e6a 00000000 00000000 0002db2c 2**0
CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000d58 00000000 00000000 0002fa28 2**3
+ 14 .debug_aranges 00000d48 00000000 00000000 0002f998 2**3
CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000c70 00000000 00000000 00030780 2**3
+ 15 .debug_ranges 00000c60 00000000 00000000 000306e0 2**3
CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 000281fd 00000000 00000000 000313f0 2**0
+ 16 .debug_macro 000281fd 00000000 00000000 00031340 2**0
CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 00009a74 00000000 00000000 000595ed 2**0
+ 17 .debug_line 00009b10 00000000 00000000 0005953d 2**0
CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000f1cb9 00000000 00000000 00063061 2**0
+ 18 .debug_str 000f1c94 00000000 00000000 0006304d 2**0
CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 00154d1a 2**0
+ 19 .comment 0000007b 00000000 00000000 00154ce1 2**0
CONTENTS, READONLY
- 20 .debug_frame 00003818 00000000 00000000 00154d98 2**2
+ 20 .debug_frame 000037cc 00000000 00000000 00154d5c 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
800020a: 2301 movs r3, #1
800020c: 7023 strb r3, [r4, #0]
800020e: bd10 pop {r4, pc}
- 8000210: 20000010 .word 0x20000010
+ 8000210: 20000014 .word 0x20000014
8000214: 00000000 .word 0x00000000
- 8000218: 08004fa4 .word 0x08004fa4
+ 8000218: 080052b0 .word 0x080052b0
0800021c <frame_dummy>:
800021c: b508 push {r3, lr}
8000226: f3af 8000 nop.w
800022a: bd08 pop {r3, pc}
800022c: 00000000 .word 0x00000000
- 8000230: 20000014 .word 0x20000014
- 8000234: 08004fa4 .word 0x08004fa4
+ 8000230: 20000018 .word 0x20000018
+ 8000234: 080052b0 .word 0x080052b0
08000238 <__aeabi_uldivmod>:
8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
80005ce: 681b ldr r3, [r3, #0]
80005d0: 213c movs r1, #60 ; 0x3c
80005d2: 4618 mov r0, r3
- 80005d4: f002 ff16 bl 8003404 <HAL_TIM_Encoder_Start>
+ 80005d4: f002 ff54 bl 8003480 <HAL_TIM_Encoder_Start>
this->ResetCount();
80005d8: 6878 ldr r0, [r7, #4]
80005da: f7ff ffc2 bl 8000562 <_ZN7Encoder10ResetCountEv>
80005e0: 2200 movs r2, #0
80005e2: 605a str r2, [r3, #4]
this->current_millis_ = HAL_GetTick();
- 80005e4: f001 fa2a bl 8001a3c <HAL_GetTick>
+ 80005e4: f001 fa68 bl 8001ab8 <HAL_GetTick>
80005e8: 4602 mov r2, r0
80005ea: 687b ldr r3, [r7, #4]
80005ec: 609a str r2, [r3, #8]
8000602: 687b ldr r3, [r7, #4]
8000604: 605a str r2, [r3, #4]
this->current_millis_ = HAL_GetTick();
- 8000606: f001 fa19 bl 8001a3c <HAL_GetTick>
+ 8000606: f001 fa57 bl 8001ab8 <HAL_GetTick>
800060a: 4602 mov r2, r0
800060c: 687b ldr r3, [r7, #4]
800060e: 609a str r2, [r3, #8]
80007b0: 695b ldr r3, [r3, #20]
80007b2: 4619 mov r1, r3
80007b4: 4610 mov r0, r2
- 80007b6: f002 fd4f bl 8003258 <HAL_TIM_PWM_Start>
+ 80007b6: f002 fd8d bl 80032d4 <HAL_TIM_PWM_Start>
}
80007ba: bf00 nop
80007bc: 3708 adds r7, #8
if (duty_cycle >= 0) {
80007cc: 683b ldr r3, [r7, #0]
80007ce: 2b00 cmp r3, #0
- 80007d0: db3f blt.n 8000852 <_ZN15MotorController9set_speedEi+0x90>
+ 80007d0: f2c0 8083 blt.w 80008da <_ZN15MotorController9set_speedEi+0x118>
// HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_RESET);
- 80007d2: 687b ldr r3, [r7, #4]
- 80007d4: 6898 ldr r0, [r3, #8]
- 80007d6: 687b ldr r3, [r7, #4]
- 80007d8: 899b ldrh r3, [r3, #12]
- 80007da: 2200 movs r2, #0
- 80007dc: 4619 mov r1, r3
- 80007de: f001 fc17 bl 8002010 <HAL_GPIO_WritePin>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 80007e2: 687b ldr r3, [r7, #4]
- 80007e4: 695b ldr r3, [r3, #20]
- 80007e6: 2b00 cmp r3, #0
- 80007e8: d105 bne.n 80007f6 <_ZN15MotorController9set_speedEi+0x34>
- 80007ea: 683a ldr r2, [r7, #0]
- 80007ec: 687b ldr r3, [r7, #4]
- 80007ee: 691b ldr r3, [r3, #16]
- 80007f0: 681b ldr r3, [r3, #0]
- 80007f2: 635a str r2, [r3, #52] ; 0x34
-// HAL_GPIO_WritePin(sleep_gpio_port_, sleep_pin_, GPIO_PIN_SET);
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
+ 80007d4: 687b ldr r3, [r7, #4]
+ 80007d6: 6898 ldr r0, [r3, #8]
+ 80007d8: 687b ldr r3, [r7, #4]
+ 80007da: 899b ldrh r3, [r3, #12]
+ 80007dc: 2200 movs r2, #0
+ 80007de: 4619 mov r1, r3
+ 80007e0: f001 fc54 bl 800208c <HAL_GPIO_WritePin>
+ if (duty_cycle > 790)
+ 80007e4: 683b ldr r3, [r7, #0]
+ 80007e6: f240 3216 movw r2, #790 ; 0x316
+ 80007ea: 4293 cmp r3, r2
+ 80007ec: dd3d ble.n 800086a <_ZN15MotorController9set_speedEi+0xa8>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 80007ee: 687b ldr r3, [r7, #4]
+ 80007f0: 695b ldr r3, [r3, #20]
+ 80007f2: 2b00 cmp r3, #0
+ 80007f4: d106 bne.n 8000804 <_ZN15MotorController9set_speedEi+0x42>
+ 80007f6: 687b ldr r3, [r7, #4]
+ 80007f8: 691b ldr r3, [r3, #16]
+ 80007fa: 681b ldr r3, [r3, #0]
+ 80007fc: f240 3216 movw r2, #790 ; 0x316
+ 8000800: 635a str r2, [r3, #52] ; 0x34
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ else
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
}
}
- 80007f4: e072 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 80007f6: 687b ldr r3, [r7, #4]
- 80007f8: 695b ldr r3, [r3, #20]
- 80007fa: 2b04 cmp r3, #4
- 80007fc: d105 bne.n 800080a <_ZN15MotorController9set_speedEi+0x48>
- 80007fe: 683a ldr r2, [r7, #0]
- 8000800: 687b ldr r3, [r7, #4]
- 8000802: 691b ldr r3, [r3, #16]
- 8000804: 681b ldr r3, [r3, #0]
- 8000806: 639a str r2, [r3, #56] ; 0x38
- }
- 8000808: e068 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 800080a: 687b ldr r3, [r7, #4]
- 800080c: 695b ldr r3, [r3, #20]
- 800080e: 2b08 cmp r3, #8
- 8000810: d105 bne.n 800081e <_ZN15MotorController9set_speedEi+0x5c>
- 8000812: 683a ldr r2, [r7, #0]
- 8000814: 687b ldr r3, [r7, #4]
- 8000816: 691b ldr r3, [r3, #16]
- 8000818: 681b ldr r3, [r3, #0]
- 800081a: 63da str r2, [r3, #60] ; 0x3c
- }
- 800081c: e05e b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 800081e: 687b ldr r3, [r7, #4]
- 8000820: 695b ldr r3, [r3, #20]
- 8000822: 2b0c cmp r3, #12
- 8000824: d105 bne.n 8000832 <_ZN15MotorController9set_speedEi+0x70>
- 8000826: 683a ldr r2, [r7, #0]
- 8000828: 687b ldr r3, [r7, #4]
- 800082a: 691b ldr r3, [r3, #16]
- 800082c: 681b ldr r3, [r3, #0]
- 800082e: 641a str r2, [r3, #64] ; 0x40
- }
- 8000830: e054 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 8000832: 687b ldr r3, [r7, #4]
- 8000834: 695b ldr r3, [r3, #20]
- 8000836: 2b10 cmp r3, #16
- 8000838: d105 bne.n 8000846 <_ZN15MotorController9set_speedEi+0x84>
- 800083a: 683a ldr r2, [r7, #0]
- 800083c: 687b ldr r3, [r7, #4]
- 800083e: 691b ldr r3, [r3, #16]
- 8000840: 681b ldr r3, [r3, #0]
- 8000842: 659a str r2, [r3, #88] ; 0x58
- }
- 8000844: e04a b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
- 8000846: 683a ldr r2, [r7, #0]
- 8000848: 687b ldr r3, [r7, #4]
- 800084a: 691b ldr r3, [r3, #16]
- 800084c: 681b ldr r3, [r3, #0]
- 800084e: 65da str r2, [r3, #92] ; 0x5c
- }
- 8000850: e044 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
- 8000852: 687b ldr r3, [r7, #4]
- 8000854: 6898 ldr r0, [r3, #8]
- 8000856: 687b ldr r3, [r7, #4]
- 8000858: 899b ldrh r3, [r3, #12]
- 800085a: 2201 movs r2, #1
- 800085c: 4619 mov r1, r3
- 800085e: f001 fbd7 bl 8002010 <HAL_GPIO_WritePin>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 8000862: 687b ldr r3, [r7, #4]
- 8000864: 695b ldr r3, [r3, #20]
- 8000866: 2b00 cmp r3, #0
- 8000868: d106 bne.n 8000878 <_ZN15MotorController9set_speedEi+0xb6>
- 800086a: 683b ldr r3, [r7, #0]
- 800086c: 425a negs r2, r3
- 800086e: 687b ldr r3, [r7, #4]
- 8000870: 691b ldr r3, [r3, #16]
- 8000872: 681b ldr r3, [r3, #0]
- 8000874: 635a str r2, [r3, #52] ; 0x34
- }
- 8000876: e031 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 8000878: 687b ldr r3, [r7, #4]
- 800087a: 695b ldr r3, [r3, #20]
- 800087c: 2b04 cmp r3, #4
- 800087e: d106 bne.n 800088e <_ZN15MotorController9set_speedEi+0xcc>
- 8000880: 683b ldr r3, [r7, #0]
- 8000882: 425a negs r2, r3
- 8000884: 687b ldr r3, [r7, #4]
- 8000886: 691b ldr r3, [r3, #16]
- 8000888: 681b ldr r3, [r3, #0]
- 800088a: 639a str r2, [r3, #56] ; 0x38
- }
- 800088c: e026 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 800088e: 687b ldr r3, [r7, #4]
- 8000890: 695b ldr r3, [r3, #20]
- 8000892: 2b08 cmp r3, #8
- 8000894: d106 bne.n 80008a4 <_ZN15MotorController9set_speedEi+0xe2>
- 8000896: 683b ldr r3, [r7, #0]
- 8000898: 425a negs r2, r3
- 800089a: 687b ldr r3, [r7, #4]
- 800089c: 691b ldr r3, [r3, #16]
- 800089e: 681b ldr r3, [r3, #0]
- 80008a0: 63da str r2, [r3, #60] ; 0x3c
- }
- 80008a2: e01b b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 80008a4: 687b ldr r3, [r7, #4]
- 80008a6: 695b ldr r3, [r3, #20]
- 80008a8: 2b0c cmp r3, #12
- 80008aa: d106 bne.n 80008ba <_ZN15MotorController9set_speedEi+0xf8>
- 80008ac: 683b ldr r3, [r7, #0]
- 80008ae: 425a negs r2, r3
+ 8000802: e0f2 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 8000804: 687b ldr r3, [r7, #4]
+ 8000806: 695b ldr r3, [r3, #20]
+ 8000808: 2b04 cmp r3, #4
+ 800080a: d106 bne.n 800081a <_ZN15MotorController9set_speedEi+0x58>
+ 800080c: 687b ldr r3, [r7, #4]
+ 800080e: 691b ldr r3, [r3, #16]
+ 8000810: 681b ldr r3, [r3, #0]
+ 8000812: f240 3216 movw r2, #790 ; 0x316
+ 8000816: 639a str r2, [r3, #56] ; 0x38
+ }
+ 8000818: e0e7 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 800081a: 687b ldr r3, [r7, #4]
+ 800081c: 695b ldr r3, [r3, #20]
+ 800081e: 2b08 cmp r3, #8
+ 8000820: d106 bne.n 8000830 <_ZN15MotorController9set_speedEi+0x6e>
+ 8000822: 687b ldr r3, [r7, #4]
+ 8000824: 691b ldr r3, [r3, #16]
+ 8000826: 681b ldr r3, [r3, #0]
+ 8000828: f240 3216 movw r2, #790 ; 0x316
+ 800082c: 63da str r2, [r3, #60] ; 0x3c
+ }
+ 800082e: e0dc b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 8000830: 687b ldr r3, [r7, #4]
+ 8000832: 695b ldr r3, [r3, #20]
+ 8000834: 2b0c cmp r3, #12
+ 8000836: d106 bne.n 8000846 <_ZN15MotorController9set_speedEi+0x84>
+ 8000838: 687b ldr r3, [r7, #4]
+ 800083a: 691b ldr r3, [r3, #16]
+ 800083c: 681b ldr r3, [r3, #0]
+ 800083e: f240 3216 movw r2, #790 ; 0x316
+ 8000842: 641a str r2, [r3, #64] ; 0x40
+ }
+ 8000844: e0d1 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 8000846: 687b ldr r3, [r7, #4]
+ 8000848: 695b ldr r3, [r3, #20]
+ 800084a: 2b10 cmp r3, #16
+ 800084c: d106 bne.n 800085c <_ZN15MotorController9set_speedEi+0x9a>
+ 800084e: 687b ldr r3, [r7, #4]
+ 8000850: 691b ldr r3, [r3, #16]
+ 8000852: 681b ldr r3, [r3, #0]
+ 8000854: f240 3216 movw r2, #790 ; 0x316
+ 8000858: 659a str r2, [r3, #88] ; 0x58
+ }
+ 800085a: e0c6 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 800085c: 687b ldr r3, [r7, #4]
+ 800085e: 691b ldr r3, [r3, #16]
+ 8000860: 681b ldr r3, [r3, #0]
+ 8000862: f240 3216 movw r2, #790 ; 0x316
+ 8000866: 65da str r2, [r3, #92] ; 0x5c
+ }
+ 8000868: e0bf b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
+ 800086a: 687b ldr r3, [r7, #4]
+ 800086c: 695b ldr r3, [r3, #20]
+ 800086e: 2b00 cmp r3, #0
+ 8000870: d105 bne.n 800087e <_ZN15MotorController9set_speedEi+0xbc>
+ 8000872: 683a ldr r2, [r7, #0]
+ 8000874: 687b ldr r3, [r7, #4]
+ 8000876: 691b ldr r3, [r3, #16]
+ 8000878: 681b ldr r3, [r3, #0]
+ 800087a: 635a str r2, [r3, #52] ; 0x34
+ }
+ 800087c: e0b5 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
+ 800087e: 687b ldr r3, [r7, #4]
+ 8000880: 695b ldr r3, [r3, #20]
+ 8000882: 2b04 cmp r3, #4
+ 8000884: d105 bne.n 8000892 <_ZN15MotorController9set_speedEi+0xd0>
+ 8000886: 683a ldr r2, [r7, #0]
+ 8000888: 687b ldr r3, [r7, #4]
+ 800088a: 691b ldr r3, [r3, #16]
+ 800088c: 681b ldr r3, [r3, #0]
+ 800088e: 639a str r2, [r3, #56] ; 0x38
+ }
+ 8000890: e0ab b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
+ 8000892: 687b ldr r3, [r7, #4]
+ 8000894: 695b ldr r3, [r3, #20]
+ 8000896: 2b08 cmp r3, #8
+ 8000898: d105 bne.n 80008a6 <_ZN15MotorController9set_speedEi+0xe4>
+ 800089a: 683a ldr r2, [r7, #0]
+ 800089c: 687b ldr r3, [r7, #4]
+ 800089e: 691b ldr r3, [r3, #16]
+ 80008a0: 681b ldr r3, [r3, #0]
+ 80008a2: 63da str r2, [r3, #60] ; 0x3c
+ }
+ 80008a4: e0a1 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
+ 80008a6: 687b ldr r3, [r7, #4]
+ 80008a8: 695b ldr r3, [r3, #20]
+ 80008aa: 2b0c cmp r3, #12
+ 80008ac: d105 bne.n 80008ba <_ZN15MotorController9set_speedEi+0xf8>
+ 80008ae: 683a ldr r2, [r7, #0]
80008b0: 687b ldr r3, [r7, #4]
80008b2: 691b ldr r3, [r3, #16]
80008b4: 681b ldr r3, [r3, #0]
80008b6: 641a str r2, [r3, #64] ; 0x40
}
- 80008b8: e010 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
- __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
+ 80008b8: e097 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
80008ba: 687b ldr r3, [r7, #4]
80008bc: 695b ldr r3, [r3, #20]
80008be: 2b10 cmp r3, #16
- 80008c0: d106 bne.n 80008d0 <_ZN15MotorController9set_speedEi+0x10e>
- 80008c2: 683b ldr r3, [r7, #0]
- 80008c4: 425a negs r2, r3
- 80008c6: 687b ldr r3, [r7, #4]
- 80008c8: 691b ldr r3, [r3, #16]
- 80008ca: 681b ldr r3, [r3, #0]
- 80008cc: 659a str r2, [r3, #88] ; 0x58
- }
- 80008ce: e005 b.n 80008dc <_ZN15MotorController9set_speedEi+0x11a>
+ 80008c0: d105 bne.n 80008ce <_ZN15MotorController9set_speedEi+0x10c>
+ 80008c2: 683a ldr r2, [r7, #0]
+ 80008c4: 687b ldr r3, [r7, #4]
+ 80008c6: 691b ldr r3, [r3, #16]
+ 80008c8: 681b ldr r3, [r3, #0]
+ 80008ca: 659a str r2, [r3, #88] ; 0x58
+ }
+ 80008cc: e08d b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, duty_cycle);
+ 80008ce: 683a ldr r2, [r7, #0]
+ 80008d0: 687b ldr r3, [r7, #4]
+ 80008d2: 691b ldr r3, [r3, #16]
+ 80008d4: 681b ldr r3, [r3, #0]
+ 80008d6: 65da str r2, [r3, #92] ; 0x5c
+ }
+ 80008d8: e087 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ HAL_GPIO_WritePin(dir_gpio_port_, dir_pin_, GPIO_PIN_SET);
+ 80008da: 687b ldr r3, [r7, #4]
+ 80008dc: 6898 ldr r0, [r3, #8]
+ 80008de: 687b ldr r3, [r7, #4]
+ 80008e0: 899b ldrh r3, [r3, #12]
+ 80008e2: 2201 movs r2, #1
+ 80008e4: 4619 mov r1, r3
+ 80008e6: f001 fbd1 bl 800208c <HAL_GPIO_WritePin>
+ if (duty_cycle < 790)
+ 80008ea: 683b ldr r3, [r7, #0]
+ 80008ec: f240 3215 movw r2, #789 ; 0x315
+ 80008f0: 4293 cmp r3, r2
+ 80008f2: dc3d bgt.n 8000970 <_ZN15MotorController9set_speedEi+0x1ae>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 80008f4: 687b ldr r3, [r7, #4]
+ 80008f6: 695b ldr r3, [r3, #20]
+ 80008f8: 2b00 cmp r3, #0
+ 80008fa: d106 bne.n 800090a <_ZN15MotorController9set_speedEi+0x148>
+ 80008fc: 687b ldr r3, [r7, #4]
+ 80008fe: 691b ldr r3, [r3, #16]
+ 8000900: 681b ldr r3, [r3, #0]
+ 8000902: f240 3216 movw r2, #790 ; 0x316
+ 8000906: 635a str r2, [r3, #52] ; 0x34
+ }
+ 8000908: e06f b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 800090a: 687b ldr r3, [r7, #4]
+ 800090c: 695b ldr r3, [r3, #20]
+ 800090e: 2b04 cmp r3, #4
+ 8000910: d106 bne.n 8000920 <_ZN15MotorController9set_speedEi+0x15e>
+ 8000912: 687b ldr r3, [r7, #4]
+ 8000914: 691b ldr r3, [r3, #16]
+ 8000916: 681b ldr r3, [r3, #0]
+ 8000918: f240 3216 movw r2, #790 ; 0x316
+ 800091c: 639a str r2, [r3, #56] ; 0x38
+ }
+ 800091e: e064 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 8000920: 687b ldr r3, [r7, #4]
+ 8000922: 695b ldr r3, [r3, #20]
+ 8000924: 2b08 cmp r3, #8
+ 8000926: d106 bne.n 8000936 <_ZN15MotorController9set_speedEi+0x174>
+ 8000928: 687b ldr r3, [r7, #4]
+ 800092a: 691b ldr r3, [r3, #16]
+ 800092c: 681b ldr r3, [r3, #0]
+ 800092e: f240 3216 movw r2, #790 ; 0x316
+ 8000932: 63da str r2, [r3, #60] ; 0x3c
+ }
+ 8000934: e059 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 8000936: 687b ldr r3, [r7, #4]
+ 8000938: 695b ldr r3, [r3, #20]
+ 800093a: 2b0c cmp r3, #12
+ 800093c: d106 bne.n 800094c <_ZN15MotorController9set_speedEi+0x18a>
+ 800093e: 687b ldr r3, [r7, #4]
+ 8000940: 691b ldr r3, [r3, #16]
+ 8000942: 681b ldr r3, [r3, #0]
+ 8000944: f240 3216 movw r2, #790 ; 0x316
+ 8000948: 641a str r2, [r3, #64] ; 0x40
+ }
+ 800094a: e04e b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 800094c: 687b ldr r3, [r7, #4]
+ 800094e: 695b ldr r3, [r3, #20]
+ 8000950: 2b10 cmp r3, #16
+ 8000952: d106 bne.n 8000962 <_ZN15MotorController9set_speedEi+0x1a0>
+ 8000954: 687b ldr r3, [r7, #4]
+ 8000956: 691b ldr r3, [r3, #16]
+ 8000958: 681b ldr r3, [r3, #0]
+ 800095a: f240 3216 movw r2, #790 ; 0x316
+ 800095e: 659a str r2, [r3, #88] ; 0x58
+ }
+ 8000960: e043 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 790);
+ 8000962: 687b ldr r3, [r7, #4]
+ 8000964: 691b ldr r3, [r3, #16]
+ 8000966: 681b ldr r3, [r3, #0]
+ 8000968: f240 3216 movw r2, #790 ; 0x316
+ 800096c: 65da str r2, [r3, #92] ; 0x5c
+ }
+ 800096e: e03c b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
+ 8000970: 687b ldr r3, [r7, #4]
+ 8000972: 695b ldr r3, [r3, #20]
+ 8000974: 2b00 cmp r3, #0
+ 8000976: d106 bne.n 8000986 <_ZN15MotorController9set_speedEi+0x1c4>
+ 8000978: 683b ldr r3, [r7, #0]
+ 800097a: 425a negs r2, r3
+ 800097c: 687b ldr r3, [r7, #4]
+ 800097e: 691b ldr r3, [r3, #16]
+ 8000980: 681b ldr r3, [r3, #0]
+ 8000982: 635a str r2, [r3, #52] ; 0x34
+ }
+ 8000984: e031 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
+ 8000986: 687b ldr r3, [r7, #4]
+ 8000988: 695b ldr r3, [r3, #20]
+ 800098a: 2b04 cmp r3, #4
+ 800098c: d106 bne.n 800099c <_ZN15MotorController9set_speedEi+0x1da>
+ 800098e: 683b ldr r3, [r7, #0]
+ 8000990: 425a negs r2, r3
+ 8000992: 687b ldr r3, [r7, #4]
+ 8000994: 691b ldr r3, [r3, #16]
+ 8000996: 681b ldr r3, [r3, #0]
+ 8000998: 639a str r2, [r3, #56] ; 0x38
+ }
+ 800099a: e026 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
+ 800099c: 687b ldr r3, [r7, #4]
+ 800099e: 695b ldr r3, [r3, #20]
+ 80009a0: 2b08 cmp r3, #8
+ 80009a2: d106 bne.n 80009b2 <_ZN15MotorController9set_speedEi+0x1f0>
+ 80009a4: 683b ldr r3, [r7, #0]
+ 80009a6: 425a negs r2, r3
+ 80009a8: 687b ldr r3, [r7, #4]
+ 80009aa: 691b ldr r3, [r3, #16]
+ 80009ac: 681b ldr r3, [r3, #0]
+ 80009ae: 63da str r2, [r3, #60] ; 0x3c
+ }
+ 80009b0: e01b b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
- 80008d0: 683b ldr r3, [r7, #0]
- 80008d2: 425a negs r2, r3
- 80008d4: 687b ldr r3, [r7, #4]
- 80008d6: 691b ldr r3, [r3, #16]
- 80008d8: 681b ldr r3, [r3, #0]
- 80008da: 65da str r2, [r3, #92] ; 0x5c
+ 80009b2: 687b ldr r3, [r7, #4]
+ 80009b4: 695b ldr r3, [r3, #20]
+ 80009b6: 2b0c cmp r3, #12
+ 80009b8: d106 bne.n 80009c8 <_ZN15MotorController9set_speedEi+0x206>
+ 80009ba: 683b ldr r3, [r7, #0]
+ 80009bc: 425a negs r2, r3
+ 80009be: 687b ldr r3, [r7, #4]
+ 80009c0: 691b ldr r3, [r3, #16]
+ 80009c2: 681b ldr r3, [r3, #0]
+ 80009c4: 641a str r2, [r3, #64] ; 0x40
+ }
+ 80009c6: e010 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
+ 80009c8: 687b ldr r3, [r7, #4]
+ 80009ca: 695b ldr r3, [r3, #20]
+ 80009cc: 2b10 cmp r3, #16
+ 80009ce: d106 bne.n 80009de <_ZN15MotorController9set_speedEi+0x21c>
+ 80009d0: 683b ldr r3, [r7, #0]
+ 80009d2: 425a negs r2, r3
+ 80009d4: 687b ldr r3, [r7, #4]
+ 80009d6: 691b ldr r3, [r3, #16]
+ 80009d8: 681b ldr r3, [r3, #0]
+ 80009da: 659a str r2, [r3, #88] ; 0x58
+ }
+ 80009dc: e005 b.n 80009ea <_ZN15MotorController9set_speedEi+0x228>
+ __HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, -duty_cycle);
+ 80009de: 683b ldr r3, [r7, #0]
+ 80009e0: 425a negs r2, r3
+ 80009e2: 687b ldr r3, [r7, #4]
+ 80009e4: 691b ldr r3, [r3, #16]
+ 80009e6: 681b ldr r3, [r3, #0]
+ 80009e8: 65da str r2, [r3, #92] ; 0x5c
}
- 80008dc: bf00 nop
- 80008de: 3708 adds r7, #8
- 80008e0: 46bd mov sp, r7
- 80008e2: bd80 pop {r7, pc}
+ 80009ea: bf00 nop
+ 80009ec: 3708 adds r7, #8
+ 80009ee: 46bd mov sp, r7
+ 80009f0: bd80 pop {r7, pc}
-080008e4 <_ZN15MotorController5brakeEv>:
+080009f2 <_ZN15MotorController5brakeEv>:
void brake() {
- 80008e4: b480 push {r7}
- 80008e6: b083 sub sp, #12
- 80008e8: af00 add r7, sp, #0
- 80008ea: 6078 str r0, [r7, #4]
+ 80009f2: b480 push {r7}
+ 80009f4: b083 sub sp, #12
+ 80009f6: af00 add r7, sp, #0
+ 80009f8: 6078 str r0, [r7, #4]
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- 80008ec: 687b ldr r3, [r7, #4]
- 80008ee: 695b ldr r3, [r3, #20]
- 80008f0: 2b00 cmp r3, #0
- 80008f2: d105 bne.n 8000900 <_ZN15MotorController5brakeEv+0x1c>
- 80008f4: 687b ldr r3, [r7, #4]
- 80008f6: 691b ldr r3, [r3, #16]
- 80008f8: 681b ldr r3, [r3, #0]
- 80008fa: 2200 movs r2, #0
- 80008fc: 635a str r2, [r3, #52] ; 0x34
- }
- 80008fe: e02c b.n 800095a <_ZN15MotorController5brakeEv+0x76>
+ 80009fa: 687b ldr r3, [r7, #4]
+ 80009fc: 695b ldr r3, [r3, #20]
+ 80009fe: 2b00 cmp r3, #0
+ 8000a00: d105 bne.n 8000a0e <_ZN15MotorController5brakeEv+0x1c>
+ 8000a02: 687b ldr r3, [r7, #4]
+ 8000a04: 691b ldr r3, [r3, #16]
+ 8000a06: 681b ldr r3, [r3, #0]
+ 8000a08: 2200 movs r2, #0
+ 8000a0a: 635a str r2, [r3, #52] ; 0x34
+ }
+ 8000a0c: e02c b.n 8000a68 <_ZN15MotorController5brakeEv+0x76>
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- 8000900: 687b ldr r3, [r7, #4]
- 8000902: 695b ldr r3, [r3, #20]
- 8000904: 2b04 cmp r3, #4
- 8000906: d105 bne.n 8000914 <_ZN15MotorController5brakeEv+0x30>
- 8000908: 687b ldr r3, [r7, #4]
- 800090a: 691b ldr r3, [r3, #16]
- 800090c: 681b ldr r3, [r3, #0]
- 800090e: 2200 movs r2, #0
- 8000910: 639a str r2, [r3, #56] ; 0x38
- }
- 8000912: e022 b.n 800095a <_ZN15MotorController5brakeEv+0x76>
+ 8000a0e: 687b ldr r3, [r7, #4]
+ 8000a10: 695b ldr r3, [r3, #20]
+ 8000a12: 2b04 cmp r3, #4
+ 8000a14: d105 bne.n 8000a22 <_ZN15MotorController5brakeEv+0x30>
+ 8000a16: 687b ldr r3, [r7, #4]
+ 8000a18: 691b ldr r3, [r3, #16]
+ 8000a1a: 681b ldr r3, [r3, #0]
+ 8000a1c: 2200 movs r2, #0
+ 8000a1e: 639a str r2, [r3, #56] ; 0x38
+ }
+ 8000a20: e022 b.n 8000a68 <_ZN15MotorController5brakeEv+0x76>
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- 8000914: 687b ldr r3, [r7, #4]
- 8000916: 695b ldr r3, [r3, #20]
- 8000918: 2b08 cmp r3, #8
- 800091a: d105 bne.n 8000928 <_ZN15MotorController5brakeEv+0x44>
- 800091c: 687b ldr r3, [r7, #4]
- 800091e: 691b ldr r3, [r3, #16]
- 8000920: 681b ldr r3, [r3, #0]
- 8000922: 2200 movs r2, #0
- 8000924: 63da str r2, [r3, #60] ; 0x3c
- }
- 8000926: e018 b.n 800095a <_ZN15MotorController5brakeEv+0x76>
+ 8000a22: 687b ldr r3, [r7, #4]
+ 8000a24: 695b ldr r3, [r3, #20]
+ 8000a26: 2b08 cmp r3, #8
+ 8000a28: d105 bne.n 8000a36 <_ZN15MotorController5brakeEv+0x44>
+ 8000a2a: 687b ldr r3, [r7, #4]
+ 8000a2c: 691b ldr r3, [r3, #16]
+ 8000a2e: 681b ldr r3, [r3, #0]
+ 8000a30: 2200 movs r2, #0
+ 8000a32: 63da str r2, [r3, #60] ; 0x3c
+ }
+ 8000a34: e018 b.n 8000a68 <_ZN15MotorController5brakeEv+0x76>
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- 8000928: 687b ldr r3, [r7, #4]
- 800092a: 695b ldr r3, [r3, #20]
- 800092c: 2b0c cmp r3, #12
- 800092e: d105 bne.n 800093c <_ZN15MotorController5brakeEv+0x58>
- 8000930: 687b ldr r3, [r7, #4]
- 8000932: 691b ldr r3, [r3, #16]
- 8000934: 681b ldr r3, [r3, #0]
- 8000936: 2200 movs r2, #0
- 8000938: 641a str r2, [r3, #64] ; 0x40
- }
- 800093a: e00e b.n 800095a <_ZN15MotorController5brakeEv+0x76>
+ 8000a36: 687b ldr r3, [r7, #4]
+ 8000a38: 695b ldr r3, [r3, #20]
+ 8000a3a: 2b0c cmp r3, #12
+ 8000a3c: d105 bne.n 8000a4a <_ZN15MotorController5brakeEv+0x58>
+ 8000a3e: 687b ldr r3, [r7, #4]
+ 8000a40: 691b ldr r3, [r3, #16]
+ 8000a42: 681b ldr r3, [r3, #0]
+ 8000a44: 2200 movs r2, #0
+ 8000a46: 641a str r2, [r3, #64] ; 0x40
+ }
+ 8000a48: e00e b.n 8000a68 <_ZN15MotorController5brakeEv+0x76>
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- 800093c: 687b ldr r3, [r7, #4]
- 800093e: 695b ldr r3, [r3, #20]
- 8000940: 2b10 cmp r3, #16
- 8000942: d105 bne.n 8000950 <_ZN15MotorController5brakeEv+0x6c>
- 8000944: 687b ldr r3, [r7, #4]
- 8000946: 691b ldr r3, [r3, #16]
- 8000948: 681b ldr r3, [r3, #0]
- 800094a: 2200 movs r2, #0
- 800094c: 659a str r2, [r3, #88] ; 0x58
- }
- 800094e: e004 b.n 800095a <_ZN15MotorController5brakeEv+0x76>
+ 8000a4a: 687b ldr r3, [r7, #4]
+ 8000a4c: 695b ldr r3, [r3, #20]
+ 8000a4e: 2b10 cmp r3, #16
+ 8000a50: d105 bne.n 8000a5e <_ZN15MotorController5brakeEv+0x6c>
+ 8000a52: 687b ldr r3, [r7, #4]
+ 8000a54: 691b ldr r3, [r3, #16]
+ 8000a56: 681b ldr r3, [r3, #0]
+ 8000a58: 2200 movs r2, #0
+ 8000a5a: 659a str r2, [r3, #88] ; 0x58
+ }
+ 8000a5c: e004 b.n 8000a68 <_ZN15MotorController5brakeEv+0x76>
__HAL_TIM_SET_COMPARE(pwm_timer_, pwm_channel_, 0);
- 8000950: 687b ldr r3, [r7, #4]
- 8000952: 691b ldr r3, [r3, #16]
- 8000954: 681b ldr r3, [r3, #0]
- 8000956: 2200 movs r2, #0
- 8000958: 65da str r2, [r3, #92] ; 0x5c
- }
- 800095a: bf00 nop
- 800095c: 370c adds r7, #12
- 800095e: 46bd mov sp, r7
- 8000960: f85d 7b04 ldr.w r7, [sp], #4
- 8000964: 4770 bx lr
-
-08000966 <_ZN3PidC1Efff>:
+ 8000a5e: 687b ldr r3, [r7, #4]
+ 8000a60: 691b ldr r3, [r3, #16]
+ 8000a62: 681b ldr r3, [r3, #0]
+ 8000a64: 2200 movs r2, #0
+ 8000a66: 65da str r2, [r3, #92] ; 0x5c
+ }
+ 8000a68: bf00 nop
+ 8000a6a: 370c adds r7, #12
+ 8000a6c: 46bd mov sp, r7
+ 8000a6e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000a72: 4770 bx lr
+
+08000a74 <_ZN3PidC1Efff>:
float previous_error_;
// int min_;
// int max_;
Pid(float kp, float ki, float kd) {
- 8000966: b480 push {r7}
- 8000968: b087 sub sp, #28
- 800096a: af00 add r7, sp, #0
- 800096c: 60f8 str r0, [r7, #12]
- 800096e: ed87 0a02 vstr s0, [r7, #8]
- 8000972: edc7 0a01 vstr s1, [r7, #4]
- 8000976: ed87 1a00 vstr s2, [r7]
+ 8000a74: b480 push {r7}
+ 8000a76: b087 sub sp, #28
+ 8000a78: af00 add r7, sp, #0
+ 8000a7a: 60f8 str r0, [r7, #12]
+ 8000a7c: ed87 0a02 vstr s0, [r7, #8]
+ 8000a80: edc7 0a01 vstr s1, [r7, #4]
+ 8000a84: ed87 1a00 vstr s2, [r7]
this->kp_ = kp;
- 800097a: 68fb ldr r3, [r7, #12]
- 800097c: 68ba ldr r2, [r7, #8]
- 800097e: 601a str r2, [r3, #0]
+ 8000a88: 68fb ldr r3, [r7, #12]
+ 8000a8a: 68ba ldr r2, [r7, #8]
+ 8000a8c: 601a str r2, [r3, #0]
this->ki_ = ki;
- 8000980: 68fb ldr r3, [r7, #12]
- 8000982: 687a ldr r2, [r7, #4]
- 8000984: 605a str r2, [r3, #4]
+ 8000a8e: 68fb ldr r3, [r7, #12]
+ 8000a90: 687a ldr r2, [r7, #4]
+ 8000a92: 605a str r2, [r3, #4]
this->kd_ = kd;
- 8000986: 68fb ldr r3, [r7, #12]
- 8000988: 683a ldr r2, [r7, #0]
- 800098a: 609a str r2, [r3, #8]
+ 8000a94: 68fb ldr r3, [r7, #12]
+ 8000a96: 683a ldr r2, [r7, #0]
+ 8000a98: 609a str r2, [r3, #8]
this->error_ = 0;
- 800098c: 68fb ldr r3, [r7, #12]
- 800098e: f04f 0200 mov.w r2, #0
- 8000992: 60da str r2, [r3, #12]
+ 8000a9a: 68fb ldr r3, [r7, #12]
+ 8000a9c: f04f 0200 mov.w r2, #0
+ 8000aa0: 60da str r2, [r3, #12]
this->setpoint_ = 0;
- 8000994: 68fb ldr r3, [r7, #12]
- 8000996: f04f 0200 mov.w r2, #0
- 800099a: 611a str r2, [r3, #16]
+ 8000aa2: 68fb ldr r3, [r7, #12]
+ 8000aa4: f04f 0200 mov.w r2, #0
+ 8000aa8: 611a str r2, [r3, #16]
this->previous_error_ = 0;
- 800099c: 68fb ldr r3, [r7, #12]
- 800099e: f04f 0200 mov.w r2, #0
- 80009a2: 641a str r2, [r3, #64] ; 0x40
+ 8000aaa: 68fb ldr r3, [r7, #12]
+ 8000aac: f04f 0200 mov.w r2, #0
+ 8000ab0: 641a str r2, [r3, #64] ; 0x40
this->error_sum_index_ = 0;
- 80009a4: 68fb ldr r3, [r7, #12]
- 80009a6: 2200 movs r2, #0
- 80009a8: 63da str r2, [r3, #60] ; 0x3c
+ 8000ab2: 68fb ldr r3, [r7, #12]
+ 8000ab4: 2200 movs r2, #0
+ 8000ab6: 63da str r2, [r3, #60] ; 0x3c
for (int i = 0; i < 10; i++) {
- 80009aa: 2300 movs r3, #0
- 80009ac: 617b str r3, [r7, #20]
- 80009ae: 697b ldr r3, [r7, #20]
- 80009b0: 2b09 cmp r3, #9
- 80009b2: dc0c bgt.n 80009ce <_ZN3PidC1Efff+0x68>
+ 8000ab8: 2300 movs r3, #0
+ 8000aba: 617b str r3, [r7, #20]
+ 8000abc: 697b ldr r3, [r7, #20]
+ 8000abe: 2b09 cmp r3, #9
+ 8000ac0: dc0c bgt.n 8000adc <_ZN3PidC1Efff+0x68>
this->error_sum_array_[i] = 0;
- 80009b4: 68fa ldr r2, [r7, #12]
- 80009b6: 697b ldr r3, [r7, #20]
- 80009b8: 3304 adds r3, #4
- 80009ba: 009b lsls r3, r3, #2
- 80009bc: 4413 add r3, r2
- 80009be: 3304 adds r3, #4
- 80009c0: f04f 0200 mov.w r2, #0
- 80009c4: 601a str r2, [r3, #0]
+ 8000ac2: 68fa ldr r2, [r7, #12]
+ 8000ac4: 697b ldr r3, [r7, #20]
+ 8000ac6: 3304 adds r3, #4
+ 8000ac8: 009b lsls r3, r3, #2
+ 8000aca: 4413 add r3, r2
+ 8000acc: 3304 adds r3, #4
+ 8000ace: f04f 0200 mov.w r2, #0
+ 8000ad2: 601a str r2, [r3, #0]
for (int i = 0; i < 10; i++) {
- 80009c6: 697b ldr r3, [r7, #20]
- 80009c8: 3301 adds r3, #1
- 80009ca: 617b str r3, [r7, #20]
- 80009cc: e7ef b.n 80009ae <_ZN3PidC1Efff+0x48>
+ 8000ad4: 697b ldr r3, [r7, #20]
+ 8000ad6: 3301 adds r3, #1
+ 8000ad8: 617b str r3, [r7, #20]
+ 8000ada: e7ef b.n 8000abc <_ZN3PidC1Efff+0x48>
}
}
- 80009ce: 68fb ldr r3, [r7, #12]
- 80009d0: 4618 mov r0, r3
- 80009d2: 371c adds r7, #28
- 80009d4: 46bd mov sp, r7
- 80009d6: f85d 7b04 ldr.w r7, [sp], #4
- 80009da: 4770 bx lr
-
-080009dc <_ZN3Pid3setEf>:
-
- void set(float setpoint) {
- 80009dc: b480 push {r7}
- 80009de: b083 sub sp, #12
- 80009e0: af00 add r7, sp, #0
- 80009e2: 6078 str r0, [r7, #4]
- 80009e4: ed87 0a00 vstr s0, [r7]
- this->setpoint_ = setpoint;
- 80009e8: 687b ldr r3, [r7, #4]
- 80009ea: 683a ldr r2, [r7, #0]
- 80009ec: 611a str r2, [r3, #16]
- }
- 80009ee: bf00 nop
- 80009f0: 370c adds r7, #12
- 80009f2: 46bd mov sp, r7
- 80009f4: f85d 7b04 ldr.w r7, [sp], #4
- 80009f8: 4770 bx lr
-
-080009fa <_ZN3Pid6updateEf>:
-
- int update(float measure) {
- 80009fa: b480 push {r7}
- 80009fc: b087 sub sp, #28
- 80009fe: af00 add r7, sp, #0
- 8000a00: 6078 str r0, [r7, #4]
- 8000a02: ed87 0a00 vstr s0, [r7]
-
- this->error_ = this->setpoint_ - measure;
- 8000a06: 687b ldr r3, [r7, #4]
- 8000a08: ed93 7a04 vldr s14, [r3, #16]
- 8000a0c: edd7 7a00 vldr s15, [r7]
- 8000a10: ee77 7a67 vsub.f32 s15, s14, s15
- 8000a14: 687b ldr r3, [r7, #4]
- 8000a16: edc3 7a03 vstr s15, [r3, #12]
-
- //proportional term
- float output = this->error_ * this->kp_;
- 8000a1a: 687b ldr r3, [r7, #4]
- 8000a1c: ed93 7a03 vldr s14, [r3, #12]
- 8000a20: 687b ldr r3, [r7, #4]
- 8000a22: edd3 7a00 vldr s15, [r3]
- 8000a26: ee67 7a27 vmul.f32 s15, s14, s15
- 8000a2a: edc7 7a03 vstr s15, [r7, #12]
-
- //integral term
- if (this->error_sum_index_ == 10) {
- 8000a2e: 687b ldr r3, [r7, #4]
- 8000a30: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8000a32: 2b0a cmp r3, #10
- 8000a34: d107 bne.n 8000a46 <_ZN3Pid6updateEf+0x4c>
- this->error_sum_array_[0] = this->error_;
- 8000a36: 687b ldr r3, [r7, #4]
- 8000a38: 68da ldr r2, [r3, #12]
- 8000a3a: 687b ldr r3, [r7, #4]
- 8000a3c: 615a str r2, [r3, #20]
- this->error_sum_index_ = 0;
- 8000a3e: 687b ldr r3, [r7, #4]
- 8000a40: 2200 movs r2, #0
- 8000a42: 63da str r2, [r3, #60] ; 0x3c
- 8000a44: e00e b.n 8000a64 <_ZN3Pid6updateEf+0x6a>
- } else {
- this->error_sum_array_[this->error_sum_index_] = this->error_;
- 8000a46: 687b ldr r3, [r7, #4]
- 8000a48: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8000a4a: 687a ldr r2, [r7, #4]
- 8000a4c: 68d2 ldr r2, [r2, #12]
- 8000a4e: 6879 ldr r1, [r7, #4]
- 8000a50: 3304 adds r3, #4
- 8000a52: 009b lsls r3, r3, #2
- 8000a54: 440b add r3, r1
- 8000a56: 3304 adds r3, #4
- 8000a58: 601a str r2, [r3, #0]
- this->error_sum_index_++;
- 8000a5a: 687b ldr r3, [r7, #4]
- 8000a5c: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8000a5e: 1c5a adds r2, r3, #1
- 8000a60: 687b ldr r3, [r7, #4]
- 8000a62: 63da str r2, [r3, #60] ; 0x3c
- }
-
- float error_sum = 0;
- 8000a64: f04f 0300 mov.w r3, #0
- 8000a68: 617b str r3, [r7, #20]
- for (int i = 0; i < 10; i++) {
- 8000a6a: 2300 movs r3, #0
- 8000a6c: 613b str r3, [r7, #16]
- 8000a6e: 693b ldr r3, [r7, #16]
- 8000a70: 2b09 cmp r3, #9
- 8000a72: dc11 bgt.n 8000a98 <_ZN3Pid6updateEf+0x9e>
- error_sum += this->error_sum_array_[i];
- 8000a74: 687a ldr r2, [r7, #4]
- 8000a76: 693b ldr r3, [r7, #16]
- 8000a78: 3304 adds r3, #4
- 8000a7a: 009b lsls r3, r3, #2
- 8000a7c: 4413 add r3, r2
- 8000a7e: 3304 adds r3, #4
- 8000a80: edd3 7a00 vldr s15, [r3]
- 8000a84: ed97 7a05 vldr s14, [r7, #20]
- 8000a88: ee77 7a27 vadd.f32 s15, s14, s15
- 8000a8c: edc7 7a05 vstr s15, [r7, #20]
- for (int i = 0; i < 10; i++) {
- 8000a90: 693b ldr r3, [r7, #16]
- 8000a92: 3301 adds r3, #1
- 8000a94: 613b str r3, [r7, #16]
- 8000a96: e7ea b.n 8000a6e <_ZN3Pid6updateEf+0x74>
- }
-
-
- output += error_sum * this->ki_;
- 8000a98: 687b ldr r3, [r7, #4]
- 8000a9a: ed93 7a01 vldr s14, [r3, #4]
- 8000a9e: edd7 7a05 vldr s15, [r7, #20]
- 8000aa2: ee67 7a27 vmul.f32 s15, s14, s15
- 8000aa6: ed97 7a03 vldr s14, [r7, #12]
- 8000aaa: ee77 7a27 vadd.f32 s15, s14, s15
- 8000aae: edc7 7a03 vstr s15, [r7, #12]
-
- //derivative term
- output += (this->error_ - this->previous_error_);
- 8000ab2: 687b ldr r3, [r7, #4]
- 8000ab4: ed93 7a03 vldr s14, [r3, #12]
- 8000ab8: 687b ldr r3, [r7, #4]
- 8000aba: edd3 7a10 vldr s15, [r3, #64] ; 0x40
- 8000abe: ee77 7a67 vsub.f32 s15, s14, s15
- 8000ac2: ed97 7a03 vldr s14, [r7, #12]
- 8000ac6: ee77 7a27 vadd.f32 s15, s14, s15
- 8000aca: edc7 7a03 vstr s15, [r7, #12]
- this->previous_error_ = this->error_;
- 8000ace: 687b ldr r3, [r7, #4]
- 8000ad0: 68da ldr r2, [r3, #12]
- 8000ad2: 687b ldr r3, [r7, #4]
- 8000ad4: 641a str r2, [r3, #64] ; 0x40
-
- int integer_output = (int) output;
- 8000ad6: edd7 7a03 vldr s15, [r7, #12]
- 8000ada: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8000ade: ee17 3a90 vmov r3, s15
- 8000ae2: 60bb str r3, [r7, #8]
-
- return integer_output;
- 8000ae4: 68bb ldr r3, [r7, #8]
-
- }
- 8000ae6: 4618 mov r0, r3
- 8000ae8: 371c adds r7, #28
- 8000aea: 46bd mov sp, r7
- 8000aec: f85d 7b04 ldr.w r7, [sp], #4
- 8000af0: 4770 bx lr
+ 8000adc: 68fb ldr r3, [r7, #12]
+ 8000ade: 4618 mov r0, r3
+ 8000ae0: 371c adds r7, #28
+ 8000ae2: 46bd mov sp, r7
+ 8000ae4: f85d 7b04 ldr.w r7, [sp], #4
+ 8000ae8: 4770 bx lr
...
-08000af4 <main>:
+08000aec <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void) {
- 8000af4: b580 push {r7, lr}
- 8000af6: af00 add r7, sp, #0
+ 8000aec: b580 push {r7, lr}
+ 8000aee: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
- 8000af8: f000 ff4f bl 800199a <HAL_Init>
+ 8000af0: f000 ff91 bl 8001a16 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
- 8000afc: f000 f838 bl 8000b70 <_Z18SystemClock_Configv>
+ 8000af4: f000 f848 bl 8000b88 <_Z18SystemClock_Configv>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
- 8000b00: f000 fb10 bl 8001124 <_ZL12MX_GPIO_Initv>
+ 8000af8: f000 fb20 bl 800113c <_ZL12MX_GPIO_Initv>
MX_TIM2_Init();
- 8000b04: f000 f8da bl 8000cbc <_ZL12MX_TIM2_Initv>
+ 8000afc: f000 f8ea bl 8000cd4 <_ZL12MX_TIM2_Initv>
MX_TIM3_Init();
- 8000b08: f000 f936 bl 8000d78 <_ZL12MX_TIM3_Initv>
+ 8000b00: f000 f946 bl 8000d90 <_ZL12MX_TIM3_Initv>
MX_TIM4_Init();
- 8000b0c: f000 f992 bl 8000e34 <_ZL12MX_TIM4_Initv>
+ 8000b04: f000 f9a2 bl 8000e4c <_ZL12MX_TIM4_Initv>
MX_TIM5_Init();
- 8000b10: f000 fa30 bl 8000f74 <_ZL12MX_TIM5_Initv>
+ 8000b08: f000 fa40 bl 8000f8c <_ZL12MX_TIM5_Initv>
MX_USART6_UART_Init();
- 8000b14: f000 fad0 bl 80010b8 <_ZL19MX_USART6_UART_Initv>
+ 8000b0c: f000 fae0 bl 80010d0 <_ZL19MX_USART6_UART_Initv>
MX_TIM6_Init();
- 8000b18: f000 fa8c bl 8001034 <_ZL12MX_TIM6_Initv>
+ 8000b10: f000 fa9c bl 800104c <_ZL12MX_TIM6_Initv>
/* Initialize interrupts */
MX_NVIC_Init();
- 8000b1c: f000 f8b2 bl 8000c84 <_ZL12MX_NVIC_Initv>
+ 8000b14: f000 f8c2 bl 8000c9c <_ZL12MX_NVIC_Initv>
/* USER CODE BEGIN 2 */
left_encoder.Setup();
- 8000b20: 480a ldr r0, [pc, #40] ; (8000b4c <main+0x58>)
- 8000b22: f7ff fd4f bl 80005c4 <_ZN7Encoder5SetupEv>
+ 8000b18: 480e ldr r0, [pc, #56] ; (8000b54 <main+0x68>)
+ 8000b1a: f7ff fd53 bl 80005c4 <_ZN7Encoder5SetupEv>
right_encoder.Setup();
- 8000b26: 480a ldr r0, [pc, #40] ; (8000b50 <main+0x5c>)
- 8000b28: f7ff fd4c bl 80005c4 <_ZN7Encoder5SetupEv>
+ 8000b1e: 480e ldr r0, [pc, #56] ; (8000b58 <main+0x6c>)
+ 8000b20: f7ff fd50 bl 80005c4 <_ZN7Encoder5SetupEv>
left_motor.setup();
- 8000b2c: 4809 ldr r0, [pc, #36] ; (8000b54 <main+0x60>)
- 8000b2e: f7ff fe38 bl 80007a2 <_ZN15MotorController5setupEv>
+ 8000b24: 480d ldr r0, [pc, #52] ; (8000b5c <main+0x70>)
+ 8000b26: f7ff fe3c bl 80007a2 <_ZN15MotorController5setupEv>
right_motor.setup();
- 8000b32: 4809 ldr r0, [pc, #36] ; (8000b58 <main+0x64>)
- 8000b34: f7ff fe35 bl 80007a2 <_ZN15MotorController5setupEv>
+ 8000b2a: 480d ldr r0, [pc, #52] ; (8000b60 <main+0x74>)
+ 8000b2c: f7ff fe39 bl 80007a2 <_ZN15MotorController5setupEv>
tx_buffer = (uint8_t*) &odom_msg;
- 8000b38: 4b08 ldr r3, [pc, #32] ; (8000b5c <main+0x68>)
- 8000b3a: 4a09 ldr r2, [pc, #36] ; (8000b60 <main+0x6c>)
- 8000b3c: 601a str r2, [r3, #0]
+ 8000b30: 4b0c ldr r3, [pc, #48] ; (8000b64 <main+0x78>)
+ 8000b32: 4a0d ldr r2, [pc, #52] ; (8000b68 <main+0x7c>)
+ 8000b34: 601a str r2, [r3, #0]
rx_buffer = (uint8_t*) &vel_msg;
- 8000b3e: 4b09 ldr r3, [pc, #36] ; (8000b64 <main+0x70>)
- 8000b40: 4a09 ldr r2, [pc, #36] ; (8000b68 <main+0x74>)
- 8000b42: 601a str r2, [r3, #0]
+ 8000b36: 4b0d ldr r3, [pc, #52] ; (8000b6c <main+0x80>)
+ 8000b38: 4a0d ldr r2, [pc, #52] ; (8000b70 <main+0x84>)
+ 8000b3a: 601a str r2, [r3, #0]
- //Enables TIM3 interrupt (used for PID control)
-// HAL_TIM_Base_Start_IT(&htim3);
+ address = &left_dutycycle;
+ 8000b3c: 4b0d ldr r3, [pc, #52] ; (8000b74 <main+0x88>)
+ 8000b3e: 4a0e ldr r2, [pc, #56] ; (8000b78 <main+0x8c>)
+ 8000b40: 601a str r2, [r3, #0]
+
+ //Enables UART RX interrupt
+// HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
- //Enables TIM6 interrupt (used for periodic transmission)
- HAL_TIM_Base_Start_IT(&htim6);
- 8000b44: 4809 ldr r0, [pc, #36] ; (8000b6c <main+0x78>)
- 8000b46: f002 fb27 bl 8003198 <HAL_TIM_Base_Start_IT>
+ //test plot stuff
+ HAL_UART_Receive_IT(&huart6, (uint8_t*) &rx_test, 4);
+ 8000b42: 2204 movs r2, #4
+ 8000b44: 490d ldr r1, [pc, #52] ; (8000b7c <main+0x90>)
+ 8000b46: 480e ldr r0, [pc, #56] ; (8000b80 <main+0x94>)
+ 8000b48: f003 fd02 bl 8004550 <HAL_UART_Receive_IT>
+
+ //Enables TIM3 interrupt (used for PID control)
+ HAL_TIM_Base_Start_IT(&htim3);
+ 8000b4c: 480d ldr r0, [pc, #52] ; (8000b84 <main+0x98>)
+ 8000b4e: f002 fb61 bl 8003214 <HAL_TIM_Base_Start_IT>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
- 8000b4a: e7fe b.n 8000b4a <main+0x56>
- 8000b4c: 200001ec .word 0x200001ec
- 8000b50: 20000208 .word 0x20000208
- 8000b54: 20000344 .word 0x20000344
- 8000b58: 2000035c .word 0x2000035c
- 8000b5c: 20000374 .word 0x20000374
- 8000b60: 2000037c .word 0x2000037c
- 8000b64: 20000378 .word 0x20000378
- 8000b68: 20000388 .word 0x20000388
- 8000b6c: 2000012c .word 0x2000012c
-
-08000b70 <_Z18SystemClock_Configv>:
+ 8000b52: e7fe b.n 8000b52 <main+0x66>
+ 8000b54: 200001f0 .word 0x200001f0
+ 8000b58: 2000020c .word 0x2000020c
+ 8000b5c: 2000034c .word 0x2000034c
+ 8000b60: 20000364 .word 0x20000364
+ 8000b64: 2000037c .word 0x2000037c
+ 8000b68: 20000384 .word 0x20000384
+ 8000b6c: 20000380 .word 0x20000380
+ 8000b70: 20000390 .word 0x20000390
+ 8000b74: 20000348 .word 0x20000348
+ 8000b78: 20000344 .word 0x20000344
+ 8000b7c: 20000398 .word 0x20000398
+ 8000b80: 20000170 .word 0x20000170
+ 8000b84: 20000070 .word 0x20000070
+
+08000b88 <_Z18SystemClock_Configv>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void) {
- 8000b70: b580 push {r7, lr}
- 8000b72: b0b8 sub sp, #224 ; 0xe0
- 8000b74: af00 add r7, sp, #0
+ 8000b88: b580 push {r7, lr}
+ 8000b8a: b0b8 sub sp, #224 ; 0xe0
+ 8000b8c: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
- 8000b76: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000b7a: 2234 movs r2, #52 ; 0x34
- 8000b7c: 2100 movs r1, #0
- 8000b7e: 4618 mov r0, r3
- 8000b80: f004 fa08 bl 8004f94 <memset>
+ 8000b8e: f107 03ac add.w r3, r7, #172 ; 0xac
+ 8000b92: 2234 movs r2, #52 ; 0x34
+ 8000b94: 2100 movs r1, #0
+ 8000b96: 4618 mov r0, r3
+ 8000b98: f004 fb82 bl 80052a0 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
- 8000b84: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000b88: 2200 movs r2, #0
- 8000b8a: 601a str r2, [r3, #0]
- 8000b8c: 605a str r2, [r3, #4]
- 8000b8e: 609a str r2, [r3, #8]
- 8000b90: 60da str r2, [r3, #12]
- 8000b92: 611a str r2, [r3, #16]
+ 8000b9c: f107 0398 add.w r3, r7, #152 ; 0x98
+ 8000ba0: 2200 movs r2, #0
+ 8000ba2: 601a str r2, [r3, #0]
+ 8000ba4: 605a str r2, [r3, #4]
+ 8000ba6: 609a str r2, [r3, #8]
+ 8000ba8: 60da str r2, [r3, #12]
+ 8000baa: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
- 8000b94: f107 0308 add.w r3, r7, #8
- 8000b98: 2290 movs r2, #144 ; 0x90
- 8000b9a: 2100 movs r1, #0
- 8000b9c: 4618 mov r0, r3
- 8000b9e: f004 f9f9 bl 8004f94 <memset>
+ 8000bac: f107 0308 add.w r3, r7, #8
+ 8000bb0: 2290 movs r2, #144 ; 0x90
+ 8000bb2: 2100 movs r1, #0
+ 8000bb4: 4618 mov r0, r3
+ 8000bb6: f004 fb73 bl 80052a0 <memset>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
- 8000ba2: 4b36 ldr r3, [pc, #216] ; (8000c7c <_Z18SystemClock_Configv+0x10c>)
- 8000ba4: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000ba6: 4a35 ldr r2, [pc, #212] ; (8000c7c <_Z18SystemClock_Configv+0x10c>)
- 8000ba8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8000bac: 6413 str r3, [r2, #64] ; 0x40
- 8000bae: 4b33 ldr r3, [pc, #204] ; (8000c7c <_Z18SystemClock_Configv+0x10c>)
- 8000bb0: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000bb2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000bb6: 607b str r3, [r7, #4]
- 8000bb8: 687b ldr r3, [r7, #4]
+ 8000bba: 4b36 ldr r3, [pc, #216] ; (8000c94 <_Z18SystemClock_Configv+0x10c>)
+ 8000bbc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000bbe: 4a35 ldr r2, [pc, #212] ; (8000c94 <_Z18SystemClock_Configv+0x10c>)
+ 8000bc0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000bc4: 6413 str r3, [r2, #64] ; 0x40
+ 8000bc6: 4b33 ldr r3, [pc, #204] ; (8000c94 <_Z18SystemClock_Configv+0x10c>)
+ 8000bc8: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000bca: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000bce: 607b str r3, [r7, #4]
+ 8000bd0: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 8000bba: 4b31 ldr r3, [pc, #196] ; (8000c80 <_Z18SystemClock_Configv+0x110>)
- 8000bbc: 681b ldr r3, [r3, #0]
- 8000bbe: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 8000bc2: 4a2f ldr r2, [pc, #188] ; (8000c80 <_Z18SystemClock_Configv+0x110>)
- 8000bc4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000bc8: 6013 str r3, [r2, #0]
- 8000bca: 4b2d ldr r3, [pc, #180] ; (8000c80 <_Z18SystemClock_Configv+0x110>)
- 8000bcc: 681b ldr r3, [r3, #0]
- 8000bce: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8000bd2: 603b str r3, [r7, #0]
- 8000bd4: 683b ldr r3, [r7, #0]
+ 8000bd2: 4b31 ldr r3, [pc, #196] ; (8000c98 <_Z18SystemClock_Configv+0x110>)
+ 8000bd4: 681b ldr r3, [r3, #0]
+ 8000bd6: f423 4340 bic.w r3, r3, #49152 ; 0xc000
+ 8000bda: 4a2f ldr r2, [pc, #188] ; (8000c98 <_Z18SystemClock_Configv+0x110>)
+ 8000bdc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000be0: 6013 str r3, [r2, #0]
+ 8000be2: 4b2d ldr r3, [pc, #180] ; (8000c98 <_Z18SystemClock_Configv+0x110>)
+ 8000be4: 681b ldr r3, [r3, #0]
+ 8000be6: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 8000bea: 603b str r3, [r7, #0]
+ 8000bec: 683b ldr r3, [r7, #0]
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8000bd6: 2302 movs r3, #2
- 8000bd8: f8c7 30ac str.w r3, [r7, #172] ; 0xac
+ 8000bee: 2302 movs r3, #2
+ 8000bf0: f8c7 30ac str.w r3, [r7, #172] ; 0xac
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000bdc: 2301 movs r3, #1
- 8000bde: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
+ 8000bf4: 2301 movs r3, #1
+ 8000bf6: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000be2: 2310 movs r3, #16
- 8000be4: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
+ 8000bfa: 2310 movs r3, #16
+ 8000bfc: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8000be8: 2300 movs r3, #0
- 8000bea: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
+ 8000c00: 2300 movs r3, #0
+ 8000c02: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- 8000bee: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000bf2: 4618 mov r0, r3
- 8000bf4: f001 fa3e bl 8002074 <HAL_RCC_OscConfig>
- 8000bf8: 4603 mov r3, r0
- 8000bfa: 2b00 cmp r3, #0
- 8000bfc: bf14 ite ne
- 8000bfe: 2301 movne r3, #1
- 8000c00: 2300 moveq r3, #0
- 8000c02: b2db uxtb r3, r3
- 8000c04: 2b00 cmp r3, #0
- 8000c06: d001 beq.n 8000c0c <_Z18SystemClock_Configv+0x9c>
+ 8000c06: f107 03ac add.w r3, r7, #172 ; 0xac
+ 8000c0a: 4618 mov r0, r3
+ 8000c0c: f001 fa70 bl 80020f0 <HAL_RCC_OscConfig>
+ 8000c10: 4603 mov r3, r0
+ 8000c12: 2b00 cmp r3, #0
+ 8000c14: bf14 ite ne
+ 8000c16: 2301 movne r3, #1
+ 8000c18: 2300 moveq r3, #0
+ 8000c1a: b2db uxtb r3, r3
+ 8000c1c: 2b00 cmp r3, #0
+ 8000c1e: d001 beq.n 8000c24 <_Z18SystemClock_Configv+0x9c>
Error_Handler();
- 8000c08: f000 fc04 bl 8001414 <Error_Handler>
+ 8000c20: f000 fc36 bl 8001490 <Error_Handler>
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
- 8000c0c: 230f movs r3, #15
- 8000c0e: f8c7 3098 str.w r3, [r7, #152] ; 0x98
+ 8000c24: 230f movs r3, #15
+ 8000c26: f8c7 3098 str.w r3, [r7, #152] ; 0x98
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 8000c12: 2300 movs r3, #0
- 8000c14: f8c7 309c str.w r3, [r7, #156] ; 0x9c
+ 8000c2a: 2300 movs r3, #0
+ 8000c2c: f8c7 309c str.w r3, [r7, #156] ; 0x9c
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000c18: 2300 movs r3, #0
- 8000c1a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
+ 8000c30: 2300 movs r3, #0
+ 8000c32: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8000c1e: 2300 movs r3, #0
- 8000c20: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
+ 8000c36: 2300 movs r3, #0
+ 8000c38: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8000c24: 2300 movs r3, #0
- 8000c26: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
+ 8000c3c: 2300 movs r3, #0
+ 8000c3e: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
- 8000c2a: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000c2e: 2100 movs r1, #0
- 8000c30: 4618 mov r0, r3
- 8000c32: f001 fc91 bl 8002558 <HAL_RCC_ClockConfig>
- 8000c36: 4603 mov r3, r0
- 8000c38: 2b00 cmp r3, #0
- 8000c3a: bf14 ite ne
- 8000c3c: 2301 movne r3, #1
- 8000c3e: 2300 moveq r3, #0
- 8000c40: b2db uxtb r3, r3
- 8000c42: 2b00 cmp r3, #0
- 8000c44: d001 beq.n 8000c4a <_Z18SystemClock_Configv+0xda>
+ 8000c42: f107 0398 add.w r3, r7, #152 ; 0x98
+ 8000c46: 2100 movs r1, #0
+ 8000c48: 4618 mov r0, r3
+ 8000c4a: f001 fcc3 bl 80025d4 <HAL_RCC_ClockConfig>
+ 8000c4e: 4603 mov r3, r0
+ 8000c50: 2b00 cmp r3, #0
+ 8000c52: bf14 ite ne
+ 8000c54: 2301 movne r3, #1
+ 8000c56: 2300 moveq r3, #0
+ 8000c58: b2db uxtb r3, r3
+ 8000c5a: 2b00 cmp r3, #0
+ 8000c5c: d001 beq.n 8000c62 <_Z18SystemClock_Configv+0xda>
Error_Handler();
- 8000c46: f000 fbe5 bl 8001414 <Error_Handler>
+ 8000c5e: f000 fc17 bl 8001490 <Error_Handler>
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
- 8000c4a: f44f 6300 mov.w r3, #2048 ; 0x800
- 8000c4e: 60bb str r3, [r7, #8]
+ 8000c62: f44f 6300 mov.w r3, #2048 ; 0x800
+ 8000c66: 60bb str r3, [r7, #8]
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
- 8000c50: 2300 movs r3, #0
- 8000c52: 663b str r3, [r7, #96] ; 0x60
+ 8000c68: 2300 movs r3, #0
+ 8000c6a: 663b str r3, [r7, #96] ; 0x60
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
- 8000c54: f107 0308 add.w r3, r7, #8
- 8000c58: 4618 mov r0, r3
- 8000c5a: f001 fe4b bl 80028f4 <HAL_RCCEx_PeriphCLKConfig>
- 8000c5e: 4603 mov r3, r0
- 8000c60: 2b00 cmp r3, #0
- 8000c62: bf14 ite ne
- 8000c64: 2301 movne r3, #1
- 8000c66: 2300 moveq r3, #0
- 8000c68: b2db uxtb r3, r3
- 8000c6a: 2b00 cmp r3, #0
- 8000c6c: d001 beq.n 8000c72 <_Z18SystemClock_Configv+0x102>
+ 8000c6c: f107 0308 add.w r3, r7, #8
+ 8000c70: 4618 mov r0, r3
+ 8000c72: f001 fe7d bl 8002970 <HAL_RCCEx_PeriphCLKConfig>
+ 8000c76: 4603 mov r3, r0
+ 8000c78: 2b00 cmp r3, #0
+ 8000c7a: bf14 ite ne
+ 8000c7c: 2301 movne r3, #1
+ 8000c7e: 2300 moveq r3, #0
+ 8000c80: b2db uxtb r3, r3
+ 8000c82: 2b00 cmp r3, #0
+ 8000c84: d001 beq.n 8000c8a <_Z18SystemClock_Configv+0x102>
Error_Handler();
- 8000c6e: f000 fbd1 bl 8001414 <Error_Handler>
+ 8000c86: f000 fc03 bl 8001490 <Error_Handler>
}
}
- 8000c72: bf00 nop
- 8000c74: 37e0 adds r7, #224 ; 0xe0
- 8000c76: 46bd mov sp, r7
- 8000c78: bd80 pop {r7, pc}
- 8000c7a: bf00 nop
- 8000c7c: 40023800 .word 0x40023800
- 8000c80: 40007000 .word 0x40007000
+ 8000c8a: bf00 nop
+ 8000c8c: 37e0 adds r7, #224 ; 0xe0
+ 8000c8e: 46bd mov sp, r7
+ 8000c90: bd80 pop {r7, pc}
+ 8000c92: bf00 nop
+ 8000c94: 40023800 .word 0x40023800
+ 8000c98: 40007000 .word 0x40007000
-08000c84 <_ZL12MX_NVIC_Initv>:
+08000c9c <_ZL12MX_NVIC_Initv>:
/**
* @brief NVIC Configuration.
* @retval None
*/
static void MX_NVIC_Init(void) {
- 8000c84: b580 push {r7, lr}
- 8000c86: af00 add r7, sp, #0
+ 8000c9c: b580 push {r7, lr}
+ 8000c9e: af00 add r7, sp, #0
/* TIM3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(TIM3_IRQn, 2, 1);
- 8000c88: 2201 movs r2, #1
- 8000c8a: 2102 movs r1, #2
- 8000c8c: 201d movs r0, #29
- 8000c8e: f000 ffbc bl 8001c0a <HAL_NVIC_SetPriority>
+ 8000ca0: 2201 movs r2, #1
+ 8000ca2: 2102 movs r1, #2
+ 8000ca4: 201d movs r0, #29
+ 8000ca6: f000 ffee bl 8001c86 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM3_IRQn);
- 8000c92: 201d movs r0, #29
- 8000c94: f000 ffd5 bl 8001c42 <HAL_NVIC_EnableIRQ>
+ 8000caa: 201d movs r0, #29
+ 8000cac: f001 f807 bl 8001cbe <HAL_NVIC_EnableIRQ>
/* TIM6_DAC_IRQn interrupt configuration */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 2, 2);
- 8000c98: 2202 movs r2, #2
- 8000c9a: 2102 movs r1, #2
- 8000c9c: 2036 movs r0, #54 ; 0x36
- 8000c9e: f000 ffb4 bl 8001c0a <HAL_NVIC_SetPriority>
+ 8000cb0: 2202 movs r2, #2
+ 8000cb2: 2102 movs r1, #2
+ 8000cb4: 2036 movs r0, #54 ; 0x36
+ 8000cb6: f000 ffe6 bl 8001c86 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
- 8000ca2: 2036 movs r0, #54 ; 0x36
- 8000ca4: f000 ffcd bl 8001c42 <HAL_NVIC_EnableIRQ>
+ 8000cba: 2036 movs r0, #54 ; 0x36
+ 8000cbc: f000 ffff bl 8001cbe <HAL_NVIC_EnableIRQ>
/* USART6_IRQn interrupt configuration */
HAL_NVIC_SetPriority(USART6_IRQn, 2, 0);
- 8000ca8: 2200 movs r2, #0
- 8000caa: 2102 movs r1, #2
- 8000cac: 2047 movs r0, #71 ; 0x47
- 8000cae: f000 ffac bl 8001c0a <HAL_NVIC_SetPriority>
+ 8000cc0: 2200 movs r2, #0
+ 8000cc2: 2102 movs r1, #2
+ 8000cc4: 2047 movs r0, #71 ; 0x47
+ 8000cc6: f000 ffde bl 8001c86 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART6_IRQn);
- 8000cb2: 2047 movs r0, #71 ; 0x47
- 8000cb4: f000 ffc5 bl 8001c42 <HAL_NVIC_EnableIRQ>
+ 8000cca: 2047 movs r0, #71 ; 0x47
+ 8000ccc: f000 fff7 bl 8001cbe <HAL_NVIC_EnableIRQ>
}
- 8000cb8: bf00 nop
- 8000cba: bd80 pop {r7, pc}
+ 8000cd0: bf00 nop
+ 8000cd2: bd80 pop {r7, pc}
-08000cbc <_ZL12MX_TIM2_Initv>:
+08000cd4 <_ZL12MX_TIM2_Initv>:
/**
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void) {
- 8000cbc: b580 push {r7, lr}
- 8000cbe: b08c sub sp, #48 ; 0x30
- 8000cc0: af00 add r7, sp, #0
+ 8000cd4: b580 push {r7, lr}
+ 8000cd6: b08c sub sp, #48 ; 0x30
+ 8000cd8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_Encoder_InitTypeDef sConfig = { 0 };
- 8000cc2: f107 030c add.w r3, r7, #12
- 8000cc6: 2224 movs r2, #36 ; 0x24
- 8000cc8: 2100 movs r1, #0
- 8000cca: 4618 mov r0, r3
- 8000ccc: f004 f962 bl 8004f94 <memset>
+ 8000cda: f107 030c add.w r3, r7, #12
+ 8000cde: 2224 movs r2, #36 ; 0x24
+ 8000ce0: 2100 movs r1, #0
+ 8000ce2: 4618 mov r0, r3
+ 8000ce4: f004 fadc bl 80052a0 <memset>
TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000cd0: 463b mov r3, r7
- 8000cd2: 2200 movs r2, #0
- 8000cd4: 601a str r2, [r3, #0]
- 8000cd6: 605a str r2, [r3, #4]
- 8000cd8: 609a str r2, [r3, #8]
+ 8000ce8: 463b mov r3, r7
+ 8000cea: 2200 movs r2, #0
+ 8000cec: 601a str r2, [r3, #0]
+ 8000cee: 605a str r2, [r3, #4]
+ 8000cf0: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
- 8000cda: 4b26 ldr r3, [pc, #152] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000cdc: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
- 8000ce0: 601a str r2, [r3, #0]
+ 8000cf2: 4b26 ldr r3, [pc, #152] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000cf4: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
+ 8000cf8: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
- 8000ce2: 4b24 ldr r3, [pc, #144] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000ce4: 2200 movs r2, #0
- 8000ce6: 605a str r2, [r3, #4]
+ 8000cfa: 4b24 ldr r3, [pc, #144] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000cfc: 2200 movs r2, #0
+ 8000cfe: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000ce8: 4b22 ldr r3, [pc, #136] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000cea: 2200 movs r2, #0
- 8000cec: 609a str r2, [r3, #8]
+ 8000d00: 4b22 ldr r3, [pc, #136] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000d02: 2200 movs r2, #0
+ 8000d04: 609a str r2, [r3, #8]
htim2.Init.Period = 4294967295;
- 8000cee: 4b21 ldr r3, [pc, #132] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000cf0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000cf4: 60da str r2, [r3, #12]
+ 8000d06: 4b21 ldr r3, [pc, #132] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000d08: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 8000d0c: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000cf6: 4b1f ldr r3, [pc, #124] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000cf8: 2200 movs r2, #0
- 8000cfa: 611a str r2, [r3, #16]
+ 8000d0e: 4b1f ldr r3, [pc, #124] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000d10: 2200 movs r2, #0
+ 8000d12: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000cfc: 4b1d ldr r3, [pc, #116] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000cfe: 2200 movs r2, #0
- 8000d00: 619a str r2, [r3, #24]
+ 8000d14: 4b1d ldr r3, [pc, #116] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000d16: 2200 movs r2, #0
+ 8000d18: 619a str r2, [r3, #24]
sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8000d02: 2303 movs r3, #3
- 8000d04: 60fb str r3, [r7, #12]
+ 8000d1a: 2303 movs r3, #3
+ 8000d1c: 60fb str r3, [r7, #12]
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8000d06: 2300 movs r3, #0
- 8000d08: 613b str r3, [r7, #16]
+ 8000d1e: 2300 movs r3, #0
+ 8000d20: 613b str r3, [r7, #16]
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8000d0a: 2301 movs r3, #1
- 8000d0c: 617b str r3, [r7, #20]
+ 8000d22: 2301 movs r3, #1
+ 8000d24: 617b str r3, [r7, #20]
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8000d0e: 2300 movs r3, #0
- 8000d10: 61bb str r3, [r7, #24]
+ 8000d26: 2300 movs r3, #0
+ 8000d28: 61bb str r3, [r7, #24]
sConfig.IC1Filter = 0;
- 8000d12: 2300 movs r3, #0
- 8000d14: 61fb str r3, [r7, #28]
+ 8000d2a: 2300 movs r3, #0
+ 8000d2c: 61fb str r3, [r7, #28]
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8000d16: 2300 movs r3, #0
- 8000d18: 623b str r3, [r7, #32]
+ 8000d2e: 2300 movs r3, #0
+ 8000d30: 623b str r3, [r7, #32]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8000d1a: 2301 movs r3, #1
- 8000d1c: 627b str r3, [r7, #36] ; 0x24
+ 8000d32: 2301 movs r3, #1
+ 8000d34: 627b str r3, [r7, #36] ; 0x24
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8000d1e: 2300 movs r3, #0
- 8000d20: 62bb str r3, [r7, #40] ; 0x28
+ 8000d36: 2300 movs r3, #0
+ 8000d38: 62bb str r3, [r7, #40] ; 0x28
sConfig.IC2Filter = 0;
- 8000d22: 2300 movs r3, #0
- 8000d24: 62fb str r3, [r7, #44] ; 0x2c
+ 8000d3a: 2300 movs r3, #0
+ 8000d3c: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK) {
- 8000d26: f107 030c add.w r3, r7, #12
- 8000d2a: 4619 mov r1, r3
- 8000d2c: 4811 ldr r0, [pc, #68] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000d2e: f002 fad7 bl 80032e0 <HAL_TIM_Encoder_Init>
- 8000d32: 4603 mov r3, r0
- 8000d34: 2b00 cmp r3, #0
- 8000d36: bf14 ite ne
- 8000d38: 2301 movne r3, #1
- 8000d3a: 2300 moveq r3, #0
- 8000d3c: b2db uxtb r3, r3
- 8000d3e: 2b00 cmp r3, #0
- 8000d40: d001 beq.n 8000d46 <_ZL12MX_TIM2_Initv+0x8a>
+ 8000d3e: f107 030c add.w r3, r7, #12
+ 8000d42: 4619 mov r1, r3
+ 8000d44: 4811 ldr r0, [pc, #68] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000d46: f002 fb09 bl 800335c <HAL_TIM_Encoder_Init>
+ 8000d4a: 4603 mov r3, r0
+ 8000d4c: 2b00 cmp r3, #0
+ 8000d4e: bf14 ite ne
+ 8000d50: 2301 movne r3, #1
+ 8000d52: 2300 moveq r3, #0
+ 8000d54: b2db uxtb r3, r3
+ 8000d56: 2b00 cmp r3, #0
+ 8000d58: d001 beq.n 8000d5e <_ZL12MX_TIM2_Initv+0x8a>
Error_Handler();
- 8000d42: f000 fb67 bl 8001414 <Error_Handler>
+ 8000d5a: f000 fb99 bl 8001490 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000d46: 2300 movs r3, #0
- 8000d48: 603b str r3, [r7, #0]
+ 8000d5e: 2300 movs r3, #0
+ 8000d60: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000d4a: 2300 movs r3, #0
- 8000d4c: 60bb str r3, [r7, #8]
+ 8000d62: 2300 movs r3, #0
+ 8000d64: 60bb str r3, [r7, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) {
- 8000d4e: 463b mov r3, r7
- 8000d50: 4619 mov r1, r3
- 8000d52: 4808 ldr r0, [pc, #32] ; (8000d74 <_ZL12MX_TIM2_Initv+0xb8>)
- 8000d54: f003 fa64 bl 8004220 <HAL_TIMEx_MasterConfigSynchronization>
- 8000d58: 4603 mov r3, r0
- 8000d5a: 2b00 cmp r3, #0
- 8000d5c: bf14 ite ne
- 8000d5e: 2301 movne r3, #1
- 8000d60: 2300 moveq r3, #0
- 8000d62: b2db uxtb r3, r3
- 8000d64: 2b00 cmp r3, #0
- 8000d66: d001 beq.n 8000d6c <_ZL12MX_TIM2_Initv+0xb0>
+ 8000d66: 463b mov r3, r7
+ 8000d68: 4619 mov r1, r3
+ 8000d6a: 4808 ldr r0, [pc, #32] ; (8000d8c <_ZL12MX_TIM2_Initv+0xb8>)
+ 8000d6c: f003 fa96 bl 800429c <HAL_TIMEx_MasterConfigSynchronization>
+ 8000d70: 4603 mov r3, r0
+ 8000d72: 2b00 cmp r3, #0
+ 8000d74: bf14 ite ne
+ 8000d76: 2301 movne r3, #1
+ 8000d78: 2300 moveq r3, #0
+ 8000d7a: b2db uxtb r3, r3
+ 8000d7c: 2b00 cmp r3, #0
+ 8000d7e: d001 beq.n 8000d84 <_ZL12MX_TIM2_Initv+0xb0>
Error_Handler();
- 8000d68: f000 fb54 bl 8001414 <Error_Handler>
+ 8000d80: f000 fb86 bl 8001490 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
- 8000d6c: bf00 nop
- 8000d6e: 3730 adds r7, #48 ; 0x30
- 8000d70: 46bd mov sp, r7
- 8000d72: bd80 pop {r7, pc}
- 8000d74: 2000002c .word 0x2000002c
+ 8000d84: bf00 nop
+ 8000d86: 3730 adds r7, #48 ; 0x30
+ 8000d88: 46bd mov sp, r7
+ 8000d8a: bd80 pop {r7, pc}
+ 8000d8c: 20000030 .word 0x20000030
-08000d78 <_ZL12MX_TIM3_Initv>:
+08000d90 <_ZL12MX_TIM3_Initv>:
/**
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void) {
- 8000d78: b580 push {r7, lr}
- 8000d7a: b088 sub sp, #32
- 8000d7c: af00 add r7, sp, #0
+ 8000d90: b580 push {r7, lr}
+ 8000d92: b088 sub sp, #32
+ 8000d94: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };
- 8000d7e: f107 0310 add.w r3, r7, #16
- 8000d82: 2200 movs r2, #0
- 8000d84: 601a str r2, [r3, #0]
- 8000d86: 605a str r2, [r3, #4]
- 8000d88: 609a str r2, [r3, #8]
- 8000d8a: 60da str r2, [r3, #12]
+ 8000d96: f107 0310 add.w r3, r7, #16
+ 8000d9a: 2200 movs r2, #0
+ 8000d9c: 601a str r2, [r3, #0]
+ 8000d9e: 605a str r2, [r3, #4]
+ 8000da0: 609a str r2, [r3, #8]
+ 8000da2: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000d8c: 1d3b adds r3, r7, #4
- 8000d8e: 2200 movs r2, #0
- 8000d90: 601a str r2, [r3, #0]
- 8000d92: 605a str r2, [r3, #4]
- 8000d94: 609a str r2, [r3, #8]
+ 8000da4: 1d3b adds r3, r7, #4
+ 8000da6: 2200 movs r2, #0
+ 8000da8: 601a str r2, [r3, #0]
+ 8000daa: 605a str r2, [r3, #4]
+ 8000dac: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
- 8000d96: 4b25 ldr r3, [pc, #148] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000d98: 4a25 ldr r2, [pc, #148] ; (8000e30 <_ZL12MX_TIM3_Initv+0xb8>)
- 8000d9a: 601a str r2, [r3, #0]
- htim3.Init.Prescaler = 9999;
- 8000d9c: 4b23 ldr r3, [pc, #140] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000d9e: f242 720f movw r2, #9999 ; 0x270f
- 8000da2: 605a str r2, [r3, #4]
+ 8000dae: 4b25 ldr r3, [pc, #148] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000db0: 4a25 ldr r2, [pc, #148] ; (8000e48 <_ZL12MX_TIM3_Initv+0xb8>)
+ 8000db2: 601a str r2, [r3, #0]
+ htim3.Init.Prescaler = 999;
+ 8000db4: 4b23 ldr r3, [pc, #140] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000db6: f240 32e7 movw r2, #999 ; 0x3e7
+ 8000dba: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000da4: 4b21 ldr r3, [pc, #132] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000da6: 2200 movs r2, #0
- 8000da8: 609a str r2, [r3, #8]
+ 8000dbc: 4b21 ldr r3, [pc, #132] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000dbe: 2200 movs r2, #0
+ 8000dc0: 609a str r2, [r3, #8]
htim3.Init.Period = 159;
- 8000daa: 4b20 ldr r3, [pc, #128] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000dac: 229f movs r2, #159 ; 0x9f
- 8000dae: 60da str r2, [r3, #12]
+ 8000dc2: 4b20 ldr r3, [pc, #128] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000dc4: 229f movs r2, #159 ; 0x9f
+ 8000dc6: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000db0: 4b1e ldr r3, [pc, #120] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000db2: 2200 movs r2, #0
- 8000db4: 611a str r2, [r3, #16]
+ 8000dc8: 4b1e ldr r3, [pc, #120] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000dca: 2200 movs r2, #0
+ 8000dcc: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000db6: 4b1d ldr r3, [pc, #116] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000db8: 2200 movs r2, #0
- 8000dba: 619a str r2, [r3, #24]
+ 8000dce: 4b1d ldr r3, [pc, #116] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000dd0: 2200 movs r2, #0
+ 8000dd2: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK) {
- 8000dbc: 481b ldr r0, [pc, #108] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000dbe: f002 f9bf bl 8003140 <HAL_TIM_Base_Init>
- 8000dc2: 4603 mov r3, r0
- 8000dc4: 2b00 cmp r3, #0
- 8000dc6: bf14 ite ne
- 8000dc8: 2301 movne r3, #1
- 8000dca: 2300 moveq r3, #0
- 8000dcc: b2db uxtb r3, r3
- 8000dce: 2b00 cmp r3, #0
- 8000dd0: d001 beq.n 8000dd6 <_ZL12MX_TIM3_Initv+0x5e>
+ 8000dd4: 481b ldr r0, [pc, #108] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000dd6: f002 f9f1 bl 80031bc <HAL_TIM_Base_Init>
+ 8000dda: 4603 mov r3, r0
+ 8000ddc: 2b00 cmp r3, #0
+ 8000dde: bf14 ite ne
+ 8000de0: 2301 movne r3, #1
+ 8000de2: 2300 moveq r3, #0
+ 8000de4: b2db uxtb r3, r3
+ 8000de6: 2b00 cmp r3, #0
+ 8000de8: d001 beq.n 8000dee <_ZL12MX_TIM3_Initv+0x5e>
Error_Handler();
- 8000dd2: f000 fb1f bl 8001414 <Error_Handler>
+ 8000dea: f000 fb51 bl 8001490 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000dd6: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000dda: 613b str r3, [r7, #16]
+ 8000dee: f44f 5380 mov.w r3, #4096 ; 0x1000
+ 8000df2: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) {
- 8000ddc: f107 0310 add.w r3, r7, #16
- 8000de0: 4619 mov r1, r3
- 8000de2: 4812 ldr r0, [pc, #72] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000de4: f002 fd7c bl 80038e0 <HAL_TIM_ConfigClockSource>
- 8000de8: 4603 mov r3, r0
- 8000dea: 2b00 cmp r3, #0
- 8000dec: bf14 ite ne
- 8000dee: 2301 movne r3, #1
- 8000df0: 2300 moveq r3, #0
- 8000df2: b2db uxtb r3, r3
- 8000df4: 2b00 cmp r3, #0
- 8000df6: d001 beq.n 8000dfc <_ZL12MX_TIM3_Initv+0x84>
+ 8000df4: f107 0310 add.w r3, r7, #16
+ 8000df8: 4619 mov r1, r3
+ 8000dfa: 4812 ldr r0, [pc, #72] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000dfc: f002 fdae bl 800395c <HAL_TIM_ConfigClockSource>
+ 8000e00: 4603 mov r3, r0
+ 8000e02: 2b00 cmp r3, #0
+ 8000e04: bf14 ite ne
+ 8000e06: 2301 movne r3, #1
+ 8000e08: 2300 moveq r3, #0
+ 8000e0a: b2db uxtb r3, r3
+ 8000e0c: 2b00 cmp r3, #0
+ 8000e0e: d001 beq.n 8000e14 <_ZL12MX_TIM3_Initv+0x84>
Error_Handler();
- 8000df8: f000 fb0c bl 8001414 <Error_Handler>
+ 8000e10: f000 fb3e bl 8001490 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000dfc: 2300 movs r3, #0
- 8000dfe: 607b str r3, [r7, #4]
+ 8000e14: 2300 movs r3, #0
+ 8000e16: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000e00: 2300 movs r3, #0
- 8000e02: 60fb str r3, [r7, #12]
+ 8000e18: 2300 movs r3, #0
+ 8000e1a: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) {
- 8000e04: 1d3b adds r3, r7, #4
- 8000e06: 4619 mov r1, r3
- 8000e08: 4808 ldr r0, [pc, #32] ; (8000e2c <_ZL12MX_TIM3_Initv+0xb4>)
- 8000e0a: f003 fa09 bl 8004220 <HAL_TIMEx_MasterConfigSynchronization>
- 8000e0e: 4603 mov r3, r0
- 8000e10: 2b00 cmp r3, #0
- 8000e12: bf14 ite ne
- 8000e14: 2301 movne r3, #1
- 8000e16: 2300 moveq r3, #0
- 8000e18: b2db uxtb r3, r3
- 8000e1a: 2b00 cmp r3, #0
- 8000e1c: d001 beq.n 8000e22 <_ZL12MX_TIM3_Initv+0xaa>
+ 8000e1c: 1d3b adds r3, r7, #4
+ 8000e1e: 4619 mov r1, r3
+ 8000e20: 4808 ldr r0, [pc, #32] ; (8000e44 <_ZL12MX_TIM3_Initv+0xb4>)
+ 8000e22: f003 fa3b bl 800429c <HAL_TIMEx_MasterConfigSynchronization>
+ 8000e26: 4603 mov r3, r0
+ 8000e28: 2b00 cmp r3, #0
+ 8000e2a: bf14 ite ne
+ 8000e2c: 2301 movne r3, #1
+ 8000e2e: 2300 moveq r3, #0
+ 8000e30: b2db uxtb r3, r3
+ 8000e32: 2b00 cmp r3, #0
+ 8000e34: d001 beq.n 8000e3a <_ZL12MX_TIM3_Initv+0xaa>
Error_Handler();
- 8000e1e: f000 faf9 bl 8001414 <Error_Handler>
+ 8000e36: f000 fb2b bl 8001490 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
- 8000e22: bf00 nop
- 8000e24: 3720 adds r7, #32
- 8000e26: 46bd mov sp, r7
- 8000e28: bd80 pop {r7, pc}
- 8000e2a: bf00 nop
- 8000e2c: 2000006c .word 0x2000006c
- 8000e30: 40000400 .word 0x40000400
-
-08000e34 <_ZL12MX_TIM4_Initv>:
+ 8000e3a: bf00 nop
+ 8000e3c: 3720 adds r7, #32
+ 8000e3e: 46bd mov sp, r7
+ 8000e40: bd80 pop {r7, pc}
+ 8000e42: bf00 nop
+ 8000e44: 20000070 .word 0x20000070
+ 8000e48: 40000400 .word 0x40000400
+
+08000e4c <_ZL12MX_TIM4_Initv>:
/**
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void) {
- 8000e34: b580 push {r7, lr}
- 8000e36: b08e sub sp, #56 ; 0x38
- 8000e38: af00 add r7, sp, #0
+ 8000e4c: b580 push {r7, lr}
+ 8000e4e: b08e sub sp, #56 ; 0x38
+ 8000e50: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = { 0 };
- 8000e3a: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000e3e: 2200 movs r2, #0
- 8000e40: 601a str r2, [r3, #0]
- 8000e42: 605a str r2, [r3, #4]
- 8000e44: 609a str r2, [r3, #8]
- 8000e46: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000e48: f107 031c add.w r3, r7, #28
- 8000e4c: 2200 movs r2, #0
- 8000e4e: 601a str r2, [r3, #0]
- 8000e50: 605a str r2, [r3, #4]
- 8000e52: 609a str r2, [r3, #8]
- TIM_OC_InitTypeDef sConfigOC = { 0 };
- 8000e54: 463b mov r3, r7
+ 8000e52: f107 0328 add.w r3, r7, #40 ; 0x28
8000e56: 2200 movs r2, #0
8000e58: 601a str r2, [r3, #0]
8000e5a: 605a str r2, [r3, #4]
8000e5c: 609a str r2, [r3, #8]
8000e5e: 60da str r2, [r3, #12]
- 8000e60: 611a str r2, [r3, #16]
- 8000e62: 615a str r2, [r3, #20]
- 8000e64: 619a str r2, [r3, #24]
+ TIM_MasterConfigTypeDef sMasterConfig = { 0 };
+ 8000e60: f107 031c add.w r3, r7, #28
+ 8000e64: 2200 movs r2, #0
+ 8000e66: 601a str r2, [r3, #0]
+ 8000e68: 605a str r2, [r3, #4]
+ 8000e6a: 609a str r2, [r3, #8]
+ TIM_OC_InitTypeDef sConfigOC = { 0 };
+ 8000e6c: 463b mov r3, r7
+ 8000e6e: 2200 movs r2, #0
+ 8000e70: 601a str r2, [r3, #0]
+ 8000e72: 605a str r2, [r3, #4]
+ 8000e74: 609a str r2, [r3, #8]
+ 8000e76: 60da str r2, [r3, #12]
+ 8000e78: 611a str r2, [r3, #16]
+ 8000e7a: 615a str r2, [r3, #20]
+ 8000e7c: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
- 8000e66: 4b41 ldr r3, [pc, #260] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000e68: 4a41 ldr r2, [pc, #260] ; (8000f70 <_ZL12MX_TIM4_Initv+0x13c>)
- 8000e6a: 601a str r2, [r3, #0]
+ 8000e7e: 4b41 ldr r3, [pc, #260] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000e80: 4a41 ldr r2, [pc, #260] ; (8000f88 <_ZL12MX_TIM4_Initv+0x13c>)
+ 8000e82: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 0;
- 8000e6c: 4b3f ldr r3, [pc, #252] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000e6e: 2200 movs r2, #0
- 8000e70: 605a str r2, [r3, #4]
+ 8000e84: 4b3f ldr r3, [pc, #252] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000e86: 2200 movs r2, #0
+ 8000e88: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000e72: 4b3e ldr r3, [pc, #248] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000e74: 2200 movs r2, #0
- 8000e76: 609a str r2, [r3, #8]
+ 8000e8a: 4b3e ldr r3, [pc, #248] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000e8c: 2200 movs r2, #0
+ 8000e8e: 609a str r2, [r3, #8]
htim4.Init.Period = 799;
- 8000e78: 4b3c ldr r3, [pc, #240] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000e7a: f240 321f movw r2, #799 ; 0x31f
- 8000e7e: 60da str r2, [r3, #12]
+ 8000e90: 4b3c ldr r3, [pc, #240] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000e92: f240 321f movw r2, #799 ; 0x31f
+ 8000e96: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000e80: 4b3a ldr r3, [pc, #232] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000e82: 2200 movs r2, #0
- 8000e84: 611a str r2, [r3, #16]
+ 8000e98: 4b3a ldr r3, [pc, #232] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000e9a: 2200 movs r2, #0
+ 8000e9c: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000e86: 4b39 ldr r3, [pc, #228] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000e88: 2200 movs r2, #0
- 8000e8a: 619a str r2, [r3, #24]
+ 8000e9e: 4b39 ldr r3, [pc, #228] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000ea0: 2200 movs r2, #0
+ 8000ea2: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim4) != HAL_OK) {
- 8000e8c: 4837 ldr r0, [pc, #220] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000e8e: f002 f957 bl 8003140 <HAL_TIM_Base_Init>
- 8000e92: 4603 mov r3, r0
- 8000e94: 2b00 cmp r3, #0
- 8000e96: bf14 ite ne
- 8000e98: 2301 movne r3, #1
- 8000e9a: 2300 moveq r3, #0
- 8000e9c: b2db uxtb r3, r3
- 8000e9e: 2b00 cmp r3, #0
- 8000ea0: d001 beq.n 8000ea6 <_ZL12MX_TIM4_Initv+0x72>
+ 8000ea4: 4837 ldr r0, [pc, #220] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000ea6: f002 f989 bl 80031bc <HAL_TIM_Base_Init>
+ 8000eaa: 4603 mov r3, r0
+ 8000eac: 2b00 cmp r3, #0
+ 8000eae: bf14 ite ne
+ 8000eb0: 2301 movne r3, #1
+ 8000eb2: 2300 moveq r3, #0
+ 8000eb4: b2db uxtb r3, r3
+ 8000eb6: 2b00 cmp r3, #0
+ 8000eb8: d001 beq.n 8000ebe <_ZL12MX_TIM4_Initv+0x72>
Error_Handler();
- 8000ea2: f000 fab7 bl 8001414 <Error_Handler>
+ 8000eba: f000 fae9 bl 8001490 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000ea6: f44f 5380 mov.w r3, #4096 ; 0x1000
- 8000eaa: 62bb str r3, [r7, #40] ; 0x28
+ 8000ebe: f44f 5380 mov.w r3, #4096 ; 0x1000
+ 8000ec2: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) {
- 8000eac: f107 0328 add.w r3, r7, #40 ; 0x28
- 8000eb0: 4619 mov r1, r3
- 8000eb2: 482e ldr r0, [pc, #184] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000eb4: f002 fd14 bl 80038e0 <HAL_TIM_ConfigClockSource>
- 8000eb8: 4603 mov r3, r0
- 8000eba: 2b00 cmp r3, #0
- 8000ebc: bf14 ite ne
- 8000ebe: 2301 movne r3, #1
- 8000ec0: 2300 moveq r3, #0
- 8000ec2: b2db uxtb r3, r3
- 8000ec4: 2b00 cmp r3, #0
- 8000ec6: d001 beq.n 8000ecc <_ZL12MX_TIM4_Initv+0x98>
+ 8000ec4: f107 0328 add.w r3, r7, #40 ; 0x28
+ 8000ec8: 4619 mov r1, r3
+ 8000eca: 482e ldr r0, [pc, #184] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000ecc: f002 fd46 bl 800395c <HAL_TIM_ConfigClockSource>
+ 8000ed0: 4603 mov r3, r0
+ 8000ed2: 2b00 cmp r3, #0
+ 8000ed4: bf14 ite ne
+ 8000ed6: 2301 movne r3, #1
+ 8000ed8: 2300 moveq r3, #0
+ 8000eda: b2db uxtb r3, r3
+ 8000edc: 2b00 cmp r3, #0
+ 8000ede: d001 beq.n 8000ee4 <_ZL12MX_TIM4_Initv+0x98>
Error_Handler();
- 8000ec8: f000 faa4 bl 8001414 <Error_Handler>
+ 8000ee0: f000 fad6 bl 8001490 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) {
- 8000ecc: 4827 ldr r0, [pc, #156] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000ece: f002 f98d bl 80031ec <HAL_TIM_PWM_Init>
- 8000ed2: 4603 mov r3, r0
- 8000ed4: 2b00 cmp r3, #0
- 8000ed6: bf14 ite ne
- 8000ed8: 2301 movne r3, #1
- 8000eda: 2300 moveq r3, #0
- 8000edc: b2db uxtb r3, r3
- 8000ede: 2b00 cmp r3, #0
- 8000ee0: d001 beq.n 8000ee6 <_ZL12MX_TIM4_Initv+0xb2>
+ 8000ee4: 4827 ldr r0, [pc, #156] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000ee6: f002 f9bf bl 8003268 <HAL_TIM_PWM_Init>
+ 8000eea: 4603 mov r3, r0
+ 8000eec: 2b00 cmp r3, #0
+ 8000eee: bf14 ite ne
+ 8000ef0: 2301 movne r3, #1
+ 8000ef2: 2300 moveq r3, #0
+ 8000ef4: b2db uxtb r3, r3
+ 8000ef6: 2b00 cmp r3, #0
+ 8000ef8: d001 beq.n 8000efe <_ZL12MX_TIM4_Initv+0xb2>
Error_Handler();
- 8000ee2: f000 fa97 bl 8001414 <Error_Handler>
+ 8000efa: f000 fac9 bl 8001490 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000ee6: 2300 movs r3, #0
- 8000ee8: 61fb str r3, [r7, #28]
+ 8000efe: 2300 movs r3, #0
+ 8000f00: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000eea: 2300 movs r3, #0
- 8000eec: 627b str r3, [r7, #36] ; 0x24
+ 8000f02: 2300 movs r3, #0
+ 8000f04: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) {
- 8000eee: f107 031c add.w r3, r7, #28
- 8000ef2: 4619 mov r1, r3
- 8000ef4: 481d ldr r0, [pc, #116] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000ef6: f003 f993 bl 8004220 <HAL_TIMEx_MasterConfigSynchronization>
- 8000efa: 4603 mov r3, r0
- 8000efc: 2b00 cmp r3, #0
- 8000efe: bf14 ite ne
- 8000f00: 2301 movne r3, #1
- 8000f02: 2300 moveq r3, #0
- 8000f04: b2db uxtb r3, r3
- 8000f06: 2b00 cmp r3, #0
- 8000f08: d001 beq.n 8000f0e <_ZL12MX_TIM4_Initv+0xda>
+ 8000f06: f107 031c add.w r3, r7, #28
+ 8000f0a: 4619 mov r1, r3
+ 8000f0c: 481d ldr r0, [pc, #116] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000f0e: f003 f9c5 bl 800429c <HAL_TIMEx_MasterConfigSynchronization>
+ 8000f12: 4603 mov r3, r0
+ 8000f14: 2b00 cmp r3, #0
+ 8000f16: bf14 ite ne
+ 8000f18: 2301 movne r3, #1
+ 8000f1a: 2300 moveq r3, #0
+ 8000f1c: b2db uxtb r3, r3
+ 8000f1e: 2b00 cmp r3, #0
+ 8000f20: d001 beq.n 8000f26 <_ZL12MX_TIM4_Initv+0xda>
Error_Handler();
- 8000f0a: f000 fa83 bl 8001414 <Error_Handler>
+ 8000f22: f000 fab5 bl 8001490 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8000f0e: 2360 movs r3, #96 ; 0x60
- 8000f10: 603b str r3, [r7, #0]
+ 8000f26: 2360 movs r3, #96 ; 0x60
+ 8000f28: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
- 8000f12: 2300 movs r3, #0
- 8000f14: 607b str r3, [r7, #4]
+ 8000f2a: 2300 movs r3, #0
+ 8000f2c: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 8000f16: 2300 movs r3, #0
- 8000f18: 60bb str r3, [r7, #8]
+ 8000f2e: 2300 movs r3, #0
+ 8000f30: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 8000f1a: 2300 movs r3, #0
- 8000f1c: 613b str r3, [r7, #16]
+ 8000f32: 2300 movs r3, #0
+ 8000f34: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) {
- 8000f1e: 463b mov r3, r7
- 8000f20: 2208 movs r2, #8
- 8000f22: 4619 mov r1, r3
- 8000f24: 4811 ldr r0, [pc, #68] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f26: f002 fbc3 bl 80036b0 <HAL_TIM_PWM_ConfigChannel>
- 8000f2a: 4603 mov r3, r0
- 8000f2c: 2b00 cmp r3, #0
- 8000f2e: bf14 ite ne
- 8000f30: 2301 movne r3, #1
- 8000f32: 2300 moveq r3, #0
- 8000f34: b2db uxtb r3, r3
- 8000f36: 2b00 cmp r3, #0
- 8000f38: d001 beq.n 8000f3e <_ZL12MX_TIM4_Initv+0x10a>
+ 8000f36: 463b mov r3, r7
+ 8000f38: 2208 movs r2, #8
+ 8000f3a: 4619 mov r1, r3
+ 8000f3c: 4811 ldr r0, [pc, #68] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000f3e: f002 fbf5 bl 800372c <HAL_TIM_PWM_ConfigChannel>
+ 8000f42: 4603 mov r3, r0
+ 8000f44: 2b00 cmp r3, #0
+ 8000f46: bf14 ite ne
+ 8000f48: 2301 movne r3, #1
+ 8000f4a: 2300 moveq r3, #0
+ 8000f4c: b2db uxtb r3, r3
+ 8000f4e: 2b00 cmp r3, #0
+ 8000f50: d001 beq.n 8000f56 <_ZL12MX_TIM4_Initv+0x10a>
Error_Handler();
- 8000f3a: f000 fa6b bl 8001414 <Error_Handler>
+ 8000f52: f000 fa9d bl 8001490 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) {
- 8000f3e: 463b mov r3, r7
- 8000f40: 220c movs r2, #12
- 8000f42: 4619 mov r1, r3
- 8000f44: 4809 ldr r0, [pc, #36] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f46: f002 fbb3 bl 80036b0 <HAL_TIM_PWM_ConfigChannel>
- 8000f4a: 4603 mov r3, r0
- 8000f4c: 2b00 cmp r3, #0
- 8000f4e: bf14 ite ne
- 8000f50: 2301 movne r3, #1
- 8000f52: 2300 moveq r3, #0
- 8000f54: b2db uxtb r3, r3
- 8000f56: 2b00 cmp r3, #0
- 8000f58: d001 beq.n 8000f5e <_ZL12MX_TIM4_Initv+0x12a>
+ 8000f56: 463b mov r3, r7
+ 8000f58: 220c movs r2, #12
+ 8000f5a: 4619 mov r1, r3
+ 8000f5c: 4809 ldr r0, [pc, #36] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000f5e: f002 fbe5 bl 800372c <HAL_TIM_PWM_ConfigChannel>
+ 8000f62: 4603 mov r3, r0
+ 8000f64: 2b00 cmp r3, #0
+ 8000f66: bf14 ite ne
+ 8000f68: 2301 movne r3, #1
+ 8000f6a: 2300 moveq r3, #0
+ 8000f6c: b2db uxtb r3, r3
+ 8000f6e: 2b00 cmp r3, #0
+ 8000f70: d001 beq.n 8000f76 <_ZL12MX_TIM4_Initv+0x12a>
Error_Handler();
- 8000f5a: f000 fa5b bl 8001414 <Error_Handler>
+ 8000f72: f000 fa8d bl 8001490 <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
- 8000f5e: 4803 ldr r0, [pc, #12] ; (8000f6c <_ZL12MX_TIM4_Initv+0x138>)
- 8000f60: f000 fbec bl 800173c <HAL_TIM_MspPostInit>
+ 8000f76: 4803 ldr r0, [pc, #12] ; (8000f84 <_ZL12MX_TIM4_Initv+0x138>)
+ 8000f78: f000 fc1e bl 80017b8 <HAL_TIM_MspPostInit>
}
- 8000f64: bf00 nop
- 8000f66: 3738 adds r7, #56 ; 0x38
- 8000f68: 46bd mov sp, r7
- 8000f6a: bd80 pop {r7, pc}
- 8000f6c: 200000ac .word 0x200000ac
- 8000f70: 40000800 .word 0x40000800
-
-08000f74 <_ZL12MX_TIM5_Initv>:
+ 8000f7c: bf00 nop
+ 8000f7e: 3738 adds r7, #56 ; 0x38
+ 8000f80: 46bd mov sp, r7
+ 8000f82: bd80 pop {r7, pc}
+ 8000f84: 200000b0 .word 0x200000b0
+ 8000f88: 40000800 .word 0x40000800
+
+08000f8c <_ZL12MX_TIM5_Initv>:
/**
* @brief TIM5 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM5_Init(void) {
- 8000f74: b580 push {r7, lr}
- 8000f76: b08c sub sp, #48 ; 0x30
- 8000f78: af00 add r7, sp, #0
+ 8000f8c: b580 push {r7, lr}
+ 8000f8e: b08c sub sp, #48 ; 0x30
+ 8000f90: af00 add r7, sp, #0
/* USER CODE BEGIN TIM5_Init 0 */
/* USER CODE END TIM5_Init 0 */
TIM_Encoder_InitTypeDef sConfig = { 0 };
- 8000f7a: f107 030c add.w r3, r7, #12
- 8000f7e: 2224 movs r2, #36 ; 0x24
- 8000f80: 2100 movs r1, #0
- 8000f82: 4618 mov r0, r3
- 8000f84: f004 f806 bl 8004f94 <memset>
+ 8000f92: f107 030c add.w r3, r7, #12
+ 8000f96: 2224 movs r2, #36 ; 0x24
+ 8000f98: 2100 movs r1, #0
+ 8000f9a: 4618 mov r0, r3
+ 8000f9c: f004 f980 bl 80052a0 <memset>
TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 8000f88: 463b mov r3, r7
- 8000f8a: 2200 movs r2, #0
- 8000f8c: 601a str r2, [r3, #0]
- 8000f8e: 605a str r2, [r3, #4]
- 8000f90: 609a str r2, [r3, #8]
+ 8000fa0: 463b mov r3, r7
+ 8000fa2: 2200 movs r2, #0
+ 8000fa4: 601a str r2, [r3, #0]
+ 8000fa6: 605a str r2, [r3, #4]
+ 8000fa8: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM5_Init 1 */
/* USER CODE END TIM5_Init 1 */
htim5.Instance = TIM5;
- 8000f92: 4b26 ldr r3, [pc, #152] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 8000f94: 4a26 ldr r2, [pc, #152] ; (8001030 <_ZL12MX_TIM5_Initv+0xbc>)
- 8000f96: 601a str r2, [r3, #0]
+ 8000faa: 4b26 ldr r3, [pc, #152] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8000fac: 4a26 ldr r2, [pc, #152] ; (8001048 <_ZL12MX_TIM5_Initv+0xbc>)
+ 8000fae: 601a str r2, [r3, #0]
htim5.Init.Prescaler = 0;
- 8000f98: 4b24 ldr r3, [pc, #144] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 8000f9a: 2200 movs r2, #0
- 8000f9c: 605a str r2, [r3, #4]
+ 8000fb0: 4b24 ldr r3, [pc, #144] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8000fb2: 2200 movs r2, #0
+ 8000fb4: 605a str r2, [r3, #4]
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000f9e: 4b23 ldr r3, [pc, #140] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 8000fa0: 2200 movs r2, #0
- 8000fa2: 609a str r2, [r3, #8]
+ 8000fb6: 4b23 ldr r3, [pc, #140] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8000fb8: 2200 movs r2, #0
+ 8000fba: 609a str r2, [r3, #8]
htim5.Init.Period = 4294967295;
- 8000fa4: 4b21 ldr r3, [pc, #132] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 8000fa6: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000faa: 60da str r2, [r3, #12]
+ 8000fbc: 4b21 ldr r3, [pc, #132] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8000fbe: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 8000fc2: 60da str r2, [r3, #12]
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000fac: 4b1f ldr r3, [pc, #124] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 8000fae: 2200 movs r2, #0
- 8000fb0: 611a str r2, [r3, #16]
+ 8000fc4: 4b1f ldr r3, [pc, #124] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8000fc6: 2200 movs r2, #0
+ 8000fc8: 611a str r2, [r3, #16]
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8000fb2: 4b1e ldr r3, [pc, #120] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 8000fb4: 2200 movs r2, #0
- 8000fb6: 619a str r2, [r3, #24]
+ 8000fca: 4b1e ldr r3, [pc, #120] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8000fcc: 2200 movs r2, #0
+ 8000fce: 619a str r2, [r3, #24]
sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8000fb8: 2303 movs r3, #3
- 8000fba: 60fb str r3, [r7, #12]
+ 8000fd0: 2303 movs r3, #3
+ 8000fd2: 60fb str r3, [r7, #12]
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8000fbc: 2300 movs r3, #0
- 8000fbe: 613b str r3, [r7, #16]
+ 8000fd4: 2300 movs r3, #0
+ 8000fd6: 613b str r3, [r7, #16]
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8000fc0: 2301 movs r3, #1
- 8000fc2: 617b str r3, [r7, #20]
+ 8000fd8: 2301 movs r3, #1
+ 8000fda: 617b str r3, [r7, #20]
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 8000fc4: 2300 movs r3, #0
- 8000fc6: 61bb str r3, [r7, #24]
+ 8000fdc: 2300 movs r3, #0
+ 8000fde: 61bb str r3, [r7, #24]
sConfig.IC1Filter = 0;
- 8000fc8: 2300 movs r3, #0
- 8000fca: 61fb str r3, [r7, #28]
+ 8000fe0: 2300 movs r3, #0
+ 8000fe2: 61fb str r3, [r7, #28]
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8000fcc: 2300 movs r3, #0
- 8000fce: 623b str r3, [r7, #32]
+ 8000fe4: 2300 movs r3, #0
+ 8000fe6: 623b str r3, [r7, #32]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 8000fd0: 2301 movs r3, #1
- 8000fd2: 627b str r3, [r7, #36] ; 0x24
+ 8000fe8: 2301 movs r3, #1
+ 8000fea: 627b str r3, [r7, #36] ; 0x24
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8000fd4: 2300 movs r3, #0
- 8000fd6: 62bb str r3, [r7, #40] ; 0x28
+ 8000fec: 2300 movs r3, #0
+ 8000fee: 62bb str r3, [r7, #40] ; 0x28
sConfig.IC2Filter = 0;
- 8000fd8: 2300 movs r3, #0
- 8000fda: 62fb str r3, [r7, #44] ; 0x2c
+ 8000ff0: 2300 movs r3, #0
+ 8000ff2: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIM_Encoder_Init(&htim5, &sConfig) != HAL_OK) {
- 8000fdc: f107 030c add.w r3, r7, #12
- 8000fe0: 4619 mov r1, r3
- 8000fe2: 4812 ldr r0, [pc, #72] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 8000fe4: f002 f97c bl 80032e0 <HAL_TIM_Encoder_Init>
- 8000fe8: 4603 mov r3, r0
- 8000fea: 2b00 cmp r3, #0
- 8000fec: bf14 ite ne
- 8000fee: 2301 movne r3, #1
- 8000ff0: 2300 moveq r3, #0
- 8000ff2: b2db uxtb r3, r3
- 8000ff4: 2b00 cmp r3, #0
- 8000ff6: d001 beq.n 8000ffc <_ZL12MX_TIM5_Initv+0x88>
+ 8000ff4: f107 030c add.w r3, r7, #12
+ 8000ff8: 4619 mov r1, r3
+ 8000ffa: 4812 ldr r0, [pc, #72] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8000ffc: f002 f9ae bl 800335c <HAL_TIM_Encoder_Init>
+ 8001000: 4603 mov r3, r0
+ 8001002: 2b00 cmp r3, #0
+ 8001004: bf14 ite ne
+ 8001006: 2301 movne r3, #1
+ 8001008: 2300 moveq r3, #0
+ 800100a: b2db uxtb r3, r3
+ 800100c: 2b00 cmp r3, #0
+ 800100e: d001 beq.n 8001014 <_ZL12MX_TIM5_Initv+0x88>
Error_Handler();
- 8000ff8: f000 fa0c bl 8001414 <Error_Handler>
+ 8001010: f000 fa3e bl 8001490 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000ffc: 2300 movs r3, #0
- 8000ffe: 603b str r3, [r7, #0]
+ 8001014: 2300 movs r3, #0
+ 8001016: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8001000: 2300 movs r3, #0
- 8001002: 60bb str r3, [r7, #8]
+ 8001018: 2300 movs r3, #0
+ 800101a: 60bb str r3, [r7, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) {
- 8001004: 463b mov r3, r7
- 8001006: 4619 mov r1, r3
- 8001008: 4808 ldr r0, [pc, #32] ; (800102c <_ZL12MX_TIM5_Initv+0xb8>)
- 800100a: f003 f909 bl 8004220 <HAL_TIMEx_MasterConfigSynchronization>
- 800100e: 4603 mov r3, r0
- 8001010: 2b00 cmp r3, #0
- 8001012: bf14 ite ne
- 8001014: 2301 movne r3, #1
- 8001016: 2300 moveq r3, #0
- 8001018: b2db uxtb r3, r3
- 800101a: 2b00 cmp r3, #0
- 800101c: d001 beq.n 8001022 <_ZL12MX_TIM5_Initv+0xae>
+ 800101c: 463b mov r3, r7
+ 800101e: 4619 mov r1, r3
+ 8001020: 4808 ldr r0, [pc, #32] ; (8001044 <_ZL12MX_TIM5_Initv+0xb8>)
+ 8001022: f003 f93b bl 800429c <HAL_TIMEx_MasterConfigSynchronization>
+ 8001026: 4603 mov r3, r0
+ 8001028: 2b00 cmp r3, #0
+ 800102a: bf14 ite ne
+ 800102c: 2301 movne r3, #1
+ 800102e: 2300 moveq r3, #0
+ 8001030: b2db uxtb r3, r3
+ 8001032: 2b00 cmp r3, #0
+ 8001034: d001 beq.n 800103a <_ZL12MX_TIM5_Initv+0xae>
Error_Handler();
- 800101e: f000 f9f9 bl 8001414 <Error_Handler>
+ 8001036: f000 fa2b bl 8001490 <Error_Handler>
}
/* USER CODE BEGIN TIM5_Init 2 */
/* USER CODE END TIM5_Init 2 */
}
- 8001022: bf00 nop
- 8001024: 3730 adds r7, #48 ; 0x30
- 8001026: 46bd mov sp, r7
- 8001028: bd80 pop {r7, pc}
- 800102a: bf00 nop
- 800102c: 200000ec .word 0x200000ec
- 8001030: 40000c00 .word 0x40000c00
-
-08001034 <_ZL12MX_TIM6_Initv>:
+ 800103a: bf00 nop
+ 800103c: 3730 adds r7, #48 ; 0x30
+ 800103e: 46bd mov sp, r7
+ 8001040: bd80 pop {r7, pc}
+ 8001042: bf00 nop
+ 8001044: 200000f0 .word 0x200000f0
+ 8001048: 40000c00 .word 0x40000c00
+
+0800104c <_ZL12MX_TIM6_Initv>:
/**
* @brief TIM6 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM6_Init(void) {
- 8001034: b580 push {r7, lr}
- 8001036: b084 sub sp, #16
- 8001038: af00 add r7, sp, #0
+ 800104c: b580 push {r7, lr}
+ 800104e: b084 sub sp, #16
+ 8001050: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_Init 0 */
/* USER CODE END TIM6_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = { 0 };
- 800103a: 1d3b adds r3, r7, #4
- 800103c: 2200 movs r2, #0
- 800103e: 601a str r2, [r3, #0]
- 8001040: 605a str r2, [r3, #4]
- 8001042: 609a str r2, [r3, #8]
+ 8001052: 1d3b adds r3, r7, #4
+ 8001054: 2200 movs r2, #0
+ 8001056: 601a str r2, [r3, #0]
+ 8001058: 605a str r2, [r3, #4]
+ 800105a: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM6_Init 1 */
/* USER CODE END TIM6_Init 1 */
htim6.Instance = TIM6;
- 8001044: 4b1a ldr r3, [pc, #104] ; (80010b0 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001046: 4a1b ldr r2, [pc, #108] ; (80010b4 <_ZL12MX_TIM6_Initv+0x80>)
- 8001048: 601a str r2, [r3, #0]
+ 800105c: 4b1a ldr r3, [pc, #104] ; (80010c8 <_ZL12MX_TIM6_Initv+0x7c>)
+ 800105e: 4a1b ldr r2, [pc, #108] ; (80010cc <_ZL12MX_TIM6_Initv+0x80>)
+ 8001060: 601a str r2, [r3, #0]
htim6.Init.Prescaler = 9999;
- 800104a: 4b19 ldr r3, [pc, #100] ; (80010b0 <_ZL12MX_TIM6_Initv+0x7c>)
- 800104c: f242 720f movw r2, #9999 ; 0x270f
- 8001050: 605a str r2, [r3, #4]
+ 8001062: 4b19 ldr r3, [pc, #100] ; (80010c8 <_ZL12MX_TIM6_Initv+0x7c>)
+ 8001064: f242 720f movw r2, #9999 ; 0x270f
+ 8001068: 605a str r2, [r3, #4]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001052: 4b17 ldr r3, [pc, #92] ; (80010b0 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001054: 2200 movs r2, #0
- 8001056: 609a str r2, [r3, #8]
+ 800106a: 4b17 ldr r3, [pc, #92] ; (80010c8 <_ZL12MX_TIM6_Initv+0x7c>)
+ 800106c: 2200 movs r2, #0
+ 800106e: 609a str r2, [r3, #8]
htim6.Init.Period = 799;
- 8001058: 4b15 ldr r3, [pc, #84] ; (80010b0 <_ZL12MX_TIM6_Initv+0x7c>)
- 800105a: f240 321f movw r2, #799 ; 0x31f
- 800105e: 60da str r2, [r3, #12]
+ 8001070: 4b15 ldr r3, [pc, #84] ; (80010c8 <_ZL12MX_TIM6_Initv+0x7c>)
+ 8001072: f240 321f movw r2, #799 ; 0x31f
+ 8001076: 60da str r2, [r3, #12]
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001060: 4b13 ldr r3, [pc, #76] ; (80010b0 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001062: 2200 movs r2, #0
- 8001064: 619a str r2, [r3, #24]
+ 8001078: 4b13 ldr r3, [pc, #76] ; (80010c8 <_ZL12MX_TIM6_Initv+0x7c>)
+ 800107a: 2200 movs r2, #0
+ 800107c: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim6) != HAL_OK) {
- 8001066: 4812 ldr r0, [pc, #72] ; (80010b0 <_ZL12MX_TIM6_Initv+0x7c>)
- 8001068: f002 f86a bl 8003140 <HAL_TIM_Base_Init>
- 800106c: 4603 mov r3, r0
- 800106e: 2b00 cmp r3, #0
- 8001070: bf14 ite ne
- 8001072: 2301 movne r3, #1
- 8001074: 2300 moveq r3, #0
- 8001076: b2db uxtb r3, r3
- 8001078: 2b00 cmp r3, #0
- 800107a: d001 beq.n 8001080 <_ZL12MX_TIM6_Initv+0x4c>
+ 800107e: 4812 ldr r0, [pc, #72] ; (80010c8 <_ZL12MX_TIM6_Initv+0x7c>)
+ 8001080: f002 f89c bl 80031bc <HAL_TIM_Base_Init>
+ 8001084: 4603 mov r3, r0
+ 8001086: 2b00 cmp r3, #0
+ 8001088: bf14 ite ne
+ 800108a: 2301 movne r3, #1
+ 800108c: 2300 moveq r3, #0
+ 800108e: b2db uxtb r3, r3
+ 8001090: 2b00 cmp r3, #0
+ 8001092: d001 beq.n 8001098 <_ZL12MX_TIM6_Initv+0x4c>
Error_Handler();
- 800107c: f000 f9ca bl 8001414 <Error_Handler>
+ 8001094: f000 f9fc bl 8001490 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001080: 2300 movs r3, #0
- 8001082: 607b str r3, [r7, #4]
+ 8001098: 2300 movs r3, #0
+ 800109a: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8001084: 2300 movs r3, #0
- 8001086: 60fb str r3, [r7, #12]
+ 800109c: 2300 movs r3, #0
+ 800109e: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) {
- 8001088: 1d3b adds r3, r7, #4
- 800108a: 4619 mov r1, r3
- 800108c: 4808 ldr r0, [pc, #32] ; (80010b0 <_ZL12MX_TIM6_Initv+0x7c>)
- 800108e: f003 f8c7 bl 8004220 <HAL_TIMEx_MasterConfigSynchronization>
- 8001092: 4603 mov r3, r0
- 8001094: 2b00 cmp r3, #0
- 8001096: bf14 ite ne
- 8001098: 2301 movne r3, #1
- 800109a: 2300 moveq r3, #0
- 800109c: b2db uxtb r3, r3
- 800109e: 2b00 cmp r3, #0
- 80010a0: d001 beq.n 80010a6 <_ZL12MX_TIM6_Initv+0x72>
+ 80010a0: 1d3b adds r3, r7, #4
+ 80010a2: 4619 mov r1, r3
+ 80010a4: 4808 ldr r0, [pc, #32] ; (80010c8 <_ZL12MX_TIM6_Initv+0x7c>)
+ 80010a6: f003 f8f9 bl 800429c <HAL_TIMEx_MasterConfigSynchronization>
+ 80010aa: 4603 mov r3, r0
+ 80010ac: 2b00 cmp r3, #0
+ 80010ae: bf14 ite ne
+ 80010b0: 2301 movne r3, #1
+ 80010b2: 2300 moveq r3, #0
+ 80010b4: b2db uxtb r3, r3
+ 80010b6: 2b00 cmp r3, #0
+ 80010b8: d001 beq.n 80010be <_ZL12MX_TIM6_Initv+0x72>
Error_Handler();
- 80010a2: f000 f9b7 bl 8001414 <Error_Handler>
+ 80010ba: f000 f9e9 bl 8001490 <Error_Handler>
}
/* USER CODE BEGIN TIM6_Init 2 */
/* USER CODE END TIM6_Init 2 */
}
- 80010a6: bf00 nop
- 80010a8: 3710 adds r7, #16
- 80010aa: 46bd mov sp, r7
- 80010ac: bd80 pop {r7, pc}
- 80010ae: bf00 nop
- 80010b0: 2000012c .word 0x2000012c
- 80010b4: 40001000 .word 0x40001000
-
-080010b8 <_ZL19MX_USART6_UART_Initv>:
+ 80010be: bf00 nop
+ 80010c0: 3710 adds r7, #16
+ 80010c2: 46bd mov sp, r7
+ 80010c4: bd80 pop {r7, pc}
+ 80010c6: bf00 nop
+ 80010c8: 20000130 .word 0x20000130
+ 80010cc: 40001000 .word 0x40001000
+
+080010d0 <_ZL19MX_USART6_UART_Initv>:
/**
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void) {
- 80010b8: b580 push {r7, lr}
- 80010ba: af00 add r7, sp, #0
+ 80010d0: b580 push {r7, lr}
+ 80010d2: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
- 80010bc: 4b17 ldr r3, [pc, #92] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010be: 4a18 ldr r2, [pc, #96] ; (8001120 <_ZL19MX_USART6_UART_Initv+0x68>)
- 80010c0: 601a str r2, [r3, #0]
+ 80010d4: 4b17 ldr r3, [pc, #92] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 80010d6: 4a18 ldr r2, [pc, #96] ; (8001138 <_ZL19MX_USART6_UART_Initv+0x68>)
+ 80010d8: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
- 80010c2: 4b16 ldr r3, [pc, #88] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010c4: f44f 32e1 mov.w r2, #115200 ; 0x1c200
- 80010c8: 605a str r2, [r3, #4]
+ 80010da: 4b16 ldr r3, [pc, #88] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 80010dc: f44f 32e1 mov.w r2, #115200 ; 0x1c200
+ 80010e0: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_9B;
- 80010ca: 4b14 ldr r3, [pc, #80] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010cc: f44f 5280 mov.w r2, #4096 ; 0x1000
- 80010d0: 609a str r2, [r3, #8]
+ 80010e2: 4b14 ldr r3, [pc, #80] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 80010e4: f44f 5280 mov.w r2, #4096 ; 0x1000
+ 80010e8: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
- 80010d2: 4b12 ldr r3, [pc, #72] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010d4: 2200 movs r2, #0
- 80010d6: 60da str r2, [r3, #12]
+ 80010ea: 4b12 ldr r3, [pc, #72] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 80010ec: 2200 movs r2, #0
+ 80010ee: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_ODD;
- 80010d8: 4b10 ldr r3, [pc, #64] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010da: f44f 62c0 mov.w r2, #1536 ; 0x600
- 80010de: 611a str r2, [r3, #16]
+ 80010f0: 4b10 ldr r3, [pc, #64] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 80010f2: f44f 62c0 mov.w r2, #1536 ; 0x600
+ 80010f6: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
- 80010e0: 4b0e ldr r3, [pc, #56] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010e2: 220c movs r2, #12
- 80010e4: 615a str r2, [r3, #20]
+ 80010f8: 4b0e ldr r3, [pc, #56] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 80010fa: 220c movs r2, #12
+ 80010fc: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 80010e6: 4b0d ldr r3, [pc, #52] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010e8: 2200 movs r2, #0
- 80010ea: 619a str r2, [r3, #24]
+ 80010fe: 4b0d ldr r3, [pc, #52] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 8001100: 2200 movs r2, #0
+ 8001102: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
- 80010ec: 4b0b ldr r3, [pc, #44] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010ee: 2200 movs r2, #0
- 80010f0: 61da str r2, [r3, #28]
+ 8001104: 4b0b ldr r3, [pc, #44] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 8001106: 2200 movs r2, #0
+ 8001108: 61da str r2, [r3, #28]
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 80010f2: 4b0a ldr r3, [pc, #40] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010f4: 2200 movs r2, #0
- 80010f6: 621a str r2, [r3, #32]
+ 800110a: 4b0a ldr r3, [pc, #40] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 800110c: 2200 movs r2, #0
+ 800110e: 621a str r2, [r3, #32]
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 80010f8: 4b08 ldr r3, [pc, #32] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 80010fa: 2200 movs r2, #0
- 80010fc: 625a str r2, [r3, #36] ; 0x24
+ 8001110: 4b08 ldr r3, [pc, #32] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 8001112: 2200 movs r2, #0
+ 8001114: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart6) != HAL_OK) {
- 80010fe: 4807 ldr r0, [pc, #28] ; (800111c <_ZL19MX_USART6_UART_Initv+0x64>)
- 8001100: f003 f908 bl 8004314 <HAL_UART_Init>
- 8001104: 4603 mov r3, r0
- 8001106: 2b00 cmp r3, #0
- 8001108: bf14 ite ne
- 800110a: 2301 movne r3, #1
- 800110c: 2300 moveq r3, #0
- 800110e: b2db uxtb r3, r3
- 8001110: 2b00 cmp r3, #0
- 8001112: d001 beq.n 8001118 <_ZL19MX_USART6_UART_Initv+0x60>
+ 8001116: 4807 ldr r0, [pc, #28] ; (8001134 <_ZL19MX_USART6_UART_Initv+0x64>)
+ 8001118: f003 f93a bl 8004390 <HAL_UART_Init>
+ 800111c: 4603 mov r3, r0
+ 800111e: 2b00 cmp r3, #0
+ 8001120: bf14 ite ne
+ 8001122: 2301 movne r3, #1
+ 8001124: 2300 moveq r3, #0
+ 8001126: b2db uxtb r3, r3
+ 8001128: 2b00 cmp r3, #0
+ 800112a: d001 beq.n 8001130 <_ZL19MX_USART6_UART_Initv+0x60>
Error_Handler();
- 8001114: f000 f97e bl 8001414 <Error_Handler>
+ 800112c: f000 f9b0 bl 8001490 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
- 8001118: bf00 nop
- 800111a: bd80 pop {r7, pc}
- 800111c: 2000016c .word 0x2000016c
- 8001120: 40011400 .word 0x40011400
+ 8001130: bf00 nop
+ 8001132: bd80 pop {r7, pc}
+ 8001134: 20000170 .word 0x20000170
+ 8001138: 40011400 .word 0x40011400
-08001124 <_ZL12MX_GPIO_Initv>:
+0800113c <_ZL12MX_GPIO_Initv>:
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void) {
- 8001124: b580 push {r7, lr}
- 8001126: b08c sub sp, #48 ; 0x30
- 8001128: af00 add r7, sp, #0
+ 800113c: b580 push {r7, lr}
+ 800113e: b08c sub sp, #48 ; 0x30
+ 8001140: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = { 0 };
- 800112a: f107 031c add.w r3, r7, #28
- 800112e: 2200 movs r2, #0
- 8001130: 601a str r2, [r3, #0]
- 8001132: 605a str r2, [r3, #4]
- 8001134: 609a str r2, [r3, #8]
- 8001136: 60da str r2, [r3, #12]
- 8001138: 611a str r2, [r3, #16]
+ 8001142: f107 031c add.w r3, r7, #28
+ 8001146: 2200 movs r2, #0
+ 8001148: 601a str r2, [r3, #0]
+ 800114a: 605a str r2, [r3, #4]
+ 800114c: 609a str r2, [r3, #8]
+ 800114e: 60da str r2, [r3, #12]
+ 8001150: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
- 800113a: 4b5e ldr r3, [pc, #376] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 800113c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800113e: 4a5d ldr r2, [pc, #372] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 8001140: f043 0304 orr.w r3, r3, #4
- 8001144: 6313 str r3, [r2, #48] ; 0x30
- 8001146: 4b5b ldr r3, [pc, #364] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 8001148: 6b1b ldr r3, [r3, #48] ; 0x30
- 800114a: f003 0304 and.w r3, r3, #4
- 800114e: 61bb str r3, [r7, #24]
- 8001150: 69bb ldr r3, [r7, #24]
- __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001152: 4b58 ldr r3, [pc, #352] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 8001152: 4b5e ldr r3, [pc, #376] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
8001154: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001156: 4a57 ldr r2, [pc, #348] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 8001158: f043 0301 orr.w r3, r3, #1
+ 8001156: 4a5d ldr r2, [pc, #372] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 8001158: f043 0304 orr.w r3, r3, #4
800115c: 6313 str r3, [r2, #48] ; 0x30
- 800115e: 4b55 ldr r3, [pc, #340] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 800115e: 4b5b ldr r3, [pc, #364] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
8001160: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001162: f003 0301 and.w r3, r3, #1
- 8001166: 617b str r3, [r7, #20]
- 8001168: 697b ldr r3, [r7, #20]
- __HAL_RCC_GPIOF_CLK_ENABLE();
- 800116a: 4b52 ldr r3, [pc, #328] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 8001162: f003 0304 and.w r3, r3, #4
+ 8001166: 61bb str r3, [r7, #24]
+ 8001168: 69bb ldr r3, [r7, #24]
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800116a: 4b58 ldr r3, [pc, #352] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
800116c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800116e: 4a51 ldr r2, [pc, #324] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 8001170: f043 0320 orr.w r3, r3, #32
+ 800116e: 4a57 ldr r2, [pc, #348] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 8001170: f043 0301 orr.w r3, r3, #1
8001174: 6313 str r3, [r2, #48] ; 0x30
- 8001176: 4b4f ldr r3, [pc, #316] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 8001176: 4b55 ldr r3, [pc, #340] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
8001178: 6b1b ldr r3, [r3, #48] ; 0x30
- 800117a: f003 0320 and.w r3, r3, #32
- 800117e: 613b str r3, [r7, #16]
- 8001180: 693b ldr r3, [r7, #16]
- __HAL_RCC_GPIOE_CLK_ENABLE();
- 8001182: 4b4c ldr r3, [pc, #304] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 800117a: f003 0301 and.w r3, r3, #1
+ 800117e: 617b str r3, [r7, #20]
+ 8001180: 697b ldr r3, [r7, #20]
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ 8001182: 4b52 ldr r3, [pc, #328] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
8001184: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001186: 4a4b ldr r2, [pc, #300] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 8001188: f043 0310 orr.w r3, r3, #16
+ 8001186: 4a51 ldr r2, [pc, #324] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 8001188: f043 0320 orr.w r3, r3, #32
800118c: 6313 str r3, [r2, #48] ; 0x30
- 800118e: 4b49 ldr r3, [pc, #292] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 800118e: 4b4f ldr r3, [pc, #316] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
8001190: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001192: f003 0310 and.w r3, r3, #16
- 8001196: 60fb str r3, [r7, #12]
- 8001198: 68fb ldr r3, [r7, #12]
- __HAL_RCC_GPIOD_CLK_ENABLE();
- 800119a: 4b46 ldr r3, [pc, #280] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 8001192: f003 0320 and.w r3, r3, #32
+ 8001196: 613b str r3, [r7, #16]
+ 8001198: 693b ldr r3, [r7, #16]
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ 800119a: 4b4c ldr r3, [pc, #304] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
800119c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800119e: 4a45 ldr r2, [pc, #276] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 80011a0: f043 0308 orr.w r3, r3, #8
+ 800119e: 4a4b ldr r2, [pc, #300] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 80011a0: f043 0310 orr.w r3, r3, #16
80011a4: 6313 str r3, [r2, #48] ; 0x30
- 80011a6: 4b43 ldr r3, [pc, #268] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 80011a6: 4b49 ldr r3, [pc, #292] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
80011a8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80011aa: f003 0308 and.w r3, r3, #8
- 80011ae: 60bb str r3, [r7, #8]
- 80011b0: 68bb ldr r3, [r7, #8]
- __HAL_RCC_GPIOB_CLK_ENABLE();
- 80011b2: 4b40 ldr r3, [pc, #256] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 80011aa: f003 0310 and.w r3, r3, #16
+ 80011ae: 60fb str r3, [r7, #12]
+ 80011b0: 68fb ldr r3, [r7, #12]
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ 80011b2: 4b46 ldr r3, [pc, #280] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
80011b4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80011b6: 4a3f ldr r2, [pc, #252] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
- 80011b8: f043 0302 orr.w r3, r3, #2
+ 80011b6: 4a45 ldr r2, [pc, #276] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 80011b8: f043 0308 orr.w r3, r3, #8
80011bc: 6313 str r3, [r2, #48] ; 0x30
- 80011be: 4b3d ldr r3, [pc, #244] ; (80012b4 <_ZL12MX_GPIO_Initv+0x190>)
+ 80011be: 4b43 ldr r3, [pc, #268] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
80011c0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80011c2: f003 0302 and.w r3, r3, #2
- 80011c6: 607b str r3, [r7, #4]
- 80011c8: 687b ldr r3, [r7, #4]
+ 80011c2: f003 0308 and.w r3, r3, #8
+ 80011c6: 60bb str r3, [r7, #8]
+ 80011c8: 68bb ldr r3, [r7, #8]
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ 80011ca: 4b40 ldr r3, [pc, #256] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 80011cc: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80011ce: 4a3f ldr r2, [pc, #252] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 80011d0: f043 0302 orr.w r3, r3, #2
+ 80011d4: 6313 str r3, [r2, #48] ; 0x30
+ 80011d6: 4b3d ldr r3, [pc, #244] ; (80012cc <_ZL12MX_GPIO_Initv+0x190>)
+ 80011d8: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80011da: f003 0302 and.w r3, r3, #2
+ 80011de: 607b str r3, [r7, #4]
+ 80011e0: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOF, dir2_Pin | dir1_Pin, GPIO_PIN_RESET);
- 80011ca: 2200 movs r2, #0
- 80011cc: f44f 5140 mov.w r1, #12288 ; 0x3000
- 80011d0: 4839 ldr r0, [pc, #228] ; (80012b8 <_ZL12MX_GPIO_Initv+0x194>)
- 80011d2: f000 ff1d bl 8002010 <HAL_GPIO_WritePin>
+ 80011e2: 2200 movs r2, #0
+ 80011e4: f44f 5140 mov.w r1, #12288 ; 0x3000
+ 80011e8: 4839 ldr r0, [pc, #228] ; (80012d0 <_ZL12MX_GPIO_Initv+0x194>)
+ 80011ea: f000 ff4f bl 800208c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOF, sleep2_Pin | sleep1_Pin, GPIO_PIN_SET);
- 80011d6: 2201 movs r2, #1
- 80011d8: f44f 4140 mov.w r1, #49152 ; 0xc000
- 80011dc: 4836 ldr r0, [pc, #216] ; (80012b8 <_ZL12MX_GPIO_Initv+0x194>)
- 80011de: f000 ff17 bl 8002010 <HAL_GPIO_WritePin>
+ 80011ee: 2201 movs r2, #1
+ 80011f0: f44f 4140 mov.w r1, #49152 ; 0xc000
+ 80011f4: 4836 ldr r0, [pc, #216] ; (80012d0 <_ZL12MX_GPIO_Initv+0x194>)
+ 80011f6: f000 ff49 bl 800208c <HAL_GPIO_WritePin>
/*Configure GPIO pin : user_button_Pin */
GPIO_InitStruct.Pin = user_button_Pin;
- 80011e2: f44f 5300 mov.w r3, #8192 ; 0x2000
- 80011e6: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
- 80011e8: 4b34 ldr r3, [pc, #208] ; (80012bc <_ZL12MX_GPIO_Initv+0x198>)
- 80011ea: 623b str r3, [r7, #32]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80011ec: 2300 movs r3, #0
- 80011ee: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct);
- 80011f0: f107 031c add.w r3, r7, #28
- 80011f4: 4619 mov r1, r3
- 80011f6: 4832 ldr r0, [pc, #200] ; (80012c0 <_ZL12MX_GPIO_Initv+0x19c>)
- 80011f8: f000 fd60 bl 8001cbc <HAL_GPIO_Init>
-
- /*Configure GPIO pin : current2_Pin */
- GPIO_InitStruct.Pin = current2_Pin;
- 80011fc: 2301 movs r3, #1
+ 80011fa: f44f 5300 mov.w r3, #8192 ; 0x2000
80011fe: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
- 8001200: 2303 movs r3, #3
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+ 8001200: 4b34 ldr r3, [pc, #208] ; (80012d4 <_ZL12MX_GPIO_Initv+0x198>)
8001202: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001204: 2300 movs r3, #0
8001206: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct);
+ HAL_GPIO_Init(user_button_GPIO_Port, &GPIO_InitStruct);
8001208: f107 031c add.w r3, r7, #28
800120c: 4619 mov r1, r3
- 800120e: 482c ldr r0, [pc, #176] ; (80012c0 <_ZL12MX_GPIO_Initv+0x19c>)
- 8001210: f000 fd54 bl 8001cbc <HAL_GPIO_Init>
+ 800120e: 4832 ldr r0, [pc, #200] ; (80012d8 <_ZL12MX_GPIO_Initv+0x19c>)
+ 8001210: f000 fd92 bl 8001d38 <HAL_GPIO_Init>
- /*Configure GPIO pin : current1_Pin */
- GPIO_InitStruct.Pin = current1_Pin;
- 8001214: 2308 movs r3, #8
+ /*Configure GPIO pin : current2_Pin */
+ GPIO_InitStruct.Pin = current2_Pin;
+ 8001214: 2301 movs r3, #1
8001216: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001218: 2303 movs r3, #3
GPIO_InitStruct.Pull = GPIO_NOPULL;
800121c: 2300 movs r3, #0
800121e: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct);
+ HAL_GPIO_Init(current2_GPIO_Port, &GPIO_InitStruct);
8001220: f107 031c add.w r3, r7, #28
8001224: 4619 mov r1, r3
- 8001226: 4827 ldr r0, [pc, #156] ; (80012c4 <_ZL12MX_GPIO_Initv+0x1a0>)
- 8001228: f000 fd48 bl 8001cbc <HAL_GPIO_Init>
+ 8001226: 482c ldr r0, [pc, #176] ; (80012d8 <_ZL12MX_GPIO_Initv+0x19c>)
+ 8001228: f000 fd86 bl 8001d38 <HAL_GPIO_Init>
- /*Configure GPIO pin : fault2_Pin */
- GPIO_InitStruct.Pin = fault2_Pin;
- 800122c: 2340 movs r3, #64 ; 0x40
+ /*Configure GPIO pin : current1_Pin */
+ GPIO_InitStruct.Pin = current1_Pin;
+ 800122c: 2308 movs r3, #8
800122e: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001230: 2300 movs r3, #0
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 8001230: 2303 movs r3, #3
8001232: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001234: 2300 movs r3, #0
8001236: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct);
+ HAL_GPIO_Init(current1_GPIO_Port, &GPIO_InitStruct);
8001238: f107 031c add.w r3, r7, #28
800123c: 4619 mov r1, r3
- 800123e: 4821 ldr r0, [pc, #132] ; (80012c4 <_ZL12MX_GPIO_Initv+0x1a0>)
- 8001240: f000 fd3c bl 8001cbc <HAL_GPIO_Init>
+ 800123e: 4827 ldr r0, [pc, #156] ; (80012dc <_ZL12MX_GPIO_Initv+0x1a0>)
+ 8001240: f000 fd7a bl 8001d38 <HAL_GPIO_Init>
+
+ /*Configure GPIO pin : fault2_Pin */
+ GPIO_InitStruct.Pin = fault2_Pin;
+ 8001244: 2340 movs r3, #64 ; 0x40
+ 8001246: 61fb str r3, [r7, #28]
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 8001248: 2300 movs r3, #0
+ 800124a: 623b str r3, [r7, #32]
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800124c: 2300 movs r3, #0
+ 800124e: 627b str r3, [r7, #36] ; 0x24
+ HAL_GPIO_Init(fault2_GPIO_Port, &GPIO_InitStruct);
+ 8001250: f107 031c add.w r3, r7, #28
+ 8001254: 4619 mov r1, r3
+ 8001256: 4821 ldr r0, [pc, #132] ; (80012dc <_ZL12MX_GPIO_Initv+0x1a0>)
+ 8001258: f000 fd6e bl 8001d38 <HAL_GPIO_Init>
/*Configure GPIO pins : dir2_Pin dir1_Pin */
GPIO_InitStruct.Pin = dir2_Pin | dir1_Pin;
- 8001244: f44f 5340 mov.w r3, #12288 ; 0x3000
- 8001248: 61fb str r3, [r7, #28]
+ 800125c: f44f 5340 mov.w r3, #12288 ; 0x3000
+ 8001260: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 800124a: 2301 movs r3, #1
- 800124c: 623b str r3, [r7, #32]
+ 8001262: 2301 movs r3, #1
+ 8001264: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800124e: 2300 movs r3, #0
- 8001250: 627b str r3, [r7, #36] ; 0x24
+ 8001266: 2300 movs r3, #0
+ 8001268: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001252: 2300 movs r3, #0
- 8001254: 62bb str r3, [r7, #40] ; 0x28
+ 800126a: 2300 movs r3, #0
+ 800126c: 62bb str r3, [r7, #40] ; 0x28
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 8001256: f107 031c add.w r3, r7, #28
- 800125a: 4619 mov r1, r3
- 800125c: 4816 ldr r0, [pc, #88] ; (80012b8 <_ZL12MX_GPIO_Initv+0x194>)
- 800125e: f000 fd2d bl 8001cbc <HAL_GPIO_Init>
+ 800126e: f107 031c add.w r3, r7, #28
+ 8001272: 4619 mov r1, r3
+ 8001274: 4816 ldr r0, [pc, #88] ; (80012d0 <_ZL12MX_GPIO_Initv+0x194>)
+ 8001276: f000 fd5f bl 8001d38 <HAL_GPIO_Init>
/*Configure GPIO pins : sleep2_Pin sleep1_Pin */
GPIO_InitStruct.Pin = sleep2_Pin | sleep1_Pin;
- 8001262: f44f 4340 mov.w r3, #49152 ; 0xc000
- 8001266: 61fb str r3, [r7, #28]
+ 800127a: f44f 4340 mov.w r3, #49152 ; 0xc000
+ 800127e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 8001268: 2301 movs r3, #1
- 800126a: 623b str r3, [r7, #32]
+ 8001280: 2301 movs r3, #1
+ 8001282: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_PULLUP;
- 800126c: 2301 movs r3, #1
- 800126e: 627b str r3, [r7, #36] ; 0x24
+ 8001284: 2301 movs r3, #1
+ 8001286: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001270: 2300 movs r3, #0
- 8001272: 62bb str r3, [r7, #40] ; 0x28
+ 8001288: 2300 movs r3, #0
+ 800128a: 62bb str r3, [r7, #40] ; 0x28
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
- 8001274: f107 031c add.w r3, r7, #28
- 8001278: 4619 mov r1, r3
- 800127a: 480f ldr r0, [pc, #60] ; (80012b8 <_ZL12MX_GPIO_Initv+0x194>)
- 800127c: f000 fd1e bl 8001cbc <HAL_GPIO_Init>
+ 800128c: f107 031c add.w r3, r7, #28
+ 8001290: 4619 mov r1, r3
+ 8001292: 480f ldr r0, [pc, #60] ; (80012d0 <_ZL12MX_GPIO_Initv+0x194>)
+ 8001294: f000 fd50 bl 8001d38 <HAL_GPIO_Init>
/*Configure GPIO pin : fault1_Pin */
GPIO_InitStruct.Pin = fault1_Pin;
- 8001280: f44f 7300 mov.w r3, #512 ; 0x200
- 8001284: 61fb str r3, [r7, #28]
+ 8001298: f44f 7300 mov.w r3, #512 ; 0x200
+ 800129c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 8001286: 2300 movs r3, #0
- 8001288: 623b str r3, [r7, #32]
+ 800129e: 2300 movs r3, #0
+ 80012a0: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800128a: 2300 movs r3, #0
- 800128c: 627b str r3, [r7, #36] ; 0x24
+ 80012a2: 2300 movs r3, #0
+ 80012a4: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(fault1_GPIO_Port, &GPIO_InitStruct);
- 800128e: f107 031c add.w r3, r7, #28
- 8001292: 4619 mov r1, r3
- 8001294: 480c ldr r0, [pc, #48] ; (80012c8 <_ZL12MX_GPIO_Initv+0x1a4>)
- 8001296: f000 fd11 bl 8001cbc <HAL_GPIO_Init>
+ 80012a6: f107 031c add.w r3, r7, #28
+ 80012aa: 4619 mov r1, r3
+ 80012ac: 480c ldr r0, [pc, #48] ; (80012e0 <_ZL12MX_GPIO_Initv+0x1a4>)
+ 80012ae: f000 fd43 bl 8001d38 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
- 800129a: 2200 movs r2, #0
- 800129c: 2100 movs r1, #0
- 800129e: 2028 movs r0, #40 ; 0x28
- 80012a0: f000 fcb3 bl 8001c0a <HAL_NVIC_SetPriority>
+ 80012b2: 2200 movs r2, #0
+ 80012b4: 2100 movs r1, #0
+ 80012b6: 2028 movs r0, #40 ; 0x28
+ 80012b8: f000 fce5 bl 8001c86 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
- 80012a4: 2028 movs r0, #40 ; 0x28
- 80012a6: f000 fccc bl 8001c42 <HAL_NVIC_EnableIRQ>
+ 80012bc: 2028 movs r0, #40 ; 0x28
+ 80012be: f000 fcfe bl 8001cbe <HAL_NVIC_EnableIRQ>
}
- 80012aa: bf00 nop
- 80012ac: 3730 adds r7, #48 ; 0x30
- 80012ae: 46bd mov sp, r7
- 80012b0: bd80 pop {r7, pc}
- 80012b2: bf00 nop
- 80012b4: 40023800 .word 0x40023800
- 80012b8: 40021400 .word 0x40021400
- 80012bc: 10110000 .word 0x10110000
- 80012c0: 40020800 .word 0x40020800
- 80012c4: 40020000 .word 0x40020000
- 80012c8: 40021000 .word 0x40021000
-
-080012cc <HAL_TIM_PeriodElapsedCallback>:
+ 80012c2: bf00 nop
+ 80012c4: 3730 adds r7, #48 ; 0x30
+ 80012c6: 46bd mov sp, r7
+ 80012c8: bd80 pop {r7, pc}
+ 80012ca: bf00 nop
+ 80012cc: 40023800 .word 0x40023800
+ 80012d0: 40021400 .word 0x40021400
+ 80012d4: 10110000 .word 0x10110000
+ 80012d8: 40020800 .word 0x40020800
+ 80012dc: 40020000 .word 0x40020000
+ 80012e0: 40021000 .word 0x40021000
+ 80012e4: 00000000 .word 0x00000000
+
+080012e8 <HAL_TIM_PeriodElapsedCallback>:
/* USER CODE BEGIN 4 */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
- 80012cc: b580 push {r7, lr}
- 80012ce: b082 sub sp, #8
- 80012d0: af00 add r7, sp, #0
- 80012d2: 6078 str r0, [r7, #4]
+ 80012e8: b580 push {r7, lr}
+ 80012ea: b082 sub sp, #8
+ 80012ec: af00 add r7, sp, #0
+ 80012ee: 6078 str r0, [r7, #4]
- //TIMER 10Hz PID control
+ //TIMER 100Hz PID control
if (htim->Instance == TIM3) {
- 80012d4: 687b ldr r3, [r7, #4]
- 80012d6: 681b ldr r3, [r3, #0]
- 80012d8: 4a34 ldr r2, [pc, #208] ; (80013ac <HAL_TIM_PeriodElapsedCallback+0xe0>)
- 80012da: 4293 cmp r3, r2
- 80012dc: d11d bne.n 800131a <HAL_TIM_PeriodElapsedCallback+0x4e>
-
-// left_pid.set(1.0);
- right_pid.set(-0.5);
- 80012de: eebe 0a00 vmov.f32 s0, #224 ; 0xbf000000 -0.5
- 80012e2: 4833 ldr r0, [pc, #204] ; (80013b0 <HAL_TIM_PeriodElapsedCallback+0xe4>)
- 80012e4: f7ff fb7a bl 80009dc <_ZN3Pid3setEf>
-
-// left_velocity = left_encoder.GetLinearVelocity();
- right_velocity = right_encoder.GetLinearVelocity();
- 80012e8: 4832 ldr r0, [pc, #200] ; (80013b4 <HAL_TIM_PeriodElapsedCallback+0xe8>)
- 80012ea: f7ff f99f bl 800062c <_ZN7Encoder17GetLinearVelocityEv>
- 80012ee: eef0 7a40 vmov.f32 s15, s0
- 80012f2: 4b31 ldr r3, [pc, #196] ; (80013b8 <HAL_TIM_PeriodElapsedCallback+0xec>)
- 80012f4: edc3 7a00 vstr s15, [r3]
-// left_dutycycle = left_pid.update(left_velocity);
- right_dutycycle = right_pid.update(right_velocity);
- 80012f8: 4b2f ldr r3, [pc, #188] ; (80013b8 <HAL_TIM_PeriodElapsedCallback+0xec>)
- 80012fa: edd3 7a00 vldr s15, [r3]
- 80012fe: eeb0 0a67 vmov.f32 s0, s15
- 8001302: 482b ldr r0, [pc, #172] ; (80013b0 <HAL_TIM_PeriodElapsedCallback+0xe4>)
- 8001304: f7ff fb79 bl 80009fa <_ZN3Pid6updateEf>
- 8001308: 4602 mov r2, r0
- 800130a: 4b2c ldr r3, [pc, #176] ; (80013bc <HAL_TIM_PeriodElapsedCallback+0xf0>)
- 800130c: 601a str r2, [r3, #0]
-
+ 80012f0: 687b ldr r3, [r7, #4]
+ 80012f2: 681b ldr r3, [r3, #0]
+ 80012f4: 4a3c ldr r2, [pc, #240] ; (80013e8 <HAL_TIM_PeriodElapsedCallback+0x100>)
+ 80012f6: 4293 cmp r3, r2
+ 80012f8: d125 bne.n 8001346 <HAL_TIM_PeriodElapsedCallback+0x5e>
// left_motor.set_speed(left_dutycycle);
- right_motor.set_speed(right_dutycycle);
- 800130e: 4b2b ldr r3, [pc, #172] ; (80013bc <HAL_TIM_PeriodElapsedCallback+0xf0>)
- 8001310: 681b ldr r3, [r3, #0]
- 8001312: 4619 mov r1, r3
- 8001314: 482a ldr r0, [pc, #168] ; (80013c0 <HAL_TIM_PeriodElapsedCallback+0xf4>)
- 8001316: f7ff fa54 bl 80007c2 <_ZN15MotorController9set_speedEi>
+// right_motor.set_speed(right_dutycycle);
+//
+// new_time = HAL_GetTick();
+
+ if (state == 0) {
+ 80012fa: 4b3c ldr r3, [pc, #240] ; (80013ec <HAL_TIM_PeriodElapsedCallback+0x104>)
+ 80012fc: 681b ldr r3, [r3, #0]
+ 80012fe: 2b00 cmp r3, #0
+ 8001300: d121 bne.n 8001346 <HAL_TIM_PeriodElapsedCallback+0x5e>
+ left_velocity += 0.01;
+ 8001302: 4b3b ldr r3, [pc, #236] ; (80013f0 <HAL_TIM_PeriodElapsedCallback+0x108>)
+ 8001304: edd3 7a00 vldr s15, [r3]
+ 8001308: eeb7 7ae7 vcvt.f64.f32 d7, s15
+ 800130c: ed9f 6b32 vldr d6, [pc, #200] ; 80013d8 <HAL_TIM_PeriodElapsedCallback+0xf0>
+ 8001310: ee37 7b06 vadd.f64 d7, d7, d6
+ 8001314: eef7 7bc7 vcvt.f32.f64 s15, d7
+ 8001318: 4b35 ldr r3, [pc, #212] ; (80013f0 <HAL_TIM_PeriodElapsedCallback+0x108>)
+ 800131a: edc3 7a00 vstr s15, [r3]
+ right_velocity += 0.1;
+ 800131e: 4b35 ldr r3, [pc, #212] ; (80013f4 <HAL_TIM_PeriodElapsedCallback+0x10c>)
+ 8001320: edd3 7a00 vldr s15, [r3]
+ 8001324: eeb7 7ae7 vcvt.f64.f32 d7, s15
+ 8001328: ed9f 6b2d vldr d6, [pc, #180] ; 80013e0 <HAL_TIM_PeriodElapsedCallback+0xf8>
+ 800132c: ee37 7b06 vadd.f64 d7, d7, d6
+ 8001330: eef7 7bc7 vcvt.f32.f64 s15, d7
+ 8001334: 4b2f ldr r3, [pc, #188] ; (80013f4 <HAL_TIM_PeriodElapsedCallback+0x10c>)
+ 8001336: edc3 7a00 vstr s15, [r3]
+ HAL_UART_Transmit(&huart6, (uint8_t*) &rx_test, 4, 100);
+ 800133a: 2364 movs r3, #100 ; 0x64
+ 800133c: 2204 movs r2, #4
+ 800133e: 492e ldr r1, [pc, #184] ; (80013f8 <HAL_TIM_PeriodElapsedCallback+0x110>)
+ 8001340: 482e ldr r0, [pc, #184] ; (80013fc <HAL_TIM_PeriodElapsedCallback+0x114>)
+ 8001342: f003 f873 bl 800442c <HAL_UART_Transmit>
+ }
+
}
//TIMER 2Hz Transmit
if (htim->Instance == TIM6) {
- 800131a: 687b ldr r3, [r7, #4]
- 800131c: 681b ldr r3, [r3, #0]
- 800131e: 4a29 ldr r2, [pc, #164] ; (80013c4 <HAL_TIM_PeriodElapsedCallback+0xf8>)
- 8001320: 4293 cmp r3, r2
- 8001322: d13f bne.n 80013a4 <HAL_TIM_PeriodElapsedCallback+0xd8>
- if(left_dutycycle >= 790){
- 8001324: 4b28 ldr r3, [pc, #160] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 8001326: 681b ldr r3, [r3, #0]
- 8001328: f240 3215 movw r2, #789 ; 0x315
- 800132c: 4293 cmp r3, r2
- 800132e: dd03 ble.n 8001338 <HAL_TIM_PeriodElapsedCallback+0x6c>
+ 8001346: 687b ldr r3, [r7, #4]
+ 8001348: 681b ldr r3, [r3, #0]
+ 800134a: 4a2d ldr r2, [pc, #180] ; (8001400 <HAL_TIM_PeriodElapsedCallback+0x118>)
+ 800134c: 4293 cmp r3, r2
+ 800134e: d13f bne.n 80013d0 <HAL_TIM_PeriodElapsedCallback+0xe8>
+ if (left_dutycycle >= 790) {
+ 8001350: 4b2c ldr r3, [pc, #176] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 8001352: 681b ldr r3, [r3, #0]
+ 8001354: f240 3215 movw r2, #789 ; 0x315
+ 8001358: 4293 cmp r3, r2
+ 800135a: dd03 ble.n 8001364 <HAL_TIM_PeriodElapsedCallback+0x7c>
flag = false;
- 8001330: 4b26 ldr r3, [pc, #152] ; (80013cc <HAL_TIM_PeriodElapsedCallback+0x100>)
- 8001332: 2200 movs r2, #0
- 8001334: 701a strb r2, [r3, #0]
- 8001336: e008 b.n 800134a <HAL_TIM_PeriodElapsedCallback+0x7e>
- } else if(left_dutycycle <= -790){
- 8001338: 4b23 ldr r3, [pc, #140] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 800133a: 681b ldr r3, [r3, #0]
- 800133c: f46f 7245 mvn.w r2, #788 ; 0x314
- 8001340: 4293 cmp r3, r2
- 8001342: da02 bge.n 800134a <HAL_TIM_PeriodElapsedCallback+0x7e>
+ 800135c: 4b2a ldr r3, [pc, #168] ; (8001408 <HAL_TIM_PeriodElapsedCallback+0x120>)
+ 800135e: 2200 movs r2, #0
+ 8001360: 701a strb r2, [r3, #0]
+ 8001362: e008 b.n 8001376 <HAL_TIM_PeriodElapsedCallback+0x8e>
+ } else if (left_dutycycle <= -790) {
+ 8001364: 4b27 ldr r3, [pc, #156] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 8001366: 681b ldr r3, [r3, #0]
+ 8001368: f46f 7245 mvn.w r2, #788 ; 0x314
+ 800136c: 4293 cmp r3, r2
+ 800136e: da02 bge.n 8001376 <HAL_TIM_PeriodElapsedCallback+0x8e>
flag = true;
- 8001344: 4b21 ldr r3, [pc, #132] ; (80013cc <HAL_TIM_PeriodElapsedCallback+0x100>)
- 8001346: 2201 movs r2, #1
- 8001348: 701a strb r2, [r3, #0]
+ 8001370: 4b25 ldr r3, [pc, #148] ; (8001408 <HAL_TIM_PeriodElapsedCallback+0x120>)
+ 8001372: 2201 movs r2, #1
+ 8001374: 701a strb r2, [r3, #0]
}
left_motor.set_speed(left_dutycycle);
- 800134a: 4b1f ldr r3, [pc, #124] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 800134c: 681b ldr r3, [r3, #0]
- 800134e: 4619 mov r1, r3
- 8001350: 481f ldr r0, [pc, #124] ; (80013d0 <HAL_TIM_PeriodElapsedCallback+0x104>)
- 8001352: f7ff fa36 bl 80007c2 <_ZN15MotorController9set_speedEi>
+ 8001376: 4b23 ldr r3, [pc, #140] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 8001378: 681b ldr r3, [r3, #0]
+ 800137a: 4619 mov r1, r3
+ 800137c: 4823 ldr r0, [pc, #140] ; (800140c <HAL_TIM_PeriodElapsedCallback+0x124>)
+ 800137e: f7ff fa20 bl 80007c2 <_ZN15MotorController9set_speedEi>
odom_msg.angular_velocity = left_dutycycle;
- 8001356: 4b1c ldr r3, [pc, #112] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 8001358: 681b ldr r3, [r3, #0]
- 800135a: ee07 3a90 vmov s15, r3
- 800135e: eef8 7ae7 vcvt.f32.s32 s15, s15
- 8001362: 4b1c ldr r3, [pc, #112] ; (80013d4 <HAL_TIM_PeriodElapsedCallback+0x108>)
- 8001364: edc3 7a00 vstr s15, [r3]
+ 8001382: 4b20 ldr r3, [pc, #128] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 8001384: 681b ldr r3, [r3, #0]
+ 8001386: ee07 3a90 vmov s15, r3
+ 800138a: eef8 7ae7 vcvt.f32.s32 s15, s15
+ 800138e: 4b20 ldr r3, [pc, #128] ; (8001410 <HAL_TIM_PeriodElapsedCallback+0x128>)
+ 8001390: edc3 7a00 vstr s15, [r3]
odom_msg.linear_velocity = left_encoder.GetLinearVelocity();
- 8001368: 481b ldr r0, [pc, #108] ; (80013d8 <HAL_TIM_PeriodElapsedCallback+0x10c>)
- 800136a: f7ff f95f bl 800062c <_ZN7Encoder17GetLinearVelocityEv>
- 800136e: eef0 7a40 vmov.f32 s15, s0
- 8001372: 4b18 ldr r3, [pc, #96] ; (80013d4 <HAL_TIM_PeriodElapsedCallback+0x108>)
- 8001374: edc3 7a01 vstr s15, [r3, #4]
+ 8001394: 481f ldr r0, [pc, #124] ; (8001414 <HAL_TIM_PeriodElapsedCallback+0x12c>)
+ 8001396: f7ff f949 bl 800062c <_ZN7Encoder17GetLinearVelocityEv>
+ 800139a: eef0 7a40 vmov.f32 s15, s0
+ 800139e: 4b1c ldr r3, [pc, #112] ; (8001410 <HAL_TIM_PeriodElapsedCallback+0x128>)
+ 80013a0: edc3 7a01 vstr s15, [r3, #4]
if (flag)
- 8001378: 4b14 ldr r3, [pc, #80] ; (80013cc <HAL_TIM_PeriodElapsedCallback+0x100>)
- 800137a: 781b ldrb r3, [r3, #0]
- 800137c: 2b00 cmp r3, #0
- 800137e: d005 beq.n 800138c <HAL_TIM_PeriodElapsedCallback+0xc0>
+ 80013a4: 4b18 ldr r3, [pc, #96] ; (8001408 <HAL_TIM_PeriodElapsedCallback+0x120>)
+ 80013a6: 781b ldrb r3, [r3, #0]
+ 80013a8: 2b00 cmp r3, #0
+ 80013aa: d005 beq.n 80013b8 <HAL_TIM_PeriodElapsedCallback+0xd0>
left_dutycycle++;
- 8001380: 4b11 ldr r3, [pc, #68] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 8001382: 681b ldr r3, [r3, #0]
- 8001384: 3301 adds r3, #1
- 8001386: 4a10 ldr r2, [pc, #64] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 8001388: 6013 str r3, [r2, #0]
- 800138a: e004 b.n 8001396 <HAL_TIM_PeriodElapsedCallback+0xca>
+ 80013ac: 4b15 ldr r3, [pc, #84] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 80013ae: 681b ldr r3, [r3, #0]
+ 80013b0: 3301 adds r3, #1
+ 80013b2: 4a14 ldr r2, [pc, #80] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 80013b4: 6013 str r3, [r2, #0]
+ 80013b6: e004 b.n 80013c2 <HAL_TIM_PeriodElapsedCallback+0xda>
else
left_dutycycle--;
- 800138c: 4b0e ldr r3, [pc, #56] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 800138e: 681b ldr r3, [r3, #0]
- 8001390: 3b01 subs r3, #1
- 8001392: 4a0d ldr r2, [pc, #52] ; (80013c8 <HAL_TIM_PeriodElapsedCallback+0xfc>)
- 8001394: 6013 str r3, [r2, #0]
+ 80013b8: 4b12 ldr r3, [pc, #72] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 80013ba: 681b ldr r3, [r3, #0]
+ 80013bc: 3b01 subs r3, #1
+ 80013be: 4a11 ldr r2, [pc, #68] ; (8001404 <HAL_TIM_PeriodElapsedCallback+0x11c>)
+ 80013c0: 6013 str r3, [r2, #0]
HAL_UART_Transmit(&huart6, tx_buffer, 8, 100);
- 8001396: 4b11 ldr r3, [pc, #68] ; (80013dc <HAL_TIM_PeriodElapsedCallback+0x110>)
- 8001398: 6819 ldr r1, [r3, #0]
- 800139a: 2364 movs r3, #100 ; 0x64
- 800139c: 2208 movs r2, #8
- 800139e: 4810 ldr r0, [pc, #64] ; (80013e0 <HAL_TIM_PeriodElapsedCallback+0x114>)
- 80013a0: f003 f806 bl 80043b0 <HAL_UART_Transmit>
+ 80013c2: 4b15 ldr r3, [pc, #84] ; (8001418 <HAL_TIM_PeriodElapsedCallback+0x130>)
+ 80013c4: 6819 ldr r1, [r3, #0]
+ 80013c6: 2364 movs r3, #100 ; 0x64
+ 80013c8: 2208 movs r2, #8
+ 80013ca: 480c ldr r0, [pc, #48] ; (80013fc <HAL_TIM_PeriodElapsedCallback+0x114>)
+ 80013cc: f003 f82e bl 800442c <HAL_UART_Transmit>
}
}
- 80013a4: bf00 nop
- 80013a6: 3708 adds r7, #8
- 80013a8: 46bd mov sp, r7
- 80013aa: bd80 pop {r7, pc}
- 80013ac: 40000400 .word 0x40000400
- 80013b0: 200002b4 .word 0x200002b4
- 80013b4: 20000208 .word 0x20000208
- 80013b8: 2000026c .word 0x2000026c
- 80013bc: 20000340 .word 0x20000340
- 80013c0: 2000035c .word 0x2000035c
- 80013c4: 40001000 .word 0x40001000
- 80013c8: 2000033c .word 0x2000033c
- 80013cc: 20000000 .word 0x20000000
- 80013d0: 20000344 .word 0x20000344
- 80013d4: 2000037c .word 0x2000037c
- 80013d8: 200001ec .word 0x200001ec
- 80013dc: 20000374 .word 0x20000374
- 80013e0: 2000016c .word 0x2000016c
-
-080013e4 <HAL_GPIO_EXTI_Callback>:
+ 80013d0: bf00 nop
+ 80013d2: 3708 adds r7, #8
+ 80013d4: 46bd mov sp, r7
+ 80013d6: bd80 pop {r7, pc}
+ 80013d8: 47ae147b .word 0x47ae147b
+ 80013dc: 3f847ae1 .word 0x3f847ae1
+ 80013e0: 9999999a .word 0x9999999a
+ 80013e4: 3fb99999 .word 0x3fb99999
+ 80013e8: 40000400 .word 0x40000400
+ 80013ec: 20000004 .word 0x20000004
+ 80013f0: 20000270 .word 0x20000270
+ 80013f4: 20000274 .word 0x20000274
+ 80013f8: 20000398 .word 0x20000398
+ 80013fc: 20000170 .word 0x20000170
+ 8001400: 40001000 .word 0x40001000
+ 8001404: 20000344 .word 0x20000344
+ 8001408: 20000000 .word 0x20000000
+ 800140c: 2000034c .word 0x2000034c
+ 8001410: 20000384 .word 0x20000384
+ 8001414: 200001f0 .word 0x200001f0
+ 8001418: 2000037c .word 0x2000037c
+
+0800141c <HAL_UART_RxCpltCallback>:
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {
+ 800141c: b580 push {r7, lr}
+ 800141e: b082 sub sp, #8
+ 8001420: af00 add r7, sp, #0
+ 8001422: 6078 str r0, [r7, #4]
+
//abilita interrupt nuovamente
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
+// HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
+
+ //test plot
+ HAL_UART_Receive_IT(&huart6, (uint8_t*) &rx_test, 4);
+ 8001424: 2204 movs r2, #4
+ 8001426: 4904 ldr r1, [pc, #16] ; (8001438 <HAL_UART_RxCpltCallback+0x1c>)
+ 8001428: 4804 ldr r0, [pc, #16] ; (800143c <HAL_UART_RxCpltCallback+0x20>)
+ 800142a: f003 f891 bl 8004550 <HAL_UART_Receive_IT>
}
+ 800142e: bf00 nop
+ 8001430: 3708 adds r7, #8
+ 8001432: 46bd mov sp, r7
+ 8001434: bd80 pop {r7, pc}
+ 8001436: bf00 nop
+ 8001438: 20000398 .word 0x20000398
+ 800143c: 20000170 .word 0x20000170
+
+08001440 <HAL_GPIO_EXTI_Callback>:
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
- 80013e4: b580 push {r7, lr}
- 80013e6: b082 sub sp, #8
- 80013e8: af00 add r7, sp, #0
- 80013ea: 4603 mov r3, r0
- 80013ec: 80fb strh r3, [r7, #6]
+ 8001440: b580 push {r7, lr}
+ 8001442: b082 sub sp, #8
+ 8001444: af00 add r7, sp, #0
+ 8001446: 4603 mov r3, r0
+ 8001448: 80fb strh r3, [r7, #6]
if (GPIO_Pin == GPIO_PIN_13) {
- 80013ee: 88fb ldrh r3, [r7, #6]
- 80013f0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 80013f4: d106 bne.n 8001404 <HAL_GPIO_EXTI_Callback+0x20>
- left_motor.brake();
- 80013f6: 4805 ldr r0, [pc, #20] ; (800140c <HAL_GPIO_EXTI_Callback+0x28>)
- 80013f8: f7ff fa74 bl 80008e4 <_ZN15MotorController5brakeEv>
- right_motor.brake();
- 80013fc: 4804 ldr r0, [pc, #16] ; (8001410 <HAL_GPIO_EXTI_Callback+0x2c>)
- 80013fe: f7ff fa71 bl 80008e4 <_ZN15MotorController5brakeEv>
- while(1){
- 8001402: e7fe b.n 8001402 <HAL_GPIO_EXTI_Callback+0x1e>
-
+ 800144a: 88fb ldrh r3, [r7, #6]
+ 800144c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
+ 8001450: d114 bne.n 800147c <HAL_GPIO_EXTI_Callback+0x3c>
+ if (state == 0) {
+ 8001452: 4b0c ldr r3, [pc, #48] ; (8001484 <HAL_GPIO_EXTI_Callback+0x44>)
+ 8001454: 681b ldr r3, [r3, #0]
+ 8001456: 2b00 cmp r3, #0
+ 8001458: d109 bne.n 800146e <HAL_GPIO_EXTI_Callback+0x2e>
+ state = 1;
+ 800145a: 4b0a ldr r3, [pc, #40] ; (8001484 <HAL_GPIO_EXTI_Callback+0x44>)
+ 800145c: 2201 movs r2, #1
+ 800145e: 601a str r2, [r3, #0]
+ left_motor.brake();
+ 8001460: 4809 ldr r0, [pc, #36] ; (8001488 <HAL_GPIO_EXTI_Callback+0x48>)
+ 8001462: f7ff fac6 bl 80009f2 <_ZN15MotorController5brakeEv>
+ right_motor.brake();
+ 8001466: 4809 ldr r0, [pc, #36] ; (800148c <HAL_GPIO_EXTI_Callback+0x4c>)
+ 8001468: f7ff fac3 bl 80009f2 <_ZN15MotorController5brakeEv>
+ else if (state == 1) {
+ state = 0;
}
+
}
}
- 8001404: bf00 nop
- 8001406: 3708 adds r7, #8
- 8001408: 46bd mov sp, r7
- 800140a: bd80 pop {r7, pc}
- 800140c: 20000344 .word 0x20000344
- 8001410: 2000035c .word 0x2000035c
+ 800146c: e006 b.n 800147c <HAL_GPIO_EXTI_Callback+0x3c>
+ else if (state == 1) {
+ 800146e: 4b05 ldr r3, [pc, #20] ; (8001484 <HAL_GPIO_EXTI_Callback+0x44>)
+ 8001470: 681b ldr r3, [r3, #0]
+ 8001472: 2b01 cmp r3, #1
+ 8001474: d102 bne.n 800147c <HAL_GPIO_EXTI_Callback+0x3c>
+ state = 0;
+ 8001476: 4b03 ldr r3, [pc, #12] ; (8001484 <HAL_GPIO_EXTI_Callback+0x44>)
+ 8001478: 2200 movs r2, #0
+ 800147a: 601a str r2, [r3, #0]
+}
+ 800147c: bf00 nop
+ 800147e: 3708 adds r7, #8
+ 8001480: 46bd mov sp, r7
+ 8001482: bd80 pop {r7, pc}
+ 8001484: 20000004 .word 0x20000004
+ 8001488: 2000034c .word 0x2000034c
+ 800148c: 20000364 .word 0x20000364
-08001414 <Error_Handler>:
+08001490 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void) {
- 8001414: b480 push {r7}
- 8001416: af00 add r7, sp, #0
+ 8001490: b480 push {r7}
+ 8001492: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
- 8001418: bf00 nop
- 800141a: 46bd mov sp, r7
- 800141c: f85d 7b04 ldr.w r7, [sp], #4
- 8001420: 4770 bx lr
+ 8001494: bf00 nop
+ 8001496: 46bd mov sp, r7
+ 8001498: f85d 7b04 ldr.w r7, [sp], #4
+ 800149c: 4770 bx lr
...
-08001424 <_Z41__static_initialization_and_destruction_0ii>:
- 8001424: b5f0 push {r4, r5, r6, r7, lr}
- 8001426: b08f sub sp, #60 ; 0x3c
- 8001428: af0c add r7, sp, #48 ; 0x30
- 800142a: 6078 str r0, [r7, #4]
- 800142c: 6039 str r1, [r7, #0]
- 800142e: 687b ldr r3, [r7, #4]
- 8001430: 2b01 cmp r3, #1
- 8001432: d158 bne.n 80014e6 <_Z41__static_initialization_and_destruction_0ii+0xc2>
- 8001434: 683b ldr r3, [r7, #0]
- 8001436: f64f 72ff movw r2, #65535 ; 0xffff
- 800143a: 4293 cmp r3, r2
- 800143c: d153 bne.n 80014e6 <_Z41__static_initialization_and_destruction_0ii+0xc2>
+080014a0 <_Z41__static_initialization_and_destruction_0ii>:
+ 80014a0: b5f0 push {r4, r5, r6, r7, lr}
+ 80014a2: b08f sub sp, #60 ; 0x3c
+ 80014a4: af0c add r7, sp, #48 ; 0x30
+ 80014a6: 6078 str r0, [r7, #4]
+ 80014a8: 6039 str r1, [r7, #0]
+ 80014aa: 687b ldr r3, [r7, #4]
+ 80014ac: 2b01 cmp r3, #1
+ 80014ae: d158 bne.n 8001562 <_Z41__static_initialization_and_destruction_0ii+0xc2>
+ 80014b0: 683b ldr r3, [r7, #0]
+ 80014b2: f64f 72ff movw r2, #65535 ; 0xffff
+ 80014b6: 4293 cmp r3, r2
+ 80014b8: d153 bne.n 8001562 <_Z41__static_initialization_and_destruction_0ii+0xc2>
Encoder left_encoder = Encoder(&htim5);
- 800143e: 492c ldr r1, [pc, #176] ; (80014f0 <_Z41__static_initialization_and_destruction_0ii+0xcc>)
- 8001440: 482c ldr r0, [pc, #176] ; (80014f4 <_Z41__static_initialization_and_destruction_0ii+0xd0>)
- 8001442: f7ff f8a1 bl 8000588 <_ZN7EncoderC1EP17TIM_HandleTypeDef>
+ 80014ba: 492c ldr r1, [pc, #176] ; (800156c <_Z41__static_initialization_and_destruction_0ii+0xcc>)
+ 80014bc: 482c ldr r0, [pc, #176] ; (8001570 <_Z41__static_initialization_and_destruction_0ii+0xd0>)
+ 80014be: f7ff f863 bl 8000588 <_ZN7EncoderC1EP17TIM_HandleTypeDef>
Encoder right_encoder = Encoder(&htim2);
- 8001446: 492c ldr r1, [pc, #176] ; (80014f8 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
- 8001448: 482c ldr r0, [pc, #176] ; (80014fc <_Z41__static_initialization_and_destruction_0ii+0xd8>)
- 800144a: f7ff f89d bl 8000588 <_ZN7EncoderC1EP17TIM_HandleTypeDef>
+ 80014c2: 492c ldr r1, [pc, #176] ; (8001574 <_Z41__static_initialization_and_destruction_0ii+0xd4>)
+ 80014c4: 482c ldr r0, [pc, #176] ; (8001578 <_Z41__static_initialization_and_destruction_0ii+0xd8>)
+ 80014c6: f7ff f85f bl 8000588 <_ZN7EncoderC1EP17TIM_HandleTypeDef>
Odometry odom = Odometry(left_encoder, right_encoder);
- 800144e: 4e29 ldr r6, [pc, #164] ; (80014f4 <_Z41__static_initialization_and_destruction_0ii+0xd0>)
- 8001450: 4b2a ldr r3, [pc, #168] ; (80014fc <_Z41__static_initialization_and_destruction_0ii+0xd8>)
- 8001452: ac04 add r4, sp, #16
- 8001454: 461d mov r5, r3
- 8001456: cd0f ldmia r5!, {r0, r1, r2, r3}
- 8001458: c40f stmia r4!, {r0, r1, r2, r3}
- 800145a: e895 0007 ldmia.w r5, {r0, r1, r2}
- 800145e: e884 0007 stmia.w r4, {r0, r1, r2}
- 8001462: 466c mov r4, sp
- 8001464: f106 030c add.w r3, r6, #12
- 8001468: cb0f ldmia r3, {r0, r1, r2, r3}
- 800146a: e884 000f stmia.w r4, {r0, r1, r2, r3}
- 800146e: e896 000e ldmia.w r6, {r1, r2, r3}
- 8001472: 4823 ldr r0, [pc, #140] ; (8001500 <_Z41__static_initialization_and_destruction_0ii+0xdc>)
- 8001474: f7ff f940 bl 80006f8 <_ZN8OdometryC1E7EncoderS0_>
-Pid left_pid(100, 10, 0.0);
- 8001478: ed9f 1a22 vldr s2, [pc, #136] ; 8001504 <_Z41__static_initialization_and_destruction_0ii+0xe0>
- 800147c: eef2 0a04 vmov.f32 s1, #36 ; 0x41200000 10.0
- 8001480: ed9f 0a21 vldr s0, [pc, #132] ; 8001508 <_Z41__static_initialization_and_destruction_0ii+0xe4>
- 8001484: 4821 ldr r0, [pc, #132] ; (800150c <_Z41__static_initialization_and_destruction_0ii+0xe8>)
- 8001486: f7ff fa6e bl 8000966 <_ZN3PidC1Efff>
-Pid right_pid(300, 50, 0.0);
- 800148a: ed9f 1a1e vldr s2, [pc, #120] ; 8001504 <_Z41__static_initialization_and_destruction_0ii+0xe0>
- 800148e: eddf 0a20 vldr s1, [pc, #128] ; 8001510 <_Z41__static_initialization_and_destruction_0ii+0xec>
- 8001492: ed9f 0a20 vldr s0, [pc, #128] ; 8001514 <_Z41__static_initialization_and_destruction_0ii+0xf0>
- 8001496: 4820 ldr r0, [pc, #128] ; (8001518 <_Z41__static_initialization_and_destruction_0ii+0xf4>)
- 8001498: f7ff fa65 bl 8000966 <_ZN3PidC1Efff>
+ 80014ca: 4e29 ldr r6, [pc, #164] ; (8001570 <_Z41__static_initialization_and_destruction_0ii+0xd0>)
+ 80014cc: 4b2a ldr r3, [pc, #168] ; (8001578 <_Z41__static_initialization_and_destruction_0ii+0xd8>)
+ 80014ce: ac04 add r4, sp, #16
+ 80014d0: 461d mov r5, r3
+ 80014d2: cd0f ldmia r5!, {r0, r1, r2, r3}
+ 80014d4: c40f stmia r4!, {r0, r1, r2, r3}
+ 80014d6: e895 0007 ldmia.w r5, {r0, r1, r2}
+ 80014da: e884 0007 stmia.w r4, {r0, r1, r2}
+ 80014de: 466c mov r4, sp
+ 80014e0: f106 030c add.w r3, r6, #12
+ 80014e4: cb0f ldmia r3, {r0, r1, r2, r3}
+ 80014e6: e884 000f stmia.w r4, {r0, r1, r2, r3}
+ 80014ea: e896 000e ldmia.w r6, {r1, r2, r3}
+ 80014ee: 4823 ldr r0, [pc, #140] ; (800157c <_Z41__static_initialization_and_destruction_0ii+0xdc>)
+ 80014f0: f7ff f902 bl 80006f8 <_ZN8OdometryC1E7EncoderS0_>
+Pid left_pid(690, 0, 0);
+ 80014f4: ed9f 1a22 vldr s2, [pc, #136] ; 8001580 <_Z41__static_initialization_and_destruction_0ii+0xe0>
+ 80014f8: eddf 0a21 vldr s1, [pc, #132] ; 8001580 <_Z41__static_initialization_and_destruction_0ii+0xe0>
+ 80014fc: ed9f 0a21 vldr s0, [pc, #132] ; 8001584 <_Z41__static_initialization_and_destruction_0ii+0xe4>
+ 8001500: 4821 ldr r0, [pc, #132] ; (8001588 <_Z41__static_initialization_and_destruction_0ii+0xe8>)
+ 8001502: f7ff fab7 bl 8000a74 <_ZN3PidC1Efff>
+Pid right_pid(650, 100, 0.0);
+ 8001506: ed9f 1a1e vldr s2, [pc, #120] ; 8001580 <_Z41__static_initialization_and_destruction_0ii+0xe0>
+ 800150a: eddf 0a20 vldr s1, [pc, #128] ; 800158c <_Z41__static_initialization_and_destruction_0ii+0xec>
+ 800150e: ed9f 0a20 vldr s0, [pc, #128] ; 8001590 <_Z41__static_initialization_and_destruction_0ii+0xf0>
+ 8001512: 4820 ldr r0, [pc, #128] ; (8001594 <_Z41__static_initialization_and_destruction_0ii+0xf4>)
+ 8001514: f7ff faae bl 8000a74 <_ZN3PidC1Efff>
Pid cross_pid(1, 0.1, 0.0);
- 800149c: ed9f 1a19 vldr s2, [pc, #100] ; 8001504 <_Z41__static_initialization_and_destruction_0ii+0xe0>
- 80014a0: eddf 0a1e vldr s1, [pc, #120] ; 800151c <_Z41__static_initialization_and_destruction_0ii+0xf8>
- 80014a4: eeb7 0a00 vmov.f32 s0, #112 ; 0x3f800000 1.0
- 80014a8: 481d ldr r0, [pc, #116] ; (8001520 <_Z41__static_initialization_and_destruction_0ii+0xfc>)
- 80014aa: f7ff fa5c bl 8000966 <_ZN3PidC1Efff>
- TIM_CHANNEL_4);
- 80014ae: 230c movs r3, #12
- 80014b0: 9302 str r3, [sp, #8]
- 80014b2: 4b1c ldr r3, [pc, #112] ; (8001524 <_Z41__static_initialization_and_destruction_0ii+0x100>)
- 80014b4: 9301 str r3, [sp, #4]
- 80014b6: f44f 5300 mov.w r3, #8192 ; 0x2000
- 80014ba: 9300 str r3, [sp, #0]
- 80014bc: 4b1a ldr r3, [pc, #104] ; (8001528 <_Z41__static_initialization_and_destruction_0ii+0x104>)
- 80014be: f44f 4200 mov.w r2, #32768 ; 0x8000
- 80014c2: 4919 ldr r1, [pc, #100] ; (8001528 <_Z41__static_initialization_and_destruction_0ii+0x104>)
- 80014c4: 4819 ldr r0, [pc, #100] ; (800152c <_Z41__static_initialization_and_destruction_0ii+0x108>)
- 80014c6: f7ff f94b bl 8000760 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
- TIM_CHANNEL_3);
- 80014ca: 2308 movs r3, #8
- 80014cc: 9302 str r3, [sp, #8]
- 80014ce: 4b15 ldr r3, [pc, #84] ; (8001524 <_Z41__static_initialization_and_destruction_0ii+0x100>)
- 80014d0: 9301 str r3, [sp, #4]
- 80014d2: f44f 5380 mov.w r3, #4096 ; 0x1000
- 80014d6: 9300 str r3, [sp, #0]
- 80014d8: 4b13 ldr r3, [pc, #76] ; (8001528 <_Z41__static_initialization_and_destruction_0ii+0x104>)
- 80014da: f44f 4280 mov.w r2, #16384 ; 0x4000
- 80014de: 4912 ldr r1, [pc, #72] ; (8001528 <_Z41__static_initialization_and_destruction_0ii+0x104>)
- 80014e0: 4813 ldr r0, [pc, #76] ; (8001530 <_Z41__static_initialization_and_destruction_0ii+0x10c>)
- 80014e2: f7ff f93d bl 8000760 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
+ 8001518: ed9f 1a19 vldr s2, [pc, #100] ; 8001580 <_Z41__static_initialization_and_destruction_0ii+0xe0>
+ 800151c: eddf 0a1e vldr s1, [pc, #120] ; 8001598 <_Z41__static_initialization_and_destruction_0ii+0xf8>
+ 8001520: eeb7 0a00 vmov.f32 s0, #112 ; 0x3f800000 1.0
+ 8001524: 481d ldr r0, [pc, #116] ; (800159c <_Z41__static_initialization_and_destruction_0ii+0xfc>)
+ 8001526: f7ff faa5 bl 8000a74 <_ZN3PidC1Efff>
+ TIM_CHANNEL_4);
+ 800152a: 230c movs r3, #12
+ 800152c: 9302 str r3, [sp, #8]
+ 800152e: 4b1c ldr r3, [pc, #112] ; (80015a0 <_Z41__static_initialization_and_destruction_0ii+0x100>)
+ 8001530: 9301 str r3, [sp, #4]
+ 8001532: f44f 5300 mov.w r3, #8192 ; 0x2000
+ 8001536: 9300 str r3, [sp, #0]
+ 8001538: 4b1a ldr r3, [pc, #104] ; (80015a4 <_Z41__static_initialization_and_destruction_0ii+0x104>)
+ 800153a: f44f 4200 mov.w r2, #32768 ; 0x8000
+ 800153e: 4919 ldr r1, [pc, #100] ; (80015a4 <_Z41__static_initialization_and_destruction_0ii+0x104>)
+ 8001540: 4819 ldr r0, [pc, #100] ; (80015a8 <_Z41__static_initialization_and_destruction_0ii+0x108>)
+ 8001542: f7ff f90d bl 8000760 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
+ TIM_CHANNEL_3);
+ 8001546: 2308 movs r3, #8
+ 8001548: 9302 str r3, [sp, #8]
+ 800154a: 4b15 ldr r3, [pc, #84] ; (80015a0 <_Z41__static_initialization_and_destruction_0ii+0x100>)
+ 800154c: 9301 str r3, [sp, #4]
+ 800154e: f44f 5380 mov.w r3, #4096 ; 0x1000
+ 8001552: 9300 str r3, [sp, #0]
+ 8001554: 4b13 ldr r3, [pc, #76] ; (80015a4 <_Z41__static_initialization_and_destruction_0ii+0x104>)
+ 8001556: f44f 4280 mov.w r2, #16384 ; 0x4000
+ 800155a: 4912 ldr r1, [pc, #72] ; (80015a4 <_Z41__static_initialization_and_destruction_0ii+0x104>)
+ 800155c: 4813 ldr r0, [pc, #76] ; (80015ac <_Z41__static_initialization_and_destruction_0ii+0x10c>)
+ 800155e: f7ff f8ff bl 8000760 <_ZN15MotorControllerC1EP12GPIO_TypeDeftS1_tP17TIM_HandleTypeDefm>
}
- 80014e6: bf00 nop
- 80014e8: 370c adds r7, #12
- 80014ea: 46bd mov sp, r7
- 80014ec: bdf0 pop {r4, r5, r6, r7, pc}
- 80014ee: bf00 nop
- 80014f0: 200000ec .word 0x200000ec
- 80014f4: 200001ec .word 0x200001ec
- 80014f8: 2000002c .word 0x2000002c
- 80014fc: 20000208 .word 0x20000208
- 8001500: 20000224 .word 0x20000224
- 8001504: 00000000 .word 0x00000000
- 8001508: 42c80000 .word 0x42c80000
- 800150c: 20000270 .word 0x20000270
- 8001510: 42480000 .word 0x42480000
- 8001514: 43960000 .word 0x43960000
- 8001518: 200002b4 .word 0x200002b4
- 800151c: 3dcccccd .word 0x3dcccccd
- 8001520: 200002f8 .word 0x200002f8
- 8001524: 200000ac .word 0x200000ac
- 8001528: 40021400 .word 0x40021400
- 800152c: 20000344 .word 0x20000344
- 8001530: 2000035c .word 0x2000035c
-
-08001534 <_GLOBAL__sub_I_htim2>:
- 8001534: b580 push {r7, lr}
- 8001536: af00 add r7, sp, #0
- 8001538: f64f 71ff movw r1, #65535 ; 0xffff
- 800153c: 2001 movs r0, #1
- 800153e: f7ff ff71 bl 8001424 <_Z41__static_initialization_and_destruction_0ii>
- 8001542: bd80 pop {r7, pc}
-
-08001544 <HAL_MspInit>:
+ 8001562: bf00 nop
+ 8001564: 370c adds r7, #12
+ 8001566: 46bd mov sp, r7
+ 8001568: bdf0 pop {r4, r5, r6, r7, pc}
+ 800156a: bf00 nop
+ 800156c: 200000f0 .word 0x200000f0
+ 8001570: 200001f0 .word 0x200001f0
+ 8001574: 20000030 .word 0x20000030
+ 8001578: 2000020c .word 0x2000020c
+ 800157c: 20000228 .word 0x20000228
+ 8001580: 00000000 .word 0x00000000
+ 8001584: 442c8000 .word 0x442c8000
+ 8001588: 20000278 .word 0x20000278
+ 800158c: 42c80000 .word 0x42c80000
+ 8001590: 44228000 .word 0x44228000
+ 8001594: 200002bc .word 0x200002bc
+ 8001598: 3dcccccd .word 0x3dcccccd
+ 800159c: 20000300 .word 0x20000300
+ 80015a0: 200000b0 .word 0x200000b0
+ 80015a4: 40021400 .word 0x40021400
+ 80015a8: 2000034c .word 0x2000034c
+ 80015ac: 20000364 .word 0x20000364
+
+080015b0 <_GLOBAL__sub_I_htim2>:
+ 80015b0: b580 push {r7, lr}
+ 80015b2: af00 add r7, sp, #0
+ 80015b4: f64f 71ff movw r1, #65535 ; 0xffff
+ 80015b8: 2001 movs r0, #1
+ 80015ba: f7ff ff71 bl 80014a0 <_Z41__static_initialization_and_destruction_0ii>
+ 80015be: bd80 pop {r7, pc}
+
+080015c0 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
- 8001544: b480 push {r7}
- 8001546: b083 sub sp, #12
- 8001548: af00 add r7, sp, #0
+ 80015c0: b480 push {r7}
+ 80015c2: b083 sub sp, #12
+ 80015c4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
- 800154a: 4b0f ldr r3, [pc, #60] ; (8001588 <HAL_MspInit+0x44>)
- 800154c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800154e: 4a0e ldr r2, [pc, #56] ; (8001588 <HAL_MspInit+0x44>)
- 8001550: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8001554: 6413 str r3, [r2, #64] ; 0x40
- 8001556: 4b0c ldr r3, [pc, #48] ; (8001588 <HAL_MspInit+0x44>)
- 8001558: 6c1b ldr r3, [r3, #64] ; 0x40
- 800155a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 800155e: 607b str r3, [r7, #4]
- 8001560: 687b ldr r3, [r7, #4]
+ 80015c6: 4b0f ldr r3, [pc, #60] ; (8001604 <HAL_MspInit+0x44>)
+ 80015c8: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80015ca: 4a0e ldr r2, [pc, #56] ; (8001604 <HAL_MspInit+0x44>)
+ 80015cc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 80015d0: 6413 str r3, [r2, #64] ; 0x40
+ 80015d2: 4b0c ldr r3, [pc, #48] ; (8001604 <HAL_MspInit+0x44>)
+ 80015d4: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80015d6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 80015da: 607b str r3, [r7, #4]
+ 80015dc: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 8001562: 4b09 ldr r3, [pc, #36] ; (8001588 <HAL_MspInit+0x44>)
- 8001564: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001566: 4a08 ldr r2, [pc, #32] ; (8001588 <HAL_MspInit+0x44>)
- 8001568: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 800156c: 6453 str r3, [r2, #68] ; 0x44
- 800156e: 4b06 ldr r3, [pc, #24] ; (8001588 <HAL_MspInit+0x44>)
- 8001570: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001572: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8001576: 603b str r3, [r7, #0]
- 8001578: 683b ldr r3, [r7, #0]
+ 80015de: 4b09 ldr r3, [pc, #36] ; (8001604 <HAL_MspInit+0x44>)
+ 80015e0: 6c5b ldr r3, [r3, #68] ; 0x44
+ 80015e2: 4a08 ldr r2, [pc, #32] ; (8001604 <HAL_MspInit+0x44>)
+ 80015e4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 80015e8: 6453 str r3, [r2, #68] ; 0x44
+ 80015ea: 4b06 ldr r3, [pc, #24] ; (8001604 <HAL_MspInit+0x44>)
+ 80015ec: 6c5b ldr r3, [r3, #68] ; 0x44
+ 80015ee: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 80015f2: 603b str r3, [r7, #0]
+ 80015f4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
- 800157a: bf00 nop
- 800157c: 370c adds r7, #12
- 800157e: 46bd mov sp, r7
- 8001580: f85d 7b04 ldr.w r7, [sp], #4
- 8001584: 4770 bx lr
- 8001586: bf00 nop
- 8001588: 40023800 .word 0x40023800
-
-0800158c <HAL_TIM_Encoder_MspInit>:
+ 80015f6: bf00 nop
+ 80015f8: 370c adds r7, #12
+ 80015fa: 46bd mov sp, r7
+ 80015fc: f85d 7b04 ldr.w r7, [sp], #4
+ 8001600: 4770 bx lr
+ 8001602: bf00 nop
+ 8001604: 40023800 .word 0x40023800
+
+08001608 <HAL_TIM_Encoder_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_encoder: TIM_Encoder handle pointer
* @retval None
*/
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
{
- 800158c: b580 push {r7, lr}
- 800158e: b08c sub sp, #48 ; 0x30
- 8001590: af00 add r7, sp, #0
- 8001592: 6078 str r0, [r7, #4]
+ 8001608: b580 push {r7, lr}
+ 800160a: b08c sub sp, #48 ; 0x30
+ 800160c: af00 add r7, sp, #0
+ 800160e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001594: f107 031c add.w r3, r7, #28
- 8001598: 2200 movs r2, #0
- 800159a: 601a str r2, [r3, #0]
- 800159c: 605a str r2, [r3, #4]
- 800159e: 609a str r2, [r3, #8]
- 80015a0: 60da str r2, [r3, #12]
- 80015a2: 611a str r2, [r3, #16]
+ 8001610: f107 031c add.w r3, r7, #28
+ 8001614: 2200 movs r2, #0
+ 8001616: 601a str r2, [r3, #0]
+ 8001618: 605a str r2, [r3, #4]
+ 800161a: 609a str r2, [r3, #8]
+ 800161c: 60da str r2, [r3, #12]
+ 800161e: 611a str r2, [r3, #16]
if(htim_encoder->Instance==TIM2)
- 80015a4: 687b ldr r3, [r7, #4]
- 80015a6: 681b ldr r3, [r3, #0]
- 80015a8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 80015ac: d144 bne.n 8001638 <HAL_TIM_Encoder_MspInit+0xac>
+ 8001620: 687b ldr r3, [r7, #4]
+ 8001622: 681b ldr r3, [r3, #0]
+ 8001624: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 8001628: d144 bne.n 80016b4 <HAL_TIM_Encoder_MspInit+0xac>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
- 80015ae: 4b3b ldr r3, [pc, #236] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015b0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80015b2: 4a3a ldr r2, [pc, #232] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015b4: f043 0301 orr.w r3, r3, #1
- 80015b8: 6413 str r3, [r2, #64] ; 0x40
- 80015ba: 4b38 ldr r3, [pc, #224] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015bc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80015be: f003 0301 and.w r3, r3, #1
- 80015c2: 61bb str r3, [r7, #24]
- 80015c4: 69bb ldr r3, [r7, #24]
+ 800162a: 4b3b ldr r3, [pc, #236] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 800162c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800162e: 4a3a ldr r2, [pc, #232] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001630: f043 0301 orr.w r3, r3, #1
+ 8001634: 6413 str r3, [r2, #64] ; 0x40
+ 8001636: 4b38 ldr r3, [pc, #224] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001638: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800163a: f003 0301 and.w r3, r3, #1
+ 800163e: 61bb str r3, [r7, #24]
+ 8001640: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOA_CLK_ENABLE();
- 80015c6: 4b35 ldr r3, [pc, #212] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015c8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80015ca: 4a34 ldr r2, [pc, #208] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015cc: f043 0301 orr.w r3, r3, #1
- 80015d0: 6313 str r3, [r2, #48] ; 0x30
- 80015d2: 4b32 ldr r3, [pc, #200] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015d4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80015d6: f003 0301 and.w r3, r3, #1
- 80015da: 617b str r3, [r7, #20]
- 80015dc: 697b ldr r3, [r7, #20]
+ 8001642: 4b35 ldr r3, [pc, #212] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001644: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001646: 4a34 ldr r2, [pc, #208] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001648: f043 0301 orr.w r3, r3, #1
+ 800164c: 6313 str r3, [r2, #48] ; 0x30
+ 800164e: 4b32 ldr r3, [pc, #200] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001650: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001652: f003 0301 and.w r3, r3, #1
+ 8001656: 617b str r3, [r7, #20]
+ 8001658: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOB_CLK_ENABLE();
- 80015de: 4b2f ldr r3, [pc, #188] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015e0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80015e2: 4a2e ldr r2, [pc, #184] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015e4: f043 0302 orr.w r3, r3, #2
- 80015e8: 6313 str r3, [r2, #48] ; 0x30
- 80015ea: 4b2c ldr r3, [pc, #176] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 80015ec: 6b1b ldr r3, [r3, #48] ; 0x30
- 80015ee: f003 0302 and.w r3, r3, #2
- 80015f2: 613b str r3, [r7, #16]
- 80015f4: 693b ldr r3, [r7, #16]
+ 800165a: 4b2f ldr r3, [pc, #188] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 800165c: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800165e: 4a2e ldr r2, [pc, #184] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001660: f043 0302 orr.w r3, r3, #2
+ 8001664: 6313 str r3, [r2, #48] ; 0x30
+ 8001666: 4b2c ldr r3, [pc, #176] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 8001668: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800166a: f003 0302 and.w r3, r3, #2
+ 800166e: 613b str r3, [r7, #16]
+ 8001670: 693b ldr r3, [r7, #16]
/**TIM2 GPIO Configuration
PA5 ------> TIM2_CH1
PB3 ------> TIM2_CH2
*/
GPIO_InitStruct.Pin = encoder_dx1_Pin;
- 80015f6: 2320 movs r3, #32
- 80015f8: 61fb str r3, [r7, #28]
+ 8001672: 2320 movs r3, #32
+ 8001674: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80015fa: 2302 movs r3, #2
- 80015fc: 623b str r3, [r7, #32]
+ 8001676: 2302 movs r3, #2
+ 8001678: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80015fe: 2300 movs r3, #0
- 8001600: 627b str r3, [r7, #36] ; 0x24
+ 800167a: 2300 movs r3, #0
+ 800167c: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001602: 2300 movs r3, #0
- 8001604: 62bb str r3, [r7, #40] ; 0x28
+ 800167e: 2300 movs r3, #0
+ 8001680: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 8001606: 2301 movs r3, #1
- 8001608: 62fb str r3, [r7, #44] ; 0x2c
+ 8001682: 2301 movs r3, #1
+ 8001684: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(encoder_dx1_GPIO_Port, &GPIO_InitStruct);
- 800160a: f107 031c add.w r3, r7, #28
- 800160e: 4619 mov r1, r3
- 8001610: 4823 ldr r0, [pc, #140] ; (80016a0 <HAL_TIM_Encoder_MspInit+0x114>)
- 8001612: f000 fb53 bl 8001cbc <HAL_GPIO_Init>
+ 8001686: f107 031c add.w r3, r7, #28
+ 800168a: 4619 mov r1, r3
+ 800168c: 4823 ldr r0, [pc, #140] ; (800171c <HAL_TIM_Encoder_MspInit+0x114>)
+ 800168e: f000 fb53 bl 8001d38 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = encoder_dx2_Pin;
- 8001616: 2308 movs r3, #8
- 8001618: 61fb str r3, [r7, #28]
+ 8001692: 2308 movs r3, #8
+ 8001694: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800161a: 2302 movs r3, #2
- 800161c: 623b str r3, [r7, #32]
+ 8001696: 2302 movs r3, #2
+ 8001698: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800161e: 2300 movs r3, #0
- 8001620: 627b str r3, [r7, #36] ; 0x24
+ 800169a: 2300 movs r3, #0
+ 800169c: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001622: 2300 movs r3, #0
- 8001624: 62bb str r3, [r7, #40] ; 0x28
+ 800169e: 2300 movs r3, #0
+ 80016a0: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
- 8001626: 2301 movs r3, #1
- 8001628: 62fb str r3, [r7, #44] ; 0x2c
+ 80016a2: 2301 movs r3, #1
+ 80016a4: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(encoder_dx2_GPIO_Port, &GPIO_InitStruct);
- 800162a: f107 031c add.w r3, r7, #28
- 800162e: 4619 mov r1, r3
- 8001630: 481c ldr r0, [pc, #112] ; (80016a4 <HAL_TIM_Encoder_MspInit+0x118>)
- 8001632: f000 fb43 bl 8001cbc <HAL_GPIO_Init>
+ 80016a6: f107 031c add.w r3, r7, #28
+ 80016aa: 4619 mov r1, r3
+ 80016ac: 481c ldr r0, [pc, #112] ; (8001720 <HAL_TIM_Encoder_MspInit+0x118>)
+ 80016ae: f000 fb43 bl 8001d38 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM5_MspInit 1 */
/* USER CODE END TIM5_MspInit 1 */
}
}
- 8001636: e02c b.n 8001692 <HAL_TIM_Encoder_MspInit+0x106>
+ 80016b2: e02c b.n 800170e <HAL_TIM_Encoder_MspInit+0x106>
else if(htim_encoder->Instance==TIM5)
- 8001638: 687b ldr r3, [r7, #4]
- 800163a: 681b ldr r3, [r3, #0]
- 800163c: 4a1a ldr r2, [pc, #104] ; (80016a8 <HAL_TIM_Encoder_MspInit+0x11c>)
- 800163e: 4293 cmp r3, r2
- 8001640: d127 bne.n 8001692 <HAL_TIM_Encoder_MspInit+0x106>
+ 80016b4: 687b ldr r3, [r7, #4]
+ 80016b6: 681b ldr r3, [r3, #0]
+ 80016b8: 4a1a ldr r2, [pc, #104] ; (8001724 <HAL_TIM_Encoder_MspInit+0x11c>)
+ 80016ba: 4293 cmp r3, r2
+ 80016bc: d127 bne.n 800170e <HAL_TIM_Encoder_MspInit+0x106>
__HAL_RCC_TIM5_CLK_ENABLE();
- 8001642: 4b16 ldr r3, [pc, #88] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 8001644: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001646: 4a15 ldr r2, [pc, #84] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 8001648: f043 0308 orr.w r3, r3, #8
- 800164c: 6413 str r3, [r2, #64] ; 0x40
- 800164e: 4b13 ldr r3, [pc, #76] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 8001650: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001652: f003 0308 and.w r3, r3, #8
- 8001656: 60fb str r3, [r7, #12]
- 8001658: 68fb ldr r3, [r7, #12]
+ 80016be: 4b16 ldr r3, [pc, #88] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 80016c0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80016c2: 4a15 ldr r2, [pc, #84] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 80016c4: f043 0308 orr.w r3, r3, #8
+ 80016c8: 6413 str r3, [r2, #64] ; 0x40
+ 80016ca: 4b13 ldr r3, [pc, #76] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 80016cc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80016ce: f003 0308 and.w r3, r3, #8
+ 80016d2: 60fb str r3, [r7, #12]
+ 80016d4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
- 800165a: 4b10 ldr r3, [pc, #64] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 800165c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800165e: 4a0f ldr r2, [pc, #60] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 8001660: f043 0301 orr.w r3, r3, #1
- 8001664: 6313 str r3, [r2, #48] ; 0x30
- 8001666: 4b0d ldr r3, [pc, #52] ; (800169c <HAL_TIM_Encoder_MspInit+0x110>)
- 8001668: 6b1b ldr r3, [r3, #48] ; 0x30
- 800166a: f003 0301 and.w r3, r3, #1
- 800166e: 60bb str r3, [r7, #8]
- 8001670: 68bb ldr r3, [r7, #8]
+ 80016d6: 4b10 ldr r3, [pc, #64] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 80016d8: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80016da: 4a0f ldr r2, [pc, #60] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 80016dc: f043 0301 orr.w r3, r3, #1
+ 80016e0: 6313 str r3, [r2, #48] ; 0x30
+ 80016e2: 4b0d ldr r3, [pc, #52] ; (8001718 <HAL_TIM_Encoder_MspInit+0x110>)
+ 80016e4: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80016e6: f003 0301 and.w r3, r3, #1
+ 80016ea: 60bb str r3, [r7, #8]
+ 80016ec: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = encoder_sx1_Pin|encoder_sx2_Pin;
- 8001672: 2303 movs r3, #3
- 8001674: 61fb str r3, [r7, #28]
+ 80016ee: 2303 movs r3, #3
+ 80016f0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001676: 2302 movs r3, #2
- 8001678: 623b str r3, [r7, #32]
+ 80016f2: 2302 movs r3, #2
+ 80016f4: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800167a: 2300 movs r3, #0
- 800167c: 627b str r3, [r7, #36] ; 0x24
+ 80016f6: 2300 movs r3, #0
+ 80016f8: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 800167e: 2300 movs r3, #0
- 8001680: 62bb str r3, [r7, #40] ; 0x28
+ 80016fa: 2300 movs r3, #0
+ 80016fc: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
- 8001682: 2302 movs r3, #2
- 8001684: 62fb str r3, [r7, #44] ; 0x2c
+ 80016fe: 2302 movs r3, #2
+ 8001700: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8001686: f107 031c add.w r3, r7, #28
- 800168a: 4619 mov r1, r3
- 800168c: 4804 ldr r0, [pc, #16] ; (80016a0 <HAL_TIM_Encoder_MspInit+0x114>)
- 800168e: f000 fb15 bl 8001cbc <HAL_GPIO_Init>
+ 8001702: f107 031c add.w r3, r7, #28
+ 8001706: 4619 mov r1, r3
+ 8001708: 4804 ldr r0, [pc, #16] ; (800171c <HAL_TIM_Encoder_MspInit+0x114>)
+ 800170a: f000 fb15 bl 8001d38 <HAL_GPIO_Init>
}
- 8001692: bf00 nop
- 8001694: 3730 adds r7, #48 ; 0x30
- 8001696: 46bd mov sp, r7
- 8001698: bd80 pop {r7, pc}
- 800169a: bf00 nop
- 800169c: 40023800 .word 0x40023800
- 80016a0: 40020000 .word 0x40020000
- 80016a4: 40020400 .word 0x40020400
- 80016a8: 40000c00 .word 0x40000c00
-
-080016ac <HAL_TIM_Base_MspInit>:
+ 800170e: bf00 nop
+ 8001710: 3730 adds r7, #48 ; 0x30
+ 8001712: 46bd mov sp, r7
+ 8001714: bd80 pop {r7, pc}
+ 8001716: bf00 nop
+ 8001718: 40023800 .word 0x40023800
+ 800171c: 40020000 .word 0x40020000
+ 8001720: 40020400 .word 0x40020400
+ 8001724: 40000c00 .word 0x40000c00
+
+08001728 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
- 80016ac: b480 push {r7}
- 80016ae: b087 sub sp, #28
- 80016b0: af00 add r7, sp, #0
- 80016b2: 6078 str r0, [r7, #4]
+ 8001728: b480 push {r7}
+ 800172a: b087 sub sp, #28
+ 800172c: af00 add r7, sp, #0
+ 800172e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM3)
- 80016b4: 687b ldr r3, [r7, #4]
- 80016b6: 681b ldr r3, [r3, #0]
- 80016b8: 4a1c ldr r2, [pc, #112] ; (800172c <HAL_TIM_Base_MspInit+0x80>)
- 80016ba: 4293 cmp r3, r2
- 80016bc: d10c bne.n 80016d8 <HAL_TIM_Base_MspInit+0x2c>
+ 8001730: 687b ldr r3, [r7, #4]
+ 8001732: 681b ldr r3, [r3, #0]
+ 8001734: 4a1c ldr r2, [pc, #112] ; (80017a8 <HAL_TIM_Base_MspInit+0x80>)
+ 8001736: 4293 cmp r3, r2
+ 8001738: d10c bne.n 8001754 <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
- 80016be: 4b1c ldr r3, [pc, #112] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 80016c0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80016c2: 4a1b ldr r2, [pc, #108] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 80016c4: f043 0302 orr.w r3, r3, #2
- 80016c8: 6413 str r3, [r2, #64] ; 0x40
- 80016ca: 4b19 ldr r3, [pc, #100] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 80016cc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80016ce: f003 0302 and.w r3, r3, #2
- 80016d2: 617b str r3, [r7, #20]
- 80016d4: 697b ldr r3, [r7, #20]
+ 800173a: 4b1c ldr r3, [pc, #112] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 800173c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800173e: 4a1b ldr r2, [pc, #108] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 8001740: f043 0302 orr.w r3, r3, #2
+ 8001744: 6413 str r3, [r2, #64] ; 0x40
+ 8001746: 4b19 ldr r3, [pc, #100] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 8001748: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800174a: f003 0302 and.w r3, r3, #2
+ 800174e: 617b str r3, [r7, #20]
+ 8001750: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN TIM6_MspInit 1 */
/* USER CODE END TIM6_MspInit 1 */
}
}
- 80016d6: e022 b.n 800171e <HAL_TIM_Base_MspInit+0x72>
+ 8001752: e022 b.n 800179a <HAL_TIM_Base_MspInit+0x72>
else if(htim_base->Instance==TIM4)
- 80016d8: 687b ldr r3, [r7, #4]
- 80016da: 681b ldr r3, [r3, #0]
- 80016dc: 4a15 ldr r2, [pc, #84] ; (8001734 <HAL_TIM_Base_MspInit+0x88>)
- 80016de: 4293 cmp r3, r2
- 80016e0: d10c bne.n 80016fc <HAL_TIM_Base_MspInit+0x50>
+ 8001754: 687b ldr r3, [r7, #4]
+ 8001756: 681b ldr r3, [r3, #0]
+ 8001758: 4a15 ldr r2, [pc, #84] ; (80017b0 <HAL_TIM_Base_MspInit+0x88>)
+ 800175a: 4293 cmp r3, r2
+ 800175c: d10c bne.n 8001778 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM4_CLK_ENABLE();
- 80016e2: 4b13 ldr r3, [pc, #76] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 80016e4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80016e6: 4a12 ldr r2, [pc, #72] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 80016e8: f043 0304 orr.w r3, r3, #4
- 80016ec: 6413 str r3, [r2, #64] ; 0x40
- 80016ee: 4b10 ldr r3, [pc, #64] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 80016f0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80016f2: f003 0304 and.w r3, r3, #4
- 80016f6: 613b str r3, [r7, #16]
- 80016f8: 693b ldr r3, [r7, #16]
+ 800175e: 4b13 ldr r3, [pc, #76] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 8001760: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001762: 4a12 ldr r2, [pc, #72] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 8001764: f043 0304 orr.w r3, r3, #4
+ 8001768: 6413 str r3, [r2, #64] ; 0x40
+ 800176a: 4b10 ldr r3, [pc, #64] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 800176c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800176e: f003 0304 and.w r3, r3, #4
+ 8001772: 613b str r3, [r7, #16]
+ 8001774: 693b ldr r3, [r7, #16]
}
- 80016fa: e010 b.n 800171e <HAL_TIM_Base_MspInit+0x72>
+ 8001776: e010 b.n 800179a <HAL_TIM_Base_MspInit+0x72>
else if(htim_base->Instance==TIM6)
- 80016fc: 687b ldr r3, [r7, #4]
- 80016fe: 681b ldr r3, [r3, #0]
- 8001700: 4a0d ldr r2, [pc, #52] ; (8001738 <HAL_TIM_Base_MspInit+0x8c>)
- 8001702: 4293 cmp r3, r2
- 8001704: d10b bne.n 800171e <HAL_TIM_Base_MspInit+0x72>
+ 8001778: 687b ldr r3, [r7, #4]
+ 800177a: 681b ldr r3, [r3, #0]
+ 800177c: 4a0d ldr r2, [pc, #52] ; (80017b4 <HAL_TIM_Base_MspInit+0x8c>)
+ 800177e: 4293 cmp r3, r2
+ 8001780: d10b bne.n 800179a <HAL_TIM_Base_MspInit+0x72>
__HAL_RCC_TIM6_CLK_ENABLE();
- 8001706: 4b0a ldr r3, [pc, #40] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 8001708: 6c1b ldr r3, [r3, #64] ; 0x40
- 800170a: 4a09 ldr r2, [pc, #36] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 800170c: f043 0310 orr.w r3, r3, #16
- 8001710: 6413 str r3, [r2, #64] ; 0x40
- 8001712: 4b07 ldr r3, [pc, #28] ; (8001730 <HAL_TIM_Base_MspInit+0x84>)
- 8001714: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001716: f003 0310 and.w r3, r3, #16
- 800171a: 60fb str r3, [r7, #12]
- 800171c: 68fb ldr r3, [r7, #12]
+ 8001782: 4b0a ldr r3, [pc, #40] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 8001784: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001786: 4a09 ldr r2, [pc, #36] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 8001788: f043 0310 orr.w r3, r3, #16
+ 800178c: 6413 str r3, [r2, #64] ; 0x40
+ 800178e: 4b07 ldr r3, [pc, #28] ; (80017ac <HAL_TIM_Base_MspInit+0x84>)
+ 8001790: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001792: f003 0310 and.w r3, r3, #16
+ 8001796: 60fb str r3, [r7, #12]
+ 8001798: 68fb ldr r3, [r7, #12]
}
- 800171e: bf00 nop
- 8001720: 371c adds r7, #28
- 8001722: 46bd mov sp, r7
- 8001724: f85d 7b04 ldr.w r7, [sp], #4
- 8001728: 4770 bx lr
- 800172a: bf00 nop
- 800172c: 40000400 .word 0x40000400
- 8001730: 40023800 .word 0x40023800
- 8001734: 40000800 .word 0x40000800
- 8001738: 40001000 .word 0x40001000
-
-0800173c <HAL_TIM_MspPostInit>:
+ 800179a: bf00 nop
+ 800179c: 371c adds r7, #28
+ 800179e: 46bd mov sp, r7
+ 80017a0: f85d 7b04 ldr.w r7, [sp], #4
+ 80017a4: 4770 bx lr
+ 80017a6: bf00 nop
+ 80017a8: 40000400 .word 0x40000400
+ 80017ac: 40023800 .word 0x40023800
+ 80017b0: 40000800 .word 0x40000800
+ 80017b4: 40001000 .word 0x40001000
+
+080017b8 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
- 800173c: b580 push {r7, lr}
- 800173e: b088 sub sp, #32
- 8001740: af00 add r7, sp, #0
- 8001742: 6078 str r0, [r7, #4]
+ 80017b8: b580 push {r7, lr}
+ 80017ba: b088 sub sp, #32
+ 80017bc: af00 add r7, sp, #0
+ 80017be: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8001744: f107 030c add.w r3, r7, #12
- 8001748: 2200 movs r2, #0
- 800174a: 601a str r2, [r3, #0]
- 800174c: 605a str r2, [r3, #4]
- 800174e: 609a str r2, [r3, #8]
- 8001750: 60da str r2, [r3, #12]
- 8001752: 611a str r2, [r3, #16]
+ 80017c0: f107 030c add.w r3, r7, #12
+ 80017c4: 2200 movs r2, #0
+ 80017c6: 601a str r2, [r3, #0]
+ 80017c8: 605a str r2, [r3, #4]
+ 80017ca: 609a str r2, [r3, #8]
+ 80017cc: 60da str r2, [r3, #12]
+ 80017ce: 611a str r2, [r3, #16]
if(htim->Instance==TIM4)
- 8001754: 687b ldr r3, [r7, #4]
- 8001756: 681b ldr r3, [r3, #0]
- 8001758: 4a11 ldr r2, [pc, #68] ; (80017a0 <HAL_TIM_MspPostInit+0x64>)
- 800175a: 4293 cmp r3, r2
- 800175c: d11c bne.n 8001798 <HAL_TIM_MspPostInit+0x5c>
+ 80017d0: 687b ldr r3, [r7, #4]
+ 80017d2: 681b ldr r3, [r3, #0]
+ 80017d4: 4a11 ldr r2, [pc, #68] ; (800181c <HAL_TIM_MspPostInit+0x64>)
+ 80017d6: 4293 cmp r3, r2
+ 80017d8: d11c bne.n 8001814 <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM4_MspPostInit 0 */
/* USER CODE END TIM4_MspPostInit 0 */
__HAL_RCC_GPIOD_CLK_ENABLE();
- 800175e: 4b11 ldr r3, [pc, #68] ; (80017a4 <HAL_TIM_MspPostInit+0x68>)
- 8001760: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001762: 4a10 ldr r2, [pc, #64] ; (80017a4 <HAL_TIM_MspPostInit+0x68>)
- 8001764: f043 0308 orr.w r3, r3, #8
- 8001768: 6313 str r3, [r2, #48] ; 0x30
- 800176a: 4b0e ldr r3, [pc, #56] ; (80017a4 <HAL_TIM_MspPostInit+0x68>)
- 800176c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800176e: f003 0308 and.w r3, r3, #8
- 8001772: 60bb str r3, [r7, #8]
- 8001774: 68bb ldr r3, [r7, #8]
+ 80017da: 4b11 ldr r3, [pc, #68] ; (8001820 <HAL_TIM_MspPostInit+0x68>)
+ 80017dc: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80017de: 4a10 ldr r2, [pc, #64] ; (8001820 <HAL_TIM_MspPostInit+0x68>)
+ 80017e0: f043 0308 orr.w r3, r3, #8
+ 80017e4: 6313 str r3, [r2, #48] ; 0x30
+ 80017e6: 4b0e ldr r3, [pc, #56] ; (8001820 <HAL_TIM_MspPostInit+0x68>)
+ 80017e8: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80017ea: f003 0308 and.w r3, r3, #8
+ 80017ee: 60bb str r3, [r7, #8]
+ 80017f0: 68bb ldr r3, [r7, #8]
/**TIM4 GPIO Configuration
PD14 ------> TIM4_CH3
PD15 ------> TIM4_CH4
*/
GPIO_InitStruct.Pin = pwm2_Pin|pwm1_Pin;
- 8001776: f44f 4340 mov.w r3, #49152 ; 0xc000
- 800177a: 60fb str r3, [r7, #12]
+ 80017f2: f44f 4340 mov.w r3, #49152 ; 0xc000
+ 80017f6: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800177c: 2302 movs r3, #2
- 800177e: 613b str r3, [r7, #16]
+ 80017f8: 2302 movs r3, #2
+ 80017fa: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001780: 2300 movs r3, #0
- 8001782: 617b str r3, [r7, #20]
+ 80017fc: 2300 movs r3, #0
+ 80017fe: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8001784: 2300 movs r3, #0
- 8001786: 61bb str r3, [r7, #24]
+ 8001800: 2300 movs r3, #0
+ 8001802: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
- 8001788: 2302 movs r3, #2
- 800178a: 61fb str r3, [r7, #28]
+ 8001804: 2302 movs r3, #2
+ 8001806: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
- 800178c: f107 030c add.w r3, r7, #12
- 8001790: 4619 mov r1, r3
- 8001792: 4805 ldr r0, [pc, #20] ; (80017a8 <HAL_TIM_MspPostInit+0x6c>)
- 8001794: f000 fa92 bl 8001cbc <HAL_GPIO_Init>
+ 8001808: f107 030c add.w r3, r7, #12
+ 800180c: 4619 mov r1, r3
+ 800180e: 4805 ldr r0, [pc, #20] ; (8001824 <HAL_TIM_MspPostInit+0x6c>)
+ 8001810: f000 fa92 bl 8001d38 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
- 8001798: bf00 nop
- 800179a: 3720 adds r7, #32
- 800179c: 46bd mov sp, r7
- 800179e: bd80 pop {r7, pc}
- 80017a0: 40000800 .word 0x40000800
- 80017a4: 40023800 .word 0x40023800
- 80017a8: 40020c00 .word 0x40020c00
-
-080017ac <HAL_UART_MspInit>:
+ 8001814: bf00 nop
+ 8001816: 3720 adds r7, #32
+ 8001818: 46bd mov sp, r7
+ 800181a: bd80 pop {r7, pc}
+ 800181c: 40000800 .word 0x40000800
+ 8001820: 40023800 .word 0x40023800
+ 8001824: 40020c00 .word 0x40020c00
+
+08001828 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
- 80017ac: b580 push {r7, lr}
- 80017ae: b08a sub sp, #40 ; 0x28
- 80017b0: af00 add r7, sp, #0
- 80017b2: 6078 str r0, [r7, #4]
+ 8001828: b580 push {r7, lr}
+ 800182a: b08a sub sp, #40 ; 0x28
+ 800182c: af00 add r7, sp, #0
+ 800182e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80017b4: f107 0314 add.w r3, r7, #20
- 80017b8: 2200 movs r2, #0
- 80017ba: 601a str r2, [r3, #0]
- 80017bc: 605a str r2, [r3, #4]
- 80017be: 609a str r2, [r3, #8]
- 80017c0: 60da str r2, [r3, #12]
- 80017c2: 611a str r2, [r3, #16]
+ 8001830: f107 0314 add.w r3, r7, #20
+ 8001834: 2200 movs r2, #0
+ 8001836: 601a str r2, [r3, #0]
+ 8001838: 605a str r2, [r3, #4]
+ 800183a: 609a str r2, [r3, #8]
+ 800183c: 60da str r2, [r3, #12]
+ 800183e: 611a str r2, [r3, #16]
if(huart->Instance==USART6)
- 80017c4: 687b ldr r3, [r7, #4]
- 80017c6: 681b ldr r3, [r3, #0]
- 80017c8: 4a17 ldr r2, [pc, #92] ; (8001828 <HAL_UART_MspInit+0x7c>)
- 80017ca: 4293 cmp r3, r2
- 80017cc: d127 bne.n 800181e <HAL_UART_MspInit+0x72>
+ 8001840: 687b ldr r3, [r7, #4]
+ 8001842: 681b ldr r3, [r3, #0]
+ 8001844: 4a17 ldr r2, [pc, #92] ; (80018a4 <HAL_UART_MspInit+0x7c>)
+ 8001846: 4293 cmp r3, r2
+ 8001848: d127 bne.n 800189a <HAL_UART_MspInit+0x72>
{
/* USER CODE BEGIN USART6_MspInit 0 */
/* USER CODE END USART6_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART6_CLK_ENABLE();
- 80017ce: 4b17 ldr r3, [pc, #92] ; (800182c <HAL_UART_MspInit+0x80>)
- 80017d0: 6c5b ldr r3, [r3, #68] ; 0x44
- 80017d2: 4a16 ldr r2, [pc, #88] ; (800182c <HAL_UART_MspInit+0x80>)
- 80017d4: f043 0320 orr.w r3, r3, #32
- 80017d8: 6453 str r3, [r2, #68] ; 0x44
- 80017da: 4b14 ldr r3, [pc, #80] ; (800182c <HAL_UART_MspInit+0x80>)
- 80017dc: 6c5b ldr r3, [r3, #68] ; 0x44
- 80017de: f003 0320 and.w r3, r3, #32
- 80017e2: 613b str r3, [r7, #16]
- 80017e4: 693b ldr r3, [r7, #16]
+ 800184a: 4b17 ldr r3, [pc, #92] ; (80018a8 <HAL_UART_MspInit+0x80>)
+ 800184c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800184e: 4a16 ldr r2, [pc, #88] ; (80018a8 <HAL_UART_MspInit+0x80>)
+ 8001850: f043 0320 orr.w r3, r3, #32
+ 8001854: 6453 str r3, [r2, #68] ; 0x44
+ 8001856: 4b14 ldr r3, [pc, #80] ; (80018a8 <HAL_UART_MspInit+0x80>)
+ 8001858: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800185a: f003 0320 and.w r3, r3, #32
+ 800185e: 613b str r3, [r7, #16]
+ 8001860: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
- 80017e6: 4b11 ldr r3, [pc, #68] ; (800182c <HAL_UART_MspInit+0x80>)
- 80017e8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80017ea: 4a10 ldr r2, [pc, #64] ; (800182c <HAL_UART_MspInit+0x80>)
- 80017ec: f043 0304 orr.w r3, r3, #4
- 80017f0: 6313 str r3, [r2, #48] ; 0x30
- 80017f2: 4b0e ldr r3, [pc, #56] ; (800182c <HAL_UART_MspInit+0x80>)
- 80017f4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80017f6: f003 0304 and.w r3, r3, #4
- 80017fa: 60fb str r3, [r7, #12]
- 80017fc: 68fb ldr r3, [r7, #12]
+ 8001862: 4b11 ldr r3, [pc, #68] ; (80018a8 <HAL_UART_MspInit+0x80>)
+ 8001864: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001866: 4a10 ldr r2, [pc, #64] ; (80018a8 <HAL_UART_MspInit+0x80>)
+ 8001868: f043 0304 orr.w r3, r3, #4
+ 800186c: 6313 str r3, [r2, #48] ; 0x30
+ 800186e: 4b0e ldr r3, [pc, #56] ; (80018a8 <HAL_UART_MspInit+0x80>)
+ 8001870: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001872: f003 0304 and.w r3, r3, #4
+ 8001876: 60fb str r3, [r7, #12]
+ 8001878: 68fb ldr r3, [r7, #12]
/**USART6 GPIO Configuration
PC6 ------> USART6_TX
PC7 ------> USART6_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 80017fe: 23c0 movs r3, #192 ; 0xc0
- 8001800: 617b str r3, [r7, #20]
+ 800187a: 23c0 movs r3, #192 ; 0xc0
+ 800187c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8001802: 2302 movs r3, #2
- 8001804: 61bb str r3, [r7, #24]
+ 800187e: 2302 movs r3, #2
+ 8001880: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001806: 2300 movs r3, #0
- 8001808: 61fb str r3, [r7, #28]
+ 8001882: 2300 movs r3, #0
+ 8001884: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 800180a: 2303 movs r3, #3
- 800180c: 623b str r3, [r7, #32]
+ 8001886: 2303 movs r3, #3
+ 8001888: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
- 800180e: 2308 movs r3, #8
- 8001810: 627b str r3, [r7, #36] ; 0x24
+ 800188a: 2308 movs r3, #8
+ 800188c: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8001812: f107 0314 add.w r3, r7, #20
- 8001816: 4619 mov r1, r3
- 8001818: 4805 ldr r0, [pc, #20] ; (8001830 <HAL_UART_MspInit+0x84>)
- 800181a: f000 fa4f bl 8001cbc <HAL_GPIO_Init>
+ 800188e: f107 0314 add.w r3, r7, #20
+ 8001892: 4619 mov r1, r3
+ 8001894: 4805 ldr r0, [pc, #20] ; (80018ac <HAL_UART_MspInit+0x84>)
+ 8001896: f000 fa4f bl 8001d38 <HAL_GPIO_Init>
/* USER CODE BEGIN USART6_MspInit 1 */
/* USER CODE END USART6_MspInit 1 */
}
}
- 800181e: bf00 nop
- 8001820: 3728 adds r7, #40 ; 0x28
- 8001822: 46bd mov sp, r7
- 8001824: bd80 pop {r7, pc}
- 8001826: bf00 nop
- 8001828: 40011400 .word 0x40011400
- 800182c: 40023800 .word 0x40023800
- 8001830: 40020800 .word 0x40020800
-
-08001834 <NMI_Handler>:
+ 800189a: bf00 nop
+ 800189c: 3728 adds r7, #40 ; 0x28
+ 800189e: 46bd mov sp, r7
+ 80018a0: bd80 pop {r7, pc}
+ 80018a2: bf00 nop
+ 80018a4: 40011400 .word 0x40011400
+ 80018a8: 40023800 .word 0x40023800
+ 80018ac: 40020800 .word 0x40020800
+
+080018b0 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
- 8001834: b480 push {r7}
- 8001836: af00 add r7, sp, #0
+ 80018b0: b480 push {r7}
+ 80018b2: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
- 8001838: bf00 nop
- 800183a: 46bd mov sp, r7
- 800183c: f85d 7b04 ldr.w r7, [sp], #4
- 8001840: 4770 bx lr
+ 80018b4: bf00 nop
+ 80018b6: 46bd mov sp, r7
+ 80018b8: f85d 7b04 ldr.w r7, [sp], #4
+ 80018bc: 4770 bx lr
-08001842 <HardFault_Handler>:
+080018be <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
- 8001842: b480 push {r7}
- 8001844: af00 add r7, sp, #0
+ 80018be: b480 push {r7}
+ 80018c0: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
- 8001846: e7fe b.n 8001846 <HardFault_Handler+0x4>
+ 80018c2: e7fe b.n 80018c2 <HardFault_Handler+0x4>
-08001848 <MemManage_Handler>:
+080018c4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
- 8001848: b480 push {r7}
- 800184a: af00 add r7, sp, #0
+ 80018c4: b480 push {r7}
+ 80018c6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
- 800184c: e7fe b.n 800184c <MemManage_Handler+0x4>
+ 80018c8: e7fe b.n 80018c8 <MemManage_Handler+0x4>
-0800184e <BusFault_Handler>:
+080018ca <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
- 800184e: b480 push {r7}
- 8001850: af00 add r7, sp, #0
+ 80018ca: b480 push {r7}
+ 80018cc: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
- 8001852: e7fe b.n 8001852 <BusFault_Handler+0x4>
+ 80018ce: e7fe b.n 80018ce <BusFault_Handler+0x4>
-08001854 <UsageFault_Handler>:
+080018d0 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
- 8001854: b480 push {r7}
- 8001856: af00 add r7, sp, #0
+ 80018d0: b480 push {r7}
+ 80018d2: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
- 8001858: e7fe b.n 8001858 <UsageFault_Handler+0x4>
+ 80018d4: e7fe b.n 80018d4 <UsageFault_Handler+0x4>
-0800185a <SVC_Handler>:
+080018d6 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
- 800185a: b480 push {r7}
- 800185c: af00 add r7, sp, #0
+ 80018d6: b480 push {r7}
+ 80018d8: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
- 800185e: bf00 nop
- 8001860: 46bd mov sp, r7
- 8001862: f85d 7b04 ldr.w r7, [sp], #4
- 8001866: 4770 bx lr
+ 80018da: bf00 nop
+ 80018dc: 46bd mov sp, r7
+ 80018de: f85d 7b04 ldr.w r7, [sp], #4
+ 80018e2: 4770 bx lr
-08001868 <DebugMon_Handler>:
+080018e4 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
- 8001868: b480 push {r7}
- 800186a: af00 add r7, sp, #0
+ 80018e4: b480 push {r7}
+ 80018e6: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
- 800186c: bf00 nop
- 800186e: 46bd mov sp, r7
- 8001870: f85d 7b04 ldr.w r7, [sp], #4
- 8001874: 4770 bx lr
+ 80018e8: bf00 nop
+ 80018ea: 46bd mov sp, r7
+ 80018ec: f85d 7b04 ldr.w r7, [sp], #4
+ 80018f0: 4770 bx lr
-080018
76 <PendSV_Handler>:
+080018
f2 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
- 8001876: b480 push {r7}
- 8001878: af00 add r7, sp, #0
+ 80018f2: b480 push {r7}
+ 80018f4: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
- 800187a: bf00 nop
- 800187c: 46bd mov sp, r7
- 800187e: f85d 7b04 ldr.w r7, [sp], #4
- 8001882: 4770 bx lr
+ 80018f6: bf00 nop
+ 80018f8: 46bd mov sp, r7
+ 80018fa: f85d 7b04 ldr.w r7, [sp], #4
+ 80018fe: 4770 bx lr
-08001884 <SysTick_Handler>:
+08001900 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
- 8001884: b580 push {r7, lr}
- 8001886: af00 add r7, sp, #0
+ 8001900: b580 push {r7, lr}
+ 8001902: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
- 8001888: f000 f8c4 bl 8001a14 <HAL_IncTick>
+ 8001904: f000 f8c4 bl 8001a90 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
- 800188c: bf00 nop
- 800188e: bd80 pop {r7, pc}
+ 8001908: bf00 nop
+ 800190a: bd80 pop {r7, pc}
-08001890 <TIM3_IRQHandler>:
+0800190c <TIM3_IRQHandler>:
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
- 8001890: b580 push {r7, lr}
- 8001892: af00 add r7, sp, #0
+ 800190c: b580 push {r7, lr}
+ 800190e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
HAL_TIM_IRQHandler(&htim3);
- 8001894: 4802 ldr r0, [pc, #8] ; (80018a0 <TIM3_IRQHandler+0x10>)
- 8001896: f001 fdec bl 8003472 <HAL_TIM_IRQHandler>
+ 8001910: 4802 ldr r0, [pc, #8] ; (800191c <TIM3_IRQHandler+0x10>)
+ 8001912: f001 fdec bl 80034ee <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM3_IRQn 1 */
/* USER CODE END TIM3_IRQn 1 */
}
- 800189a: bf00 nop
- 800189c: bd80 pop {r7, pc}
- 800189e: bf00 nop
- 80018a0: 2000006c .word 0x2000006c
+ 8001916: bf00 nop
+ 8001918: bd80 pop {r7, pc}
+ 800191a: bf00 nop
+ 800191c: 20000070 .word 0x20000070
-080018a4 <EXTI15_10_IRQHandler>:
+08001920 <EXTI15_10_IRQHandler>:
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
- 80018a4: b580 push {r7, lr}
- 80018a6: af00 add r7, sp, #0
+ 8001920: b580 push {r7, lr}
+ 8001922: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
- 80018a8: f44f 5000 mov.w r0, #8192 ; 0x2000
- 80018ac: f000 fbca bl 8002044 <HAL_GPIO_EXTI_IRQHandler>
+ 8001924: f44f 5000 mov.w r0, #8192 ; 0x2000
+ 8001928: f000 fbca bl 80020c0 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
- 80018b0: bf00 nop
- 80018b2: bd80 pop {r7, pc}
+ 800192c: bf00 nop
+ 800192e: bd80 pop {r7, pc}
-080018b4 <TIM6_DAC_IRQHandler>:
+08001930 <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
- 80018b4: b580 push {r7, lr}
- 80018b6: af00 add r7, sp, #0
+ 8001930: b580 push {r7, lr}
+ 8001932: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
- 80018b8: 4802 ldr r0, [pc, #8] ; (80018c4 <TIM6_DAC_IRQHandler+0x10>)
- 80018ba: f001 fdda bl 8003472 <HAL_TIM_IRQHandler>
+ 8001934: 4802 ldr r0, [pc, #8] ; (8001940 <TIM6_DAC_IRQHandler+0x10>)
+ 8001936: f001 fdda bl 80034ee <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
- 80018be: bf00 nop
- 80018c0: bd80 pop {r7, pc}
- 80018c2: bf00 nop
- 80018c4: 2000012c .word 0x2000012c
+ 800193a: bf00 nop
+ 800193c: bd80 pop {r7, pc}
+ 800193e: bf00 nop
+ 8001940: 20000130 .word 0x20000130
-080018c8 <USART6_IRQHandler>:
+08001944 <USART6_IRQHandler>:
/**
* @brief This function handles USART6 global interrupt.
*/
void USART6_IRQHandler(void)
{
- 80018c8: b580 push {r7, lr}
- 80018ca: af00 add r7, sp, #0
+ 8001944: b580 push {r7, lr}
+ 8001946: af00 add r7, sp, #0
/* USER CODE BEGIN USART6_IRQn 0 */
/* USER CODE END USART6_IRQn 0 */
HAL_UART_IRQHandler(&huart6);
- 80018cc: 4802 ldr r0, [pc, #8] ; (80018d8 <USART6_IRQHandler+0x10>)
- 80018ce: f002 fe01 bl 80044d4 <HAL_UART_IRQHandler>
+ 8001948: 4802 ldr r0, [pc, #8] ; (8001954 <USART6_IRQHandler+0x10>)
+ 800194a: f002 fea3 bl 8004694 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART6_IRQn 1 */
/* USER CODE END USART6_IRQn 1 */
}
- 80018d2: bf00 nop
- 80018d4: bd80 pop {r7, pc}
- 80018d6: bf00 nop
- 80018d8: 2000016c .word 0x2000016c
+ 800194e: bf00 nop
+ 8001950: bd80 pop {r7, pc}
+ 8001952: bf00 nop
+ 8001954: 20000170 .word 0x20000170
-080018dc <SystemInit>:
+08001958 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
- 80018dc: b480 push {r7}
- 80018de: af00 add r7, sp, #0
+ 8001958: b480 push {r7}
+ 800195a: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 80018e0: 4b15 ldr r3, [pc, #84] ; (8001938 <SystemInit+0x5c>)
- 80018e2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80018e6: 4a14 ldr r2, [pc, #80] ; (8001938 <SystemInit+0x5c>)
- 80018e8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 80018ec: f8c2 3088 str.w r3, [r2, #136] ; 0x88
+ 800195c: 4b15 ldr r3, [pc, #84] ; (80019b4 <SystemInit+0x5c>)
+ 800195e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001962: 4a14 ldr r2, [pc, #80] ; (80019b4 <SystemInit+0x5c>)
+ 8001964: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
+ 8001968: f8c2 3088 str.w r3, [r2, #136] ; 0x88
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
- 80018f0: 4b12 ldr r3, [pc, #72] ; (800193c <SystemInit+0x60>)
- 80018f2: 681b ldr r3, [r3, #0]
- 80018f4: 4a11 ldr r2, [pc, #68] ; (800193c <SystemInit+0x60>)
- 80018f6: f043 0301 orr.w r3, r3, #1
- 80018fa: 6013 str r3, [r2, #0]
+ 800196c: 4b12 ldr r3, [pc, #72] ; (80019b8 <SystemInit+0x60>)
+ 800196e: 681b ldr r3, [r3, #0]
+ 8001970: 4a11 ldr r2, [pc, #68] ; (80019b8 <SystemInit+0x60>)
+ 8001972: f043 0301 orr.w r3, r3, #1
+ 8001976: 6013 str r3, [r2, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
- 80018fc: 4b0f ldr r3, [pc, #60] ; (800193c <SystemInit+0x60>)
- 80018fe: 2200 movs r2, #0
- 8001900: 609a str r2, [r3, #8]
+ 8001978: 4b0f ldr r3, [pc, #60] ; (80019b8 <SystemInit+0x60>)
+ 800197a: 2200 movs r2, #0
+ 800197c: 609a str r2, [r3, #8]
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8001902: 4b0e ldr r3, [pc, #56] ; (800193c <SystemInit+0x60>)
- 8001904: 681a ldr r2, [r3, #0]
- 8001906: 490d ldr r1, [pc, #52] ; (800193c <SystemInit+0x60>)
- 8001908: 4b0d ldr r3, [pc, #52] ; (8001940 <SystemInit+0x64>)
- 800190a: 4013 ands r3, r2
- 800190c: 600b str r3, [r1, #0]
+ 800197e: 4b0e ldr r3, [pc, #56] ; (80019b8 <SystemInit+0x60>)
+ 8001980: 681a ldr r2, [r3, #0]
+ 8001982: 490d ldr r1, [pc, #52] ; (80019b8 <SystemInit+0x60>)
+ 8001984: 4b0d ldr r3, [pc, #52] ; (80019bc <SystemInit+0x64>)
+ 8001986: 4013 ands r3, r2
+ 8001988: 600b str r3, [r1, #0]
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
- 800190e: 4b0b ldr r3, [pc, #44] ; (800193c <SystemInit+0x60>)
- 8001910: 4a0c ldr r2, [pc, #48] ; (8001944 <SystemInit+0x68>)
- 8001912: 605a str r2, [r3, #4]
+ 800198a: 4b0b ldr r3, [pc, #44] ; (80019b8 <SystemInit+0x60>)
+ 800198c: 4a0c ldr r2, [pc, #48] ; (80019c0 <SystemInit+0x68>)
+ 800198e: 605a str r2, [r3, #4]
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
- 8001914: 4b09 ldr r3, [pc, #36] ; (800193c <SystemInit+0x60>)
- 8001916: 681b ldr r3, [r3, #0]
- 8001918: 4a08 ldr r2, [pc, #32] ; (800193c <SystemInit+0x60>)
- 800191a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 800191e: 6013 str r3, [r2, #0]
+ 8001990: 4b09 ldr r3, [pc, #36] ; (80019b8 <SystemInit+0x60>)
+ 8001992: 681b ldr r3, [r3, #0]
+ 8001994: 4a08 ldr r2, [pc, #32] ; (80019b8 <SystemInit+0x60>)
+ 8001996: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 800199a: 6013 str r3, [r2, #0]
/* Disable all interrupts */
RCC->CIR = 0x00000000;
- 8001920: 4b06 ldr r3, [pc, #24] ; (800193c <SystemInit+0x60>)
- 8001922: 2200 movs r2, #0
- 8001924: 60da str r2, [r3, #12]
+ 800199c: 4b06 ldr r3, [pc, #24] ; (80019b8 <SystemInit+0x60>)
+ 800199e: 2200 movs r2, #0
+ 80019a0: 60da str r2, [r3, #12]
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8001926: 4b04 ldr r3, [pc, #16] ; (8001938 <SystemInit+0x5c>)
- 8001928: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 800192c: 609a str r2, [r3, #8]
+ 80019a2: 4b04 ldr r3, [pc, #16] ; (80019b4 <SystemInit+0x5c>)
+ 80019a4: f04f 6200 mov.w r2, #134217728 ; 0x8000000
+ 80019a8: 609a str r2, [r3, #8]
#endif
}
- 800192e: bf00 nop
- 8001930: 46bd mov sp, r7
- 8001932: f85d 7b04 ldr.w r7, [sp], #4
- 8001936: 4770 bx lr
- 8001938: e000ed00 .word 0xe000ed00
- 800193c: 40023800 .word 0x40023800
- 8001940: fef6ffff .word 0xfef6ffff
- 8001944: 24003010 .word 0x24003010
+ 80019aa: bf00 nop
+ 80019ac: 46bd mov sp, r7
+ 80019ae: f85d 7b04 ldr.w r7, [sp], #4
+ 80019b2: 4770 bx lr
+ 80019b4: e000ed00 .word 0xe000ed00
+ 80019b8: 40023800 .word 0x40023800
+ 80019bc: fef6ffff .word 0xfef6ffff
+ 80019c0: 24003010 .word 0x24003010
-08001948 <Reset_Handler>:
+080019c4 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
- 8001948: f8df d034 ldr.w sp, [pc, #52] ; 8001980 <LoopFillZerobss+0x14>
+ 80019c4: f8df d034 ldr.w sp, [pc, #52] ; 80019fc <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
- 800194c: 2100 movs r1, #0
+ 80019c8: 2100 movs r1, #0
b LoopCopyDataInit
- 800194e: e003 b.n 8001958 <LoopCopyDataInit>
+ 80019ca: e003 b.n 80019d4 <LoopCopyDataInit>
-08001950 <CopyDataInit>:
+080019cc <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
- 8001950: 4b0c ldr r3, [pc, #48] ; (8001984 <LoopFillZerobss+0x18>)
+ 80019cc: 4b0c ldr r3, [pc, #48] ; (8001a00 <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
- 8001952: 585b ldr r3, [r3, r1]
+ 80019ce: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
- 8001954: 5043 str r3, [r0, r1]
+ 80019d0: 5043 str r3, [r0, r1]
adds r1, r1, #4
- 8001956: 3104 adds r1, #4
+ 80019d2: 3104 adds r1, #4
-08001958 <LoopCopyDataInit>:
+080019d4 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
- 8001958: 480b ldr r0, [pc, #44] ; (8001988 <LoopFillZerobss+0x1c>)
+ 80019d4: 480b ldr r0, [pc, #44] ; (8001a04 <LoopFillZerobss+0x1c>)
ldr r3, =_edata
- 800195a: 4b0c ldr r3, [pc, #48] ; (800198c <LoopFillZerobss+0x20>)
+ 80019d6: 4b0c ldr r3, [pc, #48] ; (8001a08 <LoopFillZerobss+0x20>)
adds r2, r0, r1
- 800195c: 1842 adds r2, r0, r1
+ 80019d8: 1842 adds r2, r0, r1
cmp r2, r3
- 800195e: 429a cmp r2, r3
+ 80019da: 429a cmp r2, r3
bcc CopyDataInit
- 8001960: d3f6 bcc.n 8001950 <CopyDataInit>
+ 80019dc: d3f6 bcc.n 80019cc <CopyDataInit>
ldr r2, =_sbss
- 8001962: 4a0b ldr r2, [pc, #44] ; (8001990 <LoopFillZerobss+0x24>)
+ 80019de: 4a0b ldr r2, [pc, #44] ; (8001a0c <LoopFillZerobss+0x24>)
b LoopFillZerobss
- 8001964: e002 b.n 800196c <LoopFillZerobss>
+ 80019e0: e002 b.n 80019e8 <LoopFillZerobss>
-08001966 <FillZerobss>:
+080019e2 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
- 8001966: 2300 movs r3, #0
+ 80019e2: 2300 movs r3, #0
str r3, [r2], #4
- 8001968: f842 3b04 str.w r3, [r2], #4
+ 80019e4: f842 3b04 str.w r3, [r2], #4
-0800196c <LoopFillZerobss>:
+080019e8 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
- 800196c: 4b09 ldr r3, [pc, #36] ; (8001994 <LoopFillZerobss+0x28>)
+ 80019e8: 4b09 ldr r3, [pc, #36] ; (8001a10 <LoopFillZerobss+0x28>)
cmp r2, r3
- 800196e: 429a cmp r2, r3
+ 80019ea: 429a cmp r2, r3
bcc FillZerobss
- 8001970: d3f9 bcc.n 8001966 <FillZerobss>
+ 80019ec: d3f9 bcc.n 80019e2 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
- 8001972: f7ff ffb3 bl 80018dc <SystemInit>
+ 80019ee: f7ff ffb3 bl 8001958 <SystemInit>
/* Call static constructors */
bl __libc_init_array
- 8001976: f003 fae9 bl 8004f4c <__libc_init_array>
+ 80019f2: f003 fc31 bl 8005258 <__libc_init_array>
/* Call the application's entry point.*/
bl main
- 800197a: f7ff f8bb bl 8000af4 <main>
+ 80019f6: f7ff f879 bl 8000aec <main>
bx lr
- 800197e: 4770 bx lr
+ 80019fa: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
- 8001980: 20080000 .word 0x20080000
+ 80019fc: 20080000 .word 0x20080000
ldr r3, =_sidata
- 8001984: 08004fe8 .word 0x08004fe8
+ 8001a00: 080052f4 .word 0x080052f4
ldr r0, =_sdata
- 8001988: 20000000 .word 0x20000000
+ 8001a04: 20000000 .word 0x20000000
ldr r3, =_edata
- 800198c: 20000010 .word 0x20000010
+ 8001a08: 20000014 .word 0x20000014
ldr r2, =_sbss
- 8001990: 20000010 .word 0x20000010
+ 8001a0c: 20000014 .word 0x20000014
ldr r3, = _ebss
- 8001994: 20000394 .word 0x20000394
+ 8001a10: 200003a0 .word 0x200003a0
-08001
998 <ADC_IRQHandler>:
+08001
a14 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 8001
998: e7fe b.n 8001998 <ADC_IRQHandler>
+ 8001
a14: e7fe b.n 8001a14 <ADC_IRQHandler>
-0800199a <HAL_Init>:
+08001a16 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
- 800199a: b580 push {r7, lr}
- 800199c: af00 add r7, sp, #0
+ 8001a16: b580 push {r7, lr}
+ 8001a18: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 800199e: 2003 movs r0, #3
- 80019a0: f000 f928 bl 8001bf4 <HAL_NVIC_SetPriorityGrouping>
+ 8001a1a: 2003 movs r0, #3
+ 8001a1c: f000 f928 bl 8001c70 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
- 80019a4: 2000 movs r0, #0
- 80019a6: f000 f805 bl 80019b4 <HAL_InitTick>
+ 8001a20: 2000 movs r0, #0
+ 8001a22: f000 f805 bl 8001a30 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
- 80019aa: f7ff fdcb bl 8001544 <HAL_MspInit>
+ 8001a26: f7ff fdcb bl 80015c0 <HAL_MspInit>
/* Return function status */
return HAL_OK;
- 80019ae: 2300 movs r3, #0
+ 8001a2a: 2300 movs r3, #0
}
- 80019b0: 4618 mov r0, r3
- 80019b2: bd80 pop {r7, pc}
+ 8001a2c: 4618 mov r0, r3
+ 8001a2e: bd80 pop {r7, pc}
-080019b4 <HAL_InitTick>:
+08001a30 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
- 80019b4: b580 push {r7, lr}
- 80019b6: b082 sub sp, #8
- 80019b8: af00 add r7, sp, #0
- 80019ba: 6078 str r0, [r7, #4]
+ 8001a30: b580 push {r7, lr}
+ 8001a32: b082 sub sp, #8
+ 8001a34: af00 add r7, sp, #0
+ 8001a36: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 80019bc: 4b12 ldr r3, [pc, #72] ; (8001a08 <HAL_InitTick+0x54>)
- 80019be: 681a ldr r2, [r3, #0]
- 80019c0: 4b12 ldr r3, [pc, #72] ; (8001a0c <HAL_InitTick+0x58>)
- 80019c2: 781b ldrb r3, [r3, #0]
- 80019c4: 4619 mov r1, r3
- 80019c6: f44f 737a mov.w r3, #1000 ; 0x3e8
- 80019ca: fbb3 f3f1 udiv r3, r3, r1
- 80019ce: fbb2 f3f3 udiv r3, r2, r3
- 80019d2: 4618 mov r0, r3
- 80019d4: f000 f943 bl 8001c5e <HAL_SYSTICK_Config>
- 80019d8: 4603 mov r3, r0
- 80019da: 2b00 cmp r3, #0
- 80019dc: d001 beq.n 80019e2 <HAL_InitTick+0x2e>
+ 8001a38: 4b12 ldr r3, [pc, #72] ; (8001a84 <HAL_InitTick+0x54>)
+ 8001a3a: 681a ldr r2, [r3, #0]
+ 8001a3c: 4b12 ldr r3, [pc, #72] ; (8001a88 <HAL_InitTick+0x58>)
+ 8001a3e: 781b ldrb r3, [r3, #0]
+ 8001a40: 4619 mov r1, r3
+ 8001a42: f44f 737a mov.w r3, #1000 ; 0x3e8
+ 8001a46: fbb3 f3f1 udiv r3, r3, r1
+ 8001a4a: fbb2 f3f3 udiv r3, r2, r3
+ 8001a4e: 4618 mov r0, r3
+ 8001a50: f000 f943 bl 8001cda <HAL_SYSTICK_Config>
+ 8001a54: 4603 mov r3, r0
+ 8001a56: 2b00 cmp r3, #0
+ 8001a58: d001 beq.n 8001a5e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
- 80019de: 2301 movs r3, #1
- 80019e0: e00e b.n 8001a00 <HAL_InitTick+0x4c>
+ 8001a5a: 2301 movs r3, #1
+ 8001a5c: e00e b.n 8001a7c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 80019e2: 687b ldr r3, [r7, #4]
- 80019e4: 2b0f cmp r3, #15
- 80019e6: d80a bhi.n 80019fe <HAL_InitTick+0x4a>
+ 8001a5e: 687b ldr r3, [r7, #4]
+ 8001a60: 2b0f cmp r3, #15
+ 8001a62: d80a bhi.n 8001a7a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 80019e8: 2200 movs r2, #0
- 80019ea: 6879 ldr r1, [r7, #4]
- 80019ec: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 80019f0: f000 f90b bl 8001c0a <HAL_NVIC_SetPriority>
+ 8001a64: 2200 movs r2, #0
+ 8001a66: 6879 ldr r1, [r7, #4]
+ 8001a68: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8001a6c: f000 f90b bl 8001c86 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
- 80019f4: 4a06 ldr r2, [pc, #24] ; (8001a10 <HAL_InitTick+0x5c>)
- 80019f6: 687b ldr r3, [r7, #4]
- 80019f8: 6013 str r3, [r2, #0]
+ 8001a70: 4a06 ldr r2, [pc, #24] ; (8001a8c <HAL_InitTick+0x5c>)
+ 8001a72: 687b ldr r3, [r7, #4]
+ 8001a74: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
- 80019fa: 2300 movs r3, #0
- 80019fc: e000 b.n 8001a00 <HAL_InitTick+0x4c>
+ 8001a76: 2300 movs r3, #0
+ 8001a78: e000 b.n 8001a7c <HAL_InitTick+0x4c>
return HAL_ERROR;
- 80019fe: 2301 movs r3, #1
+ 8001a7a: 2301 movs r3, #1
}
- 8001a00: 4618 mov r0, r3
- 8001a02: 3708 adds r7, #8
- 8001a04: 46bd mov sp, r7
- 8001a06: bd80 pop {r7, pc}
- 8001a08: 20000004 .word 0x20000004
- 8001a0c: 2000000c .word 0x2000000c
- 8001a10: 20000008 .word 0x20000008
-
-08001a14 <HAL_IncTick>:
+ 8001a7c: 4618 mov r0, r3
+ 8001a7e: 3708 adds r7, #8
+ 8001a80: 46bd mov sp, r7
+ 8001a82: bd80 pop {r7, pc}
+ 8001a84: 20000008 .word 0x20000008
+ 8001a88: 20000010 .word 0x20000010
+ 8001a8c: 2000000c .word 0x2000000c
+
+08001a90 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
- 8001a14: b480 push {r7}
- 8001a16: af00 add r7, sp, #0
+ 8001a90: b480 push {r7}
+ 8001a92: af00 add r7, sp, #0
uwTick += uwTickFreq;
- 8001a18: 4b06 ldr r3, [pc, #24] ; (8001a34 <HAL_IncTick+0x20>)
- 8001a1a: 781b ldrb r3, [r3, #0]
- 8001a1c: 461a mov r2, r3
- 8001a1e: 4b06 ldr r3, [pc, #24] ; (8001a38 <HAL_IncTick+0x24>)
- 8001a20: 681b ldr r3, [r3, #0]
- 8001a22: 4413 add r3, r2
- 8001a24: 4a04 ldr r2, [pc, #16] ; (8001a38 <HAL_IncTick+0x24>)
- 8001a26: 6013 str r3, [r2, #0]
+ 8001a94: 4b06 ldr r3, [pc, #24] ; (8001ab0 <HAL_IncTick+0x20>)
+ 8001a96: 781b ldrb r3, [r3, #0]
+ 8001a98: 461a mov r2, r3
+ 8001a9a: 4b06 ldr r3, [pc, #24] ; (8001ab4 <HAL_IncTick+0x24>)
+ 8001a9c: 681b ldr r3, [r3, #0]
+ 8001a9e: 4413 add r3, r2
+ 8001aa0: 4a04 ldr r2, [pc, #16] ; (8001ab4 <HAL_IncTick+0x24>)
+ 8001aa2: 6013 str r3, [r2, #0]
}
- 8001a28: bf00 nop
- 8001a2a: 46bd mov sp, r7
- 8001a2c: f85d 7b04 ldr.w r7, [sp], #4
- 8001a30: 4770 bx lr
- 8001a32: bf00 nop
- 8001a34: 2000000c .word 0x2000000c
- 8001a38: 20000390 .word 0x20000390
-
-08001a3c <HAL_GetTick>:
+ 8001aa4: bf00 nop
+ 8001aa6: 46bd mov sp, r7
+ 8001aa8: f85d 7b04 ldr.w r7, [sp], #4
+ 8001aac: 4770 bx lr
+ 8001aae: bf00 nop
+ 8001ab0: 20000010 .word 0x20000010
+ 8001ab4: 2000039c .word 0x2000039c
+
+08001ab8 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
- 8001a3c: b480 push {r7}
- 8001a3e: af00 add r7, sp, #0
+ 8001ab8: b480 push {r7}
+ 8001aba: af00 add r7, sp, #0
return uwTick;
- 8001a40: 4b03 ldr r3, [pc, #12] ; (8001a50 <HAL_GetTick+0x14>)
- 8001a42: 681b ldr r3, [r3, #0]
+ 8001abc: 4b03 ldr r3, [pc, #12] ; (8001acc <HAL_GetTick+0x14>)
+ 8001abe: 681b ldr r3, [r3, #0]
}
- 8001a44: 4618 mov r0, r3
- 8001a46: 46bd mov sp, r7
- 8001a48: f85d 7b04 ldr.w r7, [sp], #4
- 8001a4c: 4770 bx lr
- 8001a4e: bf00 nop
- 8001a50: 20000390 .word 0x20000390
-
-08001a54 <__NVIC_SetPriorityGrouping>:
+ 8001ac0: 4618 mov r0, r3
+ 8001ac2: 46bd mov sp, r7
+ 8001ac4: f85d 7b04 ldr.w r7, [sp], #4
+ 8001ac8: 4770 bx lr
+ 8001aca: bf00 nop
+ 8001acc: 2000039c .word 0x2000039c
+
+08001ad0 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
- 8001a54: b480 push {r7}
- 8001a56: b085 sub sp, #20
- 8001a58: af00 add r7, sp, #0
- 8001a5a: 6078 str r0, [r7, #4]
+ 8001ad0: b480 push {r7}
+ 8001ad2: b085 sub sp, #20
+ 8001ad4: af00 add r7, sp, #0
+ 8001ad6: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001a5c: 687b ldr r3, [r7, #4]
- 8001a5e: f003 0307 and.w r3, r3, #7
- 8001a62: 60fb str r3, [r7, #12]
+ 8001ad8: 687b ldr r3, [r7, #4]
+ 8001ada: f003 0307 and.w r3, r3, #7
+ 8001ade: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
- 8001a64: 4b0b ldr r3, [pc, #44] ; (8001a94 <__NVIC_SetPriorityGrouping+0x40>)
- 8001a66: 68db ldr r3, [r3, #12]
- 8001a68: 60bb str r3, [r7, #8]
+ 8001ae0: 4b0b ldr r3, [pc, #44] ; (8001b10 <__NVIC_SetPriorityGrouping+0x40>)
+ 8001ae2: 68db ldr r3, [r3, #12]
+ 8001ae4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 8001a6a: 68ba ldr r2, [r7, #8]
- 8001a6c: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8001a70: 4013 ands r3, r2
- 8001a72: 60bb str r3, [r7, #8]
+ 8001ae6: 68ba ldr r2, [r7, #8]
+ 8001ae8: f64f 03ff movw r3, #63743 ; 0xf8ff
+ 8001aec: 4013 ands r3, r2
+ 8001aee: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8001a74: 68fb ldr r3, [r7, #12]
- 8001a76: 021a lsls r2, r3, #8
+ 8001af0: 68fb ldr r3, [r7, #12]
+ 8001af2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8001a78: 68bb ldr r3, [r7, #8]
- 8001a7a: 431a orrs r2, r3
+ 8001af4: 68bb ldr r3, [r7, #8]
+ 8001af6: 431a orrs r2, r3
reg_value = (reg_value |
- 8001a7c: 4b06 ldr r3, [pc, #24] ; (8001a98 <__NVIC_SetPriorityGrouping+0x44>)
- 8001a7e: 4313 orrs r3, r2
- 8001a80: 60bb str r3, [r7, #8]
+ 8001af8: 4b06 ldr r3, [pc, #24] ; (8001b14 <__NVIC_SetPriorityGrouping+0x44>)
+ 8001afa: 4313 orrs r3, r2
+ 8001afc: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
- 8001a82: 4a04 ldr r2, [pc, #16] ; (8001a94 <__NVIC_SetPriorityGrouping+0x40>)
- 8001a84: 68bb ldr r3, [r7, #8]
- 8001a86: 60d3 str r3, [r2, #12]
+ 8001afe: 4a04 ldr r2, [pc, #16] ; (8001b10 <__NVIC_SetPriorityGrouping+0x40>)
+ 8001b00: 68bb ldr r3, [r7, #8]
+ 8001b02: 60d3 str r3, [r2, #12]
}
- 8001a88: bf00 nop
- 8001a8a: 3714 adds r7, #20
- 8001a8c: 46bd mov sp, r7
- 8001a8e: f85d 7b04 ldr.w r7, [sp], #4
- 8001a92: 4770 bx lr
- 8001a94: e000ed00 .word 0xe000ed00
- 8001a98: 05fa0000 .word 0x05fa0000
-
-08001a9c <__NVIC_GetPriorityGrouping>:
+ 8001b04: bf00 nop
+ 8001b06: 3714 adds r7, #20
+ 8001b08: 46bd mov sp, r7
+ 8001b0a: f85d 7b04 ldr.w r7, [sp], #4
+ 8001b0e: 4770 bx lr
+ 8001b10: e000ed00 .word 0xe000ed00
+ 8001b14: 05fa0000 .word 0x05fa0000
+
+08001b18 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
- 8001a9c: b480 push {r7}
- 8001a9e: af00 add r7, sp, #0
+ 8001b18: b480 push {r7}
+ 8001b1a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8001aa0: 4b04 ldr r3, [pc, #16] ; (8001ab4 <__NVIC_GetPriorityGrouping+0x18>)
- 8001aa2: 68db ldr r3, [r3, #12]
- 8001aa4: 0a1b lsrs r3, r3, #8
- 8001aa6: f003 0307 and.w r3, r3, #7
+ 8001b1c: 4b04 ldr r3, [pc, #16] ; (8001b30 <__NVIC_GetPriorityGrouping+0x18>)
+ 8001b1e: 68db ldr r3, [r3, #12]
+ 8001b20: 0a1b lsrs r3, r3, #8
+ 8001b22: f003 0307 and.w r3, r3, #7
}
- 8001aaa: 4618 mov r0, r3
- 8001aac: 46bd mov sp, r7
- 8001aae: f85d 7b04 ldr.w r7, [sp], #4
- 8001ab2: 4770 bx lr
- 8001ab4: e000ed00 .word 0xe000ed00
+ 8001b26: 4618 mov r0, r3
+ 8001b28: 46bd mov sp, r7
+ 8001b2a: f85d 7b04 ldr.w r7, [sp], #4
+ 8001b2e: 4770 bx lr
+ 8001b30: e000ed00 .word 0xe000ed00
-08001ab8 <__NVIC_EnableIRQ>:
+08001b34 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
- 8001ab8: b480 push {r7}
- 8001aba: b083 sub sp, #12
- 8001abc: af00 add r7, sp, #0
- 8001abe: 4603 mov r3, r0
- 8001ac0: 71fb strb r3, [r7, #7]
+ 8001b34: b480 push {r7}
+ 8001b36: b083 sub sp, #12
+ 8001b38: af00 add r7, sp, #0
+ 8001b3a: 4603 mov r3, r0
+ 8001b3c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
- 8001ac2: f997 3007 ldrsb.w r3, [r7, #7]
- 8001ac6: 2b00 cmp r3, #0
- 8001ac8: db0b blt.n 8001ae2 <__NVIC_EnableIRQ+0x2a>
+ 8001b3e: f997 3007 ldrsb.w r3, [r7, #7]
+ 8001b42: 2b00 cmp r3, #0
+ 8001b44: db0b blt.n 8001b5e <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 8001aca: 79fb ldrb r3, [r7, #7]
- 8001acc: f003 021f and.w r2, r3, #31
- 8001ad0: 4907 ldr r1, [pc, #28] ; (8001af0 <__NVIC_EnableIRQ+0x38>)
- 8001ad2: f997 3007 ldrsb.w r3, [r7, #7]
- 8001ad6: 095b lsrs r3, r3, #5
- 8001ad8: 2001 movs r0, #1
- 8001ada: fa00 f202 lsl.w r2, r0, r2
- 8001ade: f841 2023 str.w r2, [r1, r3, lsl #2]
+ 8001b46: 79fb ldrb r3, [r7, #7]
+ 8001b48: f003 021f and.w r2, r3, #31
+ 8001b4c: 4907 ldr r1, [pc, #28] ; (8001b6c <__NVIC_EnableIRQ+0x38>)
+ 8001b4e: f997 3007 ldrsb.w r3, [r7, #7]
+ 8001b52: 095b lsrs r3, r3, #5
+ 8001b54: 2001 movs r0, #1
+ 8001b56: fa00 f202 lsl.w r2, r0, r2
+ 8001b5a: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
- 8001ae2: bf00 nop
- 8001ae4: 370c adds r7, #12
- 8001ae6: 46bd mov sp, r7
- 8001ae8: f85d 7b04 ldr.w r7, [sp], #4
- 8001aec: 4770 bx lr
- 8001aee: bf00 nop
- 8001af0: e000e100 .word 0xe000e100
-
-08001af4 <__NVIC_SetPriority>:
+ 8001b5e: bf00 nop
+ 8001b60: 370c adds r7, #12
+ 8001b62: 46bd mov sp, r7
+ 8001b64: f85d 7b04 ldr.w r7, [sp], #4
+ 8001b68: 4770 bx lr
+ 8001b6a: bf00 nop
+ 8001b6c: e000e100 .word 0xe000e100
+
+08001b70 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- 8001af4: b480 push {r7}
- 8001af6: b083 sub sp, #12
- 8001af8: af00 add r7, sp, #0
- 8001afa: 4603 mov r3, r0
- 8001afc: 6039 str r1, [r7, #0]
- 8001afe: 71fb strb r3, [r7, #7]
+ 8001b70: b480 push {r7}
+ 8001b72: b083 sub sp, #12
+ 8001b74: af00 add r7, sp, #0
+ 8001b76: 4603 mov r3, r0
+ 8001b78: 6039 str r1, [r7, #0]
+ 8001b7a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
- 8001b00: f997 3007 ldrsb.w r3, [r7, #7]
- 8001b04: 2b00 cmp r3, #0
- 8001b06: db0a blt.n 8001b1e <__NVIC_SetPriority+0x2a>
+ 8001b7c: f997 3007 ldrsb.w r3, [r7, #7]
+ 8001b80: 2b00 cmp r3, #0
+ 8001b82: db0a blt.n 8001b9a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001b08: 683b ldr r3, [r7, #0]
- 8001b0a: b2da uxtb r2, r3
- 8001b0c: 490c ldr r1, [pc, #48] ; (8001b40 <__NVIC_SetPriority+0x4c>)
- 8001b0e: f997 3007 ldrsb.w r3, [r7, #7]
- 8001b12: 0112 lsls r2, r2, #4
- 8001b14: b2d2 uxtb r2, r2
- 8001b16: 440b add r3, r1
- 8001b18: f883 2300 strb.w r2, [r3, #768] ; 0x300
+ 8001b84: 683b ldr r3, [r7, #0]
+ 8001b86: b2da uxtb r2, r3
+ 8001b88: 490c ldr r1, [pc, #48] ; (8001bbc <__NVIC_SetPriority+0x4c>)
+ 8001b8a: f997 3007 ldrsb.w r3, [r7, #7]
+ 8001b8e: 0112 lsls r2, r2, #4
+ 8001b90: b2d2 uxtb r2, r2
+ 8001b92: 440b add r3, r1
+ 8001b94: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
- 8001b1c: e00a b.n 8001b34 <__NVIC_SetPriority+0x40>
+ 8001b98: e00a b.n 8001bb0 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8001b1e: 683b ldr r3, [r7, #0]
- 8001b20: b2da uxtb r2, r3
- 8001b22: 4908 ldr r1, [pc, #32] ; (8001b44 <__NVIC_SetPriority+0x50>)
- 8001b24: 79fb ldrb r3, [r7, #7]
- 8001b26: f003 030f and.w r3, r3, #15
- 8001b2a: 3b04 subs r3, #4
- 8001b2c: 0112 lsls r2, r2, #4
- 8001b2e: b2d2 uxtb r2, r2
- 8001b30: 440b add r3, r1
- 8001b32: 761a strb r2, [r3, #24]
+ 8001b9a: 683b ldr r3, [r7, #0]
+ 8001b9c: b2da uxtb r2, r3
+ 8001b9e: 4908 ldr r1, [pc, #32] ; (8001bc0 <__NVIC_SetPriority+0x50>)
+ 8001ba0: 79fb ldrb r3, [r7, #7]
+ 8001ba2: f003 030f and.w r3, r3, #15
+ 8001ba6: 3b04 subs r3, #4
+ 8001ba8: 0112 lsls r2, r2, #4
+ 8001baa: b2d2 uxtb r2, r2
+ 8001bac: 440b add r3, r1
+ 8001bae: 761a strb r2, [r3, #24]
}
- 8001b34: bf00 nop
- 8001b36: 370c adds r7, #12
- 8001b38: 46bd mov sp, r7
- 8001b3a: f85d 7b04 ldr.w r7, [sp], #4
- 8001b3e: 4770 bx lr
- 8001b40: e000e100 .word 0xe000e100
- 8001b44: e000ed00 .word 0xe000ed00
-
-08001b48 <NVIC_EncodePriority>:
+ 8001bb0: bf00 nop
+ 8001bb2: 370c adds r7, #12
+ 8001bb4: 46bd mov sp, r7
+ 8001bb6: f85d 7b04 ldr.w r7, [sp], #4
+ 8001bba: 4770 bx lr
+ 8001bbc: e000e100 .word 0xe000e100
+ 8001bc0: e000ed00 .word 0xe000ed00
+
+08001bc4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- 8001b48: b480 push {r7}
- 8001b4a: b089 sub sp, #36 ; 0x24
- 8001b4c: af00 add r7, sp, #0
- 8001b4e: 60f8 str r0, [r7, #12]
- 8001b50: 60b9 str r1, [r7, #8]
- 8001b52: 607a str r2, [r7, #4]
+ 8001bc4: b480 push {r7}
+ 8001bc6: b089 sub sp, #36 ; 0x24
+ 8001bc8: af00 add r7, sp, #0
+ 8001bca: 60f8 str r0, [r7, #12]
+ 8001bcc: 60b9 str r1, [r7, #8]
+ 8001bce: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8001b54: 68fb ldr r3, [r7, #12]
- 8001b56: f003 0307 and.w r3, r3, #7
- 8001b5a: 61fb str r3, [r7, #28]
+ 8001bd0: 68fb ldr r3, [r7, #12]
+ 8001bd2: f003 0307 and.w r3, r3, #7
+ 8001bd6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8001b5c: 69fb ldr r3, [r7, #28]
- 8001b5e: f1c3 0307 rsb r3, r3, #7
- 8001b62: 2b04 cmp r3, #4
- 8001b64: bf28 it cs
- 8001b66: 2304 movcs r3, #4
- 8001b68: 61bb str r3, [r7, #24]
+ 8001bd8: 69fb ldr r3, [r7, #28]
+ 8001bda: f1c3 0307 rsb r3, r3, #7
+ 8001bde: 2b04 cmp r3, #4
+ 8001be0: bf28 it cs
+ 8001be2: 2304 movcs r3, #4
+ 8001be4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8001b6a: 69fb ldr r3, [r7, #28]
- 8001b6c: 3304 adds r3, #4
- 8001b6e: 2b06 cmp r3, #6
- 8001b70: d902 bls.n 8001b78 <NVIC_EncodePriority+0x30>
- 8001b72: 69fb ldr r3, [r7, #28]
- 8001b74: 3b03 subs r3, #3
- 8001b76: e000 b.n 8001b7a <NVIC_EncodePriority+0x32>
- 8001b78: 2300 movs r3, #0
- 8001b7a: 617b str r3, [r7, #20]
+ 8001be6: 69fb ldr r3, [r7, #28]
+ 8001be8: 3304 adds r3, #4
+ 8001bea: 2b06 cmp r3, #6
+ 8001bec: d902 bls.n 8001bf4 <NVIC_EncodePriority+0x30>
+ 8001bee: 69fb ldr r3, [r7, #28]
+ 8001bf0: 3b03 subs r3, #3
+ 8001bf2: e000 b.n 8001bf6 <NVIC_EncodePriority+0x32>
+ 8001bf4: 2300 movs r3, #0
+ 8001bf6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001b7c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8001b80: 69bb ldr r3, [r7, #24]
- 8001b82: fa02 f303 lsl.w r3, r2, r3
- 8001b86: 43da mvns r2, r3
- 8001b88: 68bb ldr r3, [r7, #8]
- 8001b8a: 401a ands r2, r3
- 8001b8c: 697b ldr r3, [r7, #20]
- 8001b8e: 409a lsls r2, r3
+ 8001bf8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 8001bfc: 69bb ldr r3, [r7, #24]
+ 8001bfe: fa02 f303 lsl.w r3, r2, r3
+ 8001c02: 43da mvns r2, r3
+ 8001c04: 68bb ldr r3, [r7, #8]
+ 8001c06: 401a ands r2, r3
+ 8001c08: 697b ldr r3, [r7, #20]
+ 8001c0a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8001b90: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 8001b94: 697b ldr r3, [r7, #20]
- 8001b96: fa01 f303 lsl.w r3, r1, r3
- 8001b9a: 43d9 mvns r1, r3
- 8001b9c: 687b ldr r3, [r7, #4]
- 8001b9e: 400b ands r3, r1
+ 8001c0c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
+ 8001c10: 697b ldr r3, [r7, #20]
+ 8001c12: fa01 f303 lsl.w r3, r1, r3
+ 8001c16: 43d9 mvns r1, r3
+ 8001c18: 687b ldr r3, [r7, #4]
+ 8001c1a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001ba0: 4313 orrs r3, r2
+ 8001c1c: 4313 orrs r3, r2
);
}
- 8001ba2: 4618 mov r0, r3
- 8001ba4: 3724 adds r7, #36 ; 0x24
- 8001ba6: 46bd mov sp, r7
- 8001ba8: f85d 7b04 ldr.w r7, [sp], #4
- 8001bac: 4770 bx lr
+ 8001c1e: 4618 mov r0, r3
+ 8001c20: 3724 adds r7, #36 ; 0x24
+ 8001c22: 46bd mov sp, r7
+ 8001c24: f85d 7b04 ldr.w r7, [sp], #4
+ 8001c28: 4770 bx lr
...
-08001bb0 <SysTick_Config>:
+08001c2c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- 8001bb0: b580 push {r7, lr}
- 8001bb2: b082 sub sp, #8
- 8001bb4: af00 add r7, sp, #0
- 8001bb6: 6078 str r0, [r7, #4]
+ 8001c2c: b580 push {r7, lr}
+ 8001c2e: b082 sub sp, #8
+ 8001c30: af00 add r7, sp, #0
+ 8001c32: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8001bb8: 687b ldr r3, [r7, #4]
- 8001bba: 3b01 subs r3, #1
- 8001bbc: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8001bc0: d301 bcc.n 8001bc6 <SysTick_Config+0x16>
+ 8001c34: 687b ldr r3, [r7, #4]
+ 8001c36: 3b01 subs r3, #1
+ 8001c38: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
+ 8001c3c: d301 bcc.n 8001c42 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
- 8001bc2: 2301 movs r3, #1
- 8001bc4: e00f b.n 8001be6 <SysTick_Config+0x36>
+ 8001c3e: 2301 movs r3, #1
+ 8001c40: e00f b.n 8001c62 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8001bc6: 4a0a ldr r2, [pc, #40] ; (8001bf0 <SysTick_Config+0x40>)
- 8001bc8: 687b ldr r3, [r7, #4]
- 8001bca: 3b01 subs r3, #1
- 8001bcc: 6053 str r3, [r2, #4]
+ 8001c42: 4a0a ldr r2, [pc, #40] ; (8001c6c <SysTick_Config+0x40>)
+ 8001c44: 687b ldr r3, [r7, #4]
+ 8001c46: 3b01 subs r3, #1
+ 8001c48: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8001bce: 210f movs r1, #15
- 8001bd0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8001bd4: f7ff ff8e bl 8001af4 <__NVIC_SetPriority>
+ 8001c4a: 210f movs r1, #15
+ 8001c4c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8001c50: f7ff ff8e bl 8001b70 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8001bd8: 4b05 ldr r3, [pc, #20] ; (8001bf0 <SysTick_Config+0x40>)
- 8001bda: 2200 movs r2, #0
- 8001bdc: 609a str r2, [r3, #8]
+ 8001c54: 4b05 ldr r3, [pc, #20] ; (8001c6c <SysTick_Config+0x40>)
+ 8001c56: 2200 movs r2, #0
+ 8001c58: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001bde: 4b04 ldr r3, [pc, #16] ; (8001bf0 <SysTick_Config+0x40>)
- 8001be0: 2207 movs r2, #7
- 8001be2: 601a str r2, [r3, #0]
+ 8001c5a: 4b04 ldr r3, [pc, #16] ; (8001c6c <SysTick_Config+0x40>)
+ 8001c5c: 2207 movs r2, #7
+ 8001c5e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
- 8001be4: 2300 movs r3, #0
+ 8001c60: 2300 movs r3, #0
}
- 8001be6: 4618 mov r0, r3
- 8001be8: 3708 adds r7, #8
- 8001bea: 46bd mov sp, r7
- 8001bec: bd80 pop {r7, pc}
- 8001bee: bf00 nop
- 8001bf0: e000e010 .word 0xe000e010
-
-08001bf4 <HAL_NVIC_SetPriorityGrouping>:
+ 8001c62: 4618 mov r0, r3
+ 8001c64: 3708 adds r7, #8
+ 8001c66: 46bd mov sp, r7
+ 8001c68: bd80 pop {r7, pc}
+ 8001c6a: bf00 nop
+ 8001c6c: e000e010 .word 0xe000e010
+
+08001c70 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
- 8001bf4: b580 push {r7, lr}
- 8001bf6: b082 sub sp, #8
- 8001bf8: af00 add r7, sp, #0
- 8001bfa: 6078 str r0, [r7, #4]
+ 8001c70: b580 push {r7, lr}
+ 8001c72: b082 sub sp, #8
+ 8001c74: af00 add r7, sp, #0
+ 8001c76: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
- 8001bfc: 6878 ldr r0, [r7, #4]
- 8001bfe: f7ff ff29 bl 8001a54 <__NVIC_SetPriorityGrouping>
+ 8001c78: 6878 ldr r0, [r7, #4]
+ 8001c7a: f7ff ff29 bl 8001ad0 <__NVIC_SetPriorityGrouping>
}
- 8001c02: bf00 nop
- 8001c04: 3708 adds r7, #8
- 8001c06: 46bd mov sp, r7
- 8001c08: bd80 pop {r7, pc}
+ 8001c7e: bf00 nop
+ 8001c80: 3708 adds r7, #8
+ 8001c82: 46bd mov sp, r7
+ 8001c84: bd80 pop {r7, pc}
-08001c0a <HAL_NVIC_SetPriority>:
+08001c86 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
- 8001c0a: b580 push {r7, lr}
- 8001c0c: b086 sub sp, #24
- 8001c0e: af00 add r7, sp, #0
- 8001c10: 4603 mov r3, r0
- 8001c12: 60b9 str r1, [r7, #8]
- 8001c14: 607a str r2, [r7, #4]
- 8001c16: 73fb strb r3, [r7, #15]
+ 8001c86: b580 push {r7, lr}
+ 8001c88: b086 sub sp, #24
+ 8001c8a: af00 add r7, sp, #0
+ 8001c8c: 4603 mov r3, r0
+ 8001c8e: 60b9 str r1, [r7, #8]
+ 8001c90: 607a str r2, [r7, #4]
+ 8001c92: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
- 8001c18: 2300 movs r3, #0
- 8001c1a: 617b str r3, [r7, #20]
+ 8001c94: 2300 movs r3, #0
+ 8001c96: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
- 8001c1c: f7ff ff3e bl 8001a9c <__NVIC_GetPriorityGrouping>
- 8001c20: 6178 str r0, [r7, #20]
+ 8001c98: f7ff ff3e bl 8001b18 <__NVIC_GetPriorityGrouping>
+ 8001c9c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8001c22: 687a ldr r2, [r7, #4]
- 8001c24: 68b9 ldr r1, [r7, #8]
- 8001c26: 6978 ldr r0, [r7, #20]
- 8001c28: f7ff ff8e bl 8001b48 <NVIC_EncodePriority>
- 8001c2c: 4602 mov r2, r0
- 8001c2e: f997 300f ldrsb.w r3, [r7, #15]
- 8001c32: 4611 mov r1, r2
- 8001c34: 4618 mov r0, r3
- 8001c36: f7ff ff5d bl 8001af4 <__NVIC_SetPriority>
+ 8001c9e: 687a ldr r2, [r7, #4]
+ 8001ca0: 68b9 ldr r1, [r7, #8]
+ 8001ca2: 6978 ldr r0, [r7, #20]
+ 8001ca4: f7ff ff8e bl 8001bc4 <NVIC_EncodePriority>
+ 8001ca8: 4602 mov r2, r0
+ 8001caa: f997 300f ldrsb.w r3, [r7, #15]
+ 8001cae: 4611 mov r1, r2
+ 8001cb0: 4618 mov r0, r3
+ 8001cb2: f7ff ff5d bl 8001b70 <__NVIC_SetPriority>
}
- 8001c3a: bf00 nop
- 8001c3c: 3718 adds r7, #24
- 8001c3e: 46bd mov sp, r7
- 8001c40: bd80 pop {r7, pc}
+ 8001cb6: bf00 nop
+ 8001cb8: 3718 adds r7, #24
+ 8001cba: 46bd mov sp, r7
+ 8001cbc: bd80 pop {r7, pc}
-08001c42 <HAL_NVIC_EnableIRQ>:
+08001cbe <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
- 8001c42: b580 push {r7, lr}
- 8001c44: b082 sub sp, #8
- 8001c46: af00 add r7, sp, #0
- 8001c48: 4603 mov r3, r0
- 8001c4a: 71fb strb r3, [r7, #7]
+ 8001cbe: b580 push {r7, lr}
+ 8001cc0: b082 sub sp, #8
+ 8001cc2: af00 add r7, sp, #0
+ 8001cc4: 4603 mov r3, r0
+ 8001cc6: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
- 8001c4c: f997 3007 ldrsb.w r3, [r7, #7]
- 8001c50: 4618 mov r0, r3
- 8001c52: f7ff ff31 bl 8001ab8 <__NVIC_EnableIRQ>
+ 8001cc8: f997 3007 ldrsb.w r3, [r7, #7]
+ 8001ccc: 4618 mov r0, r3
+ 8001cce: f7ff ff31 bl 8001b34 <__NVIC_EnableIRQ>
}
- 8001c56: bf00 nop
- 8001c58: 3708 adds r7, #8
- 8001c5a: 46bd mov sp, r7
- 8001c5c: bd80 pop {r7, pc}
+ 8001cd2: bf00 nop
+ 8001cd4: 3708 adds r7, #8
+ 8001cd6: 46bd mov sp, r7
+ 8001cd8: bd80 pop {r7, pc}
-08001c5e <HAL_SYSTICK_Config>:
+08001cda <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
- 8001c5e: b580 push {r7, lr}
- 8001c60: b082 sub sp, #8
- 8001c62: af00 add r7, sp, #0
- 8001c64: 6078 str r0, [r7, #4]
+ 8001cda: b580 push {r7, lr}
+ 8001cdc: b082 sub sp, #8
+ 8001cde: af00 add r7, sp, #0
+ 8001ce0: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
- 8001c66: 6878 ldr r0, [r7, #4]
- 8001c68: f7ff ffa2 bl 8001bb0 <SysTick_Config>
- 8001c6c: 4603 mov r3, r0
+ 8001ce2: 6878 ldr r0, [r7, #4]
+ 8001ce4: f7ff ffa2 bl 8001c2c <SysTick_Config>
+ 8001ce8: 4603 mov r3, r0
}
- 8001c6e: 4618 mov r0, r3
- 8001c70: 3708 adds r7, #8
- 8001c72: 46bd mov sp, r7
- 8001c74: bd80 pop {r7, pc}
+ 8001cea: 4618 mov r0, r3
+ 8001cec: 3708 adds r7, #8
+ 8001cee: 46bd mov sp, r7
+ 8001cf0: bd80 pop {r7, pc}
-08001c76 <HAL_DMA_Abort_IT>:
+08001cf2 <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
- 8001c76: b480 push {r7}
- 8001c78: b083 sub sp, #12
- 8001c7a: af00 add r7, sp, #0
- 8001c7c: 6078 str r0, [r7, #4]
+ 8001cf2: b480 push {r7}
+ 8001cf4: b083 sub sp, #12
+ 8001cf6: af00 add r7, sp, #0
+ 8001cf8: 6078 str r0, [r7, #4]
if(hdma->State != HAL_DMA_STATE_BUSY)
- 8001c7e: 687b ldr r3, [r7, #4]
- 8001c80: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
- 8001c84: b2db uxtb r3, r3
- 8001c86: 2b02 cmp r3, #2
- 8001c88: d004 beq.n 8001c94 <HAL_DMA_Abort_IT+0x1e>
+ 8001cfa: 687b ldr r3, [r7, #4]
+ 8001cfc: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
+ 8001d00: b2db uxtb r3, r3
+ 8001d02: 2b02 cmp r3, #2
+ 8001d04: d004 beq.n 8001d10 <HAL_DMA_Abort_IT+0x1e>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 8001c8a: 687b ldr r3, [r7, #4]
- 8001c8c: 2280 movs r2, #128 ; 0x80
- 8001c8e: 655a str r2, [r3, #84] ; 0x54
+ 8001d06: 687b ldr r3, [r7, #4]
+ 8001d08: 2280 movs r2, #128 ; 0x80
+ 8001d0a: 655a str r2, [r3, #84] ; 0x54
return HAL_ERROR;
- 8001c90: 2301 movs r3, #1
- 8001c92: e00c b.n 8001cae <HAL_DMA_Abort_IT+0x38>
+ 8001d0c: 2301 movs r3, #1
+ 8001d0e: e00c b.n 8001d2a <HAL_DMA_Abort_IT+0x38>
}
else
{
/* Set Abort State */
hdma->State = HAL_DMA_STATE_ABORT;
- 8001c94: 687b ldr r3, [r7, #4]
- 8001c96: 2205 movs r2, #5
- 8001c98: f883 2035 strb.w r2, [r3, #53] ; 0x35
+ 8001d10: 687b ldr r3, [r7, #4]
+ 8001d12: 2205 movs r2, #5
+ 8001d14: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
- 8001c9c: 687b ldr r3, [r7, #4]
- 8001c9e: 681b ldr r3, [r3, #0]
- 8001ca0: 681a ldr r2, [r3, #0]
- 8001ca2: 687b ldr r3, [r7, #4]
- 8001ca4: 681b ldr r3, [r3, #0]
- 8001ca6: f022 0201 bic.w r2, r2, #1
- 8001caa: 601a str r2, [r3, #0]
+ 8001d18: 687b ldr r3, [r7, #4]
+ 8001d1a: 681b ldr r3, [r3, #0]
+ 8001d1c: 681a ldr r2, [r3, #0]
+ 8001d1e: 687b ldr r3, [r7, #4]
+ 8001d20: 681b ldr r3, [r3, #0]
+ 8001d22: f022 0201 bic.w r2, r2, #1
+ 8001d26: 601a str r2, [r3, #0]
}
return HAL_OK;
- 8001cac: 2300 movs r3, #0
+ 8001d28: 2300 movs r3, #0
}
- 8001cae: 4618 mov r0, r3
- 8001cb0: 370c adds r7, #12
- 8001cb2: 46bd mov sp, r7
- 8001cb4: f85d 7b04 ldr.w r7, [sp], #4
- 8001cb8: 4770 bx lr
+ 8001d2a: 4618 mov r0, r3
+ 8001d2c: 370c adds r7, #12
+ 8001d2e: 46bd mov sp, r7
+ 8001d30: f85d 7b04 ldr.w r7, [sp], #4
+ 8001d34: 4770 bx lr
...
-08001cbc <HAL_GPIO_Init>:
+08001d38 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
- 8001cbc: b480 push {r7}
- 8001cbe: b089 sub sp, #36 ; 0x24
- 8001cc0: af00 add r7, sp, #0
- 8001cc2: 6078 str r0, [r7, #4]
- 8001cc4: 6039 str r1, [r7, #0]
+ 8001d38: b480 push {r7}
+ 8001d3a: b089 sub sp, #36 ; 0x24
+ 8001d3c: af00 add r7, sp, #0
+ 8001d3e: 6078 str r0, [r7, #4]
+ 8001d40: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
- 8001cc6: 2300 movs r3, #0
- 8001cc8: 61fb str r3, [r7, #28]
+ 8001d42: 2300 movs r3, #0
+ 8001d44: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
- 8001cca: 2300 movs r3, #0
- 8001ccc: 617b str r3, [r7, #20]
+ 8001d46: 2300 movs r3, #0
+ 8001d48: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
- 8001cce: 2300 movs r3, #0
- 8001cd0: 613b str r3, [r7, #16]
+ 8001d4a: 2300 movs r3, #0
+ 8001d4c: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
- 8001cd2: 2300 movs r3, #0
- 8001cd4: 61bb str r3, [r7, #24]
+ 8001d4e: 2300 movs r3, #0
+ 8001d50: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
- 8001cd6: 2300 movs r3, #0
- 8001cd8: 61fb str r3, [r7, #28]
- 8001cda: e175 b.n 8001fc8 <HAL_GPIO_Init+0x30c>
+ 8001d52: 2300 movs r3, #0
+ 8001d54: 61fb str r3, [r7, #28]
+ 8001d56: e175 b.n 8002044 <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
- 8001cdc: 2201 movs r2, #1
- 8001cde: 69fb ldr r3, [r7, #28]
- 8001ce0: fa02 f303 lsl.w r3, r2, r3
- 8001ce4: 617b str r3, [r7, #20]
+ 8001d58: 2201 movs r2, #1
+ 8001d5a: 69fb ldr r3, [r7, #28]
+ 8001d5c: fa02 f303 lsl.w r3, r2, r3
+ 8001d60: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8001ce6: 683b ldr r3, [r7, #0]
- 8001ce8: 681b ldr r3, [r3, #0]
- 8001cea: 697a ldr r2, [r7, #20]
- 8001cec: 4013 ands r3, r2
- 8001cee: 613b str r3, [r7, #16]
+ 8001d62: 683b ldr r3, [r7, #0]
+ 8001d64: 681b ldr r3, [r3, #0]
+ 8001d66: 697a ldr r2, [r7, #20]
+ 8001d68: 4013 ands r3, r2
+ 8001d6a: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
- 8001cf0: 693a ldr r2, [r7, #16]
- 8001cf2: 697b ldr r3, [r7, #20]
- 8001cf4: 429a cmp r2, r3
- 8001cf6: f040 8164 bne.w 8001fc2 <HAL_GPIO_Init+0x306>
+ 8001d6c: 693a ldr r2, [r7, #16]
+ 8001d6e: 697b ldr r3, [r7, #20]
+ 8001d70: 429a cmp r2, r3
+ 8001d72: f040 8164 bne.w 800203e <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8001cfa: 683b ldr r3, [r7, #0]
- 8001cfc: 685b ldr r3, [r3, #4]
- 8001cfe: 2b02 cmp r3, #2
- 8001d00: d003 beq.n 8001d0a <HAL_GPIO_Init+0x4e>
- 8001d02: 683b ldr r3, [r7, #0]
- 8001d04: 685b ldr r3, [r3, #4]
- 8001d06: 2b12 cmp r3, #18
- 8001d08: d123 bne.n 8001d52 <HAL_GPIO_Init+0x96>
+ 8001d76: 683b ldr r3, [r7, #0]
+ 8001d78: 685b ldr r3, [r3, #4]
+ 8001d7a: 2b02 cmp r3, #2
+ 8001d7c: d003 beq.n 8001d86 <HAL_GPIO_Init+0x4e>
+ 8001d7e: 683b ldr r3, [r7, #0]
+ 8001d80: 685b ldr r3, [r3, #4]
+ 8001d82: 2b12 cmp r3, #18
+ 8001d84: d123 bne.n 8001dce <HAL_GPIO_Init+0x96>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
- 8001d0a: 69fb ldr r3, [r7, #28]
- 8001d0c: 08da lsrs r2, r3, #3
- 8001d0e: 687b ldr r3, [r7, #4]
- 8001d10: 3208 adds r2, #8
- 8001d12: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 8001d16: 61bb str r3, [r7, #24]
+ 8001d86: 69fb ldr r3, [r7, #28]
+ 8001d88: 08da lsrs r2, r3, #3
+ 8001d8a: 687b ldr r3, [r7, #4]
+ 8001d8c: 3208 adds r2, #8
+ 8001d8e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
+ 8001d92: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 8001d18: 69fb ldr r3, [r7, #28]
- 8001d1a: f003 0307 and.w r3, r3, #7
- 8001d1e: 009b lsls r3, r3, #2
- 8001d20: 220f movs r2, #15
- 8001d22: fa02 f303 lsl.w r3, r2, r3
- 8001d26: 43db mvns r3, r3
- 8001d28: 69ba ldr r2, [r7, #24]
- 8001d2a: 4013 ands r3, r2
- 8001d2c: 61bb str r3, [r7, #24]
+ 8001d94: 69fb ldr r3, [r7, #28]
+ 8001d96: f003 0307 and.w r3, r3, #7
+ 8001d9a: 009b lsls r3, r3, #2
+ 8001d9c: 220f movs r2, #15
+ 8001d9e: fa02 f303 lsl.w r3, r2, r3
+ 8001da2: 43db mvns r3, r3
+ 8001da4: 69ba ldr r2, [r7, #24]
+ 8001da6: 4013 ands r3, r2
+ 8001da8: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 8001d2e: 683b ldr r3, [r7, #0]
- 8001d30: 691a ldr r2, [r3, #16]
- 8001d32: 69fb ldr r3, [r7, #28]
- 8001d34: f003 0307 and.w r3, r3, #7
- 8001d38: 009b lsls r3, r3, #2
- 8001d3a: fa02 f303 lsl.w r3, r2, r3
- 8001d3e: 69ba ldr r2, [r7, #24]
- 8001d40: 4313 orrs r3, r2
- 8001d42: 61bb str r3, [r7, #24]
+ 8001daa: 683b ldr r3, [r7, #0]
+ 8001dac: 691a ldr r2, [r3, #16]
+ 8001dae: 69fb ldr r3, [r7, #28]
+ 8001db0: f003 0307 and.w r3, r3, #7
+ 8001db4: 009b lsls r3, r3, #2
+ 8001db6: fa02 f303 lsl.w r3, r2, r3
+ 8001dba: 69ba ldr r2, [r7, #24]
+ 8001dbc: 4313 orrs r3, r2
+ 8001dbe: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
- 8001d44: 69fb ldr r3, [r7, #28]
- 8001d46: 08da lsrs r2, r3, #3
- 8001d48: 687b ldr r3, [r7, #4]
- 8001d4a: 3208 adds r2, #8
- 8001d4c: 69b9 ldr r1, [r7, #24]
- 8001d4e: f843 1022 str.w r1, [r3, r2, lsl #2]
+ 8001dc0: 69fb ldr r3, [r7, #28]
+ 8001dc2: 08da lsrs r2, r3, #3
+ 8001dc4: 687b ldr r3, [r7, #4]
+ 8001dc6: 3208 adds r2, #8
+ 8001dc8: 69b9 ldr r1, [r7, #24]
+ 8001dca: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
- 8001d52: 687b ldr r3, [r7, #4]
- 8001d54: 681b ldr r3, [r3, #0]
- 8001d56: 61bb str r3, [r7, #24]
+ 8001dce: 687b ldr r3, [r7, #4]
+ 8001dd0: 681b ldr r3, [r3, #0]
+ 8001dd2: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 8001d58: 69fb ldr r3, [r7, #28]
- 8001d5a: 005b lsls r3, r3, #1
- 8001d5c: 2203 movs r2, #3
- 8001d5e: fa02 f303 lsl.w r3, r2, r3
- 8001d62: 43db mvns r3, r3
- 8001d64: 69ba ldr r2, [r7, #24]
- 8001d66: 4013 ands r3, r2
- 8001d68: 61bb str r3, [r7, #24]
+ 8001dd4: 69fb ldr r3, [r7, #28]
+ 8001dd6: 005b lsls r3, r3, #1
+ 8001dd8: 2203 movs r2, #3
+ 8001dda: fa02 f303 lsl.w r3, r2, r3
+ 8001dde: 43db mvns r3, r3
+ 8001de0: 69ba ldr r2, [r7, #24]
+ 8001de2: 4013 ands r3, r2
+ 8001de4: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 8001d6a: 683b ldr r3, [r7, #0]
- 8001d6c: 685b ldr r3, [r3, #4]
- 8001d6e: f003 0203 and.w r2, r3, #3
- 8001d72: 69fb ldr r3, [r7, #28]
- 8001d74: 005b lsls r3, r3, #1
- 8001d76: fa02 f303 lsl.w r3, r2, r3
- 8001d7a: 69ba ldr r2, [r7, #24]
- 8001d7c: 4313 orrs r3, r2
- 8001d7e: 61bb str r3, [r7, #24]
+ 8001de6: 683b ldr r3, [r7, #0]
+ 8001de8: 685b ldr r3, [r3, #4]
+ 8001dea: f003 0203 and.w r2, r3, #3
+ 8001dee: 69fb ldr r3, [r7, #28]
+ 8001df0: 005b lsls r3, r3, #1
+ 8001df2: fa02 f303 lsl.w r3, r2, r3
+ 8001df6: 69ba ldr r2, [r7, #24]
+ 8001df8: 4313 orrs r3, r2
+ 8001dfa: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
- 8001d80: 687b ldr r3, [r7, #4]
- 8001d82: 69ba ldr r2, [r7, #24]
- 8001d84: 601a str r2, [r3, #0]
+ 8001dfc: 687b ldr r3, [r7, #4]
+ 8001dfe: 69ba ldr r2, [r7, #24]
+ 8001e00: 601a str r2, [r3, #0]
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8001d86: 683b ldr r3, [r7, #0]
- 8001d88: 685b ldr r3, [r3, #4]
- 8001d8a: 2b01 cmp r3, #1
- 8001d8c: d00b beq.n 8001da6 <HAL_GPIO_Init+0xea>
- 8001d8e: 683b ldr r3, [r7, #0]
- 8001d90: 685b ldr r3, [r3, #4]
- 8001d92: 2b02 cmp r3, #2
- 8001d94: d007 beq.n 8001da6 <HAL_GPIO_Init+0xea>
+ 8001e02: 683b ldr r3, [r7, #0]
+ 8001e04: 685b ldr r3, [r3, #4]
+ 8001e06: 2b01 cmp r3, #1
+ 8001e08: d00b beq.n 8001e22 <HAL_GPIO_Init+0xea>
+ 8001e0a: 683b ldr r3, [r7, #0]
+ 8001e0c: 685b ldr r3, [r3, #4]
+ 8001e0e: 2b02 cmp r3, #2
+ 8001e10: d007 beq.n 8001e22 <HAL_GPIO_Init+0xea>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8001d96: 683b ldr r3, [r7, #0]
- 8001d98: 685b ldr r3, [r3, #4]
+ 8001e12: 683b ldr r3, [r7, #0]
+ 8001e14: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8001d9a: 2b11 cmp r3, #17
- 8001d9c: d003 beq.n 8001da6 <HAL_GPIO_Init+0xea>
+ 8001e16: 2b11 cmp r3, #17
+ 8001e18: d003 beq.n 8001e22 <HAL_GPIO_Init+0xea>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8001d9e: 683b ldr r3, [r7, #0]
- 8001da0: 685b ldr r3, [r3, #4]
- 8001da2: 2b12 cmp r3, #18
- 8001da4: d130 bne.n 8001e08 <HAL_GPIO_Init+0x14c>
+ 8001e1a: 683b ldr r3, [r7, #0]
+ 8001e1c: 685b ldr r3, [r3, #4]
+ 8001e1e: 2b12 cmp r3, #18
+ 8001e20: d130 bne.n 8001e84 <HAL_GPIO_Init+0x14c>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
- 8001da6: 687b ldr r3, [r7, #4]
- 8001da8: 689b ldr r3, [r3, #8]
- 8001daa: 61bb str r3, [r7, #24]
+ 8001e22: 687b ldr r3, [r7, #4]
+ 8001e24: 689b ldr r3, [r3, #8]
+ 8001e26: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8001dac: 69fb ldr r3, [r7, #28]
- 8001dae: 005b lsls r3, r3, #1
- 8001db0: 2203 movs r2, #3
- 8001db2: fa02 f303 lsl.w r3, r2, r3
- 8001db6: 43db mvns r3, r3
- 8001db8: 69ba ldr r2, [r7, #24]
- 8001dba: 4013 ands r3, r2
- 8001dbc: 61bb str r3, [r7, #24]
+ 8001e28: 69fb ldr r3, [r7, #28]
+ 8001e2a: 005b lsls r3, r3, #1
+ 8001e2c: 2203 movs r2, #3
+ 8001e2e: fa02 f303 lsl.w r3, r2, r3
+ 8001e32: 43db mvns r3, r3
+ 8001e34: 69ba ldr r2, [r7, #24]
+ 8001e36: 4013 ands r3, r2
+ 8001e38: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
- 8001dbe: 683b ldr r3, [r7, #0]
- 8001dc0: 68da ldr r2, [r3, #12]
- 8001dc2: 69fb ldr r3, [r7, #28]
- 8001dc4: 005b lsls r3, r3, #1
- 8001dc6: fa02 f303 lsl.w r3, r2, r3
- 8001dca: 69ba ldr r2, [r7, #24]
- 8001dcc: 4313 orrs r3, r2
- 8001dce: 61bb str r3, [r7, #24]
+ 8001e3a: 683b ldr r3, [r7, #0]
+ 8001e3c: 68da ldr r2, [r3, #12]
+ 8001e3e: 69fb ldr r3, [r7, #28]
+ 8001e40: 005b lsls r3, r3, #1
+ 8001e42: fa02 f303 lsl.w r3, r2, r3
+ 8001e46: 69ba ldr r2, [r7, #24]
+ 8001e48: 4313 orrs r3, r2
+ 8001e4a: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
- 8001dd0: 687b ldr r3, [r7, #4]
- 8001dd2: 69ba ldr r2, [r7, #24]
- 8001dd4: 609a str r2, [r3, #8]
+ 8001e4c: 687b ldr r3, [r7, #4]
+ 8001e4e: 69ba ldr r2, [r7, #24]
+ 8001e50: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
- 8001dd6: 687b ldr r3, [r7, #4]
- 8001dd8: 685b ldr r3, [r3, #4]
- 8001dda: 61bb str r3, [r7, #24]
+ 8001e52: 687b ldr r3, [r7, #4]
+ 8001e54: 685b ldr r3, [r3, #4]
+ 8001e56: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8001ddc: 2201 movs r2, #1
- 8001dde: 69fb ldr r3, [r7, #28]
- 8001de0: fa02 f303 lsl.w r3, r2, r3
- 8001de4: 43db mvns r3, r3
- 8001de6: 69ba ldr r2, [r7, #24]
- 8001de8: 4013 ands r3, r2
- 8001dea: 61bb str r3, [r7, #24]
+ 8001e58: 2201 movs r2, #1
+ 8001e5a: 69fb ldr r3, [r7, #28]
+ 8001e5c: fa02 f303 lsl.w r3, r2, r3
+ 8001e60: 43db mvns r3, r3
+ 8001e62: 69ba ldr r2, [r7, #24]
+ 8001e64: 4013 ands r3, r2
+ 8001e66: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 8001dec: 683b ldr r3, [r7, #0]
- 8001dee: 685b ldr r3, [r3, #4]
- 8001df0: 091b lsrs r3, r3, #4
- 8001df2: f003 0201 and.w r2, r3, #1
- 8001df6: 69fb ldr r3, [r7, #28]
- 8001df8: fa02 f303 lsl.w r3, r2, r3
- 8001dfc: 69ba ldr r2, [r7, #24]
- 8001dfe: 4313 orrs r3, r2
- 8001e00: 61bb str r3, [r7, #24]
+ 8001e68: 683b ldr r3, [r7, #0]
+ 8001e6a: 685b ldr r3, [r3, #4]
+ 8001e6c: 091b lsrs r3, r3, #4
+ 8001e6e: f003 0201 and.w r2, r3, #1
+ 8001e72: 69fb ldr r3, [r7, #28]
+ 8001e74: fa02 f303 lsl.w r3, r2, r3
+ 8001e78: 69ba ldr r2, [r7, #24]
+ 8001e7a: 4313 orrs r3, r2
+ 8001e7c: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
- 8001e02: 687b ldr r3, [r7, #4]
- 8001e04: 69ba ldr r2, [r7, #24]
- 8001e06: 605a str r2, [r3, #4]
+ 8001e7e: 687b ldr r3, [r7, #4]
+ 8001e80: 69ba ldr r2, [r7, #24]
+ 8001e82: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
- 8001e08: 687b ldr r3, [r7, #4]
- 8001e0a: 68db ldr r3, [r3, #12]
- 8001e0c: 61bb str r3, [r7, #24]
+ 8001e84: 687b ldr r3, [r7, #4]
+ 8001e86: 68db ldr r3, [r3, #12]
+ 8001e88: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 8001e0e: 69fb ldr r3, [r7, #28]
- 8001e10: 005b lsls r3, r3, #1
- 8001e12: 2203 movs r2, #3
- 8001e14: fa02 f303 lsl.w r3, r2, r3
- 8001e18: 43db mvns r3, r3
- 8001e1a: 69ba ldr r2, [r7, #24]
- 8001e1c: 4013 ands r3, r2
- 8001e1e: 61bb str r3, [r7, #24]
+ 8001e8a: 69fb ldr r3, [r7, #28]
+ 8001e8c: 005b lsls r3, r3, #1
+ 8001e8e: 2203 movs r2, #3
+ 8001e90: fa02 f303 lsl.w r3, r2, r3
+ 8001e94: 43db mvns r3, r3
+ 8001e96: 69ba ldr r2, [r7, #24]
+ 8001e98: 4013 ands r3, r2
+ 8001e9a: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
- 8001e20: 683b ldr r3, [r7, #0]
- 8001e22: 689a ldr r2, [r3, #8]
- 8001e24: 69fb ldr r3, [r7, #28]
- 8001e26: 005b lsls r3, r3, #1
- 8001e28: fa02 f303 lsl.w r3, r2, r3
- 8001e2c: 69ba ldr r2, [r7, #24]
- 8001e2e: 4313 orrs r3, r2
- 8001e30: 61bb str r3, [r7, #24]
+ 8001e9c: 683b ldr r3, [r7, #0]
+ 8001e9e: 689a ldr r2, [r3, #8]
+ 8001ea0: 69fb ldr r3, [r7, #28]
+ 8001ea2: 005b lsls r3, r3, #1
+ 8001ea4: fa02 f303 lsl.w r3, r2, r3
+ 8001ea8: 69ba ldr r2, [r7, #24]
+ 8001eaa: 4313 orrs r3, r2
+ 8001eac: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
- 8001e32: 687b ldr r3, [r7, #4]
- 8001e34: 69ba ldr r2, [r7, #24]
- 8001e36: 60da str r2, [r3, #12]
+ 8001eae: 687b ldr r3, [r7, #4]
+ 8001eb0: 69ba ldr r2, [r7, #24]
+ 8001eb2: 60da str r2, [r3, #12]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 8001e38: 683b ldr r3, [r7, #0]
- 8001e3a: 685b ldr r3, [r3, #4]
- 8001e3c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001e40: 2b00 cmp r3, #0
- 8001e42: f000 80be beq.w 8001fc2 <HAL_GPIO_Init+0x306>
+ 8001eb4: 683b ldr r3, [r7, #0]
+ 8001eb6: 685b ldr r3, [r3, #4]
+ 8001eb8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001ebc: 2b00 cmp r3, #0
+ 8001ebe: f000 80be beq.w 800203e <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 8001e46: 4b65 ldr r3, [pc, #404] ; (8001fdc <HAL_GPIO_Init+0x320>)
- 8001e48: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001e4a: 4a64 ldr r2, [pc, #400] ; (8001fdc <HAL_GPIO_Init+0x320>)
- 8001e4c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8001e50: 6453 str r3, [r2, #68] ; 0x44
- 8001e52: 4b62 ldr r3, [pc, #392] ; (8001fdc <HAL_GPIO_Init+0x320>)
- 8001e54: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001e56: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8001e5a: 60fb str r3, [r7, #12]
- 8001e5c: 68fb ldr r3, [r7, #12]
+ 8001ec2: 4b65 ldr r3, [pc, #404] ; (8002058 <HAL_GPIO_Init+0x320>)
+ 8001ec4: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001ec6: 4a64 ldr r2, [pc, #400] ; (8002058 <HAL_GPIO_Init+0x320>)
+ 8001ec8: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8001ecc: 6453 str r3, [r2, #68] ; 0x44
+ 8001ece: 4b62 ldr r3, [pc, #392] ; (8002058 <HAL_GPIO_Init+0x320>)
+ 8001ed0: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001ed2: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8001ed6: 60fb str r3, [r7, #12]
+ 8001ed8: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
- 8001e5e: 4a60 ldr r2, [pc, #384] ; (8001fe0 <HAL_GPIO_Init+0x324>)
- 8001e60: 69fb ldr r3, [r7, #28]
- 8001e62: 089b lsrs r3, r3, #2
- 8001e64: 3302 adds r3, #2
- 8001e66: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 8001e6a: 61bb str r3, [r7, #24]
+ 8001eda: 4a60 ldr r2, [pc, #384] ; (800205c <HAL_GPIO_Init+0x324>)
+ 8001edc: 69fb ldr r3, [r7, #28]
+ 8001ede: 089b lsrs r3, r3, #2
+ 8001ee0: 3302 adds r3, #2
+ 8001ee2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
+ 8001ee6: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 8001e6c: 69fb ldr r3, [r7, #28]
- 8001e6e: f003 0303 and.w r3, r3, #3
- 8001e72: 009b lsls r3, r3, #2
- 8001e74: 220f movs r2, #15
- 8001e76: fa02 f303 lsl.w r3, r2, r3
- 8001e7a: 43db mvns r3, r3
- 8001e7c: 69ba ldr r2, [r7, #24]
- 8001e7e: 4013 ands r3, r2
- 8001e80: 61bb str r3, [r7, #24]
+ 8001ee8: 69fb ldr r3, [r7, #28]
+ 8001eea: f003 0303 and.w r3, r3, #3
+ 8001eee: 009b lsls r3, r3, #2
+ 8001ef0: 220f movs r2, #15
+ 8001ef2: fa02 f303 lsl.w r3, r2, r3
+ 8001ef6: 43db mvns r3, r3
+ 8001ef8: 69ba ldr r2, [r7, #24]
+ 8001efa: 4013 ands r3, r2
+ 8001efc: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 8001e82: 687b ldr r3, [r7, #4]
- 8001e84: 4a57 ldr r2, [pc, #348] ; (8001fe4 <HAL_GPIO_Init+0x328>)
- 8001e86: 4293 cmp r3, r2
- 8001e88: d037 beq.n 8001efa <HAL_GPIO_Init+0x23e>
- 8001e8a: 687b ldr r3, [r7, #4]
- 8001e8c: 4a56 ldr r2, [pc, #344] ; (8001fe8 <HAL_GPIO_Init+0x32c>)
- 8001e8e: 4293 cmp r3, r2
- 8001e90: d031 beq.n 8001ef6 <HAL_GPIO_Init+0x23a>
- 8001e92: 687b ldr r3, [r7, #4]
- 8001e94: 4a55 ldr r2, [pc, #340] ; (8001fec <HAL_GPIO_Init+0x330>)
- 8001e96: 4293 cmp r3, r2
- 8001e98: d02b beq.n 8001ef2 <HAL_GPIO_Init+0x236>
- 8001e9a: 687b ldr r3, [r7, #4]
- 8001e9c: 4a54 ldr r2, [pc, #336] ; (8001ff0 <HAL_GPIO_Init+0x334>)
- 8001e9e: 4293 cmp r3, r2
- 8001ea0: d025 beq.n 8001eee <HAL_GPIO_Init+0x232>
- 8001ea2: 687b ldr r3, [r7, #4]
- 8001ea4: 4a53 ldr r2, [pc, #332] ; (8001ff4 <HAL_GPIO_Init+0x338>)
- 8001ea6: 4293 cmp r3, r2
- 8001ea8: d01f beq.n 8001eea <HAL_GPIO_Init+0x22e>
- 8001eaa: 687b ldr r3, [r7, #4]
- 8001eac: 4a52 ldr r2, [pc, #328] ; (8001ff8 <HAL_GPIO_Init+0x33c>)
- 8001eae: 4293 cmp r3, r2
- 8001eb0: d019 beq.n 8001ee6 <HAL_GPIO_Init+0x22a>
- 8001eb2: 687b ldr r3, [r7, #4]
- 8001eb4: 4a51 ldr r2, [pc, #324] ; (8001ffc <HAL_GPIO_Init+0x340>)
- 8001eb6: 4293 cmp r3, r2
- 8001eb8: d013 beq.n 8001ee2 <HAL_GPIO_Init+0x226>
- 8001eba: 687b ldr r3, [r7, #4]
- 8001ebc: 4a50 ldr r2, [pc, #320] ; (8002000 <HAL_GPIO_Init+0x344>)
- 8001ebe: 4293 cmp r3, r2
- 8001ec0: d00d beq.n 8001ede <HAL_GPIO_Init+0x222>
- 8001ec2: 687b ldr r3, [r7, #4]
- 8001ec4: 4a4f ldr r2, [pc, #316] ; (8002004 <HAL_GPIO_Init+0x348>)
- 8001ec6: 4293 cmp r3, r2
- 8001ec8: d007 beq.n 8001eda <HAL_GPIO_Init+0x21e>
- 8001eca: 687b ldr r3, [r7, #4]
- 8001ecc: 4a4e ldr r2, [pc, #312] ; (8002008 <HAL_GPIO_Init+0x34c>)
- 8001ece: 4293 cmp r3, r2
- 8001ed0: d101 bne.n 8001ed6 <HAL_GPIO_Init+0x21a>
- 8001ed2: 2309 movs r3, #9
- 8001ed4: e012 b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001ed6: 230a movs r3, #10
- 8001ed8: e010 b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001eda: 2308 movs r3, #8
- 8001edc: e00e b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001ede: 2307 movs r3, #7
- 8001ee0: e00c b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001ee2: 2306 movs r3, #6
- 8001ee4: e00a b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001ee6: 2305 movs r3, #5
- 8001ee8: e008 b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001eea: 2304 movs r3, #4
- 8001eec: e006 b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001eee: 2303 movs r3, #3
- 8001ef0: e004 b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001ef2: 2302 movs r3, #2
- 8001ef4: e002 b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001ef6: 2301 movs r3, #1
- 8001ef8: e000 b.n 8001efc <HAL_GPIO_Init+0x240>
- 8001efa: 2300 movs r3, #0
- 8001efc: 69fa ldr r2, [r7, #28]
- 8001efe: f002 0203 and.w r2, r2, #3
- 8001f02: 0092 lsls r2, r2, #2
- 8001f04: 4093 lsls r3, r2
- 8001f06: 69ba ldr r2, [r7, #24]
- 8001f08: 4313 orrs r3, r2
- 8001f0a: 61bb str r3, [r7, #24]
+ 8001efe: 687b ldr r3, [r7, #4]
+ 8001f00: 4a57 ldr r2, [pc, #348] ; (8002060 <HAL_GPIO_Init+0x328>)
+ 8001f02: 4293 cmp r3, r2
+ 8001f04: d037 beq.n 8001f76 <HAL_GPIO_Init+0x23e>
+ 8001f06: 687b ldr r3, [r7, #4]
+ 8001f08: 4a56 ldr r2, [pc, #344] ; (8002064 <HAL_GPIO_Init+0x32c>)
+ 8001f0a: 4293 cmp r3, r2
+ 8001f0c: d031 beq.n 8001f72 <HAL_GPIO_Init+0x23a>
+ 8001f0e: 687b ldr r3, [r7, #4]
+ 8001f10: 4a55 ldr r2, [pc, #340] ; (8002068 <HAL_GPIO_Init+0x330>)
+ 8001f12: 4293 cmp r3, r2
+ 8001f14: d02b beq.n 8001f6e <HAL_GPIO_Init+0x236>
+ 8001f16: 687b ldr r3, [r7, #4]
+ 8001f18: 4a54 ldr r2, [pc, #336] ; (800206c <HAL_GPIO_Init+0x334>)
+ 8001f1a: 4293 cmp r3, r2
+ 8001f1c: d025 beq.n 8001f6a <HAL_GPIO_Init+0x232>
+ 8001f1e: 687b ldr r3, [r7, #4]
+ 8001f20: 4a53 ldr r2, [pc, #332] ; (8002070 <HAL_GPIO_Init+0x338>)
+ 8001f22: 4293 cmp r3, r2
+ 8001f24: d01f beq.n 8001f66 <HAL_GPIO_Init+0x22e>
+ 8001f26: 687b ldr r3, [r7, #4]
+ 8001f28: 4a52 ldr r2, [pc, #328] ; (8002074 <HAL_GPIO_Init+0x33c>)
+ 8001f2a: 4293 cmp r3, r2
+ 8001f2c: d019 beq.n 8001f62 <HAL_GPIO_Init+0x22a>
+ 8001f2e: 687b ldr r3, [r7, #4]
+ 8001f30: 4a51 ldr r2, [pc, #324] ; (8002078 <HAL_GPIO_Init+0x340>)
+ 8001f32: 4293 cmp r3, r2
+ 8001f34: d013 beq.n 8001f5e <HAL_GPIO_Init+0x226>
+ 8001f36: 687b ldr r3, [r7, #4]
+ 8001f38: 4a50 ldr r2, [pc, #320] ; (800207c <HAL_GPIO_Init+0x344>)
+ 8001f3a: 4293 cmp r3, r2
+ 8001f3c: d00d beq.n 8001f5a <HAL_GPIO_Init+0x222>
+ 8001f3e: 687b ldr r3, [r7, #4]
+ 8001f40: 4a4f ldr r2, [pc, #316] ; (8002080 <HAL_GPIO_Init+0x348>)
+ 8001f42: 4293 cmp r3, r2
+ 8001f44: d007 beq.n 8001f56 <HAL_GPIO_Init+0x21e>
+ 8001f46: 687b ldr r3, [r7, #4]
+ 8001f48: 4a4e ldr r2, [pc, #312] ; (8002084 <HAL_GPIO_Init+0x34c>)
+ 8001f4a: 4293 cmp r3, r2
+ 8001f4c: d101 bne.n 8001f52 <HAL_GPIO_Init+0x21a>
+ 8001f4e: 2309 movs r3, #9
+ 8001f50: e012 b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f52: 230a movs r3, #10
+ 8001f54: e010 b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f56: 2308 movs r3, #8
+ 8001f58: e00e b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f5a: 2307 movs r3, #7
+ 8001f5c: e00c b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f5e: 2306 movs r3, #6
+ 8001f60: e00a b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f62: 2305 movs r3, #5
+ 8001f64: e008 b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f66: 2304 movs r3, #4
+ 8001f68: e006 b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f6a: 2303 movs r3, #3
+ 8001f6c: e004 b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f6e: 2302 movs r3, #2
+ 8001f70: e002 b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f72: 2301 movs r3, #1
+ 8001f74: e000 b.n 8001f78 <HAL_GPIO_Init+0x240>
+ 8001f76: 2300 movs r3, #0
+ 8001f78: 69fa ldr r2, [r7, #28]
+ 8001f7a: f002 0203 and.w r2, r2, #3
+ 8001f7e: 0092 lsls r2, r2, #2
+ 8001f80: 4093 lsls r3, r2
+ 8001f82: 69ba ldr r2, [r7, #24]
+ 8001f84: 4313 orrs r3, r2
+ 8001f86: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
- 8001f0c: 4934 ldr r1, [pc, #208] ; (8001fe0 <HAL_GPIO_Init+0x324>)
- 8001f0e: 69fb ldr r3, [r7, #28]
- 8001f10: 089b lsrs r3, r3, #2
- 8001f12: 3302 adds r3, #2
- 8001f14: 69ba ldr r2, [r7, #24]
- 8001f16: f841 2023 str.w r2, [r1, r3, lsl #2]
+ 8001f88: 4934 ldr r1, [pc, #208] ; (800205c <HAL_GPIO_Init+0x324>)
+ 8001f8a: 69fb ldr r3, [r7, #28]
+ 8001f8c: 089b lsrs r3, r3, #2
+ 8001f8e: 3302 adds r3, #2
+ 8001f90: 69ba ldr r2, [r7, #24]
+ 8001f92: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
- 8001f1a: 4b3c ldr r3, [pc, #240] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001f1c: 681b ldr r3, [r3, #0]
- 8001f1e: 61bb str r3, [r7, #24]
+ 8001f96: 4b3c ldr r3, [pc, #240] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 8001f98: 681b ldr r3, [r3, #0]
+ 8001f9a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8001f20: 693b ldr r3, [r7, #16]
- 8001f22: 43db mvns r3, r3
- 8001f24: 69ba ldr r2, [r7, #24]
- 8001f26: 4013 ands r3, r2
- 8001f28: 61bb str r3, [r7, #24]
+ 8001f9c: 693b ldr r3, [r7, #16]
+ 8001f9e: 43db mvns r3, r3
+ 8001fa0: 69ba ldr r2, [r7, #24]
+ 8001fa2: 4013 ands r3, r2
+ 8001fa4: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 8001f2a: 683b ldr r3, [r7, #0]
- 8001f2c: 685b ldr r3, [r3, #4]
- 8001f2e: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8001f32: 2b00 cmp r3, #0
- 8001f34: d003 beq.n 8001f3e <HAL_GPIO_Init+0x282>
+ 8001fa6: 683b ldr r3, [r7, #0]
+ 8001fa8: 685b ldr r3, [r3, #4]
+ 8001faa: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8001fae: 2b00 cmp r3, #0
+ 8001fb0: d003 beq.n 8001fba <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
- 8001f36: 69ba ldr r2, [r7, #24]
- 8001f38: 693b ldr r3, [r7, #16]
- 8001f3a: 4313 orrs r3, r2
- 8001f3c: 61bb str r3, [r7, #24]
+ 8001fb2: 69ba ldr r2, [r7, #24]
+ 8001fb4: 693b ldr r3, [r7, #16]
+ 8001fb6: 4313 orrs r3, r2
+ 8001fb8: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
- 8001f3e: 4a33 ldr r2, [pc, #204] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001f40: 69bb ldr r3, [r7, #24]
- 8001f42: 6013 str r3, [r2, #0]
+ 8001fba: 4a33 ldr r2, [pc, #204] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 8001fbc: 69bb ldr r3, [r7, #24]
+ 8001fbe: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
- 8001f44: 4b31 ldr r3, [pc, #196] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001f46: 685b ldr r3, [r3, #4]
- 8001f48: 61bb str r3, [r7, #24]
+ 8001fc0: 4b31 ldr r3, [pc, #196] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 8001fc2: 685b ldr r3, [r3, #4]
+ 8001fc4: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8001f4a: 693b ldr r3, [r7, #16]
- 8001f4c: 43db mvns r3, r3
- 8001f4e: 69ba ldr r2, [r7, #24]
- 8001f50: 4013 ands r3, r2
- 8001f52: 61bb str r3, [r7, #24]
+ 8001fc6: 693b ldr r3, [r7, #16]
+ 8001fc8: 43db mvns r3, r3
+ 8001fca: 69ba ldr r2, [r7, #24]
+ 8001fcc: 4013 ands r3, r2
+ 8001fce: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 8001f54: 683b ldr r3, [r7, #0]
- 8001f56: 685b ldr r3, [r3, #4]
- 8001f58: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8001f5c: 2b00 cmp r3, #0
- 8001f5e: d003 beq.n 8001f68 <HAL_GPIO_Init+0x2ac>
+ 8001fd0: 683b ldr r3, [r7, #0]
+ 8001fd2: 685b ldr r3, [r3, #4]
+ 8001fd4: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8001fd8: 2b00 cmp r3, #0
+ 8001fda: d003 beq.n 8001fe4 <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
- 8001f60: 69ba ldr r2, [r7, #24]
- 8001f62: 693b ldr r3, [r7, #16]
- 8001f64: 4313 orrs r3, r2
- 8001f66: 61bb str r3, [r7, #24]
+ 8001fdc: 69ba ldr r2, [r7, #24]
+ 8001fde: 693b ldr r3, [r7, #16]
+ 8001fe0: 4313 orrs r3, r2
+ 8001fe2: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
- 8001f68: 4a28 ldr r2, [pc, #160] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001f6a: 69bb ldr r3, [r7, #24]
- 8001f6c: 6053 str r3, [r2, #4]
+ 8001fe4: 4a28 ldr r2, [pc, #160] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 8001fe6: 69bb ldr r3, [r7, #24]
+ 8001fe8: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
- 8001f6e: 4b27 ldr r3, [pc, #156] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001f70: 689b ldr r3, [r3, #8]
- 8001f72: 61bb str r3, [r7, #24]
+ 8001fea: 4b27 ldr r3, [pc, #156] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 8001fec: 689b ldr r3, [r3, #8]
+ 8001fee: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8001f74: 693b ldr r3, [r7, #16]
- 8001f76: 43db mvns r3, r3
- 8001f78: 69ba ldr r2, [r7, #24]
- 8001f7a: 4013 ands r3, r2
- 8001f7c: 61bb str r3, [r7, #24]
+ 8001ff0: 693b ldr r3, [r7, #16]
+ 8001ff2: 43db mvns r3, r3
+ 8001ff4: 69ba ldr r2, [r7, #24]
+ 8001ff6: 4013 ands r3, r2
+ 8001ff8: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 8001f7e: 683b ldr r3, [r7, #0]
- 8001f80: 685b ldr r3, [r3, #4]
- 8001f82: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8001f86: 2b00 cmp r3, #0
- 8001f88: d003 beq.n 8001f92 <HAL_GPIO_Init+0x2d6>
+ 8001ffa: 683b ldr r3, [r7, #0]
+ 8001ffc: 685b ldr r3, [r3, #4]
+ 8001ffe: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8002002: 2b00 cmp r3, #0
+ 8002004: d003 beq.n 800200e <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
- 8001f8a: 69ba ldr r2, [r7, #24]
- 8001f8c: 693b ldr r3, [r7, #16]
- 8001f8e: 4313 orrs r3, r2
- 8001f90: 61bb str r3, [r7, #24]
+ 8002006: 69ba ldr r2, [r7, #24]
+ 8002008: 693b ldr r3, [r7, #16]
+ 800200a: 4313 orrs r3, r2
+ 800200c: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
- 8001f92: 4a1e ldr r2, [pc, #120] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001f94: 69bb ldr r3, [r7, #24]
- 8001f96: 6093 str r3, [r2, #8]
+ 800200e: 4a1e ldr r2, [pc, #120] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 8002010: 69bb ldr r3, [r7, #24]
+ 8002012: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
- 8001f98: 4b1c ldr r3, [pc, #112] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001f9a: 68db ldr r3, [r3, #12]
- 8001f9c: 61bb str r3, [r7, #24]
+ 8002014: 4b1c ldr r3, [pc, #112] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 8002016: 68db ldr r3, [r3, #12]
+ 8002018: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8001f9e: 693b ldr r3, [r7, #16]
- 8001fa0: 43db mvns r3, r3
- 8001fa2: 69ba ldr r2, [r7, #24]
- 8001fa4: 4013 ands r3, r2
- 8001fa6: 61bb str r3, [r7, #24]
+ 800201a: 693b ldr r3, [r7, #16]
+ 800201c: 43db mvns r3, r3
+ 800201e: 69ba ldr r2, [r7, #24]
+ 8002020: 4013 ands r3, r2
+ 8002022: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 8001fa8: 683b ldr r3, [r7, #0]
- 8001faa: 685b ldr r3, [r3, #4]
- 8001fac: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8001fb0: 2b00 cmp r3, #0
- 8001fb2: d003 beq.n 8001fbc <HAL_GPIO_Init+0x300>
+ 8002024: 683b ldr r3, [r7, #0]
+ 8002026: 685b ldr r3, [r3, #4]
+ 8002028: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 800202c: 2b00 cmp r3, #0
+ 800202e: d003 beq.n 8002038 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
- 8001fb4: 69ba ldr r2, [r7, #24]
- 8001fb6: 693b ldr r3, [r7, #16]
- 8001fb8: 4313 orrs r3, r2
- 8001fba: 61bb str r3, [r7, #24]
+ 8002030: 69ba ldr r2, [r7, #24]
+ 8002032: 693b ldr r3, [r7, #16]
+ 8002034: 4313 orrs r3, r2
+ 8002036: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
- 8001fbc: 4a13 ldr r2, [pc, #76] ; (800200c <HAL_GPIO_Init+0x350>)
- 8001fbe: 69bb ldr r3, [r7, #24]
- 8001fc0: 60d3 str r3, [r2, #12]
+ 8002038: 4a13 ldr r2, [pc, #76] ; (8002088 <HAL_GPIO_Init+0x350>)
+ 800203a: 69bb ldr r3, [r7, #24]
+ 800203c: 60d3 str r3, [r2, #12]
for(position = 0; position < GPIO_NUMBER; position++)
- 8001fc2: 69fb ldr r3, [r7, #28]
- 8001fc4: 3301 adds r3, #1
- 8001fc6: 61fb str r3, [r7, #28]
- 8001fc8: 69fb ldr r3, [r7, #28]
- 8001fca: 2b0f cmp r3, #15
- 8001fcc: f67f ae86 bls.w 8001cdc <HAL_GPIO_Init+0x20>
+ 800203e: 69fb ldr r3, [r7, #28]
+ 8002040: 3301 adds r3, #1
+ 8002042: 61fb str r3, [r7, #28]
+ 8002044: 69fb ldr r3, [r7, #28]
+ 8002046: 2b0f cmp r3, #15
+ 8002048: f67f ae86 bls.w 8001d58 <HAL_GPIO_Init+0x20>
}
}
}
}
- 8001fd0: bf00 nop
- 8001fd2: 3724 adds r7, #36 ; 0x24
- 8001fd4: 46bd mov sp, r7
- 8001fd6: f85d 7b04 ldr.w r7, [sp], #4
- 8001fda: 4770 bx lr
- 8001fdc: 40023800 .word 0x40023800
- 8001fe0: 40013800 .word 0x40013800
- 8001fe4: 40020000 .word 0x40020000
- 8001fe8: 40020400 .word 0x40020400
- 8001fec: 40020800 .word 0x40020800
- 8001ff0: 40020c00 .word 0x40020c00
- 8001ff4: 40021000 .word 0x40021000
- 8001ff8: 40021400 .word 0x40021400
- 8001ffc: 40021800 .word 0x40021800
- 8002000: 40021c00 .word 0x40021c00
- 8002004: 40022000 .word 0x40022000
- 8002008: 40022400 .word 0x40022400
- 800200c: 40013c00 .word 0x40013c00
-
-08002010 <HAL_GPIO_WritePin>:
+ 800204c: bf00 nop
+ 800204e: 3724 adds r7, #36 ; 0x24
+ 8002050: 46bd mov sp, r7
+ 8002052: f85d 7b04 ldr.w r7, [sp], #4
+ 8002056: 4770 bx lr
+ 8002058: 40023800 .word 0x40023800
+ 800205c: 40013800 .word 0x40013800
+ 8002060: 40020000 .word 0x40020000
+ 8002064: 40020400 .word 0x40020400
+ 8002068: 40020800 .word 0x40020800
+ 800206c: 40020c00 .word 0x40020c00
+ 8002070: 40021000 .word 0x40021000
+ 8002074: 40021400 .word 0x40021400
+ 8002078: 40021800 .word 0x40021800
+ 800207c: 40021c00 .word 0x40021c00
+ 8002080: 40022000 .word 0x40022000
+ 8002084: 40022400 .word 0x40022400
+ 8002088: 40013c00 .word 0x40013c00
+
+0800208c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
- 8002010: b480 push {r7}
- 8002012: b083 sub sp, #12
- 8002014: af00 add r7, sp, #0
- 8002016: 6078 str r0, [r7, #4]
- 8002018: 460b mov r3, r1
- 800201a: 807b strh r3, [r7, #2]
- 800201c: 4613 mov r3, r2
- 800201e: 707b strb r3, [r7, #1]
+ 800208c: b480 push {r7}
+ 800208e: b083 sub sp, #12
+ 8002090: af00 add r7, sp, #0
+ 8002092: 6078 str r0, [r7, #4]
+ 8002094: 460b mov r3, r1
+ 8002096: 807b strh r3, [r7, #2]
+ 8002098: 4613 mov r3, r2
+ 800209a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
- 8002020: 787b ldrb r3, [r7, #1]
- 8002022: 2b00 cmp r3, #0
- 8002024: d003 beq.n 800202e <HAL_GPIO_WritePin+0x1e>
+ 800209c: 787b ldrb r3, [r7, #1]
+ 800209e: 2b00 cmp r3, #0
+ 80020a0: d003 beq.n 80020aa <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
- 8002026: 887a ldrh r2, [r7, #2]
- 8002028: 687b ldr r3, [r7, #4]
- 800202a: 619a str r2, [r3, #24]
+ 80020a2: 887a ldrh r2, [r7, #2]
+ 80020a4: 687b ldr r3, [r7, #4]
+ 80020a6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
- 800202c: e003 b.n 8002036 <HAL_GPIO_WritePin+0x26>
+ 80020a8: e003 b.n 80020b2 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
- 800202e: 887b ldrh r3, [r7, #2]
- 8002030: 041a lsls r2, r3, #16
- 8002032: 687b ldr r3, [r7, #4]
- 8002034: 619a str r2, [r3, #24]
+ 80020aa: 887b ldrh r3, [r7, #2]
+ 80020ac: 041a lsls r2, r3, #16
+ 80020ae: 687b ldr r3, [r7, #4]
+ 80020b0: 619a str r2, [r3, #24]
}
- 8002036: bf00 nop
- 8002038: 370c adds r7, #12
- 800203a: 46bd mov sp, r7
- 800203c: f85d 7b04 ldr.w r7, [sp], #4
- 8002040: 4770 bx lr
+ 80020b2: bf00 nop
+ 80020b4: 370c adds r7, #12
+ 80020b6: 46bd mov sp, r7
+ 80020b8: f85d 7b04 ldr.w r7, [sp], #4
+ 80020bc: 4770 bx lr
...
-08002044 <HAL_GPIO_EXTI_IRQHandler>:
+080020c0 <HAL_GPIO_EXTI_IRQHandler>:
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin Specifies the pins connected EXTI line
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
- 8002044: b580 push {r7, lr}
- 8002046: b082 sub sp, #8
- 8002048: af00 add r7, sp, #0
- 800204a: 4603 mov r3, r0
- 800204c: 80fb strh r3, [r7, #6]
+ 80020c0: b580 push {r7, lr}
+ 80020c2: b082 sub sp, #8
+ 80020c4: af00 add r7, sp, #0
+ 80020c6: 4603 mov r3, r0
+ 80020c8: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- 800204e: 4b08 ldr r3, [pc, #32] ; (8002070 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 8002050: 695a ldr r2, [r3, #20]
- 8002052: 88fb ldrh r3, [r7, #6]
- 8002054: 4013 ands r3, r2
- 8002056: 2b00 cmp r3, #0
- 8002058: d006 beq.n 8002068 <HAL_GPIO_EXTI_IRQHandler+0x24>
+ 80020ca: 4b08 ldr r3, [pc, #32] ; (80020ec <HAL_GPIO_EXTI_IRQHandler+0x2c>)
+ 80020cc: 695a ldr r2, [r3, #20]
+ 80020ce: 88fb ldrh r3, [r7, #6]
+ 80020d0: 4013 ands r3, r2
+ 80020d2: 2b00 cmp r3, #0
+ 80020d4: d006 beq.n 80020e4 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- 800205a: 4a05 ldr r2, [pc, #20] ; (8002070 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 800205c: 88fb ldrh r3, [r7, #6]
- 800205e: 6153 str r3, [r2, #20]
+ 80020d6: 4a05 ldr r2, [pc, #20] ; (80020ec <HAL_GPIO_EXTI_IRQHandler+0x2c>)
+ 80020d8: 88fb ldrh r3, [r7, #6]
+ 80020da: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
- 8002060: 88fb ldrh r3, [r7, #6]
- 8002062: 4618 mov r0, r3
- 8002064: f7ff f9be bl 80013e4 <HAL_GPIO_EXTI_Callback>
+ 80020dc: 88fb ldrh r3, [r7, #6]
+ 80020de: 4618 mov r0, r3
+ 80020e0: f7ff f9ae bl 8001440 <HAL_GPIO_EXTI_Callback>
}
}
- 8002068: bf00 nop
- 800206a: 3708 adds r7, #8
- 800206c: 46bd mov sp, r7
- 800206e: bd80 pop {r7, pc}
- 8002070: 40013c00 .word 0x40013c00
+ 80020e4: bf00 nop
+ 80020e6: 3708 adds r7, #8
+ 80020e8: 46bd mov sp, r7
+ 80020ea: bd80 pop {r7, pc}
+ 80020ec: 40013c00 .word 0x40013c00
-08002074 <HAL_RCC_OscConfig>:
+080020f0 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- 8002074: b580 push {r7, lr}
- 8002076: b086 sub sp, #24
- 8002078: af00 add r7, sp, #0
- 800207a: 6078 str r0, [r7, #4]
+ 80020f0: b580 push {r7, lr}
+ 80020f2: b086 sub sp, #24
+ 80020f4: af00 add r7, sp, #0
+ 80020f6: 6078 str r0, [r7, #4]
uint32_t tickstart;
FlagStatus pwrclkchanged = RESET;
- 800207c: 2300 movs r3, #0
- 800207e: 75fb strb r3, [r7, #23]
+ 80020f8: 2300 movs r3, #0
+ 80020fa: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
- 8002080: 687b ldr r3, [r7, #4]
- 8002082: 2b00 cmp r3, #0
- 8002084: d101 bne.n 800208a <HAL_RCC_OscConfig+0x16>
+ 80020fc: 687b ldr r3, [r7, #4]
+ 80020fe: 2b00 cmp r3, #0
+ 8002100: d101 bne.n 8002106 <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
- 8002086: 2301 movs r3, #1
- 8002088: e25e b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 8002102: 2301 movs r3, #1
+ 8002104: e25e b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 800208a: 687b ldr r3, [r7, #4]
- 800208c: 681b ldr r3, [r3, #0]
- 800208e: f003 0301 and.w r3, r3, #1
- 8002092: 2b00 cmp r3, #0
- 8002094: f000 8087 beq.w 80021a6 <HAL_RCC_OscConfig+0x132>
+ 8002106: 687b ldr r3, [r7, #4]
+ 8002108: 681b ldr r3, [r3, #0]
+ 800210a: f003 0301 and.w r3, r3, #1
+ 800210e: 2b00 cmp r3, #0
+ 8002110: f000 8087 beq.w 8002222 <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8002098: 4b96 ldr r3, [pc, #600] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800209a: 689b ldr r3, [r3, #8]
- 800209c: f003 030c and.w r3, r3, #12
- 80020a0: 2b04 cmp r3, #4
- 80020a2: d00c beq.n 80020be <HAL_RCC_OscConfig+0x4a>
+ 8002114: 4b96 ldr r3, [pc, #600] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002116: 689b ldr r3, [r3, #8]
+ 8002118: f003 030c and.w r3, r3, #12
+ 800211c: 2b04 cmp r3, #4
+ 800211e: d00c beq.n 800213a <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 80020a4: 4b93 ldr r3, [pc, #588] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80020a6: 689b ldr r3, [r3, #8]
- 80020a8: f003 030c and.w r3, r3, #12
- 80020ac: 2b08 cmp r3, #8
- 80020ae: d112 bne.n 80020d6 <HAL_RCC_OscConfig+0x62>
- 80020b0: 4b90 ldr r3, [pc, #576] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80020b2: 685b ldr r3, [r3, #4]
- 80020b4: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 80020b8: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 80020bc: d10b bne.n 80020d6 <HAL_RCC_OscConfig+0x62>
+ 8002120: 4b93 ldr r3, [pc, #588] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002122: 689b ldr r3, [r3, #8]
+ 8002124: f003 030c and.w r3, r3, #12
+ 8002128: 2b08 cmp r3, #8
+ 800212a: d112 bne.n 8002152 <HAL_RCC_OscConfig+0x62>
+ 800212c: 4b90 ldr r3, [pc, #576] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800212e: 685b ldr r3, [r3, #4]
+ 8002130: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8002134: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8002138: d10b bne.n 8002152 <HAL_RCC_OscConfig+0x62>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 80020be: 4b8d ldr r3, [pc, #564] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80020c0: 681b ldr r3, [r3, #0]
- 80020c2: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80020c6: 2b00 cmp r3, #0
- 80020c8: d06c beq.n 80021a4 <HAL_RCC_OscConfig+0x130>
- 80020ca: 687b ldr r3, [r7, #4]
- 80020cc: 685b ldr r3, [r3, #4]
- 80020ce: 2b00 cmp r3, #0
- 80020d0: d168 bne.n 80021a4 <HAL_RCC_OscConfig+0x130>
+ 800213a: 4b8d ldr r3, [pc, #564] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800213c: 681b ldr r3, [r3, #0]
+ 800213e: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8002142: 2b00 cmp r3, #0
+ 8002144: d06c beq.n 8002220 <HAL_RCC_OscConfig+0x130>
+ 8002146: 687b ldr r3, [r7, #4]
+ 8002148: 685b ldr r3, [r3, #4]
+ 800214a: 2b00 cmp r3, #0
+ 800214c: d168 bne.n 8002220 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
- 80020d2: 2301 movs r3, #1
- 80020d4: e238 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 800214e: 2301 movs r3, #1
+ 8002150: e238 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 80020d6: 687b ldr r3, [r7, #4]
- 80020d8: 685b ldr r3, [r3, #4]
- 80020da: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 80020de: d106 bne.n 80020ee <HAL_RCC_OscConfig+0x7a>
- 80020e0: 4b84 ldr r3, [pc, #528] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80020e2: 681b ldr r3, [r3, #0]
- 80020e4: 4a83 ldr r2, [pc, #524] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80020e6: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 80020ea: 6013 str r3, [r2, #0]
- 80020ec: e02e b.n 800214c <HAL_RCC_OscConfig+0xd8>
- 80020ee: 687b ldr r3, [r7, #4]
- 80020f0: 685b ldr r3, [r3, #4]
- 80020f2: 2b00 cmp r3, #0
- 80020f4: d10c bne.n 8002110 <HAL_RCC_OscConfig+0x9c>
- 80020f6: 4b7f ldr r3, [pc, #508] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80020f8: 681b ldr r3, [r3, #0]
- 80020fa: 4a7e ldr r2, [pc, #504] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80020fc: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002100: 6013 str r3, [r2, #0]
- 8002102: 4b7c ldr r3, [pc, #496] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002104: 681b ldr r3, [r3, #0]
- 8002106: 4a7b ldr r2, [pc, #492] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002108: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 800210c: 6013 str r3, [r2, #0]
- 800210e: e01d b.n 800214c <HAL_RCC_OscConfig+0xd8>
- 8002110: 687b ldr r3, [r7, #4]
- 8002112: 685b ldr r3, [r3, #4]
- 8002114: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 8002118: d10c bne.n 8002134 <HAL_RCC_OscConfig+0xc0>
- 800211a: 4b76 ldr r3, [pc, #472] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800211c: 681b ldr r3, [r3, #0]
- 800211e: 4a75 ldr r2, [pc, #468] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002120: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 8002124: 6013 str r3, [r2, #0]
- 8002126: 4b73 ldr r3, [pc, #460] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002128: 681b ldr r3, [r3, #0]
- 800212a: 4a72 ldr r2, [pc, #456] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800212c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002130: 6013 str r3, [r2, #0]
- 8002132: e00b b.n 800214c <HAL_RCC_OscConfig+0xd8>
- 8002134: 4b6f ldr r3, [pc, #444] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002136: 681b ldr r3, [r3, #0]
- 8002138: 4a6e ldr r2, [pc, #440] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800213a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 800213e: 6013 str r3, [r2, #0]
- 8002140: 4b6c ldr r3, [pc, #432] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002142: 681b ldr r3, [r3, #0]
- 8002144: 4a6b ldr r2, [pc, #428] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002146: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 800214a: 6013 str r3, [r2, #0]
+ 8002152: 687b ldr r3, [r7, #4]
+ 8002154: 685b ldr r3, [r3, #4]
+ 8002156: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 800215a: d106 bne.n 800216a <HAL_RCC_OscConfig+0x7a>
+ 800215c: 4b84 ldr r3, [pc, #528] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800215e: 681b ldr r3, [r3, #0]
+ 8002160: 4a83 ldr r2, [pc, #524] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002162: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8002166: 6013 str r3, [r2, #0]
+ 8002168: e02e b.n 80021c8 <HAL_RCC_OscConfig+0xd8>
+ 800216a: 687b ldr r3, [r7, #4]
+ 800216c: 685b ldr r3, [r3, #4]
+ 800216e: 2b00 cmp r3, #0
+ 8002170: d10c bne.n 800218c <HAL_RCC_OscConfig+0x9c>
+ 8002172: 4b7f ldr r3, [pc, #508] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002174: 681b ldr r3, [r3, #0]
+ 8002176: 4a7e ldr r2, [pc, #504] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002178: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 800217c: 6013 str r3, [r2, #0]
+ 800217e: 4b7c ldr r3, [pc, #496] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002180: 681b ldr r3, [r3, #0]
+ 8002182: 4a7b ldr r2, [pc, #492] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002184: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8002188: 6013 str r3, [r2, #0]
+ 800218a: e01d b.n 80021c8 <HAL_RCC_OscConfig+0xd8>
+ 800218c: 687b ldr r3, [r7, #4]
+ 800218e: 685b ldr r3, [r3, #4]
+ 8002190: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
+ 8002194: d10c bne.n 80021b0 <HAL_RCC_OscConfig+0xc0>
+ 8002196: 4b76 ldr r3, [pc, #472] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002198: 681b ldr r3, [r3, #0]
+ 800219a: 4a75 ldr r2, [pc, #468] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800219c: f443 2380 orr.w r3, r3, #262144 ; 0x40000
+ 80021a0: 6013 str r3, [r2, #0]
+ 80021a2: 4b73 ldr r3, [pc, #460] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80021a4: 681b ldr r3, [r3, #0]
+ 80021a6: 4a72 ldr r2, [pc, #456] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80021a8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 80021ac: 6013 str r3, [r2, #0]
+ 80021ae: e00b b.n 80021c8 <HAL_RCC_OscConfig+0xd8>
+ 80021b0: 4b6f ldr r3, [pc, #444] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80021b2: 681b ldr r3, [r3, #0]
+ 80021b4: 4a6e ldr r2, [pc, #440] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80021b6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 80021ba: 6013 str r3, [r2, #0]
+ 80021bc: 4b6c ldr r3, [pc, #432] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80021be: 681b ldr r3, [r3, #0]
+ 80021c0: 4a6b ldr r2, [pc, #428] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80021c2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 80021c6: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 800214c: 687b ldr r3, [r7, #4]
- 800214e: 685b ldr r3, [r3, #4]
- 8002150: 2b00 cmp r3, #0
- 8002152: d013 beq.n 800217c <HAL_RCC_OscConfig+0x108>
+ 80021c8: 687b ldr r3, [r7, #4]
+ 80021ca: 685b ldr r3, [r3, #4]
+ 80021cc: 2b00 cmp r3, #0
+ 80021ce: d013 beq.n 80021f8 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002154: f7ff fc72 bl 8001a3c <HAL_GetTick>
- 8002158: 6138 str r0, [r7, #16]
+ 80021d0: f7ff fc72 bl 8001ab8 <HAL_GetTick>
+ 80021d4: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800215a: e008 b.n 800216e <HAL_RCC_OscConfig+0xfa>
+ 80021d6: e008 b.n 80021ea <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 800215c: f7ff fc6e bl 8001a3c <HAL_GetTick>
- 8002160: 4602 mov r2, r0
- 8002162: 693b ldr r3, [r7, #16]
- 8002164: 1ad3 subs r3, r2, r3
- 8002166: 2b64 cmp r3, #100 ; 0x64
- 8002168: d901 bls.n 800216e <HAL_RCC_OscConfig+0xfa>
+ 80021d8: f7ff fc6e bl 8001ab8 <HAL_GetTick>
+ 80021dc: 4602 mov r2, r0
+ 80021de: 693b ldr r3, [r7, #16]
+ 80021e0: 1ad3 subs r3, r2, r3
+ 80021e2: 2b64 cmp r3, #100 ; 0x64
+ 80021e4: d901 bls.n 80021ea <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
- 800216a: 2303 movs r3, #3
- 800216c: e1ec b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 80021e6: 2303 movs r3, #3
+ 80021e8: e1ec b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800216e: 4b61 ldr r3, [pc, #388] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002170: 681b ldr r3, [r3, #0]
- 8002172: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002176: 2b00 cmp r3, #0
- 8002178: d0f0 beq.n 800215c <HAL_RCC_OscConfig+0xe8>
- 800217a: e014 b.n 80021a6 <HAL_RCC_OscConfig+0x132>
+ 80021ea: 4b61 ldr r3, [pc, #388] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80021ec: 681b ldr r3, [r3, #0]
+ 80021ee: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80021f2: 2b00 cmp r3, #0
+ 80021f4: d0f0 beq.n 80021d8 <HAL_RCC_OscConfig+0xe8>
+ 80021f6: e014 b.n 8002222 <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 800217c: f7ff fc5e bl 8001a3c <HAL_GetTick>
- 8002180: 6138 str r0, [r7, #16]
+ 80021f8: f7ff fc5e bl 8001ab8 <HAL_GetTick>
+ 80021fc: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8002182: e008 b.n 8002196 <HAL_RCC_OscConfig+0x122>
+ 80021fe: e008 b.n 8002212 <HAL_RCC_OscConfig+0x122>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8002184: f7ff fc5a bl 8001a3c <HAL_GetTick>
- 8002188: 4602 mov r2, r0
- 800218a: 693b ldr r3, [r7, #16]
- 800218c: 1ad3 subs r3, r2, r3
- 800218e: 2b64 cmp r3, #100 ; 0x64
- 8002190: d901 bls.n 8002196 <HAL_RCC_OscConfig+0x122>
+ 8002200: f7ff fc5a bl 8001ab8 <HAL_GetTick>
+ 8002204: 4602 mov r2, r0
+ 8002206: 693b ldr r3, [r7, #16]
+ 8002208: 1ad3 subs r3, r2, r3
+ 800220a: 2b64 cmp r3, #100 ; 0x64
+ 800220c: d901 bls.n 8002212 <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
- 8002192: 2303 movs r3, #3
- 8002194: e1d8 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 800220e: 2303 movs r3, #3
+ 8002210: e1d8 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8002196: 4b57 ldr r3, [pc, #348] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002198: 681b ldr r3, [r3, #0]
- 800219a: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800219e: 2b00 cmp r3, #0
- 80021a0: d1f0 bne.n 8002184 <HAL_RCC_OscConfig+0x110>
- 80021a2: e000 b.n 80021a6 <HAL_RCC_OscConfig+0x132>
+ 8002212: 4b57 ldr r3, [pc, #348] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002214: 681b ldr r3, [r3, #0]
+ 8002216: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 800221a: 2b00 cmp r3, #0
+ 800221c: d1f0 bne.n 8002200 <HAL_RCC_OscConfig+0x110>
+ 800221e: e000 b.n 8002222 <HAL_RCC_OscConfig+0x132>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 80021a4: bf00 nop
+ 8002220: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 80021a6: 687b ldr r3, [r7, #4]
- 80021a8: 681b ldr r3, [r3, #0]
- 80021aa: f003 0302 and.w r3, r3, #2
- 80021ae: 2b00 cmp r3, #0
- 80021b0: d069 beq.n 8002286 <HAL_RCC_OscConfig+0x212>
+ 8002222: 687b ldr r3, [r7, #4]
+ 8002224: 681b ldr r3, [r3, #0]
+ 8002226: f003 0302 and.w r3, r3, #2
+ 800222a: 2b00 cmp r3, #0
+ 800222c: d069 beq.n 8002302 <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 80021b2: 4b50 ldr r3, [pc, #320] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80021b4: 689b ldr r3, [r3, #8]
- 80021b6: f003 030c and.w r3, r3, #12
- 80021ba: 2b00 cmp r3, #0
- 80021bc: d00b beq.n 80021d6 <HAL_RCC_OscConfig+0x162>
+ 800222e: 4b50 ldr r3, [pc, #320] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002230: 689b ldr r3, [r3, #8]
+ 8002232: f003 030c and.w r3, r3, #12
+ 8002236: 2b00 cmp r3, #0
+ 8002238: d00b beq.n 8002252 <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 80021be: 4b4d ldr r3, [pc, #308] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80021c0: 689b ldr r3, [r3, #8]
- 80021c2: f003 030c and.w r3, r3, #12
- 80021c6: 2b08 cmp r3, #8
- 80021c8: d11c bne.n 8002204 <HAL_RCC_OscConfig+0x190>
- 80021ca: 4b4a ldr r3, [pc, #296] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80021cc: 685b ldr r3, [r3, #4]
- 80021ce: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 80021d2: 2b00 cmp r3, #0
- 80021d4: d116 bne.n 8002204 <HAL_RCC_OscConfig+0x190>
+ 800223a: 4b4d ldr r3, [pc, #308] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800223c: 689b ldr r3, [r3, #8]
+ 800223e: f003 030c and.w r3, r3, #12
+ 8002242: 2b08 cmp r3, #8
+ 8002244: d11c bne.n 8002280 <HAL_RCC_OscConfig+0x190>
+ 8002246: 4b4a ldr r3, [pc, #296] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002248: 685b ldr r3, [r3, #4]
+ 800224a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 800224e: 2b00 cmp r3, #0
+ 8002250: d116 bne.n 8002280 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80021d6: 4b47 ldr r3, [pc, #284] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80021d8: 681b ldr r3, [r3, #0]
- 80021da: f003 0302 and.w r3, r3, #2
- 80021de: 2b00 cmp r3, #0
- 80021e0: d005 beq.n 80021ee <HAL_RCC_OscConfig+0x17a>
- 80021e2: 687b ldr r3, [r7, #4]
- 80021e4: 68db ldr r3, [r3, #12]
- 80021e6: 2b01 cmp r3, #1
- 80021e8: d001 beq.n 80021ee <HAL_RCC_OscConfig+0x17a>
+ 8002252: 4b47 ldr r3, [pc, #284] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002254: 681b ldr r3, [r3, #0]
+ 8002256: f003 0302 and.w r3, r3, #2
+ 800225a: 2b00 cmp r3, #0
+ 800225c: d005 beq.n 800226a <HAL_RCC_OscConfig+0x17a>
+ 800225e: 687b ldr r3, [r7, #4]
+ 8002260: 68db ldr r3, [r3, #12]
+ 8002262: 2b01 cmp r3, #1
+ 8002264: d001 beq.n 800226a <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
- 80021ea: 2301 movs r3, #1
- 80021ec: e1ac b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 8002266: 2301 movs r3, #1
+ 8002268: e1ac b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80021ee: 4b41 ldr r3, [pc, #260] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80021f0: 681b ldr r3, [r3, #0]
- 80021f2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 80021f6: 687b ldr r3, [r7, #4]
- 80021f8: 691b ldr r3, [r3, #16]
- 80021fa: 00db lsls r3, r3, #3
- 80021fc: 493d ldr r1, [pc, #244] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80021fe: 4313 orrs r3, r2
- 8002200: 600b str r3, [r1, #0]
+ 800226a: 4b41 ldr r3, [pc, #260] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800226c: 681b ldr r3, [r3, #0]
+ 800226e: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 8002272: 687b ldr r3, [r7, #4]
+ 8002274: 691b ldr r3, [r3, #16]
+ 8002276: 00db lsls r3, r3, #3
+ 8002278: 493d ldr r1, [pc, #244] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800227a: 4313 orrs r3, r2
+ 800227c: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8002202: e040 b.n 8002286 <HAL_RCC_OscConfig+0x212>
+ 800227e: e040 b.n 8002302 <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 8002204: 687b ldr r3, [r7, #4]
- 8002206: 68db ldr r3, [r3, #12]
- 8002208: 2b00 cmp r3, #0
- 800220a: d023 beq.n 8002254 <HAL_RCC_OscConfig+0x1e0>
+ 8002280: 687b ldr r3, [r7, #4]
+ 8002282: 68db ldr r3, [r3, #12]
+ 8002284: 2b00 cmp r3, #0
+ 8002286: d023 beq.n 80022d0 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
- 800220c: 4b39 ldr r3, [pc, #228] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800220e: 681b ldr r3, [r3, #0]
- 8002210: 4a38 ldr r2, [pc, #224] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002212: f043 0301 orr.w r3, r3, #1
- 8002216: 6013 str r3, [r2, #0]
+ 8002288: 4b39 ldr r3, [pc, #228] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800228a: 681b ldr r3, [r3, #0]
+ 800228c: 4a38 ldr r2, [pc, #224] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800228e: f043 0301 orr.w r3, r3, #1
+ 8002292: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002218: f7ff fc10 bl 8001a3c <HAL_GetTick>
- 800221c: 6138 str r0, [r7, #16]
+ 8002294: f7ff fc10 bl 8001ab8 <HAL_GetTick>
+ 8002298: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 800221e: e008 b.n 8002232 <HAL_RCC_OscConfig+0x1be>
+ 800229a: e008 b.n 80022ae <HAL_RCC_OscConfig+0x1be>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8002220: f7ff fc0c bl 8001a3c <HAL_GetTick>
- 8002224: 4602 mov r2, r0
- 8002226: 693b ldr r3, [r7, #16]
- 8002228: 1ad3 subs r3, r2, r3
- 800222a: 2b02 cmp r3, #2
- 800222c: d901 bls.n 8002232 <HAL_RCC_OscConfig+0x1be>
+ 800229c: f7ff fc0c bl 8001ab8 <HAL_GetTick>
+ 80022a0: 4602 mov r2, r0
+ 80022a2: 693b ldr r3, [r7, #16]
+ 80022a4: 1ad3 subs r3, r2, r3
+ 80022a6: 2b02 cmp r3, #2
+ 80022a8: d901 bls.n 80022ae <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
- 800222e: 2303 movs r3, #3
- 8002230: e18a b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 80022aa: 2303 movs r3, #3
+ 80022ac: e18a b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8002232: 4b30 ldr r3, [pc, #192] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002234: 681b ldr r3, [r3, #0]
- 8002236: f003 0302 and.w r3, r3, #2
- 800223a: 2b00 cmp r3, #0
- 800223c: d0f0 beq.n 8002220 <HAL_RCC_OscConfig+0x1ac>
+ 80022ae: 4b30 ldr r3, [pc, #192] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80022b0: 681b ldr r3, [r3, #0]
+ 80022b2: f003 0302 and.w r3, r3, #2
+ 80022b6: 2b00 cmp r3, #0
+ 80022b8: d0f0 beq.n 800229c <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 800223e: 4b2d ldr r3, [pc, #180] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002240: 681b ldr r3, [r3, #0]
- 8002242: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 8002246: 687b ldr r3, [r7, #4]
- 8002248: 691b ldr r3, [r3, #16]
- 800224a: 00db lsls r3, r3, #3
- 800224c: 4929 ldr r1, [pc, #164] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800224e: 4313 orrs r3, r2
- 8002250: 600b str r3, [r1, #0]
- 8002252: e018 b.n 8002286 <HAL_RCC_OscConfig+0x212>
+ 80022ba: 4b2d ldr r3, [pc, #180] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80022bc: 681b ldr r3, [r3, #0]
+ 80022be: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 80022c2: 687b ldr r3, [r7, #4]
+ 80022c4: 691b ldr r3, [r3, #16]
+ 80022c6: 00db lsls r3, r3, #3
+ 80022c8: 4929 ldr r1, [pc, #164] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80022ca: 4313 orrs r3, r2
+ 80022cc: 600b str r3, [r1, #0]
+ 80022ce: e018 b.n 8002302 <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
- 8002254: 4b27 ldr r3, [pc, #156] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 8002256: 681b ldr r3, [r3, #0]
- 8002258: 4a26 ldr r2, [pc, #152] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800225a: f023 0301 bic.w r3, r3, #1
- 800225e: 6013 str r3, [r2, #0]
+ 80022d0: 4b27 ldr r3, [pc, #156] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80022d2: 681b ldr r3, [r3, #0]
+ 80022d4: 4a26 ldr r2, [pc, #152] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80022d6: f023 0301 bic.w r3, r3, #1
+ 80022da: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002260: f7ff fbec bl 8001a3c <HAL_GetTick>
- 8002264: 6138 str r0, [r7, #16]
+ 80022dc: f7ff fbec bl 8001ab8 <HAL_GetTick>
+ 80022e0: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8002266: e008 b.n 800227a <HAL_RCC_OscConfig+0x206>
+ 80022e2: e008 b.n 80022f6 <HAL_RCC_OscConfig+0x206>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8002268: f7ff fbe8 bl 8001a3c <HAL_GetTick>
- 800226c: 4602 mov r2, r0
- 800226e: 693b ldr r3, [r7, #16]
- 8002270: 1ad3 subs r3, r2, r3
- 8002272: 2b02 cmp r3, #2
- 8002274: d901 bls.n 800227a <HAL_RCC_OscConfig+0x206>
+ 80022e4: f7ff fbe8 bl 8001ab8 <HAL_GetTick>
+ 80022e8: 4602 mov r2, r0
+ 80022ea: 693b ldr r3, [r7, #16]
+ 80022ec: 1ad3 subs r3, r2, r3
+ 80022ee: 2b02 cmp r3, #2
+ 80022f0: d901 bls.n 80022f6 <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
- 8002276: 2303 movs r3, #3
- 8002278: e166 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 80022f2: 2303 movs r3, #3
+ 80022f4: e166 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 800227a: 4b1e ldr r3, [pc, #120] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800227c: 681b ldr r3, [r3, #0]
- 800227e: f003 0302 and.w r3, r3, #2
- 8002282: 2b00 cmp r3, #0
- 8002284: d1f0 bne.n 8002268 <HAL_RCC_OscConfig+0x1f4>
+ 80022f6: 4b1e ldr r3, [pc, #120] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 80022f8: 681b ldr r3, [r3, #0]
+ 80022fa: f003 0302 and.w r3, r3, #2
+ 80022fe: 2b00 cmp r3, #0
+ 8002300: d1f0 bne.n 80022e4 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8002286: 687b ldr r3, [r7, #4]
- 8002288: 681b ldr r3, [r3, #0]
- 800228a: f003 0308 and.w r3, r3, #8
- 800228e: 2b00 cmp r3, #0
- 8002290: d038 beq.n 8002304 <HAL_RCC_OscConfig+0x290>
+ 8002302: 687b ldr r3, [r7, #4]
+ 8002304: 681b ldr r3, [r3, #0]
+ 8002306: f003 0308 and.w r3, r3, #8
+ 800230a: 2b00 cmp r3, #0
+ 800230c: d038 beq.n 8002380 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 8002292: 687b ldr r3, [r7, #4]
- 8002294: 695b ldr r3, [r3, #20]
- 8002296: 2b00 cmp r3, #0
- 8002298: d019 beq.n 80022ce <HAL_RCC_OscConfig+0x25a>
+ 800230e: 687b ldr r3, [r7, #4]
+ 8002310: 695b ldr r3, [r3, #20]
+ 8002312: 2b00 cmp r3, #0
+ 8002314: d019 beq.n 800234a <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
- 800229a: 4b16 ldr r3, [pc, #88] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 800229c: 6f5b ldr r3, [r3, #116] ; 0x74
- 800229e: 4a15 ldr r2, [pc, #84] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80022a0: f043 0301 orr.w r3, r3, #1
- 80022a4: 6753 str r3, [r2, #116] ; 0x74
+ 8002316: 4b16 ldr r3, [pc, #88] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002318: 6f5b ldr r3, [r3, #116] ; 0x74
+ 800231a: 4a15 ldr r2, [pc, #84] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800231c: f043 0301 orr.w r3, r3, #1
+ 8002320: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80022a6: f7ff fbc9 bl 8001a3c <HAL_GetTick>
- 80022aa: 6138 str r0, [r7, #16]
+ 8002322: f7ff fbc9 bl 8001ab8 <HAL_GetTick>
+ 8002326: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 80022ac: e008 b.n 80022c0 <HAL_RCC_OscConfig+0x24c>
+ 8002328: e008 b.n 800233c <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 80022ae: f7ff fbc5 bl 8001a3c <HAL_GetTick>
- 80022b2: 4602 mov r2, r0
- 80022b4: 693b ldr r3, [r7, #16]
- 80022b6: 1ad3 subs r3, r2, r3
- 80022b8: 2b02 cmp r3, #2
- 80022ba: d901 bls.n 80022c0 <HAL_RCC_OscConfig+0x24c>
+ 800232a: f7ff fbc5 bl 8001ab8 <HAL_GetTick>
+ 800232e: 4602 mov r2, r0
+ 8002330: 693b ldr r3, [r7, #16]
+ 8002332: 1ad3 subs r3, r2, r3
+ 8002334: 2b02 cmp r3, #2
+ 8002336: d901 bls.n 800233c <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
- 80022bc: 2303 movs r3, #3
- 80022be: e143 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 8002338: 2303 movs r3, #3
+ 800233a: e143 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 80022c0: 4b0c ldr r3, [pc, #48] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80022c2: 6f5b ldr r3, [r3, #116] ; 0x74
- 80022c4: f003 0302 and.w r3, r3, #2
- 80022c8: 2b00 cmp r3, #0
- 80022ca: d0f0 beq.n 80022ae <HAL_RCC_OscConfig+0x23a>
- 80022cc: e01a b.n 8002304 <HAL_RCC_OscConfig+0x290>
+ 800233c: 4b0c ldr r3, [pc, #48] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800233e: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8002340: f003 0302 and.w r3, r3, #2
+ 8002344: 2b00 cmp r3, #0
+ 8002346: d0f0 beq.n 800232a <HAL_RCC_OscConfig+0x23a>
+ 8002348: e01a b.n 8002380 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
- 80022ce: 4b09 ldr r3, [pc, #36] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80022d0: 6f5b ldr r3, [r3, #116] ; 0x74
- 80022d2: 4a08 ldr r2, [pc, #32] ; (80022f4 <HAL_RCC_OscConfig+0x280>)
- 80022d4: f023 0301 bic.w r3, r3, #1
- 80022d8: 6753 str r3, [r2, #116] ; 0x74
+ 800234a: 4b09 ldr r3, [pc, #36] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 800234c: 6f5b ldr r3, [r3, #116] ; 0x74
+ 800234e: 4a08 ldr r2, [pc, #32] ; (8002370 <HAL_RCC_OscConfig+0x280>)
+ 8002350: f023 0301 bic.w r3, r3, #1
+ 8002354: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80022da: f7ff fbaf bl 8001a3c <HAL_GetTick>
- 80022de: 6138 str r0, [r7, #16]
+ 8002356: f7ff fbaf bl 8001ab8 <HAL_GetTick>
+ 800235a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 80022e0: e00a b.n 80022f8 <HAL_RCC_OscConfig+0x284>
+ 800235c: e00a b.n 8002374 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 80022e2: f7ff fbab bl 8001a3c <HAL_GetTick>
- 80022e6: 4602 mov r2, r0
- 80022e8: 693b ldr r3, [r7, #16]
- 80022ea: 1ad3 subs r3, r2, r3
- 80022ec: 2b02 cmp r3, #2
- 80022ee: d903 bls.n 80022f8 <HAL_RCC_OscConfig+0x284>
+ 800235e: f7ff fbab bl 8001ab8 <HAL_GetTick>
+ 8002362: 4602 mov r2, r0
+ 8002364: 693b ldr r3, [r7, #16]
+ 8002366: 1ad3 subs r3, r2, r3
+ 8002368: 2b02 cmp r3, #2
+ 800236a: d903 bls.n 8002374 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
- 80022f0: 2303 movs r3, #3
- 80022f2: e129 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
- 80022f4: 40023800 .word 0x40023800
+ 800236c: 2303 movs r3, #3
+ 800236e: e129 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
+ 8002370: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 80022f8: 4b95 ldr r3, [pc, #596] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80022fa: 6f5b ldr r3, [r3, #116] ; 0x74
- 80022fc: f003 0302 and.w r3, r3, #2
- 8002300: 2b00 cmp r3, #0
- 8002302: d1ee bne.n 80022e2 <HAL_RCC_OscConfig+0x26e>
+ 8002374: 4b95 ldr r3, [pc, #596] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002376: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8002378: f003 0302 and.w r3, r3, #2
+ 800237c: 2b00 cmp r3, #0
+ 800237e: d1ee bne.n 800235e <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 8002304: 687b ldr r3, [r7, #4]
- 8002306: 681b ldr r3, [r3, #0]
- 8002308: f003 0304 and.w r3, r3, #4
- 800230c: 2b00 cmp r3, #0
- 800230e: f000 80a4 beq.w 800245a <HAL_RCC_OscConfig+0x3e6>
+ 8002380: 687b ldr r3, [r7, #4]
+ 8002382: 681b ldr r3, [r3, #0]
+ 8002384: f003 0304 and.w r3, r3, #4
+ 8002388: 2b00 cmp r3, #0
+ 800238a: f000 80a4 beq.w 80024d6 <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 8002312: 4b8f ldr r3, [pc, #572] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002314: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002316: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 800231a: 2b00 cmp r3, #0
- 800231c: d10d bne.n 800233a <HAL_RCC_OscConfig+0x2c6>
+ 800238e: 4b8f ldr r3, [pc, #572] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002390: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002392: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8002396: 2b00 cmp r3, #0
+ 8002398: d10d bne.n 80023b6 <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
- 800231e: 4b8c ldr r3, [pc, #560] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002320: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002322: 4a8b ldr r2, [pc, #556] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002324: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8002328: 6413 str r3, [r2, #64] ; 0x40
- 800232a: 4b89 ldr r3, [pc, #548] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 800232c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800232e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002332: 60fb str r3, [r7, #12]
- 8002334: 68fb ldr r3, [r7, #12]
+ 800239a: 4b8c ldr r3, [pc, #560] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800239c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800239e: 4a8b ldr r2, [pc, #556] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80023a0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 80023a4: 6413 str r3, [r2, #64] ; 0x40
+ 80023a6: 4b89 ldr r3, [pc, #548] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80023a8: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80023aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 80023ae: 60fb str r3, [r7, #12]
+ 80023b0: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
- 8002336: 2301 movs r3, #1
- 8002338: 75fb strb r3, [r7, #23]
+ 80023b2: 2301 movs r3, #1
+ 80023b4: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 800233a: 4b86 ldr r3, [pc, #536] ; (8002554 <HAL_RCC_OscConfig+0x4e0>)
- 800233c: 681b ldr r3, [r3, #0]
- 800233e: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002342: 2b00 cmp r3, #0
- 8002344: d118 bne.n 8002378 <HAL_RCC_OscConfig+0x304>
+ 80023b6: 4b86 ldr r3, [pc, #536] ; (80025d0 <HAL_RCC_OscConfig+0x4e0>)
+ 80023b8: 681b ldr r3, [r3, #0]
+ 80023ba: f403 7380 and.w r3, r3, #256 ; 0x100
+ 80023be: 2b00 cmp r3, #0
+ 80023c0: d118 bne.n 80023f4 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
- 8002346: 4b83 ldr r3, [pc, #524] ; (8002554 <HAL_RCC_OscConfig+0x4e0>)
- 8002348: 681b ldr r3, [r3, #0]
- 800234a: 4a82 ldr r2, [pc, #520] ; (8002554 <HAL_RCC_OscConfig+0x4e0>)
- 800234c: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8002350: 6013 str r3, [r2, #0]
+ 80023c2: 4b83 ldr r3, [pc, #524] ; (80025d0 <HAL_RCC_OscConfig+0x4e0>)
+ 80023c4: 681b ldr r3, [r3, #0]
+ 80023c6: 4a82 ldr r2, [pc, #520] ; (80025d0 <HAL_RCC_OscConfig+0x4e0>)
+ 80023c8: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 80023cc: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
- 8002352: f7ff fb73 bl 8001a3c <HAL_GetTick>
- 8002356: 6138 str r0, [r7, #16]
+ 80023ce: f7ff fb73 bl 8001ab8 <HAL_GetTick>
+ 80023d2: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8002358: e008 b.n 800236c <HAL_RCC_OscConfig+0x2f8>
+ 80023d4: e008 b.n 80023e8 <HAL_RCC_OscConfig+0x2f8>
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 800235a: f7ff fb6f bl 8001a3c <HAL_GetTick>
- 800235e: 4602 mov r2, r0
- 8002360: 693b ldr r3, [r7, #16]
- 8002362: 1ad3 subs r3, r2, r3
- 8002364: 2b64 cmp r3, #100 ; 0x64
- 8002366: d901 bls.n 800236c <HAL_RCC_OscConfig+0x2f8>
+ 80023d6: f7ff fb6f bl 8001ab8 <HAL_GetTick>
+ 80023da: 4602 mov r2, r0
+ 80023dc: 693b ldr r3, [r7, #16]
+ 80023de: 1ad3 subs r3, r2, r3
+ 80023e0: 2b64 cmp r3, #100 ; 0x64
+ 80023e2: d901 bls.n 80023e8 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
- 8002368: 2303 movs r3, #3
- 800236a: e0ed b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 80023e4: 2303 movs r3, #3
+ 80023e6: e0ed b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 800236c: 4b79 ldr r3, [pc, #484] ; (8002554 <HAL_RCC_OscConfig+0x4e0>)
- 800236e: 681b ldr r3, [r3, #0]
- 8002370: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002374: 2b00 cmp r3, #0
- 8002376: d0f0 beq.n 800235a <HAL_RCC_OscConfig+0x2e6>
+ 80023e8: 4b79 ldr r3, [pc, #484] ; (80025d0 <HAL_RCC_OscConfig+0x4e0>)
+ 80023ea: 681b ldr r3, [r3, #0]
+ 80023ec: f403 7380 and.w r3, r3, #256 ; 0x100
+ 80023f0: 2b00 cmp r3, #0
+ 80023f2: d0f0 beq.n 80023d6 <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8002378: 687b ldr r3, [r7, #4]
- 800237a: 689b ldr r3, [r3, #8]
- 800237c: 2b01 cmp r3, #1
- 800237e: d106 bne.n 800238e <HAL_RCC_OscConfig+0x31a>
- 8002380: 4b73 ldr r3, [pc, #460] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002382: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002384: 4a72 ldr r2, [pc, #456] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002386: f043 0301 orr.w r3, r3, #1
- 800238a: 6713 str r3, [r2, #112] ; 0x70
- 800238c: e02d b.n 80023ea <HAL_RCC_OscConfig+0x376>
- 800238e: 687b ldr r3, [r7, #4]
- 8002390: 689b ldr r3, [r3, #8]
- 8002392: 2b00 cmp r3, #0
- 8002394: d10c bne.n 80023b0 <HAL_RCC_OscConfig+0x33c>
- 8002396: 4b6e ldr r3, [pc, #440] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002398: 6f1b ldr r3, [r3, #112] ; 0x70
- 800239a: 4a6d ldr r2, [pc, #436] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 800239c: f023 0301 bic.w r3, r3, #1
- 80023a0: 6713 str r3, [r2, #112] ; 0x70
- 80023a2: 4b6b ldr r3, [pc, #428] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023a4: 6f1b ldr r3, [r3, #112] ; 0x70
- 80023a6: 4a6a ldr r2, [pc, #424] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023a8: f023 0304 bic.w r3, r3, #4
- 80023ac: 6713 str r3, [r2, #112] ; 0x70
- 80023ae: e01c b.n 80023ea <HAL_RCC_OscConfig+0x376>
- 80023b0: 687b ldr r3, [r7, #4]
- 80023b2: 689b ldr r3, [r3, #8]
- 80023b4: 2b05 cmp r3, #5
- 80023b6: d10c bne.n 80023d2 <HAL_RCC_OscConfig+0x35e>
- 80023b8: 4b65 ldr r3, [pc, #404] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023ba: 6f1b ldr r3, [r3, #112] ; 0x70
- 80023bc: 4a64 ldr r2, [pc, #400] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023be: f043 0304 orr.w r3, r3, #4
- 80023c2: 6713 str r3, [r2, #112] ; 0x70
- 80023c4: 4b62 ldr r3, [pc, #392] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023c6: 6f1b ldr r3, [r3, #112] ; 0x70
- 80023c8: 4a61 ldr r2, [pc, #388] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023ca: f043 0301 orr.w r3, r3, #1
- 80023ce: 6713 str r3, [r2, #112] ; 0x70
- 80023d0: e00b b.n 80023ea <HAL_RCC_OscConfig+0x376>
- 80023d2: 4b5f ldr r3, [pc, #380] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023d4: 6f1b ldr r3, [r3, #112] ; 0x70
- 80023d6: 4a5e ldr r2, [pc, #376] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023d8: f023 0301 bic.w r3, r3, #1
- 80023dc: 6713 str r3, [r2, #112] ; 0x70
- 80023de: 4b5c ldr r3, [pc, #368] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023e0: 6f1b ldr r3, [r3, #112] ; 0x70
- 80023e2: 4a5b ldr r2, [pc, #364] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80023e4: f023 0304 bic.w r3, r3, #4
- 80023e8: 6713 str r3, [r2, #112] ; 0x70
+ 80023f4: 687b ldr r3, [r7, #4]
+ 80023f6: 689b ldr r3, [r3, #8]
+ 80023f8: 2b01 cmp r3, #1
+ 80023fa: d106 bne.n 800240a <HAL_RCC_OscConfig+0x31a>
+ 80023fc: 4b73 ldr r3, [pc, #460] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80023fe: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002400: 4a72 ldr r2, [pc, #456] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002402: f043 0301 orr.w r3, r3, #1
+ 8002406: 6713 str r3, [r2, #112] ; 0x70
+ 8002408: e02d b.n 8002466 <HAL_RCC_OscConfig+0x376>
+ 800240a: 687b ldr r3, [r7, #4]
+ 800240c: 689b ldr r3, [r3, #8]
+ 800240e: 2b00 cmp r3, #0
+ 8002410: d10c bne.n 800242c <HAL_RCC_OscConfig+0x33c>
+ 8002412: 4b6e ldr r3, [pc, #440] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002414: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002416: 4a6d ldr r2, [pc, #436] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002418: f023 0301 bic.w r3, r3, #1
+ 800241c: 6713 str r3, [r2, #112] ; 0x70
+ 800241e: 4b6b ldr r3, [pc, #428] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002420: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002422: 4a6a ldr r2, [pc, #424] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002424: f023 0304 bic.w r3, r3, #4
+ 8002428: 6713 str r3, [r2, #112] ; 0x70
+ 800242a: e01c b.n 8002466 <HAL_RCC_OscConfig+0x376>
+ 800242c: 687b ldr r3, [r7, #4]
+ 800242e: 689b ldr r3, [r3, #8]
+ 8002430: 2b05 cmp r3, #5
+ 8002432: d10c bne.n 800244e <HAL_RCC_OscConfig+0x35e>
+ 8002434: 4b65 ldr r3, [pc, #404] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002436: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002438: 4a64 ldr r2, [pc, #400] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800243a: f043 0304 orr.w r3, r3, #4
+ 800243e: 6713 str r3, [r2, #112] ; 0x70
+ 8002440: 4b62 ldr r3, [pc, #392] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002442: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002444: 4a61 ldr r2, [pc, #388] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002446: f043 0301 orr.w r3, r3, #1
+ 800244a: 6713 str r3, [r2, #112] ; 0x70
+ 800244c: e00b b.n 8002466 <HAL_RCC_OscConfig+0x376>
+ 800244e: 4b5f ldr r3, [pc, #380] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002450: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002452: 4a5e ldr r2, [pc, #376] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002454: f023 0301 bic.w r3, r3, #1
+ 8002458: 6713 str r3, [r2, #112] ; 0x70
+ 800245a: 4b5c ldr r3, [pc, #368] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800245c: 6f1b ldr r3, [r3, #112] ; 0x70
+ 800245e: 4a5b ldr r2, [pc, #364] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002460: f023 0304 bic.w r3, r3, #4
+ 8002464: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 80023ea: 687b ldr r3, [r7, #4]
- 80023ec: 689b ldr r3, [r3, #8]
- 80023ee: 2b00 cmp r3, #0
- 80023f0: d015 beq.n 800241e <HAL_RCC_OscConfig+0x3aa>
+ 8002466: 687b ldr r3, [r7, #4]
+ 8002468: 689b ldr r3, [r3, #8]
+ 800246a: 2b00 cmp r3, #0
+ 800246c: d015 beq.n 800249a <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80023f2: f7ff fb23 bl 8001a3c <HAL_GetTick>
- 80023f6: 6138 str r0, [r7, #16]
+ 800246e: f7ff fb23 bl 8001ab8 <HAL_GetTick>
+ 8002472: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80023f8: e00a b.n 8002410 <HAL_RCC_OscConfig+0x39c>
+ 8002474: e00a b.n 800248c <HAL_RCC_OscConfig+0x39c>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80023fa: f7ff fb1f bl 8001a3c <HAL_GetTick>
- 80023fe: 4602 mov r2, r0
- 8002400: 693b ldr r3, [r7, #16]
- 8002402: 1ad3 subs r3, r2, r3
- 8002404: f241 3288 movw r2, #5000 ; 0x1388
- 8002408: 4293 cmp r3, r2
- 800240a: d901 bls.n 8002410 <HAL_RCC_OscConfig+0x39c>
+ 8002476: f7ff fb1f bl 8001ab8 <HAL_GetTick>
+ 800247a: 4602 mov r2, r0
+ 800247c: 693b ldr r3, [r7, #16]
+ 800247e: 1ad3 subs r3, r2, r3
+ 8002480: f241 3288 movw r2, #5000 ; 0x1388
+ 8002484: 4293 cmp r3, r2
+ 8002486: d901 bls.n 800248c <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
- 800240c: 2303 movs r3, #3
- 800240e: e09b b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 8002488: 2303 movs r3, #3
+ 800248a: e09b b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002410: 4b4f ldr r3, [pc, #316] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002412: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002414: f003 0302 and.w r3, r3, #2
- 8002418: 2b00 cmp r3, #0
- 800241a: d0ee beq.n 80023fa <HAL_RCC_OscConfig+0x386>
- 800241c: e014 b.n 8002448 <HAL_RCC_OscConfig+0x3d4>
+ 800248c: 4b4f ldr r3, [pc, #316] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800248e: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002490: f003 0302 and.w r3, r3, #2
+ 8002494: 2b00 cmp r3, #0
+ 8002496: d0ee beq.n 8002476 <HAL_RCC_OscConfig+0x386>
+ 8002498: e014 b.n 80024c4 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 800241e: f7ff fb0d bl 8001a3c <HAL_GetTick>
- 8002422: 6138 str r0, [r7, #16]
+ 800249a: f7ff fb0d bl 8001ab8 <HAL_GetTick>
+ 800249e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8002424: e00a b.n 800243c <HAL_RCC_OscConfig+0x3c8>
+ 80024a0: e00a b.n 80024b8 <HAL_RCC_OscConfig+0x3c8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002426: f7ff fb09 bl 8001a3c <HAL_GetTick>
- 800242a: 4602 mov r2, r0
- 800242c: 693b ldr r3, [r7, #16]
- 800242e: 1ad3 subs r3, r2, r3
- 8002430: f241 3288 movw r2, #5000 ; 0x1388
- 8002434: 4293 cmp r3, r2
- 8002436: d901 bls.n 800243c <HAL_RCC_OscConfig+0x3c8>
+ 80024a2: f7ff fb09 bl 8001ab8 <HAL_GetTick>
+ 80024a6: 4602 mov r2, r0
+ 80024a8: 693b ldr r3, [r7, #16]
+ 80024aa: 1ad3 subs r3, r2, r3
+ 80024ac: f241 3288 movw r2, #5000 ; 0x1388
+ 80024b0: 4293 cmp r3, r2
+ 80024b2: d901 bls.n 80024b8 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
- 8002438: 2303 movs r3, #3
- 800243a: e085 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 80024b4: 2303 movs r3, #3
+ 80024b6: e085 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 800243c: 4b44 ldr r3, [pc, #272] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 800243e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002440: f003 0302 and.w r3, r3, #2
- 8002444: 2b00 cmp r3, #0
- 8002446: d1ee bne.n 8002426 <HAL_RCC_OscConfig+0x3b2>
+ 80024b8: 4b44 ldr r3, [pc, #272] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80024ba: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80024bc: f003 0302 and.w r3, r3, #2
+ 80024c0: 2b00 cmp r3, #0
+ 80024c2: d1ee bne.n 80024a2 <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
- 8002448: 7dfb ldrb r3, [r7, #23]
- 800244a: 2b01 cmp r3, #1
- 800244c: d105 bne.n 800245a <HAL_RCC_OscConfig+0x3e6>
+ 80024c4: 7dfb ldrb r3, [r7, #23]
+ 80024c6: 2b01 cmp r3, #1
+ 80024c8: d105 bne.n 80024d6 <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
- 800244e: 4b40 ldr r3, [pc, #256] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002450: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002452: 4a3f ldr r2, [pc, #252] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002454: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8002458: 6413 str r3, [r2, #64] ; 0x40
+ 80024ca: 4b40 ldr r3, [pc, #256] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80024cc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80024ce: 4a3f ldr r2, [pc, #252] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80024d0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 80024d4: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 800245a: 687b ldr r3, [r7, #4]
- 800245c: 699b ldr r3, [r3, #24]
- 800245e: 2b00 cmp r3, #0
- 8002460: d071 beq.n 8002546 <HAL_RCC_OscConfig+0x4d2>
+ 80024d6: 687b ldr r3, [r7, #4]
+ 80024d8: 699b ldr r3, [r3, #24]
+ 80024da: 2b00 cmp r3, #0
+ 80024dc: d071 beq.n 80025c2 <HAL_RCC_OscConfig+0x4d2>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 8002462: 4b3b ldr r3, [pc, #236] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002464: 689b ldr r3, [r3, #8]
- 8002466: f003 030c and.w r3, r3, #12
- 800246a: 2b08 cmp r3, #8
- 800246c: d069 beq.n 8002542 <HAL_RCC_OscConfig+0x4ce>
+ 80024de: 4b3b ldr r3, [pc, #236] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80024e0: 689b ldr r3, [r3, #8]
+ 80024e2: f003 030c and.w r3, r3, #12
+ 80024e6: 2b08 cmp r3, #8
+ 80024e8: d069 beq.n 80025be <HAL_RCC_OscConfig+0x4ce>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 800246e: 687b ldr r3, [r7, #4]
- 8002470: 699b ldr r3, [r3, #24]
- 8002472: 2b02 cmp r3, #2
- 8002474: d14b bne.n 800250e <HAL_RCC_OscConfig+0x49a>
+ 80024ea: 687b ldr r3, [r7, #4]
+ 80024ec: 699b ldr r3, [r3, #24]
+ 80024ee: 2b02 cmp r3, #2
+ 80024f0: d14b bne.n 800258a <HAL_RCC_OscConfig+0x49a>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 8002476: 4b36 ldr r3, [pc, #216] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002478: 681b ldr r3, [r3, #0]
- 800247a: 4a35 ldr r2, [pc, #212] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 800247c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002480: 6013 str r3, [r2, #0]
+ 80024f2: 4b36 ldr r3, [pc, #216] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80024f4: 681b ldr r3, [r3, #0]
+ 80024f6: 4a35 ldr r2, [pc, #212] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80024f8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 80024fc: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002482: f7ff fadb bl 8001a3c <HAL_GetTick>
- 8002486: 6138 str r0, [r7, #16]
+ 80024fe: f7ff fadb bl 8001ab8 <HAL_GetTick>
+ 8002502: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002488: e008 b.n 800249c <HAL_RCC_OscConfig+0x428>
+ 8002504: e008 b.n 8002518 <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 800248a: f7ff fad7 bl 8001a3c <HAL_GetTick>
- 800248e: 4602 mov r2, r0
- 8002490: 693b ldr r3, [r7, #16]
- 8002492: 1ad3 subs r3, r2, r3
- 8002494: 2b02 cmp r3, #2
- 8002496: d901 bls.n 800249c <HAL_RCC_OscConfig+0x428>
+ 8002506: f7ff fad7 bl 8001ab8 <HAL_GetTick>
+ 800250a: 4602 mov r2, r0
+ 800250c: 693b ldr r3, [r7, #16]
+ 800250e: 1ad3 subs r3, r2, r3
+ 8002510: 2b02 cmp r3, #2
+ 8002512: d901 bls.n 8002518 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
- 8002498: 2303 movs r3, #3
- 800249a: e055 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 8002514: 2303 movs r3, #3
+ 8002516: e055 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 800249c: 4b2c ldr r3, [pc, #176] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 800249e: 681b ldr r3, [r3, #0]
- 80024a0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80024a4: 2b00 cmp r3, #0
- 80024a6: d1f0 bne.n 800248a <HAL_RCC_OscConfig+0x416>
+ 8002518: 4b2c ldr r3, [pc, #176] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800251a: 681b ldr r3, [r3, #0]
+ 800251c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8002520: 2b00 cmp r3, #0
+ 8002522: d1f0 bne.n 8002506 <HAL_RCC_OscConfig+0x416>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined (RCC_PLLCFGR_PLLR)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 80024a8: 687b ldr r3, [r7, #4]
- 80024aa: 69da ldr r2, [r3, #28]
- 80024ac: 687b ldr r3, [r7, #4]
- 80024ae: 6a1b ldr r3, [r3, #32]
- 80024b0: 431a orrs r2, r3
- 80024b2: 687b ldr r3, [r7, #4]
- 80024b4: 6a5b ldr r3, [r3, #36] ; 0x24
- 80024b6: 019b lsls r3, r3, #6
- 80024b8: 431a orrs r2, r3
- 80024ba: 687b ldr r3, [r7, #4]
- 80024bc: 6a9b ldr r3, [r3, #40] ; 0x28
- 80024be: 085b lsrs r3, r3, #1
- 80024c0: 3b01 subs r3, #1
- 80024c2: 041b lsls r3, r3, #16
- 80024c4: 431a orrs r2, r3
- 80024c6: 687b ldr r3, [r7, #4]
- 80024c8: 6adb ldr r3, [r3, #44] ; 0x2c
- 80024ca: 061b lsls r3, r3, #24
- 80024cc: 431a orrs r2, r3
- 80024ce: 687b ldr r3, [r7, #4]
- 80024d0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80024d2: 071b lsls r3, r3, #28
- 80024d4: 491e ldr r1, [pc, #120] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80024d6: 4313 orrs r3, r2
- 80024d8: 604b str r3, [r1, #4]
+ 8002524: 687b ldr r3, [r7, #4]
+ 8002526: 69da ldr r2, [r3, #28]
+ 8002528: 687b ldr r3, [r7, #4]
+ 800252a: 6a1b ldr r3, [r3, #32]
+ 800252c: 431a orrs r2, r3
+ 800252e: 687b ldr r3, [r7, #4]
+ 8002530: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8002532: 019b lsls r3, r3, #6
+ 8002534: 431a orrs r2, r3
+ 8002536: 687b ldr r3, [r7, #4]
+ 8002538: 6a9b ldr r3, [r3, #40] ; 0x28
+ 800253a: 085b lsrs r3, r3, #1
+ 800253c: 3b01 subs r3, #1
+ 800253e: 041b lsls r3, r3, #16
+ 8002540: 431a orrs r2, r3
+ 8002542: 687b ldr r3, [r7, #4]
+ 8002544: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8002546: 061b lsls r3, r3, #24
+ 8002548: 431a orrs r2, r3
+ 800254a: 687b ldr r3, [r7, #4]
+ 800254c: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800254e: 071b lsls r3, r3, #28
+ 8002550: 491e ldr r1, [pc, #120] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002552: 4313 orrs r3, r2
+ 8002554: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- 80024da: 4b1d ldr r3, [pc, #116] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80024dc: 681b ldr r3, [r3, #0]
- 80024de: 4a1c ldr r2, [pc, #112] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 80024e0: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 80024e4: 6013 str r3, [r2, #0]
+ 8002556: 4b1d ldr r3, [pc, #116] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002558: 681b ldr r3, [r3, #0]
+ 800255a: 4a1c ldr r2, [pc, #112] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800255c: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
+ 8002560: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80024e6: f7ff faa9 bl 8001a3c <HAL_GetTick>
- 80024ea: 6138 str r0, [r7, #16]
+ 8002562: f7ff faa9 bl 8001ab8 <HAL_GetTick>
+ 8002566: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80024ec: e008 b.n 8002500 <HAL_RCC_OscConfig+0x48c>
+ 8002568: e008 b.n 800257c <HAL_RCC_OscConfig+0x48c>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80024ee: f7ff faa5 bl 8001a3c <HAL_GetTick>
- 80024f2: 4602 mov r2, r0
- 80024f4: 693b ldr r3, [r7, #16]
- 80024f6: 1ad3 subs r3, r2, r3
- 80024f8: 2b02 cmp r3, #2
- 80024fa: d901 bls.n 8002500 <HAL_RCC_OscConfig+0x48c>
+ 800256a: f7ff faa5 bl 8001ab8 <HAL_GetTick>
+ 800256e: 4602 mov r2, r0
+ 8002570: 693b ldr r3, [r7, #16]
+ 8002572: 1ad3 subs r3, r2, r3
+ 8002574: 2b02 cmp r3, #2
+ 8002576: d901 bls.n 800257c <HAL_RCC_OscConfig+0x48c>
{
return HAL_TIMEOUT;
- 80024fc: 2303 movs r3, #3
- 80024fe: e023 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 8002578: 2303 movs r3, #3
+ 800257a: e023 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8002500: 4b13 ldr r3, [pc, #76] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002502: 681b ldr r3, [r3, #0]
- 8002504: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002508: 2b00 cmp r3, #0
- 800250a: d0f0 beq.n 80024ee <HAL_RCC_OscConfig+0x47a>
- 800250c: e01b b.n 8002546 <HAL_RCC_OscConfig+0x4d2>
+ 800257c: 4b13 ldr r3, [pc, #76] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800257e: 681b ldr r3, [r3, #0]
+ 8002580: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8002584: 2b00 cmp r3, #0
+ 8002586: d0f0 beq.n 800256a <HAL_RCC_OscConfig+0x47a>
+ 8002588: e01b b.n 80025c2 <HAL_RCC_OscConfig+0x4d2>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 800250e: 4b10 ldr r3, [pc, #64] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002510: 681b ldr r3, [r3, #0]
- 8002512: 4a0f ldr r2, [pc, #60] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002514: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002518: 6013 str r3, [r2, #0]
+ 800258a: 4b10 ldr r3, [pc, #64] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 800258c: 681b ldr r3, [r3, #0]
+ 800258e: 4a0f ldr r2, [pc, #60] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 8002590: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8002594: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 800251a: f7ff fa8f bl 8001a3c <HAL_GetTick>
- 800251e: 6138 str r0, [r7, #16]
+ 8002596: f7ff fa8f bl 8001ab8 <HAL_GetTick>
+ 800259a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002520: e008 b.n 8002534 <HAL_RCC_OscConfig+0x4c0>
+ 800259c: e008 b.n 80025b0 <HAL_RCC_OscConfig+0x4c0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8002522: f7ff fa8b bl 8001a3c <HAL_GetTick>
- 8002526: 4602 mov r2, r0
- 8002528: 693b ldr r3, [r7, #16]
- 800252a: 1ad3 subs r3, r2, r3
- 800252c: 2b02 cmp r3, #2
- 800252e: d901 bls.n 8002534 <HAL_RCC_OscConfig+0x4c0>
+ 800259e: f7ff fa8b bl 8001ab8 <HAL_GetTick>
+ 80025a2: 4602 mov r2, r0
+ 80025a4: 693b ldr r3, [r7, #16]
+ 80025a6: 1ad3 subs r3, r2, r3
+ 80025a8: 2b02 cmp r3, #2
+ 80025aa: d901 bls.n 80025b0 <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
- 8002530: 2303 movs r3, #3
- 8002532: e009 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 80025ac: 2303 movs r3, #3
+ 80025ae: e009 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8002534: 4b06 ldr r3, [pc, #24] ; (8002550 <HAL_RCC_OscConfig+0x4dc>)
- 8002536: 681b ldr r3, [r3, #0]
- 8002538: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 800253c: 2b00 cmp r3, #0
- 800253e: d1f0 bne.n 8002522 <HAL_RCC_OscConfig+0x4ae>
- 8002540: e001 b.n 8002546 <HAL_RCC_OscConfig+0x4d2>
+ 80025b0: 4b06 ldr r3, [pc, #24] ; (80025cc <HAL_RCC_OscConfig+0x4dc>)
+ 80025b2: 681b ldr r3, [r3, #0]
+ 80025b4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 80025b8: 2b00 cmp r3, #0
+ 80025ba: d1f0 bne.n 800259e <HAL_RCC_OscConfig+0x4ae>
+ 80025bc: e001 b.n 80025c2 <HAL_RCC_OscConfig+0x4d2>
}
}
}
else
{
return HAL_ERROR;
- 8002542: 2301 movs r3, #1
- 8002544: e000 b.n 8002548 <HAL_RCC_OscConfig+0x4d4>
+ 80025be: 2301 movs r3, #1
+ 80025c0: e000 b.n 80025c4 <HAL_RCC_OscConfig+0x4d4>
}
}
return HAL_OK;
- 8002546: 2300 movs r3, #0
+ 80025c2: 2300 movs r3, #0
}
- 8002548: 4618 mov r0, r3
- 800254a: 3718 adds r7, #24
- 800254c: 46bd mov sp, r7
- 800254e: bd80 pop {r7, pc}
- 8002550: 40023800 .word 0x40023800
- 8002554: 40007000 .word 0x40007000
-
-08002558 <HAL_RCC_ClockConfig>:
+ 80025c4: 4618 mov r0, r3
+ 80025c6: 3718 adds r7, #24
+ 80025c8: 46bd mov sp, r7
+ 80025ca: bd80 pop {r7, pc}
+ 80025cc: 40023800 .word 0x40023800
+ 80025d0: 40007000 .word 0x40007000
+
+080025d4 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- 8002558: b580 push {r7, lr}
- 800255a: b084 sub sp, #16
- 800255c: af00 add r7, sp, #0
- 800255e: 6078 str r0, [r7, #4]
- 8002560: 6039 str r1, [r7, #0]
+ 80025d4: b580 push {r7, lr}
+ 80025d6: b084 sub sp, #16
+ 80025d8: af00 add r7, sp, #0
+ 80025da: 6078 str r0, [r7, #4]
+ 80025dc: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
- 8002562: 2300 movs r3, #0
- 8002564: 60fb str r3, [r7, #12]
+ 80025de: 2300 movs r3, #0
+ 80025e0: 60fb str r3, [r7, #12]
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
- 8002566: 687b ldr r3, [r7, #4]
- 8002568: 2b00 cmp r3, #0
- 800256a: d101 bne.n 8002570 <HAL_RCC_ClockConfig+0x18>
+ 80025e2: 687b ldr r3, [r7, #4]
+ 80025e4: 2b00 cmp r3, #0
+ 80025e6: d101 bne.n 80025ec <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
- 800256c: 2301 movs r3, #1
- 800256e: e0ce b.n 800270e <HAL_RCC_ClockConfig+0x1b6>
+ 80025e8: 2301 movs r3, #1
+ 80025ea: e0ce b.n 800278a <HAL_RCC_ClockConfig+0x1b6>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8002570: 4b69 ldr r3, [pc, #420] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 8002572: 681b ldr r3, [r3, #0]
- 8002574: f003 030f and.w r3, r3, #15
- 8002578: 683a ldr r2, [r7, #0]
- 800257a: 429a cmp r2, r3
- 800257c: d910 bls.n 80025a0 <HAL_RCC_ClockConfig+0x48>
+ 80025ec: 4b69 ldr r3, [pc, #420] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 80025ee: 681b ldr r3, [r3, #0]
+ 80025f0: f003 030f and.w r3, r3, #15
+ 80025f4: 683a ldr r2, [r7, #0]
+ 80025f6: 429a cmp r2, r3
+ 80025f8: d910 bls.n 800261c <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 800257e: 4b66 ldr r3, [pc, #408] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 8002580: 681b ldr r3, [r3, #0]
- 8002582: f023 020f bic.w r2, r3, #15
- 8002586: 4964 ldr r1, [pc, #400] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 8002588: 683b ldr r3, [r7, #0]
- 800258a: 4313 orrs r3, r2
- 800258c: 600b str r3, [r1, #0]
+ 80025fa: 4b66 ldr r3, [pc, #408] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 80025fc: 681b ldr r3, [r3, #0]
+ 80025fe: f023 020f bic.w r2, r3, #15
+ 8002602: 4964 ldr r1, [pc, #400] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 8002604: 683b ldr r3, [r7, #0]
+ 8002606: 4313 orrs r3, r2
+ 8002608: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800258e: 4b62 ldr r3, [pc, #392] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 8002590: 681b ldr r3, [r3, #0]
- 8002592: f003 030f and.w r3, r3, #15
- 8002596: 683a ldr r2, [r7, #0]
- 8002598: 429a cmp r2, r3
- 800259a: d001 beq.n 80025a0 <HAL_RCC_ClockConfig+0x48>
+ 800260a: 4b62 ldr r3, [pc, #392] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 800260c: 681b ldr r3, [r3, #0]
+ 800260e: f003 030f and.w r3, r3, #15
+ 8002612: 683a ldr r2, [r7, #0]
+ 8002614: 429a cmp r2, r3
+ 8002616: d001 beq.n 800261c <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
- 800259c: 2301 movs r3, #1
- 800259e: e0b6 b.n 800270e <HAL_RCC_ClockConfig+0x1b6>
+ 8002618: 2301 movs r3, #1
+ 800261a: e0b6 b.n 800278a <HAL_RCC_ClockConfig+0x1b6>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 80025a0: 687b ldr r3, [r7, #4]
- 80025a2: 681b ldr r3, [r3, #0]
- 80025a4: f003 0302 and.w r3, r3, #2
- 80025a8: 2b00 cmp r3, #0
- 80025aa: d020 beq.n 80025ee <HAL_RCC_ClockConfig+0x96>
+ 800261c: 687b ldr r3, [r7, #4]
+ 800261e: 681b ldr r3, [r3, #0]
+ 8002620: f003 0302 and.w r3, r3, #2
+ 8002624: 2b00 cmp r3, #0
+ 8002626: d020 beq.n 800266a <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 80025ac: 687b ldr r3, [r7, #4]
- 80025ae: 681b ldr r3, [r3, #0]
- 80025b0: f003 0304 and.w r3, r3, #4
- 80025b4: 2b00 cmp r3, #0
- 80025b6: d005 beq.n 80025c4 <HAL_RCC_ClockConfig+0x6c>
+ 8002628: 687b ldr r3, [r7, #4]
+ 800262a: 681b ldr r3, [r3, #0]
+ 800262c: f003 0304 and.w r3, r3, #4
+ 8002630: 2b00 cmp r3, #0
+ 8002632: d005 beq.n 8002640 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 80025b8: 4b58 ldr r3, [pc, #352] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80025ba: 689b ldr r3, [r3, #8]
- 80025bc: 4a57 ldr r2, [pc, #348] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80025be: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 80025c2: 6093 str r3, [r2, #8]
+ 8002634: 4b58 ldr r3, [pc, #352] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002636: 689b ldr r3, [r3, #8]
+ 8002638: 4a57 ldr r2, [pc, #348] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 800263a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
+ 800263e: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 80025c4: 687b ldr r3, [r7, #4]
- 80025c6: 681b ldr r3, [r3, #0]
- 80025c8: f003 0308 and.w r3, r3, #8
- 80025cc: 2b00 cmp r3, #0
- 80025ce: d005 beq.n 80025dc <HAL_RCC_ClockConfig+0x84>
+ 8002640: 687b ldr r3, [r7, #4]
+ 8002642: 681b ldr r3, [r3, #0]
+ 8002644: f003 0308 and.w r3, r3, #8
+ 8002648: 2b00 cmp r3, #0
+ 800264a: d005 beq.n 8002658 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 80025d0: 4b52 ldr r3, [pc, #328] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80025d2: 689b ldr r3, [r3, #8]
- 80025d4: 4a51 ldr r2, [pc, #324] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80025d6: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 80025da: 6093 str r3, [r2, #8]
+ 800264c: 4b52 ldr r3, [pc, #328] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 800264e: 689b ldr r3, [r3, #8]
+ 8002650: 4a51 ldr r2, [pc, #324] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002652: f443 4360 orr.w r3, r3, #57344 ; 0xe000
+ 8002656: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 80025dc: 4b4f ldr r3, [pc, #316] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80025de: 689b ldr r3, [r3, #8]
- 80025e0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 80025e4: 687b ldr r3, [r7, #4]
- 80025e6: 689b ldr r3, [r3, #8]
- 80025e8: 494c ldr r1, [pc, #304] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80025ea: 4313 orrs r3, r2
- 80025ec: 608b str r3, [r1, #8]
+ 8002658: 4b4f ldr r3, [pc, #316] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 800265a: 689b ldr r3, [r3, #8]
+ 800265c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
+ 8002660: 687b ldr r3, [r7, #4]
+ 8002662: 689b ldr r3, [r3, #8]
+ 8002664: 494c ldr r1, [pc, #304] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002666: 4313 orrs r3, r2
+ 8002668: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 80025ee: 687b ldr r3, [r7, #4]
- 80025f0: 681b ldr r3, [r3, #0]
- 80025f2: f003 0301 and.w r3, r3, #1
- 80025f6: 2b00 cmp r3, #0
- 80025f8: d040 beq.n 800267c <HAL_RCC_ClockConfig+0x124>
+ 800266a: 687b ldr r3, [r7, #4]
+ 800266c: 681b ldr r3, [r3, #0]
+ 800266e: f003 0301 and.w r3, r3, #1
+ 8002672: 2b00 cmp r3, #0
+ 8002674: d040 beq.n 80026f8 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 80025fa: 687b ldr r3, [r7, #4]
- 80025fc: 685b ldr r3, [r3, #4]
- 80025fe: 2b01 cmp r3, #1
- 8002600: d107 bne.n 8002612 <HAL_RCC_ClockConfig+0xba>
+ 8002676: 687b ldr r3, [r7, #4]
+ 8002678: 685b ldr r3, [r3, #4]
+ 800267a: 2b01 cmp r3, #1
+ 800267c: d107 bne.n 800268e <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8002602: 4b46 ldr r3, [pc, #280] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 8002604: 681b ldr r3, [r3, #0]
- 8002606: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800260a: 2b00 cmp r3, #0
- 800260c: d115 bne.n 800263a <HAL_RCC_ClockConfig+0xe2>
+ 800267e: 4b46 ldr r3, [pc, #280] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002680: 681b ldr r3, [r3, #0]
+ 8002682: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8002686: 2b00 cmp r3, #0
+ 8002688: d115 bne.n 80026b6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 800260e: 2301 movs r3, #1
- 8002610: e07d b.n 800270e <HAL_RCC_ClockConfig+0x1b6>
+ 800268a: 2301 movs r3, #1
+ 800268c: e07d b.n 800278a <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 8002612: 687b ldr r3, [r7, #4]
- 8002614: 685b ldr r3, [r3, #4]
- 8002616: 2b02 cmp r3, #2
- 8002618: d107 bne.n 800262a <HAL_RCC_ClockConfig+0xd2>
+ 800268e: 687b ldr r3, [r7, #4]
+ 8002690: 685b ldr r3, [r3, #4]
+ 8002692: 2b02 cmp r3, #2
+ 8002694: d107 bne.n 80026a6 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 800261a: 4b40 ldr r3, [pc, #256] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 800261c: 681b ldr r3, [r3, #0]
- 800261e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002622: 2b00 cmp r3, #0
- 8002624: d109 bne.n 800263a <HAL_RCC_ClockConfig+0xe2>
+ 8002696: 4b40 ldr r3, [pc, #256] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002698: 681b ldr r3, [r3, #0]
+ 800269a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 800269e: 2b00 cmp r3, #0
+ 80026a0: d109 bne.n 80026b6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 8002626: 2301 movs r3, #1
- 8002628: e071 b.n 800270e <HAL_RCC_ClockConfig+0x1b6>
+ 80026a2: 2301 movs r3, #1
+ 80026a4: e071 b.n 800278a <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 800262a: 4b3c ldr r3, [pc, #240] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 800262c: 681b ldr r3, [r3, #0]
- 800262e: f003 0302 and.w r3, r3, #2
- 8002632: 2b00 cmp r3, #0
- 8002634: d101 bne.n 800263a <HAL_RCC_ClockConfig+0xe2>
+ 80026a6: 4b3c ldr r3, [pc, #240] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 80026a8: 681b ldr r3, [r3, #0]
+ 80026aa: f003 0302 and.w r3, r3, #2
+ 80026ae: 2b00 cmp r3, #0
+ 80026b0: d101 bne.n 80026b6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 8002636: 2301 movs r3, #1
- 8002638: e069 b.n 800270e <HAL_RCC_ClockConfig+0x1b6>
+ 80026b2: 2301 movs r3, #1
+ 80026b4: e069 b.n 800278a <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 800263a: 4b38 ldr r3, [pc, #224] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 800263c: 689b ldr r3, [r3, #8]
- 800263e: f023 0203 bic.w r2, r3, #3
- 8002642: 687b ldr r3, [r7, #4]
- 8002644: 685b ldr r3, [r3, #4]
- 8002646: 4935 ldr r1, [pc, #212] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 8002648: 4313 orrs r3, r2
- 800264a: 608b str r3, [r1, #8]
+ 80026b6: 4b38 ldr r3, [pc, #224] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 80026b8: 689b ldr r3, [r3, #8]
+ 80026ba: f023 0203 bic.w r2, r3, #3
+ 80026be: 687b ldr r3, [r7, #4]
+ 80026c0: 685b ldr r3, [r3, #4]
+ 80026c2: 4935 ldr r1, [pc, #212] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 80026c4: 4313 orrs r3, r2
+ 80026c6: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 800264c: f7ff f9f6 bl 8001a3c <HAL_GetTick>
- 8002650: 60f8 str r0, [r7, #12]
+ 80026c8: f7ff f9f6 bl 8001ab8 <HAL_GetTick>
+ 80026cc: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8002652: e00a b.n 800266a <HAL_RCC_ClockConfig+0x112>
+ 80026ce: e00a b.n 80026e6 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002654: f7ff f9f2 bl 8001a3c <HAL_GetTick>
- 8002658: 4602 mov r2, r0
- 800265a: 68fb ldr r3, [r7, #12]
- 800265c: 1ad3 subs r3, r2, r3
- 800265e: f241 3288 movw r2, #5000 ; 0x1388
- 8002662: 4293 cmp r3, r2
- 8002664: d901 bls.n 800266a <HAL_RCC_ClockConfig+0x112>
+ 80026d0: f7ff f9f2 bl 8001ab8 <HAL_GetTick>
+ 80026d4: 4602 mov r2, r0
+ 80026d6: 68fb ldr r3, [r7, #12]
+ 80026d8: 1ad3 subs r3, r2, r3
+ 80026da: f241 3288 movw r2, #5000 ; 0x1388
+ 80026de: 4293 cmp r3, r2
+ 80026e0: d901 bls.n 80026e6 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
- 8002666: 2303 movs r3, #3
- 8002668: e051 b.n 800270e <HAL_RCC_ClockConfig+0x1b6>
+ 80026e2: 2303 movs r3, #3
+ 80026e4: e051 b.n 800278a <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 800266a: 4b2c ldr r3, [pc, #176] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 800266c: 689b ldr r3, [r3, #8]
- 800266e: f003 020c and.w r2, r3, #12
- 8002672: 687b ldr r3, [r7, #4]
- 8002674: 685b ldr r3, [r3, #4]
- 8002676: 009b lsls r3, r3, #2
- 8002678: 429a cmp r2, r3
- 800267a: d1eb bne.n 8002654 <HAL_RCC_ClockConfig+0xfc>
+ 80026e6: 4b2c ldr r3, [pc, #176] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 80026e8: 689b ldr r3, [r3, #8]
+ 80026ea: f003 020c and.w r2, r3, #12
+ 80026ee: 687b ldr r3, [r7, #4]
+ 80026f0: 685b ldr r3, [r3, #4]
+ 80026f2: 009b lsls r3, r3, #2
+ 80026f4: 429a cmp r2, r3
+ 80026f6: d1eb bne.n 80026d0 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
- 800267c: 4b26 ldr r3, [pc, #152] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 800267e: 681b ldr r3, [r3, #0]
- 8002680: f003 030f and.w r3, r3, #15
- 8002684: 683a ldr r2, [r7, #0]
- 8002686: 429a cmp r2, r3
- 8002688: d210 bcs.n 80026ac <HAL_RCC_ClockConfig+0x154>
+ 80026f8: 4b26 ldr r3, [pc, #152] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 80026fa: 681b ldr r3, [r3, #0]
+ 80026fc: f003 030f and.w r3, r3, #15
+ 8002700: 683a ldr r2, [r7, #0]
+ 8002702: 429a cmp r2, r3
+ 8002704: d210 bcs.n 8002728 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 800268a: 4b23 ldr r3, [pc, #140] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 800268c: 681b ldr r3, [r3, #0]
- 800268e: f023 020f bic.w r2, r3, #15
- 8002692: 4921 ldr r1, [pc, #132] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 8002694: 683b ldr r3, [r7, #0]
- 8002696: 4313 orrs r3, r2
- 8002698: 600b str r3, [r1, #0]
+ 8002706: 4b23 ldr r3, [pc, #140] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 8002708: 681b ldr r3, [r3, #0]
+ 800270a: f023 020f bic.w r2, r3, #15
+ 800270e: 4921 ldr r1, [pc, #132] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 8002710: 683b ldr r3, [r7, #0]
+ 8002712: 4313 orrs r3, r2
+ 8002714: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800269a: 4b1f ldr r3, [pc, #124] ; (8002718 <HAL_RCC_ClockConfig+0x1c0>)
- 800269c: 681b ldr r3, [r3, #0]
- 800269e: f003 030f and.w r3, r3, #15
- 80026a2: 683a ldr r2, [r7, #0]
- 80026a4: 429a cmp r2, r3
- 80026a6: d001 beq.n 80026ac <HAL_RCC_ClockConfig+0x154>
+ 8002716: 4b1f ldr r3, [pc, #124] ; (8002794 <HAL_RCC_ClockConfig+0x1c0>)
+ 8002718: 681b ldr r3, [r3, #0]
+ 800271a: f003 030f and.w r3, r3, #15
+ 800271e: 683a ldr r2, [r7, #0]
+ 8002720: 429a cmp r2, r3
+ 8002722: d001 beq.n 8002728 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
- 80026a8: 2301 movs r3, #1
- 80026aa: e030 b.n 800270e <HAL_RCC_ClockConfig+0x1b6>
+ 8002724: 2301 movs r3, #1
+ 8002726: e030 b.n 800278a <HAL_RCC_ClockConfig+0x1b6>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 80026ac: 687b ldr r3, [r7, #4]
- 80026ae: 681b ldr r3, [r3, #0]
- 80026b0: f003 0304 and.w r3, r3, #4
- 80026b4: 2b00 cmp r3, #0
- 80026b6: d008 beq.n 80026ca <HAL_RCC_ClockConfig+0x172>
+ 8002728: 687b ldr r3, [r7, #4]
+ 800272a: 681b ldr r3, [r3, #0]
+ 800272c: f003 0304 and.w r3, r3, #4
+ 8002730: 2b00 cmp r3, #0
+ 8002732: d008 beq.n 8002746 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 80026b8: 4b18 ldr r3, [pc, #96] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80026ba: 689b ldr r3, [r3, #8]
- 80026bc: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 80026c0: 687b ldr r3, [r7, #4]
- 80026c2: 68db ldr r3, [r3, #12]
- 80026c4: 4915 ldr r1, [pc, #84] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80026c6: 4313 orrs r3, r2
- 80026c8: 608b str r3, [r1, #8]
+ 8002734: 4b18 ldr r3, [pc, #96] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002736: 689b ldr r3, [r3, #8]
+ 8002738: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
+ 800273c: 687b ldr r3, [r7, #4]
+ 800273e: 68db ldr r3, [r3, #12]
+ 8002740: 4915 ldr r1, [pc, #84] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002742: 4313 orrs r3, r2
+ 8002744: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 80026ca: 687b ldr r3, [r7, #4]
- 80026cc: 681b ldr r3, [r3, #0]
- 80026ce: f003 0308 and.w r3, r3, #8
- 80026d2: 2b00 cmp r3, #0
- 80026d4: d009 beq.n 80026ea <HAL_RCC_ClockConfig+0x192>
+ 8002746: 687b ldr r3, [r7, #4]
+ 8002748: 681b ldr r3, [r3, #0]
+ 800274a: f003 0308 and.w r3, r3, #8
+ 800274e: 2b00 cmp r3, #0
+ 8002750: d009 beq.n 8002766 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 80026d6: 4b11 ldr r3, [pc, #68] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80026d8: 689b ldr r3, [r3, #8]
- 80026da: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 80026de: 687b ldr r3, [r7, #4]
- 80026e0: 691b ldr r3, [r3, #16]
- 80026e2: 00db lsls r3, r3, #3
- 80026e4: 490d ldr r1, [pc, #52] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80026e6: 4313 orrs r3, r2
- 80026e8: 608b str r3, [r1, #8]
+ 8002752: 4b11 ldr r3, [pc, #68] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002754: 689b ldr r3, [r3, #8]
+ 8002756: f423 4260 bic.w r2, r3, #57344 ; 0xe000
+ 800275a: 687b ldr r3, [r7, #4]
+ 800275c: 691b ldr r3, [r3, #16]
+ 800275e: 00db lsls r3, r3, #3
+ 8002760: 490d ldr r1, [pc, #52] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 8002762: 4313 orrs r3, r2
+ 8002764: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 80026ea: f000 f81d bl 8002728 <HAL_RCC_GetSysClockFreq>
- 80026ee: 4601 mov r1, r0
- 80026f0: 4b0a ldr r3, [pc, #40] ; (800271c <HAL_RCC_ClockConfig+0x1c4>)
- 80026f2: 689b ldr r3, [r3, #8]
- 80026f4: 091b lsrs r3, r3, #4
- 80026f6: f003 030f and.w r3, r3, #15
- 80026fa: 4a09 ldr r2, [pc, #36] ; (8002720 <HAL_RCC_ClockConfig+0x1c8>)
- 80026fc: 5cd3 ldrb r3, [r2, r3]
- 80026fe: fa21 f303 lsr.w r3, r1, r3
- 8002702: 4a08 ldr r2, [pc, #32] ; (8002724 <HAL_RCC_ClockConfig+0x1cc>)
- 8002704: 6013 str r3, [r2, #0]
+ 8002766: f000 f81d bl 80027a4 <HAL_RCC_GetSysClockFreq>
+ 800276a: 4601 mov r1, r0
+ 800276c: 4b0a ldr r3, [pc, #40] ; (8002798 <HAL_RCC_ClockConfig+0x1c4>)
+ 800276e: 689b ldr r3, [r3, #8]
+ 8002770: 091b lsrs r3, r3, #4
+ 8002772: f003 030f and.w r3, r3, #15
+ 8002776: 4a09 ldr r2, [pc, #36] ; (800279c <HAL_RCC_ClockConfig+0x1c8>)
+ 8002778: 5cd3 ldrb r3, [r2, r3]
+ 800277a: fa21 f303 lsr.w r3, r1, r3
+ 800277e: 4a08 ldr r2, [pc, #32] ; (80027a0 <HAL_RCC_ClockConfig+0x1cc>)
+ 8002780: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
- 8002706: 2000 movs r0, #0
- 8002708: f7ff f954 bl 80019b4 <HAL_InitTick>
+ 8002782: 2000 movs r0, #0
+ 8002784: f7ff f954 bl 8001a30 <HAL_InitTick>
return HAL_OK;
- 800270c: 2300 movs r3, #0
+ 8002788: 2300 movs r3, #0
}
- 800270e: 4618 mov r0, r3
- 8002710: 3710 adds r7, #16
- 8002712: 46bd mov sp, r7
- 8002714: bd80 pop {r7, pc}
- 8002716: bf00 nop
- 8002718: 40023c00 .word 0x40023c00
- 800271c: 40023800 .word 0x40023800
- 8002720: 08004fbc .word 0x08004fbc
- 8002724: 20000004 .word 0x20000004
-
-08002728 <HAL_RCC_GetSysClockFreq>:
+ 800278a: 4618 mov r0, r3
+ 800278c: 3710 adds r7, #16
+ 800278e: 46bd mov sp, r7
+ 8002790: bd80 pop {r7, pc}
+ 8002792: bf00 nop
+ 8002794: 40023c00 .word 0x40023c00
+ 8002798: 40023800 .word 0x40023800
+ 800279c: 080052c8 .word 0x080052c8
+ 80027a0: 20000008 .word 0x20000008
+
+080027a4 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
- 8002728: b5f0 push {r4, r5, r6, r7, lr}
- 800272a: b085 sub sp, #20
- 800272c: af00 add r7, sp, #0
+ 80027a4: b5f0 push {r4, r5, r6, r7, lr}
+ 80027a6: b085 sub sp, #20
+ 80027a8: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 800272e: 2300 movs r3, #0
- 8002730: 607b str r3, [r7, #4]
- 8002732: 2300 movs r3, #0
- 8002734: 60fb str r3, [r7, #12]
- 8002736: 2300 movs r3, #0
- 8002738: 603b str r3, [r7, #0]
+ 80027aa: 2300 movs r3, #0
+ 80027ac: 607b str r3, [r7, #4]
+ 80027ae: 2300 movs r3, #0
+ 80027b0: 60fb str r3, [r7, #12]
+ 80027b2: 2300 movs r3, #0
+ 80027b4: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0;
- 800273a: 2300 movs r3, #0
- 800273c: 60bb str r3, [r7, #8]
+ 80027b6: 2300 movs r3, #0
+ 80027b8: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
- 800273e: 4b50 ldr r3, [pc, #320] ; (8002880 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002740: 689b ldr r3, [r3, #8]
- 8002742: f003 030c and.w r3, r3, #12
- 8002746: 2b04 cmp r3, #4
- 8002748: d007 beq.n 800275a <HAL_RCC_GetSysClockFreq+0x32>
- 800274a: 2b08 cmp r3, #8
- 800274c: d008 beq.n 8002760 <HAL_RCC_GetSysClockFreq+0x38>
- 800274e: 2b00 cmp r3, #0
- 8002750: f040 808d bne.w 800286e <HAL_RCC_GetSysClockFreq+0x146>
+ 80027ba: 4b50 ldr r3, [pc, #320] ; (80028fc <HAL_RCC_GetSysClockFreq+0x158>)
+ 80027bc: 689b ldr r3, [r3, #8]
+ 80027be: f003 030c and.w r3, r3, #12
+ 80027c2: 2b04 cmp r3, #4
+ 80027c4: d007 beq.n 80027d6 <HAL_RCC_GetSysClockFreq+0x32>
+ 80027c6: 2b08 cmp r3, #8
+ 80027c8: d008 beq.n 80027dc <HAL_RCC_GetSysClockFreq+0x38>
+ 80027ca: 2b00 cmp r3, #0
+ 80027cc: f040 808d bne.w 80028ea <HAL_RCC_GetSysClockFreq+0x146>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
- 8002754: 4b4b ldr r3, [pc, #300] ; (8002884 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8002756: 60bb str r3, [r7, #8]
+ 80027d0: 4b4b ldr r3, [pc, #300] ; (8002900 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 80027d2: 60bb str r3, [r7, #8]
break;
- 8002758: e08c b.n 8002874 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80027d4: e08c b.n 80028f0 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
- 800275a: 4b4b ldr r3, [pc, #300] ; (8002888 <HAL_RCC_GetSysClockFreq+0x160>)
- 800275c: 60bb str r3, [r7, #8]
+ 80027d6: 4b4b ldr r3, [pc, #300] ; (8002904 <HAL_RCC_GetSysClockFreq+0x160>)
+ 80027d8: 60bb str r3, [r7, #8]
break;
- 800275e: e089 b.n 8002874 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80027da: e089 b.n 80028f0 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 8002760: 4b47 ldr r3, [pc, #284] ; (8002880 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002762: 685b ldr r3, [r3, #4]
- 8002764: f003 033f and.w r3, r3, #63 ; 0x3f
- 8002768: 607b str r3, [r7, #4]
+ 80027dc: 4b47 ldr r3, [pc, #284] ; (80028fc <HAL_RCC_GetSysClockFreq+0x158>)
+ 80027de: 685b ldr r3, [r3, #4]
+ 80027e0: f003 033f and.w r3, r3, #63 ; 0x3f
+ 80027e4: 607b str r3, [r7, #4]
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 800276a: 4b45 ldr r3, [pc, #276] ; (8002880 <HAL_RCC_GetSysClockFreq+0x158>)
- 800276c: 685b ldr r3, [r3, #4]
- 800276e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002772: 2b00 cmp r3, #0
- 8002774: d023 beq.n 80027be <HAL_RCC_GetSysClockFreq+0x96>
+ 80027e6: 4b45 ldr r3, [pc, #276] ; (80028fc <HAL_RCC_GetSysClockFreq+0x158>)
+ 80027e8: 685b ldr r3, [r3, #4]
+ 80027ea: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 80027ee: 2b00 cmp r3, #0
+ 80027f0: d023 beq.n 800283a <HAL_RCC_GetSysClockFreq+0x96>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002776: 4b42 ldr r3, [pc, #264] ; (8002880 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002778: 685b ldr r3, [r3, #4]
- 800277a: 099b lsrs r3, r3, #6
- 800277c: f04f 0400 mov.w r4, #0
- 8002780: f240 11ff movw r1, #511 ; 0x1ff
- 8002784: f04f 0200 mov.w r2, #0
- 8002788: ea03 0501 and.w r5, r3, r1
- 800278c: ea04 0602 and.w r6, r4, r2
- 8002790: 4a3d ldr r2, [pc, #244] ; (8002888 <HAL_RCC_GetSysClockFreq+0x160>)
- 8002792: fb02 f106 mul.w r1, r2, r6
- 8002796: 2200 movs r2, #0
- 8002798: fb02 f205 mul.w r2, r2, r5
- 800279c: 440a add r2, r1
- 800279e: 493a ldr r1, [pc, #232] ; (8002888 <HAL_RCC_GetSysClockFreq+0x160>)
- 80027a0: fba5 0101 umull r0, r1, r5, r1
- 80027a4: 1853 adds r3, r2, r1
- 80027a6: 4619 mov r1, r3
- 80027a8: 687b ldr r3, [r7, #4]
- 80027aa: f04f 0400 mov.w r4, #0
- 80027ae: 461a mov r2, r3
- 80027b0: 4623 mov r3, r4
- 80027b2: f7fd fd41 bl 8000238 <__aeabi_uldivmod>
- 80027b6: 4603 mov r3, r0
- 80027b8: 460c mov r4, r1
- 80027ba: 60fb str r3, [r7, #12]
- 80027bc: e049 b.n 8002852 <HAL_RCC_GetSysClockFreq+0x12a>
+ 80027f2: 4b42 ldr r3, [pc, #264] ; (80028fc <HAL_RCC_GetSysClockFreq+0x158>)
+ 80027f4: 685b ldr r3, [r3, #4]
+ 80027f6: 099b lsrs r3, r3, #6
+ 80027f8: f04f 0400 mov.w r4, #0
+ 80027fc: f240 11ff movw r1, #511 ; 0x1ff
+ 8002800: f04f 0200 mov.w r2, #0
+ 8002804: ea03 0501 and.w r5, r3, r1
+ 8002808: ea04 0602 and.w r6, r4, r2
+ 800280c: 4a3d ldr r2, [pc, #244] ; (8002904 <HAL_RCC_GetSysClockFreq+0x160>)
+ 800280e: fb02 f106 mul.w r1, r2, r6
+ 8002812: 2200 movs r2, #0
+ 8002814: fb02 f205 mul.w r2, r2, r5
+ 8002818: 440a add r2, r1
+ 800281a: 493a ldr r1, [pc, #232] ; (8002904 <HAL_RCC_GetSysClockFreq+0x160>)
+ 800281c: fba5 0101 umull r0, r1, r5, r1
+ 8002820: 1853 adds r3, r2, r1
+ 8002822: 4619 mov r1, r3
+ 8002824: 687b ldr r3, [r7, #4]
+ 8002826: f04f 0400 mov.w r4, #0
+ 800282a: 461a mov r2, r3
+ 800282c: 4623 mov r3, r4
+ 800282e: f7fd fd03 bl 8000238 <__aeabi_uldivmod>
+ 8002832: 4603 mov r3, r0
+ 8002834: 460c mov r4, r1
+ 8002836: 60fb str r3, [r7, #12]
+ 8002838: e049 b.n 80028ce <HAL_RCC_GetSysClockFreq+0x12a>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 80027be: 4b30 ldr r3, [pc, #192] ; (8002880 <HAL_RCC_GetSysClockFreq+0x158>)
- 80027c0: 685b ldr r3, [r3, #4]
- 80027c2: 099b lsrs r3, r3, #6
- 80027c4: f04f 0400 mov.w r4, #0
- 80027c8: f240 11ff movw r1, #511 ; 0x1ff
- 80027cc: f04f 0200 mov.w r2, #0
- 80027d0: ea03 0501 and.w r5, r3, r1
- 80027d4: ea04 0602 and.w r6, r4, r2
- 80027d8: 4629 mov r1, r5
- 80027da: 4632 mov r2, r6
- 80027dc: f04f 0300 mov.w r3, #0
- 80027e0: f04f 0400 mov.w r4, #0
- 80027e4: 0154 lsls r4, r2, #5
- 80027e6: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 80027ea: 014b lsls r3, r1, #5
- 80027ec: 4619 mov r1, r3
- 80027ee: 4622 mov r2, r4
- 80027f0: 1b49 subs r1, r1, r5
- 80027f2: eb62 0206 sbc.w r2, r2, r6
- 80027f6: f04f 0300 mov.w r3, #0
- 80027fa: f04f 0400 mov.w r4, #0
- 80027fe: 0194 lsls r4, r2, #6
- 8002800: ea44 6491 orr.w r4, r4, r1, lsr #26
- 8002804: 018b lsls r3, r1, #6
- 8002806: 1a5b subs r3, r3, r1
- 8002808: eb64 0402 sbc.w r4, r4, r2
- 800280c: f04f 0100 mov.w r1, #0
- 8002810: f04f 0200 mov.w r2, #0
- 8002814: 00e2 lsls r2, r4, #3
- 8002816: ea42 7253 orr.w r2, r2, r3, lsr #29
- 800281a: 00d9 lsls r1, r3, #3
- 800281c: 460b mov r3, r1
- 800281e: 4614 mov r4, r2
- 8002820: 195b adds r3, r3, r5
- 8002822: eb44 0406 adc.w r4, r4, r6
- 8002826: f04f 0100 mov.w r1, #0
- 800282a: f04f 0200 mov.w r2, #0
- 800282e: 02a2 lsls r2, r4, #10
- 8002830: ea42 5293 orr.w r2, r2, r3, lsr #22
- 8002834: 0299 lsls r1, r3, #10
- 8002836: 460b mov r3, r1
- 8002838: 4614 mov r4, r2
- 800283a: 4618 mov r0, r3
- 800283c: 4621 mov r1, r4
- 800283e: 687b ldr r3, [r7, #4]
+ 800283a: 4b30 ldr r3, [pc, #192] ; (80028fc <HAL_RCC_GetSysClockFreq+0x158>)
+ 800283c: 685b ldr r3, [r3, #4]
+ 800283e: 099b lsrs r3, r3, #6
8002840: f04f 0400 mov.w r4, #0
- 8002844: 461a mov r2, r3
- 8002846: 4623 mov r3, r4
- 8002848: f7fd fcf6 bl 8000238 <__aeabi_uldivmod>
- 800284c: 4603 mov r3, r0
- 800284e: 460c mov r4, r1
- 8002850: 60fb str r3, [r7, #12]
+ 8002844: f240 11ff movw r1, #511 ; 0x1ff
+ 8002848: f04f 0200 mov.w r2, #0
+ 800284c: ea03 0501 and.w r5, r3, r1
+ 8002850: ea04 0602 and.w r6, r4, r2
+ 8002854: 4629 mov r1, r5
+ 8002856: 4632 mov r2, r6
+ 8002858: f04f 0300 mov.w r3, #0
+ 800285c: f04f 0400 mov.w r4, #0
+ 8002860: 0154 lsls r4, r2, #5
+ 8002862: ea44 64d1 orr.w r4, r4, r1, lsr #27
+ 8002866: 014b lsls r3, r1, #5
+ 8002868: 4619 mov r1, r3
+ 800286a: 4622 mov r2, r4
+ 800286c: 1b49 subs r1, r1, r5
+ 800286e: eb62 0206 sbc.w r2, r2, r6
+ 8002872: f04f 0300 mov.w r3, #0
+ 8002876: f04f 0400 mov.w r4, #0
+ 800287a: 0194 lsls r4, r2, #6
+ 800287c: ea44 6491 orr.w r4, r4, r1, lsr #26
+ 8002880: 018b lsls r3, r1, #6
+ 8002882: 1a5b subs r3, r3, r1
+ 8002884: eb64 0402 sbc.w r4, r4, r2
+ 8002888: f04f 0100 mov.w r1, #0
+ 800288c: f04f 0200 mov.w r2, #0
+ 8002890: 00e2 lsls r2, r4, #3
+ 8002892: ea42 7253 orr.w r2, r2, r3, lsr #29
+ 8002896: 00d9 lsls r1, r3, #3
+ 8002898: 460b mov r3, r1
+ 800289a: 4614 mov r4, r2
+ 800289c: 195b adds r3, r3, r5
+ 800289e: eb44 0406 adc.w r4, r4, r6
+ 80028a2: f04f 0100 mov.w r1, #0
+ 80028a6: f04f 0200 mov.w r2, #0
+ 80028aa: 02a2 lsls r2, r4, #10
+ 80028ac: ea42 5293 orr.w r2, r2, r3, lsr #22
+ 80028b0: 0299 lsls r1, r3, #10
+ 80028b2: 460b mov r3, r1
+ 80028b4: 4614 mov r4, r2
+ 80028b6: 4618 mov r0, r3
+ 80028b8: 4621 mov r1, r4
+ 80028ba: 687b ldr r3, [r7, #4]
+ 80028bc: f04f 0400 mov.w r4, #0
+ 80028c0: 461a mov r2, r3
+ 80028c2: 4623 mov r3, r4
+ 80028c4: f7fd fcb8 bl 8000238 <__aeabi_uldivmod>
+ 80028c8: 4603 mov r3, r0
+ 80028ca: 460c mov r4, r1
+ 80028cc: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 8002852: 4b0b ldr r3, [pc, #44] ; (8002880 <HAL_RCC_GetSysClockFreq+0x158>)
- 8002854: 685b ldr r3, [r3, #4]
- 8002856: 0c1b lsrs r3, r3, #16
- 8002858: f003 0303 and.w r3, r3, #3
- 800285c: 3301 adds r3, #1
- 800285e: 005b lsls r3, r3, #1
- 8002860: 603b str r3, [r7, #0]
+ 80028ce: 4b0b ldr r3, [pc, #44] ; (80028fc <HAL_RCC_GetSysClockFreq+0x158>)
+ 80028d0: 685b ldr r3, [r3, #4]
+ 80028d2: 0c1b lsrs r3, r3, #16
+ 80028d4: f003 0303 and.w r3, r3, #3
+ 80028d8: 3301 adds r3, #1
+ 80028da: 005b lsls r3, r3, #1
+ 80028dc: 603b str r3, [r7, #0]
sysclockfreq = pllvco/pllp;
- 8002862: 68fa ldr r2, [r7, #12]
- 8002864: 683b ldr r3, [r7, #0]
- 8002866: fbb2 f3f3 udiv r3, r2, r3
- 800286a: 60bb str r3, [r7, #8]
+ 80028de: 68fa ldr r2, [r7, #12]
+ 80028e0: 683b ldr r3, [r7, #0]
+ 80028e2: fbb2 f3f3 udiv r3, r2, r3
+ 80028e6: 60bb str r3, [r7, #8]
break;
- 800286c: e002 b.n 8002874 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80028e8: e002 b.n 80028f0 <HAL_RCC_GetSysClockFreq+0x14c>
}
default:
{
sysclockfreq = HSI_VALUE;
- 800286e: 4b05 ldr r3, [pc, #20] ; (8002884 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8002870: 60bb str r3, [r7, #8]
+ 80028ea: 4b05 ldr r3, [pc, #20] ; (8002900 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 80028ec: 60bb str r3, [r7, #8]
break;
- 8002872: bf00 nop
+ 80028ee: bf00 nop
}
}
return sysclockfreq;
- 8002874: 68bb ldr r3, [r7, #8]
+ 80028f0: 68bb ldr r3, [r7, #8]
}
- 8002876: 4618 mov r0, r3
- 8002878: 3714 adds r7, #20
- 800287a: 46bd mov sp, r7
- 800287c: bdf0 pop {r4, r5, r6, r7, pc}
- 800287e: bf00 nop
- 8002880: 40023800 .word 0x40023800
- 8002884: 00f42400 .word 0x00f42400
- 8002888: 017d7840 .word 0x017d7840
-
-0800288c <HAL_RCC_GetHCLKFreq>:
+ 80028f2: 4618 mov r0, r3
+ 80028f4: 3714 adds r7, #20
+ 80028f6: 46bd mov sp, r7
+ 80028f8: bdf0 pop {r4, r5, r6, r7, pc}
+ 80028fa: bf00 nop
+ 80028fc: 40023800 .word 0x40023800
+ 8002900: 00f42400 .word 0x00f42400
+ 8002904: 017d7840 .word 0x017d7840
+
+08002908 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
- 800288c: b480 push {r7}
- 800288e: af00 add r7, sp, #0
+ 8002908: b480 push {r7}
+ 800290a: af00 add r7, sp, #0
return SystemCoreClock;
- 8002890: 4b03 ldr r3, [pc, #12] ; (80028a0 <HAL_RCC_GetHCLKFreq+0x14>)
- 8002892: 681b ldr r3, [r3, #0]
+ 800290c: 4b03 ldr r3, [pc, #12] ; (800291c <HAL_RCC_GetHCLKFreq+0x14>)
+ 800290e: 681b ldr r3, [r3, #0]
}
- 8002894: 4618 mov r0, r3
- 8002896: 46bd mov sp, r7
- 8002898: f85d 7b04 ldr.w r7, [sp], #4
- 800289c: 4770 bx lr
- 800289e: bf00 nop
- 80028a0: 20000004 .word 0x20000004
-
-080028a4 <HAL_RCC_GetPCLK1Freq>:
+ 8002910: 4618 mov r0, r3
+ 8002912: 46bd mov sp, r7
+ 8002914: f85d 7b04 ldr.w r7, [sp], #4
+ 8002918: 4770 bx lr
+ 800291a: bf00 nop
+ 800291c: 20000008 .word 0x20000008
+
+08002920 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
- 80028a4: b580 push {r7, lr}
- 80028a6: af00 add r7, sp, #0
+ 8002920: b580 push {r7, lr}
+ 8002922: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 80028a8: f7ff fff0 bl 800288c <HAL_RCC_GetHCLKFreq>
- 80028ac: 4601 mov r1, r0
- 80028ae: 4b05 ldr r3, [pc, #20] ; (80028c4 <HAL_RCC_GetPCLK1Freq+0x20>)
- 80028b0: 689b ldr r3, [r3, #8]
- 80028b2: 0a9b lsrs r3, r3, #10
- 80028b4: f003 0307 and.w r3, r3, #7
- 80028b8: 4a03 ldr r2, [pc, #12] ; (80028c8 <HAL_RCC_GetPCLK1Freq+0x24>)
- 80028ba: 5cd3 ldrb r3, [r2, r3]
- 80028bc: fa21 f303 lsr.w r3, r1, r3
+ 8002924: f7ff fff0 bl 8002908 <HAL_RCC_GetHCLKFreq>
+ 8002928: 4601 mov r1, r0
+ 800292a: 4b05 ldr r3, [pc, #20] ; (8002940 <HAL_RCC_GetPCLK1Freq+0x20>)
+ 800292c: 689b ldr r3, [r3, #8]
+ 800292e: 0a9b lsrs r3, r3, #10
+ 8002930: f003 0307 and.w r3, r3, #7
+ 8002934: 4a03 ldr r2, [pc, #12] ; (8002944 <HAL_RCC_GetPCLK1Freq+0x24>)
+ 8002936: 5cd3 ldrb r3, [r2, r3]
+ 8002938: fa21 f303 lsr.w r3, r1, r3
}
- 80028c0: 4618 mov r0, r3
- 80028c2: bd80 pop {r7, pc}
- 80028c4: 40023800 .word 0x40023800
- 80028c8: 08004fcc .word 0x08004fcc
+ 800293c: 4618 mov r0, r3
+ 800293e: bd80 pop {r7, pc}
+ 8002940: 40023800 .word 0x40023800
+ 8002944: 080052d8 .word 0x080052d8
-080028cc <HAL_RCC_GetPCLK2Freq>:
+08002948 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
- 80028cc: b580 push {r7, lr}
- 80028ce: af00 add r7, sp, #0
+ 8002948: b580 push {r7, lr}
+ 800294a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 80028d0: f7ff ffdc bl 800288c <HAL_RCC_GetHCLKFreq>
- 80028d4: 4601 mov r1, r0
- 80028d6: 4b05 ldr r3, [pc, #20] ; (80028ec <HAL_RCC_GetPCLK2Freq+0x20>)
- 80028d8: 689b ldr r3, [r3, #8]
- 80028da: 0b5b lsrs r3, r3, #13
- 80028dc: f003 0307 and.w r3, r3, #7
- 80028e0: 4a03 ldr r2, [pc, #12] ; (80028f0 <HAL_RCC_GetPCLK2Freq+0x24>)
- 80028e2: 5cd3 ldrb r3, [r2, r3]
- 80028e4: fa21 f303 lsr.w r3, r1, r3
+ 800294c: f7ff ffdc bl 8002908 <HAL_RCC_GetHCLKFreq>
+ 8002950: 4601 mov r1, r0
+ 8002952: 4b05 ldr r3, [pc, #20] ; (8002968 <HAL_RCC_GetPCLK2Freq+0x20>)
+ 8002954: 689b ldr r3, [r3, #8]
+ 8002956: 0b5b lsrs r3, r3, #13
+ 8002958: f003 0307 and.w r3, r3, #7
+ 800295c: 4a03 ldr r2, [pc, #12] ; (800296c <HAL_RCC_GetPCLK2Freq+0x24>)
+ 800295e: 5cd3 ldrb r3, [r2, r3]
+ 8002960: fa21 f303 lsr.w r3, r1, r3
}
- 80028e8: 4618 mov r0, r3
- 80028ea: bd80 pop {r7, pc}
- 80028ec: 40023800 .word 0x40023800
- 80028f0: 08004fcc .word 0x08004fcc
+ 8002964: 4618 mov r0, r3
+ 8002966: bd80 pop {r7, pc}
+ 8002968: 40023800 .word 0x40023800
+ 800296c: 080052d8 .word 0x080052d8
-080028f4 <HAL_RCCEx_PeriphCLKConfig>:
+08002970 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- 80028f4: b580 push {r7, lr}
- 80028f6: b088 sub sp, #32
- 80028f8: af00 add r7, sp, #0
- 80028fa: 6078 str r0, [r7, #4]
+ 8002970: b580 push {r7, lr}
+ 8002972: b088 sub sp, #32
+ 8002974: af00 add r7, sp, #0
+ 8002976: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
- 80028fc: 2300 movs r3, #0
- 80028fe: 617b str r3, [r7, #20]
+ 8002978: 2300 movs r3, #0
+ 800297a: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
- 8002900: 2300 movs r3, #0
- 8002902: 613b str r3, [r7, #16]
+ 800297c: 2300 movs r3, #0
+ 800297e: 613b str r3, [r7, #16]
uint32_t tmpreg1 = 0;
- 8002904: 2300 movs r3, #0
- 8002906: 60fb str r3, [r7, #12]
+ 8002980: 2300 movs r3, #0
+ 8002982: 60fb str r3, [r7, #12]
uint32_t plli2sused = 0;
- 8002908: 2300 movs r3, #0
- 800290a: 61fb str r3, [r7, #28]
+ 8002984: 2300 movs r3, #0
+ 8002986: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
- 800290c: 2300 movs r3, #0
- 800290e: 61bb str r3, [r7, #24]
+ 8002988: 2300 movs r3, #0
+ 800298a: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 8002910: 687b ldr r3, [r7, #4]
- 8002912: 681b ldr r3, [r3, #0]
- 8002914: f003 0301 and.w r3, r3, #1
- 8002918: 2b00 cmp r3, #0
- 800291a: d012 beq.n 8002942 <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ 800298c: 687b ldr r3, [r7, #4]
+ 800298e: 681b ldr r3, [r3, #0]
+ 8002990: f003 0301 and.w r3, r3, #1
+ 8002994: 2b00 cmp r3, #0
+ 8002996: d012 beq.n 80029be <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 800291c: 4b69 ldr r3, [pc, #420] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800291e: 689b ldr r3, [r3, #8]
- 8002920: 4a68 ldr r2, [pc, #416] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002922: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
- 8002926: 6093 str r3, [r2, #8]
- 8002928: 4b66 ldr r3, [pc, #408] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800292a: 689a ldr r2, [r3, #8]
- 800292c: 687b ldr r3, [r7, #4]
- 800292e: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002930: 4964 ldr r1, [pc, #400] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002932: 4313 orrs r3, r2
- 8002934: 608b str r3, [r1, #8]
+ 8002998: 4b69 ldr r3, [pc, #420] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 800299a: 689b ldr r3, [r3, #8]
+ 800299c: 4a68 ldr r2, [pc, #416] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 800299e: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
+ 80029a2: 6093 str r3, [r2, #8]
+ 80029a4: 4b66 ldr r3, [pc, #408] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80029a6: 689a ldr r2, [r3, #8]
+ 80029a8: 687b ldr r3, [r7, #4]
+ 80029aa: 6b5b ldr r3, [r3, #52] ; 0x34
+ 80029ac: 4964 ldr r1, [pc, #400] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80029ae: 4313 orrs r3, r2
+ 80029b0: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 8002936: 687b ldr r3, [r7, #4]
- 8002938: 6b5b ldr r3, [r3, #52] ; 0x34
- 800293a: 2b00 cmp r3, #0
- 800293c: d101 bne.n 8002942 <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ 80029b2: 687b ldr r3, [r7, #4]
+ 80029b4: 6b5b ldr r3, [r3, #52] ; 0x34
+ 80029b6: 2b00 cmp r3, #0
+ 80029b8: d101 bne.n 80029be <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
plli2sused = 1;
- 800293e: 2301 movs r3, #1
- 8002940: 61fb str r3, [r7, #28]
+ 80029ba: 2301 movs r3, #1
+ 80029bc: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 8002942: 687b ldr r3, [r7, #4]
- 8002944: 681b ldr r3, [r3, #0]
- 8002946: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 800294a: 2b00 cmp r3, #0
- 800294c: d017 beq.n 800297e <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ 80029be: 687b ldr r3, [r7, #4]
+ 80029c0: 681b ldr r3, [r3, #0]
+ 80029c2: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 80029c6: 2b00 cmp r3, #0
+ 80029c8: d017 beq.n 80029fa <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 800294e: 4b5d ldr r3, [pc, #372] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002950: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002954: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002958: 687b ldr r3, [r7, #4]
- 800295a: 6bdb ldr r3, [r3, #60] ; 0x3c
- 800295c: 4959 ldr r1, [pc, #356] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800295e: 4313 orrs r3, r2
- 8002960: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 80029ca: 4b5d ldr r3, [pc, #372] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80029cc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 80029d0: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
+ 80029d4: 687b ldr r3, [r7, #4]
+ 80029d6: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 80029d8: 4959 ldr r1, [pc, #356] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80029da: 4313 orrs r3, r2
+ 80029dc: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8002964: 687b ldr r3, [r7, #4]
- 8002966: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002968: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 800296c: d101 bne.n 8002972 <HAL_RCCEx_PeriphCLKConfig+0x7e>
+ 80029e0: 687b ldr r3, [r7, #4]
+ 80029e2: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 80029e4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 80029e8: d101 bne.n 80029ee <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
plli2sused = 1;
- 800296e: 2301 movs r3, #1
- 8002970: 61fb str r3, [r7, #28]
+ 80029ea: 2301 movs r3, #1
+ 80029ec: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 8002972: 687b ldr r3, [r7, #4]
- 8002974: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002976: 2b00 cmp r3, #0
- 8002978: d101 bne.n 800297e <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ 80029ee: 687b ldr r3, [r7, #4]
+ 80029f0: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 80029f2: 2b00 cmp r3, #0
+ 80029f4: d101 bne.n 80029fa <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
pllsaiused = 1;
- 800297a: 2301 movs r3, #1
- 800297c: 61bb str r3, [r7, #24]
+ 80029f6: 2301 movs r3, #1
+ 80029f8: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 800297e: 687b ldr r3, [r7, #4]
- 8002980: 681b ldr r3, [r3, #0]
- 8002982: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8002986: 2b00 cmp r3, #0
- 8002988: d017 beq.n 80029ba <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ 80029fa: 687b ldr r3, [r7, #4]
+ 80029fc: 681b ldr r3, [r3, #0]
+ 80029fe: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8002a02: 2b00 cmp r3, #0
+ 8002a04: d017 beq.n 8002a36 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 800298a: 4b4e ldr r3, [pc, #312] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800298c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002990: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002994: 687b ldr r3, [r7, #4]
- 8002996: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002998: 494a ldr r1, [pc, #296] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800299a: 4313 orrs r3, r2
- 800299c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8002a06: 4b4e ldr r3, [pc, #312] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002a08: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8002a0c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
+ 8002a10: 687b ldr r3, [r7, #4]
+ 8002a12: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002a14: 494a ldr r1, [pc, #296] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002a16: 4313 orrs r3, r2
+ 8002a18: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 80029a0: 687b ldr r3, [r7, #4]
- 80029a2: 6c1b ldr r3, [r3, #64] ; 0x40
- 80029a4: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 80029a8: d101 bne.n 80029ae <HAL_RCCEx_PeriphCLKConfig+0xba>
+ 8002a1c: 687b ldr r3, [r7, #4]
+ 8002a1e: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002a20: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8002a24: d101 bne.n 8002a2a <HAL_RCCEx_PeriphCLKConfig+0xba>
{
plli2sused = 1;
- 80029aa: 2301 movs r3, #1
- 80029ac: 61fb str r3, [r7, #28]
+ 8002a26: 2301 movs r3, #1
+ 8002a28: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 80029ae: 687b ldr r3, [r7, #4]
- 80029b0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80029b2: 2b00 cmp r3, #0
- 80029b4: d101 bne.n 80029ba <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ 8002a2a: 687b ldr r3, [r7, #4]
+ 8002a2c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002a2e: 2b00 cmp r3, #0
+ 8002a30: d101 bne.n 8002a36 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
pllsaiused = 1;
- 80029b6: 2301 movs r3, #1
- 80029b8: 61bb str r3, [r7, #24]
+ 8002a32: 2301 movs r3, #1
+ 8002a34: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 80029ba: 687b ldr r3, [r7, #4]
- 80029bc: 681b ldr r3, [r3, #0]
- 80029be: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 80029c2: 2b00 cmp r3, #0
- 80029c4: d001 beq.n 80029ca <HAL_RCCEx_PeriphCLKConfig+0xd6>
+ 8002a36: 687b ldr r3, [r7, #4]
+ 8002a38: 681b ldr r3, [r3, #0]
+ 8002a3a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
+ 8002a3e: 2b00 cmp r3, #0
+ 8002a40: d001 beq.n 8002a46 <HAL_RCCEx_PeriphCLKConfig+0xd6>
{
plli2sused = 1;
- 80029c6: 2301 movs r3, #1
- 80029c8: 61fb str r3, [r7, #28]
+ 8002a42: 2301 movs r3, #1
+ 8002a44: 61fb str r3, [r7, #28]
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 80029ca: 687b ldr r3, [r7, #4]
- 80029cc: 681b ldr r3, [r3, #0]
- 80029ce: f003 0320 and.w r3, r3, #32
- 80029d2: 2b00 cmp r3, #0
- 80029d4: f000 808b beq.w 8002aee <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ 8002a46: 687b ldr r3, [r7, #4]
+ 8002a48: 681b ldr r3, [r3, #0]
+ 8002a4a: f003 0320 and.w r3, r3, #32
+ 8002a4e: 2b00 cmp r3, #0
+ 8002a50: f000 808b beq.w 8002b6a <HAL_RCCEx_PeriphCLKConfig+0x1fa>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
- 80029d8: 4b3a ldr r3, [pc, #232] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80029da: 6c1b ldr r3, [r3, #64] ; 0x40
- 80029dc: 4a39 ldr r2, [pc, #228] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80029de: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80029e2: 6413 str r3, [r2, #64] ; 0x40
- 80029e4: 4b37 ldr r3, [pc, #220] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80029e6: 6c1b ldr r3, [r3, #64] ; 0x40
- 80029e8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80029ec: 60bb str r3, [r7, #8]
- 80029ee: 68bb ldr r3, [r7, #8]
+ 8002a54: 4b3a ldr r3, [pc, #232] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002a56: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002a58: 4a39 ldr r2, [pc, #228] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002a5a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8002a5e: 6413 str r3, [r2, #64] ; 0x40
+ 8002a60: 4b37 ldr r3, [pc, #220] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002a62: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002a64: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8002a68: 60bb str r3, [r7, #8]
+ 8002a6a: 68bb ldr r3, [r7, #8]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
- 80029f0: 4b35 ldr r3, [pc, #212] ; (8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 80029f2: 681b ldr r3, [r3, #0]
- 80029f4: 4a34 ldr r2, [pc, #208] ; (8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 80029f6: f443 7380 orr.w r3, r3, #256 ; 0x100
- 80029fa: 6013 str r3, [r2, #0]
+ 8002a6c: 4b35 ldr r3, [pc, #212] ; (8002b44 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8002a6e: 681b ldr r3, [r3, #0]
+ 8002a70: 4a34 ldr r2, [pc, #208] ; (8002b44 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8002a72: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 8002a76: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80029fc: f7ff f81e bl 8001a3c <HAL_GetTick>
- 8002a00: 6178 str r0, [r7, #20]
+ 8002a78: f7ff f81e bl 8001ab8 <HAL_GetTick>
+ 8002a7c: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002a02: e008 b.n 8002a16 <HAL_RCCEx_PeriphCLKConfig+0x122>
+ 8002a7e: e008 b.n 8002a92 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8002a04: f7ff f81a bl 8001a3c <HAL_GetTick>
- 8002a08: 4602 mov r2, r0
- 8002a0a: 697b ldr r3, [r7, #20]
- 8002a0c: 1ad3 subs r3, r2, r3
- 8002a0e: 2b64 cmp r3, #100 ; 0x64
- 8002a10: d901 bls.n 8002a16 <HAL_RCCEx_PeriphCLKConfig+0x122>
+ 8002a80: f7ff f81a bl 8001ab8 <HAL_GetTick>
+ 8002a84: 4602 mov r2, r0
+ 8002a86: 697b ldr r3, [r7, #20]
+ 8002a88: 1ad3 subs r3, r2, r3
+ 8002a8a: 2b64 cmp r3, #100 ; 0x64
+ 8002a8c: d901 bls.n 8002a92 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
return HAL_TIMEOUT;
- 8002a12: 2303 movs r3, #3
- 8002a14: e38d b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8002a8e: 2303 movs r3, #3
+ 8002a90: e38d b.n 80031ae <HAL_RCCEx_PeriphCLKConfig+0x83e>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8002a16: 4b2c ldr r3, [pc, #176] ; (8002ac8 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8002a18: 681b ldr r3, [r3, #0]
- 8002a1a: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002a1e: 2b00 cmp r3, #0
- 8002a20: d0f0 beq.n 8002a04 <HAL_RCCEx_PeriphCLKConfig+0x110>
+ 8002a92: 4b2c ldr r3, [pc, #176] ; (8002b44 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8002a94: 681b ldr r3, [r3, #0]
+ 8002a96: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8002a9a: 2b00 cmp r3, #0
+ 8002a9c: d0f0 beq.n 8002a80 <HAL_RCCEx_PeriphCLKConfig+0x110>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8002a22: 4b28 ldr r3, [pc, #160] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a24: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002a26: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002a2a: 613b str r3, [r7, #16]
+ 8002a9e: 4b28 ldr r3, [pc, #160] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002aa0: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002aa2: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8002aa6: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8002a2c: 693b ldr r3, [r7, #16]
- 8002a2e: 2b00 cmp r3, #0
- 8002a30: d035 beq.n 8002a9e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8002a32: 687b ldr r3, [r7, #4]
- 8002a34: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002a36: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002a3a: 693a ldr r2, [r7, #16]
- 8002a3c: 429a cmp r2, r3
- 8002a3e: d02e beq.n 8002a9e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8002aa8: 693b ldr r3, [r7, #16]
+ 8002aaa: 2b00 cmp r3, #0
+ 8002aac: d035 beq.n 8002b1a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8002aae: 687b ldr r3, [r7, #4]
+ 8002ab0: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8002ab2: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8002ab6: 693a ldr r2, [r7, #16]
+ 8002ab8: 429a cmp r2, r3
+ 8002aba: d02e beq.n 8002b1a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8002a40: 4b20 ldr r3, [pc, #128] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a42: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002a44: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8002a48: 613b str r3, [r7, #16]
+ 8002abc: 4b20 ldr r3, [pc, #128] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002abe: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002ac0: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8002ac4: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
- 8002a4a: 4b1e ldr r3, [pc, #120] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a4c: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002a4e: 4a1d ldr r2, [pc, #116] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a50: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8002a54: 6713 str r3, [r2, #112] ; 0x70
+ 8002ac6: 4b1e ldr r3, [pc, #120] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002ac8: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002aca: 4a1d ldr r2, [pc, #116] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002acc: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8002ad0: 6713 str r3, [r2, #112] ; 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
- 8002a56: 4b1b ldr r3, [pc, #108] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a58: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002a5a: 4a1a ldr r2, [pc, #104] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a5c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8002a60: 6713 str r3, [r2, #112] ; 0x70
+ 8002ad2: 4b1b ldr r3, [pc, #108] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002ad4: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002ad6: 4a1a ldr r2, [pc, #104] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002ad8: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8002adc: 6713 str r3, [r2, #112] ; 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
- 8002a62: 4a18 ldr r2, [pc, #96] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a64: 693b ldr r3, [r7, #16]
- 8002a66: 6713 str r3, [r2, #112] ; 0x70
+ 8002ade: 4a18 ldr r2, [pc, #96] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002ae0: 693b ldr r3, [r7, #16]
+ 8002ae2: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8002a68: 4b16 ldr r3, [pc, #88] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a6a: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002a6c: f003 0301 and.w r3, r3, #1
- 8002a70: 2b01 cmp r3, #1
- 8002a72: d114 bne.n 8002a9e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8002ae4: 4b16 ldr r3, [pc, #88] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002ae6: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002ae8: f003 0301 and.w r3, r3, #1
+ 8002aec: 2b01 cmp r3, #1
+ 8002aee: d114 bne.n 8002b1a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002a74: f7fe ffe2 bl 8001a3c <HAL_GetTick>
- 8002a78: 6178 str r0, [r7, #20]
+ 8002af0: f7fe ffe2 bl 8001ab8 <HAL_GetTick>
+ 8002af4: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002a7a: e00a b.n 8002a92 <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ 8002af6: e00a b.n 8002b0e <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002a7c: f7fe ffde bl 8001a3c <HAL_GetTick>
- 8002a80: 4602 mov r2, r0
- 8002a82: 697b ldr r3, [r7, #20]
- 8002a84: 1ad3 subs r3, r2, r3
- 8002a86: f241 3288 movw r2, #5000 ; 0x1388
- 8002a8a: 4293 cmp r3, r2
- 8002a8c: d901 bls.n 8002a92 <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ 8002af8: f7fe ffde bl 8001ab8 <HAL_GetTick>
+ 8002afc: 4602 mov r2, r0
+ 8002afe: 697b ldr r3, [r7, #20]
+ 8002b00: 1ad3 subs r3, r2, r3
+ 8002b02: f241 3288 movw r2, #5000 ; 0x1388
+ 8002b06: 4293 cmp r3, r2
+ 8002b08: d901 bls.n 8002b0e <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
return HAL_TIMEOUT;
- 8002a8e: 2303 movs r3, #3
- 8002a90: e34f b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8002b0a: 2303 movs r3, #3
+ 8002b0c: e34f b.n 80031ae <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8002a92: 4b0c ldr r3, [pc, #48] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002a94: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002a96: f003 0302 and.w r3, r3, #2
- 8002a9a: 2b00 cmp r3, #0
- 8002a9c: d0ee beq.n 8002a7c <HAL_RCCEx_PeriphCLKConfig+0x188>
+ 8002b0e: 4b0c ldr r3, [pc, #48] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002b10: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002b12: f003 0302 and.w r3, r3, #2
+ 8002b16: 2b00 cmp r3, #0
+ 8002b18: d0ee beq.n 8002af8 <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8002a9e: 687b ldr r3, [r7, #4]
- 8002aa0: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002aa2: f403 7340 and.w r3, r3, #768 ; 0x300
- 8002aa6: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8002aaa: d111 bne.n 8002ad0 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8002aac: 4b05 ldr r3, [pc, #20] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002aae: 689b ldr r3, [r3, #8]
- 8002ab0: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
- 8002ab4: 687b ldr r3, [r7, #4]
- 8002ab6: 6b19 ldr r1, [r3, #48] ; 0x30
- 8002ab8: 4b04 ldr r3, [pc, #16] ; (8002acc <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8002aba: 400b ands r3, r1
- 8002abc: 4901 ldr r1, [pc, #4] ; (8002ac4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8002abe: 4313 orrs r3, r2
- 8002ac0: 608b str r3, [r1, #8]
- 8002ac2: e00b b.n 8002adc <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8002ac4: 40023800 .word 0x40023800
- 8002ac8: 40007000 .word 0x40007000
- 8002acc: 0ffffcff .word 0x0ffffcff
- 8002ad0: 4bb3 ldr r3, [pc, #716] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ad2: 689b ldr r3, [r3, #8]
- 8002ad4: 4ab2 ldr r2, [pc, #712] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ad6: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
- 8002ada: 6093 str r3, [r2, #8]
- 8002adc: 4bb0 ldr r3, [pc, #704] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ade: 6f1a ldr r2, [r3, #112] ; 0x70
- 8002ae0: 687b ldr r3, [r7, #4]
- 8002ae2: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002ae4: f3c3 030b ubfx r3, r3, #0, #12
- 8002ae8: 49ad ldr r1, [pc, #692] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002aea: 4313 orrs r3, r2
- 8002aec: 670b str r3, [r1, #112] ; 0x70
+ 8002b1a: 687b ldr r3, [r7, #4]
+ 8002b1c: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8002b1e: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8002b22: f5b3 7f40 cmp.w r3, #768 ; 0x300
+ 8002b26: d111 bne.n 8002b4c <HAL_RCCEx_PeriphCLKConfig+0x1dc>
+ 8002b28: 4b05 ldr r3, [pc, #20] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002b2a: 689b ldr r3, [r3, #8]
+ 8002b2c: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
+ 8002b30: 687b ldr r3, [r7, #4]
+ 8002b32: 6b19 ldr r1, [r3, #48] ; 0x30
+ 8002b34: 4b04 ldr r3, [pc, #16] ; (8002b48 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
+ 8002b36: 400b ands r3, r1
+ 8002b38: 4901 ldr r1, [pc, #4] ; (8002b40 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8002b3a: 4313 orrs r3, r2
+ 8002b3c: 608b str r3, [r1, #8]
+ 8002b3e: e00b b.n 8002b58 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
+ 8002b40: 40023800 .word 0x40023800
+ 8002b44: 40007000 .word 0x40007000
+ 8002b48: 0ffffcff .word 0x0ffffcff
+ 8002b4c: 4bb3 ldr r3, [pc, #716] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b4e: 689b ldr r3, [r3, #8]
+ 8002b50: 4ab2 ldr r2, [pc, #712] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b52: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
+ 8002b56: 6093 str r3, [r2, #8]
+ 8002b58: 4bb0 ldr r3, [pc, #704] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b5a: 6f1a ldr r2, [r3, #112] ; 0x70
+ 8002b5c: 687b ldr r3, [r7, #4]
+ 8002b5e: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8002b60: f3c3 030b ubfx r3, r3, #0, #12
+ 8002b64: 49ad ldr r1, [pc, #692] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b66: 4313 orrs r3, r2
+ 8002b68: 670b str r3, [r1, #112] ; 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 8002aee: 687b ldr r3, [r7, #4]
- 8002af0: 681b ldr r3, [r3, #0]
- 8002af2: f003 0310 and.w r3, r3, #16
- 8002af6: 2b00 cmp r3, #0
- 8002af8: d010 beq.n 8002b1c <HAL_RCCEx_PeriphCLKConfig+0x228>
+ 8002b6a: 687b ldr r3, [r7, #4]
+ 8002b6c: 681b ldr r3, [r3, #0]
+ 8002b6e: f003 0310 and.w r3, r3, #16
+ 8002b72: 2b00 cmp r3, #0
+ 8002b74: d010 beq.n 8002b98 <HAL_RCCEx_PeriphCLKConfig+0x228>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 8002afa: 4ba9 ldr r3, [pc, #676] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002afc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002b00: 4aa7 ldr r2, [pc, #668] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b02: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8002b06: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 8002b0a: 4ba5 ldr r3, [pc, #660] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b0c: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
- 8002b10: 687b ldr r3, [r7, #4]
- 8002b12: 6b9b ldr r3, [r3, #56] ; 0x38
- 8002b14: 49a2 ldr r1, [pc, #648] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b16: 4313 orrs r3, r2
- 8002b18: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8002b76: 4ba9 ldr r3, [pc, #676] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b78: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8002b7c: 4aa7 ldr r2, [pc, #668] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b7e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8002b82: f8c2 308c str.w r3, [r2, #140] ; 0x8c
+ 8002b86: 4ba5 ldr r3, [pc, #660] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b88: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
+ 8002b8c: 687b ldr r3, [r7, #4]
+ 8002b8e: 6b9b ldr r3, [r3, #56] ; 0x38
+ 8002b90: 49a2 ldr r1, [pc, #648] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002b92: 4313 orrs r3, r2
+ 8002b94: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 8002b1c: 687b ldr r3, [r7, #4]
- 8002b1e: 681b ldr r3, [r3, #0]
- 8002b20: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8002b24: 2b00 cmp r3, #0
- 8002b26: d00a beq.n 8002b3e <HAL_RCCEx_PeriphCLKConfig+0x24a>
+ 8002b98: 687b ldr r3, [r7, #4]
+ 8002b9a: 681b ldr r3, [r3, #0]
+ 8002b9c: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8002ba0: 2b00 cmp r3, #0
+ 8002ba2: d00a beq.n 8002bba <HAL_RCCEx_PeriphCLKConfig+0x24a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8002b28: 4b9d ldr r3, [pc, #628] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b2a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002b2e: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8002b32: 687b ldr r3, [r7, #4]
- 8002b34: 6e5b ldr r3, [r3, #100] ; 0x64
- 8002b36: 499a ldr r1, [pc, #616] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b38: 4313 orrs r3, r2
- 8002b3a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002ba4: 4b9d ldr r3, [pc, #628] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002ba6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002baa: f423 3240 bic.w r2, r3, #196608 ; 0x30000
+ 8002bae: 687b ldr r3, [r7, #4]
+ 8002bb0: 6e5b ldr r3, [r3, #100] ; 0x64
+ 8002bb2: 499a ldr r1, [pc, #616] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002bb4: 4313 orrs r3, r2
+ 8002bb6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 8002b3e: 687b ldr r3, [r7, #4]
- 8002b40: 681b ldr r3, [r3, #0]
- 8002b42: f403 4300 and.w r3, r3, #32768 ; 0x8000
- 8002b46: 2b00 cmp r3, #0
- 8002b48: d00a beq.n 8002b60 <HAL_RCCEx_PeriphCLKConfig+0x26c>
+ 8002bba: 687b ldr r3, [r7, #4]
+ 8002bbc: 681b ldr r3, [r3, #0]
+ 8002bbe: f403 4300 and.w r3, r3, #32768 ; 0x8000
+ 8002bc2: 2b00 cmp r3, #0
+ 8002bc4: d00a beq.n 8002bdc <HAL_RCCEx_PeriphCLKConfig+0x26c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8002b4a: 4b95 ldr r3, [pc, #596] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b4c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002b50: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
- 8002b54: 687b ldr r3, [r7, #4]
- 8002b56: 6e9b ldr r3, [r3, #104] ; 0x68
- 8002b58: 4991 ldr r1, [pc, #580] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b5a: 4313 orrs r3, r2
- 8002b5c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002bc6: 4b95 ldr r3, [pc, #596] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002bc8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002bcc: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
+ 8002bd0: 687b ldr r3, [r7, #4]
+ 8002bd2: 6e9b ldr r3, [r3, #104] ; 0x68
+ 8002bd4: 4991 ldr r1, [pc, #580] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002bd6: 4313 orrs r3, r2
+ 8002bd8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8002b60: 687b ldr r3, [r7, #4]
- 8002b62: 681b ldr r3, [r3, #0]
- 8002b64: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8002b68: 2b00 cmp r3, #0
- 8002b6a: d00a beq.n 8002b82 <HAL_RCCEx_PeriphCLKConfig+0x28e>
+ 8002bdc: 687b ldr r3, [r7, #4]
+ 8002bde: 681b ldr r3, [r3, #0]
+ 8002be0: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8002be4: 2b00 cmp r3, #0
+ 8002be6: d00a beq.n 8002bfe <HAL_RCCEx_PeriphCLKConfig+0x28e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8002b6c: 4b8c ldr r3, [pc, #560] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b6e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002b72: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8002b76: 687b ldr r3, [r7, #4]
- 8002b78: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002b7a: 4989 ldr r1, [pc, #548] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b7c: 4313 orrs r3, r2
- 8002b7e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002be8: 4b8c ldr r3, [pc, #560] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002bea: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002bee: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
+ 8002bf2: 687b ldr r3, [r7, #4]
+ 8002bf4: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8002bf6: 4989 ldr r1, [pc, #548] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002bf8: 4313 orrs r3, r2
+ 8002bfa: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8002b82: 687b ldr r3, [r7, #4]
- 8002b84: 681b ldr r3, [r3, #0]
- 8002b86: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8002b8a: 2b00 cmp r3, #0
- 8002b8c: d00a beq.n 8002ba4 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
+ 8002bfe: 687b ldr r3, [r7, #4]
+ 8002c00: 681b ldr r3, [r3, #0]
+ 8002c02: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8002c06: 2b00 cmp r3, #0
+ 8002c08: d00a beq.n 8002c20 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8002b8e: 4b84 ldr r3, [pc, #528] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b90: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002b94: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8002b98: 687b ldr r3, [r7, #4]
- 8002b9a: 6f1b ldr r3, [r3, #112] ; 0x70
- 8002b9c: 4980 ldr r1, [pc, #512] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002b9e: 4313 orrs r3, r2
- 8002ba0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002c0a: 4b84 ldr r3, [pc, #528] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002c10: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
+ 8002c14: 687b ldr r3, [r7, #4]
+ 8002c16: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8002c18: 4980 ldr r1, [pc, #512] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c1a: 4313 orrs r3, r2
+ 8002c1c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8002ba4: 687b ldr r3, [r7, #4]
- 8002ba6: 681b ldr r3, [r3, #0]
- 8002ba8: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002bac: 2b00 cmp r3, #0
- 8002bae: d00a beq.n 8002bc6 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ 8002c20: 687b ldr r3, [r7, #4]
+ 8002c22: 681b ldr r3, [r3, #0]
+ 8002c24: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8002c28: 2b00 cmp r3, #0
+ 8002c2a: d00a beq.n 8002c42 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8002bb0: 4b7b ldr r3, [pc, #492] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002bb2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002bb6: f023 0203 bic.w r2, r3, #3
- 8002bba: 687b ldr r3, [r7, #4]
- 8002bbc: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002bbe: 4978 ldr r1, [pc, #480] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002bc0: 4313 orrs r3, r2
- 8002bc2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002c2c: 4b7b ldr r3, [pc, #492] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c2e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002c32: f023 0203 bic.w r2, r3, #3
+ 8002c36: 687b ldr r3, [r7, #4]
+ 8002c38: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8002c3a: 4978 ldr r1, [pc, #480] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c3c: 4313 orrs r3, r2
+ 8002c3e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8002bc6: 687b ldr r3, [r7, #4]
- 8002bc8: 681b ldr r3, [r3, #0]
- 8002bca: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002bce: 2b00 cmp r3, #0
- 8002bd0: d00a beq.n 8002be8 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
+ 8002c42: 687b ldr r3, [r7, #4]
+ 8002c44: 681b ldr r3, [r3, #0]
+ 8002c46: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8002c4a: 2b00 cmp r3, #0
+ 8002c4c: d00a beq.n 8002c64 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8002bd2: 4b73 ldr r3, [pc, #460] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002bd4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002bd8: f023 020c bic.w r2, r3, #12
- 8002bdc: 687b ldr r3, [r7, #4]
- 8002bde: 6c9b ldr r3, [r3, #72] ; 0x48
- 8002be0: 496f ldr r1, [pc, #444] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002be2: 4313 orrs r3, r2
- 8002be4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002c4e: 4b73 ldr r3, [pc, #460] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c50: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002c54: f023 020c bic.w r2, r3, #12
+ 8002c58: 687b ldr r3, [r7, #4]
+ 8002c5a: 6c9b ldr r3, [r3, #72] ; 0x48
+ 8002c5c: 496f ldr r1, [pc, #444] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c5e: 4313 orrs r3, r2
+ 8002c60: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8002be8: 687b ldr r3, [r7, #4]
- 8002bea: 681b ldr r3, [r3, #0]
- 8002bec: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002bf0: 2b00 cmp r3, #0
- 8002bf2: d00a beq.n 8002c0a <HAL_RCCEx_PeriphCLKConfig+0x316>
+ 8002c64: 687b ldr r3, [r7, #4]
+ 8002c66: 681b ldr r3, [r3, #0]
+ 8002c68: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8002c6c: 2b00 cmp r3, #0
+ 8002c6e: d00a beq.n 8002c86 <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8002bf4: 4b6a ldr r3, [pc, #424] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002bf6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002bfa: f023 0230 bic.w r2, r3, #48 ; 0x30
- 8002bfe: 687b ldr r3, [r7, #4]
- 8002c00: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8002c02: 4967 ldr r1, [pc, #412] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c04: 4313 orrs r3, r2
- 8002c06: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002c70: 4b6a ldr r3, [pc, #424] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c72: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002c76: f023 0230 bic.w r2, r3, #48 ; 0x30
+ 8002c7a: 687b ldr r3, [r7, #4]
+ 8002c7c: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 8002c7e: 4967 ldr r1, [pc, #412] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c80: 4313 orrs r3, r2
+ 8002c82: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8002c0a: 687b ldr r3, [r7, #4]
- 8002c0c: 681b ldr r3, [r3, #0]
- 8002c0e: f403 7300 and.w r3, r3, #512 ; 0x200
- 8002c12: 2b00 cmp r3, #0
- 8002c14: d00a beq.n 8002c2c <HAL_RCCEx_PeriphCLKConfig+0x338>
+ 8002c86: 687b ldr r3, [r7, #4]
+ 8002c88: 681b ldr r3, [r3, #0]
+ 8002c8a: f403 7300 and.w r3, r3, #512 ; 0x200
+ 8002c8e: 2b00 cmp r3, #0
+ 8002c90: d00a beq.n 8002ca8 <HAL_RCCEx_PeriphCLKConfig+0x338>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8002c16: 4b62 ldr r3, [pc, #392] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c18: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002c1c: f023 02c0 bic.w r2, r3, #192 ; 0xc0
- 8002c20: 687b ldr r3, [r7, #4]
- 8002c22: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002c24: 495e ldr r1, [pc, #376] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c26: 4313 orrs r3, r2
- 8002c28: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002c92: 4b62 ldr r3, [pc, #392] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002c94: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002c98: f023 02c0 bic.w r2, r3, #192 ; 0xc0
+ 8002c9c: 687b ldr r3, [r7, #4]
+ 8002c9e: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8002ca0: 495e ldr r1, [pc, #376] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002ca2: 4313 orrs r3, r2
+ 8002ca4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8002c2c: 687b ldr r3, [r7, #4]
- 8002c2e: 681b ldr r3, [r3, #0]
- 8002c30: f403 6380 and.w r3, r3, #1024 ; 0x400
- 8002c34: 2b00 cmp r3, #0
- 8002c36: d00a beq.n 8002c4e <HAL_RCCEx_PeriphCLKConfig+0x35a>
+ 8002ca8: 687b ldr r3, [r7, #4]
+ 8002caa: 681b ldr r3, [r3, #0]
+ 8002cac: f403 6380 and.w r3, r3, #1024 ; 0x400
+ 8002cb0: 2b00 cmp r3, #0
+ 8002cb2: d00a beq.n 8002cca <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8002c38: 4b59 ldr r3, [pc, #356] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c3a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002c3e: f423 7240 bic.w r2, r3, #768 ; 0x300
- 8002c42: 687b ldr r3, [r7, #4]
- 8002c44: 6d5b ldr r3, [r3, #84] ; 0x54
- 8002c46: 4956 ldr r1, [pc, #344] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c48: 4313 orrs r3, r2
- 8002c4a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002cb4: 4b59 ldr r3, [pc, #356] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002cb6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002cba: f423 7240 bic.w r2, r3, #768 ; 0x300
+ 8002cbe: 687b ldr r3, [r7, #4]
+ 8002cc0: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8002cc2: 4956 ldr r1, [pc, #344] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002cc4: 4313 orrs r3, r2
+ 8002cc6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8002c4e: 687b ldr r3, [r7, #4]
- 8002c50: 681b ldr r3, [r3, #0]
- 8002c52: f403 6300 and.w r3, r3, #2048 ; 0x800
- 8002c56: 2b00 cmp r3, #0
- 8002c58: d00a beq.n 8002c70 <HAL_RCCEx_PeriphCLKConfig+0x37c>
+ 8002cca: 687b ldr r3, [r7, #4]
+ 8002ccc: 681b ldr r3, [r3, #0]
+ 8002cce: f403 6300 and.w r3, r3, #2048 ; 0x800
+ 8002cd2: 2b00 cmp r3, #0
+ 8002cd4: d00a beq.n 8002cec <HAL_RCCEx_PeriphCLKConfig+0x37c>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8002c5a: 4b51 ldr r3, [pc, #324] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c5c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002c60: f423 6240 bic.w r2, r3, #3072 ; 0xc00
- 8002c64: 687b ldr r3, [r7, #4]
- 8002c66: 6d9b ldr r3, [r3, #88] ; 0x58
- 8002c68: 494d ldr r1, [pc, #308] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c6a: 4313 orrs r3, r2
- 8002c6c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002cd6: 4b51 ldr r3, [pc, #324] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002cd8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002cdc: f423 6240 bic.w r2, r3, #3072 ; 0xc00
+ 8002ce0: 687b ldr r3, [r7, #4]
+ 8002ce2: 6d9b ldr r3, [r3, #88] ; 0x58
+ 8002ce4: 494d ldr r1, [pc, #308] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002ce6: 4313 orrs r3, r2
+ 8002ce8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8002c70: 687b ldr r3, [r7, #4]
- 8002c72: 681b ldr r3, [r3, #0]
- 8002c74: f403 5380 and.w r3, r3, #4096 ; 0x1000
- 8002c78: 2b00 cmp r3, #0
- 8002c7a: d00a beq.n 8002c92 <HAL_RCCEx_PeriphCLKConfig+0x39e>
+ 8002cec: 687b ldr r3, [r7, #4]
+ 8002cee: 681b ldr r3, [r3, #0]
+ 8002cf0: f403 5380 and.w r3, r3, #4096 ; 0x1000
+ 8002cf4: 2b00 cmp r3, #0
+ 8002cf6: d00a beq.n 8002d0e <HAL_RCCEx_PeriphCLKConfig+0x39e>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8002c7c: 4b48 ldr r3, [pc, #288] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c7e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002c82: f423 5240 bic.w r2, r3, #12288 ; 0x3000
- 8002c86: 687b ldr r3, [r7, #4]
- 8002c88: 6ddb ldr r3, [r3, #92] ; 0x5c
- 8002c8a: 4945 ldr r1, [pc, #276] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002c8c: 4313 orrs r3, r2
- 8002c8e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002cf8: 4b48 ldr r3, [pc, #288] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002cfa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002cfe: f423 5240 bic.w r2, r3, #12288 ; 0x3000
+ 8002d02: 687b ldr r3, [r7, #4]
+ 8002d04: 6ddb ldr r3, [r3, #92] ; 0x5c
+ 8002d06: 4945 ldr r1, [pc, #276] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002d08: 4313 orrs r3, r2
+ 8002d0a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 8002c92: 687b ldr r3, [r7, #4]
- 8002c94: 681b ldr r3, [r3, #0]
- 8002c96: f403 5300 and.w r3, r3, #8192 ; 0x2000
- 8002c9a: 2b00 cmp r3, #0
- 8002c9c: d00a beq.n 8002cb4 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
+ 8002d0e: 687b ldr r3, [r7, #4]
+ 8002d10: 681b ldr r3, [r3, #0]
+ 8002d12: f403 5300 and.w r3, r3, #8192 ; 0x2000
+ 8002d16: 2b00 cmp r3, #0
+ 8002d18: d00a beq.n 8002d30 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 8002c9e: 4b40 ldr r3, [pc, #256] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ca0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ca4: f423 4240 bic.w r2, r3, #49152 ; 0xc000
- 8002ca8: 687b ldr r3, [r7, #4]
- 8002caa: 6e1b ldr r3, [r3, #96] ; 0x60
- 8002cac: 493c ldr r1, [pc, #240] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cae: 4313 orrs r3, r2
- 8002cb0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002d1a: 4b40 ldr r3, [pc, #256] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002d1c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002d20: f423 4240 bic.w r2, r3, #49152 ; 0xc000
+ 8002d24: 687b ldr r3, [r7, #4]
+ 8002d26: 6e1b ldr r3, [r3, #96] ; 0x60
+ 8002d28: 493c ldr r1, [pc, #240] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002d2a: 4313 orrs r3, r2
+ 8002d2c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*--------------------------------------- CEC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 8002cb4: 687b ldr r3, [r7, #4]
- 8002cb6: 681b ldr r3, [r3, #0]
- 8002cb8: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8002cbc: 2b00 cmp r3, #0
- 8002cbe: d00a beq.n 8002cd6 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
+ 8002d30: 687b ldr r3, [r7, #4]
+ 8002d32: 681b ldr r3, [r3, #0]
+ 8002d34: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8002d38: 2b00 cmp r3, #0
+ 8002d3a: d00a beq.n 8002d52 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 8002cc0: 4b37 ldr r3, [pc, #220] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cc2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002cc6: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8002cca: 687b ldr r3, [r7, #4]
- 8002ccc: 6f9b ldr r3, [r3, #120] ; 0x78
- 8002cce: 4934 ldr r1, [pc, #208] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cd0: 4313 orrs r3, r2
- 8002cd2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002d3c: 4b37 ldr r3, [pc, #220] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002d3e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002d42: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
+ 8002d46: 687b ldr r3, [r7, #4]
+ 8002d48: 6f9b ldr r3, [r3, #120] ; 0x78
+ 8002d4a: 4934 ldr r1, [pc, #208] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002d4c: 4313 orrs r3, r2
+ 8002d4e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 8002cd6: 687b ldr r3, [r7, #4]
- 8002cd8: 681b ldr r3, [r3, #0]
- 8002cda: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8002cde: 2b00 cmp r3, #0
- 8002ce0: d011 beq.n 8002d06 <HAL_RCCEx_PeriphCLKConfig+0x412>
+ 8002d52: 687b ldr r3, [r7, #4]
+ 8002d54: 681b ldr r3, [r3, #0]
+ 8002d56: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8002d5a: 2b00 cmp r3, #0
+ 8002d5c: d011 beq.n 8002d82 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 8002ce2: 4b2f ldr r3, [pc, #188] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002ce4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002ce8: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
- 8002cec: 687b ldr r3, [r7, #4]
- 8002cee: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002cf0: 492b ldr r1, [pc, #172] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002cf2: 4313 orrs r3, r2
- 8002cf4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002d5e: 4b2f ldr r3, [pc, #188] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002d60: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002d64: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
+ 8002d68: 687b ldr r3, [r7, #4]
+ 8002d6a: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002d6c: 492b ldr r1, [pc, #172] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002d6e: 4313 orrs r3, r2
+ 8002d70: f8c1 3090 str.w r3, [r1, #144] ; 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 8002cf8: 687b ldr r3, [r7, #4]
- 8002cfa: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002cfc: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8002d00: d101 bne.n 8002d06 <HAL_RCCEx_PeriphCLKConfig+0x412>
+ 8002d74: 687b ldr r3, [r7, #4]
+ 8002d76: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002d78: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
+ 8002d7c: d101 bne.n 8002d82 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
pllsaiused = 1;
- 8002d02: 2301 movs r3, #1
- 8002d04: 61bb str r3, [r7, #24]
+ 8002d7e: 2301 movs r3, #1
+ 8002d80: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 8002d06: 687b ldr r3, [r7, #4]
- 8002d08: 681b ldr r3, [r3, #0]
- 8002d0a: f003 0308 and.w r3, r3, #8
- 8002d0e: 2b00 cmp r3, #0
- 8002d10: d001 beq.n 8002d16 <HAL_RCCEx_PeriphCLKConfig+0x422>
+ 8002d82: 687b ldr r3, [r7, #4]
+ 8002d84: 681b ldr r3, [r3, #0]
+ 8002d86: f003 0308 and.w r3, r3, #8
+ 8002d8a: 2b00 cmp r3, #0
+ 8002d8c: d001 beq.n 8002d92 <HAL_RCCEx_PeriphCLKConfig+0x422>
{
pllsaiused = 1;
- 8002d12: 2301 movs r3, #1
- 8002d14: 61bb str r3, [r7, #24]
+ 8002d8e: 2301 movs r3, #1
+ 8002d90: 61bb str r3, [r7, #24]
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 8002d16: 687b ldr r3, [r7, #4]
- 8002d18: 681b ldr r3, [r3, #0]
- 8002d1a: f403 2380 and.w r3, r3, #262144 ; 0x40000
- 8002d1e: 2b00 cmp r3, #0
- 8002d20: d00a beq.n 8002d38 <HAL_RCCEx_PeriphCLKConfig+0x444>
+ 8002d92: 687b ldr r3, [r7, #4]
+ 8002d94: 681b ldr r3, [r3, #0]
+ 8002d96: f403 2380 and.w r3, r3, #262144 ; 0x40000
+ 8002d9a: 2b00 cmp r3, #0
+ 8002d9c: d00a beq.n 8002db4 <HAL_RCCEx_PeriphCLKConfig+0x444>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 8002d22: 4b1f ldr r3, [pc, #124] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d24: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d28: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
- 8002d2c: 687b ldr r3, [r7, #4]
- 8002d2e: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002d30: 491b ldr r1, [pc, #108] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d32: 4313 orrs r3, r2
- 8002d34: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002d9e: 4b1f ldr r3, [pc, #124] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002da0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002da4: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
+ 8002da8: 687b ldr r3, [r7, #4]
+ 8002daa: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8002dac: 491b ldr r1, [pc, #108] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002dae: 4313 orrs r3, r2
+ 8002db0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 8002d38: 687b ldr r3, [r7, #4]
- 8002d3a: 681b ldr r3, [r3, #0]
- 8002d3c: f403 0300 and.w r3, r3, #8388608 ; 0x800000
- 8002d40: 2b00 cmp r3, #0
- 8002d42: d00b beq.n 8002d5c <HAL_RCCEx_PeriphCLKConfig+0x468>
+ 8002db4: 687b ldr r3, [r7, #4]
+ 8002db6: 681b ldr r3, [r3, #0]
+ 8002db8: f403 0300 and.w r3, r3, #8388608 ; 0x800000
+ 8002dbc: 2b00 cmp r3, #0
+ 8002dbe: d00b beq.n 8002dd8 <HAL_RCCEx_PeriphCLKConfig+0x468>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 8002d44: 4b16 ldr r3, [pc, #88] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d46: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d4a: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
- 8002d4e: 687b ldr r3, [r7, #4]
- 8002d50: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
- 8002d54: 4912 ldr r1, [pc, #72] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d56: 4313 orrs r3, r2
- 8002d58: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002dc0: 4b16 ldr r3, [pc, #88] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002dc2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002dc6: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
+ 8002dca: 687b ldr r3, [r7, #4]
+ 8002dcc: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
+ 8002dd0: 4912 ldr r1, [pc, #72] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002dd2: 4313 orrs r3, r2
+ 8002dd4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 8002d5c: 687b ldr r3, [r7, #4]
- 8002d5e: 681b ldr r3, [r3, #0]
- 8002d60: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
- 8002d64: 2b00 cmp r3, #0
- 8002d66: d00b beq.n 8002d80 <HAL_RCCEx_PeriphCLKConfig+0x48c>
+ 8002dd8: 687b ldr r3, [r7, #4]
+ 8002dda: 681b ldr r3, [r3, #0]
+ 8002ddc: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
+ 8002de0: 2b00 cmp r3, #0
+ 8002de2: d00b beq.n 8002dfc <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 8002d68: 4b0d ldr r3, [pc, #52] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d6a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002d6e: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
- 8002d72: 687b ldr r3, [r7, #4]
- 8002d74: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002d78: 4909 ldr r1, [pc, #36] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d7a: 4313 orrs r3, r2
- 8002d7c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8002de4: 4b0d ldr r3, [pc, #52] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002de6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002dea: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
+ 8002dee: 687b ldr r3, [r7, #4]
+ 8002df0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8002df4: 4909 ldr r1, [pc, #36] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002df6: 4313 orrs r3, r2
+ 8002df8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- DFSDM1 Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 8002d80: 687b ldr r3, [r7, #4]
- 8002d82: 681b ldr r3, [r3, #0]
- 8002d84: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8002d88: 2b00 cmp r3, #0
- 8002d8a: d00f beq.n 8002dac <HAL_RCCEx_PeriphCLKConfig+0x4b8>
+ 8002dfc: 687b ldr r3, [r7, #4]
+ 8002dfe: 681b ldr r3, [r3, #0]
+ 8002e00: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8002e04: 2b00 cmp r3, #0
+ 8002e06: d00f beq.n 8002e28 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8002d8c: 4b04 ldr r3, [pc, #16] ; (8002da0 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8002d8e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002d92: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
- 8002d96: 687b ldr r3, [r7, #4]
- 8002d98: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8002d9c: e002 b.n 8002da4 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 8002d9e: bf00 nop
- 8002da0: 40023800 .word 0x40023800
- 8002da4: 4985 ldr r1, [pc, #532] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002da6: 4313 orrs r3, r2
- 8002da8: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8002e08: 4b04 ldr r3, [pc, #16] ; (8002e1c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8002e0a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8002e0e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
+ 8002e12: 687b ldr r3, [r7, #4]
+ 8002e14: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8002e18: e002 b.n 8002e20 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
+ 8002e1a: bf00 nop
+ 8002e1c: 40023800 .word 0x40023800
+ 8002e20: 4985 ldr r1, [pc, #532] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002e22: 4313 orrs r3, r2
+ 8002e24: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8002dac: 687b ldr r3, [r7, #4]
- 8002dae: 681b ldr r3, [r3, #0]
- 8002db0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8002db4: 2b00 cmp r3, #0
- 8002db6: d00b beq.n 8002dd0 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
+ 8002e28: 687b ldr r3, [r7, #4]
+ 8002e2a: 681b ldr r3, [r3, #0]
+ 8002e2c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8002e30: 2b00 cmp r3, #0
+ 8002e32: d00b beq.n 8002e4c <HAL_RCCEx_PeriphCLKConfig+0x4dc>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
/* Configure the DFSDM interface clock source */
__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 8002db8: 4b80 ldr r3, [pc, #512] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002dba: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002dbe: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8002dc2: 687b ldr r3, [r7, #4]
- 8002dc4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002dc8: 497c ldr r1, [pc, #496] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002dca: 4313 orrs r3, r2
- 8002dcc: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8002e34: 4b80 ldr r3, [pc, #512] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002e36: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8002e3a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
+ 8002e3e: 687b ldr r3, [r7, #4]
+ 8002e40: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8002e44: 497c ldr r1, [pc, #496] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002e46: 4313 orrs r3, r2
+ 8002e48: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 8002dd0: 69fb ldr r3, [r7, #28]
- 8002dd2: 2b01 cmp r3, #1
- 8002dd4: d005 beq.n 8002de2 <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 8002dd6: 687b ldr r3, [r7, #4]
- 8002dd8: 681b ldr r3, [r3, #0]
- 8002dda: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 8002dde: f040 80d6 bne.w 8002f8e <HAL_RCCEx_PeriphCLKConfig+0x69a>
+ 8002e4c: 69fb ldr r3, [r7, #28]
+ 8002e4e: 2b01 cmp r3, #1
+ 8002e50: d005 beq.n 8002e5e <HAL_RCCEx_PeriphCLKConfig+0x4ee>
+ 8002e52: 687b ldr r3, [r7, #4]
+ 8002e54: 681b ldr r3, [r3, #0]
+ 8002e56: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
+ 8002e5a: f040 80d6 bne.w 800300a <HAL_RCCEx_PeriphCLKConfig+0x69a>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
- 8002de2: 4b76 ldr r3, [pc, #472] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002de4: 681b ldr r3, [r3, #0]
- 8002de6: 4a75 ldr r2, [pc, #468] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002de8: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
- 8002dec: 6013 str r3, [r2, #0]
+ 8002e5e: 4b76 ldr r3, [pc, #472] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002e60: 681b ldr r3, [r3, #0]
+ 8002e62: 4a75 ldr r2, [pc, #468] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002e64: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
+ 8002e68: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002dee: f7fe fe25 bl 8001a3c <HAL_GetTick>
- 8002df2: 6178 str r0, [r7, #20]
+ 8002e6a: f7fe fe25 bl 8001ab8 <HAL_GetTick>
+ 8002e6e: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8002df4: e008 b.n 8002e08 <HAL_RCCEx_PeriphCLKConfig+0x514>
+ 8002e70: e008 b.n 8002e84 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8002df6: f7fe fe21 bl 8001a3c <HAL_GetTick>
- 8002dfa: 4602 mov r2, r0
- 8002dfc: 697b ldr r3, [r7, #20]
- 8002dfe: 1ad3 subs r3, r2, r3
- 8002e00: 2b64 cmp r3, #100 ; 0x64
- 8002e02: d901 bls.n 8002e08 <HAL_RCCEx_PeriphCLKConfig+0x514>
+ 8002e72: f7fe fe21 bl 8001ab8 <HAL_GetTick>
+ 8002e76: 4602 mov r2, r0
+ 8002e78: 697b ldr r3, [r7, #20]
+ 8002e7a: 1ad3 subs r3, r2, r3
+ 8002e7c: 2b64 cmp r3, #100 ; 0x64
+ 8002e7e: d901 bls.n 8002e84 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 8002e04: 2303 movs r3, #3
- 8002e06: e194 b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8002e80: 2303 movs r3, #3
+ 8002e82: e194 b.n 80031ae <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8002e08: 4b6c ldr r3, [pc, #432] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002e0a: 681b ldr r3, [r3, #0]
- 8002e0c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8002e10: 2b00 cmp r3, #0
- 8002e12: d1f0 bne.n 8002df6 <HAL_RCCEx_PeriphCLKConfig+0x502>
+ 8002e84: 4b6c ldr r3, [pc, #432] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002e86: 681b ldr r3, [r3, #0]
+ 8002e88: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8002e8c: 2b00 cmp r3, #0
+ 8002e8e: d1f0 bne.n 8002e72 <HAL_RCCEx_PeriphCLKConfig+0x502>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 8002e14: 687b ldr r3, [r7, #4]
- 8002e16: 681b ldr r3, [r3, #0]
- 8002e18: f003 0301 and.w r3, r3, #1
- 8002e1c: 2b00 cmp r3, #0
- 8002e1e: d021 beq.n 8002e64 <HAL_RCCEx_PeriphCLKConfig+0x570>
- 8002e20: 687b ldr r3, [r7, #4]
- 8002e22: 6b5b ldr r3, [r3, #52] ; 0x34
- 8002e24: 2b00 cmp r3, #0
- 8002e26: d11d bne.n 8002e64 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ 8002e90: 687b ldr r3, [r7, #4]
+ 8002e92: 681b ldr r3, [r3, #0]
+ 8002e94: f003 0301 and.w r3, r3, #1
+ 8002e98: 2b00 cmp r3, #0
+ 8002e9a: d021 beq.n 8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ 8002e9c: 687b ldr r3, [r7, #4]
+ 8002e9e: 6b5b ldr r3, [r3, #52] ; 0x34
+ 8002ea0: 2b00 cmp r3, #0
+ 8002ea2: d11d bne.n 8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x570>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8002e28: 4b64 ldr r3, [pc, #400] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002e2a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002e2e: 0c1b lsrs r3, r3, #16
- 8002e30: f003 0303 and.w r3, r3, #3
- 8002e34: 613b str r3, [r7, #16]
+ 8002ea4: 4b64 ldr r3, [pc, #400] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002ea6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8002eaa: 0c1b lsrs r3, r3, #16
+ 8002eac: f003 0303 and.w r3, r3, #3
+ 8002eb0: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8002e36: 4b61 ldr r3, [pc, #388] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002e38: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002e3c: 0e1b lsrs r3, r3, #24
- 8002e3e: f003 030f and.w r3, r3, #15
- 8002e42: 60fb str r3, [r7, #12]
+ 8002eb2: 4b61 ldr r3, [pc, #388] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002eb4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8002eb8: 0e1b lsrs r3, r3, #24
+ 8002eba: f003 030f and.w r3, r3, #15
+ 8002ebe: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 8002e44: 687b ldr r3, [r7, #4]
- 8002e46: 685b ldr r3, [r3, #4]
- 8002e48: 019a lsls r2, r3, #6
- 8002e4a: 693b ldr r3, [r7, #16]
- 8002e4c: 041b lsls r3, r3, #16
- 8002e4e: 431a orrs r2, r3
- 8002e50: 68fb ldr r3, [r7, #12]
- 8002e52: 061b lsls r3, r3, #24
- 8002e54: 431a orrs r2, r3
- 8002e56: 687b ldr r3, [r7, #4]
- 8002e58: 689b ldr r3, [r3, #8]
- 8002e5a: 071b lsls r3, r3, #28
- 8002e5c: 4957 ldr r1, [pc, #348] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002e5e: 4313 orrs r3, r2
- 8002e60: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8002ec0: 687b ldr r3, [r7, #4]
+ 8002ec2: 685b ldr r3, [r3, #4]
+ 8002ec4: 019a lsls r2, r3, #6
+ 8002ec6: 693b ldr r3, [r7, #16]
+ 8002ec8: 041b lsls r3, r3, #16
+ 8002eca: 431a orrs r2, r3
+ 8002ecc: 68fb ldr r3, [r7, #12]
+ 8002ece: 061b lsls r3, r3, #24
+ 8002ed0: 431a orrs r2, r3
+ 8002ed2: 687b ldr r3, [r7, #4]
+ 8002ed4: 689b ldr r3, [r3, #8]
+ 8002ed6: 071b lsls r3, r3, #28
+ 8002ed8: 4957 ldr r1, [pc, #348] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002eda: 4313 orrs r3, r2
+ 8002edc: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8002e64: 687b ldr r3, [r7, #4]
- 8002e66: 681b ldr r3, [r3, #0]
- 8002e68: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002e6c: 2b00 cmp r3, #0
- 8002e6e: d004 beq.n 8002e7a <HAL_RCCEx_PeriphCLKConfig+0x586>
- 8002e70: 687b ldr r3, [r7, #4]
- 8002e72: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002e74: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8002e78: d00a beq.n 8002e90 <HAL_RCCEx_PeriphCLKConfig+0x59c>
+ 8002ee0: 687b ldr r3, [r7, #4]
+ 8002ee2: 681b ldr r3, [r3, #0]
+ 8002ee4: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 8002ee8: 2b00 cmp r3, #0
+ 8002eea: d004 beq.n 8002ef6 <HAL_RCCEx_PeriphCLKConfig+0x586>
+ 8002eec: 687b ldr r3, [r7, #4]
+ 8002eee: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 8002ef0: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 8002ef4: d00a beq.n 8002f0c <HAL_RCCEx_PeriphCLKConfig+0x59c>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8002e7a: 687b ldr r3, [r7, #4]
- 8002e7c: 681b ldr r3, [r3, #0]
- 8002e7e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8002ef6: 687b ldr r3, [r7, #4]
+ 8002ef8: 681b ldr r3, [r3, #0]
+ 8002efa: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8002e82: 2b00 cmp r3, #0
- 8002e84: d02e beq.n 8002ee4 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ 8002efe: 2b00 cmp r3, #0
+ 8002f00: d02e beq.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8002e86: 687b ldr r3, [r7, #4]
- 8002e88: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002e8a: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8002e8e: d129 bne.n 8002ee4 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ 8002f02: 687b ldr r3, [r7, #4]
+ 8002f04: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002f06: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8002f0a: d129 bne.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8002e90: 4b4a ldr r3, [pc, #296] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002e92: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002e96: 0c1b lsrs r3, r3, #16
- 8002e98: f003 0303 and.w r3, r3, #3
- 8002e9c: 613b str r3, [r7, #16]
+ 8002f0c: 4b4a ldr r3, [pc, #296] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002f0e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8002f12: 0c1b lsrs r3, r3, #16
+ 8002f14: f003 0303 and.w r3, r3, #3
+ 8002f18: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8002e9e: 4b47 ldr r3, [pc, #284] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002ea0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002ea4: 0f1b lsrs r3, r3, #28
- 8002ea6: f003 0307 and.w r3, r3, #7
- 8002eaa: 60fb str r3, [r7, #12]
+ 8002f1a: 4b47 ldr r3, [pc, #284] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002f1c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8002f20: 0f1b lsrs r3, r3, #28
+ 8002f22: f003 0307 and.w r3, r3, #7
+ 8002f26: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8002eac: 687b ldr r3, [r7, #4]
- 8002eae: 685b ldr r3, [r3, #4]
- 8002eb0: 019a lsls r2, r3, #6
- 8002eb2: 693b ldr r3, [r7, #16]
- 8002eb4: 041b lsls r3, r3, #16
- 8002eb6: 431a orrs r2, r3
- 8002eb8: 687b ldr r3, [r7, #4]
- 8002eba: 68db ldr r3, [r3, #12]
- 8002ebc: 061b lsls r3, r3, #24
- 8002ebe: 431a orrs r2, r3
- 8002ec0: 68fb ldr r3, [r7, #12]
- 8002ec2: 071b lsls r3, r3, #28
- 8002ec4: 493d ldr r1, [pc, #244] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002ec6: 4313 orrs r3, r2
- 8002ec8: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8002f28: 687b ldr r3, [r7, #4]
+ 8002f2a: 685b ldr r3, [r3, #4]
+ 8002f2c: 019a lsls r2, r3, #6
+ 8002f2e: 693b ldr r3, [r7, #16]
+ 8002f30: 041b lsls r3, r3, #16
+ 8002f32: 431a orrs r2, r3
+ 8002f34: 687b ldr r3, [r7, #4]
+ 8002f36: 68db ldr r3, [r3, #12]
+ 8002f38: 061b lsls r3, r3, #24
+ 8002f3a: 431a orrs r2, r3
+ 8002f3c: 68fb ldr r3, [r7, #12]
+ 8002f3e: 071b lsls r3, r3, #28
+ 8002f40: 493d ldr r1, [pc, #244] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002f42: 4313 orrs r3, r2
+ 8002f44: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8002ecc: 4b3b ldr r3, [pc, #236] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002ece: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8002ed2: f023 021f bic.w r2, r3, #31
- 8002ed6: 687b ldr r3, [r7, #4]
- 8002ed8: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002eda: 3b01 subs r3, #1
- 8002edc: 4937 ldr r1, [pc, #220] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002ede: 4313 orrs r3, r2
- 8002ee0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8002f48: 4b3b ldr r3, [pc, #236] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002f4a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8002f4e: f023 021f bic.w r2, r3, #31
+ 8002f52: 687b ldr r3, [r7, #4]
+ 8002f54: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8002f56: 3b01 subs r3, #1
+ 8002f58: 4937 ldr r1, [pc, #220] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002f5a: 4313 orrs r3, r2
+ 8002f5c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8002ee4: 687b ldr r3, [r7, #4]
- 8002ee6: 681b ldr r3, [r3, #0]
- 8002ee8: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8002eec: 2b00 cmp r3, #0
- 8002eee: d01d beq.n 8002f2c <HAL_RCCEx_PeriphCLKConfig+0x638>
+ 8002f60: 687b ldr r3, [r7, #4]
+ 8002f62: 681b ldr r3, [r3, #0]
+ 8002f64: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
+ 8002f68: 2b00 cmp r3, #0
+ 8002f6a: d01d beq.n 8002fa8 <HAL_RCCEx_PeriphCLKConfig+0x638>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8002ef0: 4b32 ldr r3, [pc, #200] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002ef2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002ef6: 0e1b lsrs r3, r3, #24
- 8002ef8: f003 030f and.w r3, r3, #15
- 8002efc: 613b str r3, [r7, #16]
+ 8002f6c: 4b32 ldr r3, [pc, #200] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002f6e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8002f72: 0e1b lsrs r3, r3, #24
+ 8002f74: f003 030f and.w r3, r3, #15
+ 8002f78: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8002efe: 4b2f ldr r3, [pc, #188] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f00: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8002f04: 0f1b lsrs r3, r3, #28
- 8002f06: f003 0307 and.w r3, r3, #7
- 8002f0a: 60fb str r3, [r7, #12]
+ 8002f7a: 4b2f ldr r3, [pc, #188] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002f7c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8002f80: 0f1b lsrs r3, r3, #28
+ 8002f82: f003 0307 and.w r3, r3, #7
+ 8002f86: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 8002f0c: 687b ldr r3, [r7, #4]
- 8002f0e: 685b ldr r3, [r3, #4]
- 8002f10: 019a lsls r2, r3, #6
- 8002f12: 687b ldr r3, [r7, #4]
- 8002f14: 691b ldr r3, [r3, #16]
- 8002f16: 041b lsls r3, r3, #16
- 8002f18: 431a orrs r2, r3
- 8002f1a: 693b ldr r3, [r7, #16]
- 8002f1c: 061b lsls r3, r3, #24
- 8002f1e: 431a orrs r2, r3
- 8002f20: 68fb ldr r3, [r7, #12]
- 8002f22: 071b lsls r3, r3, #28
- 8002f24: 4925 ldr r1, [pc, #148] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f26: 4313 orrs r3, r2
- 8002f28: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8002f88: 687b ldr r3, [r7, #4]
+ 8002f8a: 685b ldr r3, [r3, #4]
+ 8002f8c: 019a lsls r2, r3, #6
+ 8002f8e: 687b ldr r3, [r7, #4]
+ 8002f90: 691b ldr r3, [r3, #16]
+ 8002f92: 041b lsls r3, r3, #16
+ 8002f94: 431a orrs r2, r3
+ 8002f96: 693b ldr r3, [r7, #16]
+ 8002f98: 061b lsls r3, r3, #24
+ 8002f9a: 431a orrs r2, r3
+ 8002f9c: 68fb ldr r3, [r7, #12]
+ 8002f9e: 071b lsls r3, r3, #28
+ 8002fa0: 4925 ldr r1, [pc, #148] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002fa2: 4313 orrs r3, r2
+ 8002fa4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 8002f2c: 687b ldr r3, [r7, #4]
- 8002f2e: 681b ldr r3, [r3, #0]
- 8002f30: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8002f34: 2b00 cmp r3, #0
- 8002f36: d011 beq.n 8002f5c <HAL_RCCEx_PeriphCLKConfig+0x668>
+ 8002fa8: 687b ldr r3, [r7, #4]
+ 8002faa: 681b ldr r3, [r3, #0]
+ 8002fac: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8002fb0: 2b00 cmp r3, #0
+ 8002fb2: d011 beq.n 8002fd8 <HAL_RCCEx_PeriphCLKConfig+0x668>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 8002f38: 687b ldr r3, [r7, #4]
- 8002f3a: 685b ldr r3, [r3, #4]
- 8002f3c: 019a lsls r2, r3, #6
- 8002f3e: 687b ldr r3, [r7, #4]
- 8002f40: 691b ldr r3, [r3, #16]
- 8002f42: 041b lsls r3, r3, #16
- 8002f44: 431a orrs r2, r3
- 8002f46: 687b ldr r3, [r7, #4]
- 8002f48: 68db ldr r3, [r3, #12]
- 8002f4a: 061b lsls r3, r3, #24
- 8002f4c: 431a orrs r2, r3
- 8002f4e: 687b ldr r3, [r7, #4]
- 8002f50: 689b ldr r3, [r3, #8]
- 8002f52: 071b lsls r3, r3, #28
- 8002f54: 4919 ldr r1, [pc, #100] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f56: 4313 orrs r3, r2
- 8002f58: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8002fb4: 687b ldr r3, [r7, #4]
+ 8002fb6: 685b ldr r3, [r3, #4]
+ 8002fb8: 019a lsls r2, r3, #6
+ 8002fba: 687b ldr r3, [r7, #4]
+ 8002fbc: 691b ldr r3, [r3, #16]
+ 8002fbe: 041b lsls r3, r3, #16
+ 8002fc0: 431a orrs r2, r3
+ 8002fc2: 687b ldr r3, [r7, #4]
+ 8002fc4: 68db ldr r3, [r3, #12]
+ 8002fc6: 061b lsls r3, r3, #24
+ 8002fc8: 431a orrs r2, r3
+ 8002fca: 687b ldr r3, [r7, #4]
+ 8002fcc: 689b ldr r3, [r3, #8]
+ 8002fce: 071b lsls r3, r3, #28
+ 8002fd0: 4919 ldr r1, [pc, #100] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002fd2: 4313 orrs r3, r2
+ 8002fd4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
- 8002f5c: 4b17 ldr r3, [pc, #92] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f5e: 681b ldr r3, [r3, #0]
- 8002f60: 4a16 ldr r2, [pc, #88] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f62: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
- 8002f66: 6013 str r3, [r2, #0]
+ 8002fd8: 4b17 ldr r3, [pc, #92] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002fda: 681b ldr r3, [r3, #0]
+ 8002fdc: 4a16 ldr r2, [pc, #88] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002fde: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
+ 8002fe2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002f68: f7fe fd68 bl 8001a3c <HAL_GetTick>
- 8002f6c: 6178 str r0, [r7, #20]
+ 8002fe4: f7fe fd68 bl 8001ab8 <HAL_GetTick>
+ 8002fe8: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 8002f6e: e008 b.n 8002f82 <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ 8002fea: e008 b.n 8002ffe <HAL_RCCEx_PeriphCLKConfig+0x68e>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8002f70: f7fe fd64 bl 8001a3c <HAL_GetTick>
- 8002f74: 4602 mov r2, r0
- 8002f76: 697b ldr r3, [r7, #20]
- 8002f78: 1ad3 subs r3, r2, r3
- 8002f7a: 2b64 cmp r3, #100 ; 0x64
- 8002f7c: d901 bls.n 8002f82 <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ 8002fec: f7fe fd64 bl 8001ab8 <HAL_GetTick>
+ 8002ff0: 4602 mov r2, r0
+ 8002ff2: 697b ldr r3, [r7, #20]
+ 8002ff4: 1ad3 subs r3, r2, r3
+ 8002ff6: 2b64 cmp r3, #100 ; 0x64
+ 8002ff8: d901 bls.n 8002ffe <HAL_RCCEx_PeriphCLKConfig+0x68e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 8002f7e: 2303 movs r3, #3
- 8002f80: e0d7 b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8002ffa: 2303 movs r3, #3
+ 8002ffc: e0d7 b.n 80031ae <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 8002f82: 4b0e ldr r3, [pc, #56] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f84: 681b ldr r3, [r3, #0]
- 8002f86: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8002f8a: 2b00 cmp r3, #0
- 8002f8c: d0f0 beq.n 8002f70 <HAL_RCCEx_PeriphCLKConfig+0x67c>
+ 8002ffe: 4b0e ldr r3, [pc, #56] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8003000: 681b ldr r3, [r3, #0]
+ 8003002: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8003006: 2b00 cmp r3, #0
+ 8003008: d0f0 beq.n 8002fec <HAL_RCCEx_PeriphCLKConfig+0x67c>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
- 8002f8e: 69bb ldr r3, [r7, #24]
- 8002f90: 2b01 cmp r3, #1
- 8002f92: f040 80cd bne.w 8003130 <HAL_RCCEx_PeriphCLKConfig+0x83c>
+ 800300a: 69bb ldr r3, [r7, #24]
+ 800300c: 2b01 cmp r3, #1
+ 800300e: f040 80cd bne.w 80031ac <HAL_RCCEx_PeriphCLKConfig+0x83c>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
- 8002f96: 4b09 ldr r3, [pc, #36] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f98: 681b ldr r3, [r3, #0]
- 8002f9a: 4a08 ldr r2, [pc, #32] ; (8002fbc <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002f9c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8002fa0: 6013 str r3, [r2, #0]
+ 8003012: 4b09 ldr r3, [pc, #36] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8003014: 681b ldr r3, [r3, #0]
+ 8003016: 4a08 ldr r2, [pc, #32] ; (8003038 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8003018: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 800301c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8002fa2: f7fe fd4b bl 8001a3c <HAL_GetTick>
- 8002fa6: 6178 str r0, [r7, #20]
+ 800301e: f7fe fd4b bl 8001ab8 <HAL_GetTick>
+ 8003022: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8002fa8: e00a b.n 8002fc0 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ 8003024: e00a b.n 800303c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8002faa: f7fe fd47 bl 8001a3c <HAL_GetTick>
- 8002fae: 4602 mov r2, r0
- 8002fb0: 697b ldr r3, [r7, #20]
- 8002fb2: 1ad3 subs r3, r2, r3
- 8002fb4: 2b64 cmp r3, #100 ; 0x64
- 8002fb6: d903 bls.n 8002fc0 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ 8003026: f7fe fd47 bl 8001ab8 <HAL_GetTick>
+ 800302a: 4602 mov r2, r0
+ 800302c: 697b ldr r3, [r7, #20]
+ 800302e: 1ad3 subs r3, r2, r3
+ 8003030: 2b64 cmp r3, #100 ; 0x64
+ 8003032: d903 bls.n 800303c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 8002fb8: 2303 movs r3, #3
- 8002fba: e0ba b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 8002fbc: 40023800 .word 0x40023800
+ 8003034: 2303 movs r3, #3
+ 8003036: e0ba b.n 80031ae <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8003038: 40023800 .word 0x40023800
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8002fc0: 4b5e ldr r3, [pc, #376] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002fc2: 681b ldr r3, [r3, #0]
- 8002fc4: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8002fc8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8002fcc: d0ed beq.n 8002faa <HAL_RCCEx_PeriphCLKConfig+0x6b6>
+ 800303c: 4b5e ldr r3, [pc, #376] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800303e: 681b ldr r3, [r3, #0]
+ 8003040: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
+ 8003044: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
+ 8003048: d0ed beq.n 8003026 <HAL_RCCEx_PeriphCLKConfig+0x6b6>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8002fce: 687b ldr r3, [r7, #4]
- 8002fd0: 681b ldr r3, [r3, #0]
- 8002fd2: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002fd6: 2b00 cmp r3, #0
- 8002fd8: d003 beq.n 8002fe2 <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 8002fda: 687b ldr r3, [r7, #4]
- 8002fdc: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8002fde: 2b00 cmp r3, #0
- 8002fe0: d009 beq.n 8002ff6 <HAL_RCCEx_PeriphCLKConfig+0x702>
+ 800304a: 687b ldr r3, [r7, #4]
+ 800304c: 681b ldr r3, [r3, #0]
+ 800304e: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 8003052: 2b00 cmp r3, #0
+ 8003054: d003 beq.n 800305e <HAL_RCCEx_PeriphCLKConfig+0x6ee>
+ 8003056: 687b ldr r3, [r7, #4]
+ 8003058: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 800305a: 2b00 cmp r3, #0
+ 800305c: d009 beq.n 8003072 <HAL_RCCEx_PeriphCLKConfig+0x702>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 8002fe2: 687b ldr r3, [r7, #4]
- 8002fe4: 681b ldr r3, [r3, #0]
- 8002fe6: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 800305e: 687b ldr r3, [r7, #4]
+ 8003060: 681b ldr r3, [r3, #0]
+ 8003062: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8002fea: 2b00 cmp r3, #0
- 8002fec: d02e beq.n 800304c <HAL_RCCEx_PeriphCLKConfig+0x758>
+ 8003066: 2b00 cmp r3, #0
+ 8003068: d02e beq.n 80030c8 <HAL_RCCEx_PeriphCLKConfig+0x758>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 8002fee: 687b ldr r3, [r7, #4]
- 8002ff0: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002ff2: 2b00 cmp r3, #0
- 8002ff4: d12a bne.n 800304c <HAL_RCCEx_PeriphCLKConfig+0x758>
+ 800306a: 687b ldr r3, [r7, #4]
+ 800306c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800306e: 2b00 cmp r3, #0
+ 8003070: d12a bne.n 80030c8 <HAL_RCCEx_PeriphCLKConfig+0x758>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8002ff6: 4b51 ldr r3, [pc, #324] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002ff8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8002ffc: 0c1b lsrs r3, r3, #16
- 8002ffe: f003 0303 and.w r3, r3, #3
- 8003002: 613b str r3, [r7, #16]
+ 8003072: 4b51 ldr r3, [pc, #324] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8003074: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8003078: 0c1b lsrs r3, r3, #16
+ 800307a: f003 0303 and.w r3, r3, #3
+ 800307e: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8003004: 4b4d ldr r3, [pc, #308] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003006: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800300a: 0f1b lsrs r3, r3, #28
- 800300c: f003 0307 and.w r3, r3, #7
- 8003010: 60fb str r3, [r7, #12]
+ 8003080: 4b4d ldr r3, [pc, #308] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8003082: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8003086: 0f1b lsrs r3, r3, #28
+ 8003088: f003 0307 and.w r3, r3, #7
+ 800308c: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 8003012: 687b ldr r3, [r7, #4]
- 8003014: 695b ldr r3, [r3, #20]
- 8003016: 019a lsls r2, r3, #6
- 8003018: 693b ldr r3, [r7, #16]
- 800301a: 041b lsls r3, r3, #16
- 800301c: 431a orrs r2, r3
- 800301e: 687b ldr r3, [r7, #4]
- 8003020: 699b ldr r3, [r3, #24]
- 8003022: 061b lsls r3, r3, #24
- 8003024: 431a orrs r2, r3
- 8003026: 68fb ldr r3, [r7, #12]
- 8003028: 071b lsls r3, r3, #28
- 800302a: 4944 ldr r1, [pc, #272] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800302c: 4313 orrs r3, r2
- 800302e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+ 800308e: 687b ldr r3, [r7, #4]
+ 8003090: 695b ldr r3, [r3, #20]
+ 8003092: 019a lsls r2, r3, #6
+ 8003094: 693b ldr r3, [r7, #16]
+ 8003096: 041b lsls r3, r3, #16
+ 8003098: 431a orrs r2, r3
+ 800309a: 687b ldr r3, [r7, #4]
+ 800309c: 699b ldr r3, [r3, #24]
+ 800309e: 061b lsls r3, r3, #24
+ 80030a0: 431a orrs r2, r3
+ 80030a2: 68fb ldr r3, [r7, #12]
+ 80030a4: 071b lsls r3, r3, #28
+ 80030a6: 4944 ldr r1, [pc, #272] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80030a8: 4313 orrs r3, r2
+ 80030aa: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 8003032: 4b42 ldr r3, [pc, #264] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003034: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8003038: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
- 800303c: 687b ldr r3, [r7, #4]
- 800303e: 6a9b ldr r3, [r3, #40] ; 0x28
- 8003040: 3b01 subs r3, #1
- 8003042: 021b lsls r3, r3, #8
- 8003044: 493d ldr r1, [pc, #244] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003046: 4313 orrs r3, r2
- 8003048: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 80030ae: 4b42 ldr r3, [pc, #264] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80030b0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 80030b4: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
+ 80030b8: 687b ldr r3, [r7, #4]
+ 80030ba: 6a9b ldr r3, [r3, #40] ; 0x28
+ 80030bc: 3b01 subs r3, #1
+ 80030be: 021b lsls r3, r3, #8
+ 80030c0: 493d ldr r1, [pc, #244] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80030c2: 4313 orrs r3, r2
+ 80030c4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 800304c: 687b ldr r3, [r7, #4]
- 800304e: 681b ldr r3, [r3, #0]
- 8003050: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8003054: 2b00 cmp r3, #0
- 8003056: d022 beq.n 800309e <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 8003058: 687b ldr r3, [r7, #4]
- 800305a: 6fdb ldr r3, [r3, #124] ; 0x7c
- 800305c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8003060: d11d bne.n 800309e <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ 80030c8: 687b ldr r3, [r7, #4]
+ 80030ca: 681b ldr r3, [r3, #0]
+ 80030cc: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 80030d0: 2b00 cmp r3, #0
+ 80030d2: d022 beq.n 800311a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ 80030d4: 687b ldr r3, [r7, #4]
+ 80030d6: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 80030d8: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
+ 80030dc: d11d bne.n 800311a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 8003062: 4b36 ldr r3, [pc, #216] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003064: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003068: 0e1b lsrs r3, r3, #24
- 800306a: f003 030f and.w r3, r3, #15
- 800306e: 613b str r3, [r7, #16]
+ 80030de: 4b36 ldr r3, [pc, #216] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80030e0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 80030e4: 0e1b lsrs r3, r3, #24
+ 80030e6: f003 030f and.w r3, r3, #15
+ 80030ea: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8003070: 4b32 ldr r3, [pc, #200] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003072: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8003076: 0f1b lsrs r3, r3, #28
- 8003078: f003 0307 and.w r3, r3, #7
- 800307c: 60fb str r3, [r7, #12]
+ 80030ec: 4b32 ldr r3, [pc, #200] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80030ee: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 80030f2: 0f1b lsrs r3, r3, #28
+ 80030f4: f003 0307 and.w r3, r3, #7
+ 80030f8: 60fb str r3, [r7, #12]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 800307e: 687b ldr r3, [r7, #4]
- 8003080: 695b ldr r3, [r3, #20]
- 8003082: 019a lsls r2, r3, #6
- 8003084: 687b ldr r3, [r7, #4]
- 8003086: 6a1b ldr r3, [r3, #32]
- 8003088: 041b lsls r3, r3, #16
- 800308a: 431a orrs r2, r3
- 800308c: 693b ldr r3, [r7, #16]
- 800308e: 061b lsls r3, r3, #24
- 8003090: 431a orrs r2, r3
- 8003092: 68fb ldr r3, [r7, #12]
- 8003094: 071b lsls r3, r3, #28
- 8003096: 4929 ldr r1, [pc, #164] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003098: 4313 orrs r3, r2
- 800309a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+ 80030fa: 687b ldr r3, [r7, #4]
+ 80030fc: 695b ldr r3, [r3, #20]
+ 80030fe: 019a lsls r2, r3, #6
+ 8003100: 687b ldr r3, [r7, #4]
+ 8003102: 6a1b ldr r3, [r3, #32]
+ 8003104: 041b lsls r3, r3, #16
+ 8003106: 431a orrs r2, r3
+ 8003108: 693b ldr r3, [r7, #16]
+ 800310a: 061b lsls r3, r3, #24
+ 800310c: 431a orrs r2, r3
+ 800310e: 68fb ldr r3, [r7, #12]
+ 8003110: 071b lsls r3, r3, #28
+ 8003112: 4929 ldr r1, [pc, #164] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8003114: 4313 orrs r3, r2
+ 8003116: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 800309e: 687b ldr r3, [r7, #4]
- 80030a0: 681b ldr r3, [r3, #0]
- 80030a2: f003 0308 and.w r3, r3, #8
- 80030a6: 2b00 cmp r3, #0
- 80030a8: d028 beq.n 80030fc <HAL_RCCEx_PeriphCLKConfig+0x808>
+ 800311a: 687b ldr r3, [r7, #4]
+ 800311c: 681b ldr r3, [r3, #0]
+ 800311e: f003 0308 and.w r3, r3, #8
+ 8003122: 2b00 cmp r3, #0
+ 8003124: d028 beq.n 8003178 <HAL_RCCEx_PeriphCLKConfig+0x808>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 80030aa: 4b24 ldr r3, [pc, #144] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80030ac: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80030b0: 0e1b lsrs r3, r3, #24
- 80030b2: f003 030f and.w r3, r3, #15
- 80030b6: 613b str r3, [r7, #16]
+ 8003126: 4b24 ldr r3, [pc, #144] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8003128: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 800312c: 0e1b lsrs r3, r3, #24
+ 800312e: f003 030f and.w r3, r3, #15
+ 8003132: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 80030b8: 4b20 ldr r3, [pc, #128] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80030ba: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80030be: 0c1b lsrs r3, r3, #16
- 80030c0: f003 0303 and.w r3, r3, #3
- 80030c4: 60fb str r3, [r7, #12]
+ 8003134: 4b20 ldr r3, [pc, #128] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8003136: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 800313a: 0c1b lsrs r3, r3, #16
+ 800313c: f003 0303 and.w r3, r3, #3
+ 8003140: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 80030c6: 687b ldr r3, [r7, #4]
- 80030c8: 695b ldr r3, [r3, #20]
- 80030ca: 019a lsls r2, r3, #6
- 80030cc: 68fb ldr r3, [r7, #12]
- 80030ce: 041b lsls r3, r3, #16
- 80030d0: 431a orrs r2, r3
- 80030d2: 693b ldr r3, [r7, #16]
- 80030d4: 061b lsls r3, r3, #24
- 80030d6: 431a orrs r2, r3
- 80030d8: 687b ldr r3, [r7, #4]
- 80030da: 69db ldr r3, [r3, #28]
- 80030dc: 071b lsls r3, r3, #28
- 80030de: 4917 ldr r1, [pc, #92] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80030e0: 4313 orrs r3, r2
- 80030e2: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+ 8003142: 687b ldr r3, [r7, #4]
+ 8003144: 695b ldr r3, [r3, #20]
+ 8003146: 019a lsls r2, r3, #6
+ 8003148: 68fb ldr r3, [r7, #12]
+ 800314a: 041b lsls r3, r3, #16
+ 800314c: 431a orrs r2, r3
+ 800314e: 693b ldr r3, [r7, #16]
+ 8003150: 061b lsls r3, r3, #24
+ 8003152: 431a orrs r2, r3
+ 8003154: 687b ldr r3, [r7, #4]
+ 8003156: 69db ldr r3, [r3, #28]
+ 8003158: 071b lsls r3, r3, #28
+ 800315a: 4917 ldr r1, [pc, #92] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800315c: 4313 orrs r3, r2
+ 800315e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 80030e6: 4b15 ldr r3, [pc, #84] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80030e8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80030ec: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 80030f0: 687b ldr r3, [r7, #4]
- 80030f2: 6adb ldr r3, [r3, #44] ; 0x2c
- 80030f4: 4911 ldr r1, [pc, #68] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80030f6: 4313 orrs r3, r2
- 80030f8: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8003162: 4b15 ldr r3, [pc, #84] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8003164: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8003168: f423 3240 bic.w r2, r3, #196608 ; 0x30000
+ 800316c: 687b ldr r3, [r7, #4]
+ 800316e: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8003170: 4911 ldr r1, [pc, #68] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8003172: 4313 orrs r3, r2
+ 8003174: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
- 80030fc: 4b0f ldr r3, [pc, #60] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80030fe: 681b ldr r3, [r3, #0]
- 8003100: 4a0e ldr r2, [pc, #56] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003102: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8003106: 6013 str r3, [r2, #0]
+ 8003178: 4b0f ldr r3, [pc, #60] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800317a: 681b ldr r3, [r3, #0]
+ 800317c: 4a0e ldr r2, [pc, #56] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800317e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8003182: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8003108: f7fe fc98 bl 8001a3c <HAL_GetTick>
- 800310c: 6178 str r0, [r7, #20]
+ 8003184: f7fe fc98 bl 8001ab8 <HAL_GetTick>
+ 8003188: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 800310e: e008 b.n 8003122 <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ 800318a: e008 b.n 800319e <HAL_RCCEx_PeriphCLKConfig+0x82e>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8003110: f7fe fc94 bl 8001a3c <HAL_GetTick>
- 8003114: 4602 mov r2, r0
- 8003116: 697b ldr r3, [r7, #20]
- 8003118: 1ad3 subs r3, r2, r3
- 800311a: 2b64 cmp r3, #100 ; 0x64
- 800311c: d901 bls.n 8003122 <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ 800318c: f7fe fc94 bl 8001ab8 <HAL_GetTick>
+ 8003190: 4602 mov r2, r0
+ 8003192: 697b ldr r3, [r7, #20]
+ 8003194: 1ad3 subs r3, r2, r3
+ 8003196: 2b64 cmp r3, #100 ; 0x64
+ 8003198: d901 bls.n 800319e <HAL_RCCEx_PeriphCLKConfig+0x82e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 800311e: 2303 movs r3, #3
- 8003120: e007 b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 800319a: 2303 movs r3, #3
+ 800319c: e007 b.n 80031ae <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 8003122: 4b06 ldr r3, [pc, #24] ; (800313c <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8003124: 681b ldr r3, [r3, #0]
- 8003126: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 800312a: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 800312e: d1ef bne.n 8003110 <HAL_RCCEx_PeriphCLKConfig+0x81c>
+ 800319e: 4b06 ldr r3, [pc, #24] ; (80031b8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80031a0: 681b ldr r3, [r3, #0]
+ 80031a2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
+ 80031a6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
+ 80031aa: d1ef bne.n 800318c <HAL_RCCEx_PeriphCLKConfig+0x81c>
}
}
}
return HAL_OK;
- 8003130: 2300 movs r3, #0
+ 80031ac: 2300 movs r3, #0
}
- 8003132: 4618 mov r0, r3
- 8003134: 3720 adds r7, #32
- 8003136: 46bd mov sp, r7
- 8003138: bd80 pop {r7, pc}
- 800313a: bf00 nop
- 800313c: 40023800 .word 0x40023800
-
-08003140 <HAL_TIM_Base_Init>:
+ 80031ae: 4618 mov r0, r3
+ 80031b0: 3720 adds r7, #32
+ 80031b2: 46bd mov sp, r7
+ 80031b4: bd80 pop {r7, pc}
+ 80031b6: bf00 nop
+ 80031b8: 40023800 .word 0x40023800
+
+080031bc <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
- 8003140: b580 push {r7, lr}
- 8003142: b082 sub sp, #8
- 8003144: af00 add r7, sp, #0
- 8003146: 6078 str r0, [r7, #4]
+ 80031bc: b580 push {r7, lr}
+ 80031be: b082 sub sp, #8
+ 80031c0: af00 add r7, sp, #0
+ 80031c2: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
- 8003148: 687b ldr r3, [r7, #4]
- 800314a: 2b00 cmp r3, #0
- 800314c: d101 bne.n 8003152 <HAL_TIM_Base_Init+0x12>
+ 80031c4: 687b ldr r3, [r7, #4]
+ 80031c6: 2b00 cmp r3, #0
+ 80031c8: d101 bne.n 80031ce <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
- 800314e: 2301 movs r3, #1
- 8003150: e01d b.n 800318e <HAL_TIM_Base_Init+0x4e>
+ 80031ca: 2301 movs r3, #1
+ 80031cc: e01d b.n 800320a <HAL_TIM_Base_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
- 8003152: 687b ldr r3, [r7, #4]
- 8003154: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8003158: b2db uxtb r3, r3
- 800315a: 2b00 cmp r3, #0
- 800315c: d106 bne.n 800316c <HAL_TIM_Base_Init+0x2c>
+ 80031ce: 687b ldr r3, [r7, #4]
+ 80031d0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
+ 80031d4: b2db uxtb r3, r3
+ 80031d6: 2b00 cmp r3, #0
+ 80031d8: d106 bne.n 80031e8 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
- 800315e: 687b ldr r3, [r7, #4]
- 8003160: 2200 movs r2, #0
- 8003162: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 80031da: 687b ldr r3, [r7, #4]
+ 80031dc: 2200 movs r2, #0
+ 80031de: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
- 8003166: 6878 ldr r0, [r7, #4]
- 8003168: f7fe faa0 bl 80016ac <HAL_TIM_Base_MspInit>
+ 80031e2: 6878 ldr r0, [r7, #4]
+ 80031e4: f7fe faa0 bl 8001728 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
- 800316c: 687b ldr r3, [r7, #4]
- 800316e: 2202 movs r2, #2
- 8003170: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 80031e8: 687b ldr r3, [r7, #4]
+ 80031ea: 2202 movs r2, #2
+ 80031ec: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003174: 687b ldr r3, [r7, #4]
- 8003176: 681a ldr r2, [r3, #0]
- 8003178: 687b ldr r3, [r7, #4]
- 800317a: 3304 adds r3, #4
- 800317c: 4619 mov r1, r3
- 800317e: 4610 mov r0, r2
- 8003180: f000 fc90 bl 8003aa4 <TIM_Base_SetConfig>
+ 80031f0: 687b ldr r3, [r7, #4]
+ 80031f2: 681a ldr r2, [r3, #0]
+ 80031f4: 687b ldr r3, [r7, #4]
+ 80031f6: 3304 adds r3, #4
+ 80031f8: 4619 mov r1, r3
+ 80031fa: 4610 mov r0, r2
+ 80031fc: f000 fc90 bl 8003b20 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
- 8003184: 687b ldr r3, [r7, #4]
- 8003186: 2201 movs r2, #1
- 8003188: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8003200: 687b ldr r3, [r7, #4]
+ 8003202: 2201 movs r2, #1
+ 8003204: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
- 800318c: 2300 movs r3, #0
+ 8003208: 2300 movs r3, #0
}
- 800318e: 4618 mov r0, r3
- 8003190: 3708 adds r7, #8
- 8003192: 46bd mov sp, r7
- 8003194: bd80 pop {r7, pc}
+ 800320a: 4618 mov r0, r3
+ 800320c: 3708 adds r7, #8
+ 800320e: 46bd mov sp, r7
+ 8003210: bd80 pop {r7, pc}
...
-08003198 <HAL_TIM_Base_Start_IT>:
+08003214 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
- 8003198: b480 push {r7}
- 800319a: b085 sub sp, #20
- 800319c: af00 add r7, sp, #0
- 800319e: 6078 str r0, [r7, #4]
+ 8003214: b480 push {r7}
+ 8003216: b085 sub sp, #20
+ 8003218: af00 add r7, sp, #0
+ 800321a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- 80031a0: 687b ldr r3, [r7, #4]
- 80031a2: 681b ldr r3, [r3, #0]
- 80031a4: 68da ldr r2, [r3, #12]
- 80031a6: 687b ldr r3, [r7, #4]
- 80031a8: 681b ldr r3, [r3, #0]
- 80031aa: f042 0201 orr.w r2, r2, #1
- 80031ae: 60da str r2, [r3, #12]
+ 800321c: 687b ldr r3, [r7, #4]
+ 800321e: 681b ldr r3, [r3, #0]
+ 8003220: 68da ldr r2, [r3, #12]
+ 8003222: 687b ldr r3, [r7, #4]
+ 8003224: 681b ldr r3, [r3, #0]
+ 8003226: f042 0201 orr.w r2, r2, #1
+ 800322a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 80031b0: 687b ldr r3, [r7, #4]
- 80031b2: 681b ldr r3, [r3, #0]
- 80031b4: 689a ldr r2, [r3, #8]
- 80031b6: 4b0c ldr r3, [pc, #48] ; (80031e8 <HAL_TIM_Base_Start_IT+0x50>)
- 80031b8: 4013 ands r3, r2
- 80031ba: 60fb str r3, [r7, #12]
+ 800322c: 687b ldr r3, [r7, #4]
+ 800322e: 681b ldr r3, [r3, #0]
+ 8003230: 689a ldr r2, [r3, #8]
+ 8003232: 4b0c ldr r3, [pc, #48] ; (8003264 <HAL_TIM_Base_Start_IT+0x50>)
+ 8003234: 4013 ands r3, r2
+ 8003236: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 80031bc: 68fb ldr r3, [r7, #12]
- 80031be: 2b06 cmp r3, #6
- 80031c0: d00b beq.n 80031da <HAL_TIM_Base_Start_IT+0x42>
- 80031c2: 68fb ldr r3, [r7, #12]
- 80031c4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 80031c8: d007 beq.n 80031da <HAL_TIM_Base_Start_IT+0x42>
+ 8003238: 68fb ldr r3, [r7, #12]
+ 800323a: 2b06 cmp r3, #6
+ 800323c: d00b beq.n 8003256 <HAL_TIM_Base_Start_IT+0x42>
+ 800323e: 68fb ldr r3, [r7, #12]
+ 8003240: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8003244: d007 beq.n 8003256 <HAL_TIM_Base_Start_IT+0x42>
{
__HAL_TIM_ENABLE(htim);
- 80031ca: 687b ldr r3, [r7, #4]
- 80031cc: 681b ldr r3, [r3, #0]
- 80031ce: 681a ldr r2, [r3, #0]
- 80031d0: 687b ldr r3, [r7, #4]
- 80031d2: 681b ldr r3, [r3, #0]
- 80031d4: f042 0201 orr.w r2, r2, #1
- 80031d8: 601a str r2, [r3, #0]
+ 8003246: 687b ldr r3, [r7, #4]
+ 8003248: 681b ldr r3, [r3, #0]
+ 800324a: 681a ldr r2, [r3, #0]
+ 800324c: 687b ldr r3, [r7, #4]
+ 800324e: 681b ldr r3, [r3, #0]
+ 8003250: f042 0201 orr.w r2, r2, #1
+ 8003254: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
- 80031da: 2300 movs r3, #0
+ 8003256: 2300 movs r3, #0
}
- 80031dc: 4618 mov r0, r3
- 80031de: 3714 adds r7, #20
- 80031e0: 46bd mov sp, r7
- 80031e2: f85d 7b04 ldr.w r7, [sp], #4
- 80031e6: 4770 bx lr
- 80031e8: 00010007 .word 0x00010007
-
-080031ec <HAL_TIM_PWM_Init>:
+ 8003258: 4618 mov r0, r3
+ 800325a: 3714 adds r7, #20
+ 800325c: 46bd mov sp, r7
+ 800325e: f85d 7b04 ldr.w r7, [sp], #4
+ 8003262: 4770 bx lr
+ 8003264: 00010007 .word 0x00010007
+
+08003268 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
- 80031ec: b580 push {r7, lr}
- 80031ee: b082 sub sp, #8
- 80031f0: af00 add r7, sp, #0
- 80031f2: 6078 str r0, [r7, #4]
+ 8003268: b580 push {r7, lr}
+ 800326a: b082 sub sp, #8
+ 800326c: af00 add r7, sp, #0
+ 800326e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
- 80031f4: 687b ldr r3, [r7, #4]
- 80031f6: 2b00 cmp r3, #0
- 80031f8: d101 bne.n 80031fe <HAL_TIM_PWM_Init+0x12>
+ 8003270: 687b ldr r3, [r7, #4]
+ 8003272: 2b00 cmp r3, #0
+ 8003274: d101 bne.n 800327a <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
- 80031fa: 2301 movs r3, #1
- 80031fc: e01d b.n 800323a <HAL_TIM_PWM_Init+0x4e>
+ 8003276: 2301 movs r3, #1
+ 8003278: e01d b.n 80032b6 <HAL_TIM_PWM_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
- 80031fe: 687b ldr r3, [r7, #4]
- 8003200: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8003204: b2db uxtb r3, r3
- 8003206: 2b00 cmp r3, #0
- 8003208: d106 bne.n 8003218 <HAL_TIM_PWM_Init+0x2c>
+ 800327a: 687b ldr r3, [r7, #4]
+ 800327c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
+ 8003280: b2db uxtb r3, r3
+ 8003282: 2b00 cmp r3, #0
+ 8003284: d106 bne.n 8003294 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
- 800320a: 687b ldr r3, [r7, #4]
- 800320c: 2200 movs r2, #0
- 800320e: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8003286: 687b ldr r3, [r7, #4]
+ 8003288: 2200 movs r2, #0
+ 800328a: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
- 8003212: 6878 ldr r0, [r7, #4]
- 8003214: f000 f815 bl 8003242 <HAL_TIM_PWM_MspInit>
+ 800328e: 6878 ldr r0, [r7, #4]
+ 8003290: f000 f815 bl 80032be <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
- 8003218: 687b ldr r3, [r7, #4]
- 800321a: 2202 movs r2, #2
- 800321c: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8003294: 687b ldr r3, [r7, #4]
+ 8003296: 2202 movs r2, #2
+ 8003298: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003220: 687b ldr r3, [r7, #4]
- 8003222: 681a ldr r2, [r3, #0]
- 8003224: 687b ldr r3, [r7, #4]
- 8003226: 3304 adds r3, #4
- 8003228: 4619 mov r1, r3
- 800322a: 4610 mov r0, r2
- 800322c: f000 fc3a bl 8003aa4 <TIM_Base_SetConfig>
+ 800329c: 687b ldr r3, [r7, #4]
+ 800329e: 681a ldr r2, [r3, #0]
+ 80032a0: 687b ldr r3, [r7, #4]
+ 80032a2: 3304 adds r3, #4
+ 80032a4: 4619 mov r1, r3
+ 80032a6: 4610 mov r0, r2
+ 80032a8: f000 fc3a bl 8003b20 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
- 8003230: 687b ldr r3, [r7, #4]
- 8003232: 2201 movs r2, #1
- 8003234: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 80032ac: 687b ldr r3, [r7, #4]
+ 80032ae: 2201 movs r2, #1
+ 80032b0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
- 8003238: 2300 movs r3, #0
+ 80032b4: 2300 movs r3, #0
}
- 800323a: 4618 mov r0, r3
- 800323c: 3708 adds r7, #8
- 800323e: 46bd mov sp, r7
- 8003240: bd80 pop {r7, pc}
+ 80032b6: 4618 mov r0, r3
+ 80032b8: 3708 adds r7, #8
+ 80032ba: 46bd mov sp, r7
+ 80032bc: bd80 pop {r7, pc}
-08003242 <HAL_TIM_PWM_MspInit>:
+080032be <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
- 8003242: b480 push {r7}
- 8003244: b083 sub sp, #12
- 8003246: af00 add r7, sp, #0
- 8003248: 6078 str r0, [r7, #4]
+ 80032be: b480 push {r7}
+ 80032c0: b083 sub sp, #12
+ 80032c2: af00 add r7, sp, #0
+ 80032c4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
- 800324a: bf00 nop
- 800324c: 370c adds r7, #12
- 800324e: 46bd mov sp, r7
- 8003250: f85d 7b04 ldr.w r7, [sp], #4
- 8003254: 4770 bx lr
+ 80032c6: bf00 nop
+ 80032c8: 370c adds r7, #12
+ 80032ca: 46bd mov sp, r7
+ 80032cc: f85d 7b04 ldr.w r7, [sp], #4
+ 80032d0: 4770 bx lr
...
-08003258 <HAL_TIM_PWM_Start>:
+080032d4 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- 8003258: b580 push {r7, lr}
- 800325a: b084 sub sp, #16
- 800325c: af00 add r7, sp, #0
- 800325e: 6078 str r0, [r7, #4]
- 8003260: 6039 str r1, [r7, #0]
+ 80032d4: b580 push {r7, lr}
+ 80032d6: b084 sub sp, #16
+ 80032d8: af00 add r7, sp, #0
+ 80032da: 6078 str r0, [r7, #4]
+ 80032dc: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- 8003262: 687b ldr r3, [r7, #4]
- 8003264: 681b ldr r3, [r3, #0]
- 8003266: 2201 movs r2, #1
- 8003268: 6839 ldr r1, [r7, #0]
- 800326a: 4618 mov r0, r3
- 800326c: f000 ffb2 bl 80041d4 <TIM_CCxChannelCmd>
+ 80032de: 687b ldr r3, [r7, #4]
+ 80032e0: 681b ldr r3, [r3, #0]
+ 80032e2: 2201 movs r2, #1
+ 80032e4: 6839 ldr r1, [r7, #0]
+ 80032e6: 4618 mov r0, r3
+ 80032e8: f000 ffb2 bl 8004250 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- 8003270: 687b ldr r3, [r7, #4]
- 8003272: 681b ldr r3, [r3, #0]
- 8003274: 4a17 ldr r2, [pc, #92] ; (80032d4 <HAL_TIM_PWM_Start+0x7c>)
- 8003276: 4293 cmp r3, r2
- 8003278: d004 beq.n 8003284 <HAL_TIM_PWM_Start+0x2c>
- 800327a: 687b ldr r3, [r7, #4]
- 800327c: 681b ldr r3, [r3, #0]
- 800327e: 4a16 ldr r2, [pc, #88] ; (80032d8 <HAL_TIM_PWM_Start+0x80>)
- 8003280: 4293 cmp r3, r2
- 8003282: d101 bne.n 8003288 <HAL_TIM_PWM_Start+0x30>
- 8003284: 2301 movs r3, #1
- 8003286: e000 b.n 800328a <HAL_TIM_PWM_Start+0x32>
- 8003288: 2300 movs r3, #0
- 800328a: 2b00 cmp r3, #0
- 800328c: d007 beq.n 800329e <HAL_TIM_PWM_Start+0x46>
+ 80032ec: 687b ldr r3, [r7, #4]
+ 80032ee: 681b ldr r3, [r3, #0]
+ 80032f0: 4a17 ldr r2, [pc, #92] ; (8003350 <HAL_TIM_PWM_Start+0x7c>)
+ 80032f2: 4293 cmp r3, r2
+ 80032f4: d004 beq.n 8003300 <HAL_TIM_PWM_Start+0x2c>
+ 80032f6: 687b ldr r3, [r7, #4]
+ 80032f8: 681b ldr r3, [r3, #0]
+ 80032fa: 4a16 ldr r2, [pc, #88] ; (8003354 <HAL_TIM_PWM_Start+0x80>)
+ 80032fc: 4293 cmp r3, r2
+ 80032fe: d101 bne.n 8003304 <HAL_TIM_PWM_Start+0x30>
+ 8003300: 2301 movs r3, #1
+ 8003302: e000 b.n 8003306 <HAL_TIM_PWM_Start+0x32>
+ 8003304: 2300 movs r3, #0
+ 8003306: 2b00 cmp r3, #0
+ 8003308: d007 beq.n 800331a <HAL_TIM_PWM_Start+0x46>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
- 800328e: 687b ldr r3, [r7, #4]
- 8003290: 681b ldr r3, [r3, #0]
- 8003292: 6c5a ldr r2, [r3, #68] ; 0x44
- 8003294: 687b ldr r3, [r7, #4]
- 8003296: 681b ldr r3, [r3, #0]
- 8003298: f442 4200 orr.w r2, r2, #32768 ; 0x8000
- 800329c: 645a str r2, [r3, #68] ; 0x44
+ 800330a: 687b ldr r3, [r7, #4]
+ 800330c: 681b ldr r3, [r3, #0]
+ 800330e: 6c5a ldr r2, [r3, #68] ; 0x44
+ 8003310: 687b ldr r3, [r7, #4]
+ 8003312: 681b ldr r3, [r3, #0]
+ 8003314: f442 4200 orr.w r2, r2, #32768 ; 0x8000
+ 8003318: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 800329e: 687b ldr r3, [r7, #4]
- 80032a0: 681b ldr r3, [r3, #0]
- 80032a2: 689a ldr r2, [r3, #8]
- 80032a4: 4b0d ldr r3, [pc, #52] ; (80032dc <HAL_TIM_PWM_Start+0x84>)
- 80032a6: 4013 ands r3, r2
- 80032a8: 60fb str r3, [r7, #12]
+ 800331a: 687b ldr r3, [r7, #4]
+ 800331c: 681b ldr r3, [r3, #0]
+ 800331e: 689a ldr r2, [r3, #8]
+ 8003320: 4b0d ldr r3, [pc, #52] ; (8003358 <HAL_TIM_PWM_Start+0x84>)
+ 8003322: 4013 ands r3, r2
+ 8003324: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 80032aa: 68fb ldr r3, [r7, #12]
- 80032ac: 2b06 cmp r3, #6
- 80032ae: d00b beq.n 80032c8 <HAL_TIM_PWM_Start+0x70>
- 80032b0: 68fb ldr r3, [r7, #12]
- 80032b2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 80032b6: d007 beq.n 80032c8 <HAL_TIM_PWM_Start+0x70>
+ 8003326: 68fb ldr r3, [r7, #12]
+ 8003328: 2b06 cmp r3, #6
+ 800332a: d00b beq.n 8003344 <HAL_TIM_PWM_Start+0x70>
+ 800332c: 68fb ldr r3, [r7, #12]
+ 800332e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8003332: d007 beq.n 8003344 <HAL_TIM_PWM_Start+0x70>
{
__HAL_TIM_ENABLE(htim);
- 80032b8: 687b ldr r3, [r7, #4]
- 80032ba: 681b ldr r3, [r3, #0]
- 80032bc: 681a ldr r2, [r3, #0]
- 80032be: 687b ldr r3, [r7, #4]
- 80032c0: 681b ldr r3, [r3, #0]
- 80032c2: f042 0201 orr.w r2, r2, #1
- 80032c6: 601a str r2, [r3, #0]
+ 8003334: 687b ldr r3, [r7, #4]
+ 8003336: 681b ldr r3, [r3, #0]
+ 8003338: 681a ldr r2, [r3, #0]
+ 800333a: 687b ldr r3, [r7, #4]
+ 800333c: 681b ldr r3, [r3, #0]
+ 800333e: f042 0201 orr.w r2, r2, #1
+ 8003342: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
- 80032c8: 2300 movs r3, #0
+ 8003344: 2300 movs r3, #0
}
- 80032ca: 4618 mov r0, r3
- 80032cc: 3710 adds r7, #16
- 80032ce: 46bd mov sp, r7
- 80032d0: bd80 pop {r7, pc}
- 80032d2: bf00 nop
- 80032d4: 40010000 .word 0x40010000
- 80032d8: 40010400 .word 0x40010400
- 80032dc: 00010007 .word 0x00010007
-
-080032e0 <HAL_TIM_Encoder_Init>:
+ 8003346: 4618 mov r0, r3
+ 8003348: 3710 adds r7, #16
+ 800334a: 46bd mov sp, r7
+ 800334c: bd80 pop {r7, pc}
+ 800334e: bf00 nop
+ 8003350: 40010000 .word 0x40010000
+ 8003354: 40010400 .word 0x40010400
+ 8003358: 00010007 .word 0x00010007
+
+0800335c <HAL_TIM_Encoder_Init>:
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
- 80032e0: b580 push {r7, lr}
- 80032e2: b086 sub sp, #24
- 80032e4: af00 add r7, sp, #0
- 80032e6: 6078 str r0, [r7, #4]
- 80032e8: 6039 str r1, [r7, #0]
+ 800335c: b580 push {r7, lr}
+ 800335e: b086 sub sp, #24
+ 8003360: af00 add r7, sp, #0
+ 8003362: 6078 str r0, [r7, #4]
+ 8003364: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Check the TIM handle allocation */
if (htim == NULL)
- 80032ea: 687b ldr r3, [r7, #4]
- 80032ec: 2b00 cmp r3, #0
- 80032ee: d101 bne.n 80032f4 <HAL_TIM_Encoder_Init+0x14>
+ 8003366: 687b ldr r3, [r7, #4]
+ 8003368: 2b00 cmp r3, #0
+ 800336a: d101 bne.n 8003370 <HAL_TIM_Encoder_Init+0x14>
{
return HAL_ERROR;
- 80032f0: 2301 movs r3, #1
- 80032f2: e07b b.n 80033ec <HAL_TIM_Encoder_Init+0x10c>
+ 800336c: 2301 movs r3, #1
+ 800336e: e07b b.n 8003468 <HAL_TIM_Encoder_Init+0x10c>
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
if (htim->State == HAL_TIM_STATE_RESET)
- 80032f4: 687b ldr r3, [r7, #4]
- 80032f6: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 80032fa: b2db uxtb r3, r3
- 80032fc: 2b00 cmp r3, #0
- 80032fe: d106 bne.n 800330e <HAL_TIM_Encoder_Init+0x2e>
+ 8003370: 687b ldr r3, [r7, #4]
+ 8003372: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
+ 8003376: b2db uxtb r3, r3
+ 8003378: 2b00 cmp r3, #0
+ 800337a: d106 bne.n 800338a <HAL_TIM_Encoder_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
- 8003300: 687b ldr r3, [r7, #4]
- 8003302: 2200 movs r2, #0
- 8003304: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 800337c: 687b ldr r3, [r7, #4]
+ 800337e: 2200 movs r2, #0
+ 8003380: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Encoder_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
- 8003308: 6878 ldr r0, [r7, #4]
- 800330a: f7fe f93f bl 800158c <HAL_TIM_Encoder_MspInit>
+ 8003384: 6878 ldr r0, [r7, #4]
+ 8003386: f7fe f93f bl 8001608 <HAL_TIM_Encoder_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
- 800330e: 687b ldr r3, [r7, #4]
- 8003310: 2202 movs r2, #2
- 8003312: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 800338a: 687b ldr r3, [r7, #4]
+ 800338c: 2202 movs r2, #2
+ 800338e: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Reset the SMS and ECE bits */
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
- 8003316: 687b ldr r3, [r7, #4]
- 8003318: 681b ldr r3, [r3, #0]
- 800331a: 6899 ldr r1, [r3, #8]
- 800331c: 687b ldr r3, [r7, #4]
- 800331e: 681a ldr r2, [r3, #0]
- 8003320: 4b34 ldr r3, [pc, #208] ; (80033f4 <HAL_TIM_Encoder_Init+0x114>)
- 8003322: 400b ands r3, r1
- 8003324: 6093 str r3, [r2, #8]
+ 8003392: 687b ldr r3, [r7, #4]
+ 8003394: 681b ldr r3, [r3, #0]
+ 8003396: 6899 ldr r1, [r3, #8]
+ 8003398: 687b ldr r3, [r7, #4]
+ 800339a: 681a ldr r2, [r3, #0]
+ 800339c: 4b34 ldr r3, [pc, #208] ; (8003470 <HAL_TIM_Encoder_Init+0x114>)
+ 800339e: 400b ands r3, r1
+ 80033a0: 6093 str r3, [r2, #8]
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003326: 687b ldr r3, [r7, #4]
- 8003328: 681a ldr r2, [r3, #0]
- 800332a: 687b ldr r3, [r7, #4]
- 800332c: 3304 adds r3, #4
- 800332e: 4619 mov r1, r3
- 8003330: 4610 mov r0, r2
- 8003332: f000 fbb7 bl 8003aa4 <TIM_Base_SetConfig>
+ 80033a2: 687b ldr r3, [r7, #4]
+ 80033a4: 681a ldr r2, [r3, #0]
+ 80033a6: 687b ldr r3, [r7, #4]
+ 80033a8: 3304 adds r3, #4
+ 80033aa: 4619 mov r1, r3
+ 80033ac: 4610 mov r0, r2
+ 80033ae: f000 fbb7 bl 8003b20 <TIM_Base_SetConfig>
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
- 8003336: 687b ldr r3, [r7, #4]
- 8003338: 681b ldr r3, [r3, #0]
- 800333a: 689b ldr r3, [r3, #8]
- 800333c: 617b str r3, [r7, #20]
+ 80033b2: 687b ldr r3, [r7, #4]
+ 80033b4: 681b ldr r3, [r3, #0]
+ 80033b6: 689b ldr r3, [r3, #8]
+ 80033b8: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmr1 = htim->Instance->CCMR1;
- 800333e: 687b ldr r3, [r7, #4]
- 8003340: 681b ldr r3, [r3, #0]
- 8003342: 699b ldr r3, [r3, #24]
- 8003344: 613b str r3, [r7, #16]
+ 80033ba: 687b ldr r3, [r7, #4]
+ 80033bc: 681b ldr r3, [r3, #0]
+ 80033be: 699b ldr r3, [r3, #24]
+ 80033c0: 613b str r3, [r7, #16]
/* Get the TIMx CCER register value */
tmpccer = htim->Instance->CCER;
- 8003346: 687b ldr r3, [r7, #4]
- 8003348: 681b ldr r3, [r3, #0]
- 800334a: 6a1b ldr r3, [r3, #32]
- 800334c: 60fb str r3, [r7, #12]
+ 80033c2: 687b ldr r3, [r7, #4]
+ 80033c4: 681b ldr r3, [r3, #0]
+ 80033c6: 6a1b ldr r3, [r3, #32]
+ 80033c8: 60fb str r3, [r7, #12]
/* Set the encoder Mode */
tmpsmcr |= sConfig->EncoderMode;
- 800334e: 683b ldr r3, [r7, #0]
- 8003350: 681b ldr r3, [r3, #0]
- 8003352: 697a ldr r2, [r7, #20]
- 8003354: 4313 orrs r3, r2
- 8003356: 617b str r3, [r7, #20]
+ 80033ca: 683b ldr r3, [r7, #0]
+ 80033cc: 681b ldr r3, [r3, #0]
+ 80033ce: 697a ldr r2, [r7, #20]
+ 80033d0: 4313 orrs r3, r2
+ 80033d2: 617b str r3, [r7, #20]
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- 8003358: 693a ldr r2, [r7, #16]
- 800335a: 4b27 ldr r3, [pc, #156] ; (80033f8 <HAL_TIM_Encoder_Init+0x118>)
- 800335c: 4013 ands r3, r2
- 800335e: 613b str r3, [r7, #16]
+ 80033d4: 693a ldr r2, [r7, #16]
+ 80033d6: 4b27 ldr r3, [pc, #156] ; (8003474 <HAL_TIM_Encoder_Init+0x118>)
+ 80033d8: 4013 ands r3, r2
+ 80033da: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- 8003360: 683b ldr r3, [r7, #0]
- 8003362: 689a ldr r2, [r3, #8]
- 8003364: 683b ldr r3, [r7, #0]
- 8003366: 699b ldr r3, [r3, #24]
- 8003368: 021b lsls r3, r3, #8
- 800336a: 4313 orrs r3, r2
- 800336c: 693a ldr r2, [r7, #16]
- 800336e: 4313 orrs r3, r2
- 8003370: 613b str r3, [r7, #16]
+ 80033dc: 683b ldr r3, [r7, #0]
+ 80033de: 689a ldr r2, [r3, #8]
+ 80033e0: 683b ldr r3, [r7, #0]
+ 80033e2: 699b ldr r3, [r3, #24]
+ 80033e4: 021b lsls r3, r3, #8
+ 80033e6: 4313 orrs r3, r2
+ 80033e8: 693a ldr r2, [r7, #16]
+ 80033ea: 4313 orrs r3, r2
+ 80033ec: 613b str r3, [r7, #16]
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- 8003372: 693a ldr r2, [r7, #16]
- 8003374: 4b21 ldr r3, [pc, #132] ; (80033fc <HAL_TIM_Encoder_Init+0x11c>)
- 8003376: 4013 ands r3, r2
- 8003378: 613b str r3, [r7, #16]
+ 80033ee: 693a ldr r2, [r7, #16]
+ 80033f0: 4b21 ldr r3, [pc, #132] ; (8003478 <HAL_TIM_Encoder_Init+0x11c>)
+ 80033f2: 4013 ands r3, r2
+ 80033f4: 613b str r3, [r7, #16]
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- 800337a: 693a ldr r2, [r7, #16]
- 800337c: 4b20 ldr r3, [pc, #128] ; (8003400 <HAL_TIM_Encoder_Init+0x120>)
- 800337e: 4013 ands r3, r2
- 8003380: 613b str r3, [r7, #16]
+ 80033f6: 693a ldr r2, [r7, #16]
+ 80033f8: 4b20 ldr r3, [pc, #128] ; (800347c <HAL_TIM_Encoder_Init+0x120>)
+ 80033fa: 4013 ands r3, r2
+ 80033fc: 613b str r3, [r7, #16]
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- 8003382: 683b ldr r3, [r7, #0]
- 8003384: 68da ldr r2, [r3, #12]
- 8003386: 683b ldr r3, [r7, #0]
- 8003388: 69db ldr r3, [r3, #28]
- 800338a: 021b lsls r3, r3, #8
- 800338c: 4313 orrs r3, r2
- 800338e: 693a ldr r2, [r7, #16]
- 8003390: 4313 orrs r3, r2
- 8003392: 613b str r3, [r7, #16]
+ 80033fe: 683b ldr r3, [r7, #0]
+ 8003400: 68da ldr r2, [r3, #12]
+ 8003402: 683b ldr r3, [r7, #0]
+ 8003404: 69db ldr r3, [r3, #28]
+ 8003406: 021b lsls r3, r3, #8
+ 8003408: 4313 orrs r3, r2
+ 800340a: 693a ldr r2, [r7, #16]
+ 800340c: 4313 orrs r3, r2
+ 800340e: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
- 8003394: 683b ldr r3, [r7, #0]
- 8003396: 691b ldr r3, [r3, #16]
- 8003398: 011a lsls r2, r3, #4
- 800339a: 683b ldr r3, [r7, #0]
- 800339c: 6a1b ldr r3, [r3, #32]
- 800339e: 031b lsls r3, r3, #12
- 80033a0: 4313 orrs r3, r2
- 80033a2: 693a ldr r2, [r7, #16]
- 80033a4: 4313 orrs r3, r2
- 80033a6: 613b str r3, [r7, #16]
+ 8003410: 683b ldr r3, [r7, #0]
+ 8003412: 691b ldr r3, [r3, #16]
+ 8003414: 011a lsls r2, r3, #4
+ 8003416: 683b ldr r3, [r7, #0]
+ 8003418: 6a1b ldr r3, [r3, #32]
+ 800341a: 031b lsls r3, r3, #12
+ 800341c: 4313 orrs r3, r2
+ 800341e: 693a ldr r2, [r7, #16]
+ 8003420: 4313 orrs r3, r2
+ 8003422: 613b str r3, [r7, #16]
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- 80033a8: 68fb ldr r3, [r7, #12]
- 80033aa: f023 0322 bic.w r3, r3, #34 ; 0x22
- 80033ae: 60fb str r3, [r7, #12]
+ 8003424: 68fb ldr r3, [r7, #12]
+ 8003426: f023 0322 bic.w r3, r3, #34 ; 0x22
+ 800342a: 60fb str r3, [r7, #12]
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- 80033b0: 68fb ldr r3, [r7, #12]
- 80033b2: f023 0388 bic.w r3, r3, #136 ; 0x88
- 80033b6: 60fb str r3, [r7, #12]
+ 800342c: 68fb ldr r3, [r7, #12]
+ 800342e: f023 0388 bic.w r3, r3, #136 ; 0x88
+ 8003432: 60fb str r3, [r7, #12]
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
- 80033b8: 683b ldr r3, [r7, #0]
- 80033ba: 685a ldr r2, [r3, #4]
- 80033bc: 683b ldr r3, [r7, #0]
- 80033be: 695b ldr r3, [r3, #20]
- 80033c0: 011b lsls r3, r3, #4
- 80033c2: 4313 orrs r3, r2
- 80033c4: 68fa ldr r2, [r7, #12]
- 80033c6: 4313 orrs r3, r2
- 80033c8: 60fb str r3, [r7, #12]
+ 8003434: 683b ldr r3, [r7, #0]
+ 8003436: 685a ldr r2, [r3, #4]
+ 8003438: 683b ldr r3, [r7, #0]
+ 800343a: 695b ldr r3, [r3, #20]
+ 800343c: 011b lsls r3, r3, #4
+ 800343e: 4313 orrs r3, r2
+ 8003440: 68fa ldr r2, [r7, #12]
+ 8003442: 4313 orrs r3, r2
+ 8003444: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
- 80033ca: 687b ldr r3, [r7, #4]
- 80033cc: 681b ldr r3, [r3, #0]
- 80033ce: 697a ldr r2, [r7, #20]
- 80033d0: 609a str r2, [r3, #8]
+ 8003446: 687b ldr r3, [r7, #4]
+ 8003448: 681b ldr r3, [r3, #0]
+ 800344a: 697a ldr r2, [r7, #20]
+ 800344c: 609a str r2, [r3, #8]
/* Write to TIMx CCMR1 */
htim->Instance->CCMR1 = tmpccmr1;
- 80033d2: 687b ldr r3, [r7, #4]
- 80033d4: 681b ldr r3, [r3, #0]
- 80033d6: 693a ldr r2, [r7, #16]
- 80033d8: 619a str r2, [r3, #24]
+ 800344e: 687b ldr r3, [r7, #4]
+ 8003450: 681b ldr r3, [r3, #0]
+ 8003452: 693a ldr r2, [r7, #16]
+ 8003454: 619a str r2, [r3, #24]
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
- 80033da: 687b ldr r3, [r7, #4]
- 80033dc: 681b ldr r3, [r3, #0]
- 80033de: 68fa ldr r2, [r7, #12]
- 80033e0: 621a str r2, [r3, #32]
+ 8003456: 687b ldr r3, [r7, #4]
+ 8003458: 681b ldr r3, [r3, #0]
+ 800345a: 68fa ldr r2, [r7, #12]
+ 800345c: 621a str r2, [r3, #32]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
- 80033e2: 687b ldr r3, [r7, #4]
- 80033e4: 2201 movs r2, #1
- 80033e6: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 800345e: 687b ldr r3, [r7, #4]
+ 8003460: 2201 movs r2, #1
+ 8003462: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
- 80033ea: 2300 movs r3, #0
+ 8003466: 2300 movs r3, #0
}
- 80033ec: 4618 mov r0, r3
- 80033ee: 3718 adds r7, #24
- 80033f0: 46bd mov sp, r7
- 80033f2: bd80 pop {r7, pc}
- 80033f4: fffebff8 .word 0xfffebff8
- 80033f8: fffffcfc .word 0xfffffcfc
- 80033fc: fffff3f3 .word 0xfffff3f3
- 8003400: ffff0f0f .word 0xffff0f0f
-
-08003404 <HAL_TIM_Encoder_Start>:
+ 8003468: 4618 mov r0, r3
+ 800346a: 3718 adds r7, #24
+ 800346c: 46bd mov sp, r7
+ 800346e: bd80 pop {r7, pc}
+ 8003470: fffebff8 .word 0xfffebff8
+ 8003474: fffffcfc .word 0xfffffcfc
+ 8003478: fffff3f3 .word 0xfffff3f3
+ 800347c: ffff0f0f .word 0xffff0f0f
+
+08003480 <HAL_TIM_Encoder_Start>:
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- 8003404: b580 push {r7, lr}
- 8003406: b082 sub sp, #8
- 8003408: af00 add r7, sp, #0
- 800340a: 6078 str r0, [r7, #4]
- 800340c: 6039 str r1, [r7, #0]
+ 8003480: b580 push {r7, lr}
+ 8003482: b082 sub sp, #8
+ 8003484: af00 add r7, sp, #0
+ 8003486: 6078 str r0, [r7, #4]
+ 8003488: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
switch (Channel)
- 800340e: 683b ldr r3, [r7, #0]
- 8003410: 2b00 cmp r3, #0
- 8003412: d002 beq.n 800341a <HAL_TIM_Encoder_Start+0x16>
- 8003414: 2b04 cmp r3, #4
- 8003416: d008 beq.n 800342a <HAL_TIM_Encoder_Start+0x26>
- 8003418: e00f b.n 800343a <HAL_TIM_Encoder_Start+0x36>
+ 800348a: 683b ldr r3, [r7, #0]
+ 800348c: 2b00 cmp r3, #0
+ 800348e: d002 beq.n 8003496 <HAL_TIM_Encoder_Start+0x16>
+ 8003490: 2b04 cmp r3, #4
+ 8003492: d008 beq.n 80034a6 <HAL_TIM_Encoder_Start+0x26>
+ 8003494: e00f b.n 80034b6 <HAL_TIM_Encoder_Start+0x36>
{
case TIM_CHANNEL_1:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 800341a: 687b ldr r3, [r7, #4]
- 800341c: 681b ldr r3, [r3, #0]
- 800341e: 2201 movs r2, #1
- 8003420: 2100 movs r1, #0
- 8003422: 4618 mov r0, r3
- 8003424: f000 fed6 bl 80041d4 <TIM_CCxChannelCmd>
+ 8003496: 687b ldr r3, [r7, #4]
+ 8003498: 681b ldr r3, [r3, #0]
+ 800349a: 2201 movs r2, #1
+ 800349c: 2100 movs r1, #0
+ 800349e: 4618 mov r0, r3
+ 80034a0: f000 fed6 bl 8004250 <TIM_CCxChannelCmd>
break;
- 8003428: e016 b.n 8003458 <HAL_TIM_Encoder_Start+0x54>
+ 80034a4: e016 b.n 80034d4 <HAL_TIM_Encoder_Start+0x54>
}
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 800342a: 687b ldr r3, [r7, #4]
- 800342c: 681b ldr r3, [r3, #0]
- 800342e: 2201 movs r2, #1
- 8003430: 2104 movs r1, #4
- 8003432: 4618 mov r0, r3
- 8003434: f000 fece bl 80041d4 <TIM_CCxChannelCmd>
+ 80034a6: 687b ldr r3, [r7, #4]
+ 80034a8: 681b ldr r3, [r3, #0]
+ 80034aa: 2201 movs r2, #1
+ 80034ac: 2104 movs r1, #4
+ 80034ae: 4618 mov r0, r3
+ 80034b0: f000 fece bl 8004250 <TIM_CCxChannelCmd>
break;
- 8003438: e00e b.n 8003458 <HAL_TIM_Encoder_Start+0x54>
+ 80034b4: e00e b.n 80034d4 <HAL_TIM_Encoder_Start+0x54>
}
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 800343a: 687b ldr r3, [r7, #4]
- 800343c: 681b ldr r3, [r3, #0]
- 800343e: 2201 movs r2, #1
- 8003440: 2100 movs r1, #0
- 8003442: 4618 mov r0, r3
- 8003444: f000 fec6 bl 80041d4 <TIM_CCxChannelCmd>
+ 80034b6: 687b ldr r3, [r7, #4]
+ 80034b8: 681b ldr r3, [r3, #0]
+ 80034ba: 2201 movs r2, #1
+ 80034bc: 2100 movs r1, #0
+ 80034be: 4618 mov r0, r3
+ 80034c0: f000 fec6 bl 8004250 <TIM_CCxChannelCmd>
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 8003448: 687b ldr r3, [r7, #4]
- 800344a: 681b ldr r3, [r3, #0]
- 800344c: 2201 movs r2, #1
- 800344e: 2104 movs r1, #4
- 8003450: 4618 mov r0, r3
- 8003452: f000 febf bl 80041d4 <TIM_CCxChannelCmd>
+ 80034c4: 687b ldr r3, [r7, #4]
+ 80034c6: 681b ldr r3, [r3, #0]
+ 80034c8: 2201 movs r2, #1
+ 80034ca: 2104 movs r1, #4
+ 80034cc: 4618 mov r0, r3
+ 80034ce: f000 febf bl 8004250 <TIM_CCxChannelCmd>
break;
- 8003456: bf00 nop
+ 80034d2: bf00 nop
}
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
- 8003458: 687b ldr r3, [r7, #4]
- 800345a: 681b ldr r3, [r3, #0]
- 800345c: 681a ldr r2, [r3, #0]
- 800345e: 687b ldr r3, [r7, #4]
- 8003460: 681b ldr r3, [r3, #0]
- 8003462: f042 0201 orr.w r2, r2, #1
- 8003466: 601a str r2, [r3, #0]
+ 80034d4: 687b ldr r3, [r7, #4]
+ 80034d6: 681b ldr r3, [r3, #0]
+ 80034d8: 681a ldr r2, [r3, #0]
+ 80034da: 687b ldr r3, [r7, #4]
+ 80034dc: 681b ldr r3, [r3, #0]
+ 80034de: f042 0201 orr.w r2, r2, #1
+ 80034e2: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
- 8003468: 2300 movs r3, #0
+ 80034e4: 2300 movs r3, #0
}
- 800346a: 4618 mov r0, r3
- 800346c: 3708 adds r7, #8
- 800346e: 46bd mov sp, r7
- 8003470: bd80 pop {r7, pc}
+ 80034e6: 4618 mov r0, r3
+ 80034e8: 3708 adds r7, #8
+ 80034ea: 46bd mov sp, r7
+ 80034ec: bd80 pop {r7, pc}
-08003472 <HAL_TIM_IRQHandler>:
+080034ee <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
- 8003472: b580 push {r7, lr}
- 8003474: b082 sub sp, #8
- 8003476: af00 add r7, sp, #0
- 8003478: 6078 str r0, [r7, #4]
+ 80034ee: b580 push {r7, lr}
+ 80034f0: b082 sub sp, #8
+ 80034f2: af00 add r7, sp, #0
+ 80034f4: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- 800347a: 687b ldr r3, [r7, #4]
- 800347c: 681b ldr r3, [r3, #0]
- 800347e: 691b ldr r3, [r3, #16]
- 8003480: f003 0302 and.w r3, r3, #2
- 8003484: 2b02 cmp r3, #2
- 8003486: d122 bne.n 80034ce <HAL_TIM_IRQHandler+0x5c>
+ 80034f6: 687b ldr r3, [r7, #4]
+ 80034f8: 681b ldr r3, [r3, #0]
+ 80034fa: 691b ldr r3, [r3, #16]
+ 80034fc: f003 0302 and.w r3, r3, #2
+ 8003500: 2b02 cmp r3, #2
+ 8003502: d122 bne.n 800354a <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- 8003488: 687b ldr r3, [r7, #4]
- 800348a: 681b ldr r3, [r3, #0]
- 800348c: 68db ldr r3, [r3, #12]
- 800348e: f003 0302 and.w r3, r3, #2
- 8003492: 2b02 cmp r3, #2
- 8003494: d11b bne.n 80034ce <HAL_TIM_IRQHandler+0x5c>
+ 8003504: 687b ldr r3, [r7, #4]
+ 8003506: 681b ldr r3, [r3, #0]
+ 8003508: 68db ldr r3, [r3, #12]
+ 800350a: f003 0302 and.w r3, r3, #2
+ 800350e: 2b02 cmp r3, #2
+ 8003510: d11b bne.n 800354a <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- 8003496: 687b ldr r3, [r7, #4]
- 8003498: 681b ldr r3, [r3, #0]
- 800349a: f06f 0202 mvn.w r2, #2
- 800349e: 611a str r2, [r3, #16]
+ 8003512: 687b ldr r3, [r7, #4]
+ 8003514: 681b ldr r3, [r3, #0]
+ 8003516: f06f 0202 mvn.w r2, #2
+ 800351a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- 80034a0: 687b ldr r3, [r7, #4]
- 80034a2: 2201 movs r2, #1
- 80034a4: 771a strb r2, [r3, #28]
+ 800351c: 687b ldr r3, [r7, #4]
+ 800351e: 2201 movs r2, #1
+ 8003520: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- 80034a6: 687b ldr r3, [r7, #4]
- 80034a8: 681b ldr r3, [r3, #0]
- 80034aa: 699b ldr r3, [r3, #24]
- 80034ac: f003 0303 and.w r3, r3, #3
- 80034b0: 2b00 cmp r3, #0
- 80034b2: d003 beq.n 80034bc <HAL_TIM_IRQHandler+0x4a>
+ 8003522: 687b ldr r3, [r7, #4]
+ 8003524: 681b ldr r3, [r3, #0]
+ 8003526: 699b ldr r3, [r3, #24]
+ 8003528: f003 0303 and.w r3, r3, #3
+ 800352c: 2b00 cmp r3, #0
+ 800352e: d003 beq.n 8003538 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
- 80034b4: 6878 ldr r0, [r7, #4]
- 80034b6: f000 fad7 bl 8003a68 <HAL_TIM_IC_CaptureCallback>
- 80034ba: e005 b.n 80034c8 <HAL_TIM_IRQHandler+0x56>
+ 8003530: 6878 ldr r0, [r7, #4]
+ 8003532: f000 fad7 bl 8003ae4 <HAL_TIM_IC_CaptureCallback>
+ 8003536: e005 b.n 8003544 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
- 80034bc: 6878 ldr r0, [r7, #4]
- 80034be: f000 fac9 bl 8003a54 <HAL_TIM_OC_DelayElapsedCallback>
+ 8003538: 6878 ldr r0, [r7, #4]
+ 800353a: f000 fac9 bl 8003ad0 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80034c2: 6878 ldr r0, [r7, #4]
- 80034c4: f000 fada bl 8003a7c <HAL_TIM_PWM_PulseFinishedCallback>
+ 800353e: 6878 ldr r0, [r7, #4]
+ 8003540: f000 fada bl 8003af8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80034c8: 687b ldr r3, [r7, #4]
- 80034ca: 2200 movs r2, #0
- 80034cc: 771a strb r2, [r3, #28]
+ 8003544: 687b ldr r3, [r7, #4]
+ 8003546: 2200 movs r2, #0
+ 8003548: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- 80034ce: 687b ldr r3, [r7, #4]
- 80034d0: 681b ldr r3, [r3, #0]
- 80034d2: 691b ldr r3, [r3, #16]
- 80034d4: f003 0304 and.w r3, r3, #4
- 80034d8: 2b04 cmp r3, #4
- 80034da: d122 bne.n 8003522 <HAL_TIM_IRQHandler+0xb0>
+ 800354a: 687b ldr r3, [r7, #4]
+ 800354c: 681b ldr r3, [r3, #0]
+ 800354e: 691b ldr r3, [r3, #16]
+ 8003550: f003 0304 and.w r3, r3, #4
+ 8003554: 2b04 cmp r3, #4
+ 8003556: d122 bne.n 800359e <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- 80034dc: 687b ldr r3, [r7, #4]
- 80034de: 681b ldr r3, [r3, #0]
- 80034e0: 68db ldr r3, [r3, #12]
- 80034e2: f003 0304 and.w r3, r3, #4
- 80034e6: 2b04 cmp r3, #4
- 80034e8: d11b bne.n 8003522 <HAL_TIM_IRQHandler+0xb0>
+ 8003558: 687b ldr r3, [r7, #4]
+ 800355a: 681b ldr r3, [r3, #0]
+ 800355c: 68db ldr r3, [r3, #12]
+ 800355e: f003 0304 and.w r3, r3, #4
+ 8003562: 2b04 cmp r3, #4
+ 8003564: d11b bne.n 800359e <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- 80034ea: 687b ldr r3, [r7, #4]
- 80034ec: 681b ldr r3, [r3, #0]
- 80034ee: f06f 0204 mvn.w r2, #4
- 80034f2: 611a str r2, [r3, #16]
+ 8003566: 687b ldr r3, [r7, #4]
+ 8003568: 681b ldr r3, [r3, #0]
+ 800356a: f06f 0204 mvn.w r2, #4
+ 800356e: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- 80034f4: 687b ldr r3, [r7, #4]
- 80034f6: 2202 movs r2, #2
- 80034f8: 771a strb r2, [r3, #28]
+ 8003570: 687b ldr r3, [r7, #4]
+ 8003572: 2202 movs r2, #2
+ 8003574: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- 80034fa: 687b ldr r3, [r7, #4]
- 80034fc: 681b ldr r3, [r3, #0]
- 80034fe: 699b ldr r3, [r3, #24]
- 8003500: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003504: 2b00 cmp r3, #0
- 8003506: d003 beq.n 8003510 <HAL_TIM_IRQHandler+0x9e>
+ 8003576: 687b ldr r3, [r7, #4]
+ 8003578: 681b ldr r3, [r3, #0]
+ 800357a: 699b ldr r3, [r3, #24]
+ 800357c: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8003580: 2b00 cmp r3, #0
+ 8003582: d003 beq.n 800358c <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
- 8003508: 6878 ldr r0, [r7, #4]
- 800350a: f000 faad bl 8003a68 <HAL_TIM_IC_CaptureCallback>
- 800350e: e005 b.n 800351c <HAL_TIM_IRQHandler+0xaa>
+ 8003584: 6878 ldr r0, [r7, #4]
+ 8003586: f000 faad bl 8003ae4 <HAL_TIM_IC_CaptureCallback>
+ 800358a: e005 b.n 8003598 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003510: 6878 ldr r0, [r7, #4]
- 8003512: f000 fa9f bl 8003a54 <HAL_TIM_OC_DelayElapsedCallback>
+ 800358c: 6878 ldr r0, [r7, #4]
+ 800358e: f000 fa9f bl 8003ad0 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8003516: 6878 ldr r0, [r7, #4]
- 8003518: f000 fab0 bl 8003a7c <HAL_TIM_PWM_PulseFinishedCallback>
+ 8003592: 6878 ldr r0, [r7, #4]
+ 8003594: f000 fab0 bl 8003af8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 800351c: 687b ldr r3, [r7, #4]
- 800351e: 2200 movs r2, #0
- 8003520: 771a strb r2, [r3, #28]
+ 8003598: 687b ldr r3, [r7, #4]
+ 800359a: 2200 movs r2, #0
+ 800359c: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- 8003522: 687b ldr r3, [r7, #4]
- 8003524: 681b ldr r3, [r3, #0]
- 8003526: 691b ldr r3, [r3, #16]
- 8003528: f003 0308 and.w r3, r3, #8
- 800352c: 2b08 cmp r3, #8
- 800352e: d122 bne.n 8003576 <HAL_TIM_IRQHandler+0x104>
+ 800359e: 687b ldr r3, [r7, #4]
+ 80035a0: 681b ldr r3, [r3, #0]
+ 80035a2: 691b ldr r3, [r3, #16]
+ 80035a4: f003 0308 and.w r3, r3, #8
+ 80035a8: 2b08 cmp r3, #8
+ 80035aa: d122 bne.n 80035f2 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- 8003530: 687b ldr r3, [r7, #4]
- 8003532: 681b ldr r3, [r3, #0]
- 8003534: 68db ldr r3, [r3, #12]
- 8003536: f003 0308 and.w r3, r3, #8
- 800353a: 2b08 cmp r3, #8
- 800353c: d11b bne.n 8003576 <HAL_TIM_IRQHandler+0x104>
+ 80035ac: 687b ldr r3, [r7, #4]
+ 80035ae: 681b ldr r3, [r3, #0]
+ 80035b0: 68db ldr r3, [r3, #12]
+ 80035b2: f003 0308 and.w r3, r3, #8
+ 80035b6: 2b08 cmp r3, #8
+ 80035b8: d11b bne.n 80035f2 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- 800353e: 687b ldr r3, [r7, #4]
- 8003540: 681b ldr r3, [r3, #0]
- 8003542: f06f 0208 mvn.w r2, #8
- 8003546: 611a str r2, [r3, #16]
+ 80035ba: 687b ldr r3, [r7, #4]
+ 80035bc: 681b ldr r3, [r3, #0]
+ 80035be: f06f 0208 mvn.w r2, #8
+ 80035c2: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- 8003548: 687b ldr r3, [r7, #4]
- 800354a: 2204 movs r2, #4
- 800354c: 771a strb r2, [r3, #28]
+ 80035c4: 687b ldr r3, [r7, #4]
+ 80035c6: 2204 movs r2, #4
+ 80035c8: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- 800354e: 687b ldr r3, [r7, #4]
- 8003550: 681b ldr r3, [r3, #0]
- 8003552: 69db ldr r3, [r3, #28]
- 8003554: f003 0303 and.w r3, r3, #3
- 8003558: 2b00 cmp r3, #0
- 800355a: d003 beq.n 8003564 <HAL_TIM_IRQHandler+0xf2>
+ 80035ca: 687b ldr r3, [r7, #4]
+ 80035cc: 681b ldr r3, [r3, #0]
+ 80035ce: 69db ldr r3, [r3, #28]
+ 80035d0: f003 0303 and.w r3, r3, #3
+ 80035d4: 2b00 cmp r3, #0
+ 80035d6: d003 beq.n 80035e0 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
- 800355c: 6878 ldr r0, [r7, #4]
- 800355e: f000 fa83 bl 8003a68 <HAL_TIM_IC_CaptureCallback>
- 8003562: e005 b.n 8003570 <HAL_TIM_IRQHandler+0xfe>
+ 80035d8: 6878 ldr r0, [r7, #4]
+ 80035da: f000 fa83 bl 8003ae4 <HAL_TIM_IC_CaptureCallback>
+ 80035de: e005 b.n 80035ec <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
- 8003564: 6878 ldr r0, [r7, #4]
- 8003566: f000 fa75 bl 8003a54 <HAL_TIM_OC_DelayElapsedCallback>
+ 80035e0: 6878 ldr r0, [r7, #4]
+ 80035e2: f000 fa75 bl 8003ad0 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
- 800356a: 6878 ldr r0, [r7, #4]
- 800356c: f000 fa86 bl 8003a7c <HAL_TIM_PWM_PulseFinishedCallback>
+ 80035e6: 6878 ldr r0, [r7, #4]
+ 80035e8: f000 fa86 bl 8003af8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8003570: 687b ldr r3, [r7, #4]
- 8003572: 2200 movs r2, #0
- 8003574: 771a strb r2, [r3, #28]
+ 80035ec: 687b ldr r3, [r7, #4]
+ 80035ee: 2200 movs r2, #0
+ 80035f0: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- 8003576: 687b ldr r3, [r7, #4]
- 8003578: 681b ldr r3, [r3, #0]
- 800357a: 691b ldr r3, [r3, #16]
- 800357c: f003 0310 and.w r3, r3, #16
- 8003580: 2b10 cmp r3, #16
- 8003582: d122 bne.n 80035ca <HAL_TIM_IRQHandler+0x158>
+ 80035f2: 687b ldr r3, [r7, #4]
+ 80035f4: 681b ldr r3, [r3, #0]
+ 80035f6: 691b ldr r3, [r3, #16]
+ 80035f8: f003 0310 and.w r3, r3, #16
+ 80035fc: 2b10 cmp r3, #16
+ 80035fe: d122 bne.n 8003646 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- 8003584: 687b ldr r3, [r7, #4]
- 8003586: 681b ldr r3, [r3, #0]
- 8003588: 68db ldr r3, [r3, #12]
- 800358a: f003 0310 and.w r3, r3, #16
- 800358e: 2b10 cmp r3, #16
- 8003590: d11b bne.n 80035ca <HAL_TIM_IRQHandler+0x158>
+ 8003600: 687b ldr r3, [r7, #4]
+ 8003602: 681b ldr r3, [r3, #0]
+ 8003604: 68db ldr r3, [r3, #12]
+ 8003606: f003 0310 and.w r3, r3, #16
+ 800360a: 2b10 cmp r3, #16
+ 800360c: d11b bne.n 8003646 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- 8003592: 687b ldr r3, [r7, #4]
- 8003594: 681b ldr r3, [r3, #0]
- 8003596: f06f 0210 mvn.w r2, #16
- 800359a: 611a str r2, [r3, #16]
+ 800360e: 687b ldr r3, [r7, #4]
+ 8003610: 681b ldr r3, [r3, #0]
+ 8003612: f06f 0210 mvn.w r2, #16
+ 8003616: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- 800359c: 687b ldr r3, [r7, #4]
- 800359e: 2208 movs r2, #8
- 80035a0: 771a strb r2, [r3, #28]
+ 8003618: 687b ldr r3, [r7, #4]
+ 800361a: 2208 movs r2, #8
+ 800361c: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- 80035a2: 687b ldr r3, [r7, #4]
- 80035a4: 681b ldr r3, [r3, #0]
- 80035a6: 69db ldr r3, [r3, #28]
- 80035a8: f403 7340 and.w r3, r3, #768 ; 0x300
- 80035ac: 2b00 cmp r3, #0
- 80035ae: d003 beq.n 80035b8 <HAL_TIM_IRQHandler+0x146>
+ 800361e: 687b ldr r3, [r7, #4]
+ 8003620: 681b ldr r3, [r3, #0]
+ 8003622: 69db ldr r3, [r3, #28]
+ 8003624: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8003628: 2b00 cmp r3, #0
+ 800362a: d003 beq.n 8003634 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
- 80035b0: 6878 ldr r0, [r7, #4]
- 80035b2: f000 fa59 bl 8003a68 <HAL_TIM_IC_CaptureCallback>
- 80035b6: e005 b.n 80035c4 <HAL_TIM_IRQHandler+0x152>
+ 800362c: 6878 ldr r0, [r7, #4]
+ 800362e: f000 fa59 bl 8003ae4 <HAL_TIM_IC_CaptureCallback>
+ 8003632: e005 b.n 8003640 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
- 80035b8: 6878 ldr r0, [r7, #4]
- 80035ba: f000 fa4b bl 8003a54 <HAL_TIM_OC_DelayElapsedCallback>
+ 8003634: 6878 ldr r0, [r7, #4]
+ 8003636: f000 fa4b bl 8003ad0 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80035be: 6878 ldr r0, [r7, #4]
- 80035c0: f000 fa5c bl 8003a7c <HAL_TIM_PWM_PulseFinishedCallback>
+ 800363a: 6878 ldr r0, [r7, #4]
+ 800363c: f000 fa5c bl 8003af8 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80035c4: 687b ldr r3, [r7, #4]
- 80035c6: 2200 movs r2, #0
- 80035c8: 771a strb r2, [r3, #28]
+ 8003640: 687b ldr r3, [r7, #4]
+ 8003642: 2200 movs r2, #0
+ 8003644: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- 80035ca: 687b ldr r3, [r7, #4]
- 80035cc: 681b ldr r3, [r3, #0]
- 80035ce: 691b ldr r3, [r3, #16]
- 80035d0: f003 0301 and.w r3, r3, #1
- 80035d4: 2b01 cmp r3, #1
- 80035d6: d10e bne.n 80035f6 <HAL_TIM_IRQHandler+0x184>
+ 8003646: 687b ldr r3, [r7, #4]
+ 8003648: 681b ldr r3, [r3, #0]
+ 800364a: 691b ldr r3, [r3, #16]
+ 800364c: f003 0301 and.w r3, r3, #1
+ 8003650: 2b01 cmp r3, #1
+ 8003652: d10e bne.n 8003672 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- 80035d8: 687b ldr r3, [r7, #4]
- 80035da: 681b ldr r3, [r3, #0]
- 80035dc: 68db ldr r3, [r3, #12]
- 80035de: f003 0301 and.w r3, r3, #1
- 80035e2: 2b01 cmp r3, #1
- 80035e4: d107 bne.n 80035f6 <HAL_TIM_IRQHandler+0x184>
+ 8003654: 687b ldr r3, [r7, #4]
+ 8003656: 681b ldr r3, [r3, #0]
+ 8003658: 68db ldr r3, [r3, #12]
+ 800365a: f003 0301 and.w r3, r3, #1
+ 800365e: 2b01 cmp r3, #1
+ 8003660: d107 bne.n 8003672 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- 80035e6: 687b ldr r3, [r7, #4]
- 80035e8: 681b ldr r3, [r3, #0]
- 80035ea: f06f 0201 mvn.w r2, #1
- 80035ee: 611a str r2, [r3, #16]
+ 8003662: 687b ldr r3, [r7, #4]
+ 8003664: 681b ldr r3, [r3, #0]
+ 8003666: f06f 0201 mvn.w r2, #1
+ 800366a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
- 80035f0: 6878 ldr r0, [r7, #4]
- 80035f2: f7fd fe6b bl 80012cc <HAL_TIM_PeriodElapsedCallback>
+ 800366c: 6878 ldr r0, [r7, #4]
+ 800366e: f7fd fe3b bl 80012e8 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- 80035f6: 687b ldr r3, [r7, #4]
- 80035f8: 681b ldr r3, [r3, #0]
- 80035fa: 691b ldr r3, [r3, #16]
- 80035fc: f003 0380 and.w r3, r3, #128 ; 0x80
- 8003600: 2b80 cmp r3, #128 ; 0x80
- 8003602: d10e bne.n 8003622 <HAL_TIM_IRQHandler+0x1b0>
+ 8003672: 687b ldr r3, [r7, #4]
+ 8003674: 681b ldr r3, [r3, #0]
+ 8003676: 691b ldr r3, [r3, #16]
+ 8003678: f003 0380 and.w r3, r3, #128 ; 0x80
+ 800367c: 2b80 cmp r3, #128 ; 0x80
+ 800367e: d10e bne.n 800369e <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 8003604: 687b ldr r3, [r7, #4]
- 8003606: 681b ldr r3, [r3, #0]
- 8003608: 68db ldr r3, [r3, #12]
- 800360a: f003 0380 and.w r3, r3, #128 ; 0x80
- 800360e: 2b80 cmp r3, #128 ; 0x80
- 8003610: d107 bne.n 8003622 <HAL_TIM_IRQHandler+0x1b0>
+ 8003680: 687b ldr r3, [r7, #4]
+ 8003682: 681b ldr r3, [r3, #0]
+ 8003684: 68db ldr r3, [r3, #12]
+ 8003686: f003 0380 and.w r3, r3, #128 ; 0x80
+ 800368a: 2b80 cmp r3, #128 ; 0x80
+ 800368c: d107 bne.n 800369e <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- 8003612: 687b ldr r3, [r7, #4]
- 8003614: 681b ldr r3, [r3, #0]
- 8003616: f06f 0280 mvn.w r2, #128 ; 0x80
- 800361a: 611a str r2, [r3, #16]
+ 800368e: 687b ldr r3, [r7, #4]
+ 8003690: 681b ldr r3, [r3, #0]
+ 8003692: f06f 0280 mvn.w r2, #128 ; 0x80
+ 8003696: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
- 800361c: 6878 ldr r0, [r7, #4]
- 800361e: f000 fe65 bl 80042ec <HAL_TIMEx_BreakCallback>
+ 8003698: 6878 ldr r0, [r7, #4]
+ 800369a: f000 fe65 bl 8004368 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- 8003622: 687b ldr r3, [r7, #4]
- 8003624: 681b ldr r3, [r3, #0]
- 8003626: 691b ldr r3, [r3, #16]
- 8003628: f403 7380 and.w r3, r3, #256 ; 0x100
- 800362c: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8003630: d10e bne.n 8003650 <HAL_TIM_IRQHandler+0x1de>
+ 800369e: 687b ldr r3, [r7, #4]
+ 80036a0: 681b ldr r3, [r3, #0]
+ 80036a2: 691b ldr r3, [r3, #16]
+ 80036a4: f403 7380 and.w r3, r3, #256 ; 0x100
+ 80036a8: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 80036ac: d10e bne.n 80036cc <HAL_TIM_IRQHandler+0x1de>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 8003632: 687b ldr r3, [r7, #4]
- 8003634: 681b ldr r3, [r3, #0]
- 8003636: 68db ldr r3, [r3, #12]
- 8003638: f003 0380 and.w r3, r3, #128 ; 0x80
- 800363c: 2b80 cmp r3, #128 ; 0x80
- 800363e: d107 bne.n 8003650 <HAL_TIM_IRQHandler+0x1de>
+ 80036ae: 687b ldr r3, [r7, #4]
+ 80036b0: 681b ldr r3, [r3, #0]
+ 80036b2: 68db ldr r3, [r3, #12]
+ 80036b4: f003 0380 and.w r3, r3, #128 ; 0x80
+ 80036b8: 2b80 cmp r3, #128 ; 0x80
+ 80036ba: d107 bne.n 80036cc <HAL_TIM_IRQHandler+0x1de>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- 8003640: 687b ldr r3, [r7, #4]
- 8003642: 681b ldr r3, [r3, #0]
- 8003644: f46f 7280 mvn.w r2, #256 ; 0x100
- 8003648: 611a str r2, [r3, #16]
+ 80036bc: 687b ldr r3, [r7, #4]
+ 80036be: 681b ldr r3, [r3, #0]
+ 80036c0: f46f 7280 mvn.w r2, #256 ; 0x100
+ 80036c4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
- 800364a: 6878 ldr r0, [r7, #4]
- 800364c: f000 fe58 bl 8004300 <HAL_TIMEx_Break2Callback>
+ 80036c6: 6878 ldr r0, [r7, #4]
+ 80036c8: f000 fe58 bl 800437c <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- 8003650: 687b ldr r3, [r7, #4]
- 8003652: 681b ldr r3, [r3, #0]
- 8003654: 691b ldr r3, [r3, #16]
- 8003656: f003 0340 and.w r3, r3, #64 ; 0x40
- 800365a: 2b40 cmp r3, #64 ; 0x40
- 800365c: d10e bne.n 800367c <HAL_TIM_IRQHandler+0x20a>
+ 80036cc: 687b ldr r3, [r7, #4]
+ 80036ce: 681b ldr r3, [r3, #0]
+ 80036d0: 691b ldr r3, [r3, #16]
+ 80036d2: f003 0340 and.w r3, r3, #64 ; 0x40
+ 80036d6: 2b40 cmp r3, #64 ; 0x40
+ 80036d8: d10e bne.n 80036f8 <HAL_TIM_IRQHandler+0x20a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- 800365e: 687b ldr r3, [r7, #4]
- 8003660: 681b ldr r3, [r3, #0]
- 8003662: 68db ldr r3, [r3, #12]
- 8003664: f003 0340 and.w r3, r3, #64 ; 0x40
- 8003668: 2b40 cmp r3, #64 ; 0x40
- 800366a: d107 bne.n 800367c <HAL_TIM_IRQHandler+0x20a>
+ 80036da: 687b ldr r3, [r7, #4]
+ 80036dc: 681b ldr r3, [r3, #0]
+ 80036de: 68db ldr r3, [r3, #12]
+ 80036e0: f003 0340 and.w r3, r3, #64 ; 0x40
+ 80036e4: 2b40 cmp r3, #64 ; 0x40
+ 80036e6: d107 bne.n 80036f8 <HAL_TIM_IRQHandler+0x20a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- 800366c: 687b ldr r3, [r7, #4]
- 800366e: 681b ldr r3, [r3, #0]
- 8003670: f06f 0240 mvn.w r2, #64 ; 0x40
- 8003674: 611a str r2, [r3, #16]
+ 80036e8: 687b ldr r3, [r7, #4]
+ 80036ea: 681b ldr r3, [r3, #0]
+ 80036ec: f06f 0240 mvn.w r2, #64 ; 0x40
+ 80036f0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
- 8003676: 6878 ldr r0, [r7, #4]
- 8003678: f000 fa0a bl 8003a90 <HAL_TIM_TriggerCallback>
+ 80036f2: 6878 ldr r0, [r7, #4]
+ 80036f4: f000 fa0a bl 8003b0c <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- 800367c: 687b ldr r3, [r7, #4]
- 800367e: 681b ldr r3, [r3, #0]
- 8003680: 691b ldr r3, [r3, #16]
- 8003682: f003 0320 and.w r3, r3, #32
- 8003686: 2b20 cmp r3, #32
- 8003688: d10e bne.n 80036a8 <HAL_TIM_IRQHandler+0x236>
+ 80036f8: 687b ldr r3, [r7, #4]
+ 80036fa: 681b ldr r3, [r3, #0]
+ 80036fc: 691b ldr r3, [r3, #16]
+ 80036fe: f003 0320 and.w r3, r3, #32
+ 8003702: 2b20 cmp r3, #32
+ 8003704: d10e bne.n 8003724 <HAL_TIM_IRQHandler+0x236>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- 800368a: 687b ldr r3, [r7, #4]
- 800368c: 681b ldr r3, [r3, #0]
- 800368e: 68db ldr r3, [r3, #12]
- 8003690: f003 0320 and.w r3, r3, #32
- 8003694: 2b20 cmp r3, #32
- 8003696: d107 bne.n 80036a8 <HAL_TIM_IRQHandler+0x236>
+ 8003706: 687b ldr r3, [r7, #4]
+ 8003708: 681b ldr r3, [r3, #0]
+ 800370a: 68db ldr r3, [r3, #12]
+ 800370c: f003 0320 and.w r3, r3, #32
+ 8003710: 2b20 cmp r3, #32
+ 8003712: d107 bne.n 8003724 <HAL_TIM_IRQHandler+0x236>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- 8003698: 687b ldr r3, [r7, #4]
- 800369a: 681b ldr r3, [r3, #0]
- 800369c: f06f 0220 mvn.w r2, #32
- 80036a0: 611a str r2, [r3, #16]
+ 8003714: 687b ldr r3, [r7, #4]
+ 8003716: 681b ldr r3, [r3, #0]
+ 8003718: f06f 0220 mvn.w r2, #32
+ 800371c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
- 80036a2: 6878 ldr r0, [r7, #4]
- 80036a4: f000 fe18 bl 80042d8 <HAL_TIMEx_CommutCallback>
+ 800371e: 6878 ldr r0, [r7, #4]
+ 8003720: f000 fe18 bl 8004354 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
- 80036a8: bf00 nop
- 80036aa: 3708 adds r7, #8
- 80036ac: 46bd mov sp, r7
- 80036ae: bd80 pop {r7, pc}
+ 8003724: bf00 nop
+ 8003726: 3708 adds r7, #8
+ 8003728: 46bd mov sp, r7
+ 800372a: bd80 pop {r7, pc}
-080036b0 <HAL_TIM_PWM_ConfigChannel>:
+0800372c <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
- 80036b0: b580 push {r7, lr}
- 80036b2: b084 sub sp, #16
- 80036b4: af00 add r7, sp, #0
- 80036b6: 60f8 str r0, [r7, #12]
- 80036b8: 60b9 str r1, [r7, #8]
- 80036ba: 607a str r2, [r7, #4]
+ 800372c: b580 push {r7, lr}
+ 800372e: b084 sub sp, #16
+ 8003730: af00 add r7, sp, #0
+ 8003732: 60f8 str r0, [r7, #12]
+ 8003734: 60b9 str r1, [r7, #8]
+ 8003736: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
- 80036bc: 68fb ldr r3, [r7, #12]
- 80036be: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 80036c2: 2b01 cmp r3, #1
- 80036c4: d101 bne.n 80036ca <HAL_TIM_PWM_ConfigChannel+0x1a>
- 80036c6: 2302 movs r3, #2
- 80036c8: e105 b.n 80038d6 <HAL_TIM_PWM_ConfigChannel+0x226>
- 80036ca: 68fb ldr r3, [r7, #12]
- 80036cc: 2201 movs r2, #1
- 80036ce: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8003738: 68fb ldr r3, [r7, #12]
+ 800373a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 800373e: 2b01 cmp r3, #1
+ 8003740: d101 bne.n 8003746 <HAL_TIM_PWM_ConfigChannel+0x1a>
+ 8003742: 2302 movs r3, #2
+ 8003744: e105 b.n 8003952 <HAL_TIM_PWM_ConfigChannel+0x226>
+ 8003746: 68fb ldr r3, [r7, #12]
+ 8003748: 2201 movs r2, #1
+ 800374a: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
- 80036d2: 68fb ldr r3, [r7, #12]
- 80036d4: 2202 movs r2, #2
- 80036d6: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 800374e: 68fb ldr r3, [r7, #12]
+ 8003750: 2202 movs r2, #2
+ 8003752: f883 203d strb.w r2, [r3, #61] ; 0x3d
switch (Channel)
- 80036da: 687b ldr r3, [r7, #4]
- 80036dc: 2b14 cmp r3, #20
- 80036de: f200 80f0 bhi.w 80038c2 <HAL_TIM_PWM_ConfigChannel+0x212>
- 80036e2: a201 add r2, pc, #4 ; (adr r2, 80036e8 <HAL_TIM_PWM_ConfigChannel+0x38>)
- 80036e4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 80036e8: 0800373d .word 0x0800373d
- 80036ec: 080038c3 .word 0x080038c3
- 80036f0: 080038c3 .word 0x080038c3
- 80036f4: 080038c3 .word 0x080038c3
- 80036f8: 0800377d .word 0x0800377d
- 80036fc: 080038c3 .word 0x080038c3
- 8003700: 080038c3 .word 0x080038c3
- 8003704: 080038c3 .word 0x080038c3
- 8003708: 080037bf .word 0x080037bf
- 800370c: 080038c3 .word 0x080038c3
- 8003710: 080038c3 .word 0x080038c3
- 8003714: 080038c3 .word 0x080038c3
- 8003718: 080037ff .word 0x080037ff
- 800371c: 080038c3 .word 0x080038c3
- 8003720: 080038c3 .word 0x080038c3
- 8003724: 080038c3 .word 0x080038c3
- 8003728: 08003841 .word 0x08003841
- 800372c: 080038c3 .word 0x080038c3
- 8003730: 080038c3 .word 0x080038c3
- 8003734: 080038c3 .word 0x080038c3
- 8003738: 08003881 .word 0x08003881
+ 8003756: 687b ldr r3, [r7, #4]
+ 8003758: 2b14 cmp r3, #20
+ 800375a: f200 80f0 bhi.w 800393e <HAL_TIM_PWM_ConfigChannel+0x212>
+ 800375e: a201 add r2, pc, #4 ; (adr r2, 8003764 <HAL_TIM_PWM_ConfigChannel+0x38>)
+ 8003760: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 8003764: 080037b9 .word 0x080037b9
+ 8003768: 0800393f .word 0x0800393f
+ 800376c: 0800393f .word 0x0800393f
+ 8003770: 0800393f .word 0x0800393f
+ 8003774: 080037f9 .word 0x080037f9
+ 8003778: 0800393f .word 0x0800393f
+ 800377c: 0800393f .word 0x0800393f
+ 8003780: 0800393f .word 0x0800393f
+ 8003784: 0800383b .word 0x0800383b
+ 8003788: 0800393f .word 0x0800393f
+ 800378c: 0800393f .word 0x0800393f
+ 8003790: 0800393f .word 0x0800393f
+ 8003794: 0800387b .word 0x0800387b
+ 8003798: 0800393f .word 0x0800393f
+ 800379c: 0800393f .word 0x0800393f
+ 80037a0: 0800393f .word 0x0800393f
+ 80037a4: 080038bd .word 0x080038bd
+ 80037a8: 0800393f .word 0x0800393f
+ 80037ac: 0800393f .word 0x0800393f
+ 80037b0: 0800393f .word 0x0800393f
+ 80037b4: 080038fd .word 0x080038fd
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
- 800373c: 68fb ldr r3, [r7, #12]
- 800373e: 681b ldr r3, [r3, #0]
- 8003740: 68b9 ldr r1, [r7, #8]
- 8003742: 4618 mov r0, r3
- 8003744: f000 fa4e bl 8003be4 <TIM_OC1_SetConfig>
+ 80037b8: 68fb ldr r3, [r7, #12]
+ 80037ba: 681b ldr r3, [r3, #0]
+ 80037bc: 68b9 ldr r1, [r7, #8]
+ 80037be: 4618 mov r0, r3
+ 80037c0: f000 fa4e bl 8003c60 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 8003748: 68fb ldr r3, [r7, #12]
- 800374a: 681b ldr r3, [r3, #0]
- 800374c: 699a ldr r2, [r3, #24]
- 800374e: 68fb ldr r3, [r7, #12]
- 8003750: 681b ldr r3, [r3, #0]
- 8003752: f042 0208 orr.w r2, r2, #8
- 8003756: 619a str r2, [r3, #24]
+ 80037c4: 68fb ldr r3, [r7, #12]
+ 80037c6: 681b ldr r3, [r3, #0]
+ 80037c8: 699a ldr r2, [r3, #24]
+ 80037ca: 68fb ldr r3, [r7, #12]
+ 80037cc: 681b ldr r3, [r3, #0]
+ 80037ce: f042 0208 orr.w r2, r2, #8
+ 80037d2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- 8003758: 68fb ldr r3, [r7, #12]
- 800375a: 681b ldr r3, [r3, #0]
- 800375c: 699a ldr r2, [r3, #24]
- 800375e: 68fb ldr r3, [r7, #12]
- 8003760: 681b ldr r3, [r3, #0]
- 8003762: f022 0204 bic.w r2, r2, #4
- 8003766: 619a str r2, [r3, #24]
+ 80037d4: 68fb ldr r3, [r7, #12]
+ 80037d6: 681b ldr r3, [r3, #0]
+ 80037d8: 699a ldr r2, [r3, #24]
+ 80037da: 68fb ldr r3, [r7, #12]
+ 80037dc: 681b ldr r3, [r3, #0]
+ 80037de: f022 0204 bic.w r2, r2, #4
+ 80037e2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
- 8003768: 68fb ldr r3, [r7, #12]
- 800376a: 681b ldr r3, [r3, #0]
- 800376c: 6999 ldr r1, [r3, #24]
- 800376e: 68bb ldr r3, [r7, #8]
- 8003770: 691a ldr r2, [r3, #16]
- 8003772: 68fb ldr r3, [r7, #12]
- 8003774: 681b ldr r3, [r3, #0]
- 8003776: 430a orrs r2, r1
- 8003778: 619a str r2, [r3, #24]
+ 80037e4: 68fb ldr r3, [r7, #12]
+ 80037e6: 681b ldr r3, [r3, #0]
+ 80037e8: 6999 ldr r1, [r3, #24]
+ 80037ea: 68bb ldr r3, [r7, #8]
+ 80037ec: 691a ldr r2, [r3, #16]
+ 80037ee: 68fb ldr r3, [r7, #12]
+ 80037f0: 681b ldr r3, [r3, #0]
+ 80037f2: 430a orrs r2, r1
+ 80037f4: 619a str r2, [r3, #24]
break;
- 800377a: e0a3 b.n 80038c4 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 80037f6: e0a3 b.n 8003940 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
- 800377c: 68fb ldr r3, [r7, #12]
- 800377e: 681b ldr r3, [r3, #0]
- 8003780: 68b9 ldr r1, [r7, #8]
- 8003782: 4618 mov r0, r3
- 8003784: f000 faa0 bl 8003cc8 <TIM_OC2_SetConfig>
+ 80037f8: 68fb ldr r3, [r7, #12]
+ 80037fa: 681b ldr r3, [r3, #0]
+ 80037fc: 68b9 ldr r1, [r7, #8]
+ 80037fe: 4618 mov r0, r3
+ 8003800: f000 faa0 bl 8003d44 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 8003788: 68fb ldr r3, [r7, #12]
- 800378a: 681b ldr r3, [r3, #0]
- 800378c: 699a ldr r2, [r3, #24]
- 800378e: 68fb ldr r3, [r7, #12]
- 8003790: 681b ldr r3, [r3, #0]
- 8003792: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003796: 619a str r2, [r3, #24]
+ 8003804: 68fb ldr r3, [r7, #12]
+ 8003806: 681b ldr r3, [r3, #0]
+ 8003808: 699a ldr r2, [r3, #24]
+ 800380a: 68fb ldr r3, [r7, #12]
+ 800380c: 681b ldr r3, [r3, #0]
+ 800380e: f442 6200 orr.w r2, r2, #2048 ; 0x800
+ 8003812: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 8003798: 68fb ldr r3, [r7, #12]
- 800379a: 681b ldr r3, [r3, #0]
- 800379c: 699a ldr r2, [r3, #24]
- 800379e: 68fb ldr r3, [r7, #12]
- 80037a0: 681b ldr r3, [r3, #0]
- 80037a2: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 80037a6: 619a str r2, [r3, #24]
+ 8003814: 68fb ldr r3, [r7, #12]
+ 8003816: 681b ldr r3, [r3, #0]
+ 8003818: 699a ldr r2, [r3, #24]
+ 800381a: 68fb ldr r3, [r7, #12]
+ 800381c: 681b ldr r3, [r3, #0]
+ 800381e: f422 6280 bic.w r2, r2, #1024 ; 0x400
+ 8003822: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- 80037a8: 68fb ldr r3, [r7, #12]
- 80037aa: 681b ldr r3, [r3, #0]
- 80037ac: 6999 ldr r1, [r3, #24]
- 80037ae: 68bb ldr r3, [r7, #8]
- 80037b0: 691b ldr r3, [r3, #16]
- 80037b2: 021a lsls r2, r3, #8
- 80037b4: 68fb ldr r3, [r7, #12]
- 80037b6: 681b ldr r3, [r3, #0]
- 80037b8: 430a orrs r2, r1
- 80037ba: 619a str r2, [r3, #24]
+ 8003824: 68fb ldr r3, [r7, #12]
+ 8003826: 681b ldr r3, [r3, #0]
+ 8003828: 6999 ldr r1, [r3, #24]
+ 800382a: 68bb ldr r3, [r7, #8]
+ 800382c: 691b ldr r3, [r3, #16]
+ 800382e: 021a lsls r2, r3, #8
+ 8003830: 68fb ldr r3, [r7, #12]
+ 8003832: 681b ldr r3, [r3, #0]
+ 8003834: 430a orrs r2, r1
+ 8003836: 619a str r2, [r3, #24]
break;
- 80037bc: e082 b.n 80038c4 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 8003838: e082 b.n 8003940 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
- 80037be: 68fb ldr r3, [r7, #12]
- 80037c0: 681b ldr r3, [r3, #0]
- 80037c2: 68b9 ldr r1, [r7, #8]
- 80037c4: 4618 mov r0, r3
- 80037c6: f000 faf7 bl 8003db8 <TIM_OC3_SetConfig>
+ 800383a: 68fb ldr r3, [r7, #12]
+ 800383c: 681b ldr r3, [r3, #0]
+ 800383e: 68b9 ldr r1, [r7, #8]
+ 8003840: 4618 mov r0, r3
+ 8003842: f000 faf7 bl 8003e34 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 80037ca: 68fb ldr r3, [r7, #12]
- 80037cc: 681b ldr r3, [r3, #0]
- 80037ce: 69da ldr r2, [r3, #28]
- 80037d0: 68fb ldr r3, [r7, #12]
- 80037d2: 681b ldr r3, [r3, #0]
- 80037d4: f042 0208 orr.w r2, r2, #8
- 80037d8: 61da str r2, [r3, #28]
+ 8003846: 68fb ldr r3, [r7, #12]
+ 8003848: 681b ldr r3, [r3, #0]
+ 800384a: 69da ldr r2, [r3, #28]
+ 800384c: 68fb ldr r3, [r7, #12]
+ 800384e: 681b ldr r3, [r3, #0]
+ 8003850: f042 0208 orr.w r2, r2, #8
+ 8003854: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- 80037da: 68fb ldr r3, [r7, #12]
- 80037dc: 681b ldr r3, [r3, #0]
- 80037de: 69da ldr r2, [r3, #28]
- 80037e0: 68fb ldr r3, [r7, #12]
- 80037e2: 681b ldr r3, [r3, #0]
- 80037e4: f022 0204 bic.w r2, r2, #4
- 80037e8: 61da str r2, [r3, #28]
+ 8003856: 68fb ldr r3, [r7, #12]
+ 8003858: 681b ldr r3, [r3, #0]
+ 800385a: 69da ldr r2, [r3, #28]
+ 800385c: 68fb ldr r3, [r7, #12]
+ 800385e: 681b ldr r3, [r3, #0]
+ 8003860: f022 0204 bic.w r2, r2, #4
+ 8003864: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
- 80037ea: 68fb ldr r3, [r7, #12]
- 80037ec: 681b ldr r3, [r3, #0]
- 80037ee: 69d9 ldr r1, [r3, #28]
- 80037f0: 68bb ldr r3, [r7, #8]
- 80037f2: 691a ldr r2, [r3, #16]
- 80037f4: 68fb ldr r3, [r7, #12]
- 80037f6: 681b ldr r3, [r3, #0]
- 80037f8: 430a orrs r2, r1
- 80037fa: 61da str r2, [r3, #28]
+ 8003866: 68fb ldr r3, [r7, #12]
+ 8003868: 681b ldr r3, [r3, #0]
+ 800386a: 69d9 ldr r1, [r3, #28]
+ 800386c: 68bb ldr r3, [r7, #8]
+ 800386e: 691a ldr r2, [r3, #16]
+ 8003870: 68fb ldr r3, [r7, #12]
+ 8003872: 681b ldr r3, [r3, #0]
+ 8003874: 430a orrs r2, r1
+ 8003876: 61da str r2, [r3, #28]
break;
- 80037fc: e062 b.n 80038c4 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 8003878: e062 b.n 8003940 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
- 80037fe: 68fb ldr r3, [r7, #12]
- 8003800: 681b ldr r3, [r3, #0]
- 8003802: 68b9 ldr r1, [r7, #8]
- 8003804: 4618 mov r0, r3
- 8003806: f000 fb4d bl 8003ea4 <TIM_OC4_SetConfig>
+ 800387a: 68fb ldr r3, [r7, #12]
+ 800387c: 681b ldr r3, [r3, #0]
+ 800387e: 68b9 ldr r1, [r7, #8]
+ 8003880: 4618 mov r0, r3
+ 8003882: f000 fb4d bl 8003f20 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 800380a: 68fb ldr r3, [r7, #12]
- 800380c: 681b ldr r3, [r3, #0]
- 800380e: 69da ldr r2, [r3, #28]
- 8003810: 68fb ldr r3, [r7, #12]
- 8003812: 681b ldr r3, [r3, #0]
- 8003814: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8003818: 61da str r2, [r3, #28]
+ 8003886: 68fb ldr r3, [r7, #12]
+ 8003888: 681b ldr r3, [r3, #0]
+ 800388a: 69da ldr r2, [r3, #28]
+ 800388c: 68fb ldr r3, [r7, #12]
+ 800388e: 681b ldr r3, [r3, #0]
+ 8003890: f442 6200 orr.w r2, r2, #2048 ; 0x800
+ 8003894: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 800381a: 68fb ldr r3, [r7, #12]
- 800381c: 681b ldr r3, [r3, #0]
- 800381e: 69da ldr r2, [r3, #28]
- 8003820: 68fb ldr r3, [r7, #12]
- 8003822: 681b ldr r3, [r3, #0]
- 8003824: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8003828: 61da str r2, [r3, #28]
+ 8003896: 68fb ldr r3, [r7, #12]
+ 8003898: 681b ldr r3, [r3, #0]
+ 800389a: 69da ldr r2, [r3, #28]
+ 800389c: 68fb ldr r3, [r7, #12]
+ 800389e: 681b ldr r3, [r3, #0]
+ 80038a0: f422 6280 bic.w r2, r2, #1024 ; 0x400
+ 80038a4: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- 800382a: 68fb ldr r3, [r7, #12]
- 800382c: 681b ldr r3, [r3, #0]
- 800382e: 69d9 ldr r1, [r3, #28]
- 8003830: 68bb ldr r3, [r7, #8]
- 8003832: 691b ldr r3, [r3, #16]
- 8003834: 021a lsls r2, r3, #8
- 8003836: 68fb ldr r3, [r7, #12]
- 8003838: 681b ldr r3, [r3, #0]
- 800383a: 430a orrs r2, r1
- 800383c: 61da str r2, [r3, #28]
+ 80038a6: 68fb ldr r3, [r7, #12]
+ 80038a8: 681b ldr r3, [r3, #0]
+ 80038aa: 69d9 ldr r1, [r3, #28]
+ 80038ac: 68bb ldr r3, [r7, #8]
+ 80038ae: 691b ldr r3, [r3, #16]
+ 80038b0: 021a lsls r2, r3, #8
+ 80038b2: 68fb ldr r3, [r7, #12]
+ 80038b4: 681b ldr r3, [r3, #0]
+ 80038b6: 430a orrs r2, r1
+ 80038b8: 61da str r2, [r3, #28]
break;
- 800383e: e041 b.n 80038c4 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 80038ba: e041 b.n 8003940 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
- 8003840: 68fb ldr r3, [r7, #12]
- 8003842: 681b ldr r3, [r3, #0]
- 8003844: 68b9 ldr r1, [r7, #8]
- 8003846: 4618 mov r0, r3
- 8003848: f000 fb84 bl 8003f54 <TIM_OC5_SetConfig>
+ 80038bc: 68fb ldr r3, [r7, #12]
+ 80038be: 681b ldr r3, [r3, #0]
+ 80038c0: 68b9 ldr r1, [r7, #8]
+ 80038c2: 4618 mov r0, r3
+ 80038c4: f000 fb84 bl 8003fd0 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
- 800384c: 68fb ldr r3, [r7, #12]
- 800384e: 681b ldr r3, [r3, #0]
- 8003850: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003852: 68fb ldr r3, [r7, #12]
- 8003854: 681b ldr r3, [r3, #0]
- 8003856: f042 0208 orr.w r2, r2, #8
- 800385a: 655a str r2, [r3, #84] ; 0x54
+ 80038c8: 68fb ldr r3, [r7, #12]
+ 80038ca: 681b ldr r3, [r3, #0]
+ 80038cc: 6d5a ldr r2, [r3, #84] ; 0x54
+ 80038ce: 68fb ldr r3, [r7, #12]
+ 80038d0: 681b ldr r3, [r3, #0]
+ 80038d2: f042 0208 orr.w r2, r2, #8
+ 80038d6: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- 800385c: 68fb ldr r3, [r7, #12]
- 800385e: 681b ldr r3, [r3, #0]
- 8003860: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003862: 68fb ldr r3, [r7, #12]
- 8003864: 681b ldr r3, [r3, #0]
- 8003866: f022 0204 bic.w r2, r2, #4
- 800386a: 655a str r2, [r3, #84] ; 0x54
+ 80038d8: 68fb ldr r3, [r7, #12]
+ 80038da: 681b ldr r3, [r3, #0]
+ 80038dc: 6d5a ldr r2, [r3, #84] ; 0x54
+ 80038de: 68fb ldr r3, [r7, #12]
+ 80038e0: 681b ldr r3, [r3, #0]
+ 80038e2: f022 0204 bic.w r2, r2, #4
+ 80038e6: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
- 800386c: 68fb ldr r3, [r7, #12]
- 800386e: 681b ldr r3, [r3, #0]
- 8003870: 6d59 ldr r1, [r3, #84] ; 0x54
- 8003872: 68bb ldr r3, [r7, #8]
- 8003874: 691a ldr r2, [r3, #16]
- 8003876: 68fb ldr r3, [r7, #12]
- 8003878: 681b ldr r3, [r3, #0]
- 800387a: 430a orrs r2, r1
- 800387c: 655a str r2, [r3, #84] ; 0x54
+ 80038e8: 68fb ldr r3, [r7, #12]
+ 80038ea: 681b ldr r3, [r3, #0]
+ 80038ec: 6d59 ldr r1, [r3, #84] ; 0x54
+ 80038ee: 68bb ldr r3, [r7, #8]
+ 80038f0: 691a ldr r2, [r3, #16]
+ 80038f2: 68fb ldr r3, [r7, #12]
+ 80038f4: 681b ldr r3, [r3, #0]
+ 80038f6: 430a orrs r2, r1
+ 80038f8: 655a str r2, [r3, #84] ; 0x54
break;
- 800387e: e021 b.n 80038c4 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 80038fa: e021 b.n 8003940 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
- 8003880: 68fb ldr r3, [r7, #12]
- 8003882: 681b ldr r3, [r3, #0]
- 8003884: 68b9 ldr r1, [r7, #8]
- 8003886: 4618 mov r0, r3
- 8003888: f000 fbb6 bl 8003ff8 <TIM_OC6_SetConfig>
+ 80038fc: 68fb ldr r3, [r7, #12]
+ 80038fe: 681b ldr r3, [r3, #0]
+ 8003900: 68b9 ldr r1, [r7, #8]
+ 8003902: 4618 mov r0, r3
+ 8003904: f000 fbb6 bl 8004074 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
- 800388c: 68fb ldr r3, [r7, #12]
- 800388e: 681b ldr r3, [r3, #0]
- 8003890: 6d5a ldr r2, [r3, #84] ; 0x54
- 8003892: 68fb ldr r3, [r7, #12]
- 8003894: 681b ldr r3, [r3, #0]
- 8003896: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 800389a: 655a str r2, [r3, #84] ; 0x54
+ 8003908: 68fb ldr r3, [r7, #12]
+ 800390a: 681b ldr r3, [r3, #0]
+ 800390c: 6d5a ldr r2, [r3, #84] ; 0x54
+ 800390e: 68fb ldr r3, [r7, #12]
+ 8003910: 681b ldr r3, [r3, #0]
+ 8003912: f442 6200 orr.w r2, r2, #2048 ; 0x800
+ 8003916: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- 800389c: 68fb ldr r3, [r7, #12]
- 800389e: 681b ldr r3, [r3, #0]
- 80038a0: 6d5a ldr r2, [r3, #84] ; 0x54
- 80038a2: 68fb ldr r3, [r7, #12]
- 80038a4: 681b ldr r3, [r3, #0]
- 80038a6: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 80038aa: 655a str r2, [r3, #84] ; 0x54
+ 8003918: 68fb ldr r3, [r7, #12]
+ 800391a: 681b ldr r3, [r3, #0]
+ 800391c: 6d5a ldr r2, [r3, #84] ; 0x54
+ 800391e: 68fb ldr r3, [r7, #12]
+ 8003920: 681b ldr r3, [r3, #0]
+ 8003922: f422 6280 bic.w r2, r2, #1024 ; 0x400
+ 8003926: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- 80038ac: 68fb ldr r3, [r7, #12]
- 80038ae: 681b ldr r3, [r3, #0]
- 80038b0: 6d59 ldr r1, [r3, #84] ; 0x54
- 80038b2: 68bb ldr r3, [r7, #8]
- 80038b4: 691b ldr r3, [r3, #16]
- 80038b6: 021a lsls r2, r3, #8
- 80038b8: 68fb ldr r3, [r7, #12]
- 80038ba: 681b ldr r3, [r3, #0]
- 80038bc: 430a orrs r2, r1
- 80038be: 655a str r2, [r3, #84] ; 0x54
+ 8003928: 68fb ldr r3, [r7, #12]
+ 800392a: 681b ldr r3, [r3, #0]
+ 800392c: 6d59 ldr r1, [r3, #84] ; 0x54
+ 800392e: 68bb ldr r3, [r7, #8]
+ 8003930: 691b ldr r3, [r3, #16]
+ 8003932: 021a lsls r2, r3, #8
+ 8003934: 68fb ldr r3, [r7, #12]
+ 8003936: 681b ldr r3, [r3, #0]
+ 8003938: 430a orrs r2, r1
+ 800393a: 655a str r2, [r3, #84] ; 0x54
break;
- 80038c0: e000 b.n 80038c4 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 800393c: e000 b.n 8003940 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
break;
- 80038c2: bf00 nop
+ 800393e: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
- 80038c4: 68fb ldr r3, [r7, #12]
- 80038c6: 2201 movs r2, #1
- 80038c8: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8003940: 68fb ldr r3, [r7, #12]
+ 8003942: 2201 movs r2, #1
+ 8003944: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
- 80038cc: 68fb ldr r3, [r7, #12]
- 80038ce: 2200 movs r2, #0
- 80038d0: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8003948: 68fb ldr r3, [r7, #12]
+ 800394a: 2200 movs r2, #0
+ 800394c: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
- 80038d4: 2300 movs r3, #0
+ 8003950: 2300 movs r3, #0
}
- 80038d6: 4618 mov r0, r3
- 80038d8: 3710 adds r7, #16
- 80038da: 46bd mov sp, r7
- 80038dc: bd80 pop {r7, pc}
- 80038de: bf00 nop
+ 8003952: 4618 mov r0, r3
+ 8003954: 3710 adds r7, #16
+ 8003956: 46bd mov sp, r7
+ 8003958: bd80 pop {r7, pc}
+ 800395a: bf00 nop
-080038e0 <HAL_TIM_ConfigClockSource>:
+0800395c <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
- 80038e0: b580 push {r7, lr}
- 80038e2: b084 sub sp, #16
- 80038e4: af00 add r7, sp, #0
- 80038e6: 6078 str r0, [r7, #4]
- 80038e8: 6039 str r1, [r7, #0]
+ 800395c: b580 push {r7, lr}
+ 800395e: b084 sub sp, #16
+ 8003960: af00 add r7, sp, #0
+ 8003962: 6078 str r0, [r7, #4]
+ 8003964: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
- 80038ea: 687b ldr r3, [r7, #4]
- 80038ec: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 80038f0: 2b01 cmp r3, #1
- 80038f2: d101 bne.n 80038f8 <HAL_TIM_ConfigClockSource+0x18>
- 80038f4: 2302 movs r3, #2
- 80038f6: e0a6 b.n 8003a46 <HAL_TIM_ConfigClockSource+0x166>
- 80038f8: 687b ldr r3, [r7, #4]
- 80038fa: 2201 movs r2, #1
- 80038fc: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8003966: 687b ldr r3, [r7, #4]
+ 8003968: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 800396c: 2b01 cmp r3, #1
+ 800396e: d101 bne.n 8003974 <HAL_TIM_ConfigClockSource+0x18>
+ 8003970: 2302 movs r3, #2
+ 8003972: e0a6 b.n 8003ac2 <HAL_TIM_ConfigClockSource+0x166>
+ 8003974: 687b ldr r3, [r7, #4]
+ 8003976: 2201 movs r2, #1
+ 8003978: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
- 8003900: 687b ldr r3, [r7, #4]
- 8003902: 2202 movs r2, #2
- 8003904: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 800397c: 687b ldr r3, [r7, #4]
+ 800397e: 2202 movs r2, #2
+ 8003980: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
- 8003908: 687b ldr r3, [r7, #4]
- 800390a: 681b ldr r3, [r3, #0]
- 800390c: 689b ldr r3, [r3, #8]
- 800390e: 60fb str r3, [r7, #12]
+ 8003984: 687b ldr r3, [r7, #4]
+ 8003986: 681b ldr r3, [r3, #0]
+ 8003988: 689b ldr r3, [r3, #8]
+ 800398a: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 8003910: 68fa ldr r2, [r7, #12]
- 8003912: 4b4f ldr r3, [pc, #316] ; (8003a50 <HAL_TIM_ConfigClockSource+0x170>)
- 8003914: 4013 ands r3, r2
- 8003916: 60fb str r3, [r7, #12]
+ 800398c: 68fa ldr r2, [r7, #12]
+ 800398e: 4b4f ldr r3, [pc, #316] ; (8003acc <HAL_TIM_ConfigClockSource+0x170>)
+ 8003990: 4013 ands r3, r2
+ 8003992: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8003918: 68fb ldr r3, [r7, #12]
- 800391a: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 800391e: 60fb str r3, [r7, #12]
+ 8003994: 68fb ldr r3, [r7, #12]
+ 8003996: f423 437f bic.w r3, r3, #65280 ; 0xff00
+ 800399a: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
- 8003920: 687b ldr r3, [r7, #4]
- 8003922: 681b ldr r3, [r3, #0]
- 8003924: 68fa ldr r2, [r7, #12]
- 8003926: 609a str r2, [r3, #8]
+ 800399c: 687b ldr r3, [r7, #4]
+ 800399e: 681b ldr r3, [r3, #0]
+ 80039a0: 68fa ldr r2, [r7, #12]
+ 80039a2: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
- 8003928: 683b ldr r3, [r7, #0]
- 800392a: 681b ldr r3, [r3, #0]
- 800392c: 2b40 cmp r3, #64 ; 0x40
- 800392e: d067 beq.n 8003a00 <HAL_TIM_ConfigClockSource+0x120>
- 8003930: 2b40 cmp r3, #64 ; 0x40
- 8003932: d80b bhi.n 800394c <HAL_TIM_ConfigClockSource+0x6c>
- 8003934: 2b10 cmp r3, #16
- 8003936: d073 beq.n 8003a20 <HAL_TIM_ConfigClockSource+0x140>
- 8003938: 2b10 cmp r3, #16
- 800393a: d802 bhi.n 8003942 <HAL_TIM_ConfigClockSource+0x62>
- 800393c: 2b00 cmp r3, #0
- 800393e: d06f beq.n 8003a20 <HAL_TIM_ConfigClockSource+0x140>
+ 80039a4: 683b ldr r3, [r7, #0]
+ 80039a6: 681b ldr r3, [r3, #0]
+ 80039a8: 2b40 cmp r3, #64 ; 0x40
+ 80039aa: d067 beq.n 8003a7c <HAL_TIM_ConfigClockSource+0x120>
+ 80039ac: 2b40 cmp r3, #64 ; 0x40
+ 80039ae: d80b bhi.n 80039c8 <HAL_TIM_ConfigClockSource+0x6c>
+ 80039b0: 2b10 cmp r3, #16
+ 80039b2: d073 beq.n 8003a9c <HAL_TIM_ConfigClockSource+0x140>
+ 80039b4: 2b10 cmp r3, #16
+ 80039b6: d802 bhi.n 80039be <HAL_TIM_ConfigClockSource+0x62>
+ 80039b8: 2b00 cmp r3, #0
+ 80039ba: d06f beq.n 8003a9c <HAL_TIM_ConfigClockSource+0x140>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
- 8003940: e078 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 80039bc: e078 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
- 8003942: 2b20 cmp r3, #32
- 8003944: d06c beq.n 8003a20 <HAL_TIM_ConfigClockSource+0x140>
- 8003946: 2b30 cmp r3, #48 ; 0x30
- 8003948: d06a beq.n 8003a20 <HAL_TIM_ConfigClockSource+0x140>
+ 80039be: 2b20 cmp r3, #32
+ 80039c0: d06c beq.n 8003a9c <HAL_TIM_ConfigClockSource+0x140>
+ 80039c2: 2b30 cmp r3, #48 ; 0x30
+ 80039c4: d06a beq.n 8003a9c <HAL_TIM_ConfigClockSource+0x140>
break;
- 800394a: e073 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 80039c6: e073 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
- 800394c: 2b70 cmp r3, #112 ; 0x70
- 800394e: d00d beq.n 800396c <HAL_TIM_ConfigClockSource+0x8c>
- 8003950: 2b70 cmp r3, #112 ; 0x70
- 8003952: d804 bhi.n 800395e <HAL_TIM_ConfigClockSource+0x7e>
- 8003954: 2b50 cmp r3, #80 ; 0x50
- 8003956: d033 beq.n 80039c0 <HAL_TIM_ConfigClockSource+0xe0>
- 8003958: 2b60 cmp r3, #96 ; 0x60
- 800395a: d041 beq.n 80039e0 <HAL_TIM_ConfigClockSource+0x100>
+ 80039c8: 2b70 cmp r3, #112 ; 0x70
+ 80039ca: d00d beq.n 80039e8 <HAL_TIM_ConfigClockSource+0x8c>
+ 80039cc: 2b70 cmp r3, #112 ; 0x70
+ 80039ce: d804 bhi.n 80039da <HAL_TIM_ConfigClockSource+0x7e>
+ 80039d0: 2b50 cmp r3, #80 ; 0x50
+ 80039d2: d033 beq.n 8003a3c <HAL_TIM_ConfigClockSource+0xe0>
+ 80039d4: 2b60 cmp r3, #96 ; 0x60
+ 80039d6: d041 beq.n 8003a5c <HAL_TIM_ConfigClockSource+0x100>
break;
- 800395c: e06a b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 80039d8: e06a b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
- 800395e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8003962: d066 beq.n 8003a32 <HAL_TIM_ConfigClockSource+0x152>
- 8003964: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8003968: d017 beq.n 800399a <HAL_TIM_ConfigClockSource+0xba>
+ 80039da: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 80039de: d066 beq.n 8003aae <HAL_TIM_ConfigClockSource+0x152>
+ 80039e0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
+ 80039e4: d017 beq.n 8003a16 <HAL_TIM_ConfigClockSource+0xba>
break;
- 800396a: e063 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 80039e6: e063 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
- 800396c: 687b ldr r3, [r7, #4]
- 800396e: 6818 ldr r0, [r3, #0]
- 8003970: 683b ldr r3, [r7, #0]
- 8003972: 6899 ldr r1, [r3, #8]
- 8003974: 683b ldr r3, [r7, #0]
- 8003976: 685a ldr r2, [r3, #4]
- 8003978: 683b ldr r3, [r7, #0]
- 800397a: 68db ldr r3, [r3, #12]
- 800397c: f000 fc0a bl 8004194 <TIM_ETR_SetConfig>
+ 80039e8: 687b ldr r3, [r7, #4]
+ 80039ea: 6818 ldr r0, [r3, #0]
+ 80039ec: 683b ldr r3, [r7, #0]
+ 80039ee: 6899 ldr r1, [r3, #8]
+ 80039f0: 683b ldr r3, [r7, #0]
+ 80039f2: 685a ldr r2, [r3, #4]
+ 80039f4: 683b ldr r3, [r7, #0]
+ 80039f6: 68db ldr r3, [r3, #12]
+ 80039f8: f000 fc0a bl 8004210 <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
- 8003980: 687b ldr r3, [r7, #4]
- 8003982: 681b ldr r3, [r3, #0]
- 8003984: 689b ldr r3, [r3, #8]
- 8003986: 60fb str r3, [r7, #12]
+ 80039fc: 687b ldr r3, [r7, #4]
+ 80039fe: 681b ldr r3, [r3, #0]
+ 8003a00: 689b ldr r3, [r3, #8]
+ 8003a02: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8003988: 68fb ldr r3, [r7, #12]
- 800398a: f043 0377 orr.w r3, r3, #119 ; 0x77
- 800398e: 60fb str r3, [r7, #12]
+ 8003a04: 68fb ldr r3, [r7, #12]
+ 8003a06: f043 0377 orr.w r3, r3, #119 ; 0x77
+ 8003a0a: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
- 8003990: 687b ldr r3, [r7, #4]
- 8003992: 681b ldr r3, [r3, #0]
- 8003994: 68fa ldr r2, [r7, #12]
- 8003996: 609a str r2, [r3, #8]
+ 8003a0c: 687b ldr r3, [r7, #4]
+ 8003a0e: 681b ldr r3, [r3, #0]
+ 8003a10: 68fa ldr r2, [r7, #12]
+ 8003a12: 609a str r2, [r3, #8]
break;
- 8003998: e04c b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 8003a14: e04c b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
- 800399a: 687b ldr r3, [r7, #4]
- 800399c: 6818 ldr r0, [r3, #0]
- 800399e: 683b ldr r3, [r7, #0]
- 80039a0: 6899 ldr r1, [r3, #8]
- 80039a2: 683b ldr r3, [r7, #0]
- 80039a4: 685a ldr r2, [r3, #4]
- 80039a6: 683b ldr r3, [r7, #0]
- 80039a8: 68db ldr r3, [r3, #12]
- 80039aa: f000 fbf3 bl 8004194 <TIM_ETR_SetConfig>
+ 8003a16: 687b ldr r3, [r7, #4]
+ 8003a18: 6818 ldr r0, [r3, #0]
+ 8003a1a: 683b ldr r3, [r7, #0]
+ 8003a1c: 6899 ldr r1, [r3, #8]
+ 8003a1e: 683b ldr r3, [r7, #0]
+ 8003a20: 685a ldr r2, [r3, #4]
+ 8003a22: 683b ldr r3, [r7, #0]
+ 8003a24: 68db ldr r3, [r3, #12]
+ 8003a26: f000 fbf3 bl 8004210 <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
- 80039ae: 687b ldr r3, [r7, #4]
- 80039b0: 681b ldr r3, [r3, #0]
- 80039b2: 689a ldr r2, [r3, #8]
- 80039b4: 687b ldr r3, [r7, #4]
- 80039b6: 681b ldr r3, [r3, #0]
- 80039b8: f442 4280 orr.w r2, r2, #16384 ; 0x4000
- 80039bc: 609a str r2, [r3, #8]
+ 8003a2a: 687b ldr r3, [r7, #4]
+ 8003a2c: 681b ldr r3, [r3, #0]
+ 8003a2e: 689a ldr r2, [r3, #8]
+ 8003a30: 687b ldr r3, [r7, #4]
+ 8003a32: 681b ldr r3, [r3, #0]
+ 8003a34: f442 4280 orr.w r2, r2, #16384 ; 0x4000
+ 8003a38: 609a str r2, [r3, #8]
break;
- 80039be: e039 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 8003a3a: e039 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
- 80039c0: 687b ldr r3, [r7, #4]
- 80039c2: 6818 ldr r0, [r3, #0]
- 80039c4: 683b ldr r3, [r7, #0]
- 80039c6: 6859 ldr r1, [r3, #4]
- 80039c8: 683b ldr r3, [r7, #0]
- 80039ca: 68db ldr r3, [r3, #12]
- 80039cc: 461a mov r2, r3
- 80039ce: f000 fb67 bl 80040a0 <TIM_TI1_ConfigInputStage>
+ 8003a3c: 687b ldr r3, [r7, #4]
+ 8003a3e: 6818 ldr r0, [r3, #0]
+ 8003a40: 683b ldr r3, [r7, #0]
+ 8003a42: 6859 ldr r1, [r3, #4]
+ 8003a44: 683b ldr r3, [r7, #0]
+ 8003a46: 68db ldr r3, [r3, #12]
+ 8003a48: 461a mov r2, r3
+ 8003a4a: f000 fb67 bl 800411c <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 80039d2: 687b ldr r3, [r7, #4]
- 80039d4: 681b ldr r3, [r3, #0]
- 80039d6: 2150 movs r1, #80 ; 0x50
- 80039d8: 4618 mov r0, r3
- 80039da: f000 fbc0 bl 800415e <TIM_ITRx_SetConfig>
+ 8003a4e: 687b ldr r3, [r7, #4]
+ 8003a50: 681b ldr r3, [r3, #0]
+ 8003a52: 2150 movs r1, #80 ; 0x50
+ 8003a54: 4618 mov r0, r3
+ 8003a56: f000 fbc0 bl 80041da <TIM_ITRx_SetConfig>
break;
- 80039de: e029 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 8003a5a: e029 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI2_ConfigInputStage(htim->Instance,
- 80039e0: 687b ldr r3, [r7, #4]
- 80039e2: 6818 ldr r0, [r3, #0]
- 80039e4: 683b ldr r3, [r7, #0]
- 80039e6: 6859 ldr r1, [r3, #4]
- 80039e8: 683b ldr r3, [r7, #0]
- 80039ea: 68db ldr r3, [r3, #12]
- 80039ec: 461a mov r2, r3
- 80039ee: f000 fb86 bl 80040fe <TIM_TI2_ConfigInputStage>
+ 8003a5c: 687b ldr r3, [r7, #4]
+ 8003a5e: 6818 ldr r0, [r3, #0]
+ 8003a60: 683b ldr r3, [r7, #0]
+ 8003a62: 6859 ldr r1, [r3, #4]
+ 8003a64: 683b ldr r3, [r7, #0]
+ 8003a66: 68db ldr r3, [r3, #12]
+ 8003a68: 461a mov r2, r3
+ 8003a6a: f000 fb86 bl 800417a <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 80039f2: 687b ldr r3, [r7, #4]
- 80039f4: 681b ldr r3, [r3, #0]
- 80039f6: 2160 movs r1, #96 ; 0x60
- 80039f8: 4618 mov r0, r3
- 80039fa: f000 fbb0 bl 800415e <TIM_ITRx_SetConfig>
+ 8003a6e: 687b ldr r3, [r7, #4]
+ 8003a70: 681b ldr r3, [r3, #0]
+ 8003a72: 2160 movs r1, #96 ; 0x60
+ 8003a74: 4618 mov r0, r3
+ 8003a76: f000 fbb0 bl 80041da <TIM_ITRx_SetConfig>
break;
- 80039fe: e019 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 8003a7a: e019 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
- 8003a00: 687b ldr r3, [r7, #4]
- 8003a02: 6818 ldr r0, [r3, #0]
- 8003a04: 683b ldr r3, [r7, #0]
- 8003a06: 6859 ldr r1, [r3, #4]
- 8003a08: 683b ldr r3, [r7, #0]
- 8003a0a: 68db ldr r3, [r3, #12]
- 8003a0c: 461a mov r2, r3
- 8003a0e: f000 fb47 bl 80040a0 <TIM_TI1_ConfigInputStage>
+ 8003a7c: 687b ldr r3, [r7, #4]
+ 8003a7e: 6818 ldr r0, [r3, #0]
+ 8003a80: 683b ldr r3, [r7, #0]
+ 8003a82: 6859 ldr r1, [r3, #4]
+ 8003a84: 683b ldr r3, [r7, #0]
+ 8003a86: 68db ldr r3, [r3, #12]
+ 8003a88: 461a mov r2, r3
+ 8003a8a: f000 fb47 bl 800411c <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 8003a12: 687b ldr r3, [r7, #4]
- 8003a14: 681b ldr r3, [r3, #0]
- 8003a16: 2140 movs r1, #64 ; 0x40
- 8003a18: 4618 mov r0, r3
- 8003a1a: f000 fba0 bl 800415e <TIM_ITRx_SetConfig>
+ 8003a8e: 687b ldr r3, [r7, #4]
+ 8003a90: 681b ldr r3, [r3, #0]
+ 8003a92: 2140 movs r1, #64 ; 0x40
+ 8003a94: 4618 mov r0, r3
+ 8003a96: f000 fba0 bl 80041da <TIM_ITRx_SetConfig>
break;
- 8003a1e: e009 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 8003a9a: e009 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 8003a20: 687b ldr r3, [r7, #4]
- 8003a22: 681a ldr r2, [r3, #0]
- 8003a24: 683b ldr r3, [r7, #0]
- 8003a26: 681b ldr r3, [r3, #0]
- 8003a28: 4619 mov r1, r3
- 8003a2a: 4610 mov r0, r2
- 8003a2c: f000 fb97 bl 800415e <TIM_ITRx_SetConfig>
+ 8003a9c: 687b ldr r3, [r7, #4]
+ 8003a9e: 681a ldr r2, [r3, #0]
+ 8003aa0: 683b ldr r3, [r7, #0]
+ 8003aa2: 681b ldr r3, [r3, #0]
+ 8003aa4: 4619 mov r1, r3
+ 8003aa6: 4610 mov r0, r2
+ 8003aa8: f000 fb97 bl 80041da <TIM_ITRx_SetConfig>
break;
- 8003a30: e000 b.n 8003a34 <HAL_TIM_ConfigClockSource+0x154>
+ 8003aac: e000 b.n 8003ab0 <HAL_TIM_ConfigClockSource+0x154>
break;
- 8003a32: bf00 nop
+ 8003aae: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
- 8003a34: 687b ldr r3, [r7, #4]
- 8003a36: 2201 movs r2, #1
- 8003a38: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8003ab0: 687b ldr r3, [r7, #4]
+ 8003ab2: 2201 movs r2, #1
+ 8003ab4: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
- 8003a3c: 687b ldr r3, [r7, #4]
- 8003a3e: 2200 movs r2, #0
- 8003a40: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8003ab8: 687b ldr r3, [r7, #4]
+ 8003aba: 2200 movs r2, #0
+ 8003abc: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
- 8003a44: 2300 movs r3, #0
+ 8003ac0: 2300 movs r3, #0
}
- 8003a46: 4618 mov r0, r3
- 8003a48: 3710 adds r7, #16
- 8003a4a: 46bd mov sp, r7
- 8003a4c: bd80 pop {r7, pc}
- 8003a4e: bf00 nop
- 8003a50: fffeff88 .word 0xfffeff88
-
-08003a54 <HAL_TIM_OC_DelayElapsedCallback>:
+ 8003ac2: 4618 mov r0, r3
+ 8003ac4: 3710 adds r7, #16
+ 8003ac6: 46bd mov sp, r7
+ 8003ac8: bd80 pop {r7, pc}
+ 8003aca: bf00 nop
+ 8003acc: fffeff88 .word 0xfffeff88
+
+08003ad0 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
- 8003a54: b480 push {r7}
- 8003a56: b083 sub sp, #12
- 8003a58: af00 add r7, sp, #0
- 8003a5a: 6078 str r0, [r7, #4]
+ 8003ad0: b480 push {r7}
+ 8003ad2: b083 sub sp, #12
+ 8003ad4: af00 add r7, sp, #0
+ 8003ad6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
- 8003a5c: bf00 nop
- 8003a5e: 370c adds r7, #12
- 8003a60: 46bd mov sp, r7
- 8003a62: f85d 7b04 ldr.w r7, [sp], #4
- 8003a66: 4770 bx lr
+ 8003ad8: bf00 nop
+ 8003ada: 370c adds r7, #12
+ 8003adc: 46bd mov sp, r7
+ 8003ade: f85d 7b04 ldr.w r7, [sp], #4
+ 8003ae2: 4770 bx lr
-08003a68 <HAL_TIM_IC_CaptureCallback>:
+08003ae4 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
- 8003a68: b480 push {r7}
- 8003a6a: b083 sub sp, #12
- 8003a6c: af00 add r7, sp, #0
- 8003a6e: 6078 str r0, [r7, #4]
+ 8003ae4: b480 push {r7}
+ 8003ae6: b083 sub sp, #12
+ 8003ae8: af00 add r7, sp, #0
+ 8003aea: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
- 8003a70: bf00 nop
- 8003a72: 370c adds r7, #12
- 8003a74: 46bd mov sp, r7
- 8003a76: f85d 7b04 ldr.w r7, [sp], #4
- 8003a7a: 4770 bx lr
+ 8003aec: bf00 nop
+ 8003aee: 370c adds r7, #12
+ 8003af0: 46bd mov sp, r7
+ 8003af2: f85d 7b04 ldr.w r7, [sp], #4
+ 8003af6: 4770 bx lr
-08003a7c <HAL_TIM_PWM_PulseFinishedCallback>:
+08003af8 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
- 8003a7c: b480 push {r7}
- 8003a7e: b083 sub sp, #12
- 8003a80: af00 add r7, sp, #0
- 8003a82: 6078 str r0, [r7, #4]
+ 8003af8: b480 push {r7}
+ 8003afa: b083 sub sp, #12
+ 8003afc: af00 add r7, sp, #0
+ 8003afe: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
- 8003a84: bf00 nop
- 8003a86: 370c adds r7, #12
- 8003a88: 46bd mov sp, r7
- 8003a8a: f85d 7b04 ldr.w r7, [sp], #4
- 8003a8e: 4770 bx lr
+ 8003b00: bf00 nop
+ 8003b02: 370c adds r7, #12
+ 8003b04: 46bd mov sp, r7
+ 8003b06: f85d 7b04 ldr.w r7, [sp], #4
+ 8003b0a: 4770 bx lr
-08003a90 <HAL_TIM_TriggerCallback>:
+08003b0c <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
- 8003a90: b480 push {r7}
- 8003a92: b083 sub sp, #12
- 8003a94: af00 add r7, sp, #0
- 8003a96: 6078 str r0, [r7, #4]
+ 8003b0c: b480 push {r7}
+ 8003b0e: b083 sub sp, #12
+ 8003b10: af00 add r7, sp, #0
+ 8003b12: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
- 8003a98: bf00 nop
- 8003a9a: 370c adds r7, #12
- 8003a9c: 46bd mov sp, r7
- 8003a9e: f85d 7b04 ldr.w r7, [sp], #4
- 8003aa2: 4770 bx lr
+ 8003b14: bf00 nop
+ 8003b16: 370c adds r7, #12
+ 8003b18: 46bd mov sp, r7
+ 8003b1a: f85d 7b04 ldr.w r7, [sp], #4
+ 8003b1e: 4770 bx lr
-08003aa4 <TIM_Base_SetConfig>:
+08003b20 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- 8003aa4: b480 push {r7}
- 8003aa6: b085 sub sp, #20
- 8003aa8: af00 add r7, sp, #0
- 8003aaa: 6078 str r0, [r7, #4]
- 8003aac: 6039 str r1, [r7, #0]
+ 8003b20: b480 push {r7}
+ 8003b22: b085 sub sp, #20
+ 8003b24: af00 add r7, sp, #0
+ 8003b26: 6078 str r0, [r7, #4]
+ 8003b28: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
- 8003aae: 687b ldr r3, [r7, #4]
- 8003ab0: 681b ldr r3, [r3, #0]
- 8003ab2: 60fb str r3, [r7, #12]
+ 8003b2a: 687b ldr r3, [r7, #4]
+ 8003b2c: 681b ldr r3, [r3, #0]
+ 8003b2e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8003ab4: 687b ldr r3, [r7, #4]
- 8003ab6: 4a40 ldr r2, [pc, #256] ; (8003bb8 <TIM_Base_SetConfig+0x114>)
- 8003ab8: 4293 cmp r3, r2
- 8003aba: d013 beq.n 8003ae4 <TIM_Base_SetConfig+0x40>
- 8003abc: 687b ldr r3, [r7, #4]
- 8003abe: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003ac2: d00f beq.n 8003ae4 <TIM_Base_SetConfig+0x40>
- 8003ac4: 687b ldr r3, [r7, #4]
- 8003ac6: 4a3d ldr r2, [pc, #244] ; (8003bbc <TIM_Base_SetConfig+0x118>)
- 8003ac8: 4293 cmp r3, r2
- 8003aca: d00b beq.n 8003ae4 <TIM_Base_SetConfig+0x40>
- 8003acc: 687b ldr r3, [r7, #4]
- 8003ace: 4a3c ldr r2, [pc, #240] ; (8003bc0 <TIM_Base_SetConfig+0x11c>)
- 8003ad0: 4293 cmp r3, r2
- 8003ad2: d007 beq.n 8003ae4 <TIM_Base_SetConfig+0x40>
- 8003ad4: 687b ldr r3, [r7, #4]
- 8003ad6: 4a3b ldr r2, [pc, #236] ; (8003bc4 <TIM_Base_SetConfig+0x120>)
- 8003ad8: 4293 cmp r3, r2
- 8003ada: d003 beq.n 8003ae4 <TIM_Base_SetConfig+0x40>
- 8003adc: 687b ldr r3, [r7, #4]
- 8003ade: 4a3a ldr r2, [pc, #232] ; (8003bc8 <TIM_Base_SetConfig+0x124>)
- 8003ae0: 4293 cmp r3, r2
- 8003ae2: d108 bne.n 8003af6 <TIM_Base_SetConfig+0x52>
+ 8003b30: 687b ldr r3, [r7, #4]
+ 8003b32: 4a40 ldr r2, [pc, #256] ; (8003c34 <TIM_Base_SetConfig+0x114>)
+ 8003b34: 4293 cmp r3, r2
+ 8003b36: d013 beq.n 8003b60 <TIM_Base_SetConfig+0x40>
+ 8003b38: 687b ldr r3, [r7, #4]
+ 8003b3a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 8003b3e: d00f beq.n 8003b60 <TIM_Base_SetConfig+0x40>
+ 8003b40: 687b ldr r3, [r7, #4]
+ 8003b42: 4a3d ldr r2, [pc, #244] ; (8003c38 <TIM_Base_SetConfig+0x118>)
+ 8003b44: 4293 cmp r3, r2
+ 8003b46: d00b beq.n 8003b60 <TIM_Base_SetConfig+0x40>
+ 8003b48: 687b ldr r3, [r7, #4]
+ 8003b4a: 4a3c ldr r2, [pc, #240] ; (8003c3c <TIM_Base_SetConfig+0x11c>)
+ 8003b4c: 4293 cmp r3, r2
+ 8003b4e: d007 beq.n 8003b60 <TIM_Base_SetConfig+0x40>
+ 8003b50: 687b ldr r3, [r7, #4]
+ 8003b52: 4a3b ldr r2, [pc, #236] ; (8003c40 <TIM_Base_SetConfig+0x120>)
+ 8003b54: 4293 cmp r3, r2
+ 8003b56: d003 beq.n 8003b60 <TIM_Base_SetConfig+0x40>
+ 8003b58: 687b ldr r3, [r7, #4]
+ 8003b5a: 4a3a ldr r2, [pc, #232] ; (8003c44 <TIM_Base_SetConfig+0x124>)
+ 8003b5c: 4293 cmp r3, r2
+ 8003b5e: d108 bne.n 8003b72 <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 8003ae4: 68fb ldr r3, [r7, #12]
- 8003ae6: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8003aea: 60fb str r3, [r7, #12]
+ 8003b60: 68fb ldr r3, [r7, #12]
+ 8003b62: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 8003b66: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
- 8003aec: 683b ldr r3, [r7, #0]
- 8003aee: 685b ldr r3, [r3, #4]
- 8003af0: 68fa ldr r2, [r7, #12]
- 8003af2: 4313 orrs r3, r2
- 8003af4: 60fb str r3, [r7, #12]
+ 8003b68: 683b ldr r3, [r7, #0]
+ 8003b6a: 685b ldr r3, [r3, #4]
+ 8003b6c: 68fa ldr r2, [r7, #12]
+ 8003b6e: 4313 orrs r3, r2
+ 8003b70: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 8003af6: 687b ldr r3, [r7, #4]
- 8003af8: 4a2f ldr r2, [pc, #188] ; (8003bb8 <TIM_Base_SetConfig+0x114>)
- 8003afa: 4293 cmp r3, r2
- 8003afc: d02b beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003afe: 687b ldr r3, [r7, #4]
- 8003b00: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8003b04: d027 beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b06: 687b ldr r3, [r7, #4]
- 8003b08: 4a2c ldr r2, [pc, #176] ; (8003bbc <TIM_Base_SetConfig+0x118>)
- 8003b0a: 4293 cmp r3, r2
- 8003b0c: d023 beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b0e: 687b ldr r3, [r7, #4]
- 8003b10: 4a2b ldr r2, [pc, #172] ; (8003bc0 <TIM_Base_SetConfig+0x11c>)
- 8003b12: 4293 cmp r3, r2
- 8003b14: d01f beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b16: 687b ldr r3, [r7, #4]
- 8003b18: 4a2a ldr r2, [pc, #168] ; (8003bc4 <TIM_Base_SetConfig+0x120>)
- 8003b1a: 4293 cmp r3, r2
- 8003b1c: d01b beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b1e: 687b ldr r3, [r7, #4]
- 8003b20: 4a29 ldr r2, [pc, #164] ; (8003bc8 <TIM_Base_SetConfig+0x124>)
- 8003b22: 4293 cmp r3, r2
- 8003b24: d017 beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b26: 687b ldr r3, [r7, #4]
- 8003b28: 4a28 ldr r2, [pc, #160] ; (8003bcc <TIM_Base_SetConfig+0x128>)
- 8003b2a: 4293 cmp r3, r2
- 8003b2c: d013 beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b2e: 687b ldr r3, [r7, #4]
- 8003b30: 4a27 ldr r2, [pc, #156] ; (8003bd0 <TIM_Base_SetConfig+0x12c>)
- 8003b32: 4293 cmp r3, r2
- 8003b34: d00f beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b36: 687b ldr r3, [r7, #4]
- 8003b38: 4a26 ldr r2, [pc, #152] ; (8003bd4 <TIM_Base_SetConfig+0x130>)
- 8003b3a: 4293 cmp r3, r2
- 8003b3c: d00b beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b3e: 687b ldr r3, [r7, #4]
- 8003b40: 4a25 ldr r2, [pc, #148] ; (8003bd8 <TIM_Base_SetConfig+0x134>)
- 8003b42: 4293 cmp r3, r2
- 8003b44: d007 beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b46: 687b ldr r3, [r7, #4]
- 8003b48: 4a24 ldr r2, [pc, #144] ; (8003bdc <TIM_Base_SetConfig+0x138>)
- 8003b4a: 4293 cmp r3, r2
- 8003b4c: d003 beq.n 8003b56 <TIM_Base_SetConfig+0xb2>
- 8003b4e: 687b ldr r3, [r7, #4]
- 8003b50: 4a23 ldr r2, [pc, #140] ; (8003be0 <TIM_Base_SetConfig+0x13c>)
- 8003b52: 4293 cmp r3, r2
- 8003b54: d108 bne.n 8003b68 <TIM_Base_SetConfig+0xc4>
+ 8003b72: 687b ldr r3, [r7, #4]
+ 8003b74: 4a2f ldr r2, [pc, #188] ; (8003c34 <TIM_Base_SetConfig+0x114>)
+ 8003b76: 4293 cmp r3, r2
+ 8003b78: d02b beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003b7a: 687b ldr r3, [r7, #4]
+ 8003b7c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 8003b80: d027 beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003b82: 687b ldr r3, [r7, #4]
+ 8003b84: 4a2c ldr r2, [pc, #176] ; (8003c38 <TIM_Base_SetConfig+0x118>)
+ 8003b86: 4293 cmp r3, r2
+ 8003b88: d023 beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003b8a: 687b ldr r3, [r7, #4]
+ 8003b8c: 4a2b ldr r2, [pc, #172] ; (8003c3c <TIM_Base_SetConfig+0x11c>)
+ 8003b8e: 4293 cmp r3, r2
+ 8003b90: d01f beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003b92: 687b ldr r3, [r7, #4]
+ 8003b94: 4a2a ldr r2, [pc, #168] ; (8003c40 <TIM_Base_SetConfig+0x120>)
+ 8003b96: 4293 cmp r3, r2
+ 8003b98: d01b beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003b9a: 687b ldr r3, [r7, #4]
+ 8003b9c: 4a29 ldr r2, [pc, #164] ; (8003c44 <TIM_Base_SetConfig+0x124>)
+ 8003b9e: 4293 cmp r3, r2
+ 8003ba0: d017 beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003ba2: 687b ldr r3, [r7, #4]
+ 8003ba4: 4a28 ldr r2, [pc, #160] ; (8003c48 <TIM_Base_SetConfig+0x128>)
+ 8003ba6: 4293 cmp r3, r2
+ 8003ba8: d013 beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003baa: 687b ldr r3, [r7, #4]
+ 8003bac: 4a27 ldr r2, [pc, #156] ; (8003c4c <TIM_Base_SetConfig+0x12c>)
+ 8003bae: 4293 cmp r3, r2
+ 8003bb0: d00f beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003bb2: 687b ldr r3, [r7, #4]
+ 8003bb4: 4a26 ldr r2, [pc, #152] ; (8003c50 <TIM_Base_SetConfig+0x130>)
+ 8003bb6: 4293 cmp r3, r2
+ 8003bb8: d00b beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003bba: 687b ldr r3, [r7, #4]
+ 8003bbc: 4a25 ldr r2, [pc, #148] ; (8003c54 <TIM_Base_SetConfig+0x134>)
+ 8003bbe: 4293 cmp r3, r2
+ 8003bc0: d007 beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003bc2: 687b ldr r3, [r7, #4]
+ 8003bc4: 4a24 ldr r2, [pc, #144] ; (8003c58 <TIM_Base_SetConfig+0x138>)
+ 8003bc6: 4293 cmp r3, r2
+ 8003bc8: d003 beq.n 8003bd2 <TIM_Base_SetConfig+0xb2>
+ 8003bca: 687b ldr r3, [r7, #4]
+ 8003bcc: 4a23 ldr r2, [pc, #140] ; (8003c5c <TIM_Base_SetConfig+0x13c>)
+ 8003bce: 4293 cmp r3, r2
+ 8003bd0: d108 bne.n 8003be4 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
- 8003b56: 68fb ldr r3, [r7, #12]
- 8003b58: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003b5c: 60fb str r3, [r7, #12]
+ 8003bd2: 68fb ldr r3, [r7, #12]
+ 8003bd4: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8003bd8: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 8003b5e: 683b ldr r3, [r7, #0]
- 8003b60: 68db ldr r3, [r3, #12]
- 8003b62: 68fa ldr r2, [r7, #12]
- 8003b64: 4313 orrs r3, r2
- 8003b66: 60fb str r3, [r7, #12]
+ 8003bda: 683b ldr r3, [r7, #0]
+ 8003bdc: 68db ldr r3, [r3, #12]
+ 8003bde: 68fa ldr r2, [r7, #12]
+ 8003be0: 4313 orrs r3, r2
+ 8003be2: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8003b68: 68fb ldr r3, [r7, #12]
- 8003b6a: f023 0280 bic.w r2, r3, #128 ; 0x80
- 8003b6e: 683b ldr r3, [r7, #0]
- 8003b70: 695b ldr r3, [r3, #20]
- 8003b72: 4313 orrs r3, r2
- 8003b74: 60fb str r3, [r7, #12]
+ 8003be4: 68fb ldr r3, [r7, #12]
+ 8003be6: f023 0280 bic.w r2, r3, #128 ; 0x80
+ 8003bea: 683b ldr r3, [r7, #0]
+ 8003bec: 695b ldr r3, [r3, #20]
+ 8003bee: 4313 orrs r3, r2
+ 8003bf0: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
- 8003b76: 687b ldr r3, [r7, #4]
- 8003b78: 68fa ldr r2, [r7, #12]
- 8003b7a: 601a str r2, [r3, #0]
+ 8003bf2: 687b ldr r3, [r7, #4]
+ 8003bf4: 68fa ldr r2, [r7, #12]
+ 8003bf6: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
- 8003b7c: 683b ldr r3, [r7, #0]
- 8003b7e: 689a ldr r2, [r3, #8]
- 8003b80: 687b ldr r3, [r7, #4]
- 8003b82: 62da str r2, [r3, #44] ; 0x2c
+ 8003bf8: 683b ldr r3, [r7, #0]
+ 8003bfa: 689a ldr r2, [r3, #8]
+ 8003bfc: 687b ldr r3, [r7, #4]
+ 8003bfe: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
- 8003b84: 683b ldr r3, [r7, #0]
- 8003b86: 681a ldr r2, [r3, #0]
- 8003b88: 687b ldr r3, [r7, #4]
- 8003b8a: 629a str r2, [r3, #40] ; 0x28
+ 8003c00: 683b ldr r3, [r7, #0]
+ 8003c02: 681a ldr r2, [r3, #0]
+ 8003c04: 687b ldr r3, [r7, #4]
+ 8003c06: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8003b8c: 687b ldr r3, [r7, #4]
- 8003b8e: 4a0a ldr r2, [pc, #40] ; (8003bb8 <TIM_Base_SetConfig+0x114>)
- 8003b90: 4293 cmp r3, r2
- 8003b92: d003 beq.n 8003b9c <TIM_Base_SetConfig+0xf8>
- 8003b94: 687b ldr r3, [r7, #4]
- 8003b96: 4a0c ldr r2, [pc, #48] ; (8003bc8 <TIM_Base_SetConfig+0x124>)
- 8003b98: 4293 cmp r3, r2
- 8003b9a: d103 bne.n 8003ba4 <TIM_Base_SetConfig+0x100>
+ 8003c08: 687b ldr r3, [r7, #4]
+ 8003c0a: 4a0a ldr r2, [pc, #40] ; (8003c34 <TIM_Base_SetConfig+0x114>)
+ 8003c0c: 4293 cmp r3, r2
+ 8003c0e: d003 beq.n 8003c18 <TIM_Base_SetConfig+0xf8>
+ 8003c10: 687b ldr r3, [r7, #4]
+ 8003c12: 4a0c ldr r2, [pc, #48] ; (8003c44 <TIM_Base_SetConfig+0x124>)
+ 8003c14: 4293 cmp r3, r2
+ 8003c16: d103 bne.n 8003c20 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
- 8003b9c: 683b ldr r3, [r7, #0]
- 8003b9e: 691a ldr r2, [r3, #16]
- 8003ba0: 687b ldr r3, [r7, #4]
- 8003ba2: 631a str r2, [r3, #48] ; 0x30
+ 8003c18: 683b ldr r3, [r7, #0]
+ 8003c1a: 691a ldr r2, [r3, #16]
+ 8003c1c: 687b ldr r3, [r7, #4]
+ 8003c1e: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
- 8003ba4: 687b ldr r3, [r7, #4]
- 8003ba6: 2201 movs r2, #1
- 8003ba8: 615a str r2, [r3, #20]
+ 8003c20: 687b ldr r3, [r7, #4]
+ 8003c22: 2201 movs r2, #1
+ 8003c24: 615a str r2, [r3, #20]
}
- 8003baa: bf00 nop
- 8003bac: 3714 adds r7, #20
- 8003bae: 46bd mov sp, r7
- 8003bb0: f85d 7b04 ldr.w r7, [sp], #4
- 8003bb4: 4770 bx lr
- 8003bb6: bf00 nop
- 8003bb8: 40010000 .word 0x40010000
- 8003bbc: 40000400 .word 0x40000400
- 8003bc0: 40000800 .word 0x40000800
- 8003bc4: 40000c00 .word 0x40000c00
- 8003bc8: 40010400 .word 0x40010400
- 8003bcc: 40014000 .word 0x40014000
- 8003bd0: 40014400 .word 0x40014400
- 8003bd4: 40014800 .word 0x40014800
- 8003bd8: 40001800 .word 0x40001800
- 8003bdc: 40001c00 .word 0x40001c00
- 8003be0: 40002000 .word 0x40002000
-
-08003be4 <TIM_OC1_SetConfig>:
+ 8003c26: bf00 nop
+ 8003c28: 3714 adds r7, #20
+ 8003c2a: 46bd mov sp, r7
+ 8003c2c: f85d 7b04 ldr.w r7, [sp], #4
+ 8003c30: 4770 bx lr
+ 8003c32: bf00 nop
+ 8003c34: 40010000 .word 0x40010000
+ 8003c38: 40000400 .word 0x40000400
+ 8003c3c: 40000800 .word 0x40000800
+ 8003c40: 40000c00 .word 0x40000c00
+ 8003c44: 40010400 .word 0x40010400
+ 8003c48: 40014000 .word 0x40014000
+ 8003c4c: 40014400 .word 0x40014400
+ 8003c50: 40014800 .word 0x40014800
+ 8003c54: 40001800 .word 0x40001800
+ 8003c58: 40001c00 .word 0x40001c00
+ 8003c5c: 40002000 .word 0x40002000
+
+08003c60 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8003be4: b480 push {r7}
- 8003be6: b087 sub sp, #28
- 8003be8: af00 add r7, sp, #0
- 8003bea: 6078 str r0, [r7, #4]
- 8003bec: 6039 str r1, [r7, #0]
+ 8003c60: b480 push {r7}
+ 8003c62: b087 sub sp, #28
+ 8003c64: af00 add r7, sp, #0
+ 8003c66: 6078 str r0, [r7, #4]
+ 8003c68: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
- 8003bee: 687b ldr r3, [r7, #4]
- 8003bf0: 6a1b ldr r3, [r3, #32]
- 8003bf2: f023 0201 bic.w r2, r3, #1
- 8003bf6: 687b ldr r3, [r7, #4]
- 8003bf8: 621a str r2, [r3, #32]
+ 8003c6a: 687b ldr r3, [r7, #4]
+ 8003c6c: 6a1b ldr r3, [r3, #32]
+ 8003c6e: f023 0201 bic.w r2, r3, #1
+ 8003c72: 687b ldr r3, [r7, #4]
+ 8003c74: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8003bfa: 687b ldr r3, [r7, #4]
- 8003bfc: 6a1b ldr r3, [r3, #32]
- 8003bfe: 617b str r3, [r7, #20]
+ 8003c76: 687b ldr r3, [r7, #4]
+ 8003c78: 6a1b ldr r3, [r3, #32]
+ 8003c7a: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8003c00: 687b ldr r3, [r7, #4]
- 8003c02: 685b ldr r3, [r3, #4]
- 8003c04: 613b str r3, [r7, #16]
+ 8003c7c: 687b ldr r3, [r7, #4]
+ 8003c7e: 685b ldr r3, [r3, #4]
+ 8003c80: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- 8003c06: 687b ldr r3, [r7, #4]
- 8003c08: 699b ldr r3, [r3, #24]
- 8003c0a: 60fb str r3, [r7, #12]
+ 8003c82: 687b ldr r3, [r7, #4]
+ 8003c84: 699b ldr r3, [r3, #24]
+ 8003c86: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
- 8003c0c: 68fa ldr r2, [r7, #12]
- 8003c0e: 4b2b ldr r3, [pc, #172] ; (8003cbc <TIM_OC1_SetConfig+0xd8>)
- 8003c10: 4013 ands r3, r2
- 8003c12: 60fb str r3, [r7, #12]
+ 8003c88: 68fa ldr r2, [r7, #12]
+ 8003c8a: 4b2b ldr r3, [pc, #172] ; (8003d38 <TIM_OC1_SetConfig+0xd8>)
+ 8003c8c: 4013 ands r3, r2
+ 8003c8e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
- 8003c14: 68fb ldr r3, [r7, #12]
- 8003c16: f023 0303 bic.w r3, r3, #3
- 8003c1a: 60fb str r3, [r7, #12]
+ 8003c90: 68fb ldr r3, [r7, #12]
+ 8003c92: f023 0303 bic.w r3, r3, #3
+ 8003c96: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 8003c1c: 683b ldr r3, [r7, #0]
- 8003c1e: 681b ldr r3, [r3, #0]
- 8003c20: 68fa ldr r2, [r7, #12]
- 8003c22: 4313 orrs r3, r2
- 8003c24: 60fb str r3, [r7, #12]
+ 8003c98: 683b ldr r3, [r7, #0]
+ 8003c9a: 681b ldr r3, [r3, #0]
+ 8003c9c: 68fa ldr r2, [r7, #12]
+ 8003c9e: 4313 orrs r3, r2
+ 8003ca0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
- 8003c26: 697b ldr r3, [r7, #20]
- 8003c28: f023 0302 bic.w r3, r3, #2
- 8003c2c: 617b str r3, [r7, #20]
+ 8003ca2: 697b ldr r3, [r7, #20]
+ 8003ca4: f023 0302 bic.w r3, r3, #2
+ 8003ca8: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
- 8003c2e: 683b ldr r3, [r7, #0]
- 8003c30: 689b ldr r3, [r3, #8]
- 8003c32: 697a ldr r2, [r7, #20]
- 8003c34: 4313 orrs r3, r2
- 8003c36: 617b str r3, [r7, #20]
+ 8003caa: 683b ldr r3, [r7, #0]
+ 8003cac: 689b ldr r3, [r3, #8]
+ 8003cae: 697a ldr r2, [r7, #20]
+ 8003cb0: 4313 orrs r3, r2
+ 8003cb2: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- 8003c38: 687b ldr r3, [r7, #4]
- 8003c3a: 4a21 ldr r2, [pc, #132] ; (8003cc0 <TIM_OC1_SetConfig+0xdc>)
- 8003c3c: 4293 cmp r3, r2
- 8003c3e: d003 beq.n 8003c48 <TIM_OC1_SetConfig+0x64>
- 8003c40: 687b ldr r3, [r7, #4]
- 8003c42: 4a20 ldr r2, [pc, #128] ; (8003cc4 <TIM_OC1_SetConfig+0xe0>)
- 8003c44: 4293 cmp r3, r2
- 8003c46: d10c bne.n 8003c62 <TIM_OC1_SetConfig+0x7e>
+ 8003cb4: 687b ldr r3, [r7, #4]
+ 8003cb6: 4a21 ldr r2, [pc, #132] ; (8003d3c <TIM_OC1_SetConfig+0xdc>)
+ 8003cb8: 4293 cmp r3, r2
+ 8003cba: d003 beq.n 8003cc4 <TIM_OC1_SetConfig+0x64>
+ 8003cbc: 687b ldr r3, [r7, #4]
+ 8003cbe: 4a20 ldr r2, [pc, #128] ; (8003d40 <TIM_OC1_SetConfig+0xe0>)
+ 8003cc0: 4293 cmp r3, r2
+ 8003cc2: d10c bne.n 8003cde <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
- 8003c48: 697b ldr r3, [r7, #20]
- 8003c4a: f023 0308 bic.w r3, r3, #8
- 8003c4e: 617b str r3, [r7, #20]
+ 8003cc4: 697b ldr r3, [r7, #20]
+ 8003cc6: f023 0308 bic.w r3, r3, #8
+ 8003cca: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
- 8003c50: 683b ldr r3, [r7, #0]
- 8003c52: 68db ldr r3, [r3, #12]
- 8003c54: 697a ldr r2, [r7, #20]
- 8003c56: 4313 orrs r3, r2
- 8003c58: 617b str r3, [r7, #20]
+ 8003ccc: 683b ldr r3, [r7, #0]
+ 8003cce: 68db ldr r3, [r3, #12]
+ 8003cd0: 697a ldr r2, [r7, #20]
+ 8003cd2: 4313 orrs r3, r2
+ 8003cd4: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
- 8003c5a: 697b ldr r3, [r7, #20]
- 8003c5c: f023 0304 bic.w r3, r3, #4
- 8003c60: 617b str r3, [r7, #20]
+ 8003cd6: 697b ldr r3, [r7, #20]
+ 8003cd8: f023 0304 bic.w r3, r3, #4
+ 8003cdc: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003c62: 687b ldr r3, [r7, #4]
- 8003c64: 4a16 ldr r2, [pc, #88] ; (8003cc0 <TIM_OC1_SetConfig+0xdc>)
- 8003c66: 4293 cmp r3, r2
- 8003c68: d003 beq.n 8003c72 <TIM_OC1_SetConfig+0x8e>
- 8003c6a: 687b ldr r3, [r7, #4]
- 8003c6c: 4a15 ldr r2, [pc, #84] ; (8003cc4 <TIM_OC1_SetConfig+0xe0>)
- 8003c6e: 4293 cmp r3, r2
- 8003c70: d111 bne.n 8003c96 <TIM_OC1_SetConfig+0xb2>
+ 8003cde: 687b ldr r3, [r7, #4]
+ 8003ce0: 4a16 ldr r2, [pc, #88] ; (8003d3c <TIM_OC1_SetConfig+0xdc>)
+ 8003ce2: 4293 cmp r3, r2
+ 8003ce4: d003 beq.n 8003cee <TIM_OC1_SetConfig+0x8e>
+ 8003ce6: 687b ldr r3, [r7, #4]
+ 8003ce8: 4a15 ldr r2, [pc, #84] ; (8003d40 <TIM_OC1_SetConfig+0xe0>)
+ 8003cea: 4293 cmp r3, r2
+ 8003cec: d111 bne.n 8003d12 <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
- 8003c72: 693b ldr r3, [r7, #16]
- 8003c74: f423 7380 bic.w r3, r3, #256 ; 0x100
- 8003c78: 613b str r3, [r7, #16]
+ 8003cee: 693b ldr r3, [r7, #16]
+ 8003cf0: f423 7380 bic.w r3, r3, #256 ; 0x100
+ 8003cf4: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
- 8003c7a: 693b ldr r3, [r7, #16]
- 8003c7c: f423 7300 bic.w r3, r3, #512 ; 0x200
- 8003c80: 613b str r3, [r7, #16]
+ 8003cf6: 693b ldr r3, [r7, #16]
+ 8003cf8: f423 7300 bic.w r3, r3, #512 ; 0x200
+ 8003cfc: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
- 8003c82: 683b ldr r3, [r7, #0]
- 8003c84: 695b ldr r3, [r3, #20]
- 8003c86: 693a ldr r2, [r7, #16]
- 8003c88: 4313 orrs r3, r2
- 8003c8a: 613b str r3, [r7, #16]
+ 8003cfe: 683b ldr r3, [r7, #0]
+ 8003d00: 695b ldr r3, [r3, #20]
+ 8003d02: 693a ldr r2, [r7, #16]
+ 8003d04: 4313 orrs r3, r2
+ 8003d06: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
- 8003c8c: 683b ldr r3, [r7, #0]
- 8003c8e: 699b ldr r3, [r3, #24]
- 8003c90: 693a ldr r2, [r7, #16]
- 8003c92: 4313 orrs r3, r2
- 8003c94: 613b str r3, [r7, #16]
+ 8003d08: 683b ldr r3, [r7, #0]
+ 8003d0a: 699b ldr r3, [r3, #24]
+ 8003d0c: 693a ldr r2, [r7, #16]
+ 8003d0e: 4313 orrs r3, r2
+ 8003d10: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8003c96: 687b ldr r3, [r7, #4]
- 8003c98: 693a ldr r2, [r7, #16]
- 8003c9a: 605a str r2, [r3, #4]
+ 8003d12: 687b ldr r3, [r7, #4]
+ 8003d14: 693a ldr r2, [r7, #16]
+ 8003d16: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
- 8003c9c: 687b ldr r3, [r7, #4]
- 8003c9e: 68fa ldr r2, [r7, #12]
- 8003ca0: 619a str r2, [r3, #24]
+ 8003d18: 687b ldr r3, [r7, #4]
+ 8003d1a: 68fa ldr r2, [r7, #12]
+ 8003d1c: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
- 8003ca2: 683b ldr r3, [r7, #0]
- 8003ca4: 685a ldr r2, [r3, #4]
- 8003ca6: 687b ldr r3, [r7, #4]
- 8003ca8: 635a str r2, [r3, #52] ; 0x34
+ 8003d1e: 683b ldr r3, [r7, #0]
+ 8003d20: 685a ldr r2, [r3, #4]
+ 8003d22: 687b ldr r3, [r7, #4]
+ 8003d24: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8003caa: 687b ldr r3, [r7, #4]
- 8003cac: 697a ldr r2, [r7, #20]
- 8003cae: 621a str r2, [r3, #32]
+ 8003d26: 687b ldr r3, [r7, #4]
+ 8003d28: 697a ldr r2, [r7, #20]
+ 8003d2a: 621a str r2, [r3, #32]
}
- 8003cb0: bf00 nop
- 8003cb2: 371c adds r7, #28
- 8003cb4: 46bd mov sp, r7
- 8003cb6: f85d 7b04 ldr.w r7, [sp], #4
- 8003cba: 4770 bx lr
- 8003cbc: fffeff8f .word 0xfffeff8f
- 8003cc0: 40010000 .word 0x40010000
- 8003cc4: 40010400 .word 0x40010400
-
-08003cc8 <TIM_OC2_SetConfig>:
+ 8003d2c: bf00 nop
+ 8003d2e: 371c adds r7, #28
+ 8003d30: 46bd mov sp, r7
+ 8003d32: f85d 7b04 ldr.w r7, [sp], #4
+ 8003d36: 4770 bx lr
+ 8003d38: fffeff8f .word 0xfffeff8f
+ 8003d3c: 40010000 .word 0x40010000
+ 8003d40: 40010400 .word 0x40010400
+
+08003d44 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8003cc8: b480 push {r7}
- 8003cca: b087 sub sp, #28
- 8003ccc: af00 add r7, sp, #0
- 8003cce: 6078 str r0, [r7, #4]
- 8003cd0: 6039 str r1, [r7, #0]
+ 8003d44: b480 push {r7}
+ 8003d46: b087 sub sp, #28
+ 8003d48: af00 add r7, sp, #0
+ 8003d4a: 6078 str r0, [r7, #4]
+ 8003d4c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- 8003cd2: 687b ldr r3, [r7, #4]
- 8003cd4: 6a1b ldr r3, [r3, #32]
- 8003cd6: f023 0210 bic.w r2, r3, #16
- 8003cda: 687b ldr r3, [r7, #4]
- 8003cdc: 621a str r2, [r3, #32]
+ 8003d4e: 687b ldr r3, [r7, #4]
+ 8003d50: 6a1b ldr r3, [r3, #32]
+ 8003d52: f023 0210 bic.w r2, r3, #16
+ 8003d56: 687b ldr r3, [r7, #4]
+ 8003d58: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8003cde: 687b ldr r3, [r7, #4]
- 8003ce0: 6a1b ldr r3, [r3, #32]
- 8003ce2: 617b str r3, [r7, #20]
+ 8003d5a: 687b ldr r3, [r7, #4]
+ 8003d5c: 6a1b ldr r3, [r3, #32]
+ 8003d5e: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8003ce4: 687b ldr r3, [r7, #4]
- 8003ce6: 685b ldr r3, [r3, #4]
- 8003ce8: 613b str r3, [r7, #16]
+ 8003d60: 687b ldr r3, [r7, #4]
+ 8003d62: 685b ldr r3, [r3, #4]
+ 8003d64: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- 8003cea: 687b ldr r3, [r7, #4]
- 8003cec: 699b ldr r3, [r3, #24]
- 8003cee: 60fb str r3, [r7, #12]
+ 8003d66: 687b ldr r3, [r7, #4]
+ 8003d68: 699b ldr r3, [r3, #24]
+ 8003d6a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
- 8003cf0: 68fa ldr r2, [r7, #12]
- 8003cf2: 4b2e ldr r3, [pc, #184] ; (8003dac <TIM_OC2_SetConfig+0xe4>)
- 8003cf4: 4013 ands r3, r2
- 8003cf6: 60fb str r3, [r7, #12]
+ 8003d6c: 68fa ldr r2, [r7, #12]
+ 8003d6e: 4b2e ldr r3, [pc, #184] ; (8003e28 <TIM_OC2_SetConfig+0xe4>)
+ 8003d70: 4013 ands r3, r2
+ 8003d72: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
- 8003cf8: 68fb ldr r3, [r7, #12]
- 8003cfa: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003cfe: 60fb str r3, [r7, #12]
+ 8003d74: 68fb ldr r3, [r7, #12]
+ 8003d76: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8003d7a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 8003d00: 683b ldr r3, [r7, #0]
- 8003d02: 681b ldr r3, [r3, #0]
- 8003d04: 021b lsls r3, r3, #8
- 8003d06: 68fa ldr r2, [r7, #12]
- 8003d08: 4313 orrs r3, r2
- 8003d0a: 60fb str r3, [r7, #12]
+ 8003d7c: 683b ldr r3, [r7, #0]
+ 8003d7e: 681b ldr r3, [r3, #0]
+ 8003d80: 021b lsls r3, r3, #8
+ 8003d82: 68fa ldr r2, [r7, #12]
+ 8003d84: 4313 orrs r3, r2
+ 8003d86: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
- 8003d0c: 697b ldr r3, [r7, #20]
- 8003d0e: f023 0320 bic.w r3, r3, #32
- 8003d12: 617b str r3, [r7, #20]
+ 8003d88: 697b ldr r3, [r7, #20]
+ 8003d8a: f023 0320 bic.w r3, r3, #32
+ 8003d8e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
- 8003d14: 683b ldr r3, [r7, #0]
- 8003d16: 689b ldr r3, [r3, #8]
- 8003d18: 011b lsls r3, r3, #4
- 8003d1a: 697a ldr r2, [r7, #20]
- 8003d1c: 4313 orrs r3, r2
- 8003d1e: 617b str r3, [r7, #20]
+ 8003d90: 683b ldr r3, [r7, #0]
+ 8003d92: 689b ldr r3, [r3, #8]
+ 8003d94: 011b lsls r3, r3, #4
+ 8003d96: 697a ldr r2, [r7, #20]
+ 8003d98: 4313 orrs r3, r2
+ 8003d9a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- 8003d20: 687b ldr r3, [r7, #4]
- 8003d22: 4a23 ldr r2, [pc, #140] ; (8003db0 <TIM_OC2_SetConfig+0xe8>)
- 8003d24: 4293 cmp r3, r2
- 8003d26: d003 beq.n 8003d30 <TIM_OC2_SetConfig+0x68>
- 8003d28: 687b ldr r3, [r7, #4]
- 8003d2a: 4a22 ldr r2, [pc, #136] ; (8003db4 <TIM_OC2_SetConfig+0xec>)
- 8003d2c: 4293 cmp r3, r2
- 8003d2e: d10d bne.n 8003d4c <TIM_OC2_SetConfig+0x84>
+ 8003d9c: 687b ldr r3, [r7, #4]
+ 8003d9e: 4a23 ldr r2, [pc, #140] ; (8003e2c <TIM_OC2_SetConfig+0xe8>)
+ 8003da0: 4293 cmp r3, r2
+ 8003da2: d003 beq.n 8003dac <TIM_OC2_SetConfig+0x68>
+ 8003da4: 687b ldr r3, [r7, #4]
+ 8003da6: 4a22 ldr r2, [pc, #136] ; (8003e30 <TIM_OC2_SetConfig+0xec>)
+ 8003da8: 4293 cmp r3, r2
+ 8003daa: d10d bne.n 8003dc8 <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
- 8003d30: 697b ldr r3, [r7, #20]
- 8003d32: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8003d36: 617b str r3, [r7, #20]
+ 8003dac: 697b ldr r3, [r7, #20]
+ 8003dae: f023 0380 bic.w r3, r3, #128 ; 0x80
+ 8003db2: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
- 8003d38: 683b ldr r3, [r7, #0]
- 8003d3a: 68db ldr r3, [r3, #12]
- 8003d3c: 011b lsls r3, r3, #4
- 8003d3e: 697a ldr r2, [r7, #20]
- 8003d40: 4313 orrs r3, r2
- 8003d42: 617b str r3, [r7, #20]
+ 8003db4: 683b ldr r3, [r7, #0]
+ 8003db6: 68db ldr r3, [r3, #12]
+ 8003db8: 011b lsls r3, r3, #4
+ 8003dba: 697a ldr r2, [r7, #20]
+ 8003dbc: 4313 orrs r3, r2
+ 8003dbe: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
- 8003d44: 697b ldr r3, [r7, #20]
- 8003d46: f023 0340 bic.w r3, r3, #64 ; 0x40
- 8003d4a: 617b str r3, [r7, #20]
+ 8003dc0: 697b ldr r3, [r7, #20]
+ 8003dc2: f023 0340 bic.w r3, r3, #64 ; 0x40
+ 8003dc6: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003d4c: 687b ldr r3, [r7, #4]
- 8003d4e: 4a18 ldr r2, [pc, #96] ; (8003db0 <TIM_OC2_SetConfig+0xe8>)
- 8003d50: 4293 cmp r3, r2
- 8003d52: d003 beq.n 8003d5c <TIM_OC2_SetConfig+0x94>
- 8003d54: 687b ldr r3, [r7, #4]
- 8003d56: 4a17 ldr r2, [pc, #92] ; (8003db4 <TIM_OC2_SetConfig+0xec>)
- 8003d58: 4293 cmp r3, r2
- 8003d5a: d113 bne.n 8003d84 <TIM_OC2_SetConfig+0xbc>
+ 8003dc8: 687b ldr r3, [r7, #4]
+ 8003dca: 4a18 ldr r2, [pc, #96] ; (8003e2c <TIM_OC2_SetConfig+0xe8>)
+ 8003dcc: 4293 cmp r3, r2
+ 8003dce: d003 beq.n 8003dd8 <TIM_OC2_SetConfig+0x94>
+ 8003dd0: 687b ldr r3, [r7, #4]
+ 8003dd2: 4a17 ldr r2, [pc, #92] ; (8003e30 <TIM_OC2_SetConfig+0xec>)
+ 8003dd4: 4293 cmp r3, r2
+ 8003dd6: d113 bne.n 8003e00 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
- 8003d5c: 693b ldr r3, [r7, #16]
- 8003d5e: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 8003d62: 613b str r3, [r7, #16]
+ 8003dd8: 693b ldr r3, [r7, #16]
+ 8003dda: f423 6380 bic.w r3, r3, #1024 ; 0x400
+ 8003dde: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
- 8003d64: 693b ldr r3, [r7, #16]
- 8003d66: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8003d6a: 613b str r3, [r7, #16]
+ 8003de0: 693b ldr r3, [r7, #16]
+ 8003de2: f423 6300 bic.w r3, r3, #2048 ; 0x800
+ 8003de6: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
- 8003d6c: 683b ldr r3, [r7, #0]
- 8003d6e: 695b ldr r3, [r3, #20]
- 8003d70: 009b lsls r3, r3, #2
- 8003d72: 693a ldr r2, [r7, #16]
- 8003d74: 4313 orrs r3, r2
- 8003d76: 613b str r3, [r7, #16]
+ 8003de8: 683b ldr r3, [r7, #0]
+ 8003dea: 695b ldr r3, [r3, #20]
+ 8003dec: 009b lsls r3, r3, #2
+ 8003dee: 693a ldr r2, [r7, #16]
+ 8003df0: 4313 orrs r3, r2
+ 8003df2: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- 8003d78: 683b ldr r3, [r7, #0]
- 8003d7a: 699b ldr r3, [r3, #24]
- 8003d7c: 009b lsls r3, r3, #2
- 8003d7e: 693a ldr r2, [r7, #16]
- 8003d80: 4313 orrs r3, r2
- 8003d82: 613b str r3, [r7, #16]
+ 8003df4: 683b ldr r3, [r7, #0]
+ 8003df6: 699b ldr r3, [r3, #24]
+ 8003df8: 009b lsls r3, r3, #2
+ 8003dfa: 693a ldr r2, [r7, #16]
+ 8003dfc: 4313 orrs r3, r2
+ 8003dfe: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8003d84: 687b ldr r3, [r7, #4]
- 8003d86: 693a ldr r2, [r7, #16]
- 8003d88: 605a str r2, [r3, #4]
+ 8003e00: 687b ldr r3, [r7, #4]
+ 8003e02: 693a ldr r2, [r7, #16]
+ 8003e04: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
- 8003d8a: 687b ldr r3, [r7, #4]
- 8003d8c: 68fa ldr r2, [r7, #12]
- 8003d8e: 619a str r2, [r3, #24]
+ 8003e06: 687b ldr r3, [r7, #4]
+ 8003e08: 68fa ldr r2, [r7, #12]
+ 8003e0a: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
- 8003d90: 683b ldr r3, [r7, #0]
- 8003d92: 685a ldr r2, [r3, #4]
- 8003d94: 687b ldr r3, [r7, #4]
- 8003d96: 639a str r2, [r3, #56] ; 0x38
+ 8003e0c: 683b ldr r3, [r7, #0]
+ 8003e0e: 685a ldr r2, [r3, #4]
+ 8003e10: 687b ldr r3, [r7, #4]
+ 8003e12: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8003d98: 687b ldr r3, [r7, #4]
- 8003d9a: 697a ldr r2, [r7, #20]
- 8003d9c: 621a str r2, [r3, #32]
+ 8003e14: 687b ldr r3, [r7, #4]
+ 8003e16: 697a ldr r2, [r7, #20]
+ 8003e18: 621a str r2, [r3, #32]
}
- 8003d9e: bf00 nop
- 8003da0: 371c adds r7, #28
- 8003da2: 46bd mov sp, r7
- 8003da4: f85d 7b04 ldr.w r7, [sp], #4
- 8003da8: 4770 bx lr
- 8003daa: bf00 nop
- 8003dac: feff8fff .word 0xfeff8fff
- 8003db0: 40010000 .word 0x40010000
- 8003db4: 40010400 .word 0x40010400
-
-08003db8 <TIM_OC3_SetConfig>:
+ 8003e1a: bf00 nop
+ 8003e1c: 371c adds r7, #28
+ 8003e1e: 46bd mov sp, r7
+ 8003e20: f85d 7b04 ldr.w r7, [sp], #4
+ 8003e24: 4770 bx lr
+ 8003e26: bf00 nop
+ 8003e28: feff8fff .word 0xfeff8fff
+ 8003e2c: 40010000 .word 0x40010000
+ 8003e30: 40010400 .word 0x40010400
+
+08003e34 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8003db8: b480 push {r7}
- 8003dba: b087 sub sp, #28
- 8003dbc: af00 add r7, sp, #0
- 8003dbe: 6078 str r0, [r7, #4]
- 8003dc0: 6039 str r1, [r7, #0]
+ 8003e34: b480 push {r7}
+ 8003e36: b087 sub sp, #28
+ 8003e38: af00 add r7, sp, #0
+ 8003e3a: 6078 str r0, [r7, #4]
+ 8003e3c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
- 8003dc2: 687b ldr r3, [r7, #4]
- 8003dc4: 6a1b ldr r3, [r3, #32]
- 8003dc6: f423 7280 bic.w r2, r3, #256 ; 0x100
- 8003dca: 687b ldr r3, [r7, #4]
- 8003dcc: 621a str r2, [r3, #32]
+ 8003e3e: 687b ldr r3, [r7, #4]
+ 8003e40: 6a1b ldr r3, [r3, #32]
+ 8003e42: f423 7280 bic.w r2, r3, #256 ; 0x100
+ 8003e46: 687b ldr r3, [r7, #4]
+ 8003e48: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8003dce: 687b ldr r3, [r7, #4]
- 8003dd0: 6a1b ldr r3, [r3, #32]
- 8003dd2: 617b str r3, [r7, #20]
+ 8003e4a: 687b ldr r3, [r7, #4]
+ 8003e4c: 6a1b ldr r3, [r3, #32]
+ 8003e4e: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8003dd4: 687b ldr r3, [r7, #4]
- 8003dd6: 685b ldr r3, [r3, #4]
- 8003dd8: 613b str r3, [r7, #16]
+ 8003e50: 687b ldr r3, [r7, #4]
+ 8003e52: 685b ldr r3, [r3, #4]
+ 8003e54: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
- 8003dda: 687b ldr r3, [r7, #4]
- 8003ddc: 69db ldr r3, [r3, #28]
- 8003dde: 60fb str r3, [r7, #12]
+ 8003e56: 687b ldr r3, [r7, #4]
+ 8003e58: 69db ldr r3, [r3, #28]
+ 8003e5a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
- 8003de0: 68fa ldr r2, [r7, #12]
- 8003de2: 4b2d ldr r3, [pc, #180] ; (8003e98 <TIM_OC3_SetConfig+0xe0>)
- 8003de4: 4013 ands r3, r2
- 8003de6: 60fb str r3, [r7, #12]
+ 8003e5c: 68fa ldr r2, [r7, #12]
+ 8003e5e: 4b2d ldr r3, [pc, #180] ; (8003f14 <TIM_OC3_SetConfig+0xe0>)
+ 8003e60: 4013 ands r3, r2
+ 8003e62: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
- 8003de8: 68fb ldr r3, [r7, #12]
- 8003dea: f023 0303 bic.w r3, r3, #3
- 8003dee: 60fb str r3, [r7, #12]
+ 8003e64: 68fb ldr r3, [r7, #12]
+ 8003e66: f023 0303 bic.w r3, r3, #3
+ 8003e6a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 8003df0: 683b ldr r3, [r7, #0]
- 8003df2: 681b ldr r3, [r3, #0]
- 8003df4: 68fa ldr r2, [r7, #12]
- 8003df6: 4313 orrs r3, r2
- 8003df8: 60fb str r3, [r7, #12]
+ 8003e6c: 683b ldr r3, [r7, #0]
+ 8003e6e: 681b ldr r3, [r3, #0]
+ 8003e70: 68fa ldr r2, [r7, #12]
+ 8003e72: 4313 orrs r3, r2
+ 8003e74: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
- 8003dfa: 697b ldr r3, [r7, #20]
- 8003dfc: f423 7300 bic.w r3, r3, #512 ; 0x200
- 8003e00: 617b str r3, [r7, #20]
+ 8003e76: 697b ldr r3, [r7, #20]
+ 8003e78: f423 7300 bic.w r3, r3, #512 ; 0x200
+ 8003e7c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
- 8003e02: 683b ldr r3, [r7, #0]
- 8003e04: 689b ldr r3, [r3, #8]
- 8003e06: 021b lsls r3, r3, #8
- 8003e08: 697a ldr r2, [r7, #20]
- 8003e0a: 4313 orrs r3, r2
- 8003e0c: 617b str r3, [r7, #20]
+ 8003e7e: 683b ldr r3, [r7, #0]
+ 8003e80: 689b ldr r3, [r3, #8]
+ 8003e82: 021b lsls r3, r3, #8
+ 8003e84: 697a ldr r2, [r7, #20]
+ 8003e86: 4313 orrs r3, r2
+ 8003e88: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- 8003e0e: 687b ldr r3, [r7, #4]
- 8003e10: 4a22 ldr r2, [pc, #136] ; (8003e9c <TIM_OC3_SetConfig+0xe4>)
- 8003e12: 4293 cmp r3, r2
- 8003e14: d003 beq.n 8003e1e <TIM_OC3_SetConfig+0x66>
- 8003e16: 687b ldr r3, [r7, #4]
- 8003e18: 4a21 ldr r2, [pc, #132] ; (8003ea0 <TIM_OC3_SetConfig+0xe8>)
- 8003e1a: 4293 cmp r3, r2
- 8003e1c: d10d bne.n 8003e3a <TIM_OC3_SetConfig+0x82>
+ 8003e8a: 687b ldr r3, [r7, #4]
+ 8003e8c: 4a22 ldr r2, [pc, #136] ; (8003f18 <TIM_OC3_SetConfig+0xe4>)
+ 8003e8e: 4293 cmp r3, r2
+ 8003e90: d003 beq.n 8003e9a <TIM_OC3_SetConfig+0x66>
+ 8003e92: 687b ldr r3, [r7, #4]
+ 8003e94: 4a21 ldr r2, [pc, #132] ; (8003f1c <TIM_OC3_SetConfig+0xe8>)
+ 8003e96: 4293 cmp r3, r2
+ 8003e98: d10d bne.n 8003eb6 <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
- 8003e1e: 697b ldr r3, [r7, #20]
- 8003e20: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8003e24: 617b str r3, [r7, #20]
+ 8003e9a: 697b ldr r3, [r7, #20]
+ 8003e9c: f423 6300 bic.w r3, r3, #2048 ; 0x800
+ 8003ea0: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
- 8003e26: 683b ldr r3, [r7, #0]
- 8003e28: 68db ldr r3, [r3, #12]
- 8003e2a: 021b lsls r3, r3, #8
- 8003e2c: 697a ldr r2, [r7, #20]
- 8003e2e: 4313 orrs r3, r2
- 8003e30: 617b str r3, [r7, #20]
+ 8003ea2: 683b ldr r3, [r7, #0]
+ 8003ea4: 68db ldr r3, [r3, #12]
+ 8003ea6: 021b lsls r3, r3, #8
+ 8003ea8: 697a ldr r2, [r7, #20]
+ 8003eaa: 4313 orrs r3, r2
+ 8003eac: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
- 8003e32: 697b ldr r3, [r7, #20]
- 8003e34: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 8003e38: 617b str r3, [r7, #20]
+ 8003eae: 697b ldr r3, [r7, #20]
+ 8003eb0: f423 6380 bic.w r3, r3, #1024 ; 0x400
+ 8003eb4: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003e3a: 687b ldr r3, [r7, #4]
- 8003e3c: 4a17 ldr r2, [pc, #92] ; (8003e9c <TIM_OC3_SetConfig+0xe4>)
- 8003e3e: 4293 cmp r3, r2
- 8003e40: d003 beq.n 8003e4a <TIM_OC3_SetConfig+0x92>
- 8003e42: 687b ldr r3, [r7, #4]
- 8003e44: 4a16 ldr r2, [pc, #88] ; (8003ea0 <TIM_OC3_SetConfig+0xe8>)
- 8003e46: 4293 cmp r3, r2
- 8003e48: d113 bne.n 8003e72 <TIM_OC3_SetConfig+0xba>
+ 8003eb6: 687b ldr r3, [r7, #4]
+ 8003eb8: 4a17 ldr r2, [pc, #92] ; (8003f18 <TIM_OC3_SetConfig+0xe4>)
+ 8003eba: 4293 cmp r3, r2
+ 8003ebc: d003 beq.n 8003ec6 <TIM_OC3_SetConfig+0x92>
+ 8003ebe: 687b ldr r3, [r7, #4]
+ 8003ec0: 4a16 ldr r2, [pc, #88] ; (8003f1c <TIM_OC3_SetConfig+0xe8>)
+ 8003ec2: 4293 cmp r3, r2
+ 8003ec4: d113 bne.n 8003eee <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
- 8003e4a: 693b ldr r3, [r7, #16]
- 8003e4c: f423 5380 bic.w r3, r3, #4096 ; 0x1000
- 8003e50: 613b str r3, [r7, #16]
+ 8003ec6: 693b ldr r3, [r7, #16]
+ 8003ec8: f423 5380 bic.w r3, r3, #4096 ; 0x1000
+ 8003ecc: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
- 8003e52: 693b ldr r3, [r7, #16]
- 8003e54: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8003e58: 613b str r3, [r7, #16]
+ 8003ece: 693b ldr r3, [r7, #16]
+ 8003ed0: f423 5300 bic.w r3, r3, #8192 ; 0x2000
+ 8003ed4: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
- 8003e5a: 683b ldr r3, [r7, #0]
- 8003e5c: 695b ldr r3, [r3, #20]
- 8003e5e: 011b lsls r3, r3, #4
- 8003e60: 693a ldr r2, [r7, #16]
- 8003e62: 4313 orrs r3, r2
- 8003e64: 613b str r3, [r7, #16]
+ 8003ed6: 683b ldr r3, [r7, #0]
+ 8003ed8: 695b ldr r3, [r3, #20]
+ 8003eda: 011b lsls r3, r3, #4
+ 8003edc: 693a ldr r2, [r7, #16]
+ 8003ede: 4313 orrs r3, r2
+ 8003ee0: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- 8003e66: 683b ldr r3, [r7, #0]
- 8003e68: 699b ldr r3, [r3, #24]
- 8003e6a: 011b lsls r3, r3, #4
- 8003e6c: 693a ldr r2, [r7, #16]
- 8003e6e: 4313 orrs r3, r2
- 8003e70: 613b str r3, [r7, #16]
+ 8003ee2: 683b ldr r3, [r7, #0]
+ 8003ee4: 699b ldr r3, [r3, #24]
+ 8003ee6: 011b lsls r3, r3, #4
+ 8003ee8: 693a ldr r2, [r7, #16]
+ 8003eea: 4313 orrs r3, r2
+ 8003eec: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8003e72: 687b ldr r3, [r7, #4]
- 8003e74: 693a ldr r2, [r7, #16]
- 8003e76: 605a str r2, [r3, #4]
+ 8003eee: 687b ldr r3, [r7, #4]
+ 8003ef0: 693a ldr r2, [r7, #16]
+ 8003ef2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
- 8003e78: 687b ldr r3, [r7, #4]
- 8003e7a: 68fa ldr r2, [r7, #12]
- 8003e7c: 61da str r2, [r3, #28]
+ 8003ef4: 687b ldr r3, [r7, #4]
+ 8003ef6: 68fa ldr r2, [r7, #12]
+ 8003ef8: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
- 8003e7e: 683b ldr r3, [r7, #0]
- 8003e80: 685a ldr r2, [r3, #4]
- 8003e82: 687b ldr r3, [r7, #4]
- 8003e84: 63da str r2, [r3, #60] ; 0x3c
+ 8003efa: 683b ldr r3, [r7, #0]
+ 8003efc: 685a ldr r2, [r3, #4]
+ 8003efe: 687b ldr r3, [r7, #4]
+ 8003f00: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8003e86: 687b ldr r3, [r7, #4]
- 8003e88: 697a ldr r2, [r7, #20]
- 8003e8a: 621a str r2, [r3, #32]
+ 8003f02: 687b ldr r3, [r7, #4]
+ 8003f04: 697a ldr r2, [r7, #20]
+ 8003f06: 621a str r2, [r3, #32]
}
- 8003e8c: bf00 nop
- 8003e8e: 371c adds r7, #28
- 8003e90: 46bd mov sp, r7
- 8003e92: f85d 7b04 ldr.w r7, [sp], #4
- 8003e96: 4770 bx lr
- 8003e98: fffeff8f .word 0xfffeff8f
- 8003e9c: 40010000 .word 0x40010000
- 8003ea0: 40010400 .word 0x40010400
-
-08003ea4 <TIM_OC4_SetConfig>:
+ 8003f08: bf00 nop
+ 8003f0a: 371c adds r7, #28
+ 8003f0c: 46bd mov sp, r7
+ 8003f0e: f85d 7b04 ldr.w r7, [sp], #4
+ 8003f12: 4770 bx lr
+ 8003f14: fffeff8f .word 0xfffeff8f
+ 8003f18: 40010000 .word 0x40010000
+ 8003f1c: 40010400 .word 0x40010400
+
+08003f20 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8003ea4: b480 push {r7}
- 8003ea6: b087 sub sp, #28
- 8003ea8: af00 add r7, sp, #0
- 8003eaa: 6078 str r0, [r7, #4]
- 8003eac: 6039 str r1, [r7, #0]
+ 8003f20: b480 push {r7}
+ 8003f22: b087 sub sp, #28
+ 8003f24: af00 add r7, sp, #0
+ 8003f26: 6078 str r0, [r7, #4]
+ 8003f28: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
- 8003eae: 687b ldr r3, [r7, #4]
- 8003eb0: 6a1b ldr r3, [r3, #32]
- 8003eb2: f423 5280 bic.w r2, r3, #4096 ; 0x1000
- 8003eb6: 687b ldr r3, [r7, #4]
- 8003eb8: 621a str r2, [r3, #32]
+ 8003f2a: 687b ldr r3, [r7, #4]
+ 8003f2c: 6a1b ldr r3, [r3, #32]
+ 8003f2e: f423 5280 bic.w r2, r3, #4096 ; 0x1000
+ 8003f32: 687b ldr r3, [r7, #4]
+ 8003f34: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8003eba: 687b ldr r3, [r7, #4]
- 8003ebc: 6a1b ldr r3, [r3, #32]
- 8003ebe: 613b str r3, [r7, #16]
+ 8003f36: 687b ldr r3, [r7, #4]
+ 8003f38: 6a1b ldr r3, [r3, #32]
+ 8003f3a: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8003ec0: 687b ldr r3, [r7, #4]
- 8003ec2: 685b ldr r3, [r3, #4]
- 8003ec4: 617b str r3, [r7, #20]
+ 8003f3c: 687b ldr r3, [r7, #4]
+ 8003f3e: 685b ldr r3, [r3, #4]
+ 8003f40: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
- 8003ec6: 687b ldr r3, [r7, #4]
- 8003ec8: 69db ldr r3, [r3, #28]
- 8003eca: 60fb str r3, [r7, #12]
+ 8003f42: 687b ldr r3, [r7, #4]
+ 8003f44: 69db ldr r3, [r3, #28]
+ 8003f46: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
- 8003ecc: 68fa ldr r2, [r7, #12]
- 8003ece: 4b1e ldr r3, [pc, #120] ; (8003f48 <TIM_OC4_SetConfig+0xa4>)
- 8003ed0: 4013 ands r3, r2
- 8003ed2: 60fb str r3, [r7, #12]
+ 8003f48: 68fa ldr r2, [r7, #12]
+ 8003f4a: 4b1e ldr r3, [pc, #120] ; (8003fc4 <TIM_OC4_SetConfig+0xa4>)
+ 8003f4c: 4013 ands r3, r2
+ 8003f4e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
- 8003ed4: 68fb ldr r3, [r7, #12]
- 8003ed6: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8003eda: 60fb str r3, [r7, #12]
+ 8003f50: 68fb ldr r3, [r7, #12]
+ 8003f52: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8003f56: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 8003edc: 683b ldr r3, [r7, #0]
- 8003ede: 681b ldr r3, [r3, #0]
- 8003ee0: 021b lsls r3, r3, #8
- 8003ee2: 68fa ldr r2, [r7, #12]
- 8003ee4: 4313 orrs r3, r2
- 8003ee6: 60fb str r3, [r7, #12]
+ 8003f58: 683b ldr r3, [r7, #0]
+ 8003f5a: 681b ldr r3, [r3, #0]
+ 8003f5c: 021b lsls r3, r3, #8
+ 8003f5e: 68fa ldr r2, [r7, #12]
+ 8003f60: 4313 orrs r3, r2
+ 8003f62: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
- 8003ee8: 693b ldr r3, [r7, #16]
- 8003eea: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8003eee: 613b str r3, [r7, #16]
+ 8003f64: 693b ldr r3, [r7, #16]
+ 8003f66: f423 5300 bic.w r3, r3, #8192 ; 0x2000
+ 8003f6a: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
- 8003ef0: 683b ldr r3, [r7, #0]
- 8003ef2: 689b ldr r3, [r3, #8]
- 8003ef4: 031b lsls r3, r3, #12
- 8003ef6: 693a ldr r2, [r7, #16]
- 8003ef8: 4313 orrs r3, r2
- 8003efa: 613b str r3, [r7, #16]
+ 8003f6c: 683b ldr r3, [r7, #0]
+ 8003f6e: 689b ldr r3, [r3, #8]
+ 8003f70: 031b lsls r3, r3, #12
+ 8003f72: 693a ldr r2, [r7, #16]
+ 8003f74: 4313 orrs r3, r2
+ 8003f76: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003efc: 687b ldr r3, [r7, #4]
- 8003efe: 4a13 ldr r2, [pc, #76] ; (8003f4c <TIM_OC4_SetConfig+0xa8>)
- 8003f00: 4293 cmp r3, r2
- 8003f02: d003 beq.n 8003f0c <TIM_OC4_SetConfig+0x68>
- 8003f04: 687b ldr r3, [r7, #4]
- 8003f06: 4a12 ldr r2, [pc, #72] ; (8003f50 <TIM_OC4_SetConfig+0xac>)
- 8003f08: 4293 cmp r3, r2
- 8003f0a: d109 bne.n 8003f20 <TIM_OC4_SetConfig+0x7c>
+ 8003f78: 687b ldr r3, [r7, #4]
+ 8003f7a: 4a13 ldr r2, [pc, #76] ; (8003fc8 <TIM_OC4_SetConfig+0xa8>)
+ 8003f7c: 4293 cmp r3, r2
+ 8003f7e: d003 beq.n 8003f88 <TIM_OC4_SetConfig+0x68>
+ 8003f80: 687b ldr r3, [r7, #4]
+ 8003f82: 4a12 ldr r2, [pc, #72] ; (8003fcc <TIM_OC4_SetConfig+0xac>)
+ 8003f84: 4293 cmp r3, r2
+ 8003f86: d109 bne.n 8003f9c <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
- 8003f0c: 697b ldr r3, [r7, #20]
- 8003f0e: f423 4380 bic.w r3, r3, #16384 ; 0x4000
- 8003f12: 617b str r3, [r7, #20]
+ 8003f88: 697b ldr r3, [r7, #20]
+ 8003f8a: f423 4380 bic.w r3, r3, #16384 ; 0x4000
+ 8003f8e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
- 8003f14: 683b ldr r3, [r7, #0]
- 8003f16: 695b ldr r3, [r3, #20]
- 8003f18: 019b lsls r3, r3, #6
- 8003f1a: 697a ldr r2, [r7, #20]
- 8003f1c: 4313 orrs r3, r2
- 8003f1e: 617b str r3, [r7, #20]
+ 8003f90: 683b ldr r3, [r7, #0]
+ 8003f92: 695b ldr r3, [r3, #20]
+ 8003f94: 019b lsls r3, r3, #6
+ 8003f96: 697a ldr r2, [r7, #20]
+ 8003f98: 4313 orrs r3, r2
+ 8003f9a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8003f20: 687b ldr r3, [r7, #4]
- 8003f22: 697a ldr r2, [r7, #20]
- 8003f24: 605a str r2, [r3, #4]
+ 8003f9c: 687b ldr r3, [r7, #4]
+ 8003f9e: 697a ldr r2, [r7, #20]
+ 8003fa0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
- 8003f26: 687b ldr r3, [r7, #4]
- 8003f28: 68fa ldr r2, [r7, #12]
- 8003f2a: 61da str r2, [r3, #28]
+ 8003fa2: 687b ldr r3, [r7, #4]
+ 8003fa4: 68fa ldr r2, [r7, #12]
+ 8003fa6: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
- 8003f2c: 683b ldr r3, [r7, #0]
- 8003f2e: 685a ldr r2, [r3, #4]
- 8003f30: 687b ldr r3, [r7, #4]
- 8003f32: 641a str r2, [r3, #64] ; 0x40
+ 8003fa8: 683b ldr r3, [r7, #0]
+ 8003faa: 685a ldr r2, [r3, #4]
+ 8003fac: 687b ldr r3, [r7, #4]
+ 8003fae: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8003f34: 687b ldr r3, [r7, #4]
- 8003f36: 693a ldr r2, [r7, #16]
- 8003f38: 621a str r2, [r3, #32]
+ 8003fb0: 687b ldr r3, [r7, #4]
+ 8003fb2: 693a ldr r2, [r7, #16]
+ 8003fb4: 621a str r2, [r3, #32]
}
- 8003f3a: bf00 nop
- 8003f3c: 371c adds r7, #28
- 8003f3e: 46bd mov sp, r7
- 8003f40: f85d 7b04 ldr.w r7, [sp], #4
- 8003f44: 4770 bx lr
- 8003f46: bf00 nop
- 8003f48: feff8fff .word 0xfeff8fff
- 8003f4c: 40010000 .word 0x40010000
- 8003f50: 40010400 .word 0x40010400
-
-08003f54 <TIM_OC5_SetConfig>:
+ 8003fb6: bf00 nop
+ 8003fb8: 371c adds r7, #28
+ 8003fba: 46bd mov sp, r7
+ 8003fbc: f85d 7b04 ldr.w r7, [sp], #4
+ 8003fc0: 4770 bx lr
+ 8003fc2: bf00 nop
+ 8003fc4: feff8fff .word 0xfeff8fff
+ 8003fc8: 40010000 .word 0x40010000
+ 8003fcc: 40010400 .word 0x40010400
+
+08003fd0 <TIM_OC5_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
- 8003f54: b480 push {r7}
- 8003f56: b087 sub sp, #28
- 8003f58: af00 add r7, sp, #0
- 8003f5a: 6078 str r0, [r7, #4]
- 8003f5c: 6039 str r1, [r7, #0]
+ 8003fd0: b480 push {r7}
+ 8003fd2: b087 sub sp, #28
+ 8003fd4: af00 add r7, sp, #0
+ 8003fd6: 6078 str r0, [r7, #4]
+ 8003fd8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
- 8003f5e: 687b ldr r3, [r7, #4]
- 8003f60: 6a1b ldr r3, [r3, #32]
- 8003f62: f423 3280 bic.w r2, r3, #65536 ; 0x10000
- 8003f66: 687b ldr r3, [r7, #4]
- 8003f68: 621a str r2, [r3, #32]
+ 8003fda: 687b ldr r3, [r7, #4]
+ 8003fdc: 6a1b ldr r3, [r3, #32]
+ 8003fde: f423 3280 bic.w r2, r3, #65536 ; 0x10000
+ 8003fe2: 687b ldr r3, [r7, #4]
+ 8003fe4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8003f6a: 687b ldr r3, [r7, #4]
- 8003f6c: 6a1b ldr r3, [r3, #32]
- 8003f6e: 613b str r3, [r7, #16]
+ 8003fe6: 687b ldr r3, [r7, #4]
+ 8003fe8: 6a1b ldr r3, [r3, #32]
+ 8003fea: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8003f70: 687b ldr r3, [r7, #4]
- 8003f72: 685b ldr r3, [r3, #4]
- 8003f74: 617b str r3, [r7, #20]
+ 8003fec: 687b ldr r3, [r7, #4]
+ 8003fee: 685b ldr r3, [r3, #4]
+ 8003ff0: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
- 8003f76: 687b ldr r3, [r7, #4]
- 8003f78: 6d5b ldr r3, [r3, #84] ; 0x54
- 8003f7a: 60fb str r3, [r7, #12]
+ 8003ff2: 687b ldr r3, [r7, #4]
+ 8003ff4: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8003ff6: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
- 8003f7c: 68fa ldr r2, [r7, #12]
- 8003f7e: 4b1b ldr r3, [pc, #108] ; (8003fec <TIM_OC5_SetConfig+0x98>)
- 8003f80: 4013 ands r3, r2
- 8003f82: 60fb str r3, [r7, #12]
+ 8003ff8: 68fa ldr r2, [r7, #12]
+ 8003ffa: 4b1b ldr r3, [pc, #108] ; (8004068 <TIM_OC5_SetConfig+0x98>)
+ 8003ffc: 4013 ands r3, r2
+ 8003ffe: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 8003f84: 683b ldr r3, [r7, #0]
- 8003f86: 681b ldr r3, [r3, #0]
- 8003f88: 68fa ldr r2, [r7, #12]
- 8003f8a: 4313 orrs r3, r2
- 8003f8c: 60fb str r3, [r7, #12]
+ 8004000: 683b ldr r3, [r7, #0]
+ 8004002: 681b ldr r3, [r3, #0]
+ 8004004: 68fa ldr r2, [r7, #12]
+ 8004006: 4313 orrs r3, r2
+ 8004008: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
- 8003f8e: 693b ldr r3, [r7, #16]
- 8003f90: f423 3300 bic.w r3, r3, #131072 ; 0x20000
- 8003f94: 613b str r3, [r7, #16]
+ 800400a: 693b ldr r3, [r7, #16]
+ 800400c: f423 3300 bic.w r3, r3, #131072 ; 0x20000
+ 8004010: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
- 8003f96: 683b ldr r3, [r7, #0]
- 8003f98: 689b ldr r3, [r3, #8]
- 8003f9a: 041b lsls r3, r3, #16
- 8003f9c: 693a ldr r2, [r7, #16]
- 8003f9e: 4313 orrs r3, r2
- 8003fa0: 613b str r3, [r7, #16]
+ 8004012: 683b ldr r3, [r7, #0]
+ 8004014: 689b ldr r3, [r3, #8]
+ 8004016: 041b lsls r3, r3, #16
+ 8004018: 693a ldr r2, [r7, #16]
+ 800401a: 4313 orrs r3, r2
+ 800401c: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8003fa2: 687b ldr r3, [r7, #4]
- 8003fa4: 4a12 ldr r2, [pc, #72] ; (8003ff0 <TIM_OC5_SetConfig+0x9c>)
- 8003fa6: 4293 cmp r3, r2
- 8003fa8: d003 beq.n 8003fb2 <TIM_OC5_SetConfig+0x5e>
- 8003faa: 687b ldr r3, [r7, #4]
- 8003fac: 4a11 ldr r2, [pc, #68] ; (8003ff4 <TIM_OC5_SetConfig+0xa0>)
- 8003fae: 4293 cmp r3, r2
- 8003fb0: d109 bne.n 8003fc6 <TIM_OC5_SetConfig+0x72>
+ 800401e: 687b ldr r3, [r7, #4]
+ 8004020: 4a12 ldr r2, [pc, #72] ; (800406c <TIM_OC5_SetConfig+0x9c>)
+ 8004022: 4293 cmp r3, r2
+ 8004024: d003 beq.n 800402e <TIM_OC5_SetConfig+0x5e>
+ 8004026: 687b ldr r3, [r7, #4]
+ 8004028: 4a11 ldr r2, [pc, #68] ; (8004070 <TIM_OC5_SetConfig+0xa0>)
+ 800402a: 4293 cmp r3, r2
+ 800402c: d109 bne.n 8004042 <TIM_OC5_SetConfig+0x72>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
- 8003fb2: 697b ldr r3, [r7, #20]
- 8003fb4: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8003fb8: 617b str r3, [r7, #20]
+ 800402e: 697b ldr r3, [r7, #20]
+ 8004030: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8004034: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
- 8003fba: 683b ldr r3, [r7, #0]
- 8003fbc: 695b ldr r3, [r3, #20]
- 8003fbe: 021b lsls r3, r3, #8
- 8003fc0: 697a ldr r2, [r7, #20]
- 8003fc2: 4313 orrs r3, r2
- 8003fc4: 617b str r3, [r7, #20]
+ 8004036: 683b ldr r3, [r7, #0]
+ 8004038: 695b ldr r3, [r3, #20]
+ 800403a: 021b lsls r3, r3, #8
+ 800403c: 697a ldr r2, [r7, #20]
+ 800403e: 4313 orrs r3, r2
+ 8004040: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8003fc6: 687b ldr r3, [r7, #4]
- 8003fc8: 697a ldr r2, [r7, #20]
- 8003fca: 605a str r2, [r3, #4]
+ 8004042: 687b ldr r3, [r7, #4]
+ 8004044: 697a ldr r2, [r7, #20]
+ 8004046: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
- 8003fcc: 687b ldr r3, [r7, #4]
- 8003fce: 68fa ldr r2, [r7, #12]
- 8003fd0: 655a str r2, [r3, #84] ; 0x54
+ 8004048: 687b ldr r3, [r7, #4]
+ 800404a: 68fa ldr r2, [r7, #12]
+ 800404c: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
- 8003fd2: 683b ldr r3, [r7, #0]
- 8003fd4: 685a ldr r2, [r3, #4]
- 8003fd6: 687b ldr r3, [r7, #4]
- 8003fd8: 659a str r2, [r3, #88] ; 0x58
+ 800404e: 683b ldr r3, [r7, #0]
+ 8004050: 685a ldr r2, [r3, #4]
+ 8004052: 687b ldr r3, [r7, #4]
+ 8004054: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8003fda: 687b ldr r3, [r7, #4]
- 8003fdc: 693a ldr r2, [r7, #16]
- 8003fde: 621a str r2, [r3, #32]
+ 8004056: 687b ldr r3, [r7, #4]
+ 8004058: 693a ldr r2, [r7, #16]
+ 800405a: 621a str r2, [r3, #32]
}
- 8003fe0: bf00 nop
- 8003fe2: 371c adds r7, #28
- 8003fe4: 46bd mov sp, r7
- 8003fe6: f85d 7b04 ldr.w r7, [sp], #4
- 8003fea: 4770 bx lr
- 8003fec: fffeff8f .word 0xfffeff8f
- 8003ff0: 40010000 .word 0x40010000
- 8003ff4: 40010400 .word 0x40010400
-
-08003ff8 <TIM_OC6_SetConfig>:
+ 800405c: bf00 nop
+ 800405e: 371c adds r7, #28
+ 8004060: 46bd mov sp, r7
+ 8004062: f85d 7b04 ldr.w r7, [sp], #4
+ 8004066: 4770 bx lr
+ 8004068: fffeff8f .word 0xfffeff8f
+ 800406c: 40010000 .word 0x40010000
+ 8004070: 40010400 .word 0x40010400
+
+08004074 <TIM_OC6_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
- 8003ff8: b480 push {r7}
- 8003ffa: b087 sub sp, #28
- 8003ffc: af00 add r7, sp, #0
- 8003ffe: 6078 str r0, [r7, #4]
- 8004000: 6039 str r1, [r7, #0]
+ 8004074: b480 push {r7}
+ 8004076: b087 sub sp, #28
+ 8004078: af00 add r7, sp, #0
+ 800407a: 6078 str r0, [r7, #4]
+ 800407c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
- 8004002: 687b ldr r3, [r7, #4]
- 8004004: 6a1b ldr r3, [r3, #32]
- 8004006: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
- 800400a: 687b ldr r3, [r7, #4]
- 800400c: 621a str r2, [r3, #32]
+ 800407e: 687b ldr r3, [r7, #4]
+ 8004080: 6a1b ldr r3, [r3, #32]
+ 8004082: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
+ 8004086: 687b ldr r3, [r7, #4]
+ 8004088: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 800400e: 687b ldr r3, [r7, #4]
- 8004010: 6a1b ldr r3, [r3, #32]
- 8004012: 613b str r3, [r7, #16]
+ 800408a: 687b ldr r3, [r7, #4]
+ 800408c: 6a1b ldr r3, [r3, #32]
+ 800408e: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8004014: 687b ldr r3, [r7, #4]
- 8004016: 685b ldr r3, [r3, #4]
- 8004018: 617b str r3, [r7, #20]
+ 8004090: 687b ldr r3, [r7, #4]
+ 8004092: 685b ldr r3, [r3, #4]
+ 8004094: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
- 800401a: 687b ldr r3, [r7, #4]
- 800401c: 6d5b ldr r3, [r3, #84] ; 0x54
- 800401e: 60fb str r3, [r7, #12]
+ 8004096: 687b ldr r3, [r7, #4]
+ 8004098: 6d5b ldr r3, [r3, #84] ; 0x54
+ 800409a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
- 8004020: 68fa ldr r2, [r7, #12]
- 8004022: 4b1c ldr r3, [pc, #112] ; (8004094 <TIM_OC6_SetConfig+0x9c>)
- 8004024: 4013 ands r3, r2
- 8004026: 60fb str r3, [r7, #12]
+ 800409c: 68fa ldr r2, [r7, #12]
+ 800409e: 4b1c ldr r3, [pc, #112] ; (8004110 <TIM_OC6_SetConfig+0x9c>)
+ 80040a0: 4013 ands r3, r2
+ 80040a2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 8004028: 683b ldr r3, [r7, #0]
- 800402a: 681b ldr r3, [r3, #0]
- 800402c: 021b lsls r3, r3, #8
- 800402e: 68fa ldr r2, [r7, #12]
- 8004030: 4313 orrs r3, r2
- 8004032: 60fb str r3, [r7, #12]
+ 80040a4: 683b ldr r3, [r7, #0]
+ 80040a6: 681b ldr r3, [r3, #0]
+ 80040a8: 021b lsls r3, r3, #8
+ 80040aa: 68fa ldr r2, [r7, #12]
+ 80040ac: 4313 orrs r3, r2
+ 80040ae: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- 8004034: 693b ldr r3, [r7, #16]
- 8004036: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
- 800403a: 613b str r3, [r7, #16]
+ 80040b0: 693b ldr r3, [r7, #16]
+ 80040b2: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
+ 80040b6: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
- 800403c: 683b ldr r3, [r7, #0]
- 800403e: 689b ldr r3, [r3, #8]
- 8004040: 051b lsls r3, r3, #20
- 8004042: 693a ldr r2, [r7, #16]
- 8004044: 4313 orrs r3, r2
- 8004046: 613b str r3, [r7, #16]
+ 80040b8: 683b ldr r3, [r7, #0]
+ 80040ba: 689b ldr r3, [r3, #8]
+ 80040bc: 051b lsls r3, r3, #20
+ 80040be: 693a ldr r2, [r7, #16]
+ 80040c0: 4313 orrs r3, r2
+ 80040c2: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8004048: 687b ldr r3, [r7, #4]
- 800404a: 4a13 ldr r2, [pc, #76] ; (8004098 <TIM_OC6_SetConfig+0xa0>)
- 800404c: 4293 cmp r3, r2
- 800404e: d003 beq.n 8004058 <TIM_OC6_SetConfig+0x60>
- 8004050: 687b ldr r3, [r7, #4]
- 8004052: 4a12 ldr r2, [pc, #72] ; (800409c <TIM_OC6_SetConfig+0xa4>)
- 8004054: 4293 cmp r3, r2
- 8004056: d109 bne.n 800406c <TIM_OC6_SetConfig+0x74>
+ 80040c4: 687b ldr r3, [r7, #4]
+ 80040c6: 4a13 ldr r2, [pc, #76] ; (8004114 <TIM_OC6_SetConfig+0xa0>)
+ 80040c8: 4293 cmp r3, r2
+ 80040ca: d003 beq.n 80040d4 <TIM_OC6_SetConfig+0x60>
+ 80040cc: 687b ldr r3, [r7, #4]
+ 80040ce: 4a12 ldr r2, [pc, #72] ; (8004118 <TIM_OC6_SetConfig+0xa4>)
+ 80040d0: 4293 cmp r3, r2
+ 80040d2: d109 bne.n 80040e8 <TIM_OC6_SetConfig+0x74>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
- 8004058: 697b ldr r3, [r7, #20]
- 800405a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 800405e: 617b str r3, [r7, #20]
+ 80040d4: 697b ldr r3, [r7, #20]
+ 80040d6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 80040da: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
- 8004060: 683b ldr r3, [r7, #0]
- 8004062: 695b ldr r3, [r3, #20]
- 8004064: 029b lsls r3, r3, #10
- 8004066: 697a ldr r2, [r7, #20]
- 8004068: 4313 orrs r3, r2
- 800406a: 617b str r3, [r7, #20]
+ 80040dc: 683b ldr r3, [r7, #0]
+ 80040de: 695b ldr r3, [r3, #20]
+ 80040e0: 029b lsls r3, r3, #10
+ 80040e2: 697a ldr r2, [r7, #20]
+ 80040e4: 4313 orrs r3, r2
+ 80040e6: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 800406c: 687b ldr r3, [r7, #4]
- 800406e: 697a ldr r2, [r7, #20]
- 8004070: 605a str r2, [r3, #4]
+ 80040e8: 687b ldr r3, [r7, #4]
+ 80040ea: 697a ldr r2, [r7, #20]
+ 80040ec: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
- 8004072: 687b ldr r3, [r7, #4]
- 8004074: 68fa ldr r2, [r7, #12]
- 8004076: 655a str r2, [r3, #84] ; 0x54
+ 80040ee: 687b ldr r3, [r7, #4]
+ 80040f0: 68fa ldr r2, [r7, #12]
+ 80040f2: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
- 8004078: 683b ldr r3, [r7, #0]
- 800407a: 685a ldr r2, [r3, #4]
- 800407c: 687b ldr r3, [r7, #4]
- 800407e: 65da str r2, [r3, #92] ; 0x5c
+ 80040f4: 683b ldr r3, [r7, #0]
+ 80040f6: 685a ldr r2, [r3, #4]
+ 80040f8: 687b ldr r3, [r7, #4]
+ 80040fa: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8004080: 687b ldr r3, [r7, #4]
- 8004082: 693a ldr r2, [r7, #16]
- 8004084: 621a str r2, [r3, #32]
+ 80040fc: 687b ldr r3, [r7, #4]
+ 80040fe: 693a ldr r2, [r7, #16]
+ 8004100: 621a str r2, [r3, #32]
}
- 8004086: bf00 nop
- 8004088: 371c adds r7, #28
- 800408a: 46bd mov sp, r7
- 800408c: f85d 7b04 ldr.w r7, [sp], #4
- 8004090: 4770 bx lr
- 8004092: bf00 nop
- 8004094: feff8fff .word 0xfeff8fff
- 8004098: 40010000 .word 0x40010000
- 800409c: 40010400 .word 0x40010400
-
-080040a0 <TIM_TI1_ConfigInputStage>:
+ 8004102: bf00 nop
+ 8004104: 371c adds r7, #28
+ 8004106: 46bd mov sp, r7
+ 8004108: f85d 7b04 ldr.w r7, [sp], #4
+ 800410c: 4770 bx lr
+ 800410e: bf00 nop
+ 8004110: feff8fff .word 0xfeff8fff
+ 8004114: 40010000 .word 0x40010000
+ 8004118: 40010400 .word 0x40010400
+
+0800411c <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- 80040a0: b480 push {r7}
- 80040a2: b087 sub sp, #28
- 80040a4: af00 add r7, sp, #0
- 80040a6: 60f8 str r0, [r7, #12]
- 80040a8: 60b9 str r1, [r7, #8]
- 80040aa: 607a str r2, [r7, #4]
+ 800411c: b480 push {r7}
+ 800411e: b087 sub sp, #28
+ 8004120: af00 add r7, sp, #0
+ 8004122: 60f8 str r0, [r7, #12]
+ 8004124: 60b9 str r1, [r7, #8]
+ 8004126: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
- 80040ac: 68fb ldr r3, [r7, #12]
- 80040ae: 6a1b ldr r3, [r3, #32]
- 80040b0: 617b str r3, [r7, #20]
+ 8004128: 68fb ldr r3, [r7, #12]
+ 800412a: 6a1b ldr r3, [r3, #32]
+ 800412c: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
- 80040b2: 68fb ldr r3, [r7, #12]
- 80040b4: 6a1b ldr r3, [r3, #32]
- 80040b6: f023 0201 bic.w r2, r3, #1
- 80040ba: 68fb ldr r3, [r7, #12]
- 80040bc: 621a str r2, [r3, #32]
+ 800412e: 68fb ldr r3, [r7, #12]
+ 8004130: 6a1b ldr r3, [r3, #32]
+ 8004132: f023 0201 bic.w r2, r3, #1
+ 8004136: 68fb ldr r3, [r7, #12]
+ 8004138: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
- 80040be: 68fb ldr r3, [r7, #12]
- 80040c0: 699b ldr r3, [r3, #24]
- 80040c2: 613b str r3, [r7, #16]
+ 800413a: 68fb ldr r3, [r7, #12]
+ 800413c: 699b ldr r3, [r3, #24]
+ 800413e: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 80040c4: 693b ldr r3, [r7, #16]
- 80040c6: f023 03f0 bic.w r3, r3, #240 ; 0xf0
- 80040ca: 613b str r3, [r7, #16]
+ 8004140: 693b ldr r3, [r7, #16]
+ 8004142: f023 03f0 bic.w r3, r3, #240 ; 0xf0
+ 8004146: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
- 80040cc: 687b ldr r3, [r7, #4]
- 80040ce: 011b lsls r3, r3, #4
- 80040d0: 693a ldr r2, [r7, #16]
- 80040d2: 4313 orrs r3, r2
- 80040d4: 613b str r3, [r7, #16]
+ 8004148: 687b ldr r3, [r7, #4]
+ 800414a: 011b lsls r3, r3, #4
+ 800414c: 693a ldr r2, [r7, #16]
+ 800414e: 4313 orrs r3, r2
+ 8004150: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 80040d6: 697b ldr r3, [r7, #20]
- 80040d8: f023 030a bic.w r3, r3, #10
- 80040dc: 617b str r3, [r7, #20]
+ 8004152: 697b ldr r3, [r7, #20]
+ 8004154: f023 030a bic.w r3, r3, #10
+ 8004158: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
- 80040de: 697a ldr r2, [r7, #20]
- 80040e0: 68bb ldr r3, [r7, #8]
- 80040e2: 4313 orrs r3, r2
- 80040e4: 617b str r3, [r7, #20]
+ 800415a: 697a ldr r2, [r7, #20]
+ 800415c: 68bb ldr r3, [r7, #8]
+ 800415e: 4313 orrs r3, r2
+ 8004160: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
- 80040e6: 68fb ldr r3, [r7, #12]
- 80040e8: 693a ldr r2, [r7, #16]
- 80040ea: 619a str r2, [r3, #24]
+ 8004162: 68fb ldr r3, [r7, #12]
+ 8004164: 693a ldr r2, [r7, #16]
+ 8004166: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
- 80040ec: 68fb ldr r3, [r7, #12]
- 80040ee: 697a ldr r2, [r7, #20]
- 80040f0: 621a str r2, [r3, #32]
+ 8004168: 68fb ldr r3, [r7, #12]
+ 800416a: 697a ldr r2, [r7, #20]
+ 800416c: 621a str r2, [r3, #32]
}
- 80040f2: bf00 nop
- 80040f4: 371c adds r7, #28
- 80040f6: 46bd mov sp, r7
- 80040f8: f85d 7b04 ldr.w r7, [sp], #4
- 80040fc: 4770 bx lr
+ 800416e: bf00 nop
+ 8004170: 371c adds r7, #28
+ 8004172: 46bd mov sp, r7
+ 8004174: f85d 7b04 ldr.w r7, [sp], #4
+ 8004178: 4770 bx lr
-080040fe <TIM_TI2_ConfigInputStage>:
+0800417a <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- 80040fe: b480 push {r7}
- 8004100: b087 sub sp, #28
- 8004102: af00 add r7, sp, #0
- 8004104: 60f8 str r0, [r7, #12]
- 8004106: 60b9 str r1, [r7, #8]
- 8004108: 607a str r2, [r7, #4]
+ 800417a: b480 push {r7}
+ 800417c: b087 sub sp, #28
+ 800417e: af00 add r7, sp, #0
+ 8004180: 60f8 str r0, [r7, #12]
+ 8004182: 60b9 str r1, [r7, #8]
+ 8004184: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- 800410a: 68fb ldr r3, [r7, #12]
- 800410c: 6a1b ldr r3, [r3, #32]
- 800410e: f023 0210 bic.w r2, r3, #16
- 8004112: 68fb ldr r3, [r7, #12]
- 8004114: 621a str r2, [r3, #32]
+ 8004186: 68fb ldr r3, [r7, #12]
+ 8004188: 6a1b ldr r3, [r3, #32]
+ 800418a: f023 0210 bic.w r2, r3, #16
+ 800418e: 68fb ldr r3, [r7, #12]
+ 8004190: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
- 8004116: 68fb ldr r3, [r7, #12]
- 8004118: 699b ldr r3, [r3, #24]
- 800411a: 617b str r3, [r7, #20]
+ 8004192: 68fb ldr r3, [r7, #12]
+ 8004194: 699b ldr r3, [r3, #24]
+ 8004196: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
- 800411c: 68fb ldr r3, [r7, #12]
- 800411e: 6a1b ldr r3, [r3, #32]
- 8004120: 613b str r3, [r7, #16]
+ 8004198: 68fb ldr r3, [r7, #12]
+ 800419a: 6a1b ldr r3, [r3, #32]
+ 800419c: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 8004122: 697b ldr r3, [r7, #20]
- 8004124: f423 4370 bic.w r3, r3, #61440 ; 0xf000
- 8004128: 617b str r3, [r7, #20]
+ 800419e: 697b ldr r3, [r7, #20]
+ 80041a0: f423 4370 bic.w r3, r3, #61440 ; 0xf000
+ 80041a4: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
- 800412a: 687b ldr r3, [r7, #4]
- 800412c: 031b lsls r3, r3, #12
- 800412e: 697a ldr r2, [r7, #20]
- 8004130: 4313 orrs r3, r2
- 8004132: 617b str r3, [r7, #20]
+ 80041a6: 687b ldr r3, [r7, #4]
+ 80041a8: 031b lsls r3, r3, #12
+ 80041aa: 697a ldr r2, [r7, #20]
+ 80041ac: 4313 orrs r3, r2
+ 80041ae: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 8004134: 693b ldr r3, [r7, #16]
- 8004136: f023 03a0 bic.w r3, r3, #160 ; 0xa0
- 800413a: 613b str r3, [r7, #16]
+ 80041b0: 693b ldr r3, [r7, #16]
+ 80041b2: f023 03a0 bic.w r3, r3, #160 ; 0xa0
+ 80041b6: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
- 800413c: 68bb ldr r3, [r7, #8]
- 800413e: 011b lsls r3, r3, #4
- 8004140: 693a ldr r2, [r7, #16]
- 8004142: 4313 orrs r3, r2
- 8004144: 613b str r3, [r7, #16]
+ 80041b8: 68bb ldr r3, [r7, #8]
+ 80041ba: 011b lsls r3, r3, #4
+ 80041bc: 693a ldr r2, [r7, #16]
+ 80041be: 4313 orrs r3, r2
+ 80041c0: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
- 8004146: 68fb ldr r3, [r7, #12]
- 8004148: 697a ldr r2, [r7, #20]
- 800414a: 619a str r2, [r3, #24]
+ 80041c2: 68fb ldr r3, [r7, #12]
+ 80041c4: 697a ldr r2, [r7, #20]
+ 80041c6: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
- 800414c: 68fb ldr r3, [r7, #12]
- 800414e: 693a ldr r2, [r7, #16]
- 8004150: 621a str r2, [r3, #32]
+ 80041c8: 68fb ldr r3, [r7, #12]
+ 80041ca: 693a ldr r2, [r7, #16]
+ 80041cc: 621a str r2, [r3, #32]
}
- 8004152: bf00 nop
- 8004154: 371c adds r7, #28
- 8004156: 46bd mov sp, r7
- 8004158: f85d 7b04 ldr.w r7, [sp], #4
- 800415c: 4770 bx lr
+ 80041ce: bf00 nop
+ 80041d0: 371c adds r7, #28
+ 80041d2: 46bd mov sp, r7
+ 80041d4: f85d 7b04 ldr.w r7, [sp], #4
+ 80041d8: 4770 bx lr
-0800415e <TIM_ITRx_SetConfig>:
+080041da <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
- 800415e: b480 push {r7}
- 8004160: b085 sub sp, #20
- 8004162: af00 add r7, sp, #0
- 8004164: 6078 str r0, [r7, #4]
- 8004166: 6039 str r1, [r7, #0]
+ 80041da: b480 push {r7}
+ 80041dc: b085 sub sp, #20
+ 80041de: af00 add r7, sp, #0
+ 80041e0: 6078 str r0, [r7, #4]
+ 80041e2: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
- 8004168: 687b ldr r3, [r7, #4]
- 800416a: 689b ldr r3, [r3, #8]
- 800416c: 60fb str r3, [r7, #12]
+ 80041e4: 687b ldr r3, [r7, #4]
+ 80041e6: 689b ldr r3, [r3, #8]
+ 80041e8: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
- 800416e: 68fb ldr r3, [r7, #12]
- 8004170: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8004174: 60fb str r3, [r7, #12]
+ 80041ea: 68fb ldr r3, [r7, #12]
+ 80041ec: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 80041f0: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 8004176: 683a ldr r2, [r7, #0]
- 8004178: 68fb ldr r3, [r7, #12]
- 800417a: 4313 orrs r3, r2
- 800417c: f043 0307 orr.w r3, r3, #7
- 8004180: 60fb str r3, [r7, #12]
+ 80041f2: 683a ldr r2, [r7, #0]
+ 80041f4: 68fb ldr r3, [r7, #12]
+ 80041f6: 4313 orrs r3, r2
+ 80041f8: f043 0307 orr.w r3, r3, #7
+ 80041fc: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
- 8004182: 687b ldr r3, [r7, #4]
- 8004184: 68fa ldr r2, [r7, #12]
- 8004186: 609a str r2, [r3, #8]
+ 80041fe: 687b ldr r3, [r7, #4]
+ 8004200: 68fa ldr r2, [r7, #12]
+ 8004202: 609a str r2, [r3, #8]
}
- 8004188: bf00 nop
- 800418a: 3714 adds r7, #20
- 800418c: 46bd mov sp, r7
- 800418e: f85d 7b04 ldr.w r7, [sp], #4
- 8004192: 4770 bx lr
+ 8004204: bf00 nop
+ 8004206: 3714 adds r7, #20
+ 8004208: 46bd mov sp, r7
+ 800420a: f85d 7b04 ldr.w r7, [sp], #4
+ 800420e: 4770 bx lr
-08004194 <TIM_ETR_SetConfig>:
+08004210 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
- 8004194: b480 push {r7}
- 8004196: b087 sub sp, #28
- 8004198: af00 add r7, sp, #0
- 800419a: 60f8 str r0, [r7, #12]
- 800419c: 60b9 str r1, [r7, #8]
- 800419e: 607a str r2, [r7, #4]
- 80041a0: 603b str r3, [r7, #0]
+ 8004210: b480 push {r7}
+ 8004212: b087 sub sp, #28
+ 8004214: af00 add r7, sp, #0
+ 8004216: 60f8 str r0, [r7, #12]
+ 8004218: 60b9 str r1, [r7, #8]
+ 800421a: 607a str r2, [r7, #4]
+ 800421c: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
- 80041a2: 68fb ldr r3, [r7, #12]
- 80041a4: 689b ldr r3, [r3, #8]
- 80041a6: 617b str r3, [r7, #20]
+ 800421e: 68fb ldr r3, [r7, #12]
+ 8004220: 689b ldr r3, [r3, #8]
+ 8004222: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 80041a8: 697b ldr r3, [r7, #20]
- 80041aa: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 80041ae: 617b str r3, [r7, #20]
+ 8004224: 697b ldr r3, [r7, #20]
+ 8004226: f423 437f bic.w r3, r3, #65280 ; 0xff00
+ 800422a: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 80041b0: 683b ldr r3, [r7, #0]
- 80041b2: 021a lsls r2, r3, #8
- 80041b4: 687b ldr r3, [r7, #4]
- 80041b6: 431a orrs r2, r3
- 80041b8: 68bb ldr r3, [r7, #8]
- 80041ba: 4313 orrs r3, r2
- 80041bc: 697a ldr r2, [r7, #20]
- 80041be: 4313 orrs r3, r2
- 80041c0: 617b str r3, [r7, #20]
+ 800422c: 683b ldr r3, [r7, #0]
+ 800422e: 021a lsls r2, r3, #8
+ 8004230: 687b ldr r3, [r7, #4]
+ 8004232: 431a orrs r2, r3
+ 8004234: 68bb ldr r3, [r7, #8]
+ 8004236: 4313 orrs r3, r2
+ 8004238: 697a ldr r2, [r7, #20]
+ 800423a: 4313 orrs r3, r2
+ 800423c: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
- 80041c2: 68fb ldr r3, [r7, #12]
- 80041c4: 697a ldr r2, [r7, #20]
- 80041c6: 609a str r2, [r3, #8]
+ 800423e: 68fb ldr r3, [r7, #12]
+ 8004240: 697a ldr r2, [r7, #20]
+ 8004242: 609a str r2, [r3, #8]
}
- 80041c8: bf00 nop
- 80041ca: 371c adds r7, #28
- 80041cc: 46bd mov sp, r7
- 80041ce: f85d 7b04 ldr.w r7, [sp], #4
- 80041d2: 4770 bx lr
+ 8004244: bf00 nop
+ 8004246: 371c adds r7, #28
+ 8004248: 46bd mov sp, r7
+ 800424a: f85d 7b04 ldr.w r7, [sp], #4
+ 800424e: 4770 bx lr
-080041d4 <TIM_CCxChannelCmd>:
+08004250 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
- 80041d4: b480 push {r7}
- 80041d6: b087 sub sp, #28
- 80041d8: af00 add r7, sp, #0
- 80041da: 60f8 str r0, [r7, #12]
- 80041dc: 60b9 str r1, [r7, #8]
- 80041de: 607a str r2, [r7, #4]
+ 8004250: b480 push {r7}
+ 8004252: b087 sub sp, #28
+ 8004254: af00 add r7, sp, #0
+ 8004256: 60f8 str r0, [r7, #12]
+ 8004258: 60b9 str r1, [r7, #8]
+ 800425a: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
- 80041e0: 68bb ldr r3, [r7, #8]
- 80041e2: f003 031f and.w r3, r3, #31
- 80041e6: 2201 movs r2, #1
- 80041e8: fa02 f303 lsl.w r3, r2, r3
- 80041ec: 617b str r3, [r7, #20]
+ 800425c: 68bb ldr r3, [r7, #8]
+ 800425e: f003 031f and.w r3, r3, #31
+ 8004262: 2201 movs r2, #1
+ 8004264: fa02 f303 lsl.w r3, r2, r3
+ 8004268: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
- 80041ee: 68fb ldr r3, [r7, #12]
- 80041f0: 6a1a ldr r2, [r3, #32]
- 80041f2: 697b ldr r3, [r7, #20]
- 80041f4: 43db mvns r3, r3
- 80041f6: 401a ands r2, r3
- 80041f8: 68fb ldr r3, [r7, #12]
- 80041fa: 621a str r2, [r3, #32]
+ 800426a: 68fb ldr r3, [r7, #12]
+ 800426c: 6a1a ldr r2, [r3, #32]
+ 800426e: 697b ldr r3, [r7, #20]
+ 8004270: 43db mvns r3, r3
+ 8004272: 401a ands r2, r3
+ 8004274: 68fb ldr r3, [r7, #12]
+ 8004276: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
- 80041fc: 68fb ldr r3, [r7, #12]
- 80041fe: 6a1a ldr r2, [r3, #32]
- 8004200: 68bb ldr r3, [r7, #8]
- 8004202: f003 031f and.w r3, r3, #31
- 8004206: 6879 ldr r1, [r7, #4]
- 8004208: fa01 f303 lsl.w r3, r1, r3
- 800420c: 431a orrs r2, r3
- 800420e: 68fb ldr r3, [r7, #12]
- 8004210: 621a str r2, [r3, #32]
+ 8004278: 68fb ldr r3, [r7, #12]
+ 800427a: 6a1a ldr r2, [r3, #32]
+ 800427c: 68bb ldr r3, [r7, #8]
+ 800427e: f003 031f and.w r3, r3, #31
+ 8004282: 6879 ldr r1, [r7, #4]
+ 8004284: fa01 f303 lsl.w r3, r1, r3
+ 8004288: 431a orrs r2, r3
+ 800428a: 68fb ldr r3, [r7, #12]
+ 800428c: 621a str r2, [r3, #32]
}
- 8004212: bf00 nop
- 8004214: 371c adds r7, #28
- 8004216: 46bd mov sp, r7
- 8004218: f85d 7b04 ldr.w r7, [sp], #4
- 800421c: 4770 bx lr
+ 800428e: bf00 nop
+ 8004290: 371c adds r7, #28
+ 8004292: 46bd mov sp, r7
+ 8004294: f85d 7b04 ldr.w r7, [sp], #4
+ 8004298: 4770 bx lr
...
-08004220 <HAL_TIMEx_MasterConfigSynchronization>:
+0800429c <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
- 8004220: b480 push {r7}
- 8004222: b085 sub sp, #20
- 8004224: af00 add r7, sp, #0
- 8004226: 6078 str r0, [r7, #4]
- 8004228: 6039 str r1, [r7, #0]
+ 800429c: b480 push {r7}
+ 800429e: b085 sub sp, #20
+ 80042a0: af00 add r7, sp, #0
+ 80042a2: 6078 str r0, [r7, #4]
+ 80042a4: 6039 str r1, [r7, #0]
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
- 800422a: 687b ldr r3, [r7, #4]
- 800422c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8004230: 2b01 cmp r3, #1
- 8004232: d101 bne.n 8004238 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 8004234: 2302 movs r3, #2
- 8004236: e045 b.n 80042c4 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 8004238: 687b ldr r3, [r7, #4]
- 800423a: 2201 movs r2, #1
- 800423c: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 80042a6: 687b ldr r3, [r7, #4]
+ 80042a8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 80042ac: 2b01 cmp r3, #1
+ 80042ae: d101 bne.n 80042b4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 80042b0: 2302 movs r3, #2
+ 80042b2: e045 b.n 8004340 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
+ 80042b4: 687b ldr r3, [r7, #4]
+ 80042b6: 2201 movs r2, #1
+ 80042b8: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
- 8004240: 687b ldr r3, [r7, #4]
- 8004242: 2202 movs r2, #2
- 8004244: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 80042bc: 687b ldr r3, [r7, #4]
+ 80042be: 2202 movs r2, #2
+ 80042c0: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
- 8004248: 687b ldr r3, [r7, #4]
- 800424a: 681b ldr r3, [r3, #0]
- 800424c: 685b ldr r3, [r3, #4]
- 800424e: 60fb str r3, [r7, #12]
+ 80042c4: 687b ldr r3, [r7, #4]
+ 80042c6: 681b ldr r3, [r3, #0]
+ 80042c8: 685b ldr r3, [r3, #4]
+ 80042ca: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
- 8004250: 687b ldr r3, [r7, #4]
- 8004252: 681b ldr r3, [r3, #0]
- 8004254: 689b ldr r3, [r3, #8]
- 8004256: 60bb str r3, [r7, #8]
+ 80042cc: 687b ldr r3, [r7, #4]
+ 80042ce: 681b ldr r3, [r3, #0]
+ 80042d0: 689b ldr r3, [r3, #8]
+ 80042d2: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 8004258: 687b ldr r3, [r7, #4]
- 800425a: 681b ldr r3, [r3, #0]
- 800425c: 4a1c ldr r2, [pc, #112] ; (80042d0 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 800425e: 4293 cmp r3, r2
- 8004260: d004 beq.n 800426c <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 8004262: 687b ldr r3, [r7, #4]
- 8004264: 681b ldr r3, [r3, #0]
- 8004266: 4a1b ldr r2, [pc, #108] ; (80042d4 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 8004268: 4293 cmp r3, r2
- 800426a: d108 bne.n 800427e <HAL_TIMEx_MasterConfigSynchronization+0x5e>
+ 80042d4: 687b ldr r3, [r7, #4]
+ 80042d6: 681b ldr r3, [r3, #0]
+ 80042d8: 4a1c ldr r2, [pc, #112] ; (800434c <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
+ 80042da: 4293 cmp r3, r2
+ 80042dc: d004 beq.n 80042e8 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
+ 80042de: 687b ldr r3, [r7, #4]
+ 80042e0: 681b ldr r3, [r3, #0]
+ 80042e2: 4a1b ldr r2, [pc, #108] ; (8004350 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
+ 80042e4: 4293 cmp r3, r2
+ 80042e6: d108 bne.n 80042fa <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
- 800426c: 68fb ldr r3, [r7, #12]
- 800426e: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 8004272: 60fb str r3, [r7, #12]
+ 80042e8: 68fb ldr r3, [r7, #12]
+ 80042ea: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
+ 80042ee: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 8004274: 683b ldr r3, [r7, #0]
- 8004276: 685b ldr r3, [r3, #4]
- 8004278: 68fa ldr r2, [r7, #12]
- 800427a: 4313 orrs r3, r2
- 800427c: 60fb str r3, [r7, #12]
+ 80042f0: 683b ldr r3, [r7, #0]
+ 80042f2: 685b ldr r3, [r3, #4]
+ 80042f4: 68fa ldr r2, [r7, #12]
+ 80042f6: 4313 orrs r3, r2
+ 80042f8: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
- 800427e: 68fb ldr r3, [r7, #12]
- 8004280: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8004284: 60fb str r3, [r7, #12]
+ 80042fa: 68fb ldr r3, [r7, #12]
+ 80042fc: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 8004300: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 8004286: 683b ldr r3, [r7, #0]
- 8004288: 681b ldr r3, [r3, #0]
- 800428a: 68fa ldr r2, [r7, #12]
- 800428c: 4313 orrs r3, r2
- 800428e: 60fb str r3, [r7, #12]
+ 8004302: 683b ldr r3, [r7, #0]
+ 8004304: 681b ldr r3, [r3, #0]
+ 8004306: 68fa ldr r2, [r7, #12]
+ 8004308: 4313 orrs r3, r2
+ 800430a: 60fb str r3, [r7, #12]
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
- 8004290: 68bb ldr r3, [r7, #8]
- 8004292: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8004296: 60bb str r3, [r7, #8]
+ 800430c: 68bb ldr r3, [r7, #8]
+ 800430e: f023 0380 bic.w r3, r3, #128 ; 0x80
+ 8004312: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 8004298: 683b ldr r3, [r7, #0]
- 800429a: 689b ldr r3, [r3, #8]
- 800429c: 68ba ldr r2, [r7, #8]
- 800429e: 4313 orrs r3, r2
- 80042a0: 60bb str r3, [r7, #8]
+ 8004314: 683b ldr r3, [r7, #0]
+ 8004316: 689b ldr r3, [r3, #8]
+ 8004318: 68ba ldr r2, [r7, #8]
+ 800431a: 4313 orrs r3, r2
+ 800431c: 60bb str r3, [r7, #8]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- 80042a2: 687b ldr r3, [r7, #4]
- 80042a4: 681b ldr r3, [r3, #0]
- 80042a6: 68fa ldr r2, [r7, #12]
- 80042a8: 605a str r2, [r3, #4]
+ 800431e: 687b ldr r3, [r7, #4]
+ 8004320: 681b ldr r3, [r3, #0]
+ 8004322: 68fa ldr r2, [r7, #12]
+ 8004324: 605a str r2, [r3, #4]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
- 80042aa: 687b ldr r3, [r7, #4]
- 80042ac: 681b ldr r3, [r3, #0]
- 80042ae: 68ba ldr r2, [r7, #8]
- 80042b0: 609a str r2, [r3, #8]
+ 8004326: 687b ldr r3, [r7, #4]
+ 8004328: 681b ldr r3, [r3, #0]
+ 800432a: 68ba ldr r2, [r7, #8]
+ 800432c: 609a str r2, [r3, #8]
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
- 80042b2: 687b ldr r3, [r7, #4]
- 80042b4: 2201 movs r2, #1
- 80042b6: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 800432e: 687b ldr r3, [r7, #4]
+ 8004330: 2201 movs r2, #1
+ 8004332: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
- 80042ba: 687b ldr r3, [r7, #4]
- 80042bc: 2200 movs r2, #0
- 80042be: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8004336: 687b ldr r3, [r7, #4]
+ 8004338: 2200 movs r2, #0
+ 800433a: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
- 80042c2: 2300 movs r3, #0
+ 800433e: 2300 movs r3, #0
}
- 80042c4: 4618 mov r0, r3
- 80042c6: 3714 adds r7, #20
- 80042c8: 46bd mov sp, r7
- 80042ca: f85d 7b04 ldr.w r7, [sp], #4
- 80042ce: 4770 bx lr
- 80042d0: 40010000 .word 0x40010000
- 80042d4: 40010400 .word 0x40010400
-
-080042d8 <HAL_TIMEx_CommutCallback>:
+ 8004340: 4618 mov r0, r3
+ 8004342: 3714 adds r7, #20
+ 8004344: 46bd mov sp, r7
+ 8004346: f85d 7b04 ldr.w r7, [sp], #4
+ 800434a: 4770 bx lr
+ 800434c: 40010000 .word 0x40010000
+ 8004350: 40010400 .word 0x40010400
+
+08004354 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
- 80042d8: b480 push {r7}
- 80042da: b083 sub sp, #12
- 80042dc: af00 add r7, sp, #0
- 80042de: 6078 str r0, [r7, #4]
+ 8004354: b480 push {r7}
+ 8004356: b083 sub sp, #12
+ 8004358: af00 add r7, sp, #0
+ 800435a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
- 80042e0: bf00 nop
- 80042e2: 370c adds r7, #12
- 80042e4: 46bd mov sp, r7
- 80042e6: f85d 7b04 ldr.w r7, [sp], #4
- 80042ea: 4770 bx lr
+ 800435c: bf00 nop
+ 800435e: 370c adds r7, #12
+ 8004360: 46bd mov sp, r7
+ 8004362: f85d 7b04 ldr.w r7, [sp], #4
+ 8004366: 4770 bx lr
-080042ec <HAL_TIMEx_BreakCallback>:
+08004368 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
- 80042ec: b480 push {r7}
- 80042ee: b083 sub sp, #12
- 80042f0: af00 add r7, sp, #0
- 80042f2: 6078 str r0, [r7, #4]
+ 8004368: b480 push {r7}
+ 800436a: b083 sub sp, #12
+ 800436c: af00 add r7, sp, #0
+ 800436e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
- 80042f4: bf00 nop
- 80042f6: 370c adds r7, #12
- 80042f8: 46bd mov sp, r7
- 80042fa: f85d 7b04 ldr.w r7, [sp], #4
- 80042fe: 4770 bx lr
+ 8004370: bf00 nop
+ 8004372: 370c adds r7, #12
+ 8004374: 46bd mov sp, r7
+ 8004376: f85d 7b04 ldr.w r7, [sp], #4
+ 800437a: 4770 bx lr
-08004300 <HAL_TIMEx_Break2Callback>:
+0800437c <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
- 8004300: b480 push {r7}
- 8004302: b083 sub sp, #12
- 8004304: af00 add r7, sp, #0
- 8004306: 6078 str r0, [r7, #4]
+ 800437c: b480 push {r7}
+ 800437e: b083 sub sp, #12
+ 8004380: af00 add r7, sp, #0
+ 8004382: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
- 8004308: bf00 nop
- 800430a: 370c adds r7, #12
- 800430c: 46bd mov sp, r7
- 800430e: f85d 7b04 ldr.w r7, [sp], #4
- 8004312: 4770 bx lr
+ 8004384: bf00 nop
+ 8004386: 370c adds r7, #12
+ 8004388: 46bd mov sp, r7
+ 800438a: f85d 7b04 ldr.w r7, [sp], #4
+ 800438e: 4770 bx lr
-08004314 <HAL_UART_Init>:
+08004390 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
- 8004314: b580 push {r7, lr}
- 8004316: b082 sub sp, #8
- 8004318: af00 add r7, sp, #0
- 800431a: 6078 str r0, [r7, #4]
+ 8004390: b580 push {r7, lr}
+ 8004392: b082 sub sp, #8
+ 8004394: af00 add r7, sp, #0
+ 8004396: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
- 800431c: 687b ldr r3, [r7, #4]
- 800431e: 2b00 cmp r3, #0
- 8004320: d101 bne.n 8004326 <HAL_UART_Init+0x12>
+ 8004398: 687b ldr r3, [r7, #4]
+ 800439a: 2b00 cmp r3, #0
+ 800439c: d101 bne.n 80043a2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
- 8004322: 2301 movs r3, #1
- 8004324: e040 b.n 80043a8 <HAL_UART_Init+0x94>
+ 800439e: 2301 movs r3, #1
+ 80043a0: e040 b.n 8004424 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
- 8004326: 687b ldr r3, [r7, #4]
- 8004328: 6f5b ldr r3, [r3, #116] ; 0x74
- 800432a: 2b00 cmp r3, #0
- 800432c: d106 bne.n 800433c <HAL_UART_Init+0x28>
+ 80043a2: 687b ldr r3, [r7, #4]
+ 80043a4: 6f5b ldr r3, [r3, #116] ; 0x74
+ 80043a6: 2b00 cmp r3, #0
+ 80043a8: d106 bne.n 80043b8 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
- 800432e: 687b ldr r3, [r7, #4]
- 8004330: 2200 movs r2, #0
- 8004332: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 80043aa: 687b ldr r3, [r7, #4]
+ 80043ac: 2200 movs r2, #0
+ 80043ae: f883 2070 strb.w r2, [r3, #112] ; 0x70
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
- 8004336: 6878 ldr r0, [r7, #4]
- 8004338: f7fd fa38 bl 80017ac <HAL_UART_MspInit>
+ 80043b2: 6878 ldr r0, [r7, #4]
+ 80043b4: f7fd fa38 bl 8001828 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
- 800433c: 687b ldr r3, [r7, #4]
- 800433e: 2224 movs r2, #36 ; 0x24
- 8004340: 675a str r2, [r3, #116] ; 0x74
+ 80043b8: 687b ldr r3, [r7, #4]
+ 80043ba: 2224 movs r2, #36 ; 0x24
+ 80043bc: 675a str r2, [r3, #116] ; 0x74
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
- 8004342: 687b ldr r3, [r7, #4]
- 8004344: 681b ldr r3, [r3, #0]
- 8004346: 681a ldr r2, [r3, #0]
- 8004348: 687b ldr r3, [r7, #4]
- 800434a: 681b ldr r3, [r3, #0]
- 800434c: f022 0201 bic.w r2, r2, #1
- 8004350: 601a str r2, [r3, #0]
+ 80043be: 687b ldr r3, [r7, #4]
+ 80043c0: 681b ldr r3, [r3, #0]
+ 80043c2: 681a ldr r2, [r3, #0]
+ 80043c4: 687b ldr r3, [r7, #4]
+ 80043c6: 681b ldr r3, [r3, #0]
+ 80043c8: f022 0201 bic.w r2, r2, #1
+ 80043cc: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
- 8004352: 6878 ldr r0, [r7, #4]
- 8004354: f000 f9ee bl 8004734 <UART_SetConfig>
- 8004358: 4603 mov r3, r0
- 800435a: 2b01 cmp r3, #1
- 800435c: d101 bne.n 8004362 <HAL_UART_Init+0x4e>
+ 80043ce: 6878 ldr r0, [r7, #4]
+ 80043d0: f000 fa90 bl 80048f4 <UART_SetConfig>
+ 80043d4: 4603 mov r3, r0
+ 80043d6: 2b01 cmp r3, #1
+ 80043d8: d101 bne.n 80043de <HAL_UART_Init+0x4e>
{
return HAL_ERROR;
- 800435e: 2301 movs r3, #1
- 8004360: e022 b.n 80043a8 <HAL_UART_Init+0x94>
+ 80043da: 2301 movs r3, #1
+ 80043dc: e022 b.n 8004424 <HAL_UART_Init+0x94>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 8004362: 687b ldr r3, [r7, #4]
- 8004364: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004366: 2b00 cmp r3, #0
- 8004368: d002 beq.n 8004370 <HAL_UART_Init+0x5c>
+ 80043de: 687b ldr r3, [r7, #4]
+ 80043e0: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80043e2: 2b00 cmp r3, #0
+ 80043e4: d002 beq.n 80043ec <HAL_UART_Init+0x5c>
{
UART_AdvFeatureConfig(huart);
- 800436a: 6878 ldr r0, [r7, #4]
- 800436c: f000 fc86 bl 8004c7c <UART_AdvFeatureConfig>
+ 80043e6: 6878 ldr r0, [r7, #4]
+ 80043e8: f000 fd28 bl 8004e3c <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8004370: 687b ldr r3, [r7, #4]
- 8004372: 681b ldr r3, [r3, #0]
- 8004374: 685a ldr r2, [r3, #4]
- 8004376: 687b ldr r3, [r7, #4]
- 8004378: 681b ldr r3, [r3, #0]
- 800437a: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 800437e: 605a str r2, [r3, #4]
+ 80043ec: 687b ldr r3, [r7, #4]
+ 80043ee: 681b ldr r3, [r3, #0]
+ 80043f0: 685a ldr r2, [r3, #4]
+ 80043f2: 687b ldr r3, [r7, #4]
+ 80043f4: 681b ldr r3, [r3, #0]
+ 80043f6: f422 4290 bic.w r2, r2, #18432 ; 0x4800
+ 80043fa: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8004380: 687b ldr r3, [r7, #4]
- 8004382: 681b ldr r3, [r3, #0]
- 8004384: 689a ldr r2, [r3, #8]
- 8004386: 687b ldr r3, [r7, #4]
- 8004388: 681b ldr r3, [r3, #0]
- 800438a: f022 022a bic.w r2, r2, #42 ; 0x2a
- 800438e: 609a str r2, [r3, #8]
+ 80043fc: 687b ldr r3, [r7, #4]
+ 80043fe: 681b ldr r3, [r3, #0]
+ 8004400: 689a ldr r2, [r3, #8]
+ 8004402: 687b ldr r3, [r7, #4]
+ 8004404: 681b ldr r3, [r3, #0]
+ 8004406: f022 022a bic.w r2, r2, #42 ; 0x2a
+ 800440a: 609a str r2, [r3, #8]
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- 8004390: 687b ldr r3, [r7, #4]
- 8004392: 681b ldr r3, [r3, #0]
- 8004394: 681a ldr r2, [r3, #0]
- 8004396: 687b ldr r3, [r7, #4]
- 8004398: 681b ldr r3, [r3, #0]
- 800439a: f042 0201 orr.w r2, r2, #1
- 800439e: 601a str r2, [r3, #0]
+ 800440c: 687b ldr r3, [r7, #4]
+ 800440e: 681b ldr r3, [r3, #0]
+ 8004410: 681a ldr r2, [r3, #0]
+ 8004412: 687b ldr r3, [r7, #4]
+ 8004414: 681b ldr r3, [r3, #0]
+ 8004416: f042 0201 orr.w r2, r2, #1
+ 800441a: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
- 80043a0: 6878 ldr r0, [r7, #4]
- 80043a2: f000 fd0d bl 8004dc0 <UART_CheckIdleState>
- 80043a6: 4603 mov r3, r0
+ 800441c: 6878 ldr r0, [r7, #4]
+ 800441e: f000 fdaf bl 8004f80 <UART_CheckIdleState>
+ 8004422: 4603 mov r3, r0
}
- 80043a8: 4618 mov r0, r3
- 80043aa: 3708 adds r7, #8
- 80043ac: 46bd mov sp, r7
- 80043ae: bd80 pop {r7, pc}
+ 8004424: 4618 mov r0, r3
+ 8004426: 3708 adds r7, #8
+ 8004428: 46bd mov sp, r7
+ 800442a: bd80 pop {r7, pc}
-080043b0 <HAL_UART_Transmit>:
+0800442c <HAL_UART_Transmit>:
* @param Size Amount of data to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- 80043b0: b580 push {r7, lr}
- 80043b2: b08a sub sp, #40 ; 0x28
- 80043b4: af02 add r7, sp, #8
- 80043b6: 60f8 str r0, [r7, #12]
- 80043b8: 60b9 str r1, [r7, #8]
- 80043ba: 603b str r3, [r7, #0]
- 80043bc: 4613 mov r3, r2
- 80043be: 80fb strh r3, [r7, #6]
+ 800442c: b580 push {r7, lr}
+ 800442e: b08a sub sp, #40 ; 0x28
+ 8004430: af02 add r7, sp, #8
+ 8004432: 60f8 str r0, [r7, #12]
+ 8004434: 60b9 str r1, [r7, #8]
+ 8004436: 603b str r3, [r7, #0]
+ 8004438: 4613 mov r3, r2
+ 800443a: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
- 80043c0: 68fb ldr r3, [r7, #12]
- 80043c2: 6f5b ldr r3, [r3, #116] ; 0x74
- 80043c4: 2b20 cmp r3, #32
- 80043c6: d17f bne.n 80044c8 <HAL_UART_Transmit+0x118>
+ 800443c: 68fb ldr r3, [r7, #12]
+ 800443e: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8004440: 2b20 cmp r3, #32
+ 8004442: d17f bne.n 8004544 <HAL_UART_Transmit+0x118>
{
if ((pData == NULL) || (Size == 0U))
- 80043c8: 68bb ldr r3, [r7, #8]
- 80043ca: 2b00 cmp r3, #0
- 80043cc: d002 beq.n 80043d4 <HAL_UART_Transmit+0x24>
- 80043ce: 88fb ldrh r3, [r7, #6]
- 80043d0: 2b00 cmp r3, #0
- 80043d2: d101 bne.n 80043d8 <HAL_UART_Transmit+0x28>
+ 8004444: 68bb ldr r3, [r7, #8]
+ 8004446: 2b00 cmp r3, #0
+ 8004448: d002 beq.n 8004450 <HAL_UART_Transmit+0x24>
+ 800444a: 88fb ldrh r3, [r7, #6]
+ 800444c: 2b00 cmp r3, #0
+ 800444e: d101 bne.n 8004454 <HAL_UART_Transmit+0x28>
{
return HAL_ERROR;
- 80043d4: 2301 movs r3, #1
- 80043d6: e078 b.n 80044ca <HAL_UART_Transmit+0x11a>
+ 8004450: 2301 movs r3, #1
+ 8004452: e078 b.n 8004546 <HAL_UART_Transmit+0x11a>
}
/* Process Locked */
__HAL_LOCK(huart);
- 80043d8: 68fb ldr r3, [r7, #12]
- 80043da: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 80043de: 2b01 cmp r3, #1
- 80043e0: d101 bne.n 80043e6 <HAL_UART_Transmit+0x36>
- 80043e2: 2302 movs r3, #2
- 80043e4: e071 b.n 80044ca <HAL_UART_Transmit+0x11a>
- 80043e6: 68fb ldr r3, [r7, #12]
- 80043e8: 2201 movs r2, #1
- 80043ea: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 8004454: 68fb ldr r3, [r7, #12]
+ 8004456: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
+ 800445a: 2b01 cmp r3, #1
+ 800445c: d101 bne.n 8004462 <HAL_UART_Transmit+0x36>
+ 800445e: 2302 movs r3, #2
+ 8004460: e071 b.n 8004546 <HAL_UART_Transmit+0x11a>
+ 8004462: 68fb ldr r3, [r7, #12]
+ 8004464: 2201 movs r2, #1
+ 8004466: f883 2070 strb.w r2, [r3, #112] ; 0x70
huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80043ee: 68fb ldr r3, [r7, #12]
- 80043f0: 2200 movs r2, #0
- 80043f2: 67da str r2, [r3, #124] ; 0x7c
+ 800446a: 68fb ldr r3, [r7, #12]
+ 800446c: 2200 movs r2, #0
+ 800446e: 67da str r2, [r3, #124] ; 0x7c
huart->gState = HAL_UART_STATE_BUSY_TX;
- 80043f4: 68fb ldr r3, [r7, #12]
- 80043f6: 2221 movs r2, #33 ; 0x21
- 80043f8: 675a str r2, [r3, #116] ; 0x74
+ 8004470: 68fb ldr r3, [r7, #12]
+ 8004472: 2221 movs r2, #33 ; 0x21
+ 8004474: 675a str r2, [r3, #116] ; 0x74
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- 80043fa: f7fd fb1f bl 8001a3c <HAL_GetTick>
- 80043fe: 6178 str r0, [r7, #20]
+ 8004476: f7fd fb1f bl 8001ab8 <HAL_GetTick>
+ 800447a: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
- 8004400: 68fb ldr r3, [r7, #12]
- 8004402: 88fa ldrh r2, [r7, #6]
- 8004404: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
+ 800447c: 68fb ldr r3, [r7, #12]
+ 800447e: 88fa ldrh r2, [r7, #6]
+ 8004480: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
huart->TxXferCount = Size;
- 8004408: 68fb ldr r3, [r7, #12]
- 800440a: 88fa ldrh r2, [r7, #6]
- 800440c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+ 8004484: 68fb ldr r3, [r7, #12]
+ 8004486: 88fa ldrh r2, [r7, #6]
+ 8004488: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8004410: 68fb ldr r3, [r7, #12]
- 8004412: 689b ldr r3, [r3, #8]
- 8004414: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8004418: d108 bne.n 800442c <HAL_UART_Transmit+0x7c>
- 800441a: 68fb ldr r3, [r7, #12]
- 800441c: 691b ldr r3, [r3, #16]
- 800441e: 2b00 cmp r3, #0
- 8004420: d104 bne.n 800442c <HAL_UART_Transmit+0x7c>
+ 800448c: 68fb ldr r3, [r7, #12]
+ 800448e: 689b ldr r3, [r3, #8]
+ 8004490: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8004494: d108 bne.n 80044a8 <HAL_UART_Transmit+0x7c>
+ 8004496: 68fb ldr r3, [r7, #12]
+ 8004498: 691b ldr r3, [r3, #16]
+ 800449a: 2b00 cmp r3, #0
+ 800449c: d104 bne.n 80044a8 <HAL_UART_Transmit+0x7c>
{
pdata8bits = NULL;
- 8004422: 2300 movs r3, #0
- 8004424: 61fb str r3, [r7, #28]
+ 800449e: 2300 movs r3, #0
+ 80044a0: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
- 8004426: 68bb ldr r3, [r7, #8]
- 8004428: 61bb str r3, [r7, #24]
- 800442a: e003 b.n 8004434 <HAL_UART_Transmit+0x84>
+ 80044a2: 68bb ldr r3, [r7, #8]
+ 80044a4: 61bb str r3, [r7, #24]
+ 80044a6: e003 b.n 80044b0 <HAL_UART_Transmit+0x84>
}
else
{
pdata8bits = pData;
- 800442c: 68bb ldr r3, [r7, #8]
- 800442e: 61fb str r3, [r7, #28]
+ 80044a8: 68bb ldr r3, [r7, #8]
+ 80044aa: 61fb str r3, [r7, #28]
pdata16bits = NULL;
- 8004430: 2300 movs r3, #0
- 8004432: 61bb str r3, [r7, #24]
+ 80044ac: 2300 movs r3, #0
+ 80044ae: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
- 8004434: e02c b.n 8004490 <HAL_UART_Transmit+0xe0>
+ 80044b0: e02c b.n 800450c <HAL_UART_Transmit+0xe0>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 8004436: 683b ldr r3, [r7, #0]
- 8004438: 9300 str r3, [sp, #0]
- 800443a: 697b ldr r3, [r7, #20]
- 800443c: 2200 movs r2, #0
- 800443e: 2180 movs r1, #128 ; 0x80
- 8004440: 68f8 ldr r0, [r7, #12]
- 8004442: f000 fcec bl 8004e1e <UART_WaitOnFlagUntilTimeout>
- 8004446: 4603 mov r3, r0
- 8004448: 2b00 cmp r3, #0
- 800444a: d001 beq.n 8004450 <HAL_UART_Transmit+0xa0>
+ 80044b2: 683b ldr r3, [r7, #0]
+ 80044b4: 9300 str r3, [sp, #0]
+ 80044b6: 697b ldr r3, [r7, #20]
+ 80044b8: 2200 movs r2, #0
+ 80044ba: 2180 movs r1, #128 ; 0x80
+ 80044bc: 68f8 ldr r0, [r7, #12]
+ 80044be: f000 fd8e bl 8004fde <UART_WaitOnFlagUntilTimeout>
+ 80044c2: 4603 mov r3, r0
+ 80044c4: 2b00 cmp r3, #0
+ 80044c6: d001 beq.n 80044cc <HAL_UART_Transmit+0xa0>
{
return HAL_TIMEOUT;
- 800444c: 2303 movs r3, #3
- 800444e: e03c b.n 80044ca <HAL_UART_Transmit+0x11a>
+ 80044c8: 2303 movs r3, #3
+ 80044ca: e03c b.n 8004546 <HAL_UART_Transmit+0x11a>
}
if (pdata8bits == NULL)
- 8004450: 69fb ldr r3, [r7, #28]
- 8004452: 2b00 cmp r3, #0
- 8004454: d10b bne.n 800446e <HAL_UART_Transmit+0xbe>
+ 80044cc: 69fb ldr r3, [r7, #28]
+ 80044ce: 2b00 cmp r3, #0
+ 80044d0: d10b bne.n 80044ea <HAL_UART_Transmit+0xbe>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 8004456: 69bb ldr r3, [r7, #24]
- 8004458: 881b ldrh r3, [r3, #0]
- 800445a: 461a mov r2, r3
- 800445c: 68fb ldr r3, [r7, #12]
- 800445e: 681b ldr r3, [r3, #0]
- 8004460: f3c2 0208 ubfx r2, r2, #0, #9
- 8004464: 629a str r2, [r3, #40] ; 0x28
+ 80044d2: 69bb ldr r3, [r7, #24]
+ 80044d4: 881b ldrh r3, [r3, #0]
+ 80044d6: 461a mov r2, r3
+ 80044d8: 68fb ldr r3, [r7, #12]
+ 80044da: 681b ldr r3, [r3, #0]
+ 80044dc: f3c2 0208 ubfx r2, r2, #0, #9
+ 80044e0: 629a str r2, [r3, #40] ; 0x28
pdata16bits++;
- 8004466: 69bb ldr r3, [r7, #24]
- 8004468: 3302 adds r3, #2
- 800446a: 61bb str r3, [r7, #24]
- 800446c: e007 b.n 800447e <HAL_UART_Transmit+0xce>
+ 80044e2: 69bb ldr r3, [r7, #24]
+ 80044e4: 3302 adds r3, #2
+ 80044e6: 61bb str r3, [r7, #24]
+ 80044e8: e007 b.n 80044fa <HAL_UART_Transmit+0xce>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 800446e: 69fb ldr r3, [r7, #28]
- 8004470: 781a ldrb r2, [r3, #0]
- 8004472: 68fb ldr r3, [r7, #12]
- 8004474: 681b ldr r3, [r3, #0]
- 8004476: 629a str r2, [r3, #40] ; 0x28
+ 80044ea: 69fb ldr r3, [r7, #28]
+ 80044ec: 781a ldrb r2, [r3, #0]
+ 80044ee: 68fb ldr r3, [r7, #12]
+ 80044f0: 681b ldr r3, [r3, #0]
+ 80044f2: 629a str r2, [r3, #40] ; 0x28
pdata8bits++;
- 8004478: 69fb ldr r3, [r7, #28]
- 800447a: 3301 adds r3, #1
- 800447c: 61fb str r3, [r7, #28]
+ 80044f4: 69fb ldr r3, [r7, #28]
+ 80044f6: 3301 adds r3, #1
+ 80044f8: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
- 800447e: 68fb ldr r3, [r7, #12]
- 8004480: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 8004484: b29b uxth r3, r3
- 8004486: 3b01 subs r3, #1
- 8004488: b29a uxth r2, r3
- 800448a: 68fb ldr r3, [r7, #12]
- 800448c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+ 80044fa: 68fb ldr r3, [r7, #12]
+ 80044fc: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
+ 8004500: b29b uxth r3, r3
+ 8004502: 3b01 subs r3, #1
+ 8004504: b29a uxth r2, r3
+ 8004506: 68fb ldr r3, [r7, #12]
+ 8004508: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
while (huart->TxXferCount > 0U)
- 8004490: 68fb ldr r3, [r7, #12]
- 8004492: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 8004496: b29b uxth r3, r3
- 8004498: 2b00 cmp r3, #0
- 800449a: d1cc bne.n 8004436 <HAL_UART_Transmit+0x86>
+ 800450c: 68fb ldr r3, [r7, #12]
+ 800450e: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
+ 8004512: b29b uxth r3, r3
+ 8004514: 2b00 cmp r3, #0
+ 8004516: d1cc bne.n 80044b2 <HAL_UART_Transmit+0x86>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 800449c: 683b ldr r3, [r7, #0]
- 800449e: 9300 str r3, [sp, #0]
- 80044a0: 697b ldr r3, [r7, #20]
- 80044a2: 2200 movs r2, #0
- 80044a4: 2140 movs r1, #64 ; 0x40
- 80044a6: 68f8 ldr r0, [r7, #12]
- 80044a8: f000 fcb9 bl 8004e1e <UART_WaitOnFlagUntilTimeout>
- 80044ac: 4603 mov r3, r0
- 80044ae: 2b00 cmp r3, #0
- 80044b0: d001 beq.n 80044b6 <HAL_UART_Transmit+0x106>
+ 8004518: 683b ldr r3, [r7, #0]
+ 800451a: 9300 str r3, [sp, #0]
+ 800451c: 697b ldr r3, [r7, #20]
+ 800451e: 2200 movs r2, #0
+ 8004520: 2140 movs r1, #64 ; 0x40
+ 8004522: 68f8 ldr r0, [r7, #12]
+ 8004524: f000 fd5b bl 8004fde <UART_WaitOnFlagUntilTimeout>
+ 8004528: 4603 mov r3, r0
+ 800452a: 2b00 cmp r3, #0
+ 800452c: d001 beq.n 8004532 <HAL_UART_Transmit+0x106>
{
return HAL_TIMEOUT;
- 80044b2: 2303 movs r3, #3
- 80044b4: e009 b.n 80044ca <HAL_UART_Transmit+0x11a>
+ 800452e: 2303 movs r3, #3
+ 8004530: e009 b.n 8004546 <HAL_UART_Transmit+0x11a>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- 80044b6: 68fb ldr r3, [r7, #12]
- 80044b8: 2220 movs r2, #32
- 80044ba: 675a str r2, [r3, #116] ; 0x74
+ 8004532: 68fb ldr r3, [r7, #12]
+ 8004534: 2220 movs r2, #32
+ 8004536: 675a str r2, [r3, #116] ; 0x74
/* Process Unlocked */
__HAL_UNLOCK(huart);
- 80044bc: 68fb ldr r3, [r7, #12]
- 80044be: 2200 movs r2, #0
- 80044c0: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 8004538: 68fb ldr r3, [r7, #12]
+ 800453a: 2200 movs r2, #0
+ 800453c: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_OK;
- 80044c4: 2300 movs r3, #0
- 80044c6: e000 b.n 80044ca <HAL_UART_Transmit+0x11a>
+ 8004540: 2300 movs r3, #0
+ 8004542: e000 b.n 8004546 <HAL_UART_Transmit+0x11a>
}
else
{
return HAL_BUSY;
- 80044c8: 2302 movs r3, #2
+ 8004544: 2302 movs r3, #2
}
}
- 80044ca: 4618 mov r0, r3
- 80044cc: 3720 adds r7, #32
- 80044ce: 46bd mov sp, r7
- 80044d0: bd80 pop {r7, pc}
+ 8004546: 4618 mov r0, r3
+ 8004548: 3720 adds r7, #32
+ 800454a: 46bd mov sp, r7
+ 800454c: bd80 pop {r7, pc}
...
-080044d4 <HAL_UART_IRQHandler>:
+08004550 <HAL_UART_Receive_IT>:
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ 8004550: b480 push {r7}
+ 8004552: b085 sub sp, #20
+ 8004554: af00 add r7, sp, #0
+ 8004556: 60f8 str r0, [r7, #12]
+ 8004558: 60b9 str r1, [r7, #8]
+ 800455a: 4613 mov r3, r2
+ 800455c: 80fb strh r3, [r7, #6]
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ 800455e: 68fb ldr r3, [r7, #12]
+ 8004560: 6f9b ldr r3, [r3, #120] ; 0x78
+ 8004562: 2b20 cmp r3, #32
+ 8004564: f040 808a bne.w 800467c <HAL_UART_Receive_IT+0x12c>
+ {
+ if ((pData == NULL) || (Size == 0U))
+ 8004568: 68bb ldr r3, [r7, #8]
+ 800456a: 2b00 cmp r3, #0
+ 800456c: d002 beq.n 8004574 <HAL_UART_Receive_IT+0x24>
+ 800456e: 88fb ldrh r3, [r7, #6]
+ 8004570: 2b00 cmp r3, #0
+ 8004572: d101 bne.n 8004578 <HAL_UART_Receive_IT+0x28>
+ {
+ return HAL_ERROR;
+ 8004574: 2301 movs r3, #1
+ 8004576: e082 b.n 800467e <HAL_UART_Receive_IT+0x12e>
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ 8004578: 68fb ldr r3, [r7, #12]
+ 800457a: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
+ 800457e: 2b01 cmp r3, #1
+ 8004580: d101 bne.n 8004586 <HAL_UART_Receive_IT+0x36>
+ 8004582: 2302 movs r3, #2
+ 8004584: e07b b.n 800467e <HAL_UART_Receive_IT+0x12e>
+ 8004586: 68fb ldr r3, [r7, #12]
+ 8004588: 2201 movs r2, #1
+ 800458a: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ huart->pRxBuffPtr = pData;
+ 800458e: 68fb ldr r3, [r7, #12]
+ 8004590: 68ba ldr r2, [r7, #8]
+ 8004592: 655a str r2, [r3, #84] ; 0x54
+ huart->RxXferSize = Size;
+ 8004594: 68fb ldr r3, [r7, #12]
+ 8004596: 88fa ldrh r2, [r7, #6]
+ 8004598: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
+ huart->RxXferCount = Size;
+ 800459c: 68fb ldr r3, [r7, #12]
+ 800459e: 88fa ldrh r2, [r7, #6]
+ 80045a0: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+ huart->RxISR = NULL;
+ 80045a4: 68fb ldr r3, [r7, #12]
+ 80045a6: 2200 movs r2, #0
+ 80045a8: 661a str r2, [r3, #96] ; 0x60
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ 80045aa: 68fb ldr r3, [r7, #12]
+ 80045ac: 689b ldr r3, [r3, #8]
+ 80045ae: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 80045b2: d10e bne.n 80045d2 <HAL_UART_Receive_IT+0x82>
+ 80045b4: 68fb ldr r3, [r7, #12]
+ 80045b6: 691b ldr r3, [r3, #16]
+ 80045b8: 2b00 cmp r3, #0
+ 80045ba: d105 bne.n 80045c8 <HAL_UART_Receive_IT+0x78>
+ 80045bc: 68fb ldr r3, [r7, #12]
+ 80045be: f240 12ff movw r2, #511 ; 0x1ff
+ 80045c2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 80045c6: e02d b.n 8004624 <HAL_UART_Receive_IT+0xd4>
+ 80045c8: 68fb ldr r3, [r7, #12]
+ 80045ca: 22ff movs r2, #255 ; 0xff
+ 80045cc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 80045d0: e028 b.n 8004624 <HAL_UART_Receive_IT+0xd4>
+ 80045d2: 68fb ldr r3, [r7, #12]
+ 80045d4: 689b ldr r3, [r3, #8]
+ 80045d6: 2b00 cmp r3, #0
+ 80045d8: d10d bne.n 80045f6 <HAL_UART_Receive_IT+0xa6>
+ 80045da: 68fb ldr r3, [r7, #12]
+ 80045dc: 691b ldr r3, [r3, #16]
+ 80045de: 2b00 cmp r3, #0
+ 80045e0: d104 bne.n 80045ec <HAL_UART_Receive_IT+0x9c>
+ 80045e2: 68fb ldr r3, [r7, #12]
+ 80045e4: 22ff movs r2, #255 ; 0xff
+ 80045e6: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 80045ea: e01b b.n 8004624 <HAL_UART_Receive_IT+0xd4>
+ 80045ec: 68fb ldr r3, [r7, #12]
+ 80045ee: 227f movs r2, #127 ; 0x7f
+ 80045f0: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 80045f4: e016 b.n 8004624 <HAL_UART_Receive_IT+0xd4>
+ 80045f6: 68fb ldr r3, [r7, #12]
+ 80045f8: 689b ldr r3, [r3, #8]
+ 80045fa: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
+ 80045fe: d10d bne.n 800461c <HAL_UART_Receive_IT+0xcc>
+ 8004600: 68fb ldr r3, [r7, #12]
+ 8004602: 691b ldr r3, [r3, #16]
+ 8004604: 2b00 cmp r3, #0
+ 8004606: d104 bne.n 8004612 <HAL_UART_Receive_IT+0xc2>
+ 8004608: 68fb ldr r3, [r7, #12]
+ 800460a: 227f movs r2, #127 ; 0x7f
+ 800460c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 8004610: e008 b.n 8004624 <HAL_UART_Receive_IT+0xd4>
+ 8004612: 68fb ldr r3, [r7, #12]
+ 8004614: 223f movs r2, #63 ; 0x3f
+ 8004616: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 800461a: e003 b.n 8004624 <HAL_UART_Receive_IT+0xd4>
+ 800461c: 68fb ldr r3, [r7, #12]
+ 800461e: 2200 movs r2, #0
+ 8004620: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004624: 68fb ldr r3, [r7, #12]
+ 8004626: 2200 movs r2, #0
+ 8004628: 67da str r2, [r3, #124] ; 0x7c
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 800462a: 68fb ldr r3, [r7, #12]
+ 800462c: 2222 movs r2, #34 ; 0x22
+ 800462e: 679a str r2, [r3, #120] ; 0x78
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004630: 68fb ldr r3, [r7, #12]
+ 8004632: 681b ldr r3, [r3, #0]
+ 8004634: 689a ldr r2, [r3, #8]
+ 8004636: 68fb ldr r3, [r7, #12]
+ 8004638: 681b ldr r3, [r3, #0]
+ 800463a: f042 0201 orr.w r2, r2, #1
+ 800463e: 609a str r2, [r3, #8]
+
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 8004640: 68fb ldr r3, [r7, #12]
+ 8004642: 689b ldr r3, [r3, #8]
+ 8004644: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8004648: d107 bne.n 800465a <HAL_UART_Receive_IT+0x10a>
+ 800464a: 68fb ldr r3, [r7, #12]
+ 800464c: 691b ldr r3, [r3, #16]
+ 800464e: 2b00 cmp r3, #0
+ 8004650: d103 bne.n 800465a <HAL_UART_Receive_IT+0x10a>
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ 8004652: 68fb ldr r3, [r7, #12]
+ 8004654: 4a0d ldr r2, [pc, #52] ; (800468c <HAL_UART_Receive_IT+0x13c>)
+ 8004656: 661a str r2, [r3, #96] ; 0x60
+ 8004658: e002 b.n 8004660 <HAL_UART_Receive_IT+0x110>
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ 800465a: 68fb ldr r3, [r7, #12]
+ 800465c: 4a0c ldr r2, [pc, #48] ; (8004690 <HAL_UART_Receive_IT+0x140>)
+ 800465e: 661a str r2, [r3, #96] ; 0x60
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ 8004660: 68fb ldr r3, [r7, #12]
+ 8004662: 2200 movs r2, #0
+ 8004664: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ 8004668: 68fb ldr r3, [r7, #12]
+ 800466a: 681b ldr r3, [r3, #0]
+ 800466c: 681a ldr r2, [r3, #0]
+ 800466e: 68fb ldr r3, [r7, #12]
+ 8004670: 681b ldr r3, [r3, #0]
+ 8004672: f442 7290 orr.w r2, r2, #288 ; 0x120
+ 8004676: 601a str r2, [r3, #0]
+
+ return HAL_OK;
+ 8004678: 2300 movs r3, #0
+ 800467a: e000 b.n 800467e <HAL_UART_Receive_IT+0x12e>
+ }
+ else
+ {
+ return HAL_BUSY;
+ 800467c: 2302 movs r3, #2
+ }
+}
+ 800467e: 4618 mov r0, r3
+ 8004680: 3714 adds r7, #20
+ 8004682: 46bd mov sp, r7
+ 8004684: f85d 7b04 ldr.w r7, [sp], #4
+ 8004688: 4770 bx lr
+ 800468a: bf00 nop
+ 800468c: 080051b3 .word 0x080051b3
+ 8004690: 0800510d .word 0x0800510d
+
+08004694 <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
- 80044d4: b580 push {r7, lr}
- 80044d6: b088 sub sp, #32
- 80044d8: af00 add r7, sp, #0
- 80044da: 6078 str r0, [r7, #4]
+ 8004694: b580 push {r7, lr}
+ 8004696: b088 sub sp, #32
+ 8004698: af00 add r7, sp, #0
+ 800469a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
- 80044dc: 687b ldr r3, [r7, #4]
- 80044de: 681b ldr r3, [r3, #0]
- 80044e0: 69db ldr r3, [r3, #28]
- 80044e2: 61fb str r3, [r7, #28]
+ 800469c: 687b ldr r3, [r7, #4]
+ 800469e: 681b ldr r3, [r3, #0]
+ 80046a0: 69db ldr r3, [r3, #28]
+ 80046a2: 61fb str r3, [r7, #28]
uint32_t cr1its = READ_REG(huart->Instance->CR1);
- 80044e4: 687b ldr r3, [r7, #4]
- 80044e6: 681b ldr r3, [r3, #0]
- 80044e8: 681b ldr r3, [r3, #0]
- 80044ea: 61bb str r3, [r7, #24]
+ 80046a4: 687b ldr r3, [r7, #4]
+ 80046a6: 681b ldr r3, [r3, #0]
+ 80046a8: 681b ldr r3, [r3, #0]
+ 80046aa: 61bb str r3, [r7, #24]
uint32_t cr3its = READ_REG(huart->Instance->CR3);
- 80044ec: 687b ldr r3, [r7, #4]
- 80044ee: 681b ldr r3, [r3, #0]
- 80044f0: 689b ldr r3, [r3, #8]
- 80044f2: 617b str r3, [r7, #20]
+ 80046ac: 687b ldr r3, [r7, #4]
+ 80046ae: 681b ldr r3, [r3, #0]
+ 80046b0: 689b ldr r3, [r3, #8]
+ 80046b2: 617b str r3, [r7, #20]
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- 80044f4: 69fb ldr r3, [r7, #28]
- 80044f6: f003 030f and.w r3, r3, #15
- 80044fa: 613b str r3, [r7, #16]
+ 80046b4: 69fb ldr r3, [r7, #28]
+ 80046b6: f003 030f and.w r3, r3, #15
+ 80046ba: 613b str r3, [r7, #16]
if (errorflags == 0U)
- 80044fc: 693b ldr r3, [r7, #16]
- 80044fe: 2b00 cmp r3, #0
- 8004500: d113 bne.n 800452a <HAL_UART_IRQHandler+0x56>
+ 80046bc: 693b ldr r3, [r7, #16]
+ 80046be: 2b00 cmp r3, #0
+ 80046c0: d113 bne.n 80046ea <HAL_UART_IRQHandler+0x56>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
- 8004502: 69fb ldr r3, [r7, #28]
- 8004504: f003 0320 and.w r3, r3, #32
- 8004508: 2b00 cmp r3, #0
- 800450a: d00e beq.n 800452a <HAL_UART_IRQHandler+0x56>
+ 80046c2: 69fb ldr r3, [r7, #28]
+ 80046c4: f003 0320 and.w r3, r3, #32
+ 80046c8: 2b00 cmp r3, #0
+ 80046ca: d00e beq.n 80046ea <HAL_UART_IRQHandler+0x56>
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
- 800450c: 69bb ldr r3, [r7, #24]
- 800450e: f003 0320 and.w r3, r3, #32
- 8004512: 2b00 cmp r3, #0
- 8004514: d009 beq.n 800452a <HAL_UART_IRQHandler+0x56>
+ 80046cc: 69bb ldr r3, [r7, #24]
+ 80046ce: f003 0320 and.w r3, r3, #32
+ 80046d2: 2b00 cmp r3, #0
+ 80046d4: d009 beq.n 80046ea <HAL_UART_IRQHandler+0x56>
{
if (huart->RxISR != NULL)
- 8004516: 687b ldr r3, [r7, #4]
- 8004518: 6e1b ldr r3, [r3, #96] ; 0x60
- 800451a: 2b00 cmp r3, #0
- 800451c: f000 80eb beq.w 80046f6 <HAL_UART_IRQHandler+0x222>
+ 80046d6: 687b ldr r3, [r7, #4]
+ 80046d8: 6e1b ldr r3, [r3, #96] ; 0x60
+ 80046da: 2b00 cmp r3, #0
+ 80046dc: f000 80eb beq.w 80048b6 <HAL_UART_IRQHandler+0x222>
{
huart->RxISR(huart);
- 8004520: 687b ldr r3, [r7, #4]
- 8004522: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004524: 6878 ldr r0, [r7, #4]
- 8004526: 4798 blx r3
+ 80046e0: 687b ldr r3, [r7, #4]
+ 80046e2: 6e1b ldr r3, [r3, #96] ; 0x60
+ 80046e4: 6878 ldr r0, [r7, #4]
+ 80046e6: 4798 blx r3
}
return;
- 8004528: e0e5 b.n 80046f6 <HAL_UART_IRQHandler+0x222>
+ 80046e8: e0e5 b.n 80048b6 <HAL_UART_IRQHandler+0x222>
}
}
/* If some errors occur */
if ((errorflags != 0U)
- 800452a: 693b ldr r3, [r7, #16]
- 800452c: 2b00 cmp r3, #0
- 800452e: f000 80c0 beq.w 80046b2 <HAL_UART_IRQHandler+0x1de>
+ 80046ea: 693b ldr r3, [r7, #16]
+ 80046ec: 2b00 cmp r3, #0
+ 80046ee: f000 80c0 beq.w 8004872 <HAL_UART_IRQHandler+0x1de>
&& (((cr3its & USART_CR3_EIE) != 0U)
- 8004532: 697b ldr r3, [r7, #20]
- 8004534: f003 0301 and.w r3, r3, #1
- 8004538: 2b00 cmp r3, #0
- 800453a: d105 bne.n 8004548 <HAL_UART_IRQHandler+0x74>
+ 80046f2: 697b ldr r3, [r7, #20]
+ 80046f4: f003 0301 and.w r3, r3, #1
+ 80046f8: 2b00 cmp r3, #0
+ 80046fa: d105 bne.n 8004708 <HAL_UART_IRQHandler+0x74>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
- 800453c: 69bb ldr r3, [r7, #24]
- 800453e: f403 7390 and.w r3, r3, #288 ; 0x120
- 8004542: 2b00 cmp r3, #0
- 8004544: f000 80b5 beq.w 80046b2 <HAL_UART_IRQHandler+0x1de>
+ 80046fc: 69bb ldr r3, [r7, #24]
+ 80046fe: f403 7390 and.w r3, r3, #288 ; 0x120
+ 8004702: 2b00 cmp r3, #0
+ 8004704: f000 80b5 beq.w 8004872 <HAL_UART_IRQHandler+0x1de>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
- 8004548: 69fb ldr r3, [r7, #28]
- 800454a: f003 0301 and.w r3, r3, #1
- 800454e: 2b00 cmp r3, #0
- 8004550: d00e beq.n 8004570 <HAL_UART_IRQHandler+0x9c>
- 8004552: 69bb ldr r3, [r7, #24]
- 8004554: f403 7380 and.w r3, r3, #256 ; 0x100
- 8004558: 2b00 cmp r3, #0
- 800455a: d009 beq.n 8004570 <HAL_UART_IRQHandler+0x9c>
+ 8004708: 69fb ldr r3, [r7, #28]
+ 800470a: f003 0301 and.w r3, r3, #1
+ 800470e: 2b00 cmp r3, #0
+ 8004710: d00e beq.n 8004730 <HAL_UART_IRQHandler+0x9c>
+ 8004712: 69bb ldr r3, [r7, #24]
+ 8004714: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8004718: 2b00 cmp r3, #0
+ 800471a: d009 beq.n 8004730 <HAL_UART_IRQHandler+0x9c>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
- 800455c: 687b ldr r3, [r7, #4]
- 800455e: 681b ldr r3, [r3, #0]
- 8004560: 2201 movs r2, #1
- 8004562: 621a str r2, [r3, #32]
+ 800471c: 687b ldr r3, [r7, #4]
+ 800471e: 681b ldr r3, [r3, #0]
+ 8004720: 2201 movs r2, #1
+ 8004722: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
- 8004564: 687b ldr r3, [r7, #4]
- 8004566: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004568: f043 0201 orr.w r2, r3, #1
- 800456c: 687b ldr r3, [r7, #4]
- 800456e: 67da str r2, [r3, #124] ; 0x7c
+ 8004724: 687b ldr r3, [r7, #4]
+ 8004726: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8004728: f043 0201 orr.w r2, r3, #1
+ 800472c: 687b ldr r3, [r7, #4]
+ 800472e: 67da str r2, [r3, #124] ; 0x7c
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004570: 69fb ldr r3, [r7, #28]
- 8004572: f003 0302 and.w r3, r3, #2
- 8004576: 2b00 cmp r3, #0
- 8004578: d00e beq.n 8004598 <HAL_UART_IRQHandler+0xc4>
- 800457a: 697b ldr r3, [r7, #20]
- 800457c: f003 0301 and.w r3, r3, #1
- 8004580: 2b00 cmp r3, #0
- 8004582: d009 beq.n 8004598 <HAL_UART_IRQHandler+0xc4>
+ 8004730: 69fb ldr r3, [r7, #28]
+ 8004732: f003 0302 and.w r3, r3, #2
+ 8004736: 2b00 cmp r3, #0
+ 8004738: d00e beq.n 8004758 <HAL_UART_IRQHandler+0xc4>
+ 800473a: 697b ldr r3, [r7, #20]
+ 800473c: f003 0301 and.w r3, r3, #1
+ 8004740: 2b00 cmp r3, #0
+ 8004742: d009 beq.n 8004758 <HAL_UART_IRQHandler+0xc4>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
- 8004584: 687b ldr r3, [r7, #4]
- 8004586: 681b ldr r3, [r3, #0]
- 8004588: 2202 movs r2, #2
- 800458a: 621a str r2, [r3, #32]
+ 8004744: 687b ldr r3, [r7, #4]
+ 8004746: 681b ldr r3, [r3, #0]
+ 8004748: 2202 movs r2, #2
+ 800474a: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
- 800458c: 687b ldr r3, [r7, #4]
- 800458e: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004590: f043 0204 orr.w r2, r3, #4
- 8004594: 687b ldr r3, [r7, #4]
- 8004596: 67da str r2, [r3, #124] ; 0x7c
+ 800474c: 687b ldr r3, [r7, #4]
+ 800474e: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8004750: f043 0204 orr.w r2, r3, #4
+ 8004754: 687b ldr r3, [r7, #4]
+ 8004756: 67da str r2, [r3, #124] ; 0x7c
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8004598: 69fb ldr r3, [r7, #28]
- 800459a: f003 0304 and.w r3, r3, #4
- 800459e: 2b00 cmp r3, #0
- 80045a0: d00e beq.n 80045c0 <HAL_UART_IRQHandler+0xec>
- 80045a2: 697b ldr r3, [r7, #20]
- 80045a4: f003 0301 and.w r3, r3, #1
- 80045a8: 2b00 cmp r3, #0
- 80045aa: d009 beq.n 80045c0 <HAL_UART_IRQHandler+0xec>
+ 8004758: 69fb ldr r3, [r7, #28]
+ 800475a: f003 0304 and.w r3, r3, #4
+ 800475e: 2b00 cmp r3, #0
+ 8004760: d00e beq.n 8004780 <HAL_UART_IRQHandler+0xec>
+ 8004762: 697b ldr r3, [r7, #20]
+ 8004764: f003 0301 and.w r3, r3, #1
+ 8004768: 2b00 cmp r3, #0
+ 800476a: d009 beq.n 8004780 <HAL_UART_IRQHandler+0xec>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
- 80045ac: 687b ldr r3, [r7, #4]
- 80045ae: 681b ldr r3, [r3, #0]
- 80045b0: 2204 movs r2, #4
- 80045b2: 621a str r2, [r3, #32]
+ 800476c: 687b ldr r3, [r7, #4]
+ 800476e: 681b ldr r3, [r3, #0]
+ 8004770: 2204 movs r2, #4
+ 8004772: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
- 80045b4: 687b ldr r3, [r7, #4]
- 80045b6: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80045b8: f043 0202 orr.w r2, r3, #2
- 80045bc: 687b ldr r3, [r7, #4]
- 80045be: 67da str r2, [r3, #124] ; 0x7c
+ 8004774: 687b ldr r3, [r7, #4]
+ 8004776: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8004778: f043 0202 orr.w r2, r3, #2
+ 800477c: 687b ldr r3, [r7, #4]
+ 800477e: 67da str r2, [r3, #124] ; 0x7c
}
/* UART Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U)
- 80045c0: 69fb ldr r3, [r7, #28]
- 80045c2: f003 0308 and.w r3, r3, #8
- 80045c6: 2b00 cmp r3, #0
- 80045c8: d013 beq.n 80045f2 <HAL_UART_IRQHandler+0x11e>
+ 8004780: 69fb ldr r3, [r7, #28]
+ 8004782: f003 0308 and.w r3, r3, #8
+ 8004786: 2b00 cmp r3, #0
+ 8004788: d013 beq.n 80047b2 <HAL_UART_IRQHandler+0x11e>
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 80045ca: 69bb ldr r3, [r7, #24]
- 80045cc: f003 0320 and.w r3, r3, #32
- 80045d0: 2b00 cmp r3, #0
- 80045d2: d104 bne.n 80045de <HAL_UART_IRQHandler+0x10a>
+ 800478a: 69bb ldr r3, [r7, #24]
+ 800478c: f003 0320 and.w r3, r3, #32
+ 8004790: 2b00 cmp r3, #0
+ 8004792: d104 bne.n 800479e <HAL_UART_IRQHandler+0x10a>
((cr3its & USART_CR3_EIE) != 0U)))
- 80045d4: 697b ldr r3, [r7, #20]
- 80045d6: f003 0301 and.w r3, r3, #1
+ 8004794: 697b ldr r3, [r7, #20]
+ 8004796: f003 0301 and.w r3, r3, #1
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 80045da: 2b00 cmp r3, #0
- 80045dc: d009 beq.n 80045f2 <HAL_UART_IRQHandler+0x11e>
+ 800479a: 2b00 cmp r3, #0
+ 800479c: d009 beq.n 80047b2 <HAL_UART_IRQHandler+0x11e>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 80045de: 687b ldr r3, [r7, #4]
- 80045e0: 681b ldr r3, [r3, #0]
- 80045e2: 2208 movs r2, #8
- 80045e4: 621a str r2, [r3, #32]
+ 800479e: 687b ldr r3, [r7, #4]
+ 80047a0: 681b ldr r3, [r3, #0]
+ 80047a2: 2208 movs r2, #8
+ 80047a4: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 80045e6: 687b ldr r3, [r7, #4]
- 80045e8: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80045ea: f043 0208 orr.w r2, r3, #8
- 80045ee: 687b ldr r3, [r7, #4]
- 80045f0: 67da str r2, [r3, #124] ; 0x7c
+ 80047a6: 687b ldr r3, [r7, #4]
+ 80047a8: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 80047aa: f043 0208 orr.w r2, r3, #8
+ 80047ae: 687b ldr r3, [r7, #4]
+ 80047b0: 67da str r2, [r3, #124] ; 0x7c
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 80045f2: 687b ldr r3, [r7, #4]
- 80045f4: 6fdb ldr r3, [r3, #124] ; 0x7c
- 80045f6: 2b00 cmp r3, #0
- 80045f8: d07f beq.n 80046fa <HAL_UART_IRQHandler+0x226>
+ 80047b2: 687b ldr r3, [r7, #4]
+ 80047b4: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 80047b6: 2b00 cmp r3, #0
+ 80047b8: d07f beq.n 80048ba <HAL_UART_IRQHandler+0x226>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
- 80045fa: 69fb ldr r3, [r7, #28]
- 80045fc: f003 0320 and.w r3, r3, #32
- 8004600: 2b00 cmp r3, #0
- 8004602: d00c beq.n 800461e <HAL_UART_IRQHandler+0x14a>
+ 80047ba: 69fb ldr r3, [r7, #28]
+ 80047bc: f003 0320 and.w r3, r3, #32
+ 80047c0: 2b00 cmp r3, #0
+ 80047c2: d00c beq.n 80047de <HAL_UART_IRQHandler+0x14a>
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
- 8004604: 69bb ldr r3, [r7, #24]
- 8004606: f003 0320 and.w r3, r3, #32
- 800460a: 2b00 cmp r3, #0
- 800460c: d007 beq.n 800461e <HAL_UART_IRQHandler+0x14a>
+ 80047c4: 69bb ldr r3, [r7, #24]
+ 80047c6: f003 0320 and.w r3, r3, #32
+ 80047ca: 2b00 cmp r3, #0
+ 80047cc: d007 beq.n 80047de <HAL_UART_IRQHandler+0x14a>
{
if (huart->RxISR != NULL)
- 800460e: 687b ldr r3, [r7, #4]
- 8004610: 6e1b ldr r3, [r3, #96] ; 0x60
- 8004612: 2b00 cmp r3, #0
- 8004614: d003 beq.n 800461e <HAL_UART_IRQHandler+0x14a>
+ 80047ce: 687b ldr r3, [r7, #4]
+ 80047d0: 6e1b ldr r3, [r3, #96] ; 0x60
+ 80047d2: 2b00 cmp r3, #0
+ 80047d4: d003 beq.n 80047de <HAL_UART_IRQHandler+0x14a>
{
huart->RxISR(huart);
- 8004616: 687b ldr r3, [r7, #4]
- 8004618: 6e1b ldr r3, [r3, #96] ; 0x60
- 800461a: 6878 ldr r0, [r7, #4]
- 800461c: 4798 blx r3
+ 80047d6: 687b ldr r3, [r7, #4]
+ 80047d8: 6e1b ldr r3, [r3, #96] ; 0x60
+ 80047da: 6878 ldr r0, [r7, #4]
+ 80047dc: 4798 blx r3
}
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
errorcode = huart->ErrorCode;
- 800461e: 687b ldr r3, [r7, #4]
- 8004620: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8004622: 60fb str r3, [r7, #12]
+ 80047de: 687b ldr r3, [r7, #4]
+ 80047e0: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 80047e2: 60fb str r3, [r7, #12]
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8004624: 687b ldr r3, [r7, #4]
- 8004626: 681b ldr r3, [r3, #0]
- 8004628: 689b ldr r3, [r3, #8]
- 800462a: f003 0340 and.w r3, r3, #64 ; 0x40
- 800462e: 2b40 cmp r3, #64 ; 0x40
- 8004630: d004 beq.n 800463c <HAL_UART_IRQHandler+0x168>
+ 80047e4: 687b ldr r3, [r7, #4]
+ 80047e6: 681b ldr r3, [r3, #0]
+ 80047e8: 689b ldr r3, [r3, #8]
+ 80047ea: f003 0340 and.w r3, r3, #64 ; 0x40
+ 80047ee: 2b40 cmp r3, #64 ; 0x40
+ 80047f0: d004 beq.n 80047fc <HAL_UART_IRQHandler+0x168>
((errorcode & HAL_UART_ERROR_ORE) != 0U))
- 8004632: 68fb ldr r3, [r7, #12]
- 8004634: f003 0308 and.w r3, r3, #8
+ 80047f2: 68fb ldr r3, [r7, #12]
+ 80047f4: f003 0308 and.w r3, r3, #8
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8004638: 2b00 cmp r3, #0
- 800463a: d031 beq.n 80046a0 <HAL_UART_IRQHandler+0x1cc>
+ 80047f8: 2b00 cmp r3, #0
+ 80047fa: d031 beq.n 8004860 <HAL_UART_IRQHandler+0x1cc>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- 800463c: 6878 ldr r0, [r7, #4]
- 800463e: f000 fc36 bl 8004eae <UART_EndRxTransfer>
+ 80047fc: 6878 ldr r0, [r7, #4]
+ 80047fe: f000 fc36 bl 800506e <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004642: 687b ldr r3, [r7, #4]
- 8004644: 681b ldr r3, [r3, #0]
- 8004646: 689b ldr r3, [r3, #8]
- 8004648: f003 0340 and.w r3, r3, #64 ; 0x40
- 800464c: 2b40 cmp r3, #64 ; 0x40
- 800464e: d123 bne.n 8004698 <HAL_UART_IRQHandler+0x1c4>
+ 8004802: 687b ldr r3, [r7, #4]
+ 8004804: 681b ldr r3, [r3, #0]
+ 8004806: 689b ldr r3, [r3, #8]
+ 8004808: f003 0340 and.w r3, r3, #64 ; 0x40
+ 800480c: 2b40 cmp r3, #64 ; 0x40
+ 800480e: d123 bne.n 8004858 <HAL_UART_IRQHandler+0x1c4>
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 8004650: 687b ldr r3, [r7, #4]
- 8004652: 681b ldr r3, [r3, #0]
- 8004654: 689a ldr r2, [r3, #8]
- 8004656: 687b ldr r3, [r7, #4]
- 8004658: 681b ldr r3, [r3, #0]
- 800465a: f022 0240 bic.w r2, r2, #64 ; 0x40
- 800465e: 609a str r2, [r3, #8]
+ 8004810: 687b ldr r3, [r7, #4]
+ 8004812: 681b ldr r3, [r3, #0]
+ 8004814: 689a ldr r2, [r3, #8]
+ 8004816: 687b ldr r3, [r7, #4]
+ 8004818: 681b ldr r3, [r3, #0]
+ 800481a: f022 0240 bic.w r2, r2, #64 ; 0x40
+ 800481e: 609a str r2, [r3, #8]
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
- 8004660: 687b ldr r3, [r7, #4]
- 8004662: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004664: 2b00 cmp r3, #0
- 8004666: d013 beq.n 8004690 <HAL_UART_IRQHandler+0x1bc>
+ 8004820: 687b ldr r3, [r7, #4]
+ 8004822: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8004824: 2b00 cmp r3, #0
+ 8004826: d013 beq.n 8004850 <HAL_UART_IRQHandler+0x1bc>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8004668: 687b ldr r3, [r7, #4]
- 800466a: 6edb ldr r3, [r3, #108] ; 0x6c
- 800466c: 4a26 ldr r2, [pc, #152] ; (8004708 <HAL_UART_IRQHandler+0x234>)
- 800466e: 651a str r2, [r3, #80] ; 0x50
+ 8004828: 687b ldr r3, [r7, #4]
+ 800482a: 6edb ldr r3, [r3, #108] ; 0x6c
+ 800482c: 4a26 ldr r2, [pc, #152] ; (80048c8 <HAL_UART_IRQHandler+0x234>)
+ 800482e: 651a str r2, [r3, #80] ; 0x50
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 8004670: 687b ldr r3, [r7, #4]
- 8004672: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004674: 4618 mov r0, r3
- 8004676: f7fd fafe bl 8001c76 <HAL_DMA_Abort_IT>
- 800467a: 4603 mov r3, r0
- 800467c: 2b00 cmp r3, #0
- 800467e: d016 beq.n 80046ae <HAL_UART_IRQHandler+0x1da>
+ 8004830: 687b ldr r3, [r7, #4]
+ 8004832: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8004834: 4618 mov r0, r3
+ 8004836: f7fd fa5c bl 8001cf2 <HAL_DMA_Abort_IT>
+ 800483a: 4603 mov r3, r0
+ 800483c: 2b00 cmp r3, #0
+ 800483e: d016 beq.n 800486e <HAL_UART_IRQHandler+0x1da>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 8004680: 687b ldr r3, [r7, #4]
- 8004682: 6edb ldr r3, [r3, #108] ; 0x6c
- 8004684: 6d1b ldr r3, [r3, #80] ; 0x50
- 8004686: 687a ldr r2, [r7, #4]
- 8004688: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 800468a: 4610 mov r0, r2
- 800468c: 4798 blx r3
+ 8004840: 687b ldr r3, [r7, #4]
+ 8004842: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8004844: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8004846: 687a ldr r2, [r7, #4]
+ 8004848: 6ed2 ldr r2, [r2, #108] ; 0x6c
+ 800484a: 4610 mov r0, r2
+ 800484c: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 800468e: e00e b.n 80046ae <HAL_UART_IRQHandler+0x1da>
+ 800484e: e00e b.n 800486e <HAL_UART_IRQHandler+0x1da>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
- 8004690: 6878 ldr r0, [r7, #4]
- 8004692: f000 f845 bl 8004720 <HAL_UART_ErrorCallback>
+ 8004850: 6878 ldr r0, [r7, #4]
+ 8004852: f000 f845 bl 80048e0 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8004696: e00a b.n 80046ae <HAL_UART_IRQHandler+0x1da>
+ 8004856: e00a b.n 800486e <HAL_UART_IRQHandler+0x1da>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
- 8004698: 6878 ldr r0, [r7, #4]
- 800469a: f000 f841 bl 8004720 <HAL_UART_ErrorCallback>
+ 8004858: 6878 ldr r0, [r7, #4]
+ 800485a: f000 f841 bl 80048e0 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 800469e: e006 b.n 80046ae <HAL_UART_IRQHandler+0x1da>
+ 800485e: e006 b.n 800486e <HAL_UART_IRQHandler+0x1da>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
- 80046a0: 6878 ldr r0, [r7, #4]
- 80046a2: f000 f83d bl 8004720 <HAL_UART_ErrorCallback>
+ 8004860: 6878 ldr r0, [r7, #4]
+ 8004862: f000 f83d bl 80048e0 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80046a6: 687b ldr r3, [r7, #4]
- 80046a8: 2200 movs r2, #0
- 80046aa: 67da str r2, [r3, #124] ; 0x7c
+ 8004866: 687b ldr r3, [r7, #4]
+ 8004868: 2200 movs r2, #0
+ 800486a: 67da str r2, [r3, #124] ; 0x7c
}
}
return;
- 80046ac: e025 b.n 80046fa <HAL_UART_IRQHandler+0x226>
+ 800486c: e025 b.n 80048ba <HAL_UART_IRQHandler+0x226>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 80046ae: bf00 nop
+ 800486e: bf00 nop
return;
- 80046b0: e023 b.n 80046fa <HAL_UART_IRQHandler+0x226>
+ 8004870: e023 b.n 80048ba <HAL_UART_IRQHandler+0x226>
} /* End if some error occurs */
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE) != 0U)
- 80046b2: 69fb ldr r3, [r7, #28]
- 80046b4: f003 0380 and.w r3, r3, #128 ; 0x80
- 80046b8: 2b00 cmp r3, #0
- 80046ba: d00d beq.n 80046d8 <HAL_UART_IRQHandler+0x204>
+ 8004872: 69fb ldr r3, [r7, #28]
+ 8004874: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8004878: 2b00 cmp r3, #0
+ 800487a: d00d beq.n 8004898 <HAL_UART_IRQHandler+0x204>
&& ((cr1its & USART_CR1_TXEIE) != 0U))
- 80046bc: 69bb ldr r3, [r7, #24]
- 80046be: f003 0380 and.w r3, r3, #128 ; 0x80
- 80046c2: 2b00 cmp r3, #0
- 80046c4: d008 beq.n 80046d8 <HAL_UART_IRQHandler+0x204>
+ 800487c: 69bb ldr r3, [r7, #24]
+ 800487e: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8004882: 2b00 cmp r3, #0
+ 8004884: d008 beq.n 8004898 <HAL_UART_IRQHandler+0x204>
{
if (huart->TxISR != NULL)
- 80046c6: 687b ldr r3, [r7, #4]
- 80046c8: 6e5b ldr r3, [r3, #100] ; 0x64
- 80046ca: 2b00 cmp r3, #0
- 80046cc: d017 beq.n 80046fe <HAL_UART_IRQHandler+0x22a>
+ 8004886: 687b ldr r3, [r7, #4]
+ 8004888: 6e5b ldr r3, [r3, #100] ; 0x64
+ 800488a: 2b00 cmp r3, #0
+ 800488c: d017 beq.n 80048be <HAL_UART_IRQHandler+0x22a>
{
huart->TxISR(huart);
- 80046ce: 687b ldr r3, [r7, #4]
- 80046d0: 6e5b ldr r3, [r3, #100] ; 0x64
- 80046d2: 6878 ldr r0, [r7, #4]
- 80046d4: 4798 blx r3
+ 800488e: 687b ldr r3, [r7, #4]
+ 8004890: 6e5b ldr r3, [r3, #100] ; 0x64
+ 8004892: 6878 ldr r0, [r7, #4]
+ 8004894: 4798 blx r3
}
return;
- 80046d6: e012 b.n 80046fe <HAL_UART_IRQHandler+0x22a>
+ 8004896: e012 b.n 80048be <HAL_UART_IRQHandler+0x22a>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
- 80046d8: 69fb ldr r3, [r7, #28]
- 80046da: f003 0340 and.w r3, r3, #64 ; 0x40
- 80046de: 2b00 cmp r3, #0
- 80046e0: d00e beq.n 8004700 <HAL_UART_IRQHandler+0x22c>
- 80046e2: 69bb ldr r3, [r7, #24]
- 80046e4: f003 0340 and.w r3, r3, #64 ; 0x40
- 80046e8: 2b00 cmp r3, #0
- 80046ea: d009 beq.n 8004700 <HAL_UART_IRQHandler+0x22c>
+ 8004898: 69fb ldr r3, [r7, #28]
+ 800489a: f003 0340 and.w r3, r3, #64 ; 0x40
+ 800489e: 2b00 cmp r3, #0
+ 80048a0: d00e beq.n 80048c0 <HAL_UART_IRQHandler+0x22c>
+ 80048a2: 69bb ldr r3, [r7, #24]
+ 80048a4: f003 0340 and.w r3, r3, #64 ; 0x40
+ 80048a8: 2b00 cmp r3, #0
+ 80048aa: d009 beq.n 80048c0 <HAL_UART_IRQHandler+0x22c>
{
UART_EndTransmit_IT(huart);
- 80046ec: 6878 ldr r0, [r7, #4]
- 80046ee: f000 fc14 bl 8004f1a <UART_EndTransmit_IT>
+ 80048ac: 6878 ldr r0, [r7, #4]
+ 80048ae: f000 fc14 bl 80050da <UART_EndTransmit_IT>
return;
- 80046f2: bf00 nop
- 80046f4: e004 b.n 8004700 <HAL_UART_IRQHandler+0x22c>
+ 80048b2: bf00 nop
+ 80048b4: e004 b.n 80048c0 <HAL_UART_IRQHandler+0x22c>
return;
- 80046f6: bf00 nop
- 80046f8: e002 b.n 8004700 <HAL_UART_IRQHandler+0x22c>
+ 80048b6: bf00 nop
+ 80048b8: e002 b.n 80048c0 <HAL_UART_IRQHandler+0x22c>
return;
- 80046fa: bf00 nop
- 80046fc: e000 b.n 8004700 <HAL_UART_IRQHandler+0x22c>
+ 80048ba: bf00 nop
+ 80048bc: e000 b.n 80048c0 <HAL_UART_IRQHandler+0x22c>
return;
- 80046fe: bf00 nop
+ 80048be: bf00 nop
}
}
- 8004700: 3720 adds r7, #32
- 8004702: 46bd mov sp, r7
- 8004704: bd80 pop {r7, pc}
- 8004706: bf00 nop
- 8004708: 08004eef .word 0x08004eef
+ 80048c0: 3720 adds r7, #32
+ 80048c2: 46bd mov sp, r7
+ 80048c4: bd80 pop {r7, pc}
+ 80048c6: bf00 nop
+ 80048c8: 080050af .word 0x080050af
-0800470c <HAL_UART_TxCpltCallback>:
+080048cc <HAL_UART_TxCpltCallback>:
* @brief Tx Transfer completed callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
- 800470c: b480 push {r7}
- 800470e: b083 sub sp, #12
- 8004710: af00 add r7, sp, #0
- 8004712: 6078 str r0, [r7, #4]
+ 80048cc: b480 push {r7}
+ 80048ce: b083 sub sp, #12
+ 80048d0: af00 add r7, sp, #0
+ 80048d2: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback can be implemented in the user file.
*/
}
- 8004714: bf00 nop
- 8004716: 370c adds r7, #12
- 8004718: 46bd mov sp, r7
- 800471a: f85d 7b04 ldr.w r7, [sp], #4
- 800471e: 4770 bx lr
+ 80048d4: bf00 nop
+ 80048d6: 370c adds r7, #12
+ 80048d8: 46bd mov sp, r7
+ 80048da: f85d 7b04 ldr.w r7, [sp], #4
+ 80048de: 4770 bx lr
-08004720 <HAL_UART_ErrorCallback>:
+080048e0 <HAL_UART_ErrorCallback>:
* @brief UART error callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
- 8004720: b480 push {r7}
- 8004722: b083 sub sp, #12
- 8004724: af00 add r7, sp, #0
- 8004726: 6078 str r0, [r7, #4]
+ 80048e0: b480 push {r7}
+ 80048e2: b083 sub sp, #12
+ 80048e4: af00 add r7, sp, #0
+ 80048e6: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file.
*/
}
- 8004728: bf00 nop
- 800472a: 370c adds r7, #12
- 800472c: 46bd mov sp, r7
- 800472e: f85d 7b04 ldr.w r7, [sp], #4
- 8004732: 4770 bx lr
+ 80048e8: bf00 nop
+ 80048ea: 370c adds r7, #12
+ 80048ec: 46bd mov sp, r7
+ 80048ee: f85d 7b04 ldr.w r7, [sp], #4
+ 80048f2: 4770 bx lr
-08004734 <UART_SetConfig>:
+080048f4 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
- 8004734: b580 push {r7, lr}
- 8004736: b088 sub sp, #32
- 8004738: af00 add r7, sp, #0
- 800473a: 6078 str r0, [r7, #4]
+ 80048f4: b580 push {r7, lr}
+ 80048f6: b088 sub sp, #32
+ 80048f8: af00 add r7, sp, #0
+ 80048fa: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv = 0x00000000U;
- 800473c: 2300 movs r3, #0
- 800473e: 61bb str r3, [r7, #24]
+ 80048fc: 2300 movs r3, #0
+ 80048fe: 61bb str r3, [r7, #24]
HAL_StatusTypeDef ret = HAL_OK;
- 8004740: 2300 movs r3, #0
- 8004742: 75fb strb r3, [r7, #23]
+ 8004900: 2300 movs r3, #0
+ 8004902: 75fb strb r3, [r7, #23]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 8004744: 687b ldr r3, [r7, #4]
- 8004746: 689a ldr r2, [r3, #8]
- 8004748: 687b ldr r3, [r7, #4]
- 800474a: 691b ldr r3, [r3, #16]
- 800474c: 431a orrs r2, r3
- 800474e: 687b ldr r3, [r7, #4]
- 8004750: 695b ldr r3, [r3, #20]
- 8004752: 431a orrs r2, r3
- 8004754: 687b ldr r3, [r7, #4]
- 8004756: 69db ldr r3, [r3, #28]
- 8004758: 4313 orrs r3, r2
- 800475a: 613b str r3, [r7, #16]
+ 8004904: 687b ldr r3, [r7, #4]
+ 8004906: 689a ldr r2, [r3, #8]
+ 8004908: 687b ldr r3, [r7, #4]
+ 800490a: 691b ldr r3, [r3, #16]
+ 800490c: 431a orrs r2, r3
+ 800490e: 687b ldr r3, [r7, #4]
+ 8004910: 695b ldr r3, [r3, #20]
+ 8004912: 431a orrs r2, r3
+ 8004914: 687b ldr r3, [r7, #4]
+ 8004916: 69db ldr r3, [r3, #28]
+ 8004918: 4313 orrs r3, r2
+ 800491a: 613b str r3, [r7, #16]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 800475c: 687b ldr r3, [r7, #4]
- 800475e: 681b ldr r3, [r3, #0]
- 8004760: 681a ldr r2, [r3, #0]
- 8004762: 4bb1 ldr r3, [pc, #708] ; (8004a28 <UART_SetConfig+0x2f4>)
- 8004764: 4013 ands r3, r2
- 8004766: 687a ldr r2, [r7, #4]
- 8004768: 6812 ldr r2, [r2, #0]
- 800476a: 6939 ldr r1, [r7, #16]
- 800476c: 430b orrs r3, r1
- 800476e: 6013 str r3, [r2, #0]
+ 800491c: 687b ldr r3, [r7, #4]
+ 800491e: 681b ldr r3, [r3, #0]
+ 8004920: 681a ldr r2, [r3, #0]
+ 8004922: 4bb1 ldr r3, [pc, #708] ; (8004be8 <UART_SetConfig+0x2f4>)
+ 8004924: 4013 ands r3, r2
+ 8004926: 687a ldr r2, [r7, #4]
+ 8004928: 6812 ldr r2, [r2, #0]
+ 800492a: 6939 ldr r1, [r7, #16]
+ 800492c: 430b orrs r3, r1
+ 800492e: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8004770: 687b ldr r3, [r7, #4]
- 8004772: 681b ldr r3, [r3, #0]
- 8004774: 685b ldr r3, [r3, #4]
- 8004776: f423 5140 bic.w r1, r3, #12288 ; 0x3000
- 800477a: 687b ldr r3, [r7, #4]
- 800477c: 68da ldr r2, [r3, #12]
- 800477e: 687b ldr r3, [r7, #4]
- 8004780: 681b ldr r3, [r3, #0]
- 8004782: 430a orrs r2, r1
- 8004784: 605a str r2, [r3, #4]
+ 8004930: 687b ldr r3, [r7, #4]
+ 8004932: 681b ldr r3, [r3, #0]
+ 8004934: 685b ldr r3, [r3, #4]
+ 8004936: f423 5140 bic.w r1, r3, #12288 ; 0x3000
+ 800493a: 687b ldr r3, [r7, #4]
+ 800493c: 68da ldr r2, [r3, #12]
+ 800493e: 687b ldr r3, [r7, #4]
+ 8004940: 681b ldr r3, [r3, #0]
+ 8004942: 430a orrs r2, r1
+ 8004944: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8004786: 687b ldr r3, [r7, #4]
- 8004788: 699b ldr r3, [r3, #24]
- 800478a: 613b str r3, [r7, #16]
+ 8004946: 687b ldr r3, [r7, #4]
+ 8004948: 699b ldr r3, [r3, #24]
+ 800494a: 613b str r3, [r7, #16]
tmpreg |= huart->Init.OneBitSampling;
- 800478c: 687b ldr r3, [r7, #4]
- 800478e: 6a1b ldr r3, [r3, #32]
- 8004790: 693a ldr r2, [r7, #16]
- 8004792: 4313 orrs r3, r2
- 8004794: 613b str r3, [r7, #16]
+ 800494c: 687b ldr r3, [r7, #4]
+ 800494e: 6a1b ldr r3, [r3, #32]
+ 8004950: 693a ldr r2, [r7, #16]
+ 8004952: 4313 orrs r3, r2
+ 8004954: 613b str r3, [r7, #16]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8004796: 687b ldr r3, [r7, #4]
- 8004798: 681b ldr r3, [r3, #0]
- 800479a: 689b ldr r3, [r3, #8]
- 800479c: f423 6130 bic.w r1, r3, #2816 ; 0xb00
- 80047a0: 687b ldr r3, [r7, #4]
- 80047a2: 681b ldr r3, [r3, #0]
- 80047a4: 693a ldr r2, [r7, #16]
- 80047a6: 430a orrs r2, r1
- 80047a8: 609a str r2, [r3, #8]
+ 8004956: 687b ldr r3, [r7, #4]
+ 8004958: 681b ldr r3, [r3, #0]
+ 800495a: 689b ldr r3, [r3, #8]
+ 800495c: f423 6130 bic.w r1, r3, #2816 ; 0xb00
+ 8004960: 687b ldr r3, [r7, #4]
+ 8004962: 681b ldr r3, [r3, #0]
+ 8004964: 693a ldr r2, [r7, #16]
+ 8004966: 430a orrs r2, r1
+ 8004968: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
- 80047aa: 687b ldr r3, [r7, #4]
- 80047ac: 681b ldr r3, [r3, #0]
- 80047ae: 4a9f ldr r2, [pc, #636] ; (8004a2c <UART_SetConfig+0x2f8>)
- 80047b0: 4293 cmp r3, r2
- 80047b2: d121 bne.n 80047f8 <UART_SetConfig+0xc4>
- 80047b4: 4b9e ldr r3, [pc, #632] ; (8004a30 <UART_SetConfig+0x2fc>)
- 80047b6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80047ba: f003 0303 and.w r3, r3, #3
- 80047be: 2b03 cmp r3, #3
- 80047c0: d816 bhi.n 80047f0 <UART_SetConfig+0xbc>
- 80047c2: a201 add r2, pc, #4 ; (adr r2, 80047c8 <UART_SetConfig+0x94>)
- 80047c4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 80047c8: 080047d9 .word 0x080047d9
- 80047cc: 080047e5 .word 0x080047e5
- 80047d0: 080047df .word 0x080047df
- 80047d4: 080047eb .word 0x080047eb
- 80047d8: 2301 movs r3, #1
- 80047da: 77fb strb r3, [r7, #31]
- 80047dc: e151 b.n 8004a82 <UART_SetConfig+0x34e>
- 80047de: 2302 movs r3, #2
- 80047e0: 77fb strb r3, [r7, #31]
- 80047e2: e14e b.n 8004a82 <UART_SetConfig+0x34e>
- 80047e4: 2304 movs r3, #4
- 80047e6: 77fb strb r3, [r7, #31]
- 80047e8: e14b b.n 8004a82 <UART_SetConfig+0x34e>
- 80047ea: 2308 movs r3, #8
- 80047ec: 77fb strb r3, [r7, #31]
- 80047ee: e148 b.n 8004a82 <UART_SetConfig+0x34e>
- 80047f0: 2310 movs r3, #16
- 80047f2: 77fb strb r3, [r7, #31]
- 80047f4: bf00 nop
- 80047f6: e144 b.n 8004a82 <UART_SetConfig+0x34e>
- 80047f8: 687b ldr r3, [r7, #4]
- 80047fa: 681b ldr r3, [r3, #0]
- 80047fc: 4a8d ldr r2, [pc, #564] ; (8004a34 <UART_SetConfig+0x300>)
- 80047fe: 4293 cmp r3, r2
- 8004800: d134 bne.n 800486c <UART_SetConfig+0x138>
- 8004802: 4b8b ldr r3, [pc, #556] ; (8004a30 <UART_SetConfig+0x2fc>)
- 8004804: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004808: f003 030c and.w r3, r3, #12
- 800480c: 2b0c cmp r3, #12
- 800480e: d829 bhi.n 8004864 <UART_SetConfig+0x130>
- 8004810: a201 add r2, pc, #4 ; (adr r2, 8004818 <UART_SetConfig+0xe4>)
- 8004812: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004816: bf00 nop
- 8004818: 0800484d .word 0x0800484d
- 800481c: 08004865 .word 0x08004865
- 8004820: 08004865 .word 0x08004865
- 8004824: 08004865 .word 0x08004865
- 8004828: 08004859 .word 0x08004859
- 800482c: 08004865 .word 0x08004865
- 8004830: 08004865 .word 0x08004865
- 8004834: 08004865 .word 0x08004865
- 8004838: 08004853 .word 0x08004853
- 800483c: 08004865 .word 0x08004865
- 8004840: 08004865 .word 0x08004865
- 8004844: 08004865 .word 0x08004865
- 8004848: 0800485f .word 0x0800485f
- 800484c: 2300 movs r3, #0
- 800484e: 77fb strb r3, [r7, #31]
- 8004850: e117 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004852: 2302 movs r3, #2
- 8004854: 77fb strb r3, [r7, #31]
- 8004856: e114 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004858: 2304 movs r3, #4
- 800485a: 77fb strb r3, [r7, #31]
- 800485c: e111 b.n 8004a82 <UART_SetConfig+0x34e>
- 800485e: 2308 movs r3, #8
- 8004860: 77fb strb r3, [r7, #31]
- 8004862: e10e b.n 8004a82 <UART_SetConfig+0x34e>
- 8004864: 2310 movs r3, #16
- 8004866: 77fb strb r3, [r7, #31]
- 8004868: bf00 nop
- 800486a: e10a b.n 8004a82 <UART_SetConfig+0x34e>
- 800486c: 687b ldr r3, [r7, #4]
- 800486e: 681b ldr r3, [r3, #0]
- 8004870: 4a71 ldr r2, [pc, #452] ; (8004a38 <UART_SetConfig+0x304>)
- 8004872: 4293 cmp r3, r2
- 8004874: d120 bne.n 80048b8 <UART_SetConfig+0x184>
- 8004876: 4b6e ldr r3, [pc, #440] ; (8004a30 <UART_SetConfig+0x2fc>)
- 8004878: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800487c: f003 0330 and.w r3, r3, #48 ; 0x30
- 8004880: 2b10 cmp r3, #16
- 8004882: d00f beq.n 80048a4 <UART_SetConfig+0x170>
- 8004884: 2b10 cmp r3, #16
- 8004886: d802 bhi.n 800488e <UART_SetConfig+0x15a>
- 8004888: 2b00 cmp r3, #0
- 800488a: d005 beq.n 8004898 <UART_SetConfig+0x164>
- 800488c: e010 b.n 80048b0 <UART_SetConfig+0x17c>
- 800488e: 2b20 cmp r3, #32
- 8004890: d005 beq.n 800489e <UART_SetConfig+0x16a>
- 8004892: 2b30 cmp r3, #48 ; 0x30
- 8004894: d009 beq.n 80048aa <UART_SetConfig+0x176>
- 8004896: e00b b.n 80048b0 <UART_SetConfig+0x17c>
- 8004898: 2300 movs r3, #0
- 800489a: 77fb strb r3, [r7, #31]
- 800489c: e0f1 b.n 8004a82 <UART_SetConfig+0x34e>
- 800489e: 2302 movs r3, #2
- 80048a0: 77fb strb r3, [r7, #31]
- 80048a2: e0ee b.n 8004a82 <UART_SetConfig+0x34e>
- 80048a4: 2304 movs r3, #4
- 80048a6: 77fb strb r3, [r7, #31]
- 80048a8: e0eb b.n 8004a82 <UART_SetConfig+0x34e>
- 80048aa: 2308 movs r3, #8
- 80048ac: 77fb strb r3, [r7, #31]
- 80048ae: e0e8 b.n 8004a82 <UART_SetConfig+0x34e>
- 80048b0: 2310 movs r3, #16
- 80048b2: 77fb strb r3, [r7, #31]
- 80048b4: bf00 nop
- 80048b6: e0e4 b.n 8004a82 <UART_SetConfig+0x34e>
- 80048b8: 687b ldr r3, [r7, #4]
- 80048ba: 681b ldr r3, [r3, #0]
- 80048bc: 4a5f ldr r2, [pc, #380] ; (8004a3c <UART_SetConfig+0x308>)
- 80048be: 4293 cmp r3, r2
- 80048c0: d120 bne.n 8004904 <UART_SetConfig+0x1d0>
- 80048c2: 4b5b ldr r3, [pc, #364] ; (8004a30 <UART_SetConfig+0x2fc>)
- 80048c4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80048c8: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 80048cc: 2b40 cmp r3, #64 ; 0x40
- 80048ce: d00f beq.n 80048f0 <UART_SetConfig+0x1bc>
- 80048d0: 2b40 cmp r3, #64 ; 0x40
- 80048d2: d802 bhi.n 80048da <UART_SetConfig+0x1a6>
- 80048d4: 2b00 cmp r3, #0
- 80048d6: d005 beq.n 80048e4 <UART_SetConfig+0x1b0>
- 80048d8: e010 b.n 80048fc <UART_SetConfig+0x1c8>
- 80048da: 2b80 cmp r3, #128 ; 0x80
- 80048dc: d005 beq.n 80048ea <UART_SetConfig+0x1b6>
- 80048de: 2bc0 cmp r3, #192 ; 0xc0
- 80048e0: d009 beq.n 80048f6 <UART_SetConfig+0x1c2>
- 80048e2: e00b b.n 80048fc <UART_SetConfig+0x1c8>
- 80048e4: 2300 movs r3, #0
- 80048e6: 77fb strb r3, [r7, #31]
- 80048e8: e0cb b.n 8004a82 <UART_SetConfig+0x34e>
- 80048ea: 2302 movs r3, #2
- 80048ec: 77fb strb r3, [r7, #31]
- 80048ee: e0c8 b.n 8004a82 <UART_SetConfig+0x34e>
- 80048f0: 2304 movs r3, #4
- 80048f2: 77fb strb r3, [r7, #31]
- 80048f4: e0c5 b.n 8004a82 <UART_SetConfig+0x34e>
- 80048f6: 2308 movs r3, #8
- 80048f8: 77fb strb r3, [r7, #31]
- 80048fa: e0c2 b.n 8004a82 <UART_SetConfig+0x34e>
- 80048fc: 2310 movs r3, #16
- 80048fe: 77fb strb r3, [r7, #31]
- 8004900: bf00 nop
- 8004902: e0be b.n 8004a82 <UART_SetConfig+0x34e>
- 8004904: 687b ldr r3, [r7, #4]
- 8004906: 681b ldr r3, [r3, #0]
- 8004908: 4a4d ldr r2, [pc, #308] ; (8004a40 <UART_SetConfig+0x30c>)
- 800490a: 4293 cmp r3, r2
- 800490c: d124 bne.n 8004958 <UART_SetConfig+0x224>
- 800490e: 4b48 ldr r3, [pc, #288] ; (8004a30 <UART_SetConfig+0x2fc>)
- 8004910: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004914: f403 7340 and.w r3, r3, #768 ; 0x300
- 8004918: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 800491c: d012 beq.n 8004944 <UART_SetConfig+0x210>
- 800491e: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8004922: d802 bhi.n 800492a <UART_SetConfig+0x1f6>
- 8004924: 2b00 cmp r3, #0
- 8004926: d007 beq.n 8004938 <UART_SetConfig+0x204>
- 8004928: e012 b.n 8004950 <UART_SetConfig+0x21c>
- 800492a: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 800492e: d006 beq.n 800493e <UART_SetConfig+0x20a>
- 8004930: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8004934: d009 beq.n 800494a <UART_SetConfig+0x216>
- 8004936: e00b b.n 8004950 <UART_SetConfig+0x21c>
- 8004938: 2300 movs r3, #0
- 800493a: 77fb strb r3, [r7, #31]
- 800493c: e0a1 b.n 8004a82 <UART_SetConfig+0x34e>
- 800493e: 2302 movs r3, #2
- 8004940: 77fb strb r3, [r7, #31]
- 8004942: e09e b.n 8004a82 <UART_SetConfig+0x34e>
- 8004944: 2304 movs r3, #4
- 8004946: 77fb strb r3, [r7, #31]
- 8004948: e09b b.n 8004a82 <UART_SetConfig+0x34e>
- 800494a: 2308 movs r3, #8
- 800494c: 77fb strb r3, [r7, #31]
- 800494e: e098 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004950: 2310 movs r3, #16
- 8004952: 77fb strb r3, [r7, #31]
- 8004954: bf00 nop
- 8004956: e094 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004958: 687b ldr r3, [r7, #4]
- 800495a: 681b ldr r3, [r3, #0]
- 800495c: 4a39 ldr r2, [pc, #228] ; (8004a44 <UART_SetConfig+0x310>)
- 800495e: 4293 cmp r3, r2
- 8004960: d124 bne.n 80049ac <UART_SetConfig+0x278>
- 8004962: 4b33 ldr r3, [pc, #204] ; (8004a30 <UART_SetConfig+0x2fc>)
- 8004964: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004968: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 800496c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004970: d012 beq.n 8004998 <UART_SetConfig+0x264>
- 8004972: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8004976: d802 bhi.n 800497e <UART_SetConfig+0x24a>
- 8004978: 2b00 cmp r3, #0
- 800497a: d007 beq.n 800498c <UART_SetConfig+0x258>
- 800497c: e012 b.n 80049a4 <UART_SetConfig+0x270>
- 800497e: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 8004982: d006 beq.n 8004992 <UART_SetConfig+0x25e>
- 8004984: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 8004988: d009 beq.n 800499e <UART_SetConfig+0x26a>
- 800498a: e00b b.n 80049a4 <UART_SetConfig+0x270>
- 800498c: 2301 movs r3, #1
- 800498e: 77fb strb r3, [r7, #31]
- 8004990: e077 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004992: 2302 movs r3, #2
- 8004994: 77fb strb r3, [r7, #31]
- 8004996: e074 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004998: 2304 movs r3, #4
+ 800496a: 687b ldr r3, [r7, #4]
+ 800496c: 681b ldr r3, [r3, #0]
+ 800496e: 4a9f ldr r2, [pc, #636] ; (8004bec <UART_SetConfig+0x2f8>)
+ 8004970: 4293 cmp r3, r2
+ 8004972: d121 bne.n 80049b8 <UART_SetConfig+0xc4>
+ 8004974: 4b9e ldr r3, [pc, #632] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 8004976: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 800497a: f003 0303 and.w r3, r3, #3
+ 800497e: 2b03 cmp r3, #3
+ 8004980: d816 bhi.n 80049b0 <UART_SetConfig+0xbc>
+ 8004982: a201 add r2, pc, #4 ; (adr r2, 8004988 <UART_SetConfig+0x94>)
+ 8004984: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 8004988: 08004999 .word 0x08004999
+ 800498c: 080049a5 .word 0x080049a5
+ 8004990: 0800499f .word 0x0800499f
+ 8004994: 080049ab .word 0x080049ab
+ 8004998: 2301 movs r3, #1
800499a: 77fb strb r3, [r7, #31]
- 800499c: e071 b.n 8004a82 <UART_SetConfig+0x34e>
- 800499e: 2308 movs r3, #8
+ 800499c: e151 b.n 8004c42 <UART_SetConfig+0x34e>
+ 800499e: 2302 movs r3, #2
80049a0: 77fb strb r3, [r7, #31]
- 80049a2: e06e b.n 8004a82 <UART_SetConfig+0x34e>
- 80049a4: 2310 movs r3, #16
+ 80049a2: e14e b.n 8004c42 <UART_SetConfig+0x34e>
+ 80049a4: 2304 movs r3, #4
80049a6: 77fb strb r3, [r7, #31]
- 80049a8: bf00 nop
- 80049aa: e06a b.n 8004a82 <UART_SetConfig+0x34e>
- 80049ac: 687b ldr r3, [r7, #4]
- 80049ae: 681b ldr r3, [r3, #0]
- 80049b0: 4a25 ldr r2, [pc, #148] ; (8004a48 <UART_SetConfig+0x314>)
- 80049b2: 4293 cmp r3, r2
- 80049b4: d124 bne.n 8004a00 <UART_SetConfig+0x2cc>
- 80049b6: 4b1e ldr r3, [pc, #120] ; (8004a30 <UART_SetConfig+0x2fc>)
- 80049b8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80049bc: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 80049c0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80049c4: d012 beq.n 80049ec <UART_SetConfig+0x2b8>
- 80049c6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80049ca: d802 bhi.n 80049d2 <UART_SetConfig+0x29e>
- 80049cc: 2b00 cmp r3, #0
- 80049ce: d007 beq.n 80049e0 <UART_SetConfig+0x2ac>
- 80049d0: e012 b.n 80049f8 <UART_SetConfig+0x2c4>
- 80049d2: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 80049d6: d006 beq.n 80049e6 <UART_SetConfig+0x2b2>
- 80049d8: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 80049dc: d009 beq.n 80049f2 <UART_SetConfig+0x2be>
- 80049de: e00b b.n 80049f8 <UART_SetConfig+0x2c4>
- 80049e0: 2300 movs r3, #0
- 80049e2: 77fb strb r3, [r7, #31]
- 80049e4: e04d b.n 8004a82 <UART_SetConfig+0x34e>
- 80049e6: 2302 movs r3, #2
- 80049e8: 77fb strb r3, [r7, #31]
- 80049ea: e04a b.n 8004a82 <UART_SetConfig+0x34e>
- 80049ec: 2304 movs r3, #4
- 80049ee: 77fb strb r3, [r7, #31]
- 80049f0: e047 b.n 8004a82 <UART_SetConfig+0x34e>
- 80049f2: 2308 movs r3, #8
- 80049f4: 77fb strb r3, [r7, #31]
- 80049f6: e044 b.n 8004a82 <UART_SetConfig+0x34e>
- 80049f8: 2310 movs r3, #16
- 80049fa: 77fb strb r3, [r7, #31]
- 80049fc: bf00 nop
- 80049fe: e040 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004a00: 687b ldr r3, [r7, #4]
- 8004a02: 681b ldr r3, [r3, #0]
- 8004a04: 4a11 ldr r2, [pc, #68] ; (8004a4c <UART_SetConfig+0x318>)
- 8004a06: 4293 cmp r3, r2
- 8004a08: d139 bne.n 8004a7e <UART_SetConfig+0x34a>
- 8004a0a: 4b09 ldr r3, [pc, #36] ; (8004a30 <UART_SetConfig+0x2fc>)
- 8004a0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8004a10: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8004a14: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004a18: d027 beq.n 8004a6a <UART_SetConfig+0x336>
- 8004a1a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8004a1e: d817 bhi.n 8004a50 <UART_SetConfig+0x31c>
- 8004a20: 2b00 cmp r3, #0
- 8004a22: d01c beq.n 8004a5e <UART_SetConfig+0x32a>
- 8004a24: e027 b.n 8004a76 <UART_SetConfig+0x342>
- 8004a26: bf00 nop
- 8004a28: efff69f3 .word 0xefff69f3
- 8004a2c: 40011000 .word 0x40011000
- 8004a30: 40023800 .word 0x40023800
- 8004a34: 40004400 .word 0x40004400
- 8004a38: 40004800 .word 0x40004800
- 8004a3c: 40004c00 .word 0x40004c00
- 8004a40: 40005000 .word 0x40005000
- 8004a44: 40011400 .word 0x40011400
- 8004a48: 40007800 .word 0x40007800
- 8004a4c: 40007c00 .word 0x40007c00
- 8004a50: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004a54: d006 beq.n 8004a64 <UART_SetConfig+0x330>
- 8004a56: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 8004a5a: d009 beq.n 8004a70 <UART_SetConfig+0x33c>
- 8004a5c: e00b b.n 8004a76 <UART_SetConfig+0x342>
- 8004a5e: 2300 movs r3, #0
+ 80049a8: e14b b.n 8004c42 <UART_SetConfig+0x34e>
+ 80049aa: 2308 movs r3, #8
+ 80049ac: 77fb strb r3, [r7, #31]
+ 80049ae: e148 b.n 8004c42 <UART_SetConfig+0x34e>
+ 80049b0: 2310 movs r3, #16
+ 80049b2: 77fb strb r3, [r7, #31]
+ 80049b4: bf00 nop
+ 80049b6: e144 b.n 8004c42 <UART_SetConfig+0x34e>
+ 80049b8: 687b ldr r3, [r7, #4]
+ 80049ba: 681b ldr r3, [r3, #0]
+ 80049bc: 4a8d ldr r2, [pc, #564] ; (8004bf4 <UART_SetConfig+0x300>)
+ 80049be: 4293 cmp r3, r2
+ 80049c0: d134 bne.n 8004a2c <UART_SetConfig+0x138>
+ 80049c2: 4b8b ldr r3, [pc, #556] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 80049c4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 80049c8: f003 030c and.w r3, r3, #12
+ 80049cc: 2b0c cmp r3, #12
+ 80049ce: d829 bhi.n 8004a24 <UART_SetConfig+0x130>
+ 80049d0: a201 add r2, pc, #4 ; (adr r2, 80049d8 <UART_SetConfig+0xe4>)
+ 80049d2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80049d6: bf00 nop
+ 80049d8: 08004a0d .word 0x08004a0d
+ 80049dc: 08004a25 .word 0x08004a25
+ 80049e0: 08004a25 .word 0x08004a25
+ 80049e4: 08004a25 .word 0x08004a25
+ 80049e8: 08004a19 .word 0x08004a19
+ 80049ec: 08004a25 .word 0x08004a25
+ 80049f0: 08004a25 .word 0x08004a25
+ 80049f4: 08004a25 .word 0x08004a25
+ 80049f8: 08004a13 .word 0x08004a13
+ 80049fc: 08004a25 .word 0x08004a25
+ 8004a00: 08004a25 .word 0x08004a25
+ 8004a04: 08004a25 .word 0x08004a25
+ 8004a08: 08004a1f .word 0x08004a1f
+ 8004a0c: 2300 movs r3, #0
+ 8004a0e: 77fb strb r3, [r7, #31]
+ 8004a10: e117 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a12: 2302 movs r3, #2
+ 8004a14: 77fb strb r3, [r7, #31]
+ 8004a16: e114 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a18: 2304 movs r3, #4
+ 8004a1a: 77fb strb r3, [r7, #31]
+ 8004a1c: e111 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a1e: 2308 movs r3, #8
+ 8004a20: 77fb strb r3, [r7, #31]
+ 8004a22: e10e b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a24: 2310 movs r3, #16
+ 8004a26: 77fb strb r3, [r7, #31]
+ 8004a28: bf00 nop
+ 8004a2a: e10a b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a2c: 687b ldr r3, [r7, #4]
+ 8004a2e: 681b ldr r3, [r3, #0]
+ 8004a30: 4a71 ldr r2, [pc, #452] ; (8004bf8 <UART_SetConfig+0x304>)
+ 8004a32: 4293 cmp r3, r2
+ 8004a34: d120 bne.n 8004a78 <UART_SetConfig+0x184>
+ 8004a36: 4b6e ldr r3, [pc, #440] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 8004a38: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8004a3c: f003 0330 and.w r3, r3, #48 ; 0x30
+ 8004a40: 2b10 cmp r3, #16
+ 8004a42: d00f beq.n 8004a64 <UART_SetConfig+0x170>
+ 8004a44: 2b10 cmp r3, #16
+ 8004a46: d802 bhi.n 8004a4e <UART_SetConfig+0x15a>
+ 8004a48: 2b00 cmp r3, #0
+ 8004a4a: d005 beq.n 8004a58 <UART_SetConfig+0x164>
+ 8004a4c: e010 b.n 8004a70 <UART_SetConfig+0x17c>
+ 8004a4e: 2b20 cmp r3, #32
+ 8004a50: d005 beq.n 8004a5e <UART_SetConfig+0x16a>
+ 8004a52: 2b30 cmp r3, #48 ; 0x30
+ 8004a54: d009 beq.n 8004a6a <UART_SetConfig+0x176>
+ 8004a56: e00b b.n 8004a70 <UART_SetConfig+0x17c>
+ 8004a58: 2300 movs r3, #0
+ 8004a5a: 77fb strb r3, [r7, #31]
+ 8004a5c: e0f1 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a5e: 2302 movs r3, #2
8004a60: 77fb strb r3, [r7, #31]
- 8004a62: e00e b.n 8004a82 <UART_SetConfig+0x34e>
- 8004a64: 2302 movs r3, #2
+ 8004a62: e0ee b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a64: 2304 movs r3, #4
8004a66: 77fb strb r3, [r7, #31]
- 8004a68: e00b b.n 8004a82 <UART_SetConfig+0x34e>
- 8004a6a: 2304 movs r3, #4
+ 8004a68: e0eb b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a6a: 2308 movs r3, #8
8004a6c: 77fb strb r3, [r7, #31]
- 8004a6e: e008 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004a70: 2308 movs r3, #8
+ 8004a6e: e0e8 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a70: 2310 movs r3, #16
8004a72: 77fb strb r3, [r7, #31]
- 8004a74: e005 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004a76: 2310 movs r3, #16
- 8004a78: 77fb strb r3, [r7, #31]
- 8004a7a: bf00 nop
- 8004a7c: e001 b.n 8004a82 <UART_SetConfig+0x34e>
- 8004a7e: 2310 movs r3, #16
- 8004a80: 77fb strb r3, [r7, #31]
+ 8004a74: bf00 nop
+ 8004a76: e0e4 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004a78: 687b ldr r3, [r7, #4]
+ 8004a7a: 681b ldr r3, [r3, #0]
+ 8004a7c: 4a5f ldr r2, [pc, #380] ; (8004bfc <UART_SetConfig+0x308>)
+ 8004a7e: 4293 cmp r3, r2
+ 8004a80: d120 bne.n 8004ac4 <UART_SetConfig+0x1d0>
+ 8004a82: 4b5b ldr r3, [pc, #364] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 8004a84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8004a88: f003 03c0 and.w r3, r3, #192 ; 0xc0
+ 8004a8c: 2b40 cmp r3, #64 ; 0x40
+ 8004a8e: d00f beq.n 8004ab0 <UART_SetConfig+0x1bc>
+ 8004a90: 2b40 cmp r3, #64 ; 0x40
+ 8004a92: d802 bhi.n 8004a9a <UART_SetConfig+0x1a6>
+ 8004a94: 2b00 cmp r3, #0
+ 8004a96: d005 beq.n 8004aa4 <UART_SetConfig+0x1b0>
+ 8004a98: e010 b.n 8004abc <UART_SetConfig+0x1c8>
+ 8004a9a: 2b80 cmp r3, #128 ; 0x80
+ 8004a9c: d005 beq.n 8004aaa <UART_SetConfig+0x1b6>
+ 8004a9e: 2bc0 cmp r3, #192 ; 0xc0
+ 8004aa0: d009 beq.n 8004ab6 <UART_SetConfig+0x1c2>
+ 8004aa2: e00b b.n 8004abc <UART_SetConfig+0x1c8>
+ 8004aa4: 2300 movs r3, #0
+ 8004aa6: 77fb strb r3, [r7, #31]
+ 8004aa8: e0cb b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004aaa: 2302 movs r3, #2
+ 8004aac: 77fb strb r3, [r7, #31]
+ 8004aae: e0c8 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004ab0: 2304 movs r3, #4
+ 8004ab2: 77fb strb r3, [r7, #31]
+ 8004ab4: e0c5 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004ab6: 2308 movs r3, #8
+ 8004ab8: 77fb strb r3, [r7, #31]
+ 8004aba: e0c2 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004abc: 2310 movs r3, #16
+ 8004abe: 77fb strb r3, [r7, #31]
+ 8004ac0: bf00 nop
+ 8004ac2: e0be b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004ac4: 687b ldr r3, [r7, #4]
+ 8004ac6: 681b ldr r3, [r3, #0]
+ 8004ac8: 4a4d ldr r2, [pc, #308] ; (8004c00 <UART_SetConfig+0x30c>)
+ 8004aca: 4293 cmp r3, r2
+ 8004acc: d124 bne.n 8004b18 <UART_SetConfig+0x224>
+ 8004ace: 4b48 ldr r3, [pc, #288] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 8004ad0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8004ad4: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8004ad8: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 8004adc: d012 beq.n 8004b04 <UART_SetConfig+0x210>
+ 8004ade: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 8004ae2: d802 bhi.n 8004aea <UART_SetConfig+0x1f6>
+ 8004ae4: 2b00 cmp r3, #0
+ 8004ae6: d007 beq.n 8004af8 <UART_SetConfig+0x204>
+ 8004ae8: e012 b.n 8004b10 <UART_SetConfig+0x21c>
+ 8004aea: f5b3 7f00 cmp.w r3, #512 ; 0x200
+ 8004aee: d006 beq.n 8004afe <UART_SetConfig+0x20a>
+ 8004af0: f5b3 7f40 cmp.w r3, #768 ; 0x300
+ 8004af4: d009 beq.n 8004b0a <UART_SetConfig+0x216>
+ 8004af6: e00b b.n 8004b10 <UART_SetConfig+0x21c>
+ 8004af8: 2300 movs r3, #0
+ 8004afa: 77fb strb r3, [r7, #31]
+ 8004afc: e0a1 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004afe: 2302 movs r3, #2
+ 8004b00: 77fb strb r3, [r7, #31]
+ 8004b02: e09e b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b04: 2304 movs r3, #4
+ 8004b06: 77fb strb r3, [r7, #31]
+ 8004b08: e09b b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b0a: 2308 movs r3, #8
+ 8004b0c: 77fb strb r3, [r7, #31]
+ 8004b0e: e098 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b10: 2310 movs r3, #16
+ 8004b12: 77fb strb r3, [r7, #31]
+ 8004b14: bf00 nop
+ 8004b16: e094 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b18: 687b ldr r3, [r7, #4]
+ 8004b1a: 681b ldr r3, [r3, #0]
+ 8004b1c: 4a39 ldr r2, [pc, #228] ; (8004c04 <UART_SetConfig+0x310>)
+ 8004b1e: 4293 cmp r3, r2
+ 8004b20: d124 bne.n 8004b6c <UART_SetConfig+0x278>
+ 8004b22: 4b33 ldr r3, [pc, #204] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 8004b24: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8004b28: f403 6340 and.w r3, r3, #3072 ; 0xc00
+ 8004b2c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
+ 8004b30: d012 beq.n 8004b58 <UART_SetConfig+0x264>
+ 8004b32: f5b3 6f80 cmp.w r3, #1024 ; 0x400
+ 8004b36: d802 bhi.n 8004b3e <UART_SetConfig+0x24a>
+ 8004b38: 2b00 cmp r3, #0
+ 8004b3a: d007 beq.n 8004b4c <UART_SetConfig+0x258>
+ 8004b3c: e012 b.n 8004b64 <UART_SetConfig+0x270>
+ 8004b3e: f5b3 6f00 cmp.w r3, #2048 ; 0x800
+ 8004b42: d006 beq.n 8004b52 <UART_SetConfig+0x25e>
+ 8004b44: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
+ 8004b48: d009 beq.n 8004b5e <UART_SetConfig+0x26a>
+ 8004b4a: e00b b.n 8004b64 <UART_SetConfig+0x270>
+ 8004b4c: 2301 movs r3, #1
+ 8004b4e: 77fb strb r3, [r7, #31]
+ 8004b50: e077 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b52: 2302 movs r3, #2
+ 8004b54: 77fb strb r3, [r7, #31]
+ 8004b56: e074 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b58: 2304 movs r3, #4
+ 8004b5a: 77fb strb r3, [r7, #31]
+ 8004b5c: e071 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b5e: 2308 movs r3, #8
+ 8004b60: 77fb strb r3, [r7, #31]
+ 8004b62: e06e b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b64: 2310 movs r3, #16
+ 8004b66: 77fb strb r3, [r7, #31]
+ 8004b68: bf00 nop
+ 8004b6a: e06a b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004b6c: 687b ldr r3, [r7, #4]
+ 8004b6e: 681b ldr r3, [r3, #0]
+ 8004b70: 4a25 ldr r2, [pc, #148] ; (8004c08 <UART_SetConfig+0x314>)
+ 8004b72: 4293 cmp r3, r2
+ 8004b74: d124 bne.n 8004bc0 <UART_SetConfig+0x2cc>
+ 8004b76: 4b1e ldr r3, [pc, #120] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 8004b78: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8004b7c: f403 5340 and.w r3, r3, #12288 ; 0x3000
+ 8004b80: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8004b84: d012 beq.n 8004bac <UART_SetConfig+0x2b8>
+ 8004b86: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8004b8a: d802 bhi.n 8004b92 <UART_SetConfig+0x29e>
+ 8004b8c: 2b00 cmp r3, #0
+ 8004b8e: d007 beq.n 8004ba0 <UART_SetConfig+0x2ac>
+ 8004b90: e012 b.n 8004bb8 <UART_SetConfig+0x2c4>
+ 8004b92: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
+ 8004b96: d006 beq.n 8004ba6 <UART_SetConfig+0x2b2>
+ 8004b98: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
+ 8004b9c: d009 beq.n 8004bb2 <UART_SetConfig+0x2be>
+ 8004b9e: e00b b.n 8004bb8 <UART_SetConfig+0x2c4>
+ 8004ba0: 2300 movs r3, #0
+ 8004ba2: 77fb strb r3, [r7, #31]
+ 8004ba4: e04d b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004ba6: 2302 movs r3, #2
+ 8004ba8: 77fb strb r3, [r7, #31]
+ 8004baa: e04a b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004bac: 2304 movs r3, #4
+ 8004bae: 77fb strb r3, [r7, #31]
+ 8004bb0: e047 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004bb2: 2308 movs r3, #8
+ 8004bb4: 77fb strb r3, [r7, #31]
+ 8004bb6: e044 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004bb8: 2310 movs r3, #16
+ 8004bba: 77fb strb r3, [r7, #31]
+ 8004bbc: bf00 nop
+ 8004bbe: e040 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004bc0: 687b ldr r3, [r7, #4]
+ 8004bc2: 681b ldr r3, [r3, #0]
+ 8004bc4: 4a11 ldr r2, [pc, #68] ; (8004c0c <UART_SetConfig+0x318>)
+ 8004bc6: 4293 cmp r3, r2
+ 8004bc8: d139 bne.n 8004c3e <UART_SetConfig+0x34a>
+ 8004bca: 4b09 ldr r3, [pc, #36] ; (8004bf0 <UART_SetConfig+0x2fc>)
+ 8004bcc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8004bd0: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 8004bd4: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
+ 8004bd8: d027 beq.n 8004c2a <UART_SetConfig+0x336>
+ 8004bda: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
+ 8004bde: d817 bhi.n 8004c10 <UART_SetConfig+0x31c>
+ 8004be0: 2b00 cmp r3, #0
+ 8004be2: d01c beq.n 8004c1e <UART_SetConfig+0x32a>
+ 8004be4: e027 b.n 8004c36 <UART_SetConfig+0x342>
+ 8004be6: bf00 nop
+ 8004be8: efff69f3 .word 0xefff69f3
+ 8004bec: 40011000 .word 0x40011000
+ 8004bf0: 40023800 .word 0x40023800
+ 8004bf4: 40004400 .word 0x40004400
+ 8004bf8: 40004800 .word 0x40004800
+ 8004bfc: 40004c00 .word 0x40004c00
+ 8004c00: 40005000 .word 0x40005000
+ 8004c04: 40011400 .word 0x40011400
+ 8004c08: 40007800 .word 0x40007800
+ 8004c0c: 40007c00 .word 0x40007c00
+ 8004c10: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
+ 8004c14: d006 beq.n 8004c24 <UART_SetConfig+0x330>
+ 8004c16: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
+ 8004c1a: d009 beq.n 8004c30 <UART_SetConfig+0x33c>
+ 8004c1c: e00b b.n 8004c36 <UART_SetConfig+0x342>
+ 8004c1e: 2300 movs r3, #0
+ 8004c20: 77fb strb r3, [r7, #31]
+ 8004c22: e00e b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004c24: 2302 movs r3, #2
+ 8004c26: 77fb strb r3, [r7, #31]
+ 8004c28: e00b b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004c2a: 2304 movs r3, #4
+ 8004c2c: 77fb strb r3, [r7, #31]
+ 8004c2e: e008 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004c30: 2308 movs r3, #8
+ 8004c32: 77fb strb r3, [r7, #31]
+ 8004c34: e005 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004c36: 2310 movs r3, #16
+ 8004c38: 77fb strb r3, [r7, #31]
+ 8004c3a: bf00 nop
+ 8004c3c: e001 b.n 8004c42 <UART_SetConfig+0x34e>
+ 8004c3e: 2310 movs r3, #16
+ 8004c40: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8004a82: 687b ldr r3, [r7, #4]
- 8004a84: 69db ldr r3, [r3, #28]
- 8004a86: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8004a8a: d17c bne.n 8004b86 <UART_SetConfig+0x452>
+ 8004c42: 687b ldr r3, [r7, #4]
+ 8004c44: 69db ldr r3, [r3, #28]
+ 8004c46: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
+ 8004c4a: d17c bne.n 8004d46 <UART_SetConfig+0x452>
{
switch (clocksource)
- 8004a8c: 7ffb ldrb r3, [r7, #31]
- 8004a8e: 2b08 cmp r3, #8
- 8004a90: d859 bhi.n 8004b46 <UART_SetConfig+0x412>
- 8004a92: a201 add r2, pc, #4 ; (adr r2, 8004a98 <UART_SetConfig+0x364>)
- 8004a94: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004a98: 08004abd .word 0x08004abd
- 8004a9c: 08004adb .word 0x08004adb
- 8004aa0: 08004af9 .word 0x08004af9
- 8004aa4: 08004b47 .word 0x08004b47
- 8004aa8: 08004b11 .word 0x08004b11
- 8004aac: 08004b47 .word 0x08004b47
- 8004ab0: 08004b47 .word 0x08004b47
- 8004ab4: 08004b47 .word 0x08004b47
- 8004ab8: 08004b2f .word 0x08004b2f
+ 8004c4c: 7ffb ldrb r3, [r7, #31]
+ 8004c4e: 2b08 cmp r3, #8
+ 8004c50: d859 bhi.n 8004d06 <UART_SetConfig+0x412>
+ 8004c52: a201 add r2, pc, #4 ; (adr r2, 8004c58 <UART_SetConfig+0x364>)
+ 8004c54: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 8004c58: 08004c7d .word 0x08004c7d
+ 8004c5c: 08004c9b .word 0x08004c9b
+ 8004c60: 08004cb9 .word 0x08004cb9
+ 8004c64: 08004d07 .word 0x08004d07
+ 8004c68: 08004cd1 .word 0x08004cd1
+ 8004c6c: 08004d07 .word 0x08004d07
+ 8004c70: 08004d07 .word 0x08004d07
+ 8004c74: 08004d07 .word 0x08004d07
+ 8004c78: 08004cef .word 0x08004cef
{
case UART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004abc: f7fd fef2 bl 80028a4 <HAL_RCC_GetPCLK1Freq>
- 8004ac0: 4603 mov r3, r0
- 8004ac2: 005a lsls r2, r3, #1
- 8004ac4: 687b ldr r3, [r7, #4]
- 8004ac6: 685b ldr r3, [r3, #4]
- 8004ac8: 085b lsrs r3, r3, #1
- 8004aca: 441a add r2, r3
- 8004acc: 687b ldr r3, [r7, #4]
- 8004ace: 685b ldr r3, [r3, #4]
- 8004ad0: fbb2 f3f3 udiv r3, r2, r3
- 8004ad4: b29b uxth r3, r3
- 8004ad6: 61bb str r3, [r7, #24]
+ 8004c7c: f7fd fe50 bl 8002920 <HAL_RCC_GetPCLK1Freq>
+ 8004c80: 4603 mov r3, r0
+ 8004c82: 005a lsls r2, r3, #1
+ 8004c84: 687b ldr r3, [r7, #4]
+ 8004c86: 685b ldr r3, [r3, #4]
+ 8004c88: 085b lsrs r3, r3, #1
+ 8004c8a: 441a add r2, r3
+ 8004c8c: 687b ldr r3, [r7, #4]
+ 8004c8e: 685b ldr r3, [r3, #4]
+ 8004c90: fbb2 f3f3 udiv r3, r2, r3
+ 8004c94: b29b uxth r3, r3
+ 8004c96: 61bb str r3, [r7, #24]
break;
- 8004ad8: e038 b.n 8004b4c <UART_SetConfig+0x418>
+ 8004c98: e038 b.n 8004d0c <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004ada: f7fd fef7 bl 80028cc <HAL_RCC_GetPCLK2Freq>
- 8004ade: 4603 mov r3, r0
- 8004ae0: 005a lsls r2, r3, #1
- 8004ae2: 687b ldr r3, [r7, #4]
- 8004ae4: 685b ldr r3, [r3, #4]
- 8004ae6: 085b lsrs r3, r3, #1
- 8004ae8: 441a add r2, r3
- 8004aea: 687b ldr r3, [r7, #4]
- 8004aec: 685b ldr r3, [r3, #4]
- 8004aee: fbb2 f3f3 udiv r3, r2, r3
- 8004af2: b29b uxth r3, r3
- 8004af4: 61bb str r3, [r7, #24]
+ 8004c9a: f7fd fe55 bl 8002948 <HAL_RCC_GetPCLK2Freq>
+ 8004c9e: 4603 mov r3, r0
+ 8004ca0: 005a lsls r2, r3, #1
+ 8004ca2: 687b ldr r3, [r7, #4]
+ 8004ca4: 685b ldr r3, [r3, #4]
+ 8004ca6: 085b lsrs r3, r3, #1
+ 8004ca8: 441a add r2, r3
+ 8004caa: 687b ldr r3, [r7, #4]
+ 8004cac: 685b ldr r3, [r3, #4]
+ 8004cae: fbb2 f3f3 udiv r3, r2, r3
+ 8004cb2: b29b uxth r3, r3
+ 8004cb4: 61bb str r3, [r7, #24]
break;
- 8004af6: e029 b.n 8004b4c <UART_SetConfig+0x418>
+ 8004cb6: e029 b.n 8004d0c <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8004af8: 687b ldr r3, [r7, #4]
- 8004afa: 685b ldr r3, [r3, #4]
- 8004afc: 085a lsrs r2, r3, #1
- 8004afe: 4b5d ldr r3, [pc, #372] ; (8004c74 <UART_SetConfig+0x540>)
- 8004b00: 4413 add r3, r2
- 8004b02: 687a ldr r2, [r7, #4]
- 8004b04: 6852 ldr r2, [r2, #4]
- 8004b06: fbb3 f3f2 udiv r3, r3, r2
- 8004b0a: b29b uxth r3, r3
- 8004b0c: 61bb str r3, [r7, #24]
+ 8004cb8: 687b ldr r3, [r7, #4]
+ 8004cba: 685b ldr r3, [r3, #4]
+ 8004cbc: 085a lsrs r2, r3, #1
+ 8004cbe: 4b5d ldr r3, [pc, #372] ; (8004e34 <UART_SetConfig+0x540>)
+ 8004cc0: 4413 add r3, r2
+ 8004cc2: 687a ldr r2, [r7, #4]
+ 8004cc4: 6852 ldr r2, [r2, #4]
+ 8004cc6: fbb3 f3f2 udiv r3, r3, r2
+ 8004cca: b29b uxth r3, r3
+ 8004ccc: 61bb str r3, [r7, #24]
break;
- 8004b0e: e01d b.n 8004b4c <UART_SetConfig+0x418>
+ 8004cce: e01d b.n 8004d0c <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8004b10: f7fd fe0a bl 8002728 <HAL_RCC_GetSysClockFreq>
- 8004b14: 4603 mov r3, r0
- 8004b16: 005a lsls r2, r3, #1
- 8004b18: 687b ldr r3, [r7, #4]
- 8004b1a: 685b ldr r3, [r3, #4]
- 8004b1c: 085b lsrs r3, r3, #1
- 8004b1e: 441a add r2, r3
- 8004b20: 687b ldr r3, [r7, #4]
- 8004b22: 685b ldr r3, [r3, #4]
- 8004b24: fbb2 f3f3 udiv r3, r2, r3
- 8004b28: b29b uxth r3, r3
- 8004b2a: 61bb str r3, [r7, #24]
+ 8004cd0: f7fd fd68 bl 80027a4 <HAL_RCC_GetSysClockFreq>
+ 8004cd4: 4603 mov r3, r0
+ 8004cd6: 005a lsls r2, r3, #1
+ 8004cd8: 687b ldr r3, [r7, #4]
+ 8004cda: 685b ldr r3, [r3, #4]
+ 8004cdc: 085b lsrs r3, r3, #1
+ 8004cde: 441a add r2, r3
+ 8004ce0: 687b ldr r3, [r7, #4]
+ 8004ce2: 685b ldr r3, [r3, #4]
+ 8004ce4: fbb2 f3f3 udiv r3, r2, r3
+ 8004ce8: b29b uxth r3, r3
+ 8004cea: 61bb str r3, [r7, #24]
break;
- 8004b2c: e00e b.n 8004b4c <UART_SetConfig+0x418>
+ 8004cec: e00e b.n 8004d0c <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 8004b2e: 687b ldr r3, [r7, #4]
- 8004b30: 685b ldr r3, [r3, #4]
- 8004b32: 085b lsrs r3, r3, #1
- 8004b34: f503 3280 add.w r2, r3, #65536 ; 0x10000
- 8004b38: 687b ldr r3, [r7, #4]
- 8004b3a: 685b ldr r3, [r3, #4]
- 8004b3c: fbb2 f3f3 udiv r3, r2, r3
- 8004b40: b29b uxth r3, r3
- 8004b42: 61bb str r3, [r7, #24]
+ 8004cee: 687b ldr r3, [r7, #4]
+ 8004cf0: 685b ldr r3, [r3, #4]
+ 8004cf2: 085b lsrs r3, r3, #1
+ 8004cf4: f503 3280 add.w r2, r3, #65536 ; 0x10000
+ 8004cf8: 687b ldr r3, [r7, #4]
+ 8004cfa: 685b ldr r3, [r3, #4]
+ 8004cfc: fbb2 f3f3 udiv r3, r2, r3
+ 8004d00: b29b uxth r3, r3
+ 8004d02: 61bb str r3, [r7, #24]
break;
- 8004b44: e002 b.n 8004b4c <UART_SetConfig+0x418>
+ 8004d04: e002 b.n 8004d0c <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
- 8004b46: 2301 movs r3, #1
- 8004b48: 75fb strb r3, [r7, #23]
+ 8004d06: 2301 movs r3, #1
+ 8004d08: 75fb strb r3, [r7, #23]
break;
- 8004b4a: bf00 nop
+ 8004d0a: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8004b4c: 69bb ldr r3, [r7, #24]
- 8004b4e: 2b0f cmp r3, #15
- 8004b50: d916 bls.n 8004b80 <UART_SetConfig+0x44c>
- 8004b52: 69bb ldr r3, [r7, #24]
- 8004b54: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8004b58: d212 bcs.n 8004b80 <UART_SetConfig+0x44c>
+ 8004d0c: 69bb ldr r3, [r7, #24]
+ 8004d0e: 2b0f cmp r3, #15
+ 8004d10: d916 bls.n 8004d40 <UART_SetConfig+0x44c>
+ 8004d12: 69bb ldr r3, [r7, #24]
+ 8004d14: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8004d18: d212 bcs.n 8004d40 <UART_SetConfig+0x44c>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 8004b5a: 69bb ldr r3, [r7, #24]
- 8004b5c: b29b uxth r3, r3
- 8004b5e: f023 030f bic.w r3, r3, #15
- 8004b62: 81fb strh r3, [r7, #14]
+ 8004d1a: 69bb ldr r3, [r7, #24]
+ 8004d1c: b29b uxth r3, r3
+ 8004d1e: f023 030f bic.w r3, r3, #15
+ 8004d22: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8004b64: 69bb ldr r3, [r7, #24]
- 8004b66: 085b lsrs r3, r3, #1
- 8004b68: b29b uxth r3, r3
- 8004b6a: f003 0307 and.w r3, r3, #7
- 8004b6e: b29a uxth r2, r3
- 8004b70: 89fb ldrh r3, [r7, #14]
- 8004b72: 4313 orrs r3, r2
- 8004b74: 81fb strh r3, [r7, #14]
+ 8004d24: 69bb ldr r3, [r7, #24]
+ 8004d26: 085b lsrs r3, r3, #1
+ 8004d28: b29b uxth r3, r3
+ 8004d2a: f003 0307 and.w r3, r3, #7
+ 8004d2e: b29a uxth r2, r3
+ 8004d30: 89fb ldrh r3, [r7, #14]
+ 8004d32: 4313 orrs r3, r2
+ 8004d34: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
- 8004b76: 687b ldr r3, [r7, #4]
- 8004b78: 681b ldr r3, [r3, #0]
- 8004b7a: 89fa ldrh r2, [r7, #14]
- 8004b7c: 60da str r2, [r3, #12]
- 8004b7e: e06e b.n 8004c5e <UART_SetConfig+0x52a>
+ 8004d36: 687b ldr r3, [r7, #4]
+ 8004d38: 681b ldr r3, [r3, #0]
+ 8004d3a: 89fa ldrh r2, [r7, #14]
+ 8004d3c: 60da str r2, [r3, #12]
+ 8004d3e: e06e b.n 8004e1e <UART_SetConfig+0x52a>
}
else
{
ret = HAL_ERROR;
- 8004b80: 2301 movs r3, #1
- 8004b82: 75fb strb r3, [r7, #23]
- 8004b84: e06b b.n 8004c5e <UART_SetConfig+0x52a>
+ 8004d40: 2301 movs r3, #1
+ 8004d42: 75fb strb r3, [r7, #23]
+ 8004d44: e06b b.n 8004e1e <UART_SetConfig+0x52a>
}
}
else
{
switch (clocksource)
- 8004b86: 7ffb ldrb r3, [r7, #31]
- 8004b88: 2b08 cmp r3, #8
- 8004b8a: d857 bhi.n 8004c3c <UART_SetConfig+0x508>
- 8004b8c: a201 add r2, pc, #4 ; (adr r2, 8004b94 <UART_SetConfig+0x460>)
- 8004b8e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8004b92: bf00 nop
- 8004b94: 08004bb9 .word 0x08004bb9
- 8004b98: 08004bd5 .word 0x08004bd5
- 8004b9c: 08004bf1 .word 0x08004bf1
- 8004ba0: 08004c3d .word 0x08004c3d
- 8004ba4: 08004c09 .word 0x08004c09
- 8004ba8: 08004c3d .word 0x08004c3d
- 8004bac: 08004c3d .word 0x08004c3d
- 8004bb0: 08004c3d .word 0x08004c3d
- 8004bb4: 08004c25 .word 0x08004c25
+ 8004d46: 7ffb ldrb r3, [r7, #31]
+ 8004d48: 2b08 cmp r3, #8
+ 8004d4a: d857 bhi.n 8004dfc <UART_SetConfig+0x508>
+ 8004d4c: a201 add r2, pc, #4 ; (adr r2, 8004d54 <UART_SetConfig+0x460>)
+ 8004d4e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 8004d52: bf00 nop
+ 8004d54: 08004d79 .word 0x08004d79
+ 8004d58: 08004d95 .word 0x08004d95
+ 8004d5c: 08004db1 .word 0x08004db1
+ 8004d60: 08004dfd .word 0x08004dfd
+ 8004d64: 08004dc9 .word 0x08004dc9
+ 8004d68: 08004dfd .word 0x08004dfd
+ 8004d6c: 08004dfd .word 0x08004dfd
+ 8004d70: 08004dfd .word 0x08004dfd
+ 8004d74: 08004de5 .word 0x08004de5
{
case UART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8004bb8: f7fd fe74 bl 80028a4 <HAL_RCC_GetPCLK1Freq>
- 8004bbc: 4602 mov r2, r0
- 8004bbe: 687b ldr r3, [r7, #4]
- 8004bc0: 685b ldr r3, [r3, #4]
- 8004bc2: 085b lsrs r3, r3, #1
- 8004bc4: 441a add r2, r3
- 8004bc6: 687b ldr r3, [r7, #4]
- 8004bc8: 685b ldr r3, [r3, #4]
- 8004bca: fbb2 f3f3 udiv r3, r2, r3
- 8004bce: b29b uxth r3, r3
- 8004bd0: 61bb str r3, [r7, #24]
+ 8004d78: f7fd fdd2 bl 8002920 <HAL_RCC_GetPCLK1Freq>
+ 8004d7c: 4602 mov r2, r0
+ 8004d7e: 687b ldr r3, [r7, #4]
+ 8004d80: 685b ldr r3, [r3, #4]
+ 8004d82: 085b lsrs r3, r3, #1
+ 8004d84: 441a add r2, r3
+ 8004d86: 687b ldr r3, [r7, #4]
+ 8004d88: 685b ldr r3, [r3, #4]
+ 8004d8a: fbb2 f3f3 udiv r3, r2, r3
+ 8004d8e: b29b uxth r3, r3
+ 8004d90: 61bb str r3, [r7, #24]
break;
- 8004bd2: e036 b.n 8004c42 <UART_SetConfig+0x50e>
+ 8004d92: e036 b.n 8004e02 <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8004bd4: f7fd fe7a bl 80028cc <HAL_RCC_GetPCLK2Freq>
- 8004bd8: 4602 mov r2, r0
- 8004bda: 687b ldr r3, [r7, #4]
- 8004bdc: 685b ldr r3, [r3, #4]
- 8004bde: 085b lsrs r3, r3, #1
- 8004be0: 441a add r2, r3
- 8004be2: 687b ldr r3, [r7, #4]
- 8004be4: 685b ldr r3, [r3, #4]
- 8004be6: fbb2 f3f3 udiv r3, r2, r3
- 8004bea: b29b uxth r3, r3
- 8004bec: 61bb str r3, [r7, #24]
+ 8004d94: f7fd fdd8 bl 8002948 <HAL_RCC_GetPCLK2Freq>
+ 8004d98: 4602 mov r2, r0
+ 8004d9a: 687b ldr r3, [r7, #4]
+ 8004d9c: 685b ldr r3, [r3, #4]
+ 8004d9e: 085b lsrs r3, r3, #1
+ 8004da0: 441a add r2, r3
+ 8004da2: 687b ldr r3, [r7, #4]
+ 8004da4: 685b ldr r3, [r3, #4]
+ 8004da6: fbb2 f3f3 udiv r3, r2, r3
+ 8004daa: b29b uxth r3, r3
+ 8004dac: 61bb str r3, [r7, #24]
break;
- 8004bee: e028 b.n 8004c42 <UART_SetConfig+0x50e>
+ 8004dae: e028 b.n 8004e02 <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 8004bf0: 687b ldr r3, [r7, #4]
- 8004bf2: 685b ldr r3, [r3, #4]
- 8004bf4: 085a lsrs r2, r3, #1
- 8004bf6: 4b20 ldr r3, [pc, #128] ; (8004c78 <UART_SetConfig+0x544>)
- 8004bf8: 4413 add r3, r2
- 8004bfa: 687a ldr r2, [r7, #4]
- 8004bfc: 6852 ldr r2, [r2, #4]
- 8004bfe: fbb3 f3f2 udiv r3, r3, r2
- 8004c02: b29b uxth r3, r3
- 8004c04: 61bb str r3, [r7, #24]
+ 8004db0: 687b ldr r3, [r7, #4]
+ 8004db2: 685b ldr r3, [r3, #4]
+ 8004db4: 085a lsrs r2, r3, #1
+ 8004db6: 4b20 ldr r3, [pc, #128] ; (8004e38 <UART_SetConfig+0x544>)
+ 8004db8: 4413 add r3, r2
+ 8004dba: 687a ldr r2, [r7, #4]
+ 8004dbc: 6852 ldr r2, [r2, #4]
+ 8004dbe: fbb3 f3f2 udiv r3, r3, r2
+ 8004dc2: b29b uxth r3, r3
+ 8004dc4: 61bb str r3, [r7, #24]
break;
- 8004c06: e01c b.n 8004c42 <UART_SetConfig+0x50e>
+ 8004dc6: e01c b.n 8004e02 <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8004c08: f7fd fd8e bl 8002728 <HAL_RCC_GetSysClockFreq>
- 8004c0c: 4602 mov r2, r0
- 8004c0e: 687b ldr r3, [r7, #4]
- 8004c10: 685b ldr r3, [r3, #4]
- 8004c12: 085b lsrs r3, r3, #1
- 8004c14: 441a add r2, r3
- 8004c16: 687b ldr r3, [r7, #4]
- 8004c18: 685b ldr r3, [r3, #4]
- 8004c1a: fbb2 f3f3 udiv r3, r2, r3
- 8004c1e: b29b uxth r3, r3
- 8004c20: 61bb str r3, [r7, #24]
+ 8004dc8: f7fd fcec bl 80027a4 <HAL_RCC_GetSysClockFreq>
+ 8004dcc: 4602 mov r2, r0
+ 8004dce: 687b ldr r3, [r7, #4]
+ 8004dd0: 685b ldr r3, [r3, #4]
+ 8004dd2: 085b lsrs r3, r3, #1
+ 8004dd4: 441a add r2, r3
+ 8004dd6: 687b ldr r3, [r7, #4]
+ 8004dd8: 685b ldr r3, [r3, #4]
+ 8004dda: fbb2 f3f3 udiv r3, r2, r3
+ 8004dde: b29b uxth r3, r3
+ 8004de0: 61bb str r3, [r7, #24]
break;
- 8004c22: e00e b.n 8004c42 <UART_SetConfig+0x50e>
+ 8004de2: e00e b.n 8004e02 <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 8004c24: 687b ldr r3, [r7, #4]
- 8004c26: 685b ldr r3, [r3, #4]
- 8004c28: 085b lsrs r3, r3, #1
- 8004c2a: f503 4200 add.w r2, r3, #32768 ; 0x8000
- 8004c2e: 687b ldr r3, [r7, #4]
- 8004c30: 685b ldr r3, [r3, #4]
- 8004c32: fbb2 f3f3 udiv r3, r2, r3
- 8004c36: b29b uxth r3, r3
- 8004c38: 61bb str r3, [r7, #24]
+ 8004de4: 687b ldr r3, [r7, #4]
+ 8004de6: 685b ldr r3, [r3, #4]
+ 8004de8: 085b lsrs r3, r3, #1
+ 8004dea: f503 4200 add.w r2, r3, #32768 ; 0x8000
+ 8004dee: 687b ldr r3, [r7, #4]
+ 8004df0: 685b ldr r3, [r3, #4]
+ 8004df2: fbb2 f3f3 udiv r3, r2, r3
+ 8004df6: b29b uxth r3, r3
+ 8004df8: 61bb str r3, [r7, #24]
break;
- 8004c3a: e002 b.n 8004c42 <UART_SetConfig+0x50e>
+ 8004dfa: e002 b.n 8004e02 <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
- 8004c3c: 2301 movs r3, #1
- 8004c3e: 75fb strb r3, [r7, #23]
+ 8004dfc: 2301 movs r3, #1
+ 8004dfe: 75fb strb r3, [r7, #23]
break;
- 8004c40: bf00 nop
+ 8004e00: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8004c42: 69bb ldr r3, [r7, #24]
- 8004c44: 2b0f cmp r3, #15
- 8004c46: d908 bls.n 8004c5a <UART_SetConfig+0x526>
- 8004c48: 69bb ldr r3, [r7, #24]
- 8004c4a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8004c4e: d204 bcs.n 8004c5a <UART_SetConfig+0x526>
+ 8004e02: 69bb ldr r3, [r7, #24]
+ 8004e04: 2b0f cmp r3, #15
+ 8004e06: d908 bls.n 8004e1a <UART_SetConfig+0x526>
+ 8004e08: 69bb ldr r3, [r7, #24]
+ 8004e0a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8004e0e: d204 bcs.n 8004e1a <UART_SetConfig+0x526>
{
huart->Instance->BRR = usartdiv;
- 8004c50: 687b ldr r3, [r7, #4]
- 8004c52: 681b ldr r3, [r3, #0]
- 8004c54: 69ba ldr r2, [r7, #24]
- 8004c56: 60da str r2, [r3, #12]
- 8004c58: e001 b.n 8004c5e <UART_SetConfig+0x52a>
+ 8004e10: 687b ldr r3, [r7, #4]
+ 8004e12: 681b ldr r3, [r3, #0]
+ 8004e14: 69ba ldr r2, [r7, #24]
+ 8004e16: 60da str r2, [r3, #12]
+ 8004e18: e001 b.n 8004e1e <UART_SetConfig+0x52a>
}
else
{
ret = HAL_ERROR;
- 8004c5a: 2301 movs r3, #1
- 8004c5c: 75fb strb r3, [r7, #23]
+ 8004e1a: 2301 movs r3, #1
+ 8004e1c: 75fb strb r3, [r7, #23]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
- 8004c5e: 687b ldr r3, [r7, #4]
- 8004c60: 2200 movs r2, #0
- 8004c62: 661a str r2, [r3, #96] ; 0x60
+ 8004e1e: 687b ldr r3, [r7, #4]
+ 8004e20: 2200 movs r2, #0
+ 8004e22: 661a str r2, [r3, #96] ; 0x60
huart->TxISR = NULL;
- 8004c64: 687b ldr r3, [r7, #4]
- 8004c66: 2200 movs r2, #0
- 8004c68: 665a str r2, [r3, #100] ; 0x64
+ 8004e24: 687b ldr r3, [r7, #4]
+ 8004e26: 2200 movs r2, #0
+ 8004e28: 665a str r2, [r3, #100] ; 0x64
return ret;
- 8004c6a: 7dfb ldrb r3, [r7, #23]
+ 8004e2a: 7dfb ldrb r3, [r7, #23]
}
- 8004c6c: 4618 mov r0, r3
- 8004c6e: 3720 adds r7, #32
- 8004c70: 46bd mov sp, r7
- 8004c72: bd80 pop {r7, pc}
- 8004c74: 01e84800 .word 0x01e84800
- 8004c78: 00f42400 .word 0x00f42400
-
-08004c7c <UART_AdvFeatureConfig>:
+ 8004e2c: 4618 mov r0, r3
+ 8004e2e: 3720 adds r7, #32
+ 8004e30: 46bd mov sp, r7
+ 8004e32: bd80 pop {r7, pc}
+ 8004e34: 01e84800 .word 0x01e84800
+ 8004e38: 00f42400 .word 0x00f42400
+
+08004e3c <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
- 8004c7c: b480 push {r7}
- 8004c7e: b083 sub sp, #12
- 8004c80: af00 add r7, sp, #0
- 8004c82: 6078 str r0, [r7, #4]
+ 8004e3c: b480 push {r7}
+ 8004e3e: b083 sub sp, #12
+ 8004e40: af00 add r7, sp, #0
+ 8004e42: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 8004c84: 687b ldr r3, [r7, #4]
- 8004c86: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004c88: f003 0301 and.w r3, r3, #1
- 8004c8c: 2b00 cmp r3, #0
- 8004c8e: d00a beq.n 8004ca6 <UART_AdvFeatureConfig+0x2a>
+ 8004e44: 687b ldr r3, [r7, #4]
+ 8004e46: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004e48: f003 0301 and.w r3, r3, #1
+ 8004e4c: 2b00 cmp r3, #0
+ 8004e4e: d00a beq.n 8004e66 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8004c90: 687b ldr r3, [r7, #4]
- 8004c92: 681b ldr r3, [r3, #0]
- 8004c94: 685b ldr r3, [r3, #4]
- 8004c96: f423 3100 bic.w r1, r3, #131072 ; 0x20000
- 8004c9a: 687b ldr r3, [r7, #4]
- 8004c9c: 6a9a ldr r2, [r3, #40] ; 0x28
- 8004c9e: 687b ldr r3, [r7, #4]
- 8004ca0: 681b ldr r3, [r3, #0]
- 8004ca2: 430a orrs r2, r1
- 8004ca4: 605a str r2, [r3, #4]
+ 8004e50: 687b ldr r3, [r7, #4]
+ 8004e52: 681b ldr r3, [r3, #0]
+ 8004e54: 685b ldr r3, [r3, #4]
+ 8004e56: f423 3100 bic.w r1, r3, #131072 ; 0x20000
+ 8004e5a: 687b ldr r3, [r7, #4]
+ 8004e5c: 6a9a ldr r2, [r3, #40] ; 0x28
+ 8004e5e: 687b ldr r3, [r7, #4]
+ 8004e60: 681b ldr r3, [r3, #0]
+ 8004e62: 430a orrs r2, r1
+ 8004e64: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 8004ca6: 687b ldr r3, [r7, #4]
- 8004ca8: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004caa: f003 0302 and.w r3, r3, #2
- 8004cae: 2b00 cmp r3, #0
- 8004cb0: d00a beq.n 8004cc8 <UART_AdvFeatureConfig+0x4c>
+ 8004e66: 687b ldr r3, [r7, #4]
+ 8004e68: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004e6a: f003 0302 and.w r3, r3, #2
+ 8004e6e: 2b00 cmp r3, #0
+ 8004e70: d00a beq.n 8004e88 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 8004cb2: 687b ldr r3, [r7, #4]
- 8004cb4: 681b ldr r3, [r3, #0]
- 8004cb6: 685b ldr r3, [r3, #4]
- 8004cb8: f423 3180 bic.w r1, r3, #65536 ; 0x10000
- 8004cbc: 687b ldr r3, [r7, #4]
- 8004cbe: 6ada ldr r2, [r3, #44] ; 0x2c
- 8004cc0: 687b ldr r3, [r7, #4]
- 8004cc2: 681b ldr r3, [r3, #0]
- 8004cc4: 430a orrs r2, r1
- 8004cc6: 605a str r2, [r3, #4]
+ 8004e72: 687b ldr r3, [r7, #4]
+ 8004e74: 681b ldr r3, [r3, #0]
+ 8004e76: 685b ldr r3, [r3, #4]
+ 8004e78: f423 3180 bic.w r1, r3, #65536 ; 0x10000
+ 8004e7c: 687b ldr r3, [r7, #4]
+ 8004e7e: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8004e80: 687b ldr r3, [r7, #4]
+ 8004e82: 681b ldr r3, [r3, #0]
+ 8004e84: 430a orrs r2, r1
+ 8004e86: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 8004cc8: 687b ldr r3, [r7, #4]
- 8004cca: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004ccc: f003 0304 and.w r3, r3, #4
- 8004cd0: 2b00 cmp r3, #0
- 8004cd2: d00a beq.n 8004cea <UART_AdvFeatureConfig+0x6e>
+ 8004e88: 687b ldr r3, [r7, #4]
+ 8004e8a: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004e8c: f003 0304 and.w r3, r3, #4
+ 8004e90: 2b00 cmp r3, #0
+ 8004e92: d00a beq.n 8004eaa <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 8004cd4: 687b ldr r3, [r7, #4]
- 8004cd6: 681b ldr r3, [r3, #0]
- 8004cd8: 685b ldr r3, [r3, #4]
- 8004cda: f423 2180 bic.w r1, r3, #262144 ; 0x40000
- 8004cde: 687b ldr r3, [r7, #4]
- 8004ce0: 6b1a ldr r2, [r3, #48] ; 0x30
- 8004ce2: 687b ldr r3, [r7, #4]
- 8004ce4: 681b ldr r3, [r3, #0]
- 8004ce6: 430a orrs r2, r1
- 8004ce8: 605a str r2, [r3, #4]
+ 8004e94: 687b ldr r3, [r7, #4]
+ 8004e96: 681b ldr r3, [r3, #0]
+ 8004e98: 685b ldr r3, [r3, #4]
+ 8004e9a: f423 2180 bic.w r1, r3, #262144 ; 0x40000
+ 8004e9e: 687b ldr r3, [r7, #4]
+ 8004ea0: 6b1a ldr r2, [r3, #48] ; 0x30
+ 8004ea2: 687b ldr r3, [r7, #4]
+ 8004ea4: 681b ldr r3, [r3, #0]
+ 8004ea6: 430a orrs r2, r1
+ 8004ea8: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 8004cea: 687b ldr r3, [r7, #4]
- 8004cec: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004cee: f003 0308 and.w r3, r3, #8
- 8004cf2: 2b00 cmp r3, #0
- 8004cf4: d00a beq.n 8004d0c <UART_AdvFeatureConfig+0x90>
+ 8004eaa: 687b ldr r3, [r7, #4]
+ 8004eac: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004eae: f003 0308 and.w r3, r3, #8
+ 8004eb2: 2b00 cmp r3, #0
+ 8004eb4: d00a beq.n 8004ecc <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 8004cf6: 687b ldr r3, [r7, #4]
- 8004cf8: 681b ldr r3, [r3, #0]
- 8004cfa: 685b ldr r3, [r3, #4]
- 8004cfc: f423 4100 bic.w r1, r3, #32768 ; 0x8000
- 8004d00: 687b ldr r3, [r7, #4]
- 8004d02: 6b5a ldr r2, [r3, #52] ; 0x34
- 8004d04: 687b ldr r3, [r7, #4]
- 8004d06: 681b ldr r3, [r3, #0]
- 8004d08: 430a orrs r2, r1
- 8004d0a: 605a str r2, [r3, #4]
+ 8004eb6: 687b ldr r3, [r7, #4]
+ 8004eb8: 681b ldr r3, [r3, #0]
+ 8004eba: 685b ldr r3, [r3, #4]
+ 8004ebc: f423 4100 bic.w r1, r3, #32768 ; 0x8000
+ 8004ec0: 687b ldr r3, [r7, #4]
+ 8004ec2: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8004ec4: 687b ldr r3, [r7, #4]
+ 8004ec6: 681b ldr r3, [r3, #0]
+ 8004ec8: 430a orrs r2, r1
+ 8004eca: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 8004d0c: 687b ldr r3, [r7, #4]
- 8004d0e: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004d10: f003 0310 and.w r3, r3, #16
- 8004d14: 2b00 cmp r3, #0
- 8004d16: d00a beq.n 8004d2e <UART_AdvFeatureConfig+0xb2>
+ 8004ecc: 687b ldr r3, [r7, #4]
+ 8004ece: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004ed0: f003 0310 and.w r3, r3, #16
+ 8004ed4: 2b00 cmp r3, #0
+ 8004ed6: d00a beq.n 8004eee <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 8004d18: 687b ldr r3, [r7, #4]
- 8004d1a: 681b ldr r3, [r3, #0]
- 8004d1c: 689b ldr r3, [r3, #8]
- 8004d1e: f423 5180 bic.w r1, r3, #4096 ; 0x1000
- 8004d22: 687b ldr r3, [r7, #4]
- 8004d24: 6b9a ldr r2, [r3, #56] ; 0x38
- 8004d26: 687b ldr r3, [r7, #4]
- 8004d28: 681b ldr r3, [r3, #0]
- 8004d2a: 430a orrs r2, r1
- 8004d2c: 609a str r2, [r3, #8]
+ 8004ed8: 687b ldr r3, [r7, #4]
+ 8004eda: 681b ldr r3, [r3, #0]
+ 8004edc: 689b ldr r3, [r3, #8]
+ 8004ede: f423 5180 bic.w r1, r3, #4096 ; 0x1000
+ 8004ee2: 687b ldr r3, [r7, #4]
+ 8004ee4: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8004ee6: 687b ldr r3, [r7, #4]
+ 8004ee8: 681b ldr r3, [r3, #0]
+ 8004eea: 430a orrs r2, r1
+ 8004eec: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 8004d2e: 687b ldr r3, [r7, #4]
- 8004d30: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004d32: f003 0320 and.w r3, r3, #32
- 8004d36: 2b00 cmp r3, #0
- 8004d38: d00a beq.n 8004d50 <UART_AdvFeatureConfig+0xd4>
+ 8004eee: 687b ldr r3, [r7, #4]
+ 8004ef0: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004ef2: f003 0320 and.w r3, r3, #32
+ 8004ef6: 2b00 cmp r3, #0
+ 8004ef8: d00a beq.n 8004f10 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 8004d3a: 687b ldr r3, [r7, #4]
- 8004d3c: 681b ldr r3, [r3, #0]
- 8004d3e: 689b ldr r3, [r3, #8]
- 8004d40: f423 5100 bic.w r1, r3, #8192 ; 0x2000
- 8004d44: 687b ldr r3, [r7, #4]
- 8004d46: 6bda ldr r2, [r3, #60] ; 0x3c
- 8004d48: 687b ldr r3, [r7, #4]
- 8004d4a: 681b ldr r3, [r3, #0]
- 8004d4c: 430a orrs r2, r1
- 8004d4e: 609a str r2, [r3, #8]
+ 8004efa: 687b ldr r3, [r7, #4]
+ 8004efc: 681b ldr r3, [r3, #0]
+ 8004efe: 689b ldr r3, [r3, #8]
+ 8004f00: f423 5100 bic.w r1, r3, #8192 ; 0x2000
+ 8004f04: 687b ldr r3, [r7, #4]
+ 8004f06: 6bda ldr r2, [r3, #60] ; 0x3c
+ 8004f08: 687b ldr r3, [r7, #4]
+ 8004f0a: 681b ldr r3, [r3, #0]
+ 8004f0c: 430a orrs r2, r1
+ 8004f0e: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 8004d50: 687b ldr r3, [r7, #4]
- 8004d52: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004d54: f003 0340 and.w r3, r3, #64 ; 0x40
- 8004d58: 2b00 cmp r3, #0
- 8004d5a: d01a beq.n 8004d92 <UART_AdvFeatureConfig+0x116>
+ 8004f10: 687b ldr r3, [r7, #4]
+ 8004f12: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004f14: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8004f18: 2b00 cmp r3, #0
+ 8004f1a: d01a beq.n 8004f52 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 8004d5c: 687b ldr r3, [r7, #4]
- 8004d5e: 681b ldr r3, [r3, #0]
- 8004d60: 685b ldr r3, [r3, #4]
- 8004d62: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
- 8004d66: 687b ldr r3, [r7, #4]
- 8004d68: 6c1a ldr r2, [r3, #64] ; 0x40
- 8004d6a: 687b ldr r3, [r7, #4]
- 8004d6c: 681b ldr r3, [r3, #0]
- 8004d6e: 430a orrs r2, r1
- 8004d70: 605a str r2, [r3, #4]
+ 8004f1c: 687b ldr r3, [r7, #4]
+ 8004f1e: 681b ldr r3, [r3, #0]
+ 8004f20: 685b ldr r3, [r3, #4]
+ 8004f22: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
+ 8004f26: 687b ldr r3, [r7, #4]
+ 8004f28: 6c1a ldr r2, [r3, #64] ; 0x40
+ 8004f2a: 687b ldr r3, [r7, #4]
+ 8004f2c: 681b ldr r3, [r3, #0]
+ 8004f2e: 430a orrs r2, r1
+ 8004f30: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 8004d72: 687b ldr r3, [r7, #4]
- 8004d74: 6c1b ldr r3, [r3, #64] ; 0x40
- 8004d76: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8004d7a: d10a bne.n 8004d92 <UART_AdvFeatureConfig+0x116>
+ 8004f32: 687b ldr r3, [r7, #4]
+ 8004f34: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8004f36: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 8004f3a: d10a bne.n 8004f52 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8004d7c: 687b ldr r3, [r7, #4]
- 8004d7e: 681b ldr r3, [r3, #0]
- 8004d80: 685b ldr r3, [r3, #4]
- 8004d82: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
- 8004d86: 687b ldr r3, [r7, #4]
- 8004d88: 6c5a ldr r2, [r3, #68] ; 0x44
- 8004d8a: 687b ldr r3, [r7, #4]
- 8004d8c: 681b ldr r3, [r3, #0]
- 8004d8e: 430a orrs r2, r1
- 8004d90: 605a str r2, [r3, #4]
+ 8004f3c: 687b ldr r3, [r7, #4]
+ 8004f3e: 681b ldr r3, [r3, #0]
+ 8004f40: 685b ldr r3, [r3, #4]
+ 8004f42: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
+ 8004f46: 687b ldr r3, [r7, #4]
+ 8004f48: 6c5a ldr r2, [r3, #68] ; 0x44
+ 8004f4a: 687b ldr r3, [r7, #4]
+ 8004f4c: 681b ldr r3, [r3, #0]
+ 8004f4e: 430a orrs r2, r1
+ 8004f50: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 8004d92: 687b ldr r3, [r7, #4]
- 8004d94: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004d96: f003 0380 and.w r3, r3, #128 ; 0x80
- 8004d9a: 2b00 cmp r3, #0
- 8004d9c: d00a beq.n 8004db4 <UART_AdvFeatureConfig+0x138>
+ 8004f52: 687b ldr r3, [r7, #4]
+ 8004f54: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004f56: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8004f5a: 2b00 cmp r3, #0
+ 8004f5c: d00a beq.n 8004f74 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 8004d9e: 687b ldr r3, [r7, #4]
- 8004da0: 681b ldr r3, [r3, #0]
- 8004da2: 685b ldr r3, [r3, #4]
- 8004da4: f423 2100 bic.w r1, r3, #524288 ; 0x80000
- 8004da8: 687b ldr r3, [r7, #4]
- 8004daa: 6c9a ldr r2, [r3, #72] ; 0x48
- 8004dac: 687b ldr r3, [r7, #4]
- 8004dae: 681b ldr r3, [r3, #0]
- 8004db0: 430a orrs r2, r1
- 8004db2: 605a str r2, [r3, #4]
+ 8004f5e: 687b ldr r3, [r7, #4]
+ 8004f60: 681b ldr r3, [r3, #0]
+ 8004f62: 685b ldr r3, [r3, #4]
+ 8004f64: f423 2100 bic.w r1, r3, #524288 ; 0x80000
+ 8004f68: 687b ldr r3, [r7, #4]
+ 8004f6a: 6c9a ldr r2, [r3, #72] ; 0x48
+ 8004f6c: 687b ldr r3, [r7, #4]
+ 8004f6e: 681b ldr r3, [r3, #0]
+ 8004f70: 430a orrs r2, r1
+ 8004f72: 605a str r2, [r3, #4]
}
}
- 8004db4: bf00 nop
- 8004db6: 370c adds r7, #12
- 8004db8: 46bd mov sp, r7
- 8004dba: f85d 7b04 ldr.w r7, [sp], #4
- 8004dbe: 4770 bx lr
+ 8004f74: bf00 nop
+ 8004f76: 370c adds r7, #12
+ 8004f78: 46bd mov sp, r7
+ 8004f7a: f85d 7b04 ldr.w r7, [sp], #4
+ 8004f7e: 4770 bx lr
-08004dc0 <UART_CheckIdleState>:
+08004f80 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
- 8004dc0: b580 push {r7, lr}
- 8004dc2: b086 sub sp, #24
- 8004dc4: af02 add r7, sp, #8
- 8004dc6: 6078 str r0, [r7, #4]
+ 8004f80: b580 push {r7, lr}
+ 8004f82: b086 sub sp, #24
+ 8004f84: af02 add r7, sp, #8
+ 8004f86: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8004dc8: 687b ldr r3, [r7, #4]
- 8004dca: 2200 movs r2, #0
- 8004dcc: 67da str r2, [r3, #124] ; 0x7c
+ 8004f88: 687b ldr r3, [r7, #4]
+ 8004f8a: 2200 movs r2, #0
+ 8004f8c: 67da str r2, [r3, #124] ; 0x7c
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- 8004dce: f7fc fe35 bl 8001a3c <HAL_GetTick>
- 8004dd2: 60f8 str r0, [r7, #12]
+ 8004f8e: f7fc fd93 bl 8001ab8 <HAL_GetTick>
+ 8004f92: 60f8 str r0, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 8004dd4: 687b ldr r3, [r7, #4]
- 8004dd6: 681b ldr r3, [r3, #0]
- 8004dd8: 681b ldr r3, [r3, #0]
- 8004dda: f003 0308 and.w r3, r3, #8
- 8004dde: 2b08 cmp r3, #8
- 8004de0: d10e bne.n 8004e00 <UART_CheckIdleState+0x40>
+ 8004f94: 687b ldr r3, [r7, #4]
+ 8004f96: 681b ldr r3, [r3, #0]
+ 8004f98: 681b ldr r3, [r3, #0]
+ 8004f9a: f003 0308 and.w r3, r3, #8
+ 8004f9e: 2b08 cmp r3, #8
+ 8004fa0: d10e bne.n 8004fc0 <UART_CheckIdleState+0x40>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 8004de2: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
- 8004de6: 9300 str r3, [sp, #0]
- 8004de8: 68fb ldr r3, [r7, #12]
- 8004dea: 2200 movs r2, #0
- 8004dec: f44f 1100 mov.w r1, #2097152 ; 0x200000
- 8004df0: 6878 ldr r0, [r7, #4]
- 8004df2: f000 f814 bl 8004e1e <UART_WaitOnFlagUntilTimeout>
- 8004df6: 4603 mov r3, r0
- 8004df8: 2b00 cmp r3, #0
- 8004dfa: d001 beq.n 8004e00 <UART_CheckIdleState+0x40>
+ 8004fa2: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
+ 8004fa6: 9300 str r3, [sp, #0]
+ 8004fa8: 68fb ldr r3, [r7, #12]
+ 8004faa: 2200 movs r2, #0
+ 8004fac: f44f 1100 mov.w r1, #2097152 ; 0x200000
+ 8004fb0: 6878 ldr r0, [r7, #4]
+ 8004fb2: f000 f814 bl 8004fde <UART_WaitOnFlagUntilTimeout>
+ 8004fb6: 4603 mov r3, r0
+ 8004fb8: 2b00 cmp r3, #0
+ 8004fba: d001 beq.n 8004fc0 <UART_CheckIdleState+0x40>
{
/* Timeout occurred */
return HAL_TIMEOUT;
- 8004dfc: 2303 movs r3, #3
- 8004dfe: e00a b.n 8004e16 <UART_CheckIdleState+0x56>
+ 8004fbc: 2303 movs r3, #3
+ 8004fbe: e00a b.n 8004fd6 <UART_CheckIdleState+0x56>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
- 8004e00: 687b ldr r3, [r7, #4]
- 8004e02: 2220 movs r2, #32
- 8004e04: 675a str r2, [r3, #116] ; 0x74
+ 8004fc0: 687b ldr r3, [r7, #4]
+ 8004fc2: 2220 movs r2, #32
+ 8004fc4: 675a str r2, [r3, #116] ; 0x74
huart->RxState = HAL_UART_STATE_READY;
- 8004e06: 687b ldr r3, [r7, #4]
- 8004e08: 2220 movs r2, #32
- 8004e0a: 679a str r2, [r3, #120] ; 0x78
+ 8004fc6: 687b ldr r3, [r7, #4]
+ 8004fc8: 2220 movs r2, #32
+ 8004fca: 679a str r2, [r3, #120] ; 0x78
/* Process Unlocked */
__HAL_UNLOCK(huart);
- 8004e0c: 687b ldr r3, [r7, #4]
- 8004e0e: 2200 movs r2, #0
- 8004e10: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 8004fcc: 687b ldr r3, [r7, #4]
+ 8004fce: 2200 movs r2, #0
+ 8004fd0: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_OK;
- 8004e14: 2300 movs r3, #0
+ 8004fd4: 2300 movs r3, #0
}
- 8004e16: 4618 mov r0, r3
- 8004e18: 3710 adds r7, #16
- 8004e1a: 46bd mov sp, r7
- 8004e1c: bd80 pop {r7, pc}
+ 8004fd6: 4618 mov r0, r3
+ 8004fd8: 3710 adds r7, #16
+ 8004fda: 46bd mov sp, r7
+ 8004fdc: bd80 pop {r7, pc}
-08004e1e <UART_WaitOnFlagUntilTimeout>:
+08004fde <UART_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- 8004e1e: b580 push {r7, lr}
- 8004e20: b084 sub sp, #16
- 8004e22: af00 add r7, sp, #0
- 8004e24: 60f8 str r0, [r7, #12]
- 8004e26: 60b9 str r1, [r7, #8]
- 8004e28: 603b str r3, [r7, #0]
- 8004e2a: 4613 mov r3, r2
- 8004e2c: 71fb strb r3, [r7, #7]
+ 8004fde: b580 push {r7, lr}
+ 8004fe0: b084 sub sp, #16
+ 8004fe2: af00 add r7, sp, #0
+ 8004fe4: 60f8 str r0, [r7, #12]
+ 8004fe6: 60b9 str r1, [r7, #8]
+ 8004fe8: 603b str r3, [r7, #0]
+ 8004fea: 4613 mov r3, r2
+ 8004fec: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8004e2e: e02a b.n 8004e86 <UART_WaitOnFlagUntilTimeout+0x68>
+ 8004fee: e02a b.n 8005046 <UART_WaitOnFlagUntilTimeout+0x68>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
- 8004e30: 69bb ldr r3, [r7, #24]
- 8004e32: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 8004e36: d026 beq.n 8004e86 <UART_WaitOnFlagUntilTimeout+0x68>
+ 8004ff0: 69bb ldr r3, [r7, #24]
+ 8004ff2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
+ 8004ff6: d026 beq.n 8005046 <UART_WaitOnFlagUntilTimeout+0x68>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8004e38: f7fc fe00 bl 8001a3c <HAL_GetTick>
- 8004e3c: 4602 mov r2, r0
- 8004e3e: 683b ldr r3, [r7, #0]
- 8004e40: 1ad3 subs r3, r2, r3
- 8004e42: 69ba ldr r2, [r7, #24]
- 8004e44: 429a cmp r2, r3
- 8004e46: d302 bcc.n 8004e4e <UART_WaitOnFlagUntilTimeout+0x30>
- 8004e48: 69bb ldr r3, [r7, #24]
- 8004e4a: 2b00 cmp r3, #0
- 8004e4c: d11b bne.n 8004e86 <UART_WaitOnFlagUntilTimeout+0x68>
+ 8004ff8: f7fc fd5e bl 8001ab8 <HAL_GetTick>
+ 8004ffc: 4602 mov r2, r0
+ 8004ffe: 683b ldr r3, [r7, #0]
+ 8005000: 1ad3 subs r3, r2, r3
+ 8005002: 69ba ldr r2, [r7, #24]
+ 8005004: 429a cmp r2, r3
+ 8005006: d302 bcc.n 800500e <UART_WaitOnFlagUntilTimeout+0x30>
+ 8005008: 69bb ldr r3, [r7, #24]
+ 800500a: 2b00 cmp r3, #0
+ 800500c: d11b bne.n 8005046 <UART_WaitOnFlagUntilTimeout+0x68>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 8004e4e: 68fb ldr r3, [r7, #12]
- 8004e50: 681b ldr r3, [r3, #0]
- 8004e52: 681a ldr r2, [r3, #0]
- 8004e54: 68fb ldr r3, [r7, #12]
- 8004e56: 681b ldr r3, [r3, #0]
- 8004e58: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 8004e5c: 601a str r2, [r3, #0]
+ 800500e: 68fb ldr r3, [r7, #12]
+ 8005010: 681b ldr r3, [r3, #0]
+ 8005012: 681a ldr r2, [r3, #0]
+ 8005014: 68fb ldr r3, [r7, #12]
+ 8005016: 681b ldr r3, [r3, #0]
+ 8005018: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
+ 800501c: 601a str r2, [r3, #0]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8004e5e: 68fb ldr r3, [r7, #12]
- 8004e60: 681b ldr r3, [r3, #0]
- 8004e62: 689a ldr r2, [r3, #8]
- 8004e64: 68fb ldr r3, [r7, #12]
- 8004e66: 681b ldr r3, [r3, #0]
- 8004e68: f022 0201 bic.w r2, r2, #1
- 8004e6c: 609a str r2, [r3, #8]
+ 800501e: 68fb ldr r3, [r7, #12]
+ 8005020: 681b ldr r3, [r3, #0]
+ 8005022: 689a ldr r2, [r3, #8]
+ 8005024: 68fb ldr r3, [r7, #12]
+ 8005026: 681b ldr r3, [r3, #0]
+ 8005028: f022 0201 bic.w r2, r2, #1
+ 800502c: 609a str r2, [r3, #8]
huart->gState = HAL_UART_STATE_READY;
- 8004e6e: 68fb ldr r3, [r7, #12]
- 8004e70: 2220 movs r2, #32
- 8004e72: 675a str r2, [r3, #116] ; 0x74
+ 800502e: 68fb ldr r3, [r7, #12]
+ 8005030: 2220 movs r2, #32
+ 8005032: 675a str r2, [r3, #116] ; 0x74
huart->RxState = HAL_UART_STATE_READY;
- 8004e74: 68fb ldr r3, [r7, #12]
- 8004e76: 2220 movs r2, #32
- 8004e78: 679a str r2, [r3, #120] ; 0x78
+ 8005034: 68fb ldr r3, [r7, #12]
+ 8005036: 2220 movs r2, #32
+ 8005038: 679a str r2, [r3, #120] ; 0x78
/* Process Unlocked */
__HAL_UNLOCK(huart);
- 8004e7a: 68fb ldr r3, [r7, #12]
- 8004e7c: 2200 movs r2, #0
- 8004e7e: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 800503a: 68fb ldr r3, [r7, #12]
+ 800503c: 2200 movs r2, #0
+ 800503e: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_TIMEOUT;
- 8004e82: 2303 movs r3, #3
- 8004e84: e00f b.n 8004ea6 <UART_WaitOnFlagUntilTimeout+0x88>
+ 8005042: 2303 movs r3, #3
+ 8005044: e00f b.n 8005066 <UART_WaitOnFlagUntilTimeout+0x88>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8004e86: 68fb ldr r3, [r7, #12]
- 8004e88: 681b ldr r3, [r3, #0]
- 8004e8a: 69da ldr r2, [r3, #28]
- 8004e8c: 68bb ldr r3, [r7, #8]
- 8004e8e: 4013 ands r3, r2
- 8004e90: 68ba ldr r2, [r7, #8]
- 8004e92: 429a cmp r2, r3
- 8004e94: bf0c ite eq
- 8004e96: 2301 moveq r3, #1
- 8004e98: 2300 movne r3, #0
- 8004e9a: b2db uxtb r3, r3
- 8004e9c: 461a mov r2, r3
- 8004e9e: 79fb ldrb r3, [r7, #7]
- 8004ea0: 429a cmp r2, r3
- 8004ea2: d0c5 beq.n 8004e30 <UART_WaitOnFlagUntilTimeout+0x12>
+ 8005046: 68fb ldr r3, [r7, #12]
+ 8005048: 681b ldr r3, [r3, #0]
+ 800504a: 69da ldr r2, [r3, #28]
+ 800504c: 68bb ldr r3, [r7, #8]
+ 800504e: 4013 ands r3, r2
+ 8005050: 68ba ldr r2, [r7, #8]
+ 8005052: 429a cmp r2, r3
+ 8005054: bf0c ite eq
+ 8005056: 2301 moveq r3, #1
+ 8005058: 2300 movne r3, #0
+ 800505a: b2db uxtb r3, r3
+ 800505c: 461a mov r2, r3
+ 800505e: 79fb ldrb r3, [r7, #7]
+ 8005060: 429a cmp r2, r3
+ 8005062: d0c5 beq.n 8004ff0 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
- 8004ea4: 2300 movs r3, #0
+ 8005064: 2300 movs r3, #0
}
- 8004ea6: 4618 mov r0, r3
- 8004ea8: 3710 adds r7, #16
- 8004eaa: 46bd mov sp, r7
- 8004eac: bd80 pop {r7, pc}
+ 8005066: 4618 mov r0, r3
+ 8005068: 3710 adds r7, #16
+ 800506a: 46bd mov sp, r7
+ 800506c: bd80 pop {r7, pc}
-08004eae <UART_EndRxTransfer>:
+0800506e <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
- 8004eae: b480 push {r7}
- 8004eb0: b083 sub sp, #12
- 8004eb2: af00 add r7, sp, #0
- 8004eb4: 6078 str r0, [r7, #4]
+ 800506e: b480 push {r7}
+ 8005070: b083 sub sp, #12
+ 8005072: af00 add r7, sp, #0
+ 8005074: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 8004eb6: 687b ldr r3, [r7, #4]
- 8004eb8: 681b ldr r3, [r3, #0]
- 8004eba: 681a ldr r2, [r3, #0]
- 8004ebc: 687b ldr r3, [r7, #4]
- 8004ebe: 681b ldr r3, [r3, #0]
- 8004ec0: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8004ec4: 601a str r2, [r3, #0]
+ 8005076: 687b ldr r3, [r7, #4]
+ 8005078: 681b ldr r3, [r3, #0]
+ 800507a: 681a ldr r2, [r3, #0]
+ 800507c: 687b ldr r3, [r7, #4]
+ 800507e: 681b ldr r3, [r3, #0]
+ 8005080: f422 7290 bic.w r2, r2, #288 ; 0x120
+ 8005084: 601a str r2, [r3, #0]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8004ec6: 687b ldr r3, [r7, #4]
- 8004ec8: 681b ldr r3, [r3, #0]
- 8004eca: 689a ldr r2, [r3, #8]
- 8004ecc: 687b ldr r3, [r7, #4]
- 8004ece: 681b ldr r3, [r3, #0]
- 8004ed0: f022 0201 bic.w r2, r2, #1
- 8004ed4: 609a str r2, [r3, #8]
+ 8005086: 687b ldr r3, [r7, #4]
+ 8005088: 681b ldr r3, [r3, #0]
+ 800508a: 689a ldr r2, [r3, #8]
+ 800508c: 687b ldr r3, [r7, #4]
+ 800508e: 681b ldr r3, [r3, #0]
+ 8005090: f022 0201 bic.w r2, r2, #1
+ 8005094: 609a str r2, [r3, #8]
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
- 8004ed6: 687b ldr r3, [r7, #4]
- 8004ed8: 2220 movs r2, #32
- 8004eda: 679a str r2, [r3, #120] ; 0x78
+ 8005096: 687b ldr r3, [r7, #4]
+ 8005098: 2220 movs r2, #32
+ 800509a: 679a str r2, [r3, #120] ; 0x78
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
- 8004edc: 687b ldr r3, [r7, #4]
- 8004ede: 2200 movs r2, #0
- 8004ee0: 661a str r2, [r3, #96] ; 0x60
+ 800509c: 687b ldr r3, [r7, #4]
+ 800509e: 2200 movs r2, #0
+ 80050a0: 661a str r2, [r3, #96] ; 0x60
}
- 8004ee2: bf00 nop
- 8004ee4: 370c adds r7, #12
- 8004ee6: 46bd mov sp, r7
- 8004ee8: f85d 7b04 ldr.w r7, [sp], #4
- 8004eec: 4770 bx lr
+ 80050a2: bf00 nop
+ 80050a4: 370c adds r7, #12
+ 80050a6: 46bd mov sp, r7
+ 80050a8: f85d 7b04 ldr.w r7, [sp], #4
+ 80050ac: 4770 bx lr
-08004eee <UART_DMAAbortOnError>:
+080050ae <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- 8004eee: b580 push {r7, lr}
- 8004ef0: b084 sub sp, #16
- 8004ef2: af00 add r7, sp, #0
- 8004ef4: 6078 str r0, [r7, #4]
+ 80050ae: b580 push {r7, lr}
+ 80050b0: b084 sub sp, #16
+ 80050b2: af00 add r7, sp, #0
+ 80050b4: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 8004ef6: 687b ldr r3, [r7, #4]
- 8004ef8: 6b9b ldr r3, [r3, #56] ; 0x38
- 8004efa: 60fb str r3, [r7, #12]
+ 80050b6: 687b ldr r3, [r7, #4]
+ 80050b8: 6b9b ldr r3, [r3, #56] ; 0x38
+ 80050ba: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
- 8004efc: 68fb ldr r3, [r7, #12]
- 8004efe: 2200 movs r2, #0
- 8004f00: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+ 80050bc: 68fb ldr r3, [r7, #12]
+ 80050be: 2200 movs r2, #0
+ 80050c0: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
huart->TxXferCount = 0U;
- 8004f04: 68fb ldr r3, [r7, #12]
- 8004f06: 2200 movs r2, #0
- 8004f08: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+ 80050c4: 68fb ldr r3, [r7, #12]
+ 80050c6: 2200 movs r2, #0
+ 80050c8: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
- 8004f0c: 68f8 ldr r0, [r7, #12]
- 8004f0e: f7ff fc07 bl 8004720 <HAL_UART_ErrorCallback>
+ 80050cc: 68f8 ldr r0, [r7, #12]
+ 80050ce: f7ff fc07 bl 80048e0 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- 8004f12: bf00 nop
- 8004f14: 3710 adds r7, #16
- 8004f16: 46bd mov sp, r7
- 8004f18: bd80 pop {r7, pc}
+ 80050d2: bf00 nop
+ 80050d4: 3710 adds r7, #16
+ 80050d6: 46bd mov sp, r7
+ 80050d8: bd80 pop {r7, pc}
-08004f1a <UART_EndTransmit_IT>:
+080050da <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
- 8004f1a: b580 push {r7, lr}
- 8004f1c: b082 sub sp, #8
- 8004f1e: af00 add r7, sp, #0
- 8004f20: 6078 str r0, [r7, #4]
+ 80050da: b580 push {r7, lr}
+ 80050dc: b082 sub sp, #8
+ 80050de: af00 add r7, sp, #0
+ 80050e0: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- 8004f22: 687b ldr r3, [r7, #4]
- 8004f24: 681b ldr r3, [r3, #0]
- 8004f26: 681a ldr r2, [r3, #0]
- 8004f28: 687b ldr r3, [r7, #4]
- 8004f2a: 681b ldr r3, [r3, #0]
- 8004f2c: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8004f30: 601a str r2, [r3, #0]
+ 80050e2: 687b ldr r3, [r7, #4]
+ 80050e4: 681b ldr r3, [r3, #0]
+ 80050e6: 681a ldr r2, [r3, #0]
+ 80050e8: 687b ldr r3, [r7, #4]
+ 80050ea: 681b ldr r3, [r3, #0]
+ 80050ec: f022 0240 bic.w r2, r2, #64 ; 0x40
+ 80050f0: 601a str r2, [r3, #0]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- 8004f32: 687b ldr r3, [r7, #4]
- 8004f34: 2220 movs r2, #32
- 8004f36: 675a str r2, [r3, #116] ; 0x74
+ 80050f2: 687b ldr r3, [r7, #4]
+ 80050f4: 2220 movs r2, #32
+ 80050f6: 675a str r2, [r3, #116] ; 0x74
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
- 8004f38: 687b ldr r3, [r7, #4]
- 8004f3a: 2200 movs r2, #0
- 8004f3c: 665a str r2, [r3, #100] ; 0x64
+ 80050f8: 687b ldr r3, [r7, #4]
+ 80050fa: 2200 movs r2, #0
+ 80050fc: 665a str r2, [r3, #100] ; 0x64
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
- 8004f3e: 6878 ldr r0, [r7, #4]
- 8004f40: f7ff fbe4 bl 800470c <HAL_UART_TxCpltCallback>
+ 80050fe: 6878 ldr r0, [r7, #4]
+ 8005100: f7ff fbe4 bl 80048cc <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- 8004f44: bf00 nop
- 8004f46: 3708 adds r7, #8
- 8004f48: 46bd mov sp, r7
- 8004f4a: bd80 pop {r7, pc}
-
-08004f4c <__libc_init_array>:
- 8004f4c: b570 push {r4, r5, r6, lr}
- 8004f4e: 4e0d ldr r6, [pc, #52] ; (8004f84 <__libc_init_array+0x38>)
- 8004f50: 4c0d ldr r4, [pc, #52] ; (8004f88 <__libc_init_array+0x3c>)
- 8004f52: 1ba4 subs r4, r4, r6
- 8004f54: 10a4 asrs r4, r4, #2
- 8004f56: 2500 movs r5, #0
- 8004f58: 42a5 cmp r5, r4
- 8004f5a: d109 bne.n 8004f70 <__libc_init_array+0x24>
- 8004f5c: 4e0b ldr r6, [pc, #44] ; (8004f8c <__libc_init_array+0x40>)
- 8004f5e: 4c0c ldr r4, [pc, #48] ; (8004f90 <__libc_init_array+0x44>)
- 8004f60: f000 f820 bl 8004fa4 <_init>
- 8004f64: 1ba4 subs r4, r4, r6
- 8004f66: 10a4 asrs r4, r4, #2
- 8004f68: 2500 movs r5, #0
- 8004f6a: 42a5 cmp r5, r4
- 8004f6c: d105 bne.n 8004f7a <__libc_init_array+0x2e>
- 8004f6e: bd70 pop {r4, r5, r6, pc}
- 8004f70: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8004f74: 4798 blx r3
- 8004f76: 3501 adds r5, #1
- 8004f78: e7ee b.n 8004f58 <__libc_init_array+0xc>
- 8004f7a: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8004f7e: 4798 blx r3
- 8004f80: 3501 adds r5, #1
- 8004f82: e7f2 b.n 8004f6a <__libc_init_array+0x1e>
- 8004f84: 08004fdc .word 0x08004fdc
- 8004f88: 08004fdc .word 0x08004fdc
- 8004f8c: 08004fdc .word 0x08004fdc
- 8004f90: 08004fe4 .word 0x08004fe4
-
-08004f94 <memset>:
- 8004f94: 4402 add r2, r0
- 8004f96: 4603 mov r3, r0
- 8004f98: 4293 cmp r3, r2
- 8004f9a: d100 bne.n 8004f9e <memset+0xa>
- 8004f9c: 4770 bx lr
- 8004f9e: f803 1b01 strb.w r1, [r3], #1
- 8004fa2: e7f9 b.n 8004f98 <memset+0x4>
-
-08004fa4 <_init>:
- 8004fa4: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8004fa6: bf00 nop
- 8004fa8: bcf8 pop {r3, r4, r5, r6, r7}
- 8004faa: bc08 pop {r3}
- 8004fac: 469e mov lr, r3
- 8004fae: 4770 bx lr
-
-08004fb0 <_fini>:
- 8004fb0: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8004fb2: bf00 nop
- 8004fb4: bcf8 pop {r3, r4, r5, r6, r7}
- 8004fb6: bc08 pop {r3}
- 8004fb8: 469e mov lr, r3
- 8004fba: 4770 bx lr
+ 8005104: bf00 nop
+ 8005106: 3708 adds r7, #8
+ 8005108: 46bd mov sp, r7
+ 800510a: bd80 pop {r7, pc}
+
+0800510c <UART_RxISR_8BIT>:
+ * @brief RX interrrupt handler for 7 or 8 bits data word length .
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ 800510c: b580 push {r7, lr}
+ 800510e: b084 sub sp, #16
+ 8005110: af00 add r7, sp, #0
+ 8005112: 6078 str r0, [r7, #4]
+ uint16_t uhMask = huart->Mask;
+ 8005114: 687b ldr r3, [r7, #4]
+ 8005116: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
+ 800511a: 81fb strh r3, [r7, #14]
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 800511c: 687b ldr r3, [r7, #4]
+ 800511e: 6f9b ldr r3, [r3, #120] ; 0x78
+ 8005120: 2b22 cmp r3, #34 ; 0x22
+ 8005122: d13a bne.n 800519a <UART_RxISR_8BIT+0x8e>
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 8005124: 687b ldr r3, [r7, #4]
+ 8005126: 681b ldr r3, [r3, #0]
+ 8005128: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800512a: 81bb strh r3, [r7, #12]
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 800512c: 89bb ldrh r3, [r7, #12]
+ 800512e: b2d9 uxtb r1, r3
+ 8005130: 89fb ldrh r3, [r7, #14]
+ 8005132: b2da uxtb r2, r3
+ 8005134: 687b ldr r3, [r7, #4]
+ 8005136: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8005138: 400a ands r2, r1
+ 800513a: b2d2 uxtb r2, r2
+ 800513c: 701a strb r2, [r3, #0]
+ huart->pRxBuffPtr++;
+ 800513e: 687b ldr r3, [r7, #4]
+ 8005140: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8005142: 1c5a adds r2, r3, #1
+ 8005144: 687b ldr r3, [r7, #4]
+ 8005146: 655a str r2, [r3, #84] ; 0x54
+ huart->RxXferCount--;
+ 8005148: 687b ldr r3, [r7, #4]
+ 800514a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 800514e: b29b uxth r3, r3
+ 8005150: 3b01 subs r3, #1
+ 8005152: b29a uxth r2, r3
+ 8005154: 687b ldr r3, [r7, #4]
+ 8005156: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+
+ if (huart->RxXferCount == 0U)
+ 800515a: 687b ldr r3, [r7, #4]
+ 800515c: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 8005160: b29b uxth r3, r3
+ 8005162: 2b00 cmp r3, #0
+ 8005164: d121 bne.n 80051aa <UART_RxISR_8BIT+0x9e>
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ 8005166: 687b ldr r3, [r7, #4]
+ 8005168: 681b ldr r3, [r3, #0]
+ 800516a: 681a ldr r2, [r3, #0]
+ 800516c: 687b ldr r3, [r7, #4]
+ 800516e: 681b ldr r3, [r3, #0]
+ 8005170: f422 7290 bic.w r2, r2, #288 ; 0x120
+ 8005174: 601a str r2, [r3, #0]
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8005176: 687b ldr r3, [r7, #4]
+ 8005178: 681b ldr r3, [r3, #0]
+ 800517a: 689a ldr r2, [r3, #8]
+ 800517c: 687b ldr r3, [r7, #4]
+ 800517e: 681b ldr r3, [r3, #0]
+ 8005180: f022 0201 bic.w r2, r2, #1
+ 8005184: 609a str r2, [r3, #8]
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ 8005186: 687b ldr r3, [r7, #4]
+ 8005188: 2220 movs r2, #32
+ 800518a: 679a str r2, [r3, #120] ; 0x78
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+ 800518c: 687b ldr r3, [r7, #4]
+ 800518e: 2200 movs r2, #0
+ 8005190: 661a str r2, [r3, #96] ; 0x60
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+ 8005192: 6878 ldr r0, [r7, #4]
+ 8005194: f7fc f942 bl 800141c <HAL_UART_RxCpltCallback>
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+ 8005198: e007 b.n 80051aa <UART_RxISR_8BIT+0x9e>
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 800519a: 687b ldr r3, [r7, #4]
+ 800519c: 681b ldr r3, [r3, #0]
+ 800519e: 699a ldr r2, [r3, #24]
+ 80051a0: 687b ldr r3, [r7, #4]
+ 80051a2: 681b ldr r3, [r3, #0]
+ 80051a4: f042 0208 orr.w r2, r2, #8
+ 80051a8: 619a str r2, [r3, #24]
+}
+ 80051aa: bf00 nop
+ 80051ac: 3710 adds r7, #16
+ 80051ae: 46bd mov sp, r7
+ 80051b0: bd80 pop {r7, pc}
+
+080051b2 <UART_RxISR_16BIT>:
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ 80051b2: b580 push {r7, lr}
+ 80051b4: b084 sub sp, #16
+ 80051b6: af00 add r7, sp, #0
+ 80051b8: 6078 str r0, [r7, #4]
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ 80051ba: 687b ldr r3, [r7, #4]
+ 80051bc: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
+ 80051c0: 81fb strh r3, [r7, #14]
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 80051c2: 687b ldr r3, [r7, #4]
+ 80051c4: 6f9b ldr r3, [r3, #120] ; 0x78
+ 80051c6: 2b22 cmp r3, #34 ; 0x22
+ 80051c8: d13a bne.n 8005240 <UART_RxISR_16BIT+0x8e>
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 80051ca: 687b ldr r3, [r7, #4]
+ 80051cc: 681b ldr r3, [r3, #0]
+ 80051ce: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80051d0: 81bb strh r3, [r7, #12]
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 80051d2: 687b ldr r3, [r7, #4]
+ 80051d4: 6d5b ldr r3, [r3, #84] ; 0x54
+ 80051d6: 60bb str r3, [r7, #8]
+ *tmp = (uint16_t)(uhdata & uhMask);
+ 80051d8: 89ba ldrh r2, [r7, #12]
+ 80051da: 89fb ldrh r3, [r7, #14]
+ 80051dc: 4013 ands r3, r2
+ 80051de: b29a uxth r2, r3
+ 80051e0: 68bb ldr r3, [r7, #8]
+ 80051e2: 801a strh r2, [r3, #0]
+ huart->pRxBuffPtr += 2U;
+ 80051e4: 687b ldr r3, [r7, #4]
+ 80051e6: 6d5b ldr r3, [r3, #84] ; 0x54
+ 80051e8: 1c9a adds r2, r3, #2
+ 80051ea: 687b ldr r3, [r7, #4]
+ 80051ec: 655a str r2, [r3, #84] ; 0x54
+ huart->RxXferCount--;
+ 80051ee: 687b ldr r3, [r7, #4]
+ 80051f0: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 80051f4: b29b uxth r3, r3
+ 80051f6: 3b01 subs r3, #1
+ 80051f8: b29a uxth r2, r3
+ 80051fa: 687b ldr r3, [r7, #4]
+ 80051fc: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+
+ if (huart->RxXferCount == 0U)
+ 8005200: 687b ldr r3, [r7, #4]
+ 8005202: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 8005206: b29b uxth r3, r3
+ 8005208: 2b00 cmp r3, #0
+ 800520a: d121 bne.n 8005250 <UART_RxISR_16BIT+0x9e>
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ 800520c: 687b ldr r3, [r7, #4]
+ 800520e: 681b ldr r3, [r3, #0]
+ 8005210: 681a ldr r2, [r3, #0]
+ 8005212: 687b ldr r3, [r7, #4]
+ 8005214: 681b ldr r3, [r3, #0]
+ 8005216: f422 7290 bic.w r2, r2, #288 ; 0x120
+ 800521a: 601a str r2, [r3, #0]
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 800521c: 687b ldr r3, [r7, #4]
+ 800521e: 681b ldr r3, [r3, #0]
+ 8005220: 689a ldr r2, [r3, #8]
+ 8005222: 687b ldr r3, [r7, #4]
+ 8005224: 681b ldr r3, [r3, #0]
+ 8005226: f022 0201 bic.w r2, r2, #1
+ 800522a: 609a str r2, [r3, #8]
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ 800522c: 687b ldr r3, [r7, #4]
+ 800522e: 2220 movs r2, #32
+ 8005230: 679a str r2, [r3, #120] ; 0x78
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+ 8005232: 687b ldr r3, [r7, #4]
+ 8005234: 2200 movs r2, #0
+ 8005236: 661a str r2, [r3, #96] ; 0x60
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+ 8005238: 6878 ldr r0, [r7, #4]
+ 800523a: f7fc f8ef bl 800141c <HAL_UART_RxCpltCallback>
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+ 800523e: e007 b.n 8005250 <UART_RxISR_16BIT+0x9e>
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 8005240: 687b ldr r3, [r7, #4]
+ 8005242: 681b ldr r3, [r3, #0]
+ 8005244: 699a ldr r2, [r3, #24]
+ 8005246: 687b ldr r3, [r7, #4]
+ 8005248: 681b ldr r3, [r3, #0]
+ 800524a: f042 0208 orr.w r2, r2, #8
+ 800524e: 619a str r2, [r3, #24]
+}
+ 8005250: bf00 nop
+ 8005252: 3710 adds r7, #16
+ 8005254: 46bd mov sp, r7
+ 8005256: bd80 pop {r7, pc}
+
+08005258 <__libc_init_array>:
+ 8005258: b570 push {r4, r5, r6, lr}
+ 800525a: 4e0d ldr r6, [pc, #52] ; (8005290 <__libc_init_array+0x38>)
+ 800525c: 4c0d ldr r4, [pc, #52] ; (8005294 <__libc_init_array+0x3c>)
+ 800525e: 1ba4 subs r4, r4, r6
+ 8005260: 10a4 asrs r4, r4, #2
+ 8005262: 2500 movs r5, #0
+ 8005264: 42a5 cmp r5, r4
+ 8005266: d109 bne.n 800527c <__libc_init_array+0x24>
+ 8005268: 4e0b ldr r6, [pc, #44] ; (8005298 <__libc_init_array+0x40>)
+ 800526a: 4c0c ldr r4, [pc, #48] ; (800529c <__libc_init_array+0x44>)
+ 800526c: f000 f820 bl 80052b0 <_init>
+ 8005270: 1ba4 subs r4, r4, r6
+ 8005272: 10a4 asrs r4, r4, #2
+ 8005274: 2500 movs r5, #0
+ 8005276: 42a5 cmp r5, r4
+ 8005278: d105 bne.n 8005286 <__libc_init_array+0x2e>
+ 800527a: bd70 pop {r4, r5, r6, pc}
+ 800527c: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8005280: 4798 blx r3
+ 8005282: 3501 adds r5, #1
+ 8005284: e7ee b.n 8005264 <__libc_init_array+0xc>
+ 8005286: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 800528a: 4798 blx r3
+ 800528c: 3501 adds r5, #1
+ 800528e: e7f2 b.n 8005276 <__libc_init_array+0x1e>
+ 8005290: 080052e8 .word 0x080052e8
+ 8005294: 080052e8 .word 0x080052e8
+ 8005298: 080052e8 .word 0x080052e8
+ 800529c: 080052f0 .word 0x080052f0
+
+080052a0 <memset>:
+ 80052a0: 4402 add r2, r0
+ 80052a2: 4603 mov r3, r0
+ 80052a4: 4293 cmp r3, r2
+ 80052a6: d100 bne.n 80052aa <memset+0xa>
+ 80052a8: 4770 bx lr
+ 80052aa: f803 1b01 strb.w r1, [r3], #1
+ 80052ae: e7f9 b.n 80052a4 <memset+0x4>
+
+080052b0 <_init>:
+ 80052b0: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 80052b2: bf00 nop
+ 80052b4: bcf8 pop {r3, r4, r5, r6, r7}
+ 80052b6: bc08 pop {r3}
+ 80052b8: 469e mov lr, r3
+ 80052ba: 4770 bx lr
+
+080052bc <_fini>:
+ 80052bc: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 80052be: bf00 nop
+ 80052c0: bcf8 pop {r3, r4, r5, r6, r7}
+ 80052c2: bc08 pop {r3}
+ 80052c4: 469e mov lr, r3
+ 80052c6: 4770 bx lr
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Core/Src/stm32f7xx_hal_msp.c \
-../Core/Src/stm32f7xx_it.c \
-../Core/Src/syscalls.c \
-../Core/Src/sysmem.c \
-../Core/Src/system_stm32f7xx.c
-
-CPP_SRCS += \
-../Core/Src/duration.cpp \
-../Core/Src/encoder.cpp \
-../Core/Src/main.cpp \
-../Core/Src/odometry_calc.cpp \
-../Core/Src/time.cpp
-
-OBJS += \
-./Core/Src/duration.o \
-./Core/Src/encoder.o \
-./Core/Src/main.o \
-./Core/Src/odometry_calc.o \
-./Core/Src/stm32f7xx_hal_msp.o \
-./Core/Src/stm32f7xx_it.o \
-./Core/Src/syscalls.o \
-./Core/Src/sysmem.o \
-./Core/Src/system_stm32f7xx.o \
-./Core/Src/time.o
-
-C_DEPS += \
-./Core/Src/stm32f7xx_hal_msp.d \
-./Core/Src/stm32f7xx_it.d \
-./Core/Src/syscalls.d \
-./Core/Src/sysmem.d \
-./Core/Src/system_stm32f7xx.d
-
-CPP_DEPS += \
-./Core/Src/duration.d \
-./Core/Src/encoder.d \
-./Core/Src/main.d \
-./Core/Src/odometry_calc.d \
-./Core/Src/time.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Src/duration.o: ../Core/Src/duration.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/duration.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/encoder.o: ../Core/Src/encoder.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/encoder.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/main.o: ../Core/Src/main.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/odometry_calc.o: ../Core/Src/odometry_calc.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/odometry_calc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/syscalls.o: ../Core/Src/syscalls.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/sysmem.o: ../Core/Src/sysmem.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Core/Src/time.o: ../Core/Src/time.cpp
- arm-none-eabi-g++ "$<" -mcpu=cortex-m7 -std=gnu++14 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-threadsafe-statics -fno-use-cxa-atexit -Wall -fstack-usage -MMD -MP -MF"Core/Src/time.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-S_SRCS += \
-../Core/Startup/startup_stm32f767zitx.s
-
-OBJS += \
-./Core/Startup/startup_stm32f767zitx.o
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Core/Startup/%.o: ../Core/Startup/%.s
- arm-none-eabi-gcc -mcpu=cortex-m7 -c -x assembler-with-cpp --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-# Add inputs and outputs from these tool invocations to the build variables
-C_SRCS += \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \
-../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
-
-OBJS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o
-
-C_DEPS += \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \
-./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d
-
-
-# Each subdirectory must supply rules for building sources it contributes
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c
- arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -DUSE_HAL_DRIVER -DSTM32F767xx -c -I../Drivers/CMSIS/Include -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -O3 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
-
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
--include ../makefile.init
-
-RM := rm -rf
-
-# All of the sources participating in the build are defined here
--include sources.mk
--include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk
--include Core/Startup/subdir.mk
--include Core/Src/subdir.mk
--include subdir.mk
--include objects.mk
-
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(CC_DEPS)),)
--include $(CC_DEPS)
-endif
-ifneq ($(strip $(C++_DEPS)),)
--include $(C++_DEPS)
-endif
-ifneq ($(strip $(C_UPPER_DEPS)),)
--include $(C_UPPER_DEPS)
-endif
-ifneq ($(strip $(CXX_DEPS)),)
--include $(CXX_DEPS)
-endif
-ifneq ($(strip $(C_DEPS)),)
--include $(C_DEPS)
-endif
-ifneq ($(strip $(CPP_DEPS)),)
--include $(CPP_DEPS)
-endif
-endif
-
--include ../makefile.defs
-
-# Add inputs and outputs from these tool invocations to the build variables
-EXECUTABLES += \
-otto_controller_source.elf \
-
-SIZE_OUTPUT += \
-default.size.stdout \
-
-OBJDUMP_LIST += \
-otto_controller_source.list \
-
-
-# All Target
-all: otto_controller_source.elf secondary-outputs
-
-# Tool invocations
-otto_controller_source.elf: $(OBJS) $(USER_OBJS) /home/fdila/Projects/otto/otto_controller_source/STM32F767ZITX_FLASH.ld
- arm-none-eabi-g++ -o "otto_controller_source.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/fdila/Projects/otto/otto_controller_source/STM32F767ZITX_FLASH.ld" -Wl,-Map="otto_controller_source.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
- @echo 'Finished building target: $@'
- @echo ' '
-
-default.size.stdout: $(EXECUTABLES)
- arm-none-eabi-size $(EXECUTABLES)
- @echo 'Finished building: $@'
- @echo ' '
-
-otto_controller_source.list: $(EXECUTABLES)
- arm-none-eabi-objdump -h -S $(EXECUTABLES) > "otto_controller_source.list"
- @echo 'Finished building: $@'
- @echo ' '
-
-# Other Targets
-clean:
- -$(RM) *
- -@echo ' '
-
-secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
-
-.PHONY: all clean dependents
-.SECONDARY:
-
--include ../makefile.targets
+++ /dev/null
-"Core/Src/duration.o"
-"Core/Src/encoder.o"
-"Core/Src/main.o"
-"Core/Src/odometry_calc.o"
-"Core/Src/stm32f7xx_hal_msp.o"
-"Core/Src/stm32f7xx_it.o"
-"Core/Src/syscalls.o"
-"Core/Src/sysmem.o"
-"Core/Src/system_stm32f7xx.o"
-"Core/Src/time.o"
-"Core/Startup/startup_stm32f767zitx.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o"
-"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o"
+++ /dev/null
-
-otto_controller_source.elf: file format elf32-littlearm
-
-Sections:
-Idx Name Size VMA LMA File off Algn
- 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 00009dc4 080001f8 080001f8 000101f8 2**3
- CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000ab0 08009fc0 08009fc0 00019fc0 2**3
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 0800aa70 0800aa70 00020080 2**0
- CONTENTS
- 4 .ARM 00000008 0800aa70 0800aa70 0001aa70 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 0800aa78 0800aa78 00020080 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000008 0800aa78 0800aa78 0001aa78 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 0800aa80 0800aa80 0001aa80 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 8 .data 00000080 20000000 0800aa84 00020000 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 00000e40 20000080 0800ab04 00020080 2**2
- ALLOC
- 10 ._user_heap_stack 00000600 20000ec0 0800ab04 00020ec0 2**0
- ALLOC
- 11 .ARM.attributes 0000002e 00000000 00000000 00020080 2**0
- CONTENTS, READONLY
- 12 .comment 0000007b 00000000 00000000 000200ae 2**0
- CONTENTS, READONLY
- 13 .debug_frame 0000065c 00000000 00000000 0002012c 2**2
- CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-080001f8 <__do_global_dtors_aux>:
- 80001f8: b510 push {r4, lr}
- 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
- 80001fc: 7823 ldrb r3, [r4, #0]
- 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
- 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
- 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
- 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
- 8000206: f3af 8000 nop.w
- 800020a: 2301 movs r3, #1
- 800020c: 7023 strb r3, [r4, #0]
- 800020e: bd10 pop {r4, pc}
- 8000210: 20000080 .word 0x20000080
- 8000214: 00000000 .word 0x00000000
- 8000218: 08009fa4 .word 0x08009fa4
-
-0800021c <frame_dummy>:
- 800021c: b508 push {r3, lr}
- 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
- 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
- 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
- 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
- 8000226: f3af 8000 nop.w
- 800022a: bd08 pop {r3, pc}
- 800022c: 00000000 .word 0x00000000
- 8000230: 20000084 .word 0x20000084
- 8000234: 08009fa4 .word 0x08009fa4
-
-08000238 <strlen>:
- 8000238: 4603 mov r3, r0
- 800023a: f813 2b01 ldrb.w r2, [r3], #1
- 800023e: 2a00 cmp r2, #0
- 8000240: d1fb bne.n 800023a <strlen+0x2>
- 8000242: 1a18 subs r0, r3, r0
- 8000244: 3801 subs r0, #1
- 8000246: 4770 bx lr
-
-08000248 <__aeabi_uldivmod>:
- 8000248: b953 cbnz r3, 8000260 <__aeabi_uldivmod+0x18>
- 800024a: b94a cbnz r2, 8000260 <__aeabi_uldivmod+0x18>
- 800024c: 2900 cmp r1, #0
- 800024e: bf08 it eq
- 8000250: 2800 cmpeq r0, #0
- 8000252: bf1c itt ne
- 8000254: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
- 8000258: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
- 800025c: f000 b972 b.w 8000544 <__aeabi_idiv0>
- 8000260: f1ad 0c08 sub.w ip, sp, #8
- 8000264: e96d ce04 strd ip, lr, [sp, #-16]!
- 8000268: f000 f806 bl 8000278 <__udivmoddi4>
- 800026c: f8dd e004 ldr.w lr, [sp, #4]
- 8000270: e9dd 2302 ldrd r2, r3, [sp, #8]
- 8000274: b004 add sp, #16
- 8000276: 4770 bx lr
-
-08000278 <__udivmoddi4>:
- 8000278: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 800027c: 9e08 ldr r6, [sp, #32]
- 800027e: 4604 mov r4, r0
- 8000280: 4688 mov r8, r1
- 8000282: 2b00 cmp r3, #0
- 8000284: d14b bne.n 800031e <__udivmoddi4+0xa6>
- 8000286: 428a cmp r2, r1
- 8000288: 4615 mov r5, r2
- 800028a: d967 bls.n 800035c <__udivmoddi4+0xe4>
- 800028c: fab2 f282 clz r2, r2
- 8000290: b14a cbz r2, 80002a6 <__udivmoddi4+0x2e>
- 8000292: f1c2 0720 rsb r7, r2, #32
- 8000296: fa01 f302 lsl.w r3, r1, r2
- 800029a: fa20 f707 lsr.w r7, r0, r7
- 800029e: 4095 lsls r5, r2
- 80002a0: ea47 0803 orr.w r8, r7, r3
- 80002a4: 4094 lsls r4, r2
- 80002a6: ea4f 4e15 mov.w lr, r5, lsr #16
- 80002aa: 0c23 lsrs r3, r4, #16
- 80002ac: fbb8 f7fe udiv r7, r8, lr
- 80002b0: fa1f fc85 uxth.w ip, r5
- 80002b4: fb0e 8817 mls r8, lr, r7, r8
- 80002b8: ea43 4308 orr.w r3, r3, r8, lsl #16
- 80002bc: fb07 f10c mul.w r1, r7, ip
- 80002c0: 4299 cmp r1, r3
- 80002c2: d909 bls.n 80002d8 <__udivmoddi4+0x60>
- 80002c4: 18eb adds r3, r5, r3
- 80002c6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
- 80002ca: f080 811b bcs.w 8000504 <__udivmoddi4+0x28c>
- 80002ce: 4299 cmp r1, r3
- 80002d0: f240 8118 bls.w 8000504 <__udivmoddi4+0x28c>
- 80002d4: 3f02 subs r7, #2
- 80002d6: 442b add r3, r5
- 80002d8: 1a5b subs r3, r3, r1
- 80002da: b2a4 uxth r4, r4
- 80002dc: fbb3 f0fe udiv r0, r3, lr
- 80002e0: fb0e 3310 mls r3, lr, r0, r3
- 80002e4: ea44 4403 orr.w r4, r4, r3, lsl #16
- 80002e8: fb00 fc0c mul.w ip, r0, ip
- 80002ec: 45a4 cmp ip, r4
- 80002ee: d909 bls.n 8000304 <__udivmoddi4+0x8c>
- 80002f0: 192c adds r4, r5, r4
- 80002f2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80002f6: f080 8107 bcs.w 8000508 <__udivmoddi4+0x290>
- 80002fa: 45a4 cmp ip, r4
- 80002fc: f240 8104 bls.w 8000508 <__udivmoddi4+0x290>
- 8000300: 3802 subs r0, #2
- 8000302: 442c add r4, r5
- 8000304: ea40 4007 orr.w r0, r0, r7, lsl #16
- 8000308: eba4 040c sub.w r4, r4, ip
- 800030c: 2700 movs r7, #0
- 800030e: b11e cbz r6, 8000318 <__udivmoddi4+0xa0>
- 8000310: 40d4 lsrs r4, r2
- 8000312: 2300 movs r3, #0
- 8000314: e9c6 4300 strd r4, r3, [r6]
- 8000318: 4639 mov r1, r7
- 800031a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 800031e: 428b cmp r3, r1
- 8000320: d909 bls.n 8000336 <__udivmoddi4+0xbe>
- 8000322: 2e00 cmp r6, #0
- 8000324: f000 80eb beq.w 80004fe <__udivmoddi4+0x286>
- 8000328: 2700 movs r7, #0
- 800032a: e9c6 0100 strd r0, r1, [r6]
- 800032e: 4638 mov r0, r7
- 8000330: 4639 mov r1, r7
- 8000332: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000336: fab3 f783 clz r7, r3
- 800033a: 2f00 cmp r7, #0
- 800033c: d147 bne.n 80003ce <__udivmoddi4+0x156>
- 800033e: 428b cmp r3, r1
- 8000340: d302 bcc.n 8000348 <__udivmoddi4+0xd0>
- 8000342: 4282 cmp r2, r0
- 8000344: f200 80fa bhi.w 800053c <__udivmoddi4+0x2c4>
- 8000348: 1a84 subs r4, r0, r2
- 800034a: eb61 0303 sbc.w r3, r1, r3
- 800034e: 2001 movs r0, #1
- 8000350: 4698 mov r8, r3
- 8000352: 2e00 cmp r6, #0
- 8000354: d0e0 beq.n 8000318 <__udivmoddi4+0xa0>
- 8000356: e9c6 4800 strd r4, r8, [r6]
- 800035a: e7dd b.n 8000318 <__udivmoddi4+0xa0>
- 800035c: b902 cbnz r2, 8000360 <__udivmoddi4+0xe8>
- 800035e: deff udf #255 ; 0xff
- 8000360: fab2 f282 clz r2, r2
- 8000364: 2a00 cmp r2, #0
- 8000366: f040 808f bne.w 8000488 <__udivmoddi4+0x210>
- 800036a: 1b49 subs r1, r1, r5
- 800036c: ea4f 4e15 mov.w lr, r5, lsr #16
- 8000370: fa1f f885 uxth.w r8, r5
- 8000374: 2701 movs r7, #1
- 8000376: fbb1 fcfe udiv ip, r1, lr
- 800037a: 0c23 lsrs r3, r4, #16
- 800037c: fb0e 111c mls r1, lr, ip, r1
- 8000380: ea43 4301 orr.w r3, r3, r1, lsl #16
- 8000384: fb08 f10c mul.w r1, r8, ip
- 8000388: 4299 cmp r1, r3
- 800038a: d907 bls.n 800039c <__udivmoddi4+0x124>
- 800038c: 18eb adds r3, r5, r3
- 800038e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
- 8000392: d202 bcs.n 800039a <__udivmoddi4+0x122>
- 8000394: 4299 cmp r1, r3
- 8000396: f200 80cd bhi.w 8000534 <__udivmoddi4+0x2bc>
- 800039a: 4684 mov ip, r0
- 800039c: 1a59 subs r1, r3, r1
- 800039e: b2a3 uxth r3, r4
- 80003a0: fbb1 f0fe udiv r0, r1, lr
- 80003a4: fb0e 1410 mls r4, lr, r0, r1
- 80003a8: ea43 4404 orr.w r4, r3, r4, lsl #16
- 80003ac: fb08 f800 mul.w r8, r8, r0
- 80003b0: 45a0 cmp r8, r4
- 80003b2: d907 bls.n 80003c4 <__udivmoddi4+0x14c>
- 80003b4: 192c adds r4, r5, r4
- 80003b6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80003ba: d202 bcs.n 80003c2 <__udivmoddi4+0x14a>
- 80003bc: 45a0 cmp r8, r4
- 80003be: f200 80b6 bhi.w 800052e <__udivmoddi4+0x2b6>
- 80003c2: 4618 mov r0, r3
- 80003c4: eba4 0408 sub.w r4, r4, r8
- 80003c8: ea40 400c orr.w r0, r0, ip, lsl #16
- 80003cc: e79f b.n 800030e <__udivmoddi4+0x96>
- 80003ce: f1c7 0c20 rsb ip, r7, #32
- 80003d2: 40bb lsls r3, r7
- 80003d4: fa22 fe0c lsr.w lr, r2, ip
- 80003d8: ea4e 0e03 orr.w lr, lr, r3
- 80003dc: fa01 f407 lsl.w r4, r1, r7
- 80003e0: fa20 f50c lsr.w r5, r0, ip
- 80003e4: fa21 f30c lsr.w r3, r1, ip
- 80003e8: ea4f 481e mov.w r8, lr, lsr #16
- 80003ec: 4325 orrs r5, r4
- 80003ee: fbb3 f9f8 udiv r9, r3, r8
- 80003f2: 0c2c lsrs r4, r5, #16
- 80003f4: fb08 3319 mls r3, r8, r9, r3
- 80003f8: fa1f fa8e uxth.w sl, lr
- 80003fc: ea44 4303 orr.w r3, r4, r3, lsl #16
- 8000400: fb09 f40a mul.w r4, r9, sl
- 8000404: 429c cmp r4, r3
- 8000406: fa02 f207 lsl.w r2, r2, r7
- 800040a: fa00 f107 lsl.w r1, r0, r7
- 800040e: d90b bls.n 8000428 <__udivmoddi4+0x1b0>
- 8000410: eb1e 0303 adds.w r3, lr, r3
- 8000414: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
- 8000418: f080 8087 bcs.w 800052a <__udivmoddi4+0x2b2>
- 800041c: 429c cmp r4, r3
- 800041e: f240 8084 bls.w 800052a <__udivmoddi4+0x2b2>
- 8000422: f1a9 0902 sub.w r9, r9, #2
- 8000426: 4473 add r3, lr
- 8000428: 1b1b subs r3, r3, r4
- 800042a: b2ad uxth r5, r5
- 800042c: fbb3 f0f8 udiv r0, r3, r8
- 8000430: fb08 3310 mls r3, r8, r0, r3
- 8000434: ea45 4403 orr.w r4, r5, r3, lsl #16
- 8000438: fb00 fa0a mul.w sl, r0, sl
- 800043c: 45a2 cmp sl, r4
- 800043e: d908 bls.n 8000452 <__udivmoddi4+0x1da>
- 8000440: eb1e 0404 adds.w r4, lr, r4
- 8000444: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 8000448: d26b bcs.n 8000522 <__udivmoddi4+0x2aa>
- 800044a: 45a2 cmp sl, r4
- 800044c: d969 bls.n 8000522 <__udivmoddi4+0x2aa>
- 800044e: 3802 subs r0, #2
- 8000450: 4474 add r4, lr
- 8000452: ea40 4009 orr.w r0, r0, r9, lsl #16
- 8000456: fba0 8902 umull r8, r9, r0, r2
- 800045a: eba4 040a sub.w r4, r4, sl
- 800045e: 454c cmp r4, r9
- 8000460: 46c2 mov sl, r8
- 8000462: 464b mov r3, r9
- 8000464: d354 bcc.n 8000510 <__udivmoddi4+0x298>
- 8000466: d051 beq.n 800050c <__udivmoddi4+0x294>
- 8000468: 2e00 cmp r6, #0
- 800046a: d069 beq.n 8000540 <__udivmoddi4+0x2c8>
- 800046c: ebb1 050a subs.w r5, r1, sl
- 8000470: eb64 0403 sbc.w r4, r4, r3
- 8000474: fa04 fc0c lsl.w ip, r4, ip
- 8000478: 40fd lsrs r5, r7
- 800047a: 40fc lsrs r4, r7
- 800047c: ea4c 0505 orr.w r5, ip, r5
- 8000480: e9c6 5400 strd r5, r4, [r6]
- 8000484: 2700 movs r7, #0
- 8000486: e747 b.n 8000318 <__udivmoddi4+0xa0>
- 8000488: f1c2 0320 rsb r3, r2, #32
- 800048c: fa20 f703 lsr.w r7, r0, r3
- 8000490: 4095 lsls r5, r2
- 8000492: fa01 f002 lsl.w r0, r1, r2
- 8000496: fa21 f303 lsr.w r3, r1, r3
- 800049a: ea4f 4e15 mov.w lr, r5, lsr #16
- 800049e: 4338 orrs r0, r7
- 80004a0: 0c01 lsrs r1, r0, #16
- 80004a2: fbb3 f7fe udiv r7, r3, lr
- 80004a6: fa1f f885 uxth.w r8, r5
- 80004aa: fb0e 3317 mls r3, lr, r7, r3
- 80004ae: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004b2: fb07 f308 mul.w r3, r7, r8
- 80004b6: 428b cmp r3, r1
- 80004b8: fa04 f402 lsl.w r4, r4, r2
- 80004bc: d907 bls.n 80004ce <__udivmoddi4+0x256>
- 80004be: 1869 adds r1, r5, r1
- 80004c0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
- 80004c4: d22f bcs.n 8000526 <__udivmoddi4+0x2ae>
- 80004c6: 428b cmp r3, r1
- 80004c8: d92d bls.n 8000526 <__udivmoddi4+0x2ae>
- 80004ca: 3f02 subs r7, #2
- 80004cc: 4429 add r1, r5
- 80004ce: 1acb subs r3, r1, r3
- 80004d0: b281 uxth r1, r0
- 80004d2: fbb3 f0fe udiv r0, r3, lr
- 80004d6: fb0e 3310 mls r3, lr, r0, r3
- 80004da: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004de: fb00 f308 mul.w r3, r0, r8
- 80004e2: 428b cmp r3, r1
- 80004e4: d907 bls.n 80004f6 <__udivmoddi4+0x27e>
- 80004e6: 1869 adds r1, r5, r1
- 80004e8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
- 80004ec: d217 bcs.n 800051e <__udivmoddi4+0x2a6>
- 80004ee: 428b cmp r3, r1
- 80004f0: d915 bls.n 800051e <__udivmoddi4+0x2a6>
- 80004f2: 3802 subs r0, #2
- 80004f4: 4429 add r1, r5
- 80004f6: 1ac9 subs r1, r1, r3
- 80004f8: ea40 4707 orr.w r7, r0, r7, lsl #16
- 80004fc: e73b b.n 8000376 <__udivmoddi4+0xfe>
- 80004fe: 4637 mov r7, r6
- 8000500: 4630 mov r0, r6
- 8000502: e709 b.n 8000318 <__udivmoddi4+0xa0>
- 8000504: 4607 mov r7, r0
- 8000506: e6e7 b.n 80002d8 <__udivmoddi4+0x60>
- 8000508: 4618 mov r0, r3
- 800050a: e6fb b.n 8000304 <__udivmoddi4+0x8c>
- 800050c: 4541 cmp r1, r8
- 800050e: d2ab bcs.n 8000468 <__udivmoddi4+0x1f0>
- 8000510: ebb8 0a02 subs.w sl, r8, r2
- 8000514: eb69 020e sbc.w r2, r9, lr
- 8000518: 3801 subs r0, #1
- 800051a: 4613 mov r3, r2
- 800051c: e7a4 b.n 8000468 <__udivmoddi4+0x1f0>
- 800051e: 4660 mov r0, ip
- 8000520: e7e9 b.n 80004f6 <__udivmoddi4+0x27e>
- 8000522: 4618 mov r0, r3
- 8000524: e795 b.n 8000452 <__udivmoddi4+0x1da>
- 8000526: 4667 mov r7, ip
- 8000528: e7d1 b.n 80004ce <__udivmoddi4+0x256>
- 800052a: 4681 mov r9, r0
- 800052c: e77c b.n 8000428 <__udivmoddi4+0x1b0>
- 800052e: 3802 subs r0, #2
- 8000530: 442c add r4, r5
- 8000532: e747 b.n 80003c4 <__udivmoddi4+0x14c>
- 8000534: f1ac 0c02 sub.w ip, ip, #2
- 8000538: 442b add r3, r5
- 800053a: e72f b.n 800039c <__udivmoddi4+0x124>
- 800053c: 4638 mov r0, r7
- 800053e: e708 b.n 8000352 <__udivmoddi4+0xda>
- 8000540: 4637 mov r7, r6
- 8000542: e6e9 b.n 8000318 <__udivmoddi4+0xa0>
-
-08000544 <__aeabi_idiv0>:
- 8000544: 4770 bx lr
- 8000546: bf00 nop
-
-08000548 <_ZN7EncoderC1EP17TIM_HandleTypeDef>:
- 8000548: b430 push {r4, r5}
- 800054a: 4d04 ldr r5, [pc, #16] ; (800055c <_ZN7EncoderC1EP17TIM_HandleTypeDef+0x14>)
- 800054c: 4c04 ldr r4, [pc, #16] ; (8000560 <_ZN7EncoderC1EP17TIM_HandleTypeDef+0x18>)
- 800054e: 4a05 ldr r2, [pc, #20] ; (8000564 <_ZN7EncoderC1EP17TIM_HandleTypeDef+0x1c>)
- 8000550: 6105 str r5, [r0, #16]
- 8000552: 6144 str r4, [r0, #20]
- 8000554: 6001 str r1, [r0, #0]
- 8000556: 6182 str r2, [r0, #24]
- 8000558: bc30 pop {r4, r5}
- 800055a: 4770 bx lr
- 800055c: 00012110 .word 0x00012110
- 8000560: 40490fd0 .word 0x40490fd0
- 8000564: 3f40ff97 .word 0x3f40ff97
-
-08000568 <_ZN7Encoder5SetupEv>:
- 8000568: b510 push {r4, lr}
- 800056a: 4604 mov r4, r0
- 800056c: 213c movs r1, #60 ; 0x3c
- 800056e: 6800 ldr r0, [r0, #0]
- 8000570: f007 f8ce bl 8007710 <HAL_TIM_Encoder_Start>
- 8000574: 6822 ldr r2, [r4, #0]
- 8000576: 2100 movs r1, #0
- 8000578: 68d3 ldr r3, [r2, #12]
- 800057a: 6812 ldr r2, [r2, #0]
- 800057c: 085b lsrs r3, r3, #1
- 800057e: 6253 str r3, [r2, #36] ; 0x24
- 8000580: 6061 str r1, [r4, #4]
- 8000582: f005 fde7 bl 8006154 <HAL_GetTick>
- 8000586: 60a0 str r0, [r4, #8]
- 8000588: bd10 pop {r4, pc}
- 800058a: bf00 nop
-
-0800058c <_ZN7Encoder17GetLinearVelocityEv>:
- 800058c: b538 push {r3, r4, r5, lr}
- 800058e: 6883 ldr r3, [r0, #8]
- 8000590: 4604 mov r4, r0
- 8000592: 6043 str r3, [r0, #4]
- 8000594: f005 fdde bl 8006154 <HAL_GetTick>
- 8000598: edd4 5a06 vldr s11, [r4, #24]
- 800059c: ed94 7a04 vldr s14, [r4, #16]
- 80005a0: ed9f 5a0f vldr s10, [pc, #60] ; 80005e0 <_ZN7Encoder17GetLinearVelocityEv+0x54>
- 80005a4: eeb8 7a47 vcvt.f32.u32 s14, s14
- 80005a8: e9d4 2300 ldrd r2, r3, [r4]
- 80005ac: 6815 ldr r5, [r2, #0]
- 80005ae: 1ac3 subs r3, r0, r3
- 80005b0: 68d2 ldr r2, [r2, #12]
- 80005b2: 6a69 ldr r1, [r5, #36] ; 0x24
- 80005b4: ee07 3a90 vmov s15, r3
- 80005b8: 0852 lsrs r2, r2, #1
- 80005ba: 60a0 str r0, [r4, #8]
- 80005bc: eef8 7a67 vcvt.f32.u32 s15, s15
- 80005c0: 1a89 subs r1, r1, r2
- 80005c2: ee06 1a90 vmov s13, r1
- 80005c6: ee87 6a85 vdiv.f32 s12, s15, s10
- 80005ca: 60e1 str r1, [r4, #12]
- 80005cc: 626a str r2, [r5, #36] ; 0x24
- 80005ce: eef8 6ae6 vcvt.f32.s32 s13, s13
- 80005d2: ee66 7aa5 vmul.f32 s15, s13, s11
- 80005d6: ee87 0a87 vdiv.f32 s0, s15, s14
- 80005da: ee80 0a06 vdiv.f32 s0, s0, s12
- 80005de: bd38 pop {r3, r4, r5, pc}
- 80005e0: 447a0000 .word 0x447a0000
-
-080005e4 <_ZN8std_msgs6String11deserializeEPh>:
- 80005e4: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80005e6: 788c ldrb r4, [r1, #2]
- 80005e8: 460d mov r5, r1
- 80005ea: 784a ldrb r2, [r1, #1]
- 80005ec: 1ccb adds r3, r1, #3
- 80005ee: 0424 lsls r4, r4, #16
- 80005f0: 78c9 ldrb r1, [r1, #3]
- 80005f2: 4606 mov r6, r0
- 80005f4: ea44 2402 orr.w r4, r4, r2, lsl #8
- 80005f8: 782a ldrb r2, [r5, #0]
- 80005fa: ea44 6401 orr.w r4, r4, r1, lsl #24
- 80005fe: 4314 orrs r4, r2
- 8000600: 1d27 adds r7, r4, #4
- 8000602: 2f04 cmp r7, #4
- 8000604: d905 bls.n 8000612 <_ZN8std_msgs6String11deserializeEPh+0x2e>
- 8000606: 4618 mov r0, r3
- 8000608: 4622 mov r2, r4
- 800060a: 1d29 adds r1, r5, #4
- 800060c: f009 fbb9 bl 8009d82 <memmove>
- 8000610: 4603 mov r3, r0
- 8000612: 442c add r4, r5
- 8000614: 2200 movs r2, #0
- 8000616: 4638 mov r0, r7
- 8000618: 70e2 strb r2, [r4, #3]
- 800061a: 6073 str r3, [r6, #4]
- 800061c: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 800061e: bf00 nop
-
-08000620 <_ZN8std_msgs6String7getTypeEv>:
- 8000620: 4800 ldr r0, [pc, #0] ; (8000624 <_ZN8std_msgs6String7getTypeEv+0x4>)
- 8000622: 4770 bx lr
- 8000624: 0800a480 .word 0x0800a480
-
-08000628 <_ZN8std_msgs6String6getMD5Ev>:
- 8000628: 4800 ldr r0, [pc, #0] ; (800062c <_ZN8std_msgs6String6getMD5Ev+0x4>)
- 800062a: 4770 bx lr
- 800062c: 0800a45c .word 0x0800a45c
-
-08000630 <_ZNK8std_msgs4Time9serializeEPh>:
- 8000630: 4603 mov r3, r0
- 8000632: 2008 movs r0, #8
- 8000634: 685a ldr r2, [r3, #4]
- 8000636: 700a strb r2, [r1, #0]
- 8000638: 685a ldr r2, [r3, #4]
- 800063a: 40c2 lsrs r2, r0
- 800063c: 704a strb r2, [r1, #1]
- 800063e: 88da ldrh r2, [r3, #6]
- 8000640: 708a strb r2, [r1, #2]
- 8000642: 79da ldrb r2, [r3, #7]
- 8000644: 70ca strb r2, [r1, #3]
- 8000646: 689a ldr r2, [r3, #8]
- 8000648: 710a strb r2, [r1, #4]
- 800064a: 689a ldr r2, [r3, #8]
- 800064c: 40c2 lsrs r2, r0
- 800064e: 714a strb r2, [r1, #5]
- 8000650: 895a ldrh r2, [r3, #10]
- 8000652: 718a strb r2, [r1, #6]
- 8000654: 7adb ldrb r3, [r3, #11]
- 8000656: 71cb strb r3, [r1, #7]
- 8000658: 4770 bx lr
- 800065a: bf00 nop
-
-0800065c <_ZN8std_msgs4Time11deserializeEPh>:
- 800065c: b410 push {r4}
- 800065e: 4602 mov r2, r0
- 8000660: 780b ldrb r3, [r1, #0]
- 8000662: 2008 movs r0, #8
- 8000664: 6053 str r3, [r2, #4]
- 8000666: 784c ldrb r4, [r1, #1]
- 8000668: ea43 2304 orr.w r3, r3, r4, lsl #8
- 800066c: 6053 str r3, [r2, #4]
- 800066e: 788c ldrb r4, [r1, #2]
- 8000670: ea43 4304 orr.w r3, r3, r4, lsl #16
- 8000674: 6053 str r3, [r2, #4]
- 8000676: 78cc ldrb r4, [r1, #3]
- 8000678: ea43 6304 orr.w r3, r3, r4, lsl #24
- 800067c: 6053 str r3, [r2, #4]
- 800067e: 790b ldrb r3, [r1, #4]
- 8000680: 6093 str r3, [r2, #8]
- 8000682: 794c ldrb r4, [r1, #5]
- 8000684: ea43 2304 orr.w r3, r3, r4, lsl #8
- 8000688: 6093 str r3, [r2, #8]
- 800068a: 798c ldrb r4, [r1, #6]
- 800068c: ea43 4304 orr.w r3, r3, r4, lsl #16
- 8000690: f85d 4b04 ldr.w r4, [sp], #4
- 8000694: 6093 str r3, [r2, #8]
- 8000696: 79c9 ldrb r1, [r1, #7]
- 8000698: ea43 6301 orr.w r3, r3, r1, lsl #24
- 800069c: 6093 str r3, [r2, #8]
- 800069e: 4770 bx lr
-
-080006a0 <_ZN8std_msgs4Time7getTypeEv>:
- 80006a0: 4800 ldr r0, [pc, #0] ; (80006a4 <_ZN8std_msgs4Time7getTypeEv+0x4>)
- 80006a2: 4770 bx lr
- 80006a4: 0800a418 .word 0x0800a418
-
-080006a8 <_ZN8std_msgs4Time6getMD5Ev>:
- 80006a8: 4800 ldr r0, [pc, #0] ; (80006ac <_ZN8std_msgs4Time6getMD5Ev+0x4>)
- 80006aa: 4770 bx lr
- 80006ac: 0800a3f4 .word 0x0800a3f4
-
-080006b0 <_ZN14rosserial_msgs9TopicInfo11deserializeEPh>:
- 80006b0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- 80006b4: 780a ldrb r2, [r1, #0]
- 80006b6: 460e mov r6, r1
- 80006b8: 1d4b adds r3, r1, #5
- 80006ba: 4607 mov r7, r0
- 80006bc: 8082 strh r2, [r0, #4]
- 80006be: 7849 ldrb r1, [r1, #1]
- 80006c0: ea42 2201 orr.w r2, r2, r1, lsl #8
- 80006c4: 8082 strh r2, [r0, #4]
- 80006c6: 7935 ldrb r5, [r6, #4]
- 80006c8: 78f1 ldrb r1, [r6, #3]
- 80006ca: 042d lsls r5, r5, #16
- 80006cc: 7972 ldrb r2, [r6, #5]
- 80006ce: 78b0 ldrb r0, [r6, #2]
- 80006d0: ea45 2501 orr.w r5, r5, r1, lsl #8
- 80006d4: ea45 6502 orr.w r5, r5, r2, lsl #24
- 80006d8: 4305 orrs r5, r0
- 80006da: f105 0906 add.w r9, r5, #6
- 80006de: f1b9 0f06 cmp.w r9, #6
- 80006e2: d905 bls.n 80006f0 <_ZN14rosserial_msgs9TopicInfo11deserializeEPh+0x40>
- 80006e4: 4618 mov r0, r3
- 80006e6: 462a mov r2, r5
- 80006e8: 1db1 adds r1, r6, #6
- 80006ea: f009 fb4a bl 8009d82 <memmove>
- 80006ee: 4603 mov r3, r0
- 80006f0: 1972 adds r2, r6, r5
- 80006f2: 2100 movs r1, #0
- 80006f4: f109 0804 add.w r8, r9, #4
- 80006f8: 7151 strb r1, [r2, #5]
- 80006fa: 60bb str r3, [r7, #8]
- 80006fc: 79d4 ldrb r4, [r2, #7]
- 80006fe: 7a11 ldrb r1, [r2, #8]
- 8000700: 0224 lsls r4, r4, #8
- 8000702: 7a53 ldrb r3, [r2, #9]
- 8000704: f816 0009 ldrb.w r0, [r6, r9]
- 8000708: ea44 4401 orr.w r4, r4, r1, lsl #16
- 800070c: ea44 6403 orr.w r4, r4, r3, lsl #24
- 8000710: 4304 orrs r4, r0
- 8000712: 4444 add r4, r8
- 8000714: 4544 cmp r4, r8
- 8000716: d90f bls.n 8000738 <_ZN14rosserial_msgs9TopicInfo11deserializeEPh+0x88>
- 8000718: 1b63 subs r3, r4, r5
- 800071a: f105 020b add.w r2, r5, #11
- 800071e: f105 010a add.w r1, r5, #10
- 8000722: f105 0009 add.w r0, r5, #9
- 8000726: 3b0a subs r3, #10
- 8000728: 4431 add r1, r6
- 800072a: 4430 add r0, r6
- 800072c: 4294 cmp r4, r2
- 800072e: bf2c ite cs
- 8000730: 461a movcs r2, r3
- 8000732: 2201 movcc r2, #1
- 8000734: f009 fb25 bl 8009d82 <memmove>
- 8000738: f108 33ff add.w r3, r8, #4294967295 ; 0xffffffff
- 800073c: 1932 adds r2, r6, r4
- 800073e: 2100 movs r1, #0
- 8000740: f104 0804 add.w r8, r4, #4
- 8000744: 4433 add r3, r6
- 8000746: f802 1c01 strb.w r1, [r2, #-1]
- 800074a: 60fb str r3, [r7, #12]
- 800074c: 7855 ldrb r5, [r2, #1]
- 800074e: 7893 ldrb r3, [r2, #2]
- 8000750: 022d lsls r5, r5, #8
- 8000752: 78d2 ldrb r2, [r2, #3]
- 8000754: ea45 4503 orr.w r5, r5, r3, lsl #16
- 8000758: 5d33 ldrb r3, [r6, r4]
- 800075a: ea45 6502 orr.w r5, r5, r2, lsl #24
- 800075e: 431d orrs r5, r3
- 8000760: 4445 add r5, r8
- 8000762: 45a8 cmp r8, r5
- 8000764: d20c bcs.n 8000780 <_ZN14rosserial_msgs9TopicInfo11deserializeEPh+0xd0>
- 8000766: 1b2b subs r3, r5, r4
- 8000768: 1d62 adds r2, r4, #5
- 800076a: 1ce0 adds r0, r4, #3
- 800076c: eb06 0108 add.w r1, r6, r8
- 8000770: 3b04 subs r3, #4
- 8000772: 4430 add r0, r6
- 8000774: 4295 cmp r5, r2
- 8000776: bf2c ite cs
- 8000778: 461a movcs r2, r3
- 800077a: 2201 movcc r2, #1
- 800077c: f009 fb01 bl 8009d82 <memmove>
- 8000780: f108 38ff add.w r8, r8, #4294967295 ; 0xffffffff
- 8000784: 1972 adds r2, r6, r5
- 8000786: 2100 movs r1, #0
- 8000788: 1d28 adds r0, r5, #4
- 800078a: eb06 0308 add.w r3, r6, r8
- 800078e: f802 1c01 strb.w r1, [r2, #-1]
- 8000792: 613b str r3, [r7, #16]
- 8000794: 7893 ldrb r3, [r2, #2]
- 8000796: 7854 ldrb r4, [r2, #1]
- 8000798: 041b lsls r3, r3, #16
- 800079a: 5d71 ldrb r1, [r6, r5]
- 800079c: 78d2 ldrb r2, [r2, #3]
- 800079e: ea43 2304 orr.w r3, r3, r4, lsl #8
- 80007a2: 430b orrs r3, r1
- 80007a4: ea43 6302 orr.w r3, r3, r2, lsl #24
- 80007a8: 617b str r3, [r7, #20]
- 80007aa: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
- 80007ae: bf00 nop
-
-080007b0 <_ZN14rosserial_msgs9TopicInfo7getTypeEv>:
- 80007b0: 4800 ldr r0, [pc, #0] ; (80007b4 <_ZN14rosserial_msgs9TopicInfo7getTypeEv+0x4>)
- 80007b2: 4770 bx lr
- 80007b4: 0800a348 .word 0x0800a348
-
-080007b8 <_ZN14rosserial_msgs9TopicInfo6getMD5Ev>:
- 80007b8: 4800 ldr r0, [pc, #0] ; (80007bc <_ZN14rosserial_msgs9TopicInfo6getMD5Ev+0x4>)
- 80007ba: 4770 bx lr
- 80007bc: 0800a324 .word 0x0800a324
-
-080007c0 <_ZN14rosserial_msgs3Log11deserializeEPh>:
- 80007c0: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80007c2: 460b mov r3, r1
- 80007c4: 460d mov r5, r1
- 80007c6: 4606 mov r6, r0
- 80007c8: f813 2b04 ldrb.w r2, [r3], #4
- 80007cc: 7102 strb r2, [r0, #4]
- 80007ce: 78cc ldrb r4, [r1, #3]
- 80007d0: 788a ldrb r2, [r1, #2]
- 80007d2: 0424 lsls r4, r4, #16
- 80007d4: 7909 ldrb r1, [r1, #4]
- 80007d6: ea44 2402 orr.w r4, r4, r2, lsl #8
- 80007da: 786a ldrb r2, [r5, #1]
- 80007dc: ea44 6401 orr.w r4, r4, r1, lsl #24
- 80007e0: 4314 orrs r4, r2
- 80007e2: 1d67 adds r7, r4, #5
- 80007e4: 2f05 cmp r7, #5
- 80007e6: d905 bls.n 80007f4 <_ZN14rosserial_msgs3Log11deserializeEPh+0x34>
- 80007e8: 4618 mov r0, r3
- 80007ea: 4622 mov r2, r4
- 80007ec: 1d69 adds r1, r5, #5
- 80007ee: f009 fac8 bl 8009d82 <memmove>
- 80007f2: 4603 mov r3, r0
- 80007f4: 442c add r4, r5
- 80007f6: 2200 movs r2, #0
- 80007f8: 4638 mov r0, r7
- 80007fa: 7122 strb r2, [r4, #4]
- 80007fc: 60b3 str r3, [r6, #8]
- 80007fe: bdf8 pop {r3, r4, r5, r6, r7, pc}
-
-08000800 <_ZN14rosserial_msgs3Log7getTypeEv>:
- 8000800: 4800 ldr r0, [pc, #0] ; (8000804 <_ZN14rosserial_msgs3Log7getTypeEv+0x4>)
- 8000802: 4770 bx lr
- 8000804: 0800a310 .word 0x0800a310
-
-08000808 <_ZN14rosserial_msgs3Log6getMD5Ev>:
- 8000808: 4800 ldr r0, [pc, #0] ; (800080c <_ZN14rosserial_msgs3Log6getMD5Ev+0x4>)
- 800080a: 4770 bx lr
- 800080c: 0800a2ec .word 0x0800a2ec
-
-08000810 <_ZN14rosserial_msgs20RequestParamResponse7getTypeEv>:
- 8000810: 4800 ldr r0, [pc, #0] ; (8000814 <_ZN14rosserial_msgs20RequestParamResponse7getTypeEv+0x4>)
- 8000812: 4770 bx lr
- 8000814: 0800a364 .word 0x0800a364
-
-08000818 <_ZN14rosserial_msgs20RequestParamResponse6getMD5Ev>:
- 8000818: 4800 ldr r0, [pc, #0] ; (800081c <_ZN14rosserial_msgs20RequestParamResponse6getMD5Ev+0x4>)
- 800081a: 4770 bx lr
- 800081c: 0800a2c8 .word 0x0800a2c8
-
-08000820 <_ZN8std_msgs6Header11deserializeEPh>:
- 8000820: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8000822: 780a ldrb r2, [r1, #0]
- 8000824: 460c mov r4, r1
- 8000826: f101 030f add.w r3, r1, #15
- 800082a: 4605 mov r5, r0
- 800082c: 6042 str r2, [r0, #4]
- 800082e: 7849 ldrb r1, [r1, #1]
- 8000830: ea42 2201 orr.w r2, r2, r1, lsl #8
- 8000834: 6042 str r2, [r0, #4]
- 8000836: 78a1 ldrb r1, [r4, #2]
- 8000838: ea42 4201 orr.w r2, r2, r1, lsl #16
- 800083c: 6042 str r2, [r0, #4]
- 800083e: 78e1 ldrb r1, [r4, #3]
- 8000840: ea42 6201 orr.w r2, r2, r1, lsl #24
- 8000844: 6042 str r2, [r0, #4]
- 8000846: 7922 ldrb r2, [r4, #4]
- 8000848: 6082 str r2, [r0, #8]
- 800084a: 7961 ldrb r1, [r4, #5]
- 800084c: ea42 2201 orr.w r2, r2, r1, lsl #8
- 8000850: 6082 str r2, [r0, #8]
- 8000852: 79a1 ldrb r1, [r4, #6]
- 8000854: ea42 4201 orr.w r2, r2, r1, lsl #16
- 8000858: 6082 str r2, [r0, #8]
- 800085a: 79e1 ldrb r1, [r4, #7]
- 800085c: ea42 6201 orr.w r2, r2, r1, lsl #24
- 8000860: 6082 str r2, [r0, #8]
- 8000862: 7a22 ldrb r2, [r4, #8]
- 8000864: 60c2 str r2, [r0, #12]
- 8000866: 7a61 ldrb r1, [r4, #9]
- 8000868: ea42 2201 orr.w r2, r2, r1, lsl #8
- 800086c: 60c2 str r2, [r0, #12]
- 800086e: 7aa1 ldrb r1, [r4, #10]
- 8000870: ea42 4201 orr.w r2, r2, r1, lsl #16
- 8000874: 60c2 str r2, [r0, #12]
- 8000876: 7ae1 ldrb r1, [r4, #11]
- 8000878: ea42 6201 orr.w r2, r2, r1, lsl #24
- 800087c: 60c2 str r2, [r0, #12]
- 800087e: 7ba6 ldrb r6, [r4, #14]
- 8000880: 7b62 ldrb r2, [r4, #13]
- 8000882: 0436 lsls r6, r6, #16
- 8000884: 7be1 ldrb r1, [r4, #15]
- 8000886: ea46 2602 orr.w r6, r6, r2, lsl #8
- 800088a: 7b22 ldrb r2, [r4, #12]
- 800088c: ea46 6601 orr.w r6, r6, r1, lsl #24
- 8000890: 4316 orrs r6, r2
- 8000892: f106 0710 add.w r7, r6, #16
- 8000896: 2f10 cmp r7, #16
- 8000898: d906 bls.n 80008a8 <_ZN8std_msgs6Header11deserializeEPh+0x88>
- 800089a: 4618 mov r0, r3
- 800089c: 4632 mov r2, r6
- 800089e: f104 0110 add.w r1, r4, #16
- 80008a2: f009 fa6e bl 8009d82 <memmove>
- 80008a6: 4603 mov r3, r0
- 80008a8: 4434 add r4, r6
- 80008aa: 2200 movs r2, #0
- 80008ac: 4638 mov r0, r7
- 80008ae: 73e2 strb r2, [r4, #15]
- 80008b0: 612b str r3, [r5, #16]
- 80008b2: bdf8 pop {r3, r4, r5, r6, r7, pc}
-
-080008b4 <_ZN8std_msgs6Header7getTypeEv>:
- 80008b4: 4800 ldr r0, [pc, #0] ; (80008b8 <_ZN8std_msgs6Header7getTypeEv+0x4>)
- 80008b6: 4770 bx lr
- 80008b8: 0800a44c .word 0x0800a44c
-
-080008bc <_ZN8std_msgs6Header6getMD5Ev>:
- 80008bc: 4800 ldr r0, [pc, #0] ; (80008c0 <_ZN8std_msgs6Header6getMD5Ev+0x4>)
- 80008be: 4770 bx lr
- 80008c0: 0800a428 .word 0x0800a428
-
-080008c4 <_ZN13geometry_msgs5Point7getTypeEv>:
- 80008c4: 4800 ldr r0, [pc, #0] ; (80008c8 <_ZN13geometry_msgs5Point7getTypeEv+0x4>)
- 80008c6: 4770 bx lr
- 80008c8: 0800a264 .word 0x0800a264
-
-080008cc <_ZN13geometry_msgs5Point6getMD5Ev>:
- 80008cc: 4800 ldr r0, [pc, #0] ; (80008d0 <_ZN13geometry_msgs5Point6getMD5Ev+0x4>)
- 80008ce: 4770 bx lr
- 80008d0: 0800a240 .word 0x0800a240
-
-080008d4 <_ZN13geometry_msgs10Quaternion7getTypeEv>:
- 80008d4: 4800 ldr r0, [pc, #0] ; (80008d8 <_ZN13geometry_msgs10Quaternion7getTypeEv+0x4>)
- 80008d6: 4770 bx lr
- 80008d8: 0800a15c .word 0x0800a15c
-
-080008dc <_ZN13geometry_msgs10Quaternion6getMD5Ev>:
- 80008dc: 4800 ldr r0, [pc, #0] ; (80008e0 <_ZN13geometry_msgs10Quaternion6getMD5Ev+0x4>)
- 80008de: 4770 bx lr
- 80008e0: 0800a138 .word 0x0800a138
-
-080008e4 <_ZN13geometry_msgs4Pose7getTypeEv>:
- 80008e4: 4800 ldr r0, [pc, #0] ; (80008e8 <_ZN13geometry_msgs4Pose7getTypeEv+0x4>)
- 80008e6: 4770 bx lr
- 80008e8: 0800a22c .word 0x0800a22c
-
-080008ec <_ZN13geometry_msgs4Pose6getMD5Ev>:
- 80008ec: 4800 ldr r0, [pc, #0] ; (80008f0 <_ZN13geometry_msgs4Pose6getMD5Ev+0x4>)
- 80008ee: 4770 bx lr
- 80008f0: 0800a208 .word 0x0800a208
-
-080008f4 <_ZN13geometry_msgs18PoseWithCovariance7getTypeEv>:
- 80008f4: 4800 ldr r0, [pc, #0] ; (80008f8 <_ZN13geometry_msgs18PoseWithCovariance7getTypeEv+0x4>)
- 80008f6: 4770 bx lr
- 80008f8: 0800a19c .word 0x0800a19c
-
-080008fc <_ZN13geometry_msgs18PoseWithCovariance6getMD5Ev>:
- 80008fc: 4800 ldr r0, [pc, #0] ; (8000900 <_ZN13geometry_msgs18PoseWithCovariance6getMD5Ev+0x4>)
- 80008fe: 4770 bx lr
- 8000900: 0800a178 .word 0x0800a178
-
-08000904 <_ZN13geometry_msgs7Vector37getTypeEv>:
- 8000904: 4800 ldr r0, [pc, #0] ; (8000908 <_ZN13geometry_msgs7Vector37getTypeEv+0x4>)
- 8000906: 4770 bx lr
- 8000908: 0800a2b0 .word 0x0800a2b0
-
-0800090c <_ZN13geometry_msgs7Vector36getMD5Ev>:
- 800090c: 4800 ldr r0, [pc, #0] ; (8000910 <_ZN13geometry_msgs7Vector36getMD5Ev+0x4>)
- 800090e: 4770 bx lr
- 8000910: 0800a240 .word 0x0800a240
-
-08000914 <_ZN13geometry_msgs5Twist7getTypeEv>:
- 8000914: 4800 ldr r0, [pc, #0] ; (8000918 <_ZN13geometry_msgs5Twist7getTypeEv+0x4>)
- 8000916: 4770 bx lr
- 8000918: 0800a29c .word 0x0800a29c
-
-0800091c <_ZN13geometry_msgs5Twist6getMD5Ev>:
- 800091c: 4800 ldr r0, [pc, #0] ; (8000920 <_ZN13geometry_msgs5Twist6getMD5Ev+0x4>)
- 800091e: 4770 bx lr
- 8000920: 0800a278 .word 0x0800a278
-
-08000924 <_ZN13geometry_msgs19TwistWithCovariance7getTypeEv>:
- 8000924: 4800 ldr r0, [pc, #0] ; (8000928 <_ZN13geometry_msgs19TwistWithCovariance7getTypeEv+0x4>)
- 8000926: 4770 bx lr
- 8000928: 0800a1e4 .word 0x0800a1e4
-
-0800092c <_ZN13geometry_msgs19TwistWithCovariance6getMD5Ev>:
- 800092c: 4800 ldr r0, [pc, #0] ; (8000930 <_ZN13geometry_msgs19TwistWithCovariance6getMD5Ev+0x4>)
- 800092e: 4770 bx lr
- 8000930: 0800a1c0 .word 0x0800a1c0
-
-08000934 <_ZN8nav_msgs8Odometry7getTypeEv>:
- 8000934: 4800 ldr r0, [pc, #0] ; (8000938 <_ZN8nav_msgs8Odometry7getTypeEv+0x4>)
- 8000936: 4770 bx lr
- 8000938: 0800a3e0 .word 0x0800a3e0
-
-0800093c <_ZN8nav_msgs8Odometry6getMD5Ev>:
- 800093c: 4800 ldr r0, [pc, #0] ; (8000940 <_ZN8nav_msgs8Odometry6getMD5Ev+0x4>)
- 800093e: 4770 bx lr
- 8000940: 0800a3bc .word 0x0800a3bc
-
-08000944 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE9connectedEv>:
- 8000944: f890 0680 ldrb.w r0, [r0, #1664] ; 0x680
- 8000948: 4770 bx lr
- 800094a: bf00 nop
-
-0800094c <_ZNK8std_msgs6Header9serializeEPh>:
- 800094c: 6843 ldr r3, [r0, #4]
- 800094e: b570 push {r4, r5, r6, lr}
- 8000950: 700b strb r3, [r1, #0]
- 8000952: 4605 mov r5, r0
- 8000954: 6843 ldr r3, [r0, #4]
- 8000956: 460c mov r4, r1
- 8000958: 0a1b lsrs r3, r3, #8
- 800095a: 704b strb r3, [r1, #1]
- 800095c: 88c3 ldrh r3, [r0, #6]
- 800095e: 708b strb r3, [r1, #2]
- 8000960: 79c3 ldrb r3, [r0, #7]
- 8000962: 70cb strb r3, [r1, #3]
- 8000964: 6883 ldr r3, [r0, #8]
- 8000966: 710b strb r3, [r1, #4]
- 8000968: 6883 ldr r3, [r0, #8]
- 800096a: 0a1b lsrs r3, r3, #8
- 800096c: 714b strb r3, [r1, #5]
- 800096e: 8943 ldrh r3, [r0, #10]
- 8000970: 718b strb r3, [r1, #6]
- 8000972: 7ac3 ldrb r3, [r0, #11]
- 8000974: 71cb strb r3, [r1, #7]
- 8000976: 68c3 ldr r3, [r0, #12]
- 8000978: 720b strb r3, [r1, #8]
- 800097a: 68c3 ldr r3, [r0, #12]
- 800097c: 0a1b lsrs r3, r3, #8
- 800097e: 724b strb r3, [r1, #9]
- 8000980: 89c3 ldrh r3, [r0, #14]
- 8000982: 728b strb r3, [r1, #10]
- 8000984: 7bc3 ldrb r3, [r0, #15]
- 8000986: 72cb strb r3, [r1, #11]
- 8000988: 6900 ldr r0, [r0, #16]
- 800098a: f7ff fc55 bl 8000238 <strlen>
- 800098e: 4606 mov r6, r0
- 8000990: f104 0010 add.w r0, r4, #16
- 8000994: 0a33 lsrs r3, r6, #8
- 8000996: 7326 strb r6, [r4, #12]
- 8000998: 0c32 lsrs r2, r6, #16
- 800099a: 7363 strb r3, [r4, #13]
- 800099c: 0e33 lsrs r3, r6, #24
- 800099e: 73a2 strb r2, [r4, #14]
- 80009a0: 4632 mov r2, r6
- 80009a2: 73e3 strb r3, [r4, #15]
- 80009a4: 6929 ldr r1, [r5, #16]
- 80009a6: f009 f9e1 bl 8009d6c <memcpy>
- 80009aa: f106 0010 add.w r0, r6, #16
- 80009ae: bd70 pop {r4, r5, r6, pc}
-
-080009b0 <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh>:
- 80009b0: 6843 ldr r3, [r0, #4]
- 80009b2: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 80009b6: 700b strb r3, [r1, #0]
- 80009b8: 6843 ldr r3, [r0, #4]
- 80009ba: 0a1b lsrs r3, r3, #8
- 80009bc: 704b strb r3, [r1, #1]
- 80009be: 88c3 ldrh r3, [r0, #6]
- 80009c0: 708b strb r3, [r1, #2]
- 80009c2: 79c3 ldrb r3, [r0, #7]
- 80009c4: 70cb strb r3, [r1, #3]
- 80009c6: 6843 ldr r3, [r0, #4]
- 80009c8: 2b00 cmp r3, #0
- 80009ca: f000 8089 beq.w 8000ae0 <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh+0x130>
- 80009ce: 460a mov r2, r1
- 80009d0: 2500 movs r5, #0
- 80009d2: 2704 movs r7, #4
- 80009d4: 68c3 ldr r3, [r0, #12]
- 80009d6: 1d3e adds r6, r7, #4
- 80009d8: 463c mov r4, r7
- 80009da: 3204 adds r2, #4
- 80009dc: f853 3025 ldr.w r3, [r3, r5, lsl #2]
- 80009e0: 3501 adds r5, #1
- 80009e2: 4637 mov r7, r6
- 80009e4: 7013 strb r3, [r2, #0]
- 80009e6: ea4f 2e13 mov.w lr, r3, lsr #8
- 80009ea: ea4f 4c13 mov.w ip, r3, lsr #16
- 80009ee: 0e1b lsrs r3, r3, #24
- 80009f0: f882 e001 strb.w lr, [r2, #1]
- 80009f4: f882 c002 strb.w ip, [r2, #2]
- 80009f8: 70d3 strb r3, [r2, #3]
- 80009fa: 6843 ldr r3, [r0, #4]
- 80009fc: 42ab cmp r3, r5
- 80009fe: d8e9 bhi.n 80009d4 <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh+0x24>
- 8000a00: f104 0508 add.w r5, r4, #8
- 8000a04: f104 0a05 add.w sl, r4, #5
- 8000a08: f104 0906 add.w r9, r4, #6
- 8000a0c: f104 0807 add.w r8, r4, #7
- 8000a10: f104 0e09 add.w lr, r4, #9
- 8000a14: f104 0c0a add.w ip, r4, #10
- 8000a18: f104 070b add.w r7, r4, #11
- 8000a1c: 462a mov r2, r5
- 8000a1e: 340c adds r4, #12
- 8000a20: 6903 ldr r3, [r0, #16]
- 8000a22: 558b strb r3, [r1, r6]
- 8000a24: 6903 ldr r3, [r0, #16]
- 8000a26: 0a1b lsrs r3, r3, #8
- 8000a28: f801 300a strb.w r3, [r1, sl]
- 8000a2c: 8a43 ldrh r3, [r0, #18]
- 8000a2e: f801 3009 strb.w r3, [r1, r9]
- 8000a32: 7cc3 ldrb r3, [r0, #19]
- 8000a34: f801 3008 strb.w r3, [r1, r8]
- 8000a38: 6903 ldr r3, [r0, #16]
- 8000a3a: b1fb cbz r3, 8000a7c <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh+0xcc>
- 8000a3c: 2700 movs r7, #0
- 8000a3e: 6983 ldr r3, [r0, #24]
- 8000a40: 2600 movs r6, #0
- 8000a42: 1d15 adds r5, r2, #4
- 8000a44: 4614 mov r4, r2
- 8000a46: f853 3027 ldr.w r3, [r3, r7, lsl #2]
- 8000a4a: 3701 adds r7, #1
- 8000a4c: f363 0607 bfi r6, r3, #0, #8
- 8000a50: ea4f 2e13 mov.w lr, r3, lsr #8
- 8000a54: ea4f 4c13 mov.w ip, r3, lsr #16
- 8000a58: f36e 260f bfi r6, lr, #8, #8
- 8000a5c: 0e1b lsrs r3, r3, #24
- 8000a5e: f36c 4617 bfi r6, ip, #16, #8
- 8000a62: f363 661f bfi r6, r3, #24, #8
- 8000a66: 508e str r6, [r1, r2]
- 8000a68: 462a mov r2, r5
- 8000a6a: 6903 ldr r3, [r0, #16]
- 8000a6c: 42bb cmp r3, r7
- 8000a6e: d8e6 bhi.n 8000a3e <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh+0x8e>
- 8000a70: f104 0e05 add.w lr, r4, #5
- 8000a74: f104 0c06 add.w ip, r4, #6
- 8000a78: 1de7 adds r7, r4, #7
- 8000a7a: 3408 adds r4, #8
- 8000a7c: 69c3 ldr r3, [r0, #28]
- 8000a7e: 554b strb r3, [r1, r5]
- 8000a80: 69c3 ldr r3, [r0, #28]
- 8000a82: 0a1b lsrs r3, r3, #8
- 8000a84: f801 300e strb.w r3, [r1, lr]
- 8000a88: 8bc3 ldrh r3, [r0, #30]
- 8000a8a: f801 300c strb.w r3, [r1, ip]
- 8000a8e: 7fc3 ldrb r3, [r0, #31]
- 8000a90: 55cb strb r3, [r1, r7]
- 8000a92: 69c3 ldr r3, [r0, #28]
- 8000a94: b30b cbz r3, 8000ada <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh+0x12a>
- 8000a96: 460f mov r7, r1
- 8000a98: 4606 mov r6, r0
- 8000a9a: 2500 movs r5, #0
- 8000a9c: 6a73 ldr r3, [r6, #36] ; 0x24
- 8000a9e: f104 0804 add.w r8, r4, #4
- 8000aa2: f853 0025 ldr.w r0, [r3, r5, lsl #2]
- 8000aa6: f7ff fbc7 bl 8000238 <strlen>
- 8000aaa: 4602 mov r2, r0
- 8000aac: 193b adds r3, r7, r4
- 8000aae: eb07 0008 add.w r0, r7, r8
- 8000ab2: 553a strb r2, [r7, r4]
- 8000ab4: 0e11 lsrs r1, r2, #24
- 8000ab6: 0c14 lsrs r4, r2, #16
- 8000ab8: ea4f 2c12 mov.w ip, r2, lsr #8
- 8000abc: 70d9 strb r1, [r3, #3]
- 8000abe: 709c strb r4, [r3, #2]
- 8000ac0: eb08 0402 add.w r4, r8, r2
- 8000ac4: f883 c001 strb.w ip, [r3, #1]
- 8000ac8: 6a73 ldr r3, [r6, #36] ; 0x24
- 8000aca: f853 1025 ldr.w r1, [r3, r5, lsl #2]
- 8000ace: 3501 adds r5, #1
- 8000ad0: f009 f94c bl 8009d6c <memcpy>
- 8000ad4: 69f3 ldr r3, [r6, #28]
- 8000ad6: 42ab cmp r3, r5
- 8000ad8: d8e0 bhi.n 8000a9c <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh+0xec>
- 8000ada: 4620 mov r0, r4
- 8000adc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000ae0: 2508 movs r5, #8
- 8000ae2: 240c movs r4, #12
- 8000ae4: 270b movs r7, #11
- 8000ae6: f04f 0c0a mov.w ip, #10
- 8000aea: 462a mov r2, r5
- 8000aec: f04f 0e09 mov.w lr, #9
- 8000af0: f04f 0807 mov.w r8, #7
- 8000af4: f04f 0906 mov.w r9, #6
- 8000af8: f04f 0a05 mov.w sl, #5
- 8000afc: 2604 movs r6, #4
- 8000afe: e78f b.n 8000a20 <_ZNK14rosserial_msgs20RequestParamResponse9serializeEPh+0x70>
-
-08000b00 <_ZNK14rosserial_msgs3Log9serializeEPh>:
- 8000b00: b570 push {r4, r5, r6, lr}
- 8000b02: 7903 ldrb r3, [r0, #4]
- 8000b04: 4605 mov r5, r0
- 8000b06: 460e mov r6, r1
- 8000b08: 700b strb r3, [r1, #0]
- 8000b0a: 6880 ldr r0, [r0, #8]
- 8000b0c: f7ff fb94 bl 8000238 <strlen>
- 8000b10: 2300 movs r3, #0
- 8000b12: 4604 mov r4, r0
- 8000b14: 1d70 adds r0, r6, #5
- 8000b16: 0a21 lsrs r1, r4, #8
- 8000b18: f364 0307 bfi r3, r4, #0, #8
- 8000b1c: 0c22 lsrs r2, r4, #16
- 8000b1e: f361 230f bfi r3, r1, #8, #8
- 8000b22: 0e21 lsrs r1, r4, #24
- 8000b24: f362 4317 bfi r3, r2, #16, #8
- 8000b28: 4622 mov r2, r4
- 8000b2a: f361 631f bfi r3, r1, #24, #8
- 8000b2e: f8c6 3001 str.w r3, [r6, #1]
- 8000b32: 68a9 ldr r1, [r5, #8]
- 8000b34: f009 f91a bl 8009d6c <memcpy>
- 8000b38: 1d60 adds r0, r4, #5
- 8000b3a: bd70 pop {r4, r5, r6, pc}
-
-08000b3c <_ZNK14rosserial_msgs9TopicInfo9serializeEPh>:
- 8000b3c: 8883 ldrh r3, [r0, #4]
- 8000b3e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
- 8000b42: 700b strb r3, [r1, #0]
- 8000b44: 4605 mov r5, r0
- 8000b46: 8883 ldrh r3, [r0, #4]
- 8000b48: 460c mov r4, r1
- 8000b4a: 0a1b lsrs r3, r3, #8
- 8000b4c: 704b strb r3, [r1, #1]
- 8000b4e: 6880 ldr r0, [r0, #8]
- 8000b50: f7ff fb72 bl 8000238 <strlen>
- 8000b54: 4602 mov r2, r0
- 8000b56: 1da0 adds r0, r4, #6
- 8000b58: 0a16 lsrs r6, r2, #8
- 8000b5a: 70a2 strb r2, [r4, #2]
- 8000b5c: 0c11 lsrs r1, r2, #16
- 8000b5e: 1d97 adds r7, r2, #6
- 8000b60: 0e13 lsrs r3, r2, #24
- 8000b62: 70e6 strb r6, [r4, #3]
- 8000b64: 7121 strb r1, [r4, #4]
- 8000b66: f102 080a add.w r8, r2, #10
- 8000b6a: 7163 strb r3, [r4, #5]
- 8000b6c: 68a9 ldr r1, [r5, #8]
- 8000b6e: f009 f8fd bl 8009d6c <memcpy>
- 8000b72: 68e8 ldr r0, [r5, #12]
- 8000b74: f7ff fb60 bl 8000238 <strlen>
- 8000b78: 2300 movs r3, #0
- 8000b7a: 4602 mov r2, r0
- 8000b7c: eb04 0008 add.w r0, r4, r8
- 8000b80: 0a11 lsrs r1, r2, #8
- 8000b82: f362 0307 bfi r3, r2, #0, #8
- 8000b86: 0c16 lsrs r6, r2, #16
- 8000b88: 4490 add r8, r2
- 8000b8a: f361 230f bfi r3, r1, #8, #8
- 8000b8e: 0e11 lsrs r1, r2, #24
- 8000b90: f366 4317 bfi r3, r6, #16, #8
- 8000b94: f108 0604 add.w r6, r8, #4
- 8000b98: f361 631f bfi r3, r1, #24, #8
- 8000b9c: 51e3 str r3, [r4, r7]
- 8000b9e: 68e9 ldr r1, [r5, #12]
- 8000ba0: f009 f8e4 bl 8009d6c <memcpy>
- 8000ba4: 6928 ldr r0, [r5, #16]
- 8000ba6: f7ff fb47 bl 8000238 <strlen>
- 8000baa: 2300 movs r3, #0
- 8000bac: 4607 mov r7, r0
- 8000bae: 19a0 adds r0, r4, r6
- 8000bb0: 0a39 lsrs r1, r7, #8
- 8000bb2: f367 0307 bfi r3, r7, #0, #8
- 8000bb6: 0c3a lsrs r2, r7, #16
- 8000bb8: f361 230f bfi r3, r1, #8, #8
- 8000bbc: 0e39 lsrs r1, r7, #24
- 8000bbe: f362 4317 bfi r3, r2, #16, #8
- 8000bc2: 463a mov r2, r7
- 8000bc4: f361 631f bfi r3, r1, #24, #8
- 8000bc8: f844 3008 str.w r3, [r4, r8]
- 8000bcc: 6929 ldr r1, [r5, #16]
- 8000bce: f009 f8cd bl 8009d6c <memcpy>
- 8000bd2: 696b ldr r3, [r5, #20]
- 8000bd4: 19f2 adds r2, r6, r7
- 8000bd6: 0a1d lsrs r5, r3, #8
- 8000bd8: 54a3 strb r3, [r4, r2]
- 8000bda: 18a1 adds r1, r4, r2
- 8000bdc: 1d10 adds r0, r2, #4
- 8000bde: 0c1a lsrs r2, r3, #16
- 8000be0: 0e1b lsrs r3, r3, #24
- 8000be2: 704d strb r5, [r1, #1]
- 8000be4: 708a strb r2, [r1, #2]
- 8000be6: 70cb strb r3, [r1, #3]
- 8000be8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
-
-08000bec <_ZNK8std_msgs6String9serializeEPh>:
- 8000bec: b570 push {r4, r5, r6, lr}
- 8000bee: 4606 mov r6, r0
- 8000bf0: 6840 ldr r0, [r0, #4]
- 8000bf2: 460d mov r5, r1
- 8000bf4: f7ff fb20 bl 8000238 <strlen>
- 8000bf8: 4604 mov r4, r0
- 8000bfa: 1d28 adds r0, r5, #4
- 8000bfc: 0a23 lsrs r3, r4, #8
- 8000bfe: 702c strb r4, [r5, #0]
- 8000c00: 0c22 lsrs r2, r4, #16
- 8000c02: 706b strb r3, [r5, #1]
- 8000c04: 0e23 lsrs r3, r4, #24
- 8000c06: 70aa strb r2, [r5, #2]
- 8000c08: 4622 mov r2, r4
- 8000c0a: 70eb strb r3, [r5, #3]
- 8000c0c: 6871 ldr r1, [r6, #4]
- 8000c0e: f009 f8ad bl 8009d6c <memcpy>
- 8000c12: 1d20 adds r0, r4, #4
- 8000c14: bd70 pop {r4, r5, r6, pc}
- 8000c16: bf00 nop
-
-08000c18 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh>:
- 8000c18: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 8000c1c: 6843 ldr r3, [r0, #4]
- 8000c1e: b083 sub sp, #12
- 8000c20: 680c ldr r4, [r1, #0]
- 8000c22: 4605 mov r5, r0
- 8000c24: 460e mov r6, r1
- 8000c26: 42a3 cmp r3, r4
- 8000c28: f0c0 80b4 bcc.w 8000d94 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x17c>
- 8000c2c: 606c str r4, [r5, #4]
- 8000c2e: 2c00 cmp r4, #0
- 8000c30: f000 80b9 beq.w 8000da6 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x18e>
- 8000c34: 4630 mov r0, r6
- 8000c36: 2400 movs r4, #0
- 8000c38: 2704 movs r7, #4
- 8000c3a: 7983 ldrb r3, [r0, #6]
- 8000c3c: 1d3a adds r2, r7, #4
- 8000c3e: 7941 ldrb r1, [r0, #5]
- 8000c40: 46ba mov sl, r7
- 8000c42: 041b lsls r3, r3, #16
- 8000c44: f890 e004 ldrb.w lr, [r0, #4]
- 8000c48: f890 c007 ldrb.w ip, [r0, #7]
- 8000c4c: 4617 mov r7, r2
- 8000c4e: ea43 2301 orr.w r3, r3, r1, lsl #8
- 8000c52: 68e9 ldr r1, [r5, #12]
- 8000c54: 3004 adds r0, #4
- 8000c56: ea43 030e orr.w r3, r3, lr
- 8000c5a: ea43 630c orr.w r3, r3, ip, lsl #24
- 8000c5e: 60ab str r3, [r5, #8]
- 8000c60: f841 3024 str.w r3, [r1, r4, lsl #2]
- 8000c64: 3401 adds r4, #1
- 8000c66: 686b ldr r3, [r5, #4]
- 8000c68: 42a3 cmp r3, r4
- 8000c6a: d8e6 bhi.n 8000c3a <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x22>
- 8000c6c: f10a 0708 add.w r7, sl, #8
- 8000c70: f10a 0005 add.w r0, sl, #5
- 8000c74: f10a 0306 add.w r3, sl, #6
- 8000c78: f10a 0107 add.w r1, sl, #7
- 8000c7c: f10a 0909 add.w r9, sl, #9
- 8000c80: f10a 0b0a add.w fp, sl, #10
- 8000c84: f10a 080b add.w r8, sl, #11
- 8000c88: 463c mov r4, r7
- 8000c8a: f10a 0a0c add.w sl, sl, #12
- 8000c8e: 5cf3 ldrb r3, [r6, r3]
- 8000c90: f816 c000 ldrb.w ip, [r6, r0]
- 8000c94: 041b lsls r3, r3, #16
- 8000c96: 5cb0 ldrb r0, [r6, r2]
- 8000c98: 5c71 ldrb r1, [r6, r1]
- 8000c9a: ea43 230c orr.w r3, r3, ip, lsl #8
- 8000c9e: 692a ldr r2, [r5, #16]
- 8000ca0: 4303 orrs r3, r0
- 8000ca2: ea43 6301 orr.w r3, r3, r1, lsl #24
- 8000ca6: 429a cmp r2, r3
- 8000ca8: f0c0 8092 bcc.w 8000dd0 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x1b8>
- 8000cac: 612b str r3, [r5, #16]
- 8000cae: b313 cbz r3, 8000cf6 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0xde>
- 8000cb0: 1931 adds r1, r6, r4
- 8000cb2: 2000 movs r0, #0
- 8000cb4: 788b ldrb r3, [r1, #2]
- 8000cb6: 1d27 adds r7, r4, #4
- 8000cb8: 784a ldrb r2, [r1, #1]
- 8000cba: 46a2 mov sl, r4
- 8000cbc: 041b lsls r3, r3, #16
- 8000cbe: f891 e000 ldrb.w lr, [r1]
- 8000cc2: f891 c003 ldrb.w ip, [r1, #3]
- 8000cc6: 463c mov r4, r7
- 8000cc8: ea43 2302 orr.w r3, r3, r2, lsl #8
- 8000ccc: 69aa ldr r2, [r5, #24]
- 8000cce: 3104 adds r1, #4
- 8000cd0: ea43 030e orr.w r3, r3, lr
- 8000cd4: ea43 630c orr.w r3, r3, ip, lsl #24
- 8000cd8: 616b str r3, [r5, #20]
- 8000cda: f842 3020 str.w r3, [r2, r0, lsl #2]
- 8000cde: 3001 adds r0, #1
- 8000ce0: 692b ldr r3, [r5, #16]
- 8000ce2: 4283 cmp r3, r0
- 8000ce4: d8e6 bhi.n 8000cb4 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x9c>
- 8000ce6: f10a 0905 add.w r9, sl, #5
- 8000cea: f10a 0b06 add.w fp, sl, #6
- 8000cee: f10a 0807 add.w r8, sl, #7
- 8000cf2: f10a 0a08 add.w sl, sl, #8
- 8000cf6: f816 400b ldrb.w r4, [r6, fp]
- 8000cfa: f816 3009 ldrb.w r3, [r6, r9]
- 8000cfe: 0424 lsls r4, r4, #16
- 8000d00: 5df1 ldrb r1, [r6, r7]
- 8000d02: f816 2008 ldrb.w r2, [r6, r8]
- 8000d06: ea44 2403 orr.w r4, r4, r3, lsl #8
- 8000d0a: 69eb ldr r3, [r5, #28]
- 8000d0c: 430c orrs r4, r1
- 8000d0e: ea44 6402 orr.w r4, r4, r2, lsl #24
- 8000d12: 42a3 cmp r3, r4
- 8000d14: d356 bcc.n 8000dc4 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x1ac>
- 8000d16: 61ec str r4, [r5, #28]
- 8000d18: 2c00 cmp r4, #0
- 8000d1a: d037 beq.n 8000d8c <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x174>
- 8000d1c: f04f 0900 mov.w r9, #0
- 8000d20: f06f 0803 mvn.w r8, #3
- 8000d24: 464f mov r7, r9
- 8000d26: eb06 020a add.w r2, r6, sl
- 8000d2a: f10a 0003 add.w r0, sl, #3
- 8000d2e: f816 e00a ldrb.w lr, [r6, sl]
- 8000d32: f10a 0b04 add.w fp, sl, #4
- 8000d36: 7894 ldrb r4, [r2, #2]
- 8000d38: eba8 030a sub.w r3, r8, sl
- 8000d3c: 7852 ldrb r2, [r2, #1]
- 8000d3e: f10a 0c05 add.w ip, sl, #5
- 8000d42: 0424 lsls r4, r4, #16
- 8000d44: eb06 010b add.w r1, r6, fp
- 8000d48: ea44 2402 orr.w r4, r4, r2, lsl #8
- 8000d4c: 5c32 ldrb r2, [r6, r0]
- 8000d4e: 4430 add r0, r6
- 8000d50: ea44 040e orr.w r4, r4, lr
- 8000d54: ea44 6402 orr.w r4, r4, r2, lsl #24
- 8000d58: 445c add r4, fp
- 8000d5a: 45a3 cmp fp, r4
- 8000d5c: 4423 add r3, r4
- 8000d5e: 46a2 mov sl, r4
- 8000d60: d205 bcs.n 8000d6e <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x156>
- 8000d62: 45a4 cmp ip, r4
- 8000d64: bf94 ite ls
- 8000d66: 461a movls r2, r3
- 8000d68: 2201 movhi r2, #1
- 8000d6a: f009 f80a bl 8009d82 <memmove>
- 8000d6e: 4434 add r4, r6
- 8000d70: f10b 33ff add.w r3, fp, #4294967295 ; 0xffffffff
- 8000d74: f804 7c01 strb.w r7, [r4, #-1]
- 8000d78: 4433 add r3, r6
- 8000d7a: 6a6a ldr r2, [r5, #36] ; 0x24
- 8000d7c: 622b str r3, [r5, #32]
- 8000d7e: f842 3029 str.w r3, [r2, r9, lsl #2]
- 8000d82: f109 0901 add.w r9, r9, #1
- 8000d86: 69eb ldr r3, [r5, #28]
- 8000d88: 454b cmp r3, r9
- 8000d8a: d8cc bhi.n 8000d26 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x10e>
- 8000d8c: 4650 mov r0, sl
- 8000d8e: b003 add sp, #12
- 8000d90: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 8000d94: 00a1 lsls r1, r4, #2
- 8000d96: 68c0 ldr r0, [r0, #12]
- 8000d98: f009 f814 bl 8009dc4 <realloc>
- 8000d9c: 606c str r4, [r5, #4]
- 8000d9e: 60e8 str r0, [r5, #12]
- 8000da0: 2c00 cmp r4, #0
- 8000da2: f47f af47 bne.w 8000c34 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x1c>
- 8000da6: 2708 movs r7, #8
- 8000da8: f04f 0a0c mov.w sl, #12
- 8000dac: f04f 080b mov.w r8, #11
- 8000db0: f04f 0b0a mov.w fp, #10
- 8000db4: 463c mov r4, r7
- 8000db6: f04f 0909 mov.w r9, #9
- 8000dba: 2107 movs r1, #7
- 8000dbc: 2306 movs r3, #6
- 8000dbe: 2005 movs r0, #5
- 8000dc0: 2204 movs r2, #4
- 8000dc2: e764 b.n 8000c8e <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x76>
- 8000dc4: 00a1 lsls r1, r4, #2
- 8000dc6: 6a68 ldr r0, [r5, #36] ; 0x24
- 8000dc8: f008 fffc bl 8009dc4 <realloc>
- 8000dcc: 6268 str r0, [r5, #36] ; 0x24
- 8000dce: e7a2 b.n 8000d16 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0xfe>
- 8000dd0: 0099 lsls r1, r3, #2
- 8000dd2: 69a8 ldr r0, [r5, #24]
- 8000dd4: 9301 str r3, [sp, #4]
- 8000dd6: f008 fff5 bl 8009dc4 <realloc>
- 8000dda: 9b01 ldr r3, [sp, #4]
- 8000ddc: 61a8 str r0, [r5, #24]
- 8000dde: e765 b.n 8000cac <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh+0x94>
-
-08000de0 <_ZNK13geometry_msgs5Twist9serializeEPh>:
- 8000de0: edd0 7a02 vldr s15, [r0, #8]
- 8000de4: ee17 3a90 vmov r3, s15
- 8000de8: f3c3 52c7 ubfx r2, r3, #23, #8
- 8000dec: b4f0 push {r4, r5, r6, r7}
- 8000dee: 2a00 cmp r2, #0
- 8000df0: f000 80e5 beq.w 8000fbe <_ZNK13geometry_msgs5Twist9serializeEPh+0x1de>
- 8000df4: f502 7260 add.w r2, r2, #896 ; 0x380
- 8000df8: 0114 lsls r4, r2, #4
- 8000dfa: 0912 lsrs r2, r2, #4
- 8000dfc: b264 sxtb r4, r4
- 8000dfe: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8000e02: f3c3 46c3 ubfx r6, r3, #19, #4
- 8000e06: 2500 movs r5, #0
- 8000e08: 015f lsls r7, r3, #5
- 8000e0a: 4334 orrs r4, r6
- 8000e0c: 10de asrs r6, r3, #3
- 8000e0e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8000e12: ea4f 23e3 mov.w r3, r3, asr #11
- 8000e16: 700d strb r5, [r1, #0]
- 8000e18: 714b strb r3, [r1, #5]
- 8000e1a: bf48 it mi
- 8000e1c: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8000e20: 718c strb r4, [r1, #6]
- 8000e22: 704d strb r5, [r1, #1]
- 8000e24: 71ca strb r2, [r1, #7]
- 8000e26: 708d strb r5, [r1, #2]
- 8000e28: 70cf strb r7, [r1, #3]
- 8000e2a: 710e strb r6, [r1, #4]
- 8000e2c: edd0 7a03 vldr s15, [r0, #12]
- 8000e30: ee17 3a90 vmov r3, s15
- 8000e34: f3c3 52c7 ubfx r2, r3, #23, #8
- 8000e38: 2a00 cmp r2, #0
- 8000e3a: f000 80ca beq.w 8000fd2 <_ZNK13geometry_msgs5Twist9serializeEPh+0x1f2>
- 8000e3e: f502 7260 add.w r2, r2, #896 ; 0x380
- 8000e42: 0114 lsls r4, r2, #4
- 8000e44: 0912 lsrs r2, r2, #4
- 8000e46: b264 sxtb r4, r4
- 8000e48: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8000e4c: f3c3 46c3 ubfx r6, r3, #19, #4
- 8000e50: 2500 movs r5, #0
- 8000e52: 015f lsls r7, r3, #5
- 8000e54: 4334 orrs r4, r6
- 8000e56: 10de asrs r6, r3, #3
- 8000e58: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8000e5c: ea4f 23e3 mov.w r3, r3, asr #11
- 8000e60: 720d strb r5, [r1, #8]
- 8000e62: 734b strb r3, [r1, #13]
- 8000e64: bf48 it mi
- 8000e66: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8000e6a: 738c strb r4, [r1, #14]
- 8000e6c: 724d strb r5, [r1, #9]
- 8000e6e: 73ca strb r2, [r1, #15]
- 8000e70: 728d strb r5, [r1, #10]
- 8000e72: 72cf strb r7, [r1, #11]
- 8000e74: 730e strb r6, [r1, #12]
- 8000e76: edd0 7a04 vldr s15, [r0, #16]
- 8000e7a: ee17 3a90 vmov r3, s15
- 8000e7e: f3c3 52c7 ubfx r2, r3, #23, #8
- 8000e82: 2a00 cmp r2, #0
- 8000e84: f000 80a3 beq.w 8000fce <_ZNK13geometry_msgs5Twist9serializeEPh+0x1ee>
- 8000e88: f502 7260 add.w r2, r2, #896 ; 0x380
- 8000e8c: 0114 lsls r4, r2, #4
- 8000e8e: 0912 lsrs r2, r2, #4
- 8000e90: b264 sxtb r4, r4
- 8000e92: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8000e96: f3c3 46c3 ubfx r6, r3, #19, #4
- 8000e9a: 2500 movs r5, #0
- 8000e9c: 015f lsls r7, r3, #5
- 8000e9e: 4334 orrs r4, r6
- 8000ea0: 10de asrs r6, r3, #3
- 8000ea2: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8000ea6: ea4f 23e3 mov.w r3, r3, asr #11
- 8000eaa: 740d strb r5, [r1, #16]
- 8000eac: 754b strb r3, [r1, #21]
- 8000eae: bf48 it mi
- 8000eb0: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8000eb4: 758c strb r4, [r1, #22]
- 8000eb6: 744d strb r5, [r1, #17]
- 8000eb8: 75ca strb r2, [r1, #23]
- 8000eba: 748d strb r5, [r1, #18]
- 8000ebc: 74cf strb r7, [r1, #19]
- 8000ebe: 750e strb r6, [r1, #20]
- 8000ec0: edd0 7a06 vldr s15, [r0, #24]
- 8000ec4: ee17 3a90 vmov r3, s15
- 8000ec8: f3c3 52c7 ubfx r2, r3, #23, #8
- 8000ecc: 2a00 cmp r2, #0
- 8000ece: d07c beq.n 8000fca <_ZNK13geometry_msgs5Twist9serializeEPh+0x1ea>
- 8000ed0: f502 7260 add.w r2, r2, #896 ; 0x380
- 8000ed4: 0114 lsls r4, r2, #4
- 8000ed6: 0912 lsrs r2, r2, #4
- 8000ed8: b264 sxtb r4, r4
- 8000eda: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8000ede: f3c3 46c3 ubfx r6, r3, #19, #4
- 8000ee2: 2500 movs r5, #0
- 8000ee4: 015f lsls r7, r3, #5
- 8000ee6: 4334 orrs r4, r6
- 8000ee8: 10de asrs r6, r3, #3
- 8000eea: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8000eee: ea4f 23e3 mov.w r3, r3, asr #11
- 8000ef2: 760d strb r5, [r1, #24]
- 8000ef4: 774b strb r3, [r1, #29]
- 8000ef6: bf48 it mi
- 8000ef8: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8000efc: 778c strb r4, [r1, #30]
- 8000efe: 764d strb r5, [r1, #25]
- 8000f00: 77ca strb r2, [r1, #31]
- 8000f02: 768d strb r5, [r1, #26]
- 8000f04: 76cf strb r7, [r1, #27]
- 8000f06: 770e strb r6, [r1, #28]
- 8000f08: edd0 7a07 vldr s15, [r0, #28]
- 8000f0c: ee17 3a90 vmov r3, s15
- 8000f10: f3c3 52c7 ubfx r2, r3, #23, #8
- 8000f14: 2a00 cmp r2, #0
- 8000f16: d056 beq.n 8000fc6 <_ZNK13geometry_msgs5Twist9serializeEPh+0x1e6>
- 8000f18: f502 7260 add.w r2, r2, #896 ; 0x380
- 8000f1c: 0114 lsls r4, r2, #4
- 8000f1e: 0912 lsrs r2, r2, #4
- 8000f20: b264 sxtb r4, r4
- 8000f22: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8000f26: f3c3 46c3 ubfx r6, r3, #19, #4
- 8000f2a: 2500 movs r5, #0
- 8000f2c: 015f lsls r7, r3, #5
- 8000f2e: 4334 orrs r4, r6
- 8000f30: 10de asrs r6, r3, #3
- 8000f32: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8000f36: ea4f 23e3 mov.w r3, r3, asr #11
- 8000f3a: f881 5020 strb.w r5, [r1, #32]
- 8000f3e: f881 3025 strb.w r3, [r1, #37] ; 0x25
- 8000f42: bf48 it mi
- 8000f44: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8000f48: f881 4026 strb.w r4, [r1, #38] ; 0x26
- 8000f4c: f881 5021 strb.w r5, [r1, #33] ; 0x21
- 8000f50: f881 2027 strb.w r2, [r1, #39] ; 0x27
- 8000f54: f881 5022 strb.w r5, [r1, #34] ; 0x22
- 8000f58: f881 7023 strb.w r7, [r1, #35] ; 0x23
- 8000f5c: f881 6024 strb.w r6, [r1, #36] ; 0x24
- 8000f60: edd0 7a08 vldr s15, [r0, #32]
- 8000f64: ee17 3a90 vmov r3, s15
- 8000f68: f3c3 52c7 ubfx r2, r3, #23, #8
- 8000f6c: b34a cbz r2, 8000fc2 <_ZNK13geometry_msgs5Twist9serializeEPh+0x1e2>
- 8000f6e: f502 7260 add.w r2, r2, #896 ; 0x380
- 8000f72: 0110 lsls r0, r2, #4
- 8000f74: 0912 lsrs r2, r2, #4
- 8000f76: b240 sxtb r0, r0
- 8000f78: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8000f7c: f3c3 45c3 ubfx r5, r3, #19, #4
- 8000f80: 2400 movs r4, #0
- 8000f82: 015e lsls r6, r3, #5
- 8000f84: 4328 orrs r0, r5
- 8000f86: 10dd asrs r5, r3, #3
- 8000f88: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8000f8c: ea4f 23e3 mov.w r3, r3, asr #11
- 8000f90: f881 4028 strb.w r4, [r1, #40] ; 0x28
- 8000f94: f881 002e strb.w r0, [r1, #46] ; 0x2e
- 8000f98: f04f 0030 mov.w r0, #48 ; 0x30
- 8000f9c: bf48 it mi
- 8000f9e: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8000fa2: f881 4029 strb.w r4, [r1, #41] ; 0x29
- 8000fa6: f881 402a strb.w r4, [r1, #42] ; 0x2a
- 8000faa: f881 602b strb.w r6, [r1, #43] ; 0x2b
- 8000fae: f881 502c strb.w r5, [r1, #44] ; 0x2c
- 8000fb2: f881 302d strb.w r3, [r1, #45] ; 0x2d
- 8000fb6: f881 202f strb.w r2, [r1, #47] ; 0x2f
- 8000fba: bcf0 pop {r4, r5, r6, r7}
- 8000fbc: 4770 bx lr
- 8000fbe: 4614 mov r4, r2
- 8000fc0: e71d b.n 8000dfe <_ZNK13geometry_msgs5Twist9serializeEPh+0x1e>
- 8000fc2: 4610 mov r0, r2
- 8000fc4: e7d8 b.n 8000f78 <_ZNK13geometry_msgs5Twist9serializeEPh+0x198>
- 8000fc6: 4614 mov r4, r2
- 8000fc8: e7ab b.n 8000f22 <_ZNK13geometry_msgs5Twist9serializeEPh+0x142>
- 8000fca: 4614 mov r4, r2
- 8000fcc: e785 b.n 8000eda <_ZNK13geometry_msgs5Twist9serializeEPh+0xfa>
- 8000fce: 4614 mov r4, r2
- 8000fd0: e75f b.n 8000e92 <_ZNK13geometry_msgs5Twist9serializeEPh+0xb2>
- 8000fd2: 4614 mov r4, r2
- 8000fd4: e738 b.n 8000e48 <_ZNK13geometry_msgs5Twist9serializeEPh+0x68>
- 8000fd6: bf00 nop
-
-08000fd8 <_ZNK13geometry_msgs4Pose9serializeEPh>:
- 8000fd8: edd0 7a02 vldr s15, [r0, #8]
- 8000fdc: ee17 3a90 vmov r3, s15
- 8000fe0: f3c3 52c7 ubfx r2, r3, #23, #8
- 8000fe4: b4f0 push {r4, r5, r6, r7}
- 8000fe6: 2a00 cmp r2, #0
- 8000fe8: f000 8113 beq.w 8001212 <_ZNK13geometry_msgs4Pose9serializeEPh+0x23a>
- 8000fec: f502 7260 add.w r2, r2, #896 ; 0x380
- 8000ff0: 0114 lsls r4, r2, #4
- 8000ff2: 0912 lsrs r2, r2, #4
- 8000ff4: b264 sxtb r4, r4
- 8000ff6: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8000ffa: f3c3 46c3 ubfx r6, r3, #19, #4
- 8000ffe: 2500 movs r5, #0
- 8001000: 015f lsls r7, r3, #5
- 8001002: 4334 orrs r4, r6
- 8001004: 10de asrs r6, r3, #3
- 8001006: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800100a: ea4f 23e3 mov.w r3, r3, asr #11
- 800100e: 700d strb r5, [r1, #0]
- 8001010: 714b strb r3, [r1, #5]
- 8001012: bf48 it mi
- 8001014: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001018: 718c strb r4, [r1, #6]
- 800101a: 704d strb r5, [r1, #1]
- 800101c: 71ca strb r2, [r1, #7]
- 800101e: 708d strb r5, [r1, #2]
- 8001020: 70cf strb r7, [r1, #3]
- 8001022: 710e strb r6, [r1, #4]
- 8001024: edd0 7a03 vldr s15, [r0, #12]
- 8001028: ee17 3a90 vmov r3, s15
- 800102c: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001030: 2a00 cmp r2, #0
- 8001032: f000 80fa beq.w 800122a <_ZNK13geometry_msgs4Pose9serializeEPh+0x252>
- 8001036: f502 7260 add.w r2, r2, #896 ; 0x380
- 800103a: 0114 lsls r4, r2, #4
- 800103c: 0912 lsrs r2, r2, #4
- 800103e: b264 sxtb r4, r4
- 8001040: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001044: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001048: 2500 movs r5, #0
- 800104a: 015f lsls r7, r3, #5
- 800104c: 4334 orrs r4, r6
- 800104e: 10de asrs r6, r3, #3
- 8001050: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001054: ea4f 23e3 mov.w r3, r3, asr #11
- 8001058: 720d strb r5, [r1, #8]
- 800105a: 734b strb r3, [r1, #13]
- 800105c: bf48 it mi
- 800105e: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001062: 738c strb r4, [r1, #14]
- 8001064: 724d strb r5, [r1, #9]
- 8001066: 73ca strb r2, [r1, #15]
- 8001068: 728d strb r5, [r1, #10]
- 800106a: 72cf strb r7, [r1, #11]
- 800106c: 730e strb r6, [r1, #12]
- 800106e: edd0 7a04 vldr s15, [r0, #16]
- 8001072: ee17 3a90 vmov r3, s15
- 8001076: f3c3 52c7 ubfx r2, r3, #23, #8
- 800107a: 2a00 cmp r2, #0
- 800107c: f000 80d3 beq.w 8001226 <_ZNK13geometry_msgs4Pose9serializeEPh+0x24e>
- 8001080: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001084: 0114 lsls r4, r2, #4
- 8001086: 0912 lsrs r2, r2, #4
- 8001088: b264 sxtb r4, r4
- 800108a: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800108e: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001092: 2500 movs r5, #0
- 8001094: 015f lsls r7, r3, #5
- 8001096: 4334 orrs r4, r6
- 8001098: 10de asrs r6, r3, #3
- 800109a: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800109e: ea4f 23e3 mov.w r3, r3, asr #11
- 80010a2: 740d strb r5, [r1, #16]
- 80010a4: 754b strb r3, [r1, #21]
- 80010a6: bf48 it mi
- 80010a8: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80010ac: 758c strb r4, [r1, #22]
- 80010ae: 744d strb r5, [r1, #17]
- 80010b0: 75ca strb r2, [r1, #23]
- 80010b2: 748d strb r5, [r1, #18]
- 80010b4: 74cf strb r7, [r1, #19]
- 80010b6: 750e strb r6, [r1, #20]
- 80010b8: edd0 7a06 vldr s15, [r0, #24]
- 80010bc: ee17 3a90 vmov r3, s15
- 80010c0: f3c3 52c7 ubfx r2, r3, #23, #8
- 80010c4: 2a00 cmp r2, #0
- 80010c6: f000 80ac beq.w 8001222 <_ZNK13geometry_msgs4Pose9serializeEPh+0x24a>
- 80010ca: f502 7260 add.w r2, r2, #896 ; 0x380
- 80010ce: 0114 lsls r4, r2, #4
- 80010d0: 0912 lsrs r2, r2, #4
- 80010d2: b264 sxtb r4, r4
- 80010d4: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80010d8: f3c3 46c3 ubfx r6, r3, #19, #4
- 80010dc: 2500 movs r5, #0
- 80010de: 015f lsls r7, r3, #5
- 80010e0: 4334 orrs r4, r6
- 80010e2: 10de asrs r6, r3, #3
- 80010e4: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80010e8: ea4f 23e3 mov.w r3, r3, asr #11
- 80010ec: 760d strb r5, [r1, #24]
- 80010ee: 774b strb r3, [r1, #29]
- 80010f0: bf48 it mi
- 80010f2: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80010f6: 778c strb r4, [r1, #30]
- 80010f8: 764d strb r5, [r1, #25]
- 80010fa: 77ca strb r2, [r1, #31]
- 80010fc: 768d strb r5, [r1, #26]
- 80010fe: 76cf strb r7, [r1, #27]
- 8001100: 770e strb r6, [r1, #28]
- 8001102: edd0 7a07 vldr s15, [r0, #28]
- 8001106: ee17 3a90 vmov r3, s15
- 800110a: f3c3 52c7 ubfx r2, r3, #23, #8
- 800110e: 2a00 cmp r2, #0
- 8001110: f000 8085 beq.w 800121e <_ZNK13geometry_msgs4Pose9serializeEPh+0x246>
- 8001114: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001118: 0114 lsls r4, r2, #4
- 800111a: 0912 lsrs r2, r2, #4
- 800111c: b264 sxtb r4, r4
- 800111e: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001122: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001126: 2500 movs r5, #0
- 8001128: 015f lsls r7, r3, #5
- 800112a: 4334 orrs r4, r6
- 800112c: 10de asrs r6, r3, #3
- 800112e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001132: ea4f 23e3 mov.w r3, r3, asr #11
- 8001136: f881 5020 strb.w r5, [r1, #32]
- 800113a: f881 3025 strb.w r3, [r1, #37] ; 0x25
- 800113e: bf48 it mi
- 8001140: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001144: f881 4026 strb.w r4, [r1, #38] ; 0x26
- 8001148: f881 5021 strb.w r5, [r1, #33] ; 0x21
- 800114c: f881 2027 strb.w r2, [r1, #39] ; 0x27
- 8001150: f881 5022 strb.w r5, [r1, #34] ; 0x22
- 8001154: f881 7023 strb.w r7, [r1, #35] ; 0x23
- 8001158: f881 6024 strb.w r6, [r1, #36] ; 0x24
- 800115c: edd0 7a08 vldr s15, [r0, #32]
- 8001160: ee17 3a90 vmov r3, s15
- 8001164: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001168: 2a00 cmp r2, #0
- 800116a: d056 beq.n 800121a <_ZNK13geometry_msgs4Pose9serializeEPh+0x242>
- 800116c: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001170: 0114 lsls r4, r2, #4
- 8001172: 0912 lsrs r2, r2, #4
- 8001174: b264 sxtb r4, r4
- 8001176: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800117a: f3c3 46c3 ubfx r6, r3, #19, #4
- 800117e: 2500 movs r5, #0
- 8001180: 015f lsls r7, r3, #5
- 8001182: 4334 orrs r4, r6
- 8001184: 10de asrs r6, r3, #3
- 8001186: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800118a: ea4f 23e3 mov.w r3, r3, asr #11
- 800118e: f881 5028 strb.w r5, [r1, #40] ; 0x28
- 8001192: f881 302d strb.w r3, [r1, #45] ; 0x2d
- 8001196: bf48 it mi
- 8001198: f062 027f ornmi r2, r2, #127 ; 0x7f
- 800119c: f881 402e strb.w r4, [r1, #46] ; 0x2e
- 80011a0: f881 5029 strb.w r5, [r1, #41] ; 0x29
- 80011a4: f881 202f strb.w r2, [r1, #47] ; 0x2f
- 80011a8: f881 502a strb.w r5, [r1, #42] ; 0x2a
- 80011ac: f881 702b strb.w r7, [r1, #43] ; 0x2b
- 80011b0: f881 602c strb.w r6, [r1, #44] ; 0x2c
- 80011b4: edd0 7a09 vldr s15, [r0, #36] ; 0x24
- 80011b8: ee17 3a90 vmov r3, s15
- 80011bc: f3c3 52c7 ubfx r2, r3, #23, #8
- 80011c0: b34a cbz r2, 8001216 <_ZNK13geometry_msgs4Pose9serializeEPh+0x23e>
- 80011c2: f502 7260 add.w r2, r2, #896 ; 0x380
- 80011c6: 0110 lsls r0, r2, #4
- 80011c8: 0912 lsrs r2, r2, #4
- 80011ca: b240 sxtb r0, r0
- 80011cc: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80011d0: f3c3 45c3 ubfx r5, r3, #19, #4
- 80011d4: 2400 movs r4, #0
- 80011d6: 015e lsls r6, r3, #5
- 80011d8: 4328 orrs r0, r5
- 80011da: 10dd asrs r5, r3, #3
- 80011dc: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80011e0: ea4f 23e3 mov.w r3, r3, asr #11
- 80011e4: f881 4030 strb.w r4, [r1, #48] ; 0x30
- 80011e8: f881 0036 strb.w r0, [r1, #54] ; 0x36
- 80011ec: f04f 0038 mov.w r0, #56 ; 0x38
- 80011f0: bf48 it mi
- 80011f2: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80011f6: f881 4031 strb.w r4, [r1, #49] ; 0x31
- 80011fa: f881 4032 strb.w r4, [r1, #50] ; 0x32
- 80011fe: f881 6033 strb.w r6, [r1, #51] ; 0x33
- 8001202: f881 5034 strb.w r5, [r1, #52] ; 0x34
- 8001206: f881 3035 strb.w r3, [r1, #53] ; 0x35
- 800120a: f881 2037 strb.w r2, [r1, #55] ; 0x37
- 800120e: bcf0 pop {r4, r5, r6, r7}
- 8001210: 4770 bx lr
- 8001212: 4614 mov r4, r2
- 8001214: e6ef b.n 8000ff6 <_ZNK13geometry_msgs4Pose9serializeEPh+0x1e>
- 8001216: 4610 mov r0, r2
- 8001218: e7d8 b.n 80011cc <_ZNK13geometry_msgs4Pose9serializeEPh+0x1f4>
- 800121a: 4614 mov r4, r2
- 800121c: e7ab b.n 8001176 <_ZNK13geometry_msgs4Pose9serializeEPh+0x19e>
- 800121e: 4614 mov r4, r2
- 8001220: e77d b.n 800111e <_ZNK13geometry_msgs4Pose9serializeEPh+0x146>
- 8001222: 4614 mov r4, r2
- 8001224: e756 b.n 80010d4 <_ZNK13geometry_msgs4Pose9serializeEPh+0xfc>
- 8001226: 4614 mov r4, r2
- 8001228: e72f b.n 800108a <_ZNK13geometry_msgs4Pose9serializeEPh+0xb2>
- 800122a: 4614 mov r4, r2
- 800122c: e708 b.n 8001040 <_ZNK13geometry_msgs4Pose9serializeEPh+0x68>
- 800122e: bf00 nop
-
-08001230 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh>:
- 8001230: edd0 7a03 vldr s15, [r0, #12]
- 8001234: ee17 3a90 vmov r3, s15
- 8001238: f3c3 52c7 ubfx r2, r3, #23, #8
- 800123c: b5f0 push {r4, r5, r6, r7, lr}
- 800123e: 2a00 cmp r2, #0
- 8001240: f000 8157 beq.w 80014f2 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x2c2>
- 8001244: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001248: 0114 lsls r4, r2, #4
- 800124a: 0912 lsrs r2, r2, #4
- 800124c: b264 sxtb r4, r4
- 800124e: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001252: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001256: 2500 movs r5, #0
- 8001258: 015f lsls r7, r3, #5
- 800125a: 4334 orrs r4, r6
- 800125c: 10de asrs r6, r3, #3
- 800125e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001262: ea4f 23e3 mov.w r3, r3, asr #11
- 8001266: 700d strb r5, [r1, #0]
- 8001268: 714b strb r3, [r1, #5]
- 800126a: bf48 it mi
- 800126c: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001270: 718c strb r4, [r1, #6]
- 8001272: 704d strb r5, [r1, #1]
- 8001274: 71ca strb r2, [r1, #7]
- 8001276: 708d strb r5, [r1, #2]
- 8001278: 70cf strb r7, [r1, #3]
- 800127a: 710e strb r6, [r1, #4]
- 800127c: edd0 7a04 vldr s15, [r0, #16]
- 8001280: ee17 3a90 vmov r3, s15
- 8001284: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001288: 2a00 cmp r2, #0
- 800128a: f000 8130 beq.w 80014ee <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x2be>
- 800128e: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001292: 0114 lsls r4, r2, #4
- 8001294: 0912 lsrs r2, r2, #4
- 8001296: b264 sxtb r4, r4
- 8001298: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800129c: f3c3 46c3 ubfx r6, r3, #19, #4
- 80012a0: 2500 movs r5, #0
- 80012a2: 015f lsls r7, r3, #5
- 80012a4: 4334 orrs r4, r6
- 80012a6: 10de asrs r6, r3, #3
- 80012a8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80012ac: ea4f 23e3 mov.w r3, r3, asr #11
- 80012b0: 720d strb r5, [r1, #8]
- 80012b2: 734b strb r3, [r1, #13]
- 80012b4: bf48 it mi
- 80012b6: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80012ba: 738c strb r4, [r1, #14]
- 80012bc: 724d strb r5, [r1, #9]
- 80012be: 73ca strb r2, [r1, #15]
- 80012c0: 728d strb r5, [r1, #10]
- 80012c2: 72cf strb r7, [r1, #11]
- 80012c4: 730e strb r6, [r1, #12]
- 80012c6: edd0 7a05 vldr s15, [r0, #20]
- 80012ca: ee17 3a90 vmov r3, s15
- 80012ce: f3c3 52c7 ubfx r2, r3, #23, #8
- 80012d2: 2a00 cmp r2, #0
- 80012d4: f000 8109 beq.w 80014ea <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x2ba>
- 80012d8: f502 7260 add.w r2, r2, #896 ; 0x380
- 80012dc: 0114 lsls r4, r2, #4
- 80012de: 0912 lsrs r2, r2, #4
- 80012e0: b264 sxtb r4, r4
- 80012e2: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80012e6: f3c3 46c3 ubfx r6, r3, #19, #4
- 80012ea: 2500 movs r5, #0
- 80012ec: 015f lsls r7, r3, #5
- 80012ee: 4334 orrs r4, r6
- 80012f0: 10de asrs r6, r3, #3
- 80012f2: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80012f6: ea4f 23e3 mov.w r3, r3, asr #11
- 80012fa: 740d strb r5, [r1, #16]
- 80012fc: 754b strb r3, [r1, #21]
- 80012fe: bf48 it mi
- 8001300: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001304: 758c strb r4, [r1, #22]
- 8001306: 744d strb r5, [r1, #17]
- 8001308: 75ca strb r2, [r1, #23]
- 800130a: 748d strb r5, [r1, #18]
- 800130c: 74cf strb r7, [r1, #19]
- 800130e: 750e strb r6, [r1, #20]
- 8001310: edd0 7a07 vldr s15, [r0, #28]
- 8001314: ee17 3a90 vmov r3, s15
- 8001318: f3c3 52c7 ubfx r2, r3, #23, #8
- 800131c: 2a00 cmp r2, #0
- 800131e: f000 80e2 beq.w 80014e6 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x2b6>
- 8001322: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001326: 0114 lsls r4, r2, #4
- 8001328: 0912 lsrs r2, r2, #4
- 800132a: b264 sxtb r4, r4
- 800132c: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001330: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001334: 2500 movs r5, #0
- 8001336: 015f lsls r7, r3, #5
- 8001338: 4334 orrs r4, r6
- 800133a: 10de asrs r6, r3, #3
- 800133c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001340: ea4f 23e3 mov.w r3, r3, asr #11
- 8001344: 760d strb r5, [r1, #24]
- 8001346: 774b strb r3, [r1, #29]
- 8001348: bf48 it mi
- 800134a: f062 027f ornmi r2, r2, #127 ; 0x7f
- 800134e: 778c strb r4, [r1, #30]
- 8001350: 764d strb r5, [r1, #25]
- 8001352: 77ca strb r2, [r1, #31]
- 8001354: 768d strb r5, [r1, #26]
- 8001356: 76cf strb r7, [r1, #27]
- 8001358: 770e strb r6, [r1, #28]
- 800135a: edd0 7a08 vldr s15, [r0, #32]
- 800135e: ee17 3a90 vmov r3, s15
- 8001362: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001366: 2a00 cmp r2, #0
- 8001368: f000 80bb beq.w 80014e2 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x2b2>
- 800136c: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001370: 0114 lsls r4, r2, #4
- 8001372: 0912 lsrs r2, r2, #4
- 8001374: b264 sxtb r4, r4
- 8001376: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800137a: f3c3 46c3 ubfx r6, r3, #19, #4
- 800137e: 2500 movs r5, #0
- 8001380: 015f lsls r7, r3, #5
- 8001382: 4334 orrs r4, r6
- 8001384: 10de asrs r6, r3, #3
- 8001386: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800138a: ea4f 23e3 mov.w r3, r3, asr #11
- 800138e: f881 5020 strb.w r5, [r1, #32]
- 8001392: f881 3025 strb.w r3, [r1, #37] ; 0x25
- 8001396: bf48 it mi
- 8001398: f062 027f ornmi r2, r2, #127 ; 0x7f
- 800139c: f881 4026 strb.w r4, [r1, #38] ; 0x26
- 80013a0: f881 5021 strb.w r5, [r1, #33] ; 0x21
- 80013a4: f881 2027 strb.w r2, [r1, #39] ; 0x27
- 80013a8: f881 5022 strb.w r5, [r1, #34] ; 0x22
- 80013ac: f881 7023 strb.w r7, [r1, #35] ; 0x23
- 80013b0: f881 6024 strb.w r6, [r1, #36] ; 0x24
- 80013b4: edd0 7a09 vldr s15, [r0, #36] ; 0x24
- 80013b8: ee17 3a90 vmov r3, s15
- 80013bc: f3c3 52c7 ubfx r2, r3, #23, #8
- 80013c0: 2a00 cmp r2, #0
- 80013c2: f000 808c beq.w 80014de <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x2ae>
- 80013c6: f502 7260 add.w r2, r2, #896 ; 0x380
- 80013ca: 0114 lsls r4, r2, #4
- 80013cc: 0912 lsrs r2, r2, #4
- 80013ce: b264 sxtb r4, r4
- 80013d0: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80013d4: f3c3 46c3 ubfx r6, r3, #19, #4
- 80013d8: 2500 movs r5, #0
- 80013da: 015f lsls r7, r3, #5
- 80013dc: 4334 orrs r4, r6
- 80013de: 10de asrs r6, r3, #3
- 80013e0: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80013e4: ea4f 23e3 mov.w r3, r3, asr #11
- 80013e8: f881 5028 strb.w r5, [r1, #40] ; 0x28
- 80013ec: f881 302d strb.w r3, [r1, #45] ; 0x2d
- 80013f0: bf48 it mi
- 80013f2: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80013f6: f881 402e strb.w r4, [r1, #46] ; 0x2e
- 80013fa: f881 5029 strb.w r5, [r1, #41] ; 0x29
- 80013fe: f881 202f strb.w r2, [r1, #47] ; 0x2f
- 8001402: f881 502a strb.w r5, [r1, #42] ; 0x2a
- 8001406: f881 702b strb.w r7, [r1, #43] ; 0x2b
- 800140a: f881 602c strb.w r6, [r1, #44] ; 0x2c
- 800140e: edd0 7a0a vldr s15, [r0, #40] ; 0x28
- 8001412: ee17 3a90 vmov r3, s15
- 8001416: f3c3 52c7 ubfx r2, r3, #23, #8
- 800141a: 2a00 cmp r2, #0
- 800141c: d05d beq.n 80014da <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x2aa>
- 800141e: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001422: 0114 lsls r4, r2, #4
- 8001424: 0912 lsrs r2, r2, #4
- 8001426: b264 sxtb r4, r4
- 8001428: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800142c: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001430: 2500 movs r5, #0
- 8001432: 015f lsls r7, r3, #5
- 8001434: 4334 orrs r4, r6
- 8001436: f100 0ebc add.w lr, r0, #188 ; 0xbc
- 800143a: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800143e: ea4f 06e3 mov.w r6, r3, asr #3
- 8001442: f881 5030 strb.w r5, [r1, #48] ; 0x30
- 8001446: ea4f 23e3 mov.w r3, r3, asr #11
- 800144a: f881 4036 strb.w r4, [r1, #54] ; 0x36
- 800144e: f04f 0400 mov.w r4, #0
- 8001452: f881 5031 strb.w r5, [r1, #49] ; 0x31
- 8001456: bf48 it mi
- 8001458: f062 027f ornmi r2, r2, #127 ; 0x7f
- 800145c: f881 5032 strb.w r5, [r1, #50] ; 0x32
- 8001460: f100 052c add.w r5, r0, #44 ; 0x2c
- 8001464: f881 7033 strb.w r7, [r1, #51] ; 0x33
- 8001468: f881 6034 strb.w r6, [r1, #52] ; 0x34
- 800146c: f881 3035 strb.w r3, [r1, #53] ; 0x35
- 8001470: f881 2037 strb.w r2, [r1, #55] ; 0x37
- 8001474: ecf5 7a01 vldmia r5!, {s15}
- 8001478: ee17 3a90 vmov r3, s15
- 800147c: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001480: 4610 mov r0, r2
- 8001482: f502 7660 add.w r6, r2, #896 ; 0x380
- 8001486: b112 cbz r2, 800148e <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x25e>
- 8001488: 0132 lsls r2, r6, #4
- 800148a: 0930 lsrs r0, r6, #4
- 800148c: b252 sxtb r2, r2
- 800148e: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001492: f3c3 4cc3 ubfx ip, r3, #19, #4
- 8001496: 015f lsls r7, r3, #5
- 8001498: f881 4038 strb.w r4, [r1, #56] ; 0x38
- 800149c: 10de asrs r6, r3, #3
- 800149e: ea42 020c orr.w r2, r2, ip
- 80014a2: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80014a6: ea4f 23e3 mov.w r3, r3, asr #11
- 80014aa: f881 4039 strb.w r4, [r1, #57] ; 0x39
- 80014ae: f101 0108 add.w r1, r1, #8
- 80014b2: f881 4032 strb.w r4, [r1, #50] ; 0x32
- 80014b6: bf48 it mi
- 80014b8: f060 007f ornmi r0, r0, #127 ; 0x7f
- 80014bc: 4575 cmp r5, lr
- 80014be: f881 2036 strb.w r2, [r1, #54] ; 0x36
- 80014c2: f881 7033 strb.w r7, [r1, #51] ; 0x33
- 80014c6: f881 6034 strb.w r6, [r1, #52] ; 0x34
- 80014ca: f881 3035 strb.w r3, [r1, #53] ; 0x35
- 80014ce: f881 0037 strb.w r0, [r1, #55] ; 0x37
- 80014d2: d1cf bne.n 8001474 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x244>
- 80014d4: f44f 70ac mov.w r0, #344 ; 0x158
- 80014d8: bdf0 pop {r4, r5, r6, r7, pc}
- 80014da: 4614 mov r4, r2
- 80014dc: e7a4 b.n 8001428 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x1f8>
- 80014de: 4614 mov r4, r2
- 80014e0: e776 b.n 80013d0 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x1a0>
- 80014e2: 4614 mov r4, r2
- 80014e4: e747 b.n 8001376 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x146>
- 80014e6: 4614 mov r4, r2
- 80014e8: e720 b.n 800132c <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0xfc>
- 80014ea: 4614 mov r4, r2
- 80014ec: e6f9 b.n 80012e2 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0xb2>
- 80014ee: 4614 mov r4, r2
- 80014f0: e6d2 b.n 8001298 <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x68>
- 80014f2: 4614 mov r4, r2
- 80014f4: e6ab b.n 800124e <_ZNK13geometry_msgs18PoseWithCovariance9serializeEPh+0x1e>
- 80014f6: bf00 nop
-
-080014f8 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh>:
- 80014f8: edd0 7a03 vldr s15, [r0, #12]
- 80014fc: ee17 3a90 vmov r3, s15
- 8001500: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001504: b5f0 push {r4, r5, r6, r7, lr}
- 8001506: 2a00 cmp r2, #0
- 8001508: f000 8128 beq.w 800175c <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x264>
- 800150c: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001510: 0114 lsls r4, r2, #4
- 8001512: 0912 lsrs r2, r2, #4
- 8001514: b264 sxtb r4, r4
- 8001516: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800151a: f3c3 46c3 ubfx r6, r3, #19, #4
- 800151e: 2500 movs r5, #0
- 8001520: 015f lsls r7, r3, #5
- 8001522: 4334 orrs r4, r6
- 8001524: 10de asrs r6, r3, #3
- 8001526: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800152a: ea4f 23e3 mov.w r3, r3, asr #11
- 800152e: 700d strb r5, [r1, #0]
- 8001530: 714b strb r3, [r1, #5]
- 8001532: bf48 it mi
- 8001534: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001538: 718c strb r4, [r1, #6]
- 800153a: 704d strb r5, [r1, #1]
- 800153c: 71ca strb r2, [r1, #7]
- 800153e: 708d strb r5, [r1, #2]
- 8001540: 70cf strb r7, [r1, #3]
- 8001542: 710e strb r6, [r1, #4]
- 8001544: edd0 7a04 vldr s15, [r0, #16]
- 8001548: ee17 3a90 vmov r3, s15
- 800154c: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001550: 2a00 cmp r2, #0
- 8001552: f000 8101 beq.w 8001758 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x260>
- 8001556: f502 7260 add.w r2, r2, #896 ; 0x380
- 800155a: 0114 lsls r4, r2, #4
- 800155c: 0912 lsrs r2, r2, #4
- 800155e: b264 sxtb r4, r4
- 8001560: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001564: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001568: 2500 movs r5, #0
- 800156a: 015f lsls r7, r3, #5
- 800156c: 4334 orrs r4, r6
- 800156e: 10de asrs r6, r3, #3
- 8001570: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001574: ea4f 23e3 mov.w r3, r3, asr #11
- 8001578: 720d strb r5, [r1, #8]
- 800157a: 734b strb r3, [r1, #13]
- 800157c: bf48 it mi
- 800157e: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001582: 738c strb r4, [r1, #14]
- 8001584: 724d strb r5, [r1, #9]
- 8001586: 73ca strb r2, [r1, #15]
- 8001588: 728d strb r5, [r1, #10]
- 800158a: 72cf strb r7, [r1, #11]
- 800158c: 730e strb r6, [r1, #12]
- 800158e: edd0 7a05 vldr s15, [r0, #20]
- 8001592: ee17 3a90 vmov r3, s15
- 8001596: f3c3 52c7 ubfx r2, r3, #23, #8
- 800159a: 2a00 cmp r2, #0
- 800159c: f000 80da beq.w 8001754 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x25c>
- 80015a0: f502 7260 add.w r2, r2, #896 ; 0x380
- 80015a4: 0114 lsls r4, r2, #4
- 80015a6: 0912 lsrs r2, r2, #4
- 80015a8: b264 sxtb r4, r4
- 80015aa: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80015ae: f3c3 46c3 ubfx r6, r3, #19, #4
- 80015b2: 2500 movs r5, #0
- 80015b4: 015f lsls r7, r3, #5
- 80015b6: 4334 orrs r4, r6
- 80015b8: 10de asrs r6, r3, #3
- 80015ba: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80015be: ea4f 23e3 mov.w r3, r3, asr #11
- 80015c2: 740d strb r5, [r1, #16]
- 80015c4: 754b strb r3, [r1, #21]
- 80015c6: bf48 it mi
- 80015c8: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80015cc: 758c strb r4, [r1, #22]
- 80015ce: 744d strb r5, [r1, #17]
- 80015d0: 75ca strb r2, [r1, #23]
- 80015d2: 748d strb r5, [r1, #18]
- 80015d4: 74cf strb r7, [r1, #19]
- 80015d6: 750e strb r6, [r1, #20]
- 80015d8: edd0 7a07 vldr s15, [r0, #28]
- 80015dc: ee17 3a90 vmov r3, s15
- 80015e0: f3c3 52c7 ubfx r2, r3, #23, #8
- 80015e4: 2a00 cmp r2, #0
- 80015e6: f000 80b3 beq.w 8001750 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x258>
- 80015ea: f502 7260 add.w r2, r2, #896 ; 0x380
- 80015ee: 0114 lsls r4, r2, #4
- 80015f0: 0912 lsrs r2, r2, #4
- 80015f2: b264 sxtb r4, r4
- 80015f4: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80015f8: f3c3 46c3 ubfx r6, r3, #19, #4
- 80015fc: 2500 movs r5, #0
- 80015fe: 015f lsls r7, r3, #5
- 8001600: 4334 orrs r4, r6
- 8001602: 10de asrs r6, r3, #3
- 8001604: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001608: ea4f 23e3 mov.w r3, r3, asr #11
- 800160c: 760d strb r5, [r1, #24]
- 800160e: 774b strb r3, [r1, #29]
- 8001610: bf48 it mi
- 8001612: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001616: 778c strb r4, [r1, #30]
- 8001618: 764d strb r5, [r1, #25]
- 800161a: 77ca strb r2, [r1, #31]
- 800161c: 768d strb r5, [r1, #26]
- 800161e: 76cf strb r7, [r1, #27]
- 8001620: 770e strb r6, [r1, #28]
- 8001622: edd0 7a08 vldr s15, [r0, #32]
- 8001626: ee17 3a90 vmov r3, s15
- 800162a: f3c3 52c7 ubfx r2, r3, #23, #8
- 800162e: 2a00 cmp r2, #0
- 8001630: f000 808c beq.w 800174c <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x254>
- 8001634: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001638: 0114 lsls r4, r2, #4
- 800163a: 0912 lsrs r2, r2, #4
- 800163c: b264 sxtb r4, r4
- 800163e: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001642: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001646: 2500 movs r5, #0
- 8001648: 015f lsls r7, r3, #5
- 800164a: 4334 orrs r4, r6
- 800164c: 10de asrs r6, r3, #3
- 800164e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001652: ea4f 23e3 mov.w r3, r3, asr #11
- 8001656: f881 5020 strb.w r5, [r1, #32]
- 800165a: f881 3025 strb.w r3, [r1, #37] ; 0x25
- 800165e: bf48 it mi
- 8001660: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001664: f881 4026 strb.w r4, [r1, #38] ; 0x26
- 8001668: f881 5021 strb.w r5, [r1, #33] ; 0x21
- 800166c: f881 2027 strb.w r2, [r1, #39] ; 0x27
- 8001670: f881 5022 strb.w r5, [r1, #34] ; 0x22
- 8001674: f881 7023 strb.w r7, [r1, #35] ; 0x23
- 8001678: f881 6024 strb.w r6, [r1, #36] ; 0x24
- 800167c: edd0 7a09 vldr s15, [r0, #36] ; 0x24
- 8001680: ee17 3a90 vmov r3, s15
- 8001684: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001688: 2a00 cmp r2, #0
- 800168a: d05d beq.n 8001748 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x250>
- 800168c: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001690: 0114 lsls r4, r2, #4
- 8001692: 0912 lsrs r2, r2, #4
- 8001694: b264 sxtb r4, r4
- 8001696: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800169a: f3c3 46c3 ubfx r6, r3, #19, #4
- 800169e: 2500 movs r5, #0
- 80016a0: 015f lsls r7, r3, #5
- 80016a2: 4334 orrs r4, r6
- 80016a4: f100 0eb8 add.w lr, r0, #184 ; 0xb8
- 80016a8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80016ac: ea4f 06e3 mov.w r6, r3, asr #3
- 80016b0: f881 5028 strb.w r5, [r1, #40] ; 0x28
- 80016b4: ea4f 23e3 mov.w r3, r3, asr #11
- 80016b8: f881 402e strb.w r4, [r1, #46] ; 0x2e
- 80016bc: f04f 0400 mov.w r4, #0
- 80016c0: f881 5029 strb.w r5, [r1, #41] ; 0x29
- 80016c4: bf48 it mi
- 80016c6: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80016ca: f881 502a strb.w r5, [r1, #42] ; 0x2a
- 80016ce: f100 0528 add.w r5, r0, #40 ; 0x28
- 80016d2: f881 702b strb.w r7, [r1, #43] ; 0x2b
- 80016d6: f881 602c strb.w r6, [r1, #44] ; 0x2c
- 80016da: f881 302d strb.w r3, [r1, #45] ; 0x2d
- 80016de: f881 202f strb.w r2, [r1, #47] ; 0x2f
- 80016e2: ecf5 7a01 vldmia r5!, {s15}
- 80016e6: ee17 3a90 vmov r3, s15
- 80016ea: f3c3 52c7 ubfx r2, r3, #23, #8
- 80016ee: 4610 mov r0, r2
- 80016f0: f502 7660 add.w r6, r2, #896 ; 0x380
- 80016f4: b112 cbz r2, 80016fc <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x204>
- 80016f6: 0132 lsls r2, r6, #4
- 80016f8: 0930 lsrs r0, r6, #4
- 80016fa: b252 sxtb r2, r2
- 80016fc: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001700: f3c3 4cc3 ubfx ip, r3, #19, #4
- 8001704: 015f lsls r7, r3, #5
- 8001706: f881 4030 strb.w r4, [r1, #48] ; 0x30
- 800170a: 10de asrs r6, r3, #3
- 800170c: ea42 020c orr.w r2, r2, ip
- 8001710: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001714: ea4f 23e3 mov.w r3, r3, asr #11
- 8001718: f881 4031 strb.w r4, [r1, #49] ; 0x31
- 800171c: f101 0108 add.w r1, r1, #8
- 8001720: f881 402a strb.w r4, [r1, #42] ; 0x2a
- 8001724: bf48 it mi
- 8001726: f060 007f ornmi r0, r0, #127 ; 0x7f
- 800172a: 4575 cmp r5, lr
- 800172c: f881 202e strb.w r2, [r1, #46] ; 0x2e
- 8001730: f881 702b strb.w r7, [r1, #43] ; 0x2b
- 8001734: f881 602c strb.w r6, [r1, #44] ; 0x2c
- 8001738: f881 302d strb.w r3, [r1, #45] ; 0x2d
- 800173c: f881 002f strb.w r0, [r1, #47] ; 0x2f
- 8001740: d1cf bne.n 80016e2 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x1ea>
- 8001742: f44f 70a8 mov.w r0, #336 ; 0x150
- 8001746: bdf0 pop {r4, r5, r6, r7, pc}
- 8001748: 4614 mov r4, r2
- 800174a: e7a4 b.n 8001696 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x19e>
- 800174c: 4614 mov r4, r2
- 800174e: e776 b.n 800163e <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x146>
- 8001750: 4614 mov r4, r2
- 8001752: e74f b.n 80015f4 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0xfc>
- 8001754: 4614 mov r4, r2
- 8001756: e728 b.n 80015aa <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0xb2>
- 8001758: 4614 mov r4, r2
- 800175a: e701 b.n 8001560 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x68>
- 800175c: 4614 mov r4, r2
- 800175e: e6da b.n 8001516 <_ZNK13geometry_msgs19TwistWithCovariance9serializeEPh+0x1e>
-
-08001760 <_ZNK13geometry_msgs7Vector39serializeEPh>:
- 8001760: edd0 7a01 vldr s15, [r0, #4]
- 8001764: ee17 3a90 vmov r3, s15
- 8001768: f3c3 52c7 ubfx r2, r3, #23, #8
- 800176c: b4f0 push {r4, r5, r6, r7}
- 800176e: 2a00 cmp r2, #0
- 8001770: d066 beq.n 8001840 <_ZNK13geometry_msgs7Vector39serializeEPh+0xe0>
- 8001772: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001776: 0114 lsls r4, r2, #4
- 8001778: 0912 lsrs r2, r2, #4
- 800177a: b264 sxtb r4, r4
- 800177c: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001780: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001784: 2500 movs r5, #0
- 8001786: 015f lsls r7, r3, #5
- 8001788: 4334 orrs r4, r6
- 800178a: 10de asrs r6, r3, #3
- 800178c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001790: ea4f 23e3 mov.w r3, r3, asr #11
- 8001794: 700d strb r5, [r1, #0]
- 8001796: 714b strb r3, [r1, #5]
- 8001798: bf48 it mi
- 800179a: f062 027f ornmi r2, r2, #127 ; 0x7f
- 800179e: 718c strb r4, [r1, #6]
- 80017a0: 704d strb r5, [r1, #1]
- 80017a2: 71ca strb r2, [r1, #7]
- 80017a4: 708d strb r5, [r1, #2]
- 80017a6: 70cf strb r7, [r1, #3]
- 80017a8: 710e strb r6, [r1, #4]
- 80017aa: edd0 7a02 vldr s15, [r0, #8]
- 80017ae: ee17 3a90 vmov r3, s15
- 80017b2: f3c3 52c7 ubfx r2, r3, #23, #8
- 80017b6: 2a00 cmp r2, #0
- 80017b8: d046 beq.n 8001848 <_ZNK13geometry_msgs7Vector39serializeEPh+0xe8>
- 80017ba: f502 7260 add.w r2, r2, #896 ; 0x380
- 80017be: 0114 lsls r4, r2, #4
- 80017c0: 0912 lsrs r2, r2, #4
- 80017c2: b264 sxtb r4, r4
- 80017c4: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80017c8: f3c3 46c3 ubfx r6, r3, #19, #4
- 80017cc: 2500 movs r5, #0
- 80017ce: 015f lsls r7, r3, #5
- 80017d0: 4334 orrs r4, r6
- 80017d2: 10de asrs r6, r3, #3
- 80017d4: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80017d8: ea4f 23e3 mov.w r3, r3, asr #11
- 80017dc: 720d strb r5, [r1, #8]
- 80017de: 734b strb r3, [r1, #13]
- 80017e0: bf48 it mi
- 80017e2: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80017e6: 738c strb r4, [r1, #14]
- 80017e8: 724d strb r5, [r1, #9]
- 80017ea: 73ca strb r2, [r1, #15]
- 80017ec: 728d strb r5, [r1, #10]
- 80017ee: 72cf strb r7, [r1, #11]
- 80017f0: 730e strb r6, [r1, #12]
- 80017f2: edd0 7a03 vldr s15, [r0, #12]
- 80017f6: ee17 3a90 vmov r3, s15
- 80017fa: f3c3 52c7 ubfx r2, r3, #23, #8
- 80017fe: b30a cbz r2, 8001844 <_ZNK13geometry_msgs7Vector39serializeEPh+0xe4>
- 8001800: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001804: 0110 lsls r0, r2, #4
- 8001806: 0912 lsrs r2, r2, #4
- 8001808: b240 sxtb r0, r0
- 800180a: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800180e: f3c3 45c3 ubfx r5, r3, #19, #4
- 8001812: 2400 movs r4, #0
- 8001814: 015e lsls r6, r3, #5
- 8001816: 4328 orrs r0, r5
- 8001818: 10dd asrs r5, r3, #3
- 800181a: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800181e: ea4f 23e3 mov.w r3, r3, asr #11
- 8001822: 740c strb r4, [r1, #16]
- 8001824: 7588 strb r0, [r1, #22]
- 8001826: f04f 0018 mov.w r0, #24
- 800182a: bf48 it mi
- 800182c: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001830: 744c strb r4, [r1, #17]
- 8001832: 748c strb r4, [r1, #18]
- 8001834: 74ce strb r6, [r1, #19]
- 8001836: 750d strb r5, [r1, #20]
- 8001838: 754b strb r3, [r1, #21]
- 800183a: 75ca strb r2, [r1, #23]
- 800183c: bcf0 pop {r4, r5, r6, r7}
- 800183e: 4770 bx lr
- 8001840: 4614 mov r4, r2
- 8001842: e79b b.n 800177c <_ZNK13geometry_msgs7Vector39serializeEPh+0x1c>
- 8001844: 4610 mov r0, r2
- 8001846: e7e0 b.n 800180a <_ZNK13geometry_msgs7Vector39serializeEPh+0xaa>
- 8001848: 4614 mov r4, r2
- 800184a: e7bb b.n 80017c4 <_ZNK13geometry_msgs7Vector39serializeEPh+0x64>
-
-0800184c <_ZNK13geometry_msgs5Point9serializeEPh>:
- 800184c: edd0 7a01 vldr s15, [r0, #4]
- 8001850: ee17 3a90 vmov r3, s15
- 8001854: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001858: b4f0 push {r4, r5, r6, r7}
- 800185a: 2a00 cmp r2, #0
- 800185c: d066 beq.n 800192c <_ZNK13geometry_msgs5Point9serializeEPh+0xe0>
- 800185e: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001862: 0114 lsls r4, r2, #4
- 8001864: 0912 lsrs r2, r2, #4
- 8001866: b264 sxtb r4, r4
- 8001868: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800186c: f3c3 46c3 ubfx r6, r3, #19, #4
- 8001870: 2500 movs r5, #0
- 8001872: 015f lsls r7, r3, #5
- 8001874: 4334 orrs r4, r6
- 8001876: 10de asrs r6, r3, #3
- 8001878: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800187c: ea4f 23e3 mov.w r3, r3, asr #11
- 8001880: 700d strb r5, [r1, #0]
- 8001882: 714b strb r3, [r1, #5]
- 8001884: bf48 it mi
- 8001886: f062 027f ornmi r2, r2, #127 ; 0x7f
- 800188a: 718c strb r4, [r1, #6]
- 800188c: 704d strb r5, [r1, #1]
- 800188e: 71ca strb r2, [r1, #7]
- 8001890: 708d strb r5, [r1, #2]
- 8001892: 70cf strb r7, [r1, #3]
- 8001894: 710e strb r6, [r1, #4]
- 8001896: edd0 7a02 vldr s15, [r0, #8]
- 800189a: ee17 3a90 vmov r3, s15
- 800189e: f3c3 52c7 ubfx r2, r3, #23, #8
- 80018a2: 2a00 cmp r2, #0
- 80018a4: d046 beq.n 8001934 <_ZNK13geometry_msgs5Point9serializeEPh+0xe8>
- 80018a6: f502 7260 add.w r2, r2, #896 ; 0x380
- 80018aa: 0114 lsls r4, r2, #4
- 80018ac: 0912 lsrs r2, r2, #4
- 80018ae: b264 sxtb r4, r4
- 80018b0: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80018b4: f3c3 46c3 ubfx r6, r3, #19, #4
- 80018b8: 2500 movs r5, #0
- 80018ba: 015f lsls r7, r3, #5
- 80018bc: 4334 orrs r4, r6
- 80018be: 10de asrs r6, r3, #3
- 80018c0: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80018c4: ea4f 23e3 mov.w r3, r3, asr #11
- 80018c8: 720d strb r5, [r1, #8]
- 80018ca: 734b strb r3, [r1, #13]
- 80018cc: bf48 it mi
- 80018ce: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80018d2: 738c strb r4, [r1, #14]
- 80018d4: 724d strb r5, [r1, #9]
- 80018d6: 73ca strb r2, [r1, #15]
- 80018d8: 728d strb r5, [r1, #10]
- 80018da: 72cf strb r7, [r1, #11]
- 80018dc: 730e strb r6, [r1, #12]
- 80018de: edd0 7a03 vldr s15, [r0, #12]
- 80018e2: ee17 3a90 vmov r3, s15
- 80018e6: f3c3 52c7 ubfx r2, r3, #23, #8
- 80018ea: b30a cbz r2, 8001930 <_ZNK13geometry_msgs5Point9serializeEPh+0xe4>
- 80018ec: f502 7260 add.w r2, r2, #896 ; 0x380
- 80018f0: 0110 lsls r0, r2, #4
- 80018f2: 0912 lsrs r2, r2, #4
- 80018f4: b240 sxtb r0, r0
- 80018f6: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80018fa: f3c3 45c3 ubfx r5, r3, #19, #4
- 80018fe: 2400 movs r4, #0
- 8001900: 015e lsls r6, r3, #5
- 8001902: 4328 orrs r0, r5
- 8001904: 10dd asrs r5, r3, #3
- 8001906: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800190a: ea4f 23e3 mov.w r3, r3, asr #11
- 800190e: 740c strb r4, [r1, #16]
- 8001910: 7588 strb r0, [r1, #22]
- 8001912: f04f 0018 mov.w r0, #24
- 8001916: bf48 it mi
- 8001918: f062 027f ornmi r2, r2, #127 ; 0x7f
- 800191c: 744c strb r4, [r1, #17]
- 800191e: 748c strb r4, [r1, #18]
- 8001920: 74ce strb r6, [r1, #19]
- 8001922: 750d strb r5, [r1, #20]
- 8001924: 754b strb r3, [r1, #21]
- 8001926: 75ca strb r2, [r1, #23]
- 8001928: bcf0 pop {r4, r5, r6, r7}
- 800192a: 4770 bx lr
- 800192c: 4614 mov r4, r2
- 800192e: e79b b.n 8001868 <_ZNK13geometry_msgs5Point9serializeEPh+0x1c>
- 8001930: 4610 mov r0, r2
- 8001932: e7e0 b.n 80018f6 <_ZNK13geometry_msgs5Point9serializeEPh+0xaa>
- 8001934: 4614 mov r4, r2
- 8001936: e7bb b.n 80018b0 <_ZNK13geometry_msgs5Point9serializeEPh+0x64>
-
-08001938 <_ZNK13geometry_msgs10Quaternion9serializeEPh>:
- 8001938: edd0 7a01 vldr s15, [r0, #4]
- 800193c: ee17 3a90 vmov r3, s15
- 8001940: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001944: b4f0 push {r4, r5, r6, r7}
- 8001946: 2a00 cmp r2, #0
- 8001948: f000 808b beq.w 8001a62 <_ZNK13geometry_msgs10Quaternion9serializeEPh+0x12a>
- 800194c: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001950: 0114 lsls r4, r2, #4
- 8001952: 0912 lsrs r2, r2, #4
- 8001954: b264 sxtb r4, r4
- 8001956: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800195a: f3c3 46c3 ubfx r6, r3, #19, #4
- 800195e: 2500 movs r5, #0
- 8001960: 015f lsls r7, r3, #5
- 8001962: 4334 orrs r4, r6
- 8001964: 10de asrs r6, r3, #3
- 8001966: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800196a: ea4f 23e3 mov.w r3, r3, asr #11
- 800196e: 700d strb r5, [r1, #0]
- 8001970: 714b strb r3, [r1, #5]
- 8001972: bf48 it mi
- 8001974: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001978: 718c strb r4, [r1, #6]
- 800197a: 704d strb r5, [r1, #1]
- 800197c: 71ca strb r2, [r1, #7]
- 800197e: 708d strb r5, [r1, #2]
- 8001980: 70cf strb r7, [r1, #3]
- 8001982: 710e strb r6, [r1, #4]
- 8001984: edd0 7a02 vldr s15, [r0, #8]
- 8001988: ee17 3a90 vmov r3, s15
- 800198c: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001990: 2a00 cmp r2, #0
- 8001992: d06c beq.n 8001a6e <_ZNK13geometry_msgs10Quaternion9serializeEPh+0x136>
- 8001994: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001998: 0114 lsls r4, r2, #4
- 800199a: 0912 lsrs r2, r2, #4
- 800199c: b264 sxtb r4, r4
- 800199e: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80019a2: f3c3 46c3 ubfx r6, r3, #19, #4
- 80019a6: 2500 movs r5, #0
- 80019a8: 015f lsls r7, r3, #5
- 80019aa: 4334 orrs r4, r6
- 80019ac: 10de asrs r6, r3, #3
- 80019ae: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80019b2: ea4f 23e3 mov.w r3, r3, asr #11
- 80019b6: 720d strb r5, [r1, #8]
- 80019b8: 734b strb r3, [r1, #13]
- 80019ba: bf48 it mi
- 80019bc: f062 027f ornmi r2, r2, #127 ; 0x7f
- 80019c0: 738c strb r4, [r1, #14]
- 80019c2: 724d strb r5, [r1, #9]
- 80019c4: 73ca strb r2, [r1, #15]
- 80019c6: 728d strb r5, [r1, #10]
- 80019c8: 72cf strb r7, [r1, #11]
- 80019ca: 730e strb r6, [r1, #12]
- 80019cc: edd0 7a03 vldr s15, [r0, #12]
- 80019d0: ee17 3a90 vmov r3, s15
- 80019d4: f3c3 52c7 ubfx r2, r3, #23, #8
- 80019d8: 2a00 cmp r2, #0
- 80019da: d046 beq.n 8001a6a <_ZNK13geometry_msgs10Quaternion9serializeEPh+0x132>
- 80019dc: f502 7260 add.w r2, r2, #896 ; 0x380
- 80019e0: 0114 lsls r4, r2, #4
- 80019e2: 0912 lsrs r2, r2, #4
- 80019e4: b264 sxtb r4, r4
- 80019e6: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80019ea: f3c3 46c3 ubfx r6, r3, #19, #4
- 80019ee: 2500 movs r5, #0
- 80019f0: 015f lsls r7, r3, #5
- 80019f2: 4334 orrs r4, r6
- 80019f4: 10de asrs r6, r3, #3
- 80019f6: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80019fa: ea4f 23e3 mov.w r3, r3, asr #11
- 80019fe: 740d strb r5, [r1, #16]
- 8001a00: 754b strb r3, [r1, #21]
- 8001a02: bf48 it mi
- 8001a04: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001a08: 758c strb r4, [r1, #22]
- 8001a0a: 744d strb r5, [r1, #17]
- 8001a0c: 75ca strb r2, [r1, #23]
- 8001a0e: 748d strb r5, [r1, #18]
- 8001a10: 74cf strb r7, [r1, #19]
- 8001a12: 750e strb r6, [r1, #20]
- 8001a14: edd0 7a04 vldr s15, [r0, #16]
- 8001a18: ee17 3a90 vmov r3, s15
- 8001a1c: f3c3 52c7 ubfx r2, r3, #23, #8
- 8001a20: b30a cbz r2, 8001a66 <_ZNK13geometry_msgs10Quaternion9serializeEPh+0x12e>
- 8001a22: f502 7260 add.w r2, r2, #896 ; 0x380
- 8001a26: 0110 lsls r0, r2, #4
- 8001a28: 0912 lsrs r2, r2, #4
- 8001a2a: b240 sxtb r0, r0
- 8001a2c: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001a30: f3c3 45c3 ubfx r5, r3, #19, #4
- 8001a34: 2400 movs r4, #0
- 8001a36: 015e lsls r6, r3, #5
- 8001a38: 4328 orrs r0, r5
- 8001a3a: 10dd asrs r5, r3, #3
- 8001a3c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001a40: ea4f 23e3 mov.w r3, r3, asr #11
- 8001a44: 760c strb r4, [r1, #24]
- 8001a46: 7788 strb r0, [r1, #30]
- 8001a48: f04f 0020 mov.w r0, #32
- 8001a4c: bf48 it mi
- 8001a4e: f062 027f ornmi r2, r2, #127 ; 0x7f
- 8001a52: 764c strb r4, [r1, #25]
- 8001a54: 768c strb r4, [r1, #26]
- 8001a56: 76ce strb r6, [r1, #27]
- 8001a58: 770d strb r5, [r1, #28]
- 8001a5a: 774b strb r3, [r1, #29]
- 8001a5c: 77ca strb r2, [r1, #31]
- 8001a5e: bcf0 pop {r4, r5, r6, r7}
- 8001a60: 4770 bx lr
- 8001a62: 4614 mov r4, r2
- 8001a64: e777 b.n 8001956 <_ZNK13geometry_msgs10Quaternion9serializeEPh+0x1e>
- 8001a66: 4610 mov r0, r2
- 8001a68: e7e0 b.n 8001a2c <_ZNK13geometry_msgs10Quaternion9serializeEPh+0xf4>
- 8001a6a: 4614 mov r4, r2
- 8001a6c: e7bb b.n 80019e6 <_ZNK13geometry_msgs10Quaternion9serializeEPh+0xae>
- 8001a6e: 4614 mov r4, r2
- 8001a70: e795 b.n 800199e <_ZNK13geometry_msgs10Quaternion9serializeEPh+0x66>
- 8001a72: bf00 nop
-
-08001a74 <_ZNK8nav_msgs8Odometry9serializeEPh>:
- 8001a74: 6883 ldr r3, [r0, #8]
- 8001a76: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 8001a7a: 700b strb r3, [r1, #0]
- 8001a7c: 4604 mov r4, r0
- 8001a7e: 6883 ldr r3, [r0, #8]
- 8001a80: 460d mov r5, r1
- 8001a82: 0a1b lsrs r3, r3, #8
- 8001a84: 704b strb r3, [r1, #1]
- 8001a86: 8943 ldrh r3, [r0, #10]
- 8001a88: 708b strb r3, [r1, #2]
- 8001a8a: 7ac3 ldrb r3, [r0, #11]
- 8001a8c: 70cb strb r3, [r1, #3]
- 8001a8e: 68c3 ldr r3, [r0, #12]
- 8001a90: 710b strb r3, [r1, #4]
- 8001a92: 68c3 ldr r3, [r0, #12]
- 8001a94: 0a1b lsrs r3, r3, #8
- 8001a96: 714b strb r3, [r1, #5]
- 8001a98: 89c3 ldrh r3, [r0, #14]
- 8001a9a: 718b strb r3, [r1, #6]
- 8001a9c: 7bc3 ldrb r3, [r0, #15]
- 8001a9e: 71cb strb r3, [r1, #7]
- 8001aa0: 6903 ldr r3, [r0, #16]
- 8001aa2: 720b strb r3, [r1, #8]
- 8001aa4: 6903 ldr r3, [r0, #16]
- 8001aa6: 0a1b lsrs r3, r3, #8
- 8001aa8: 724b strb r3, [r1, #9]
- 8001aaa: 8a43 ldrh r3, [r0, #18]
- 8001aac: 728b strb r3, [r1, #10]
- 8001aae: 7cc3 ldrb r3, [r0, #19]
- 8001ab0: 72cb strb r3, [r1, #11]
- 8001ab2: 6940 ldr r0, [r0, #20]
- 8001ab4: f7fe fbc0 bl 8000238 <strlen>
- 8001ab8: 4602 mov r2, r0
- 8001aba: f105 0010 add.w r0, r5, #16
- 8001abe: 0a16 lsrs r6, r2, #8
- 8001ac0: 732a strb r2, [r5, #12]
- 8001ac2: 0c11 lsrs r1, r2, #16
- 8001ac4: f102 0714 add.w r7, r2, #20
- 8001ac8: 0e13 lsrs r3, r2, #24
- 8001aca: 736e strb r6, [r5, #13]
- 8001acc: 73a9 strb r1, [r5, #14]
- 8001ace: f102 0810 add.w r8, r2, #16
- 8001ad2: 73eb strb r3, [r5, #15]
- 8001ad4: 6961 ldr r1, [r4, #20]
- 8001ad6: f008 f949 bl 8009d6c <memcpy>
- 8001ada: 69a0 ldr r0, [r4, #24]
- 8001adc: f7fe fbac bl 8000238 <strlen>
- 8001ae0: 2300 movs r3, #0
- 8001ae2: 4606 mov r6, r0
- 8001ae4: 19e8 adds r0, r5, r7
- 8001ae6: 0a31 lsrs r1, r6, #8
- 8001ae8: f366 0307 bfi r3, r6, #0, #8
- 8001aec: 0c32 lsrs r2, r6, #16
- 8001aee: f361 230f bfi r3, r1, #8, #8
- 8001af2: 0e31 lsrs r1, r6, #24
- 8001af4: f362 4317 bfi r3, r2, #16, #8
- 8001af8: 4632 mov r2, r6
- 8001afa: f361 631f bfi r3, r1, #24, #8
- 8001afe: f845 3008 str.w r3, [r5, r8]
- 8001b02: 69a1 ldr r1, [r4, #24]
- 8001b04: f008 f932 bl 8009d6c <memcpy>
- 8001b08: edd4 7a0a vldr s15, [r4, #40] ; 0x28
- 8001b0c: 19b8 adds r0, r7, r6
- 8001b0e: ee17 2a90 vmov r2, s15
- 8001b12: 182b adds r3, r5, r0
- 8001b14: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001b18: 2900 cmp r1, #0
- 8001b1a: f000 82bc beq.w 8002096 <_ZNK8nav_msgs8Odometry9serializeEPh+0x622>
- 8001b1e: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001b22: 010e lsls r6, r1, #4
- 8001b24: 0909 lsrs r1, r1, #4
- 8001b26: b276 sxtb r6, r6
- 8001b28: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001b2c: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8001b30: 2700 movs r7, #0
- 8001b32: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001b36: ea46 060c orr.w r6, r6, ip
- 8001b3a: ea4f 0ce2 mov.w ip, r2, asr #3
- 8001b3e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001b42: ea4f 22e2 mov.w r2, r2, asr #11
- 8001b46: 542f strb r7, [r5, r0]
- 8001b48: 715a strb r2, [r3, #5]
- 8001b4a: bf48 it mi
- 8001b4c: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001b50: 719e strb r6, [r3, #6]
- 8001b52: 705f strb r7, [r3, #1]
- 8001b54: 71d9 strb r1, [r3, #7]
- 8001b56: 709f strb r7, [r3, #2]
- 8001b58: f883 e003 strb.w lr, [r3, #3]
- 8001b5c: f883 c004 strb.w ip, [r3, #4]
- 8001b60: edd4 7a0b vldr s15, [r4, #44] ; 0x2c
- 8001b64: ee17 2a90 vmov r2, s15
- 8001b68: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001b6c: 2900 cmp r1, #0
- 8001b6e: f000 8290 beq.w 8002092 <_ZNK8nav_msgs8Odometry9serializeEPh+0x61e>
- 8001b72: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001b76: 010e lsls r6, r1, #4
- 8001b78: 0909 lsrs r1, r1, #4
- 8001b7a: b276 sxtb r6, r6
- 8001b7c: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001b80: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8001b84: 2700 movs r7, #0
- 8001b86: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001b8a: ea46 060c orr.w r6, r6, ip
- 8001b8e: ea4f 0ce2 mov.w ip, r2, asr #3
- 8001b92: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001b96: ea4f 22e2 mov.w r2, r2, asr #11
- 8001b9a: 721f strb r7, [r3, #8]
- 8001b9c: 735a strb r2, [r3, #13]
- 8001b9e: bf48 it mi
- 8001ba0: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001ba4: 739e strb r6, [r3, #14]
- 8001ba6: 725f strb r7, [r3, #9]
- 8001ba8: 73d9 strb r1, [r3, #15]
- 8001baa: 729f strb r7, [r3, #10]
- 8001bac: f883 e00b strb.w lr, [r3, #11]
- 8001bb0: f883 c00c strb.w ip, [r3, #12]
- 8001bb4: edd4 7a0c vldr s15, [r4, #48] ; 0x30
- 8001bb8: ee17 2a90 vmov r2, s15
- 8001bbc: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001bc0: 2900 cmp r1, #0
- 8001bc2: f000 8264 beq.w 800208e <_ZNK8nav_msgs8Odometry9serializeEPh+0x61a>
- 8001bc6: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001bca: 010e lsls r6, r1, #4
- 8001bcc: 0909 lsrs r1, r1, #4
- 8001bce: b276 sxtb r6, r6
- 8001bd0: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001bd4: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8001bd8: 2700 movs r7, #0
- 8001bda: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001bde: ea46 060c orr.w r6, r6, ip
- 8001be2: ea4f 0ce2 mov.w ip, r2, asr #3
- 8001be6: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001bea: ea4f 22e2 mov.w r2, r2, asr #11
- 8001bee: 741f strb r7, [r3, #16]
- 8001bf0: 755a strb r2, [r3, #21]
- 8001bf2: bf48 it mi
- 8001bf4: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001bf8: 759e strb r6, [r3, #22]
- 8001bfa: 745f strb r7, [r3, #17]
- 8001bfc: 75d9 strb r1, [r3, #23]
- 8001bfe: 749f strb r7, [r3, #18]
- 8001c00: f883 e013 strb.w lr, [r3, #19]
- 8001c04: f883 c014 strb.w ip, [r3, #20]
- 8001c08: edd4 7a0e vldr s15, [r4, #56] ; 0x38
- 8001c0c: ee17 2a90 vmov r2, s15
- 8001c10: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001c14: 2900 cmp r1, #0
- 8001c16: f000 8238 beq.w 800208a <_ZNK8nav_msgs8Odometry9serializeEPh+0x616>
- 8001c1a: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001c1e: 010e lsls r6, r1, #4
- 8001c20: 0909 lsrs r1, r1, #4
- 8001c22: b276 sxtb r6, r6
- 8001c24: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001c28: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8001c2c: 2700 movs r7, #0
- 8001c2e: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001c32: ea46 060c orr.w r6, r6, ip
- 8001c36: ea4f 0ce2 mov.w ip, r2, asr #3
- 8001c3a: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001c3e: ea4f 22e2 mov.w r2, r2, asr #11
- 8001c42: 761f strb r7, [r3, #24]
- 8001c44: 775a strb r2, [r3, #29]
- 8001c46: bf48 it mi
- 8001c48: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001c4c: 779e strb r6, [r3, #30]
- 8001c4e: 765f strb r7, [r3, #25]
- 8001c50: 77d9 strb r1, [r3, #31]
- 8001c52: 769f strb r7, [r3, #26]
- 8001c54: f883 e01b strb.w lr, [r3, #27]
- 8001c58: f883 c01c strb.w ip, [r3, #28]
- 8001c5c: edd4 7a0f vldr s15, [r4, #60] ; 0x3c
- 8001c60: ee17 2a90 vmov r2, s15
- 8001c64: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001c68: 2900 cmp r1, #0
- 8001c6a: f000 820c beq.w 8002086 <_ZNK8nav_msgs8Odometry9serializeEPh+0x612>
- 8001c6e: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001c72: 010e lsls r6, r1, #4
- 8001c74: 0909 lsrs r1, r1, #4
- 8001c76: b276 sxtb r6, r6
- 8001c78: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001c7c: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8001c80: 2700 movs r7, #0
- 8001c82: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001c86: ea46 060c orr.w r6, r6, ip
- 8001c8a: ea4f 0ce2 mov.w ip, r2, asr #3
- 8001c8e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001c92: ea4f 22e2 mov.w r2, r2, asr #11
- 8001c96: f883 7020 strb.w r7, [r3, #32]
- 8001c9a: f883 2025 strb.w r2, [r3, #37] ; 0x25
- 8001c9e: bf48 it mi
- 8001ca0: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001ca4: f883 6026 strb.w r6, [r3, #38] ; 0x26
- 8001ca8: f883 7021 strb.w r7, [r3, #33] ; 0x21
- 8001cac: f883 1027 strb.w r1, [r3, #39] ; 0x27
- 8001cb0: f883 7022 strb.w r7, [r3, #34] ; 0x22
- 8001cb4: f883 e023 strb.w lr, [r3, #35] ; 0x23
- 8001cb8: f883 c024 strb.w ip, [r3, #36] ; 0x24
- 8001cbc: edd4 7a10 vldr s15, [r4, #64] ; 0x40
- 8001cc0: ee17 2a90 vmov r2, s15
- 8001cc4: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001cc8: 2900 cmp r1, #0
- 8001cca: f000 81da beq.w 8002082 <_ZNK8nav_msgs8Odometry9serializeEPh+0x60e>
- 8001cce: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001cd2: 010e lsls r6, r1, #4
- 8001cd4: 0909 lsrs r1, r1, #4
- 8001cd6: b276 sxtb r6, r6
- 8001cd8: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001cdc: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8001ce0: 2700 movs r7, #0
- 8001ce2: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001ce6: ea46 060c orr.w r6, r6, ip
- 8001cea: ea4f 0ce2 mov.w ip, r2, asr #3
- 8001cee: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001cf2: ea4f 22e2 mov.w r2, r2, asr #11
- 8001cf6: f883 7028 strb.w r7, [r3, #40] ; 0x28
- 8001cfa: f883 202d strb.w r2, [r3, #45] ; 0x2d
- 8001cfe: bf48 it mi
- 8001d00: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001d04: f883 602e strb.w r6, [r3, #46] ; 0x2e
- 8001d08: f883 7029 strb.w r7, [r3, #41] ; 0x29
- 8001d0c: f883 102f strb.w r1, [r3, #47] ; 0x2f
- 8001d10: f883 702a strb.w r7, [r3, #42] ; 0x2a
- 8001d14: f883 e02b strb.w lr, [r3, #43] ; 0x2b
- 8001d18: f883 c02c strb.w ip, [r3, #44] ; 0x2c
- 8001d1c: edd4 7a11 vldr s15, [r4, #68] ; 0x44
- 8001d20: ee17 2a90 vmov r2, s15
- 8001d24: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001d28: 2900 cmp r1, #0
- 8001d2a: f000 81a8 beq.w 800207e <_ZNK8nav_msgs8Odometry9serializeEPh+0x60a>
- 8001d2e: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001d32: 010e lsls r6, r1, #4
- 8001d34: 0909 lsrs r1, r1, #4
- 8001d36: b276 sxtb r6, r6
- 8001d38: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001d3c: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8001d40: 2700 movs r7, #0
- 8001d42: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001d46: ea46 060c orr.w r6, r6, ip
- 8001d4a: ea4f 0ce2 mov.w ip, r2, asr #3
- 8001d4e: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001d52: f883 7030 strb.w r7, [r3, #48] ; 0x30
- 8001d56: ea4f 22e2 mov.w r2, r2, asr #11
- 8001d5a: f883 7031 strb.w r7, [r3, #49] ; 0x31
- 8001d5e: f883 7032 strb.w r7, [r3, #50] ; 0x32
- 8001d62: f04f 0700 mov.w r7, #0
- 8001d66: f883 e033 strb.w lr, [r3, #51] ; 0x33
- 8001d6a: bf48 it mi
- 8001d6c: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001d70: f883 c034 strb.w ip, [r3, #52] ; 0x34
- 8001d74: f104 0ed8 add.w lr, r4, #216 ; 0xd8
- 8001d78: f104 0c48 add.w ip, r4, #72 ; 0x48
- 8001d7c: f883 6036 strb.w r6, [r3, #54] ; 0x36
- 8001d80: f883 2035 strb.w r2, [r3, #53] ; 0x35
- 8001d84: f883 1037 strb.w r1, [r3, #55] ; 0x37
- 8001d88: ecfc 7a01 vldmia ip!, {s15}
- 8001d8c: ee17 2a90 vmov r2, s15
- 8001d90: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001d94: 460e mov r6, r1
- 8001d96: f501 7860 add.w r8, r1, #896 ; 0x380
- 8001d9a: b121 cbz r1, 8001da6 <_ZNK8nav_msgs8Odometry9serializeEPh+0x332>
- 8001d9c: ea4f 1108 mov.w r1, r8, lsl #4
- 8001da0: ea4f 1618 mov.w r6, r8, lsr #4
- 8001da4: b249 sxtb r1, r1
- 8001da6: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001daa: f3c2 4ac3 ubfx sl, r2, #19, #4
- 8001dae: ea4f 1942 mov.w r9, r2, lsl #5
- 8001db2: f883 7038 strb.w r7, [r3, #56] ; 0x38
- 8001db6: ea4f 08e2 mov.w r8, r2, asr #3
- 8001dba: ea41 010a orr.w r1, r1, sl
- 8001dbe: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001dc2: ea4f 22e2 mov.w r2, r2, asr #11
- 8001dc6: f883 7039 strb.w r7, [r3, #57] ; 0x39
- 8001dca: f103 0308 add.w r3, r3, #8
- 8001dce: f883 7032 strb.w r7, [r3, #50] ; 0x32
- 8001dd2: bf48 it mi
- 8001dd4: f066 067f ornmi r6, r6, #127 ; 0x7f
- 8001dd8: 45e6 cmp lr, ip
- 8001dda: f883 1036 strb.w r1, [r3, #54] ; 0x36
- 8001dde: f883 9033 strb.w r9, [r3, #51] ; 0x33
- 8001de2: f883 8034 strb.w r8, [r3, #52] ; 0x34
- 8001de6: f883 2035 strb.w r2, [r3, #53] ; 0x35
- 8001dea: f883 6037 strb.w r6, [r3, #55] ; 0x37
- 8001dee: d1cb bne.n 8001d88 <_ZNK8nav_msgs8Odometry9serializeEPh+0x314>
- 8001df0: edd4 7a39 vldr s15, [r4, #228] ; 0xe4
- 8001df4: f500 7cac add.w ip, r0, #344 ; 0x158
- 8001df8: ee17 2a90 vmov r2, s15
- 8001dfc: eb05 030c add.w r3, r5, ip
- 8001e00: f3c2 56c7 ubfx r6, r2, #23, #8
- 8001e04: 2e00 cmp r6, #0
- 8001e06: f000 8138 beq.w 800207a <_ZNK8nav_msgs8Odometry9serializeEPh+0x606>
- 8001e0a: f506 7660 add.w r6, r6, #896 ; 0x380
- 8001e0e: 0131 lsls r1, r6, #4
- 8001e10: 0936 lsrs r6, r6, #4
- 8001e12: b249 sxtb r1, r1
- 8001e14: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001e18: f3c2 4ec3 ubfx lr, r2, #19, #4
- 8001e1c: 2700 movs r7, #0
- 8001e1e: ea41 010e orr.w r1, r1, lr
- 8001e22: ea4f 1e42 mov.w lr, r2, lsl #5
- 8001e26: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001e2a: f805 700c strb.w r7, [r5, ip]
- 8001e2e: ea4f 05e2 mov.w r5, r2, asr #3
- 8001e32: 7199 strb r1, [r3, #6]
- 8001e34: ea4f 22e2 mov.w r2, r2, asr #11
- 8001e38: 705f strb r7, [r3, #1]
- 8001e3a: 709f strb r7, [r3, #2]
- 8001e3c: f883 e003 strb.w lr, [r3, #3]
- 8001e40: 711d strb r5, [r3, #4]
- 8001e42: 715a strb r2, [r3, #5]
- 8001e44: f100 8129 bmi.w 800209a <_ZNK8nav_msgs8Odometry9serializeEPh+0x626>
- 8001e48: 71de strb r6, [r3, #7]
- 8001e4a: edd4 7a3a vldr s15, [r4, #232] ; 0xe8
- 8001e4e: ee17 2a90 vmov r2, s15
- 8001e52: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001e56: 2900 cmp r1, #0
- 8001e58: f000 810d beq.w 8002076 <_ZNK8nav_msgs8Odometry9serializeEPh+0x602>
- 8001e5c: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001e60: 010d lsls r5, r1, #4
- 8001e62: 0909 lsrs r1, r1, #4
- 8001e64: b26d sxtb r5, r5
- 8001e66: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001e6a: f3c2 47c3 ubfx r7, r2, #19, #4
- 8001e6e: 2600 movs r6, #0
- 8001e70: ea4f 1c42 mov.w ip, r2, lsl #5
- 8001e74: 433d orrs r5, r7
- 8001e76: 10d7 asrs r7, r2, #3
- 8001e78: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001e7c: ea4f 22e2 mov.w r2, r2, asr #11
- 8001e80: 721e strb r6, [r3, #8]
- 8001e82: 735a strb r2, [r3, #13]
- 8001e84: bf48 it mi
- 8001e86: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001e8a: 739d strb r5, [r3, #14]
- 8001e8c: 725e strb r6, [r3, #9]
- 8001e8e: 73d9 strb r1, [r3, #15]
- 8001e90: 729e strb r6, [r3, #10]
- 8001e92: f883 c00b strb.w ip, [r3, #11]
- 8001e96: 731f strb r7, [r3, #12]
- 8001e98: edd4 7a3b vldr s15, [r4, #236] ; 0xec
- 8001e9c: ee17 2a90 vmov r2, s15
- 8001ea0: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001ea4: 2900 cmp r1, #0
- 8001ea6: f000 80e4 beq.w 8002072 <_ZNK8nav_msgs8Odometry9serializeEPh+0x5fe>
- 8001eaa: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001eae: 010d lsls r5, r1, #4
- 8001eb0: 0909 lsrs r1, r1, #4
- 8001eb2: b26d sxtb r5, r5
- 8001eb4: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001eb8: f3c2 47c3 ubfx r7, r2, #19, #4
- 8001ebc: 2600 movs r6, #0
- 8001ebe: ea4f 1c42 mov.w ip, r2, lsl #5
- 8001ec2: 433d orrs r5, r7
- 8001ec4: 10d7 asrs r7, r2, #3
- 8001ec6: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001eca: ea4f 22e2 mov.w r2, r2, asr #11
- 8001ece: 741e strb r6, [r3, #16]
- 8001ed0: 755a strb r2, [r3, #21]
- 8001ed2: bf48 it mi
- 8001ed4: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001ed8: 759d strb r5, [r3, #22]
- 8001eda: 745e strb r6, [r3, #17]
- 8001edc: 75d9 strb r1, [r3, #23]
- 8001ede: 749e strb r6, [r3, #18]
- 8001ee0: f883 c013 strb.w ip, [r3, #19]
- 8001ee4: 751f strb r7, [r3, #20]
- 8001ee6: edd4 7a3d vldr s15, [r4, #244] ; 0xf4
- 8001eea: ee17 2a90 vmov r2, s15
- 8001eee: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001ef2: 2900 cmp r1, #0
- 8001ef4: f000 80bb beq.w 800206e <_ZNK8nav_msgs8Odometry9serializeEPh+0x5fa>
- 8001ef8: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001efc: 010d lsls r5, r1, #4
- 8001efe: 0909 lsrs r1, r1, #4
- 8001f00: b26d sxtb r5, r5
- 8001f02: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001f06: f3c2 47c3 ubfx r7, r2, #19, #4
- 8001f0a: 2600 movs r6, #0
- 8001f0c: ea4f 1c42 mov.w ip, r2, lsl #5
- 8001f10: 433d orrs r5, r7
- 8001f12: 10d7 asrs r7, r2, #3
- 8001f14: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001f18: ea4f 22e2 mov.w r2, r2, asr #11
- 8001f1c: 761e strb r6, [r3, #24]
- 8001f1e: 775a strb r2, [r3, #29]
- 8001f20: bf48 it mi
- 8001f22: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001f26: 779d strb r5, [r3, #30]
- 8001f28: 765e strb r6, [r3, #25]
- 8001f2a: 77d9 strb r1, [r3, #31]
- 8001f2c: 769e strb r6, [r3, #26]
- 8001f2e: f883 c01b strb.w ip, [r3, #27]
- 8001f32: 771f strb r7, [r3, #28]
- 8001f34: edd4 7a3e vldr s15, [r4, #248] ; 0xf8
- 8001f38: ee17 2a90 vmov r2, s15
- 8001f3c: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001f40: 2900 cmp r1, #0
- 8001f42: f000 8092 beq.w 800206a <_ZNK8nav_msgs8Odometry9serializeEPh+0x5f6>
- 8001f46: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001f4a: 010d lsls r5, r1, #4
- 8001f4c: 0909 lsrs r1, r1, #4
- 8001f4e: b26d sxtb r5, r5
- 8001f50: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001f54: f3c2 47c3 ubfx r7, r2, #19, #4
- 8001f58: 2600 movs r6, #0
- 8001f5a: ea4f 1c42 mov.w ip, r2, lsl #5
- 8001f5e: 433d orrs r5, r7
- 8001f60: 10d7 asrs r7, r2, #3
- 8001f62: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001f66: ea4f 22e2 mov.w r2, r2, asr #11
- 8001f6a: f883 6020 strb.w r6, [r3, #32]
- 8001f6e: f883 2025 strb.w r2, [r3, #37] ; 0x25
- 8001f72: bf48 it mi
- 8001f74: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001f78: f883 5026 strb.w r5, [r3, #38] ; 0x26
- 8001f7c: f883 6021 strb.w r6, [r3, #33] ; 0x21
- 8001f80: f883 1027 strb.w r1, [r3, #39] ; 0x27
- 8001f84: f883 6022 strb.w r6, [r3, #34] ; 0x22
- 8001f88: f883 c023 strb.w ip, [r3, #35] ; 0x23
- 8001f8c: f883 7024 strb.w r7, [r3, #36] ; 0x24
- 8001f90: edd4 7a3f vldr s15, [r4, #252] ; 0xfc
- 8001f94: ee17 2a90 vmov r2, s15
- 8001f98: f3c2 51c7 ubfx r1, r2, #23, #8
- 8001f9c: 2900 cmp r1, #0
- 8001f9e: d062 beq.n 8002066 <_ZNK8nav_msgs8Odometry9serializeEPh+0x5f2>
- 8001fa0: f501 7160 add.w r1, r1, #896 ; 0x380
- 8001fa4: 010d lsls r5, r1, #4
- 8001fa6: 0909 lsrs r1, r1, #4
- 8001fa8: b26d sxtb r5, r5
- 8001faa: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8001fae: f3c2 47c3 ubfx r7, r2, #19, #4
- 8001fb2: 2600 movs r6, #0
- 8001fb4: ea4f 1c42 mov.w ip, r2, lsl #5
- 8001fb8: 433d orrs r5, r7
- 8001fba: 10d7 asrs r7, r2, #3
- 8001fbc: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8001fc0: f883 6028 strb.w r6, [r3, #40] ; 0x28
- 8001fc4: ea4f 22e2 mov.w r2, r2, asr #11
- 8001fc8: f883 6029 strb.w r6, [r3, #41] ; 0x29
- 8001fcc: f883 602a strb.w r6, [r3, #42] ; 0x2a
- 8001fd0: f04f 0600 mov.w r6, #0
- 8001fd4: f883 702c strb.w r7, [r3, #44] ; 0x2c
- 8001fd8: bf48 it mi
- 8001fda: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8001fde: f504 7780 add.w r7, r4, #256 ; 0x100
- 8001fe2: f504 74c8 add.w r4, r4, #400 ; 0x190
- 8001fe6: f883 502e strb.w r5, [r3, #46] ; 0x2e
- 8001fea: f883 c02b strb.w ip, [r3, #43] ; 0x2b
- 8001fee: f883 202d strb.w r2, [r3, #45] ; 0x2d
- 8001ff2: f883 102f strb.w r1, [r3, #47] ; 0x2f
- 8001ff6: ecf7 7a01 vldmia r7!, {s15}
- 8001ffa: ee17 2a90 vmov r2, s15
- 8001ffe: f3c2 51c7 ubfx r1, r2, #23, #8
- 8002002: 460d mov r5, r1
- 8002004: f501 7c60 add.w ip, r1, #896 ; 0x380
- 8002008: b121 cbz r1, 8002014 <_ZNK8nav_msgs8Odometry9serializeEPh+0x5a0>
- 800200a: ea4f 110c mov.w r1, ip, lsl #4
- 800200e: ea4f 151c mov.w r5, ip, lsr #4
- 8002012: b249 sxtb r1, r1
- 8002014: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8002018: f3c2 48c3 ubfx r8, r2, #19, #4
- 800201c: ea4f 1e42 mov.w lr, r2, lsl #5
- 8002020: f883 6030 strb.w r6, [r3, #48] ; 0x30
- 8002024: ea4f 0ce2 mov.w ip, r2, asr #3
- 8002028: ea41 0108 orr.w r1, r1, r8
- 800202c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8002030: ea4f 22e2 mov.w r2, r2, asr #11
- 8002034: f883 6031 strb.w r6, [r3, #49] ; 0x31
- 8002038: f103 0308 add.w r3, r3, #8
- 800203c: f883 602a strb.w r6, [r3, #42] ; 0x2a
- 8002040: bf48 it mi
- 8002042: f065 057f ornmi r5, r5, #127 ; 0x7f
- 8002046: 42bc cmp r4, r7
- 8002048: f883 102e strb.w r1, [r3, #46] ; 0x2e
- 800204c: f883 e02b strb.w lr, [r3, #43] ; 0x2b
- 8002050: f883 c02c strb.w ip, [r3, #44] ; 0x2c
- 8002054: f883 202d strb.w r2, [r3, #45] ; 0x2d
- 8002058: f883 502f strb.w r5, [r3, #47] ; 0x2f
- 800205c: d1cb bne.n 8001ff6 <_ZNK8nav_msgs8Odometry9serializeEPh+0x582>
- 800205e: f500 702a add.w r0, r0, #680 ; 0x2a8
- 8002062: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8002066: 460d mov r5, r1
- 8002068: e79f b.n 8001faa <_ZNK8nav_msgs8Odometry9serializeEPh+0x536>
- 800206a: 460d mov r5, r1
- 800206c: e770 b.n 8001f50 <_ZNK8nav_msgs8Odometry9serializeEPh+0x4dc>
- 800206e: 460d mov r5, r1
- 8002070: e747 b.n 8001f02 <_ZNK8nav_msgs8Odometry9serializeEPh+0x48e>
- 8002072: 460d mov r5, r1
- 8002074: e71e b.n 8001eb4 <_ZNK8nav_msgs8Odometry9serializeEPh+0x440>
- 8002076: 460d mov r5, r1
- 8002078: e6f5 b.n 8001e66 <_ZNK8nav_msgs8Odometry9serializeEPh+0x3f2>
- 800207a: 4631 mov r1, r6
- 800207c: e6ca b.n 8001e14 <_ZNK8nav_msgs8Odometry9serializeEPh+0x3a0>
- 800207e: 460e mov r6, r1
- 8002080: e65a b.n 8001d38 <_ZNK8nav_msgs8Odometry9serializeEPh+0x2c4>
- 8002082: 460e mov r6, r1
- 8002084: e628 b.n 8001cd8 <_ZNK8nav_msgs8Odometry9serializeEPh+0x264>
- 8002086: 460e mov r6, r1
- 8002088: e5f6 b.n 8001c78 <_ZNK8nav_msgs8Odometry9serializeEPh+0x204>
- 800208a: 460e mov r6, r1
- 800208c: e5ca b.n 8001c24 <_ZNK8nav_msgs8Odometry9serializeEPh+0x1b0>
- 800208e: 460e mov r6, r1
- 8002090: e59e b.n 8001bd0 <_ZNK8nav_msgs8Odometry9serializeEPh+0x15c>
- 8002092: 460e mov r6, r1
- 8002094: e572 b.n 8001b7c <_ZNK8nav_msgs8Odometry9serializeEPh+0x108>
- 8002096: 460e mov r6, r1
- 8002098: e546 b.n 8001b28 <_ZNK8nav_msgs8Odometry9serializeEPh+0xb4>
- 800209a: f066 017f orn r1, r6, #127 ; 0x7f
- 800209e: 71d9 strb r1, [r3, #7]
- 80020a0: e6d3 b.n 8001e4a <_ZNK8nav_msgs8Odometry9serializeEPh+0x3d6>
- 80020a2: bf00 nop
-
-080020a4 <_ZN13geometry_msgs5Twist11deserializeEPh>:
- 80020a4: b430 push {r4, r5}
- 80020a6: 78ca ldrb r2, [r1, #3]
- 80020a8: 4603 mov r3, r0
- 80020aa: 0952 lsrs r2, r2, #5
- 80020ac: 6082 str r2, [r0, #8]
- 80020ae: 7908 ldrb r0, [r1, #4]
- 80020b0: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 80020b4: 609a str r2, [r3, #8]
- 80020b6: 7948 ldrb r0, [r1, #5]
- 80020b8: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 80020bc: 609a str r2, [r3, #8]
- 80020be: 7988 ldrb r0, [r1, #6]
- 80020c0: 04c0 lsls r0, r0, #19
- 80020c2: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 80020c6: 4302 orrs r2, r0
- 80020c8: 609a str r2, [r3, #8]
- 80020ca: 79c8 ldrb r0, [r1, #7]
- 80020cc: 798d ldrb r5, [r1, #6]
- 80020ce: 0104 lsls r4, r0, #4
- 80020d0: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80020d4: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80020d8: d005 beq.n 80020e6 <_ZN13geometry_msgs5Twist11deserializeEPh+0x42>
- 80020da: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80020de: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 80020e2: 609a str r2, [r3, #8]
- 80020e4: 79c8 ldrb r0, [r1, #7]
- 80020e6: 0600 lsls r0, r0, #24
- 80020e8: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 80020ec: 4302 orrs r2, r0
- 80020ee: 609a str r2, [r3, #8]
- 80020f0: 7aca ldrb r2, [r1, #11]
- 80020f2: 0952 lsrs r2, r2, #5
- 80020f4: 60da str r2, [r3, #12]
- 80020f6: 7b08 ldrb r0, [r1, #12]
- 80020f8: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 80020fc: 60da str r2, [r3, #12]
- 80020fe: 7b48 ldrb r0, [r1, #13]
- 8002100: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002104: 60da str r2, [r3, #12]
- 8002106: 7b88 ldrb r0, [r1, #14]
- 8002108: 04c0 lsls r0, r0, #19
- 800210a: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 800210e: 4302 orrs r2, r0
- 8002110: 60da str r2, [r3, #12]
- 8002112: 7bc8 ldrb r0, [r1, #15]
- 8002114: 7b8d ldrb r5, [r1, #14]
- 8002116: 0104 lsls r4, r0, #4
- 8002118: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800211c: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002120: d005 beq.n 800212e <_ZN13geometry_msgs5Twist11deserializeEPh+0x8a>
- 8002122: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002126: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 800212a: 60da str r2, [r3, #12]
- 800212c: 7bc8 ldrb r0, [r1, #15]
- 800212e: 0600 lsls r0, r0, #24
- 8002130: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002134: 4302 orrs r2, r0
- 8002136: 60da str r2, [r3, #12]
- 8002138: 7cca ldrb r2, [r1, #19]
- 800213a: 0952 lsrs r2, r2, #5
- 800213c: 611a str r2, [r3, #16]
- 800213e: 7d08 ldrb r0, [r1, #20]
- 8002140: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002144: 611a str r2, [r3, #16]
- 8002146: 7d48 ldrb r0, [r1, #21]
- 8002148: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 800214c: 611a str r2, [r3, #16]
- 800214e: 7d88 ldrb r0, [r1, #22]
- 8002150: 04c0 lsls r0, r0, #19
- 8002152: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002156: 4302 orrs r2, r0
- 8002158: 611a str r2, [r3, #16]
- 800215a: 7dc8 ldrb r0, [r1, #23]
- 800215c: 7d8d ldrb r5, [r1, #22]
- 800215e: 0104 lsls r4, r0, #4
- 8002160: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002164: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002168: d005 beq.n 8002176 <_ZN13geometry_msgs5Twist11deserializeEPh+0xd2>
- 800216a: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 800216e: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002172: 611a str r2, [r3, #16]
- 8002174: 7dc8 ldrb r0, [r1, #23]
- 8002176: 0600 lsls r0, r0, #24
- 8002178: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 800217c: 4302 orrs r2, r0
- 800217e: 611a str r2, [r3, #16]
- 8002180: 7eca ldrb r2, [r1, #27]
- 8002182: 0952 lsrs r2, r2, #5
- 8002184: 619a str r2, [r3, #24]
- 8002186: 7f08 ldrb r0, [r1, #28]
- 8002188: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 800218c: 619a str r2, [r3, #24]
- 800218e: 7f48 ldrb r0, [r1, #29]
- 8002190: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002194: 619a str r2, [r3, #24]
- 8002196: 7f88 ldrb r0, [r1, #30]
- 8002198: 04c0 lsls r0, r0, #19
- 800219a: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 800219e: 4302 orrs r2, r0
- 80021a0: 619a str r2, [r3, #24]
- 80021a2: 7fc8 ldrb r0, [r1, #31]
- 80021a4: 7f8d ldrb r5, [r1, #30]
- 80021a6: 0104 lsls r4, r0, #4
- 80021a8: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80021ac: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80021b0: d005 beq.n 80021be <_ZN13geometry_msgs5Twist11deserializeEPh+0x11a>
- 80021b2: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80021b6: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 80021ba: 619a str r2, [r3, #24]
- 80021bc: 7fc8 ldrb r0, [r1, #31]
- 80021be: 0600 lsls r0, r0, #24
- 80021c0: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 80021c4: 4302 orrs r2, r0
- 80021c6: 619a str r2, [r3, #24]
- 80021c8: f891 2023 ldrb.w r2, [r1, #35] ; 0x23
- 80021cc: 0952 lsrs r2, r2, #5
- 80021ce: 61da str r2, [r3, #28]
- 80021d0: f891 0024 ldrb.w r0, [r1, #36] ; 0x24
- 80021d4: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 80021d8: 61da str r2, [r3, #28]
- 80021da: f891 0025 ldrb.w r0, [r1, #37] ; 0x25
- 80021de: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 80021e2: 61da str r2, [r3, #28]
- 80021e4: f891 0026 ldrb.w r0, [r1, #38] ; 0x26
- 80021e8: 04c0 lsls r0, r0, #19
- 80021ea: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 80021ee: 4302 orrs r2, r0
- 80021f0: 61da str r2, [r3, #28]
- 80021f2: f891 0027 ldrb.w r0, [r1, #39] ; 0x27
- 80021f6: f891 5026 ldrb.w r5, [r1, #38] ; 0x26
- 80021fa: 0104 lsls r4, r0, #4
- 80021fc: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002200: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002204: d006 beq.n 8002214 <_ZN13geometry_msgs5Twist11deserializeEPh+0x170>
- 8002206: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 800220a: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 800220e: 61da str r2, [r3, #28]
- 8002210: f891 0027 ldrb.w r0, [r1, #39] ; 0x27
- 8002214: 0600 lsls r0, r0, #24
- 8002216: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 800221a: 4302 orrs r2, r0
- 800221c: 61da str r2, [r3, #28]
- 800221e: f891 202b ldrb.w r2, [r1, #43] ; 0x2b
- 8002222: 0952 lsrs r2, r2, #5
- 8002224: 621a str r2, [r3, #32]
- 8002226: f891 002c ldrb.w r0, [r1, #44] ; 0x2c
- 800222a: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 800222e: 621a str r2, [r3, #32]
- 8002230: f891 002d ldrb.w r0, [r1, #45] ; 0x2d
- 8002234: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002238: 621a str r2, [r3, #32]
- 800223a: f891 002e ldrb.w r0, [r1, #46] ; 0x2e
- 800223e: 04c0 lsls r0, r0, #19
- 8002240: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002244: 4302 orrs r2, r0
- 8002246: 621a str r2, [r3, #32]
- 8002248: f891 002f ldrb.w r0, [r1, #47] ; 0x2f
- 800224c: f891 502e ldrb.w r5, [r1, #46] ; 0x2e
- 8002250: 0104 lsls r4, r0, #4
- 8002252: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002256: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 800225a: d006 beq.n 800226a <_ZN13geometry_msgs5Twist11deserializeEPh+0x1c6>
- 800225c: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002260: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002264: 621a str r2, [r3, #32]
- 8002266: f891 002f ldrb.w r0, [r1, #47] ; 0x2f
- 800226a: 0601 lsls r1, r0, #24
- 800226c: 2030 movs r0, #48 ; 0x30
- 800226e: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
- 8002272: 430a orrs r2, r1
- 8002274: bc30 pop {r4, r5}
- 8002276: 621a str r2, [r3, #32]
- 8002278: 4770 bx lr
- 800227a: bf00 nop
-
-0800227c <_ZN13geometry_msgs4Pose11deserializeEPh>:
- 800227c: b430 push {r4, r5}
- 800227e: 78ca ldrb r2, [r1, #3]
- 8002280: 4603 mov r3, r0
- 8002282: 0952 lsrs r2, r2, #5
- 8002284: 6082 str r2, [r0, #8]
- 8002286: 7908 ldrb r0, [r1, #4]
- 8002288: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 800228c: 609a str r2, [r3, #8]
- 800228e: 7948 ldrb r0, [r1, #5]
- 8002290: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002294: 609a str r2, [r3, #8]
- 8002296: 7988 ldrb r0, [r1, #6]
- 8002298: 04c0 lsls r0, r0, #19
- 800229a: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 800229e: 4302 orrs r2, r0
- 80022a0: 609a str r2, [r3, #8]
- 80022a2: 79c8 ldrb r0, [r1, #7]
- 80022a4: 798d ldrb r5, [r1, #6]
- 80022a6: 0104 lsls r4, r0, #4
- 80022a8: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80022ac: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80022b0: d005 beq.n 80022be <_ZN13geometry_msgs4Pose11deserializeEPh+0x42>
- 80022b2: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80022b6: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 80022ba: 609a str r2, [r3, #8]
- 80022bc: 79c8 ldrb r0, [r1, #7]
- 80022be: 0600 lsls r0, r0, #24
- 80022c0: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 80022c4: 4302 orrs r2, r0
- 80022c6: 609a str r2, [r3, #8]
- 80022c8: 7aca ldrb r2, [r1, #11]
- 80022ca: 0952 lsrs r2, r2, #5
- 80022cc: 60da str r2, [r3, #12]
- 80022ce: 7b08 ldrb r0, [r1, #12]
- 80022d0: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 80022d4: 60da str r2, [r3, #12]
- 80022d6: 7b48 ldrb r0, [r1, #13]
- 80022d8: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 80022dc: 60da str r2, [r3, #12]
- 80022de: 7b88 ldrb r0, [r1, #14]
- 80022e0: 04c0 lsls r0, r0, #19
- 80022e2: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 80022e6: 4302 orrs r2, r0
- 80022e8: 60da str r2, [r3, #12]
- 80022ea: 7bc8 ldrb r0, [r1, #15]
- 80022ec: 7b8d ldrb r5, [r1, #14]
- 80022ee: 0104 lsls r4, r0, #4
- 80022f0: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80022f4: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80022f8: d005 beq.n 8002306 <_ZN13geometry_msgs4Pose11deserializeEPh+0x8a>
- 80022fa: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80022fe: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002302: 60da str r2, [r3, #12]
- 8002304: 7bc8 ldrb r0, [r1, #15]
- 8002306: 0600 lsls r0, r0, #24
- 8002308: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 800230c: 4302 orrs r2, r0
- 800230e: 60da str r2, [r3, #12]
- 8002310: 7cca ldrb r2, [r1, #19]
- 8002312: 0952 lsrs r2, r2, #5
- 8002314: 611a str r2, [r3, #16]
- 8002316: 7d08 ldrb r0, [r1, #20]
- 8002318: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 800231c: 611a str r2, [r3, #16]
- 800231e: 7d48 ldrb r0, [r1, #21]
- 8002320: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002324: 611a str r2, [r3, #16]
- 8002326: 7d88 ldrb r0, [r1, #22]
- 8002328: 04c0 lsls r0, r0, #19
- 800232a: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 800232e: 4302 orrs r2, r0
- 8002330: 611a str r2, [r3, #16]
- 8002332: 7dc8 ldrb r0, [r1, #23]
- 8002334: 7d8d ldrb r5, [r1, #22]
- 8002336: 0104 lsls r4, r0, #4
- 8002338: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800233c: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002340: d005 beq.n 800234e <_ZN13geometry_msgs4Pose11deserializeEPh+0xd2>
- 8002342: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002346: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 800234a: 611a str r2, [r3, #16]
- 800234c: 7dc8 ldrb r0, [r1, #23]
- 800234e: 0600 lsls r0, r0, #24
- 8002350: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002354: 4302 orrs r2, r0
- 8002356: 611a str r2, [r3, #16]
- 8002358: 7eca ldrb r2, [r1, #27]
- 800235a: 0952 lsrs r2, r2, #5
- 800235c: 619a str r2, [r3, #24]
- 800235e: 7f08 ldrb r0, [r1, #28]
- 8002360: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002364: 619a str r2, [r3, #24]
- 8002366: 7f48 ldrb r0, [r1, #29]
- 8002368: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 800236c: 619a str r2, [r3, #24]
- 800236e: 7f88 ldrb r0, [r1, #30]
- 8002370: 04c0 lsls r0, r0, #19
- 8002372: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002376: 4302 orrs r2, r0
- 8002378: 619a str r2, [r3, #24]
- 800237a: 7fc8 ldrb r0, [r1, #31]
- 800237c: 7f8d ldrb r5, [r1, #30]
- 800237e: 0104 lsls r4, r0, #4
- 8002380: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002384: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002388: d005 beq.n 8002396 <_ZN13geometry_msgs4Pose11deserializeEPh+0x11a>
- 800238a: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 800238e: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002392: 619a str r2, [r3, #24]
- 8002394: 7fc8 ldrb r0, [r1, #31]
- 8002396: 0600 lsls r0, r0, #24
- 8002398: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 800239c: 4302 orrs r2, r0
- 800239e: 619a str r2, [r3, #24]
- 80023a0: f891 2023 ldrb.w r2, [r1, #35] ; 0x23
- 80023a4: 0952 lsrs r2, r2, #5
- 80023a6: 61da str r2, [r3, #28]
- 80023a8: f891 0024 ldrb.w r0, [r1, #36] ; 0x24
- 80023ac: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 80023b0: 61da str r2, [r3, #28]
- 80023b2: f891 0025 ldrb.w r0, [r1, #37] ; 0x25
- 80023b6: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 80023ba: 61da str r2, [r3, #28]
- 80023bc: f891 0026 ldrb.w r0, [r1, #38] ; 0x26
- 80023c0: 04c0 lsls r0, r0, #19
- 80023c2: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 80023c6: 4302 orrs r2, r0
- 80023c8: 61da str r2, [r3, #28]
- 80023ca: f891 0027 ldrb.w r0, [r1, #39] ; 0x27
- 80023ce: f891 5026 ldrb.w r5, [r1, #38] ; 0x26
- 80023d2: 0104 lsls r4, r0, #4
- 80023d4: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80023d8: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80023dc: d006 beq.n 80023ec <_ZN13geometry_msgs4Pose11deserializeEPh+0x170>
- 80023de: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80023e2: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 80023e6: 61da str r2, [r3, #28]
- 80023e8: f891 0027 ldrb.w r0, [r1, #39] ; 0x27
- 80023ec: 0600 lsls r0, r0, #24
- 80023ee: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 80023f2: 4302 orrs r2, r0
- 80023f4: 61da str r2, [r3, #28]
- 80023f6: f891 202b ldrb.w r2, [r1, #43] ; 0x2b
- 80023fa: 0952 lsrs r2, r2, #5
- 80023fc: 621a str r2, [r3, #32]
- 80023fe: f891 002c ldrb.w r0, [r1, #44] ; 0x2c
- 8002402: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002406: 621a str r2, [r3, #32]
- 8002408: f891 002d ldrb.w r0, [r1, #45] ; 0x2d
- 800240c: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002410: 621a str r2, [r3, #32]
- 8002412: f891 002e ldrb.w r0, [r1, #46] ; 0x2e
- 8002416: 04c0 lsls r0, r0, #19
- 8002418: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 800241c: 4302 orrs r2, r0
- 800241e: 621a str r2, [r3, #32]
- 8002420: f891 002f ldrb.w r0, [r1, #47] ; 0x2f
- 8002424: f891 502e ldrb.w r5, [r1, #46] ; 0x2e
- 8002428: 0104 lsls r4, r0, #4
- 800242a: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800242e: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002432: d006 beq.n 8002442 <_ZN13geometry_msgs4Pose11deserializeEPh+0x1c6>
- 8002434: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002438: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 800243c: 621a str r2, [r3, #32]
- 800243e: f891 002f ldrb.w r0, [r1, #47] ; 0x2f
- 8002442: 0600 lsls r0, r0, #24
- 8002444: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002448: 4302 orrs r2, r0
- 800244a: 621a str r2, [r3, #32]
- 800244c: f891 2033 ldrb.w r2, [r1, #51] ; 0x33
- 8002450: 0952 lsrs r2, r2, #5
- 8002452: 625a str r2, [r3, #36] ; 0x24
- 8002454: f891 0034 ldrb.w r0, [r1, #52] ; 0x34
- 8002458: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 800245c: 625a str r2, [r3, #36] ; 0x24
- 800245e: f891 0035 ldrb.w r0, [r1, #53] ; 0x35
- 8002462: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002466: 625a str r2, [r3, #36] ; 0x24
- 8002468: f891 0036 ldrb.w r0, [r1, #54] ; 0x36
- 800246c: 04c0 lsls r0, r0, #19
- 800246e: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002472: 4302 orrs r2, r0
- 8002474: 625a str r2, [r3, #36] ; 0x24
- 8002476: f891 0037 ldrb.w r0, [r1, #55] ; 0x37
- 800247a: f891 5036 ldrb.w r5, [r1, #54] ; 0x36
- 800247e: 0104 lsls r4, r0, #4
- 8002480: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002484: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002488: d006 beq.n 8002498 <_ZN13geometry_msgs4Pose11deserializeEPh+0x21c>
- 800248a: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 800248e: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002492: 625a str r2, [r3, #36] ; 0x24
- 8002494: f891 0037 ldrb.w r0, [r1, #55] ; 0x37
- 8002498: 0601 lsls r1, r0, #24
- 800249a: 2038 movs r0, #56 ; 0x38
- 800249c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
- 80024a0: 430a orrs r2, r1
- 80024a2: bc30 pop {r4, r5}
- 80024a4: 625a str r2, [r3, #36] ; 0x24
- 80024a6: 4770 bx lr
-
-080024a8 <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh>:
- 80024a8: 78cb ldrb r3, [r1, #3]
- 80024aa: 095b lsrs r3, r3, #5
- 80024ac: b470 push {r4, r5, r6}
- 80024ae: 60c3 str r3, [r0, #12]
- 80024b0: 790a ldrb r2, [r1, #4]
- 80024b2: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80024b6: 60c3 str r3, [r0, #12]
- 80024b8: 794a ldrb r2, [r1, #5]
- 80024ba: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 80024be: 60c3 str r3, [r0, #12]
- 80024c0: 798a ldrb r2, [r1, #6]
- 80024c2: 04d2 lsls r2, r2, #19
- 80024c4: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80024c8: 4313 orrs r3, r2
- 80024ca: 60c3 str r3, [r0, #12]
- 80024cc: 79ca ldrb r2, [r1, #7]
- 80024ce: 798d ldrb r5, [r1, #6]
- 80024d0: 0114 lsls r4, r2, #4
- 80024d2: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80024d6: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80024da: d005 beq.n 80024e8 <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x40>
- 80024dc: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80024e0: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 80024e4: 60c3 str r3, [r0, #12]
- 80024e6: 79ca ldrb r2, [r1, #7]
- 80024e8: 0612 lsls r2, r2, #24
- 80024ea: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80024ee: 4313 orrs r3, r2
- 80024f0: 60c3 str r3, [r0, #12]
- 80024f2: 7acb ldrb r3, [r1, #11]
- 80024f4: 095b lsrs r3, r3, #5
- 80024f6: 6103 str r3, [r0, #16]
- 80024f8: 7b0a ldrb r2, [r1, #12]
- 80024fa: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80024fe: 6103 str r3, [r0, #16]
- 8002500: 7b4a ldrb r2, [r1, #13]
- 8002502: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002506: 6103 str r3, [r0, #16]
- 8002508: 7b8a ldrb r2, [r1, #14]
- 800250a: 04d2 lsls r2, r2, #19
- 800250c: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002510: 4313 orrs r3, r2
- 8002512: 6103 str r3, [r0, #16]
- 8002514: 7bca ldrb r2, [r1, #15]
- 8002516: 7b8d ldrb r5, [r1, #14]
- 8002518: 0114 lsls r4, r2, #4
- 800251a: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800251e: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002522: d005 beq.n 8002530 <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x88>
- 8002524: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002528: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 800252c: 6103 str r3, [r0, #16]
- 800252e: 7bca ldrb r2, [r1, #15]
- 8002530: 0612 lsls r2, r2, #24
- 8002532: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002536: 4313 orrs r3, r2
- 8002538: 6103 str r3, [r0, #16]
- 800253a: 7ccb ldrb r3, [r1, #19]
- 800253c: 095b lsrs r3, r3, #5
- 800253e: 6143 str r3, [r0, #20]
- 8002540: 7d0a ldrb r2, [r1, #20]
- 8002542: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002546: 6143 str r3, [r0, #20]
- 8002548: 7d4a ldrb r2, [r1, #21]
- 800254a: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 800254e: 6143 str r3, [r0, #20]
- 8002550: 7d8a ldrb r2, [r1, #22]
- 8002552: 04d2 lsls r2, r2, #19
- 8002554: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002558: 4313 orrs r3, r2
- 800255a: 6143 str r3, [r0, #20]
- 800255c: 7dca ldrb r2, [r1, #23]
- 800255e: 7d8d ldrb r5, [r1, #22]
- 8002560: 0114 lsls r4, r2, #4
- 8002562: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002566: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 800256a: d005 beq.n 8002578 <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0xd0>
- 800256c: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002570: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 8002574: 6143 str r3, [r0, #20]
- 8002576: 7dca ldrb r2, [r1, #23]
- 8002578: 0612 lsls r2, r2, #24
- 800257a: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 800257e: 4313 orrs r3, r2
- 8002580: 6143 str r3, [r0, #20]
- 8002582: 7ecb ldrb r3, [r1, #27]
- 8002584: 095b lsrs r3, r3, #5
- 8002586: 61c3 str r3, [r0, #28]
- 8002588: 7f0a ldrb r2, [r1, #28]
- 800258a: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 800258e: 61c3 str r3, [r0, #28]
- 8002590: 7f4a ldrb r2, [r1, #29]
- 8002592: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002596: 61c3 str r3, [r0, #28]
- 8002598: 7f8a ldrb r2, [r1, #30]
- 800259a: 04d2 lsls r2, r2, #19
- 800259c: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80025a0: 4313 orrs r3, r2
- 80025a2: 61c3 str r3, [r0, #28]
- 80025a4: 7fca ldrb r2, [r1, #31]
- 80025a6: 7f8d ldrb r5, [r1, #30]
- 80025a8: 0114 lsls r4, r2, #4
- 80025aa: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80025ae: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80025b2: d005 beq.n 80025c0 <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x118>
- 80025b4: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80025b8: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 80025bc: 61c3 str r3, [r0, #28]
- 80025be: 7fca ldrb r2, [r1, #31]
- 80025c0: 0612 lsls r2, r2, #24
- 80025c2: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80025c6: 4313 orrs r3, r2
- 80025c8: 61c3 str r3, [r0, #28]
- 80025ca: f891 3023 ldrb.w r3, [r1, #35] ; 0x23
- 80025ce: 095b lsrs r3, r3, #5
- 80025d0: 6203 str r3, [r0, #32]
- 80025d2: f891 2024 ldrb.w r2, [r1, #36] ; 0x24
- 80025d6: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80025da: 6203 str r3, [r0, #32]
- 80025dc: f891 2025 ldrb.w r2, [r1, #37] ; 0x25
- 80025e0: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 80025e4: 6203 str r3, [r0, #32]
- 80025e6: f891 2026 ldrb.w r2, [r1, #38] ; 0x26
- 80025ea: 04d2 lsls r2, r2, #19
- 80025ec: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80025f0: 4313 orrs r3, r2
- 80025f2: 6203 str r3, [r0, #32]
- 80025f4: f891 2027 ldrb.w r2, [r1, #39] ; 0x27
- 80025f8: f891 5026 ldrb.w r5, [r1, #38] ; 0x26
- 80025fc: 0114 lsls r4, r2, #4
- 80025fe: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002602: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002606: d006 beq.n 8002616 <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x16e>
- 8002608: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 800260c: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 8002610: 6203 str r3, [r0, #32]
- 8002612: f891 2027 ldrb.w r2, [r1, #39] ; 0x27
- 8002616: 0612 lsls r2, r2, #24
- 8002618: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 800261c: 4313 orrs r3, r2
- 800261e: 6203 str r3, [r0, #32]
- 8002620: f891 302b ldrb.w r3, [r1, #43] ; 0x2b
- 8002624: 095b lsrs r3, r3, #5
- 8002626: 6243 str r3, [r0, #36] ; 0x24
- 8002628: f891 202c ldrb.w r2, [r1, #44] ; 0x2c
- 800262c: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002630: 6243 str r3, [r0, #36] ; 0x24
- 8002632: f891 202d ldrb.w r2, [r1, #45] ; 0x2d
- 8002636: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 800263a: 6243 str r3, [r0, #36] ; 0x24
- 800263c: f891 202e ldrb.w r2, [r1, #46] ; 0x2e
- 8002640: 04d2 lsls r2, r2, #19
- 8002642: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002646: 4313 orrs r3, r2
- 8002648: 6243 str r3, [r0, #36] ; 0x24
- 800264a: f891 202f ldrb.w r2, [r1, #47] ; 0x2f
- 800264e: f891 502e ldrb.w r5, [r1, #46] ; 0x2e
- 8002652: 0114 lsls r4, r2, #4
- 8002654: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002658: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 800265c: d006 beq.n 800266c <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x1c4>
- 800265e: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002662: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 8002666: 6243 str r3, [r0, #36] ; 0x24
- 8002668: f891 202f ldrb.w r2, [r1, #47] ; 0x2f
- 800266c: 0612 lsls r2, r2, #24
- 800266e: f100 04b4 add.w r4, r0, #180 ; 0xb4
- 8002672: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002676: 4313 orrs r3, r2
- 8002678: f840 3f24 str.w r3, [r0, #36]!
- 800267c: f891 2033 ldrb.w r2, [r1, #51] ; 0x33
- 8002680: 0952 lsrs r2, r2, #5
- 8002682: f840 2f04 str.w r2, [r0, #4]!
- 8002686: f891 3034 ldrb.w r3, [r1, #52] ; 0x34
- 800268a: ea42 02c3 orr.w r2, r2, r3, lsl #3
- 800268e: 6002 str r2, [r0, #0]
- 8002690: f891 3035 ldrb.w r3, [r1, #53] ; 0x35
- 8002694: ea42 23c3 orr.w r3, r2, r3, lsl #11
- 8002698: 6003 str r3, [r0, #0]
- 800269a: f891 2036 ldrb.w r2, [r1, #54] ; 0x36
- 800269e: 04d2 lsls r2, r2, #19
- 80026a0: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80026a4: 431a orrs r2, r3
- 80026a6: 6002 str r2, [r0, #0]
- 80026a8: f891 3037 ldrb.w r3, [r1, #55] ; 0x37
- 80026ac: f891 6036 ldrb.w r6, [r1, #54] ; 0x36
- 80026b0: 061d lsls r5, r3, #24
- 80026b2: 011b lsls r3, r3, #4
- 80026b4: f005 4500 and.w r5, r5, #2147483648 ; 0x80000000
- 80026b8: f403 63fe and.w r3, r3, #2032 ; 0x7f0
- 80026bc: 4315 orrs r5, r2
- 80026be: ea53 1316 orrs.w r3, r3, r6, lsr #4
- 80026c2: f5a3 7360 sub.w r3, r3, #896 ; 0x380
- 80026c6: d013 beq.n 80026f0 <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x248>
- 80026c8: ea42 53c3 orr.w r3, r2, r3, lsl #23
- 80026cc: 42a0 cmp r0, r4
- 80026ce: f101 0108 add.w r1, r1, #8
- 80026d2: 6003 str r3, [r0, #0]
- 80026d4: f891 202f ldrb.w r2, [r1, #47] ; 0x2f
- 80026d8: ea4f 6202 mov.w r2, r2, lsl #24
- 80026dc: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80026e0: ea43 0302 orr.w r3, r3, r2
- 80026e4: 6003 str r3, [r0, #0]
- 80026e6: d1c9 bne.n 800267c <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x1d4>
- 80026e8: f44f 70a8 mov.w r0, #336 ; 0x150
- 80026ec: bc70 pop {r4, r5, r6}
- 80026ee: 4770 bx lr
- 80026f0: 42a0 cmp r0, r4
- 80026f2: 6005 str r5, [r0, #0]
- 80026f4: f101 0108 add.w r1, r1, #8
- 80026f8: d1c0 bne.n 800267c <_ZN13geometry_msgs19TwistWithCovariance11deserializeEPh+0x1d4>
- 80026fa: f44f 70a8 mov.w r0, #336 ; 0x150
- 80026fe: bc70 pop {r4, r5, r6}
- 8002700: 4770 bx lr
- 8002702: bf00 nop
-
-08002704 <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh>:
- 8002704: 78cb ldrb r3, [r1, #3]
- 8002706: 095b lsrs r3, r3, #5
- 8002708: b470 push {r4, r5, r6}
- 800270a: 60c3 str r3, [r0, #12]
- 800270c: 790a ldrb r2, [r1, #4]
- 800270e: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002712: 60c3 str r3, [r0, #12]
- 8002714: 794a ldrb r2, [r1, #5]
- 8002716: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 800271a: 60c3 str r3, [r0, #12]
- 800271c: 798a ldrb r2, [r1, #6]
- 800271e: 04d2 lsls r2, r2, #19
- 8002720: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002724: 4313 orrs r3, r2
- 8002726: 60c3 str r3, [r0, #12]
- 8002728: 79ca ldrb r2, [r1, #7]
- 800272a: 798d ldrb r5, [r1, #6]
- 800272c: 0114 lsls r4, r2, #4
- 800272e: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002732: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002736: d005 beq.n 8002744 <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x40>
- 8002738: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 800273c: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 8002740: 60c3 str r3, [r0, #12]
- 8002742: 79ca ldrb r2, [r1, #7]
- 8002744: 0612 lsls r2, r2, #24
- 8002746: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 800274a: 4313 orrs r3, r2
- 800274c: 60c3 str r3, [r0, #12]
- 800274e: 7acb ldrb r3, [r1, #11]
- 8002750: 095b lsrs r3, r3, #5
- 8002752: 6103 str r3, [r0, #16]
- 8002754: 7b0a ldrb r2, [r1, #12]
- 8002756: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 800275a: 6103 str r3, [r0, #16]
- 800275c: 7b4a ldrb r2, [r1, #13]
- 800275e: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002762: 6103 str r3, [r0, #16]
- 8002764: 7b8a ldrb r2, [r1, #14]
- 8002766: 04d2 lsls r2, r2, #19
- 8002768: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 800276c: 4313 orrs r3, r2
- 800276e: 6103 str r3, [r0, #16]
- 8002770: 7bca ldrb r2, [r1, #15]
- 8002772: 7b8d ldrb r5, [r1, #14]
- 8002774: 0114 lsls r4, r2, #4
- 8002776: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800277a: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 800277e: d005 beq.n 800278c <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x88>
- 8002780: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002784: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 8002788: 6103 str r3, [r0, #16]
- 800278a: 7bca ldrb r2, [r1, #15]
- 800278c: 0612 lsls r2, r2, #24
- 800278e: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002792: 4313 orrs r3, r2
- 8002794: 6103 str r3, [r0, #16]
- 8002796: 7ccb ldrb r3, [r1, #19]
- 8002798: 095b lsrs r3, r3, #5
- 800279a: 6143 str r3, [r0, #20]
- 800279c: 7d0a ldrb r2, [r1, #20]
- 800279e: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80027a2: 6143 str r3, [r0, #20]
- 80027a4: 7d4a ldrb r2, [r1, #21]
- 80027a6: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 80027aa: 6143 str r3, [r0, #20]
- 80027ac: 7d8a ldrb r2, [r1, #22]
- 80027ae: 04d2 lsls r2, r2, #19
- 80027b0: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80027b4: 4313 orrs r3, r2
- 80027b6: 6143 str r3, [r0, #20]
- 80027b8: 7dca ldrb r2, [r1, #23]
- 80027ba: 7d8d ldrb r5, [r1, #22]
- 80027bc: 0114 lsls r4, r2, #4
- 80027be: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80027c2: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80027c6: d005 beq.n 80027d4 <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0xd0>
- 80027c8: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80027cc: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 80027d0: 6143 str r3, [r0, #20]
- 80027d2: 7dca ldrb r2, [r1, #23]
- 80027d4: 0612 lsls r2, r2, #24
- 80027d6: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80027da: 4313 orrs r3, r2
- 80027dc: 6143 str r3, [r0, #20]
- 80027de: 7ecb ldrb r3, [r1, #27]
- 80027e0: 095b lsrs r3, r3, #5
- 80027e2: 61c3 str r3, [r0, #28]
- 80027e4: 7f0a ldrb r2, [r1, #28]
- 80027e6: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80027ea: 61c3 str r3, [r0, #28]
- 80027ec: 7f4a ldrb r2, [r1, #29]
- 80027ee: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 80027f2: 61c3 str r3, [r0, #28]
- 80027f4: 7f8a ldrb r2, [r1, #30]
- 80027f6: 04d2 lsls r2, r2, #19
- 80027f8: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80027fc: 4313 orrs r3, r2
- 80027fe: 61c3 str r3, [r0, #28]
- 8002800: 7fca ldrb r2, [r1, #31]
- 8002802: 7f8d ldrb r5, [r1, #30]
- 8002804: 0114 lsls r4, r2, #4
- 8002806: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800280a: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 800280e: d005 beq.n 800281c <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x118>
- 8002810: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002814: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 8002818: 61c3 str r3, [r0, #28]
- 800281a: 7fca ldrb r2, [r1, #31]
- 800281c: 0612 lsls r2, r2, #24
- 800281e: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002822: 4313 orrs r3, r2
- 8002824: 61c3 str r3, [r0, #28]
- 8002826: f891 3023 ldrb.w r3, [r1, #35] ; 0x23
- 800282a: 095b lsrs r3, r3, #5
- 800282c: 6203 str r3, [r0, #32]
- 800282e: f891 2024 ldrb.w r2, [r1, #36] ; 0x24
- 8002832: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002836: 6203 str r3, [r0, #32]
- 8002838: f891 2025 ldrb.w r2, [r1, #37] ; 0x25
- 800283c: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002840: 6203 str r3, [r0, #32]
- 8002842: f891 2026 ldrb.w r2, [r1, #38] ; 0x26
- 8002846: 04d2 lsls r2, r2, #19
- 8002848: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 800284c: 4313 orrs r3, r2
- 800284e: 6203 str r3, [r0, #32]
- 8002850: f891 2027 ldrb.w r2, [r1, #39] ; 0x27
- 8002854: f891 5026 ldrb.w r5, [r1, #38] ; 0x26
- 8002858: 0114 lsls r4, r2, #4
- 800285a: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800285e: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002862: d006 beq.n 8002872 <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x16e>
- 8002864: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002868: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 800286c: 6203 str r3, [r0, #32]
- 800286e: f891 2027 ldrb.w r2, [r1, #39] ; 0x27
- 8002872: 0612 lsls r2, r2, #24
- 8002874: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002878: 4313 orrs r3, r2
- 800287a: 6203 str r3, [r0, #32]
- 800287c: f891 302b ldrb.w r3, [r1, #43] ; 0x2b
- 8002880: 095b lsrs r3, r3, #5
- 8002882: 6243 str r3, [r0, #36] ; 0x24
- 8002884: f891 202c ldrb.w r2, [r1, #44] ; 0x2c
- 8002888: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 800288c: 6243 str r3, [r0, #36] ; 0x24
- 800288e: f891 202d ldrb.w r2, [r1, #45] ; 0x2d
- 8002892: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002896: 6243 str r3, [r0, #36] ; 0x24
- 8002898: f891 202e ldrb.w r2, [r1, #46] ; 0x2e
- 800289c: 04d2 lsls r2, r2, #19
- 800289e: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80028a2: 4313 orrs r3, r2
- 80028a4: 6243 str r3, [r0, #36] ; 0x24
- 80028a6: f891 202f ldrb.w r2, [r1, #47] ; 0x2f
- 80028aa: f891 502e ldrb.w r5, [r1, #46] ; 0x2e
- 80028ae: 0114 lsls r4, r2, #4
- 80028b0: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80028b4: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80028b8: d006 beq.n 80028c8 <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x1c4>
- 80028ba: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80028be: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 80028c2: 6243 str r3, [r0, #36] ; 0x24
- 80028c4: f891 202f ldrb.w r2, [r1, #47] ; 0x2f
- 80028c8: 0612 lsls r2, r2, #24
- 80028ca: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80028ce: 4313 orrs r3, r2
- 80028d0: 6243 str r3, [r0, #36] ; 0x24
- 80028d2: f891 3033 ldrb.w r3, [r1, #51] ; 0x33
- 80028d6: 095b lsrs r3, r3, #5
- 80028d8: 6283 str r3, [r0, #40] ; 0x28
- 80028da: f891 2034 ldrb.w r2, [r1, #52] ; 0x34
- 80028de: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80028e2: 6283 str r3, [r0, #40] ; 0x28
- 80028e4: f891 2035 ldrb.w r2, [r1, #53] ; 0x35
- 80028e8: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 80028ec: 6283 str r3, [r0, #40] ; 0x28
- 80028ee: f891 2036 ldrb.w r2, [r1, #54] ; 0x36
- 80028f2: 04d2 lsls r2, r2, #19
- 80028f4: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80028f8: 4313 orrs r3, r2
- 80028fa: 6283 str r3, [r0, #40] ; 0x28
- 80028fc: f891 2037 ldrb.w r2, [r1, #55] ; 0x37
- 8002900: f891 5036 ldrb.w r5, [r1, #54] ; 0x36
- 8002904: 0114 lsls r4, r2, #4
- 8002906: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 800290a: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 800290e: d006 beq.n 800291e <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x21a>
- 8002910: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002914: ea43 53c4 orr.w r3, r3, r4, lsl #23
- 8002918: 6283 str r3, [r0, #40] ; 0x28
- 800291a: f891 2037 ldrb.w r2, [r1, #55] ; 0x37
- 800291e: 0612 lsls r2, r2, #24
- 8002920: f100 04b8 add.w r4, r0, #184 ; 0xb8
- 8002924: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002928: 4313 orrs r3, r2
- 800292a: f840 3f28 str.w r3, [r0, #40]!
- 800292e: f891 203b ldrb.w r2, [r1, #59] ; 0x3b
- 8002932: 0952 lsrs r2, r2, #5
- 8002934: f840 2f04 str.w r2, [r0, #4]!
- 8002938: f891 303c ldrb.w r3, [r1, #60] ; 0x3c
- 800293c: ea42 02c3 orr.w r2, r2, r3, lsl #3
- 8002940: 6002 str r2, [r0, #0]
- 8002942: f891 303d ldrb.w r3, [r1, #61] ; 0x3d
- 8002946: ea42 23c3 orr.w r3, r2, r3, lsl #11
- 800294a: 6003 str r3, [r0, #0]
- 800294c: f891 203e ldrb.w r2, [r1, #62] ; 0x3e
- 8002950: 04d2 lsls r2, r2, #19
- 8002952: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002956: 431a orrs r2, r3
- 8002958: 6002 str r2, [r0, #0]
- 800295a: f891 303f ldrb.w r3, [r1, #63] ; 0x3f
- 800295e: f891 603e ldrb.w r6, [r1, #62] ; 0x3e
- 8002962: 061d lsls r5, r3, #24
- 8002964: 011b lsls r3, r3, #4
- 8002966: f005 4500 and.w r5, r5, #2147483648 ; 0x80000000
- 800296a: f403 63fe and.w r3, r3, #2032 ; 0x7f0
- 800296e: 4315 orrs r5, r2
- 8002970: ea53 1316 orrs.w r3, r3, r6, lsr #4
- 8002974: f5a3 7360 sub.w r3, r3, #896 ; 0x380
- 8002978: d013 beq.n 80029a2 <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x29e>
- 800297a: ea42 53c3 orr.w r3, r2, r3, lsl #23
- 800297e: 4284 cmp r4, r0
- 8002980: f101 0108 add.w r1, r1, #8
- 8002984: 6003 str r3, [r0, #0]
- 8002986: f891 2037 ldrb.w r2, [r1, #55] ; 0x37
- 800298a: ea4f 6202 mov.w r2, r2, lsl #24
- 800298e: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002992: ea43 0302 orr.w r3, r3, r2
- 8002996: 6003 str r3, [r0, #0]
- 8002998: d1c9 bne.n 800292e <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x22a>
- 800299a: f44f 70ac mov.w r0, #344 ; 0x158
- 800299e: bc70 pop {r4, r5, r6}
- 80029a0: 4770 bx lr
- 80029a2: 4284 cmp r4, r0
- 80029a4: 6005 str r5, [r0, #0]
- 80029a6: f101 0108 add.w r1, r1, #8
- 80029aa: d1c0 bne.n 800292e <_ZN13geometry_msgs18PoseWithCovariance11deserializeEPh+0x22a>
- 80029ac: f44f 70ac mov.w r0, #344 ; 0x158
- 80029b0: bc70 pop {r4, r5, r6}
- 80029b2: 4770 bx lr
-
-080029b4 <_ZN13geometry_msgs7Vector311deserializeEPh>:
- 80029b4: b430 push {r4, r5}
- 80029b6: 78ca ldrb r2, [r1, #3]
- 80029b8: 4603 mov r3, r0
- 80029ba: 0952 lsrs r2, r2, #5
- 80029bc: 6042 str r2, [r0, #4]
- 80029be: 7908 ldrb r0, [r1, #4]
- 80029c0: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 80029c4: 605a str r2, [r3, #4]
- 80029c6: 7948 ldrb r0, [r1, #5]
- 80029c8: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 80029cc: 605a str r2, [r3, #4]
- 80029ce: 7988 ldrb r0, [r1, #6]
- 80029d0: 04c0 lsls r0, r0, #19
- 80029d2: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 80029d6: 4302 orrs r2, r0
- 80029d8: 605a str r2, [r3, #4]
- 80029da: 79c8 ldrb r0, [r1, #7]
- 80029dc: 798d ldrb r5, [r1, #6]
- 80029de: 0104 lsls r4, r0, #4
- 80029e0: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 80029e4: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 80029e8: d005 beq.n 80029f6 <_ZN13geometry_msgs7Vector311deserializeEPh+0x42>
- 80029ea: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 80029ee: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 80029f2: 605a str r2, [r3, #4]
- 80029f4: 79c8 ldrb r0, [r1, #7]
- 80029f6: 0600 lsls r0, r0, #24
- 80029f8: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 80029fc: 4302 orrs r2, r0
- 80029fe: 605a str r2, [r3, #4]
- 8002a00: 7aca ldrb r2, [r1, #11]
- 8002a02: 0952 lsrs r2, r2, #5
- 8002a04: 609a str r2, [r3, #8]
- 8002a06: 7b08 ldrb r0, [r1, #12]
- 8002a08: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002a0c: 609a str r2, [r3, #8]
- 8002a0e: 7b48 ldrb r0, [r1, #13]
- 8002a10: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002a14: 609a str r2, [r3, #8]
- 8002a16: 7b88 ldrb r0, [r1, #14]
- 8002a18: 04c0 lsls r0, r0, #19
- 8002a1a: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002a1e: 4302 orrs r2, r0
- 8002a20: 609a str r2, [r3, #8]
- 8002a22: 7bc8 ldrb r0, [r1, #15]
- 8002a24: 7b8d ldrb r5, [r1, #14]
- 8002a26: 0104 lsls r4, r0, #4
- 8002a28: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002a2c: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002a30: d005 beq.n 8002a3e <_ZN13geometry_msgs7Vector311deserializeEPh+0x8a>
- 8002a32: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002a36: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002a3a: 609a str r2, [r3, #8]
- 8002a3c: 7bc8 ldrb r0, [r1, #15]
- 8002a3e: 0600 lsls r0, r0, #24
- 8002a40: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002a44: 4302 orrs r2, r0
- 8002a46: 609a str r2, [r3, #8]
- 8002a48: 7cca ldrb r2, [r1, #19]
- 8002a4a: 0952 lsrs r2, r2, #5
- 8002a4c: 60da str r2, [r3, #12]
- 8002a4e: 7d08 ldrb r0, [r1, #20]
- 8002a50: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002a54: 60da str r2, [r3, #12]
- 8002a56: 7d48 ldrb r0, [r1, #21]
- 8002a58: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002a5c: 60da str r2, [r3, #12]
- 8002a5e: 7d88 ldrb r0, [r1, #22]
- 8002a60: 04c0 lsls r0, r0, #19
- 8002a62: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002a66: 4302 orrs r2, r0
- 8002a68: 60da str r2, [r3, #12]
- 8002a6a: 7dc8 ldrb r0, [r1, #23]
- 8002a6c: 7d8d ldrb r5, [r1, #22]
- 8002a6e: 0104 lsls r4, r0, #4
- 8002a70: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002a74: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002a78: d005 beq.n 8002a86 <_ZN13geometry_msgs7Vector311deserializeEPh+0xd2>
- 8002a7a: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002a7e: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002a82: 60da str r2, [r3, #12]
- 8002a84: 7dc8 ldrb r0, [r1, #23]
- 8002a86: 0601 lsls r1, r0, #24
- 8002a88: 2018 movs r0, #24
- 8002a8a: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
- 8002a8e: 430a orrs r2, r1
- 8002a90: bc30 pop {r4, r5}
- 8002a92: 60da str r2, [r3, #12]
- 8002a94: 4770 bx lr
- 8002a96: bf00 nop
-
-08002a98 <_ZN13geometry_msgs5Point11deserializeEPh>:
- 8002a98: b430 push {r4, r5}
- 8002a9a: 78ca ldrb r2, [r1, #3]
- 8002a9c: 4603 mov r3, r0
- 8002a9e: 0952 lsrs r2, r2, #5
- 8002aa0: 6042 str r2, [r0, #4]
- 8002aa2: 7908 ldrb r0, [r1, #4]
- 8002aa4: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002aa8: 605a str r2, [r3, #4]
- 8002aaa: 7948 ldrb r0, [r1, #5]
- 8002aac: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002ab0: 605a str r2, [r3, #4]
- 8002ab2: 7988 ldrb r0, [r1, #6]
- 8002ab4: 04c0 lsls r0, r0, #19
- 8002ab6: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002aba: 4302 orrs r2, r0
- 8002abc: 605a str r2, [r3, #4]
- 8002abe: 79c8 ldrb r0, [r1, #7]
- 8002ac0: 798d ldrb r5, [r1, #6]
- 8002ac2: 0104 lsls r4, r0, #4
- 8002ac4: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002ac8: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002acc: d005 beq.n 8002ada <_ZN13geometry_msgs5Point11deserializeEPh+0x42>
- 8002ace: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002ad2: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002ad6: 605a str r2, [r3, #4]
- 8002ad8: 79c8 ldrb r0, [r1, #7]
- 8002ada: 0600 lsls r0, r0, #24
- 8002adc: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002ae0: 4302 orrs r2, r0
- 8002ae2: 605a str r2, [r3, #4]
- 8002ae4: 7aca ldrb r2, [r1, #11]
- 8002ae6: 0952 lsrs r2, r2, #5
- 8002ae8: 609a str r2, [r3, #8]
- 8002aea: 7b08 ldrb r0, [r1, #12]
- 8002aec: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002af0: 609a str r2, [r3, #8]
- 8002af2: 7b48 ldrb r0, [r1, #13]
- 8002af4: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002af8: 609a str r2, [r3, #8]
- 8002afa: 7b88 ldrb r0, [r1, #14]
- 8002afc: 04c0 lsls r0, r0, #19
- 8002afe: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002b02: 4302 orrs r2, r0
- 8002b04: 609a str r2, [r3, #8]
- 8002b06: 7bc8 ldrb r0, [r1, #15]
- 8002b08: 7b8d ldrb r5, [r1, #14]
- 8002b0a: 0104 lsls r4, r0, #4
- 8002b0c: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002b10: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002b14: d005 beq.n 8002b22 <_ZN13geometry_msgs5Point11deserializeEPh+0x8a>
- 8002b16: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002b1a: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002b1e: 609a str r2, [r3, #8]
- 8002b20: 7bc8 ldrb r0, [r1, #15]
- 8002b22: 0600 lsls r0, r0, #24
- 8002b24: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002b28: 4302 orrs r2, r0
- 8002b2a: 609a str r2, [r3, #8]
- 8002b2c: 7cca ldrb r2, [r1, #19]
- 8002b2e: 0952 lsrs r2, r2, #5
- 8002b30: 60da str r2, [r3, #12]
- 8002b32: 7d08 ldrb r0, [r1, #20]
- 8002b34: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002b38: 60da str r2, [r3, #12]
- 8002b3a: 7d48 ldrb r0, [r1, #21]
- 8002b3c: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002b40: 60da str r2, [r3, #12]
- 8002b42: 7d88 ldrb r0, [r1, #22]
- 8002b44: 04c0 lsls r0, r0, #19
- 8002b46: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002b4a: 4302 orrs r2, r0
- 8002b4c: 60da str r2, [r3, #12]
- 8002b4e: 7dc8 ldrb r0, [r1, #23]
- 8002b50: 7d8d ldrb r5, [r1, #22]
- 8002b52: 0104 lsls r4, r0, #4
- 8002b54: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002b58: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002b5c: d005 beq.n 8002b6a <_ZN13geometry_msgs5Point11deserializeEPh+0xd2>
- 8002b5e: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002b62: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002b66: 60da str r2, [r3, #12]
- 8002b68: 7dc8 ldrb r0, [r1, #23]
- 8002b6a: 0601 lsls r1, r0, #24
- 8002b6c: 2018 movs r0, #24
- 8002b6e: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
- 8002b72: 430a orrs r2, r1
- 8002b74: bc30 pop {r4, r5}
- 8002b76: 60da str r2, [r3, #12]
- 8002b78: 4770 bx lr
- 8002b7a: bf00 nop
-
-08002b7c <_ZN13geometry_msgs10Quaternion11deserializeEPh>:
- 8002b7c: b430 push {r4, r5}
- 8002b7e: 78ca ldrb r2, [r1, #3]
- 8002b80: 4603 mov r3, r0
- 8002b82: 0952 lsrs r2, r2, #5
- 8002b84: 6042 str r2, [r0, #4]
- 8002b86: 7908 ldrb r0, [r1, #4]
- 8002b88: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002b8c: 605a str r2, [r3, #4]
- 8002b8e: 7948 ldrb r0, [r1, #5]
- 8002b90: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002b94: 605a str r2, [r3, #4]
- 8002b96: 7988 ldrb r0, [r1, #6]
- 8002b98: 04c0 lsls r0, r0, #19
- 8002b9a: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002b9e: 4302 orrs r2, r0
- 8002ba0: 605a str r2, [r3, #4]
- 8002ba2: 79c8 ldrb r0, [r1, #7]
- 8002ba4: 798d ldrb r5, [r1, #6]
- 8002ba6: 0104 lsls r4, r0, #4
- 8002ba8: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002bac: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002bb0: d005 beq.n 8002bbe <_ZN13geometry_msgs10Quaternion11deserializeEPh+0x42>
- 8002bb2: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002bb6: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002bba: 605a str r2, [r3, #4]
- 8002bbc: 79c8 ldrb r0, [r1, #7]
- 8002bbe: 0600 lsls r0, r0, #24
- 8002bc0: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002bc4: 4302 orrs r2, r0
- 8002bc6: 605a str r2, [r3, #4]
- 8002bc8: 7aca ldrb r2, [r1, #11]
- 8002bca: 0952 lsrs r2, r2, #5
- 8002bcc: 609a str r2, [r3, #8]
- 8002bce: 7b08 ldrb r0, [r1, #12]
- 8002bd0: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002bd4: 609a str r2, [r3, #8]
- 8002bd6: 7b48 ldrb r0, [r1, #13]
- 8002bd8: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002bdc: 609a str r2, [r3, #8]
- 8002bde: 7b88 ldrb r0, [r1, #14]
- 8002be0: 04c0 lsls r0, r0, #19
- 8002be2: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002be6: 4302 orrs r2, r0
- 8002be8: 609a str r2, [r3, #8]
- 8002bea: 7bc8 ldrb r0, [r1, #15]
- 8002bec: 7b8d ldrb r5, [r1, #14]
- 8002bee: 0104 lsls r4, r0, #4
- 8002bf0: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002bf4: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002bf8: d005 beq.n 8002c06 <_ZN13geometry_msgs10Quaternion11deserializeEPh+0x8a>
- 8002bfa: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002bfe: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002c02: 609a str r2, [r3, #8]
- 8002c04: 7bc8 ldrb r0, [r1, #15]
- 8002c06: 0600 lsls r0, r0, #24
- 8002c08: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002c0c: 4302 orrs r2, r0
- 8002c0e: 609a str r2, [r3, #8]
- 8002c10: 7cca ldrb r2, [r1, #19]
- 8002c12: 0952 lsrs r2, r2, #5
- 8002c14: 60da str r2, [r3, #12]
- 8002c16: 7d08 ldrb r0, [r1, #20]
- 8002c18: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002c1c: 60da str r2, [r3, #12]
- 8002c1e: 7d48 ldrb r0, [r1, #21]
- 8002c20: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002c24: 60da str r2, [r3, #12]
- 8002c26: 7d88 ldrb r0, [r1, #22]
- 8002c28: 04c0 lsls r0, r0, #19
- 8002c2a: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002c2e: 4302 orrs r2, r0
- 8002c30: 60da str r2, [r3, #12]
- 8002c32: 7dc8 ldrb r0, [r1, #23]
- 8002c34: 7d8d ldrb r5, [r1, #22]
- 8002c36: 0104 lsls r4, r0, #4
- 8002c38: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002c3c: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002c40: d005 beq.n 8002c4e <_ZN13geometry_msgs10Quaternion11deserializeEPh+0xd2>
- 8002c42: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002c46: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002c4a: 60da str r2, [r3, #12]
- 8002c4c: 7dc8 ldrb r0, [r1, #23]
- 8002c4e: 0600 lsls r0, r0, #24
- 8002c50: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8002c54: 4302 orrs r2, r0
- 8002c56: 60da str r2, [r3, #12]
- 8002c58: 7eca ldrb r2, [r1, #27]
- 8002c5a: 0952 lsrs r2, r2, #5
- 8002c5c: 611a str r2, [r3, #16]
- 8002c5e: 7f08 ldrb r0, [r1, #28]
- 8002c60: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8002c64: 611a str r2, [r3, #16]
- 8002c66: 7f48 ldrb r0, [r1, #29]
- 8002c68: ea42 22c0 orr.w r2, r2, r0, lsl #11
- 8002c6c: 611a str r2, [r3, #16]
- 8002c6e: 7f88 ldrb r0, [r1, #30]
- 8002c70: 04c0 lsls r0, r0, #19
- 8002c72: f400 00f0 and.w r0, r0, #7864320 ; 0x780000
- 8002c76: 4302 orrs r2, r0
- 8002c78: 611a str r2, [r3, #16]
- 8002c7a: 7fc8 ldrb r0, [r1, #31]
- 8002c7c: 7f8d ldrb r5, [r1, #30]
- 8002c7e: 0104 lsls r4, r0, #4
- 8002c80: f404 64fe and.w r4, r4, #2032 ; 0x7f0
- 8002c84: ea54 1415 orrs.w r4, r4, r5, lsr #4
- 8002c88: d005 beq.n 8002c96 <_ZN13geometry_msgs10Quaternion11deserializeEPh+0x11a>
- 8002c8a: f5a4 7460 sub.w r4, r4, #896 ; 0x380
- 8002c8e: ea42 52c4 orr.w r2, r2, r4, lsl #23
- 8002c92: 611a str r2, [r3, #16]
- 8002c94: 7fc8 ldrb r0, [r1, #31]
- 8002c96: 0601 lsls r1, r0, #24
- 8002c98: 2020 movs r0, #32
- 8002c9a: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
- 8002c9e: 430a orrs r2, r1
- 8002ca0: bc30 pop {r4, r5}
- 8002ca2: 611a str r2, [r3, #16]
- 8002ca4: 4770 bx lr
- 8002ca6: bf00 nop
-
-08002ca8 <_ZN8nav_msgs8Odometry11deserializeEPh>:
- 8002ca8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
- 8002cac: 780b ldrb r3, [r1, #0]
- 8002cae: 4605 mov r5, r0
- 8002cb0: 460e mov r6, r1
- 8002cb2: f101 040f add.w r4, r1, #15
- 8002cb6: 6083 str r3, [r0, #8]
- 8002cb8: 784a ldrb r2, [r1, #1]
- 8002cba: ea43 2302 orr.w r3, r3, r2, lsl #8
- 8002cbe: 6083 str r3, [r0, #8]
- 8002cc0: 788a ldrb r2, [r1, #2]
- 8002cc2: ea43 4302 orr.w r3, r3, r2, lsl #16
- 8002cc6: 6083 str r3, [r0, #8]
- 8002cc8: 78ca ldrb r2, [r1, #3]
- 8002cca: ea43 6302 orr.w r3, r3, r2, lsl #24
- 8002cce: 6083 str r3, [r0, #8]
- 8002cd0: 790b ldrb r3, [r1, #4]
- 8002cd2: 60c3 str r3, [r0, #12]
- 8002cd4: 794a ldrb r2, [r1, #5]
- 8002cd6: ea43 2302 orr.w r3, r3, r2, lsl #8
- 8002cda: 60c3 str r3, [r0, #12]
- 8002cdc: 798a ldrb r2, [r1, #6]
- 8002cde: ea43 4302 orr.w r3, r3, r2, lsl #16
- 8002ce2: 60c3 str r3, [r0, #12]
- 8002ce4: 79ca ldrb r2, [r1, #7]
- 8002ce6: ea43 6302 orr.w r3, r3, r2, lsl #24
- 8002cea: 60c3 str r3, [r0, #12]
- 8002cec: 7a0b ldrb r3, [r1, #8]
- 8002cee: 6103 str r3, [r0, #16]
- 8002cf0: 7a4a ldrb r2, [r1, #9]
- 8002cf2: ea43 2302 orr.w r3, r3, r2, lsl #8
- 8002cf6: 6103 str r3, [r0, #16]
- 8002cf8: 7a8a ldrb r2, [r1, #10]
- 8002cfa: ea43 4302 orr.w r3, r3, r2, lsl #16
- 8002cfe: 6103 str r3, [r0, #16]
- 8002d00: 7aca ldrb r2, [r1, #11]
- 8002d02: ea43 6302 orr.w r3, r3, r2, lsl #24
- 8002d06: 6103 str r3, [r0, #16]
- 8002d08: 7b4f ldrb r7, [r1, #13]
- 8002d0a: 7b8a ldrb r2, [r1, #14]
- 8002d0c: 023f lsls r7, r7, #8
- 8002d0e: 7bcb ldrb r3, [r1, #15]
- 8002d10: 7b08 ldrb r0, [r1, #12]
- 8002d12: ea47 4702 orr.w r7, r7, r2, lsl #16
- 8002d16: ea47 6703 orr.w r7, r7, r3, lsl #24
- 8002d1a: 4307 orrs r7, r0
- 8002d1c: f107 0910 add.w r9, r7, #16
- 8002d20: f1b9 0f10 cmp.w r9, #16
- 8002d24: d904 bls.n 8002d30 <_ZN8nav_msgs8Odometry11deserializeEPh+0x88>
- 8002d26: 463a mov r2, r7
- 8002d28: 3110 adds r1, #16
- 8002d2a: 4620 mov r0, r4
- 8002d2c: f007 f829 bl 8009d82 <memmove>
- 8002d30: 19f3 adds r3, r6, r7
- 8002d32: 2200 movs r2, #0
- 8002d34: f109 0804 add.w r8, r9, #4
- 8002d38: 73da strb r2, [r3, #15]
- 8002d3a: 616c str r4, [r5, #20]
- 8002d3c: 7c9c ldrb r4, [r3, #18]
- 8002d3e: 7c59 ldrb r1, [r3, #17]
- 8002d40: 0424 lsls r4, r4, #16
- 8002d42: 7cda ldrb r2, [r3, #19]
- 8002d44: f816 3009 ldrb.w r3, [r6, r9]
- 8002d48: ea44 2401 orr.w r4, r4, r1, lsl #8
- 8002d4c: ea44 6402 orr.w r4, r4, r2, lsl #24
- 8002d50: 431c orrs r4, r3
- 8002d52: 4444 add r4, r8
- 8002d54: 45a0 cmp r8, r4
- 8002d56: d20f bcs.n 8002d78 <_ZN8nav_msgs8Odometry11deserializeEPh+0xd0>
- 8002d58: 1be3 subs r3, r4, r7
- 8002d5a: f107 0215 add.w r2, r7, #21
- 8002d5e: f107 0114 add.w r1, r7, #20
- 8002d62: f107 0013 add.w r0, r7, #19
- 8002d66: 3b14 subs r3, #20
- 8002d68: 4431 add r1, r6
- 8002d6a: 4430 add r0, r6
- 8002d6c: 4294 cmp r4, r2
- 8002d6e: bf2c ite cs
- 8002d70: 461a movcs r2, r3
- 8002d72: 2201 movcc r2, #1
- 8002d74: f007 f805 bl 8009d82 <memmove>
- 8002d78: f108 38ff add.w r8, r8, #4294967295 ; 0xffffffff
- 8002d7c: 1930 adds r0, r6, r4
- 8002d7e: 2200 movs r2, #0
- 8002d80: eb06 0308 add.w r3, r6, r8
- 8002d84: f800 2c01 strb.w r2, [r0, #-1]
- 8002d88: 61ab str r3, [r5, #24]
- 8002d8a: 78c3 ldrb r3, [r0, #3]
- 8002d8c: 095b lsrs r3, r3, #5
- 8002d8e: 62ab str r3, [r5, #40] ; 0x28
- 8002d90: 7902 ldrb r2, [r0, #4]
- 8002d92: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002d96: 62ab str r3, [r5, #40] ; 0x28
- 8002d98: 7942 ldrb r2, [r0, #5]
- 8002d9a: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002d9e: 62ab str r3, [r5, #40] ; 0x28
- 8002da0: 7982 ldrb r2, [r0, #6]
- 8002da2: 04d2 lsls r2, r2, #19
- 8002da4: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002da8: 4313 orrs r3, r2
- 8002daa: 62ab str r3, [r5, #40] ; 0x28
- 8002dac: 79c2 ldrb r2, [r0, #7]
- 8002dae: 7987 ldrb r7, [r0, #6]
- 8002db0: 0111 lsls r1, r2, #4
- 8002db2: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8002db6: ea51 1117 orrs.w r1, r1, r7, lsr #4
- 8002dba: d005 beq.n 8002dc8 <_ZN8nav_msgs8Odometry11deserializeEPh+0x120>
- 8002dbc: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8002dc0: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8002dc4: 62ab str r3, [r5, #40] ; 0x28
- 8002dc6: 79c2 ldrb r2, [r0, #7]
- 8002dc8: 0612 lsls r2, r2, #24
- 8002dca: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002dce: 4313 orrs r3, r2
- 8002dd0: 62ab str r3, [r5, #40] ; 0x28
- 8002dd2: 7ac3 ldrb r3, [r0, #11]
- 8002dd4: 095b lsrs r3, r3, #5
- 8002dd6: 62eb str r3, [r5, #44] ; 0x2c
- 8002dd8: 7b02 ldrb r2, [r0, #12]
- 8002dda: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002dde: 62eb str r3, [r5, #44] ; 0x2c
- 8002de0: 7b42 ldrb r2, [r0, #13]
- 8002de2: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002de6: 62eb str r3, [r5, #44] ; 0x2c
- 8002de8: 7b82 ldrb r2, [r0, #14]
- 8002dea: 04d2 lsls r2, r2, #19
- 8002dec: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002df0: 4313 orrs r3, r2
- 8002df2: 62eb str r3, [r5, #44] ; 0x2c
- 8002df4: 7bc2 ldrb r2, [r0, #15]
- 8002df6: 7b87 ldrb r7, [r0, #14]
- 8002df8: 0111 lsls r1, r2, #4
- 8002dfa: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8002dfe: ea51 1117 orrs.w r1, r1, r7, lsr #4
- 8002e02: d005 beq.n 8002e10 <_ZN8nav_msgs8Odometry11deserializeEPh+0x168>
- 8002e04: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8002e08: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8002e0c: 62eb str r3, [r5, #44] ; 0x2c
- 8002e0e: 7bc2 ldrb r2, [r0, #15]
- 8002e10: 0612 lsls r2, r2, #24
- 8002e12: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002e16: 4313 orrs r3, r2
- 8002e18: 62eb str r3, [r5, #44] ; 0x2c
- 8002e1a: 7cc3 ldrb r3, [r0, #19]
- 8002e1c: 095b lsrs r3, r3, #5
- 8002e1e: 632b str r3, [r5, #48] ; 0x30
- 8002e20: 7d02 ldrb r2, [r0, #20]
- 8002e22: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002e26: 632b str r3, [r5, #48] ; 0x30
- 8002e28: 7d42 ldrb r2, [r0, #21]
- 8002e2a: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002e2e: 632b str r3, [r5, #48] ; 0x30
- 8002e30: 7d82 ldrb r2, [r0, #22]
- 8002e32: 04d2 lsls r2, r2, #19
- 8002e34: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002e38: 4313 orrs r3, r2
- 8002e3a: 632b str r3, [r5, #48] ; 0x30
- 8002e3c: 7dc2 ldrb r2, [r0, #23]
- 8002e3e: 7d87 ldrb r7, [r0, #22]
- 8002e40: 0111 lsls r1, r2, #4
- 8002e42: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8002e46: ea51 1117 orrs.w r1, r1, r7, lsr #4
- 8002e4a: d005 beq.n 8002e58 <_ZN8nav_msgs8Odometry11deserializeEPh+0x1b0>
- 8002e4c: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8002e50: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8002e54: 632b str r3, [r5, #48] ; 0x30
- 8002e56: 7dc2 ldrb r2, [r0, #23]
- 8002e58: 0612 lsls r2, r2, #24
- 8002e5a: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002e5e: 4313 orrs r3, r2
- 8002e60: 632b str r3, [r5, #48] ; 0x30
- 8002e62: 7ec3 ldrb r3, [r0, #27]
- 8002e64: 095b lsrs r3, r3, #5
- 8002e66: 63ab str r3, [r5, #56] ; 0x38
- 8002e68: 7f02 ldrb r2, [r0, #28]
- 8002e6a: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002e6e: 63ab str r3, [r5, #56] ; 0x38
- 8002e70: 7f42 ldrb r2, [r0, #29]
- 8002e72: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002e76: 63ab str r3, [r5, #56] ; 0x38
- 8002e78: 7f82 ldrb r2, [r0, #30]
- 8002e7a: 04d2 lsls r2, r2, #19
- 8002e7c: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002e80: 4313 orrs r3, r2
- 8002e82: 63ab str r3, [r5, #56] ; 0x38
- 8002e84: 7fc2 ldrb r2, [r0, #31]
- 8002e86: 7f87 ldrb r7, [r0, #30]
- 8002e88: 0111 lsls r1, r2, #4
- 8002e8a: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8002e8e: ea51 1117 orrs.w r1, r1, r7, lsr #4
- 8002e92: d005 beq.n 8002ea0 <_ZN8nav_msgs8Odometry11deserializeEPh+0x1f8>
- 8002e94: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8002e98: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8002e9c: 63ab str r3, [r5, #56] ; 0x38
- 8002e9e: 7fc2 ldrb r2, [r0, #31]
- 8002ea0: 0612 lsls r2, r2, #24
- 8002ea2: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002ea6: 4313 orrs r3, r2
- 8002ea8: 63ab str r3, [r5, #56] ; 0x38
- 8002eaa: f890 3023 ldrb.w r3, [r0, #35] ; 0x23
- 8002eae: 095b lsrs r3, r3, #5
- 8002eb0: 63eb str r3, [r5, #60] ; 0x3c
- 8002eb2: f890 2024 ldrb.w r2, [r0, #36] ; 0x24
- 8002eb6: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002eba: 63eb str r3, [r5, #60] ; 0x3c
- 8002ebc: f890 2025 ldrb.w r2, [r0, #37] ; 0x25
- 8002ec0: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002ec4: 63eb str r3, [r5, #60] ; 0x3c
- 8002ec6: f890 2026 ldrb.w r2, [r0, #38] ; 0x26
- 8002eca: 04d2 lsls r2, r2, #19
- 8002ecc: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002ed0: 4313 orrs r3, r2
- 8002ed2: 63eb str r3, [r5, #60] ; 0x3c
- 8002ed4: f890 2027 ldrb.w r2, [r0, #39] ; 0x27
- 8002ed8: f890 7026 ldrb.w r7, [r0, #38] ; 0x26
- 8002edc: 0111 lsls r1, r2, #4
- 8002ede: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8002ee2: ea51 1117 orrs.w r1, r1, r7, lsr #4
- 8002ee6: d006 beq.n 8002ef6 <_ZN8nav_msgs8Odometry11deserializeEPh+0x24e>
- 8002ee8: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8002eec: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8002ef0: 63eb str r3, [r5, #60] ; 0x3c
- 8002ef2: f890 2027 ldrb.w r2, [r0, #39] ; 0x27
- 8002ef6: 0612 lsls r2, r2, #24
- 8002ef8: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002efc: 4313 orrs r3, r2
- 8002efe: 63eb str r3, [r5, #60] ; 0x3c
- 8002f00: f890 302b ldrb.w r3, [r0, #43] ; 0x2b
- 8002f04: 095b lsrs r3, r3, #5
- 8002f06: 642b str r3, [r5, #64] ; 0x40
- 8002f08: f890 202c ldrb.w r2, [r0, #44] ; 0x2c
- 8002f0c: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002f10: 642b str r3, [r5, #64] ; 0x40
- 8002f12: f890 202d ldrb.w r2, [r0, #45] ; 0x2d
- 8002f16: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002f1a: 642b str r3, [r5, #64] ; 0x40
- 8002f1c: f890 202e ldrb.w r2, [r0, #46] ; 0x2e
- 8002f20: 04d2 lsls r2, r2, #19
- 8002f22: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002f26: 4313 orrs r3, r2
- 8002f28: 642b str r3, [r5, #64] ; 0x40
- 8002f2a: f890 202f ldrb.w r2, [r0, #47] ; 0x2f
- 8002f2e: f890 702e ldrb.w r7, [r0, #46] ; 0x2e
- 8002f32: 0111 lsls r1, r2, #4
- 8002f34: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8002f38: ea51 1117 orrs.w r1, r1, r7, lsr #4
- 8002f3c: d006 beq.n 8002f4c <_ZN8nav_msgs8Odometry11deserializeEPh+0x2a4>
- 8002f3e: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8002f42: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8002f46: 642b str r3, [r5, #64] ; 0x40
- 8002f48: f890 202f ldrb.w r2, [r0, #47] ; 0x2f
- 8002f4c: 0612 lsls r2, r2, #24
- 8002f4e: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002f52: 4313 orrs r3, r2
- 8002f54: 642b str r3, [r5, #64] ; 0x40
- 8002f56: f890 3033 ldrb.w r3, [r0, #51] ; 0x33
- 8002f5a: 095b lsrs r3, r3, #5
- 8002f5c: 646b str r3, [r5, #68] ; 0x44
- 8002f5e: f890 2034 ldrb.w r2, [r0, #52] ; 0x34
- 8002f62: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8002f66: 646b str r3, [r5, #68] ; 0x44
- 8002f68: f890 2035 ldrb.w r2, [r0, #53] ; 0x35
- 8002f6c: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8002f70: 646b str r3, [r5, #68] ; 0x44
- 8002f72: f890 2036 ldrb.w r2, [r0, #54] ; 0x36
- 8002f76: 04d2 lsls r2, r2, #19
- 8002f78: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002f7c: 4313 orrs r3, r2
- 8002f7e: 646b str r3, [r5, #68] ; 0x44
- 8002f80: f890 2037 ldrb.w r2, [r0, #55] ; 0x37
- 8002f84: f890 7036 ldrb.w r7, [r0, #54] ; 0x36
- 8002f88: 0111 lsls r1, r2, #4
- 8002f8a: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8002f8e: ea51 1117 orrs.w r1, r1, r7, lsr #4
- 8002f92: d006 beq.n 8002fa2 <_ZN8nav_msgs8Odometry11deserializeEPh+0x2fa>
- 8002f94: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8002f98: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8002f9c: 646b str r3, [r5, #68] ; 0x44
- 8002f9e: f890 2037 ldrb.w r2, [r0, #55] ; 0x37
- 8002fa2: 0612 lsls r2, r2, #24
- 8002fa4: 462f mov r7, r5
- 8002fa6: f105 0cd4 add.w ip, r5, #212 ; 0xd4
- 8002faa: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8002fae: 4313 orrs r3, r2
- 8002fb0: f847 3f44 str.w r3, [r7, #68]!
- 8002fb4: f890 203b ldrb.w r2, [r0, #59] ; 0x3b
- 8002fb8: 0952 lsrs r2, r2, #5
- 8002fba: f847 2f04 str.w r2, [r7, #4]!
- 8002fbe: f890 103c ldrb.w r1, [r0, #60] ; 0x3c
- 8002fc2: ea42 02c1 orr.w r2, r2, r1, lsl #3
- 8002fc6: 603a str r2, [r7, #0]
- 8002fc8: f890 103d ldrb.w r1, [r0, #61] ; 0x3d
- 8002fcc: ea42 21c1 orr.w r1, r2, r1, lsl #11
- 8002fd0: 6039 str r1, [r7, #0]
- 8002fd2: f890 203e ldrb.w r2, [r0, #62] ; 0x3e
- 8002fd6: 04d2 lsls r2, r2, #19
- 8002fd8: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8002fdc: 430a orrs r2, r1
- 8002fde: 603a str r2, [r7, #0]
- 8002fe0: f890 303f ldrb.w r3, [r0, #63] ; 0x3f
- 8002fe4: f890 e03e ldrb.w lr, [r0, #62] ; 0x3e
- 8002fe8: 0619 lsls r1, r3, #24
- 8002fea: 011b lsls r3, r3, #4
- 8002fec: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
- 8002ff0: f403 63fe and.w r3, r3, #2032 ; 0x7f0
- 8002ff4: 4311 orrs r1, r2
- 8002ff6: ea53 131e orrs.w r3, r3, lr, lsr #4
- 8002ffa: f5a3 7360 sub.w r3, r3, #896 ; 0x380
- 8002ffe: f000 8163 beq.w 80032c8 <_ZN8nav_msgs8Odometry11deserializeEPh+0x620>
- 8003002: ea42 53c3 orr.w r3, r2, r3, lsl #23
- 8003006: 4567 cmp r7, ip
- 8003008: f100 0008 add.w r0, r0, #8
- 800300c: 603b str r3, [r7, #0]
- 800300e: f890 2037 ldrb.w r2, [r0, #55] ; 0x37
- 8003012: ea4f 6202 mov.w r2, r2, lsl #24
- 8003016: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 800301a: ea43 0302 orr.w r3, r3, r2
- 800301e: 603b str r3, [r7, #0]
- 8003020: d1c8 bne.n 8002fb4 <_ZN8nav_msgs8Odometry11deserializeEPh+0x30c>
- 8003022: f504 70ac add.w r0, r4, #344 ; 0x158
- 8003026: 4430 add r0, r6
- 8003028: 78c3 ldrb r3, [r0, #3]
- 800302a: 095b lsrs r3, r3, #5
- 800302c: f8c5 30e4 str.w r3, [r5, #228] ; 0xe4
- 8003030: 7902 ldrb r2, [r0, #4]
- 8003032: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8003036: f8c5 30e4 str.w r3, [r5, #228] ; 0xe4
- 800303a: 7942 ldrb r2, [r0, #5]
- 800303c: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8003040: f8c5 30e4 str.w r3, [r5, #228] ; 0xe4
- 8003044: 7982 ldrb r2, [r0, #6]
- 8003046: 04d2 lsls r2, r2, #19
- 8003048: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 800304c: 4313 orrs r3, r2
- 800304e: f8c5 30e4 str.w r3, [r5, #228] ; 0xe4
- 8003052: 79c2 ldrb r2, [r0, #7]
- 8003054: 7986 ldrb r6, [r0, #6]
- 8003056: 0111 lsls r1, r2, #4
- 8003058: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 800305c: ea51 1116 orrs.w r1, r1, r6, lsr #4
- 8003060: d006 beq.n 8003070 <_ZN8nav_msgs8Odometry11deserializeEPh+0x3c8>
- 8003062: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8003066: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 800306a: f8c5 30e4 str.w r3, [r5, #228] ; 0xe4
- 800306e: 79c2 ldrb r2, [r0, #7]
- 8003070: 0612 lsls r2, r2, #24
- 8003072: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8003076: 4313 orrs r3, r2
- 8003078: f8c5 30e4 str.w r3, [r5, #228] ; 0xe4
- 800307c: 7ac3 ldrb r3, [r0, #11]
- 800307e: 095b lsrs r3, r3, #5
- 8003080: f8c5 30e8 str.w r3, [r5, #232] ; 0xe8
- 8003084: 7b02 ldrb r2, [r0, #12]
- 8003086: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 800308a: f8c5 30e8 str.w r3, [r5, #232] ; 0xe8
- 800308e: 7b42 ldrb r2, [r0, #13]
- 8003090: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8003094: f8c5 30e8 str.w r3, [r5, #232] ; 0xe8
- 8003098: 7b82 ldrb r2, [r0, #14]
- 800309a: 04d2 lsls r2, r2, #19
- 800309c: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80030a0: 4313 orrs r3, r2
- 80030a2: f8c5 30e8 str.w r3, [r5, #232] ; 0xe8
- 80030a6: 7bc2 ldrb r2, [r0, #15]
- 80030a8: 7b86 ldrb r6, [r0, #14]
- 80030aa: 0111 lsls r1, r2, #4
- 80030ac: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 80030b0: ea51 1116 orrs.w r1, r1, r6, lsr #4
- 80030b4: d006 beq.n 80030c4 <_ZN8nav_msgs8Odometry11deserializeEPh+0x41c>
- 80030b6: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 80030ba: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 80030be: f8c5 30e8 str.w r3, [r5, #232] ; 0xe8
- 80030c2: 7bc2 ldrb r2, [r0, #15]
- 80030c4: 0612 lsls r2, r2, #24
- 80030c6: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80030ca: 4313 orrs r3, r2
- 80030cc: f8c5 30e8 str.w r3, [r5, #232] ; 0xe8
- 80030d0: 7cc3 ldrb r3, [r0, #19]
- 80030d2: 095b lsrs r3, r3, #5
- 80030d4: f8c5 30ec str.w r3, [r5, #236] ; 0xec
- 80030d8: 7d02 ldrb r2, [r0, #20]
- 80030da: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80030de: f8c5 30ec str.w r3, [r5, #236] ; 0xec
- 80030e2: 7d42 ldrb r2, [r0, #21]
- 80030e4: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 80030e8: f8c5 30ec str.w r3, [r5, #236] ; 0xec
- 80030ec: 7d82 ldrb r2, [r0, #22]
- 80030ee: 04d2 lsls r2, r2, #19
- 80030f0: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80030f4: 4313 orrs r3, r2
- 80030f6: f8c5 30ec str.w r3, [r5, #236] ; 0xec
- 80030fa: 7dc2 ldrb r2, [r0, #23]
- 80030fc: 7d86 ldrb r6, [r0, #22]
- 80030fe: 0111 lsls r1, r2, #4
- 8003100: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8003104: ea51 1116 orrs.w r1, r1, r6, lsr #4
- 8003108: d006 beq.n 8003118 <_ZN8nav_msgs8Odometry11deserializeEPh+0x470>
- 800310a: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 800310e: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8003112: f8c5 30ec str.w r3, [r5, #236] ; 0xec
- 8003116: 7dc2 ldrb r2, [r0, #23]
- 8003118: 0612 lsls r2, r2, #24
- 800311a: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 800311e: 4313 orrs r3, r2
- 8003120: f8c5 30ec str.w r3, [r5, #236] ; 0xec
- 8003124: 7ec3 ldrb r3, [r0, #27]
- 8003126: 095b lsrs r3, r3, #5
- 8003128: f8c5 30f4 str.w r3, [r5, #244] ; 0xf4
- 800312c: 7f02 ldrb r2, [r0, #28]
- 800312e: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8003132: f8c5 30f4 str.w r3, [r5, #244] ; 0xf4
- 8003136: 7f42 ldrb r2, [r0, #29]
- 8003138: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 800313c: f8c5 30f4 str.w r3, [r5, #244] ; 0xf4
- 8003140: 7f82 ldrb r2, [r0, #30]
- 8003142: 04d2 lsls r2, r2, #19
- 8003144: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8003148: 4313 orrs r3, r2
- 800314a: f8c5 30f4 str.w r3, [r5, #244] ; 0xf4
- 800314e: 7fc2 ldrb r2, [r0, #31]
- 8003150: 7f86 ldrb r6, [r0, #30]
- 8003152: 0111 lsls r1, r2, #4
- 8003154: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 8003158: ea51 1116 orrs.w r1, r1, r6, lsr #4
- 800315c: d006 beq.n 800316c <_ZN8nav_msgs8Odometry11deserializeEPh+0x4c4>
- 800315e: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8003162: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8003166: f8c5 30f4 str.w r3, [r5, #244] ; 0xf4
- 800316a: 7fc2 ldrb r2, [r0, #31]
- 800316c: 0612 lsls r2, r2, #24
- 800316e: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8003172: 4313 orrs r3, r2
- 8003174: f8c5 30f4 str.w r3, [r5, #244] ; 0xf4
- 8003178: f890 3023 ldrb.w r3, [r0, #35] ; 0x23
- 800317c: 095b lsrs r3, r3, #5
- 800317e: f8c5 30f8 str.w r3, [r5, #248] ; 0xf8
- 8003182: f890 2024 ldrb.w r2, [r0, #36] ; 0x24
- 8003186: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 800318a: f8c5 30f8 str.w r3, [r5, #248] ; 0xf8
- 800318e: f890 2025 ldrb.w r2, [r0, #37] ; 0x25
- 8003192: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 8003196: f8c5 30f8 str.w r3, [r5, #248] ; 0xf8
- 800319a: f890 2026 ldrb.w r2, [r0, #38] ; 0x26
- 800319e: 04d2 lsls r2, r2, #19
- 80031a0: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 80031a4: 4313 orrs r3, r2
- 80031a6: f8c5 30f8 str.w r3, [r5, #248] ; 0xf8
- 80031aa: f890 2027 ldrb.w r2, [r0, #39] ; 0x27
- 80031ae: f890 6026 ldrb.w r6, [r0, #38] ; 0x26
- 80031b2: 0111 lsls r1, r2, #4
- 80031b4: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 80031b8: ea51 1116 orrs.w r1, r1, r6, lsr #4
- 80031bc: d007 beq.n 80031ce <_ZN8nav_msgs8Odometry11deserializeEPh+0x526>
- 80031be: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 80031c2: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 80031c6: f8c5 30f8 str.w r3, [r5, #248] ; 0xf8
- 80031ca: f890 2027 ldrb.w r2, [r0, #39] ; 0x27
- 80031ce: 0612 lsls r2, r2, #24
- 80031d0: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80031d4: 4313 orrs r3, r2
- 80031d6: f8c5 30f8 str.w r3, [r5, #248] ; 0xf8
- 80031da: f890 302b ldrb.w r3, [r0, #43] ; 0x2b
- 80031de: 095b lsrs r3, r3, #5
- 80031e0: f8c5 30fc str.w r3, [r5, #252] ; 0xfc
- 80031e4: f890 202c ldrb.w r2, [r0, #44] ; 0x2c
- 80031e8: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 80031ec: f8c5 30fc str.w r3, [r5, #252] ; 0xfc
- 80031f0: f890 202d ldrb.w r2, [r0, #45] ; 0x2d
- 80031f4: ea43 23c2 orr.w r3, r3, r2, lsl #11
- 80031f8: f8c5 30fc str.w r3, [r5, #252] ; 0xfc
- 80031fc: f890 202e ldrb.w r2, [r0, #46] ; 0x2e
- 8003200: 04d2 lsls r2, r2, #19
- 8003202: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 8003206: 4313 orrs r3, r2
- 8003208: f8c5 30fc str.w r3, [r5, #252] ; 0xfc
- 800320c: f890 202f ldrb.w r2, [r0, #47] ; 0x2f
- 8003210: f890 602e ldrb.w r6, [r0, #46] ; 0x2e
- 8003214: 0111 lsls r1, r2, #4
- 8003216: f401 61fe and.w r1, r1, #2032 ; 0x7f0
- 800321a: ea51 1116 orrs.w r1, r1, r6, lsr #4
- 800321e: d007 beq.n 8003230 <_ZN8nav_msgs8Odometry11deserializeEPh+0x588>
- 8003220: f5a1 7160 sub.w r1, r1, #896 ; 0x380
- 8003224: ea43 53c1 orr.w r3, r3, r1, lsl #23
- 8003228: f8c5 30fc str.w r3, [r5, #252] ; 0xfc
- 800322c: f890 202f ldrb.w r2, [r0, #47] ; 0x2f
- 8003230: 0612 lsls r2, r2, #24
- 8003232: 4629 mov r1, r5
- 8003234: f505 75c6 add.w r5, r5, #396 ; 0x18c
- 8003238: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 800323c: 4313 orrs r3, r2
- 800323e: f841 3ffc str.w r3, [r1, #252]!
- 8003242: f890 2033 ldrb.w r2, [r0, #51] ; 0x33
- 8003246: 0952 lsrs r2, r2, #5
- 8003248: f841 2f04 str.w r2, [r1, #4]!
- 800324c: f890 3034 ldrb.w r3, [r0, #52] ; 0x34
- 8003250: ea42 02c3 orr.w r2, r2, r3, lsl #3
- 8003254: 600a str r2, [r1, #0]
- 8003256: f890 3035 ldrb.w r3, [r0, #53] ; 0x35
- 800325a: ea42 23c3 orr.w r3, r2, r3, lsl #11
- 800325e: 600b str r3, [r1, #0]
- 8003260: f890 2036 ldrb.w r2, [r0, #54] ; 0x36
- 8003264: 04d2 lsls r2, r2, #19
- 8003266: f402 02f0 and.w r2, r2, #7864320 ; 0x780000
- 800326a: 431a orrs r2, r3
- 800326c: 600a str r2, [r1, #0]
- 800326e: f890 3037 ldrb.w r3, [r0, #55] ; 0x37
- 8003272: f890 7036 ldrb.w r7, [r0, #54] ; 0x36
- 8003276: 061e lsls r6, r3, #24
- 8003278: 011b lsls r3, r3, #4
- 800327a: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000
- 800327e: f403 63fe and.w r3, r3, #2032 ; 0x7f0
- 8003282: 4316 orrs r6, r2
- 8003284: ea53 1317 orrs.w r3, r3, r7, lsr #4
- 8003288: f5a3 7360 sub.w r3, r3, #896 ; 0x380
- 800328c: d013 beq.n 80032b6 <_ZN8nav_msgs8Odometry11deserializeEPh+0x60e>
- 800328e: ea42 53c3 orr.w r3, r2, r3, lsl #23
- 8003292: 428d cmp r5, r1
- 8003294: f100 0008 add.w r0, r0, #8
- 8003298: 600b str r3, [r1, #0]
- 800329a: f890 202f ldrb.w r2, [r0, #47] ; 0x2f
- 800329e: ea4f 6202 mov.w r2, r2, lsl #24
- 80032a2: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 80032a6: ea43 0302 orr.w r3, r3, r2
- 80032aa: 600b str r3, [r1, #0]
- 80032ac: d1c9 bne.n 8003242 <_ZN8nav_msgs8Odometry11deserializeEPh+0x59a>
- 80032ae: f504 702a add.w r0, r4, #680 ; 0x2a8
- 80032b2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
- 80032b6: 428d cmp r5, r1
- 80032b8: 600e str r6, [r1, #0]
- 80032ba: f100 0008 add.w r0, r0, #8
- 80032be: d1c0 bne.n 8003242 <_ZN8nav_msgs8Odometry11deserializeEPh+0x59a>
- 80032c0: f504 702a add.w r0, r4, #680 ; 0x2a8
- 80032c4: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
- 80032c8: 4567 cmp r7, ip
- 80032ca: 6039 str r1, [r7, #0]
- 80032cc: f100 0008 add.w r0, r0, #8
- 80032d0: f47f ae70 bne.w 8002fb4 <_ZN8nav_msgs8Odometry11deserializeEPh+0x30c>
- 80032d4: e6a5 b.n 8003022 <_ZN8nav_msgs8Odometry11deserializeEPh+0x37a>
- 80032d6: bf00 nop
-
-080032d8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE>:
- 80032d8: 2963 cmp r1, #99 ; 0x63
- 80032da: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
- 80032de: b085 sub sp, #20
- 80032e0: dd03 ble.n 80032ea <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x12>
- 80032e2: f890 5680 ldrb.w r5, [r0, #1664] ; 0x680
- 80032e6: 2d00 cmp r5, #0
- 80032e8: d056 beq.n 8003398 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0xc0>
- 80032ea: 4604 mov r4, r0
- 80032ec: 6813 ldr r3, [r2, #0]
- 80032ee: 460d mov r5, r1
- 80032f0: 4610 mov r0, r2
- 80032f2: f204 31ab addw r1, r4, #939 ; 0x3ab
- 80032f6: 681b ldr r3, [r3, #0]
- 80032f8: 4798 blx r3
- 80032fa: f3c0 2207 ubfx r2, r0, #8, #8
- 80032fe: b2c1 uxtb r1, r0
- 8003300: f345 2707 sbfx r7, r5, #8, #8
- 8003304: f64f 66ff movw r6, #65279 ; 0xfeff
- 8003308: f884 53a9 strb.w r5, [r4, #937] ; 0x3a9
- 800330c: 188b adds r3, r1, r2
- 800330e: f884 73aa strb.w r7, [r4, #938] ; 0x3aa
- 8003312: f884 13a6 strb.w r1, [r4, #934] ; 0x3a6
- 8003316: 43db mvns r3, r3
- 8003318: f884 23a7 strb.w r2, [r4, #935] ; 0x3a7
- 800331c: f8a4 63a4 strh.w r6, [r4, #932] ; 0x3a4
- 8003320: f884 33a8 strb.w r3, [r4, #936] ; 0x3a8
- 8003324: 1c43 adds r3, r0, #1
- 8003326: db67 blt.n 80033f8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x120>
- 8003328: f204 35aa addw r5, r4, #938 ; 0x3aa
- 800332c: f504 736a add.w r3, r4, #936 ; 0x3a8
- 8003330: 2200 movs r2, #0
- 8003332: 4405 add r5, r0
- 8003334: f813 1f01 ldrb.w r1, [r3, #1]!
- 8003338: 429d cmp r5, r3
- 800333a: 440a add r2, r1
- 800333c: d1fa bne.n 8003334 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x5c>
- 800333e: 43d2 mvns r2, r2
- 8003340: b2d2 uxtb r2, r2
- 8003342: f100 0508 add.w r5, r0, #8
- 8003346: 1823 adds r3, r4, r0
- 8003348: f5b5 7f00 cmp.w r5, #512 ; 0x200
- 800334c: f883 23ab strb.w r2, [r3, #939] ; 0x3ab
- 8003350: dc54 bgt.n 80033fc <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x124>
- 8003352: f8d4 018c ldr.w r0, [r4, #396] ; 0x18c
- 8003356: f5b5 7f80 cmp.w r5, #256 ; 0x100
- 800335a: 462f mov r7, r5
- 800335c: f104 0804 add.w r8, r4, #4
- 8003360: f5c0 7680 rsb r6, r0, #256 ; 0x100
- 8003364: bfa8 it ge
- 8003366: f44f 7780 movge.w r7, #256 ; 0x100
- 800336a: f504 7969 add.w r9, r4, #932 ; 0x3a4
- 800336e: 3088 adds r0, #136 ; 0x88
- 8003370: 42be cmp r6, r7
- 8003372: 4649 mov r1, r9
- 8003374: 4440 add r0, r8
- 8003376: bf28 it cs
- 8003378: 463e movcs r6, r7
- 800337a: 4632 mov r2, r6
- 800337c: f006 fcf6 bl 8009d6c <memcpy>
- 8003380: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8003384: 42b7 cmp r7, r6
- 8003386: 443b add r3, r7
- 8003388: b2db uxtb r3, r3
- 800338a: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 800338e: d107 bne.n 80033a0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0xc8>
- 8003390: 6860 ldr r0, [r4, #4]
- 8003392: 6f43 ldr r3, [r0, #116] ; 0x74
- 8003394: 2b20 cmp r3, #32
- 8003396: d00e beq.n 80033b6 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0xde>
- 8003398: 4628 mov r0, r5
- 800339a: b005 add sp, #20
- 800339c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
- 80033a0: 1bba subs r2, r7, r6
- 80033a2: eb09 0106 add.w r1, r9, r6
- 80033a6: f104 008c add.w r0, r4, #140 ; 0x8c
- 80033aa: f006 fcdf bl 8009d6c <memcpy>
- 80033ae: 6860 ldr r0, [r4, #4]
- 80033b0: 6f43 ldr r3, [r0, #116] ; 0x74
- 80033b2: 2b20 cmp r3, #32
- 80033b4: d1f0 bne.n 8003398 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0xc0>
- 80033b6: 4e59 ldr r6, [pc, #356] ; (800351c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x244>)
- 80033b8: 7833 ldrb r3, [r6, #0]
- 80033ba: 2b00 cmp r3, #0
- 80033bc: d1ec bne.n 8003398 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0xc0>
- 80033be: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 80033c2: 2301 movs r3, #1
- 80033c4: f8d4 2190 ldr.w r2, [r4, #400] ; 0x190
- 80033c8: 7033 strb r3, [r6, #0]
- 80033ca: 4291 cmp r1, r2
- 80033cc: d011 beq.n 80033f2 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x11a>
- 80033ce: b293 uxth r3, r2
- 80033d0: bf8c ite hi
- 80033d2: 1acb subhi r3, r1, r3
- 80033d4: f5c3 7380 rsbls r3, r3, #256 ; 0x100
- 80033d8: f102 0188 add.w r1, r2, #136 ; 0x88
- 80033dc: b29f uxth r7, r3
- 80033de: 4441 add r1, r8
- 80033e0: 463a mov r2, r7
- 80033e2: f004 fce5 bl 8007db0 <HAL_UART_Transmit_DMA>
- 80033e6: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 80033ea: 443b add r3, r7
- 80033ec: b2db uxtb r3, r3
- 80033ee: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 80033f2: 2300 movs r3, #0
- 80033f4: 7033 strb r3, [r6, #0]
- 80033f6: e7cf b.n 8003398 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0xc0>
- 80033f8: 22ff movs r2, #255 ; 0xff
- 80033fa: e7a2 b.n 8003342 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x6a>
- 80033fc: 6822 ldr r2, [r4, #0]
- 80033fe: 2303 movs r3, #3
- 8003400: 4947 ldr r1, [pc, #284] ; (8003520 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x248>)
- 8003402: f88d 3008 strb.w r3, [sp, #8]
- 8003406: 6816 ldr r6, [r2, #0]
- 8003408: 4a46 ldr r2, [pc, #280] ; (8003524 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x24c>)
- 800340a: 4d47 ldr r5, [pc, #284] ; (8003528 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x250>)
- 800340c: 4296 cmp r6, r2
- 800340e: 9101 str r1, [sp, #4]
- 8003410: 9503 str r5, [sp, #12]
- 8003412: d17d bne.n 8003510 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x238>
- 8003414: 2238 movs r2, #56 ; 0x38
- 8003416: f504 776c add.w r7, r4, #944 ; 0x3b0
- 800341a: f105 0c30 add.w ip, r5, #48 ; 0x30
- 800341e: f884 33ab strb.w r3, [r4, #939] ; 0x3ab
- 8003422: f8c4 23ac str.w r2, [r4, #940] ; 0x3ac
- 8003426: 462e mov r6, r5
- 8003428: 3710 adds r7, #16
- 800342a: 3510 adds r5, #16
- 800342c: ce0f ldmia r6!, {r0, r1, r2, r3}
- 800342e: 4566 cmp r6, ip
- 8003430: f847 0c10 str.w r0, [r7, #-16]
- 8003434: f847 1c0c str.w r1, [r7, #-12]
- 8003438: f847 2c08 str.w r2, [r7, #-8]
- 800343c: f847 3c04 str.w r3, [r7, #-4]
- 8003440: d1f1 bne.n 8003426 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x14e>
- 8003442: 2600 movs r6, #0
- 8003444: f8df e0e4 ldr.w lr, [pc, #228] ; 800352c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x254>
- 8003448: f240 7cc2 movw ip, #1986 ; 0x7c2
- 800344c: f504 736a add.w r3, r4, #936 ; 0x3a8
- 8003450: 4632 mov r2, r6
- 8003452: cd03 ldmia r5!, {r0, r1}
- 8003454: 6038 str r0, [r7, #0]
- 8003456: f204 30e7 addw r0, r4, #999 ; 0x3e7
- 800345a: 6079 str r1, [r7, #4]
- 800345c: f884 63aa strb.w r6, [r4, #938] ; 0x3aa
- 8003460: f8c4 e3a4 str.w lr, [r4, #932] ; 0x3a4
- 8003464: f8a4 c3a8 strh.w ip, [r4, #936] ; 0x3a8
- 8003468: f813 1f01 ldrb.w r1, [r3, #1]!
- 800346c: 4283 cmp r3, r0
- 800346e: 440a add r2, r1
- 8003470: d1fa bne.n 8003468 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x190>
- 8003472: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8003476: 43d2 mvns r2, r2
- 8003478: 1d25 adds r5, r4, #4
- 800347a: f504 7769 add.w r7, r4, #932 ; 0x3a4
- 800347e: f5c3 7680 rsb r6, r3, #256 ; 0x100
- 8003482: 3388 adds r3, #136 ; 0x88
- 8003484: f884 23e8 strb.w r2, [r4, #1000] ; 0x3e8
- 8003488: 4639 mov r1, r7
- 800348a: 2e45 cmp r6, #69 ; 0x45
- 800348c: 46b0 mov r8, r6
- 800348e: eb05 0003 add.w r0, r5, r3
- 8003492: bf28 it cs
- 8003494: f04f 0845 movcs.w r8, #69 ; 0x45
- 8003498: 4642 mov r2, r8
- 800349a: f006 fc67 bl 8009d6c <memcpy>
- 800349e: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 80034a2: 2e44 cmp r6, #68 ; 0x44
- 80034a4: f103 0345 add.w r3, r3, #69 ; 0x45
- 80034a8: b2db uxtb r3, r3
- 80034aa: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 80034ae: d807 bhi.n 80034c0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x1e8>
- 80034b0: eb07 0108 add.w r1, r7, r8
- 80034b4: f1c8 0245 rsb r2, r8, #69 ; 0x45
- 80034b8: f104 008c add.w r0, r4, #140 ; 0x8c
- 80034bc: f006 fc56 bl 8009d6c <memcpy>
- 80034c0: 6860 ldr r0, [r4, #4]
- 80034c2: 6f43 ldr r3, [r0, #116] ; 0x74
- 80034c4: 2b20 cmp r3, #32
- 80034c6: d002 beq.n 80034ce <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x1f6>
- 80034c8: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff
- 80034cc: e764 b.n 8003398 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0xc0>
- 80034ce: 4e13 ldr r6, [pc, #76] ; (800351c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x244>)
- 80034d0: 7833 ldrb r3, [r6, #0]
- 80034d2: 2b00 cmp r3, #0
- 80034d4: d1f8 bne.n 80034c8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x1f0>
- 80034d6: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 80034da: 2301 movs r3, #1
- 80034dc: f8d4 2190 ldr.w r2, [r4, #400] ; 0x190
- 80034e0: 7033 strb r3, [r6, #0]
- 80034e2: 4291 cmp r1, r2
- 80034e4: d011 beq.n 800350a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x232>
- 80034e6: b293 uxth r3, r2
- 80034e8: bf8c ite hi
- 80034ea: 1acb subhi r3, r1, r3
- 80034ec: f5c3 7380 rsbls r3, r3, #256 ; 0x100
- 80034f0: f102 0188 add.w r1, r2, #136 ; 0x88
- 80034f4: b29f uxth r7, r3
- 80034f6: 4429 add r1, r5
- 80034f8: 463a mov r2, r7
- 80034fa: f004 fc59 bl 8007db0 <HAL_UART_Transmit_DMA>
- 80034fe: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8003502: 443b add r3, r7
- 8003504: b2db uxtb r3, r3
- 8003506: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 800350a: 2300 movs r3, #0
- 800350c: 7033 strb r3, [r6, #0]
- 800350e: e7db b.n 80034c8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x1f0>
- 8003510: 4620 mov r0, r4
- 8003512: aa01 add r2, sp, #4
- 8003514: 2107 movs r1, #7
- 8003516: 47b0 blx r6
- 8003518: e7d6 b.n 80034c8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE7publishEiPKNS_3MsgE+0x1f0>
- 800351a: bf00 nop
- 800351c: 2000009c .word 0x2000009c
- 8003520: 0800a010 .word 0x0800a010
- 8003524: 080032d9 .word 0x080032d9
- 8003528: 0800a380 .word 0x0800a380
- 800352c: 003dfeff .word 0x003dfeff
-
-08003530 <_ZN8nav_msgs8OdometryC1Ev>:
- 8003530: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8003532: 4604 mov r4, r0
- 8003534: 4b20 ldr r3, [pc, #128] ; (80035b8 <_ZN8nav_msgs8OdometryC1Ev+0x88>)
- 8003536: 4d21 ldr r5, [pc, #132] ; (80035bc <_ZN8nav_msgs8OdometryC1Ev+0x8c>)
- 8003538: 2600 movs r6, #0
- 800353a: 61e3 str r3, [r4, #28]
- 800353c: 2790 movs r7, #144 ; 0x90
- 800353e: 6225 str r5, [r4, #32]
- 8003540: 4631 mov r1, r6
- 8003542: 4b1f ldr r3, [pc, #124] ; (80035c0 <_ZN8nav_msgs8OdometryC1Ev+0x90>)
- 8003544: 4d1f ldr r5, [pc, #124] ; (80035c4 <_ZN8nav_msgs8OdometryC1Ev+0x94>)
- 8003546: 6263 str r3, [r4, #36] ; 0x24
- 8003548: 6365 str r5, [r4, #52] ; 0x34
- 800354a: 2500 movs r5, #0
- 800354c: 4b1e ldr r3, [pc, #120] ; (80035c8 <_ZN8nav_msgs8OdometryC1Ev+0x98>)
- 800354e: 481f ldr r0, [pc, #124] ; (80035cc <_ZN8nav_msgs8OdometryC1Ev+0x9c>)
- 8003550: 4a1f ldr r2, [pc, #124] ; (80035d0 <_ZN8nav_msgs8OdometryC1Ev+0xa0>)
- 8003552: 6020 str r0, [r4, #0]
- 8003554: f104 0048 add.w r0, r4, #72 ; 0x48
- 8003558: 6062 str r2, [r4, #4]
- 800355a: 463a mov r2, r7
- 800355c: 61a3 str r3, [r4, #24]
- 800355e: 62a5 str r5, [r4, #40] ; 0x28
- 8003560: 62e5 str r5, [r4, #44] ; 0x2c
- 8003562: 6325 str r5, [r4, #48] ; 0x30
- 8003564: 63a5 str r5, [r4, #56] ; 0x38
- 8003566: 63e5 str r5, [r4, #60] ; 0x3c
- 8003568: 6425 str r5, [r4, #64] ; 0x40
- 800356a: 6465 str r5, [r4, #68] ; 0x44
- 800356c: e9c4 6304 strd r6, r3, [r4, #16]
- 8003570: e9c4 6602 strd r6, r6, [r4, #8]
- 8003574: f006 fc1e bl 8009db4 <memset>
- 8003578: 4b16 ldr r3, [pc, #88] ; (80035d4 <_ZN8nav_msgs8OdometryC1Ev+0xa4>)
- 800357a: f8df e05c ldr.w lr, [pc, #92] ; 80035d8 <_ZN8nav_msgs8OdometryC1Ev+0xa8>
- 800357e: 463a mov r2, r7
- 8003580: f8df c058 ldr.w ip, [pc, #88] ; 80035dc <_ZN8nav_msgs8OdometryC1Ev+0xac>
- 8003584: 4631 mov r1, r6
- 8003586: f8c4 50e4 str.w r5, [r4, #228] ; 0xe4
- 800358a: f504 7080 add.w r0, r4, #256 ; 0x100
- 800358e: f8c4 50e8 str.w r5, [r4, #232] ; 0xe8
- 8003592: f8c4 50ec str.w r5, [r4, #236] ; 0xec
- 8003596: f8c4 50f4 str.w r5, [r4, #244] ; 0xf4
- 800359a: f8c4 50f8 str.w r5, [r4, #248] ; 0xf8
- 800359e: f8c4 50fc str.w r5, [r4, #252] ; 0xfc
- 80035a2: f8c4 30e0 str.w r3, [r4, #224] ; 0xe0
- 80035a6: f8c4 30f0 str.w r3, [r4, #240] ; 0xf0
- 80035aa: e9c4 ec36 strd lr, ip, [r4, #216] ; 0xd8
- 80035ae: f006 fc01 bl 8009db4 <memset>
- 80035b2: 4620 mov r0, r4
- 80035b4: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 80035b6: bf00 nop
- 80035b8: 0800a0a0 .word 0x0800a0a0
- 80035bc: 0800a088 .word 0x0800a088
- 80035c0: 0800a058 .word 0x0800a058
- 80035c4: 0800a070 .word 0x0800a070
- 80035c8: 0800a3b8 .word 0x0800a3b8
- 80035cc: 0800a100 .word 0x0800a100
- 80035d0: 0800a040 .word 0x0800a040
- 80035d4: 0800a0b8 .word 0x0800a0b8
- 80035d8: 0800a0e8 .word 0x0800a0e8
- 80035dc: 0800a0d0 .word 0x0800a0d0
-
-080035e0 <_Z18SystemClock_Configv>:
- 80035e0: b530 push {r4, r5, lr}
- 80035e2: 2400 movs r4, #0
- 80035e4: b0b9 sub sp, #228 ; 0xe4
- 80035e6: 2230 movs r2, #48 ; 0x30
- 80035e8: 2501 movs r5, #1
- 80035ea: 4621 mov r1, r4
- 80035ec: a808 add r0, sp, #32
- 80035ee: f006 fbe1 bl 8009db4 <memset>
- 80035f2: 4621 mov r1, r4
- 80035f4: a814 add r0, sp, #80 ; 0x50
- 80035f6: 2290 movs r2, #144 ; 0x90
- 80035f8: 9406 str r4, [sp, #24]
- 80035fa: e9cd 4402 strd r4, r4, [sp, #8]
- 80035fe: e9cd 4404 strd r4, r4, [sp, #16]
- 8003602: f006 fbd7 bl 8009db4 <memset>
- 8003606: 4b19 ldr r3, [pc, #100] ; (800366c <_Z18SystemClock_Configv+0x8c>)
- 8003608: 4a19 ldr r2, [pc, #100] ; (8003670 <_Z18SystemClock_Configv+0x90>)
- 800360a: 2002 movs r0, #2
- 800360c: 6c19 ldr r1, [r3, #64] ; 0x40
- 800360e: f041 5180 orr.w r1, r1, #268435456 ; 0x10000000
- 8003612: 6419 str r1, [r3, #64] ; 0x40
- 8003614: 2110 movs r1, #16
- 8003616: 6c1b ldr r3, [r3, #64] ; 0x40
- 8003618: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 800361c: 9300 str r3, [sp, #0]
- 800361e: 9b00 ldr r3, [sp, #0]
- 8003620: 6813 ldr r3, [r2, #0]
- 8003622: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 8003626: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 800362a: 6013 str r3, [r2, #0]
- 800362c: 6813 ldr r3, [r2, #0]
- 800362e: 9007 str r0, [sp, #28]
- 8003630: a807 add r0, sp, #28
- 8003632: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8003636: 910b str r1, [sp, #44] ; 0x2c
- 8003638: 940d str r4, [sp, #52] ; 0x34
- 800363a: 9301 str r3, [sp, #4]
- 800363c: 9b01 ldr r3, [sp, #4]
- 800363e: 950a str r5, [sp, #40] ; 0x28
- 8003640: f003 f8ec bl 800681c <HAL_RCC_OscConfig>
- 8003644: 230f movs r3, #15
- 8003646: 4621 mov r1, r4
- 8003648: a802 add r0, sp, #8
- 800364a: 9302 str r3, [sp, #8]
- 800364c: e9cd 4403 strd r4, r4, [sp, #12]
- 8003650: e9cd 4405 strd r4, r4, [sp, #20]
- 8003654: f003 fab0 bl 8006bb8 <HAL_RCC_ClockConfig>
- 8003658: f44f 6310 mov.w r3, #2304 ; 0x900
- 800365c: a814 add r0, sp, #80 ; 0x50
- 800365e: 9427 str r4, [sp, #156] ; 0x9c
- 8003660: 942a str r4, [sp, #168] ; 0xa8
- 8003662: 9314 str r3, [sp, #80] ; 0x50
- 8003664: f003 fbc6 bl 8006df4 <HAL_RCCEx_PeriphCLKConfig>
- 8003668: b039 add sp, #228 ; 0xe4
- 800366a: bd30 pop {r4, r5, pc}
- 800366c: 40023800 .word 0x40023800
- 8003670: 40007000 .word 0x40007000
-
-08003674 <main>:
- 8003674: 2400 movs r4, #0
- 8003676: 4dc0 ldr r5, [pc, #768] ; (8003978 <main+0x304>)
- 8003678: 2601 movs r6, #1
- 800367a: f04f 0808 mov.w r8, #8
- 800367e: f04f 39ff mov.w r9, #4294967295 ; 0xffffffff
- 8003682: f44f 5a80 mov.w sl, #4096 ; 0x1000
- 8003686: e92d 4880 stmdb sp!, {r7, fp, lr}
- 800368a: b09b sub sp, #108 ; 0x6c
- 800368c: 2703 movs r7, #3
- 800368e: f002 fd49 bl 8006124 <HAL_Init>
- 8003692: f8df b324 ldr.w fp, [pc, #804] ; 80039b8 <main+0x344>
- 8003696: f7ff ffa3 bl 80035e0 <_Z18SystemClock_Configv>
- 800369a: 9413 str r4, [sp, #76] ; 0x4c
- 800369c: 9414 str r4, [sp, #80] ; 0x50
- 800369e: 4622 mov r2, r4
- 80036a0: 9415 str r4, [sp, #84] ; 0x54
- 80036a2: f44f 4160 mov.w r1, #57344 ; 0xe000
- 80036a6: 48b5 ldr r0, [pc, #724] ; (800397c <main+0x308>)
- 80036a8: e9cd 4411 strd r4, r4, [sp, #68] ; 0x44
- 80036ac: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036ae: f043 0304 orr.w r3, r3, #4
- 80036b2: 632b str r3, [r5, #48] ; 0x30
- 80036b4: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036b6: f003 0304 and.w r3, r3, #4
- 80036ba: 9304 str r3, [sp, #16]
- 80036bc: 9b04 ldr r3, [sp, #16]
- 80036be: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036c0: 4333 orrs r3, r6
- 80036c2: 632b str r3, [r5, #48] ; 0x30
- 80036c4: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036c6: 4033 ands r3, r6
- 80036c8: 9305 str r3, [sp, #20]
- 80036ca: 9b05 ldr r3, [sp, #20]
- 80036cc: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036ce: f043 0320 orr.w r3, r3, #32
- 80036d2: 632b str r3, [r5, #48] ; 0x30
- 80036d4: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036d6: f003 0320 and.w r3, r3, #32
- 80036da: 9306 str r3, [sp, #24]
- 80036dc: 9b06 ldr r3, [sp, #24]
- 80036de: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036e0: f043 0310 orr.w r3, r3, #16
- 80036e4: 632b str r3, [r5, #48] ; 0x30
- 80036e6: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036e8: f003 0310 and.w r3, r3, #16
- 80036ec: 9307 str r3, [sp, #28]
- 80036ee: 9b07 ldr r3, [sp, #28]
- 80036f0: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036f2: ea43 0308 orr.w r3, r3, r8
- 80036f6: 632b str r3, [r5, #48] ; 0x30
- 80036f8: 6b2b ldr r3, [r5, #48] ; 0x30
- 80036fa: ea03 0308 and.w r3, r3, r8
- 80036fe: 9308 str r3, [sp, #32]
- 8003700: 9b08 ldr r3, [sp, #32]
- 8003702: 6b2b ldr r3, [r5, #48] ; 0x30
- 8003704: f043 0302 orr.w r3, r3, #2
- 8003708: 632b str r3, [r5, #48] ; 0x30
- 800370a: 6b2b ldr r3, [r5, #48] ; 0x30
- 800370c: f003 0302 and.w r3, r3, #2
- 8003710: 9309 str r3, [sp, #36] ; 0x24
- 8003712: 9b09 ldr r3, [sp, #36] ; 0x24
- 8003714: f003 f87e bl 8006814 <HAL_GPIO_WritePin>
- 8003718: 4622 mov r2, r4
- 800371a: f44f 7180 mov.w r1, #256 ; 0x100
- 800371e: 4898 ldr r0, [pc, #608] ; (8003980 <main+0x30c>)
- 8003720: f003 f878 bl 8006814 <HAL_GPIO_WritePin>
- 8003724: a911 add r1, sp, #68 ; 0x44
- 8003726: 4897 ldr r0, [pc, #604] ; (8003984 <main+0x310>)
- 8003728: 9413 str r4, [sp, #76] ; 0x4c
- 800372a: e9cd 6711 strd r6, r7, [sp, #68] ; 0x44
- 800372e: f002 ff53 bl 80065d8 <HAL_GPIO_Init>
- 8003732: a911 add r1, sp, #68 ; 0x44
- 8003734: 4894 ldr r0, [pc, #592] ; (8003988 <main+0x314>)
- 8003736: f8cd 8044 str.w r8, [sp, #68] ; 0x44
- 800373a: e9cd 7412 strd r7, r4, [sp, #72] ; 0x48
- 800373e: f002 ff4b bl 80065d8 <HAL_GPIO_Init>
- 8003742: 2340 movs r3, #64 ; 0x40
- 8003744: a911 add r1, sp, #68 ; 0x44
- 8003746: 4890 ldr r0, [pc, #576] ; (8003988 <main+0x314>)
- 8003748: 9311 str r3, [sp, #68] ; 0x44
- 800374a: e9cd 4412 strd r4, r4, [sp, #72] ; 0x48
- 800374e: f002 ff43 bl 80065d8 <HAL_GPIO_Init>
- 8003752: f44f 4360 mov.w r3, #57344 ; 0xe000
- 8003756: a911 add r1, sp, #68 ; 0x44
- 8003758: 4888 ldr r0, [pc, #544] ; (800397c <main+0x308>)
- 800375a: 9311 str r3, [sp, #68] ; 0x44
- 800375c: 9414 str r4, [sp, #80] ; 0x50
- 800375e: e9cd 6412 strd r6, r4, [sp, #72] ; 0x48
- 8003762: f002 ff39 bl 80065d8 <HAL_GPIO_Init>
- 8003766: f44f 7300 mov.w r3, #512 ; 0x200
- 800376a: a911 add r1, sp, #68 ; 0x44
- 800376c: 4887 ldr r0, [pc, #540] ; (800398c <main+0x318>)
- 800376e: 9311 str r3, [sp, #68] ; 0x44
- 8003770: e9cd 4412 strd r4, r4, [sp, #72] ; 0x48
- 8003774: f002 ff30 bl 80065d8 <HAL_GPIO_Init>
- 8003778: f44f 7380 mov.w r3, #256 ; 0x100
- 800377c: a911 add r1, sp, #68 ; 0x44
- 800377e: 4880 ldr r0, [pc, #512] ; (8003980 <main+0x30c>)
- 8003780: 9311 str r3, [sp, #68] ; 0x44
- 8003782: 9414 str r4, [sp, #80] ; 0x50
- 8003784: e9cd 6412 strd r6, r4, [sp, #72] ; 0x48
- 8003788: f002 ff26 bl 80065d8 <HAL_GPIO_Init>
- 800378c: 6b2b ldr r3, [r5, #48] ; 0x30
- 800378e: 4622 mov r2, r4
- 8003790: 4621 mov r1, r4
- 8003792: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
- 8003796: 200c movs r0, #12
- 8003798: 632b str r3, [r5, #48] ; 0x30
- 800379a: 6b2b ldr r3, [r5, #48] ; 0x30
- 800379c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 80037a0: 9302 str r3, [sp, #8]
- 80037a2: 9b02 ldr r3, [sp, #8]
- 80037a4: 6b2b ldr r3, [r5, #48] ; 0x30
- 80037a6: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
- 80037aa: 632b str r3, [r5, #48] ; 0x30
- 80037ac: 6b2b ldr r3, [r5, #48] ; 0x30
- 80037ae: 4d78 ldr r5, [pc, #480] ; (8003990 <main+0x31c>)
- 80037b0: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 80037b4: 9303 str r3, [sp, #12]
- 80037b6: 9b03 ldr r3, [sp, #12]
- 80037b8: f002 fce6 bl 8006188 <HAL_NVIC_SetPriority>
- 80037bc: 200c movs r0, #12
- 80037be: f002 fd19 bl 80061f4 <HAL_NVIC_EnableIRQ>
- 80037c2: 4622 mov r2, r4
- 80037c4: 4621 mov r1, r4
- 80037c6: 200e movs r0, #14
- 80037c8: f002 fcde bl 8006188 <HAL_NVIC_SetPriority>
- 80037cc: 200e movs r0, #14
- 80037ce: f002 fd11 bl 80061f4 <HAL_NVIC_EnableIRQ>
- 80037d2: 4622 mov r2, r4
- 80037d4: 4621 mov r1, r4
- 80037d6: 2039 movs r0, #57 ; 0x39
- 80037d8: f002 fcd6 bl 8006188 <HAL_NVIC_SetPriority>
- 80037dc: 2039 movs r0, #57 ; 0x39
- 80037de: f002 fd09 bl 80061f4 <HAL_NVIC_EnableIRQ>
- 80037e2: 4622 mov r2, r4
- 80037e4: 4621 mov r1, r4
- 80037e6: 2045 movs r0, #69 ; 0x45
- 80037e8: f002 fcce bl 8006188 <HAL_NVIC_SetPriority>
- 80037ec: 2045 movs r0, #69 ; 0x45
- 80037ee: f002 fd01 bl 80061f4 <HAL_NVIC_EnableIRQ>
- 80037f2: 2220 movs r2, #32
- 80037f4: 4621 mov r1, r4
- 80037f6: a812 add r0, sp, #72 ; 0x48
- 80037f8: f006 fadc bl 8009db4 <memset>
- 80037fc: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
- 8003800: a911 add r1, sp, #68 ; 0x44
- 8003802: 4658 mov r0, fp
- 8003804: f8cb 3000 str.w r3, [fp]
- 8003808: 9711 str r7, [sp, #68] ; 0x44
- 800380a: 940d str r4, [sp, #52] ; 0x34
- 800380c: 9613 str r6, [sp, #76] ; 0x4c
- 800380e: 9617 str r6, [sp, #92] ; 0x5c
- 8003810: f8cb 4010 str.w r4, [fp, #16]
- 8003814: f8cb 4018 str.w r4, [fp, #24]
- 8003818: f8cb 900c str.w r9, [fp, #12]
- 800381c: e9cd 440e strd r4, r4, [sp, #56] ; 0x38
- 8003820: e9cb 4401 strd r4, r4, [fp, #4]
- 8003824: f003 feb4 bl 8007590 <HAL_TIM_Encoder_Init>
- 8003828: a90d add r1, sp, #52 ; 0x34
- 800382a: 4658 mov r0, fp
- 800382c: 940d str r4, [sp, #52] ; 0x34
- 800382e: 940f str r4, [sp, #60] ; 0x3c
- 8003830: f004 fa88 bl 8007d44 <HAL_TIMEx_MasterConfigSynchronization>
- 8003834: f649 423f movw r2, #39999 ; 0x9c3f
- 8003838: 2309 movs r3, #9
- 800383a: 4956 ldr r1, [pc, #344] ; (8003994 <main+0x320>)
- 800383c: 4628 mov r0, r5
- 800383e: 606a str r2, [r5, #4]
- 8003840: 60eb str r3, [r5, #12]
- 8003842: 6029 str r1, [r5, #0]
- 8003844: 60ac str r4, [r5, #8]
- 8003846: 612c str r4, [r5, #16]
- 8003848: 61ac str r4, [r5, #24]
- 800384a: 940f str r4, [sp, #60] ; 0x3c
- 800384c: e9cd 4411 strd r4, r4, [sp, #68] ; 0x44
- 8003850: e9cd 4413 strd r4, r4, [sp, #76] ; 0x4c
- 8003854: e9cd 440d strd r4, r4, [sp, #52] ; 0x34
- 8003858: f003 fd90 bl 800737c <HAL_TIM_Base_Init>
- 800385c: a911 add r1, sp, #68 ; 0x44
- 800385e: 4628 mov r0, r5
- 8003860: f8cd a044 str.w sl, [sp, #68] ; 0x44
- 8003864: f004 f906 bl 8007a74 <HAL_TIM_ConfigClockSource>
- 8003868: a90d add r1, sp, #52 ; 0x34
- 800386a: 4628 mov r0, r5
- 800386c: 4d4a ldr r5, [pc, #296] ; (8003998 <main+0x324>)
- 800386e: 940d str r4, [sp, #52] ; 0x34
- 8003870: 940f str r4, [sp, #60] ; 0x3c
- 8003872: f004 fa67 bl 8007d44 <HAL_TIMEx_MasterConfigSynchronization>
- 8003876: 4b49 ldr r3, [pc, #292] ; (800399c <main+0x328>)
- 8003878: 4628 mov r0, r5
- 800387a: 61ac str r4, [r5, #24]
- 800387c: 602b str r3, [r5, #0]
- 800387e: 940a str r4, [sp, #40] ; 0x28
- 8003880: 9417 str r4, [sp, #92] ; 0x5c
- 8003882: e9c5 4401 strd r4, r4, [r5, #4]
- 8003886: e9c5 4403 strd r4, r4, [r5, #12]
- 800388a: e9cd 440d strd r4, r4, [sp, #52] ; 0x34
- 800388e: e9cd 440f strd r4, r4, [sp, #60] ; 0x3c
- 8003892: e9cd 4411 strd r4, r4, [sp, #68] ; 0x44
- 8003896: e9cd 4413 strd r4, r4, [sp, #76] ; 0x4c
- 800389a: e9cd 4415 strd r4, r4, [sp, #84] ; 0x54
- 800389e: e9cd 440b strd r4, r4, [sp, #44] ; 0x2c
- 80038a2: f003 fd6b bl 800737c <HAL_TIM_Base_Init>
- 80038a6: a90d add r1, sp, #52 ; 0x34
- 80038a8: 4628 mov r0, r5
- 80038aa: f8cd a034 str.w sl, [sp, #52] ; 0x34
- 80038ae: f004 f8e1 bl 8007a74 <HAL_TIM_ConfigClockSource>
- 80038b2: 4628 mov r0, r5
- 80038b4: f003 fde8 bl 8007488 <HAL_TIM_PWM_Init>
- 80038b8: a90a add r1, sp, #40 ; 0x28
- 80038ba: 4628 mov r0, r5
- 80038bc: 940a str r4, [sp, #40] ; 0x28
- 80038be: 940c str r4, [sp, #48] ; 0x30
- 80038c0: f004 fa40 bl 8007d44 <HAL_TIMEx_MasterConfigSynchronization>
- 80038c4: 2360 movs r3, #96 ; 0x60
- 80038c6: 4642 mov r2, r8
- 80038c8: a911 add r1, sp, #68 ; 0x44
- 80038ca: 4628 mov r0, r5
- 80038cc: 9311 str r3, [sp, #68] ; 0x44
- 80038ce: f44f 38e1 mov.w r8, #115200 ; 0x1c200
- 80038d2: 9412 str r4, [sp, #72] ; 0x48
- 80038d4: 9413 str r4, [sp, #76] ; 0x4c
- 80038d6: 9415 str r4, [sp, #84] ; 0x54
- 80038d8: f003 ff3e bl 8007758 <HAL_TIM_PWM_ConfigChannel>
- 80038dc: a911 add r1, sp, #68 ; 0x44
- 80038de: 220c movs r2, #12
- 80038e0: 4628 mov r0, r5
- 80038e2: f8df a0d8 ldr.w sl, [pc, #216] ; 80039bc <main+0x348>
- 80038e6: f003 ff37 bl 8007758 <HAL_TIM_PWM_ConfigChannel>
- 80038ea: 4628 mov r0, r5
- 80038ec: f002 fa24 bl 8005d38 <HAL_TIM_MspPostInit>
- 80038f0: 2220 movs r2, #32
- 80038f2: 4621 mov r1, r4
- 80038f4: a812 add r0, sp, #72 ; 0x48
- 80038f6: f006 fa5d bl 8009db4 <memset>
- 80038fa: 4b29 ldr r3, [pc, #164] ; (80039a0 <main+0x32c>)
- 80038fc: a911 add r1, sp, #68 ; 0x44
- 80038fe: 4650 mov r0, sl
- 8003900: f8ca 3000 str.w r3, [sl]
- 8003904: 9711 str r7, [sp, #68] ; 0x44
- 8003906: 270c movs r7, #12
- 8003908: 940f str r4, [sp, #60] ; 0x3c
- 800390a: 9613 str r6, [sp, #76] ; 0x4c
- 800390c: 9617 str r6, [sp, #92] ; 0x5c
- 800390e: f8ca 900c str.w r9, [sl, #12]
- 8003912: f8ca 4010 str.w r4, [sl, #16]
- 8003916: f8ca 4018 str.w r4, [sl, #24]
- 800391a: 4d22 ldr r5, [pc, #136] ; (80039a4 <main+0x330>)
- 800391c: e9cd 440d strd r4, r4, [sp, #52] ; 0x34
- 8003920: e9ca 4401 strd r4, r4, [sl, #4]
- 8003924: f003 fe34 bl 8007590 <HAL_TIM_Encoder_Init>
- 8003928: a90d add r1, sp, #52 ; 0x34
- 800392a: 4650 mov r0, sl
- 800392c: 940d str r4, [sp, #52] ; 0x34
- 800392e: 940f str r4, [sp, #60] ; 0x3c
- 8003930: f004 fa08 bl 8007d44 <HAL_TIMEx_MasterConfigSynchronization>
- 8003934: 4b1c ldr r3, [pc, #112] ; (80039a8 <main+0x334>)
- 8003936: 4a1d ldr r2, [pc, #116] ; (80039ac <main+0x338>)
- 8003938: 4618 mov r0, r3
- 800393a: 611c str r4, [r3, #16]
- 800393c: 615f str r7, [r3, #20]
- 800393e: e9c3 2800 strd r2, r8, [r3]
- 8003942: e9c3 4402 strd r4, r4, [r3, #8]
- 8003946: e9c3 4406 strd r4, r4, [r3, #24]
- 800394a: e9c3 4408 strd r4, r4, [r3, #32]
- 800394e: f004 fc5b bl 8008208 <HAL_UART_Init>
- 8003952: 4b17 ldr r3, [pc, #92] ; (80039b0 <main+0x33c>)
- 8003954: 4a17 ldr r2, [pc, #92] ; (80039b4 <main+0x340>)
- 8003956: 4618 mov r0, r3
- 8003958: 625c str r4, [r3, #36] ; 0x24
- 800395a: 601a str r2, [r3, #0]
- 800395c: e9c3 8401 strd r8, r4, [r3, #4]
- 8003960: e9c3 4403 strd r4, r4, [r3, #12]
- 8003964: e9c3 7405 strd r7, r4, [r3, #20]
- 8003968: e9c3 4407 strd r4, r4, [r3, #28]
- 800396c: f004 fc4c bl 8008208 <HAL_UART_Init>
- 8003970: 2280 movs r2, #128 ; 0x80
- 8003972: f105 0108 add.w r1, r5, #8
- 8003976: e023 b.n 80039c0 <main+0x34c>
- 8003978: 40023800 .word 0x40023800
- 800397c: 40021400 .word 0x40021400
- 8003980: 40020400 .word 0x40020400
- 8003984: 40020800 .word 0x40020800
- 8003988: 40020000 .word 0x40020000
- 800398c: 40021000 .word 0x40021000
- 8003990: 20000274 .word 0x20000274
- 8003994: 40000400 .word 0x40000400
- 8003998: 200002b4 .word 0x200002b4
- 800399c: 40000800 .word 0x40000800
- 80039a0: 40000c00 .word 0x40000c00
- 80039a4: 20000450 .word 0x20000450
- 80039a8: 20000334 .word 0x20000334
- 80039ac: 40004800 .word 0x40004800
- 80039b0: 200003b4 .word 0x200003b4
- 80039b4: 40011400 .word 0x40011400
- 80039b8: 20000234 .word 0x20000234
- 80039bc: 200002f4 .word 0x200002f4
- 80039c0: 6868 ldr r0, [r5, #4]
- 80039c2: f004 fa47 bl 8007e54 <HAL_UART_Receive_DMA>
- 80039c6: 4623 mov r3, r4
- 80039c8: f505 62b4 add.w r2, r5, #1440 ; 0x5a0
- 80039cc: f8c5 466c str.w r4, [r5, #1644] ; 0x66c
- 80039d0: f8c5 4670 str.w r4, [r5, #1648] ; 0x670
- 80039d4: f8c5 4678 str.w r4, [r5, #1656] ; 0x678
- 80039d8: f8c5 4674 str.w r4, [r5, #1652] ; 0x674
- 80039dc: f852 1f04 ldr.w r1, [r2, #4]!
- 80039e0: b119 cbz r1, 80039ea <main+0x376>
- 80039e2: 3301 adds r3, #1
- 80039e4: 2b19 cmp r3, #25
- 80039e6: d1f9 bne.n 80039dc <main+0x368>
- 80039e8: e007 b.n 80039fa <main+0x386>
- 80039ea: eb05 0183 add.w r1, r5, r3, lsl #2
- 80039ee: 4a35 ldr r2, [pc, #212] ; (8003ac4 <main+0x450>)
- 80039f0: 337d adds r3, #125 ; 0x7d
- 80039f2: f8c1 25a4 str.w r2, [r1, #1444] ; 0x5a4
- 80039f6: e9c2 3502 strd r3, r5, [r2, #8]
- 80039fa: 4b33 ldr r3, [pc, #204] ; (8003ac8 <main+0x454>)
- 80039fc: 4a33 ldr r2, [pc, #204] ; (8003acc <main+0x458>)
- 80039fe: 4c34 ldr r4, [pc, #208] ; (8003ad0 <main+0x45c>)
- 8003a00: 4834 ldr r0, [pc, #208] ; (8003ad4 <main+0x460>)
- 8003a02: 605a str r2, [r3, #4]
- 8003a04: f7fc fdb0 bl 8000568 <_ZN7Encoder5SetupEv>
- 8003a08: 4833 ldr r0, [pc, #204] ; (8003ad8 <main+0x464>)
- 8003a0a: f104 0bd8 add.w fp, r4, #216 ; 0xd8
- 8003a0e: 4e33 ldr r6, [pc, #204] ; (8003adc <main+0x468>)
- 8003a10: f504 78c8 add.w r8, r4, #400 ; 0x190
- 8003a14: f7fc fda8 bl 8000568 <_ZN7Encoder5SetupEv>
- 8003a18: 4b2e ldr r3, [pc, #184] ; (8003ad4 <main+0x460>)
- 8003a1a: 4830 ldr r0, [pc, #192] ; (8003adc <main+0x468>)
- 8003a1c: 681b ldr r3, [r3, #0]
- 8003a1e: 681b ldr r3, [r3, #0]
- 8003a20: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003a22: f002 f84f bl 8005ac4 <_ZN12OdometryCalc21OdometryUpdateMessageEv>
- 8003a26: 6e73 ldr r3, [r6, #100] ; 0x64
- 8003a28: 2290 movs r2, #144 ; 0x90
- 8003a2a: 6eb5 ldr r5, [r6, #104] ; 0x68
- 8003a2c: 62a3 str r3, [r4, #40] ; 0x28
- 8003a2e: 6ef3 ldr r3, [r6, #108] ; 0x6c
- 8003a30: 62e5 str r5, [r4, #44] ; 0x2c
- 8003a32: 6323 str r3, [r4, #48] ; 0x30
- 8003a34: 6fb3 ldr r3, [r6, #120] ; 0x78
- 8003a36: 6f75 ldr r5, [r6, #116] ; 0x74
- 8003a38: 63e3 str r3, [r4, #60] ; 0x3c
- 8003a3a: 4929 ldr r1, [pc, #164] ; (8003ae0 <main+0x46c>)
- 8003a3c: f8d6 3080 ldr.w r3, [r6, #128] ; 0x80
- 8003a40: 6c77 ldr r7, [r6, #68] ; 0x44
- 8003a42: 63a5 str r5, [r4, #56] ; 0x38
- 8003a44: 6463 str r3, [r4, #68] ; 0x44
- 8003a46: 6ff5 ldr r5, [r6, #124] ; 0x7c
- 8003a48: 4b26 ldr r3, [pc, #152] ; (8003ae4 <main+0x470>)
- 8003a4a: 6425 str r5, [r4, #64] ; 0x40
- 8003a4c: 60a7 str r7, [r4, #8]
- 8003a4e: c903 ldmia r1, {r0, r1}
- 8003a50: e9d6 a914 ldrd sl, r9, [r6, #80] ; 0x50
- 8003a54: e9c4 a905 strd sl, r9, [r4, #20]
- 8003a58: e883 0003 stmia.w r3, {r0, r1}
- 8003a5c: 4922 ldr r1, [pc, #136] ; (8003ae8 <main+0x474>)
- 8003a5e: f103 003c add.w r0, r3, #60 ; 0x3c
- 8003a62: f006 f983 bl 8009d6c <memcpy>
- 8003a66: f8d6 1120 ldr.w r1, [r6, #288] ; 0x120
- 8003a6a: f8d6 0124 ldr.w r0, [r6, #292] ; 0x124
- 8003a6e: 2290 movs r2, #144 ; 0x90
- 8003a70: f8d6 3128 ldr.w r3, [r6, #296] ; 0x128
- 8003a74: f8c4 10e4 str.w r1, [r4, #228] ; 0xe4
- 8003a78: f8c4 00e8 str.w r0, [r4, #232] ; 0xe8
- 8003a7c: f8d6 1130 ldr.w r1, [r6, #304] ; 0x130
- 8003a80: f8d6 0134 ldr.w r0, [r6, #308] ; 0x134
- 8003a84: f8c4 30ec str.w r3, [r4, #236] ; 0xec
- 8003a88: f8d6 3138 ldr.w r3, [r6, #312] ; 0x138
- 8003a8c: f8c4 10f4 str.w r1, [r4, #244] ; 0xf4
- 8003a90: f8c4 00f8 str.w r0, [r4, #248] ; 0xf8
- 8003a94: 4915 ldr r1, [pc, #84] ; (8003aec <main+0x478>)
- 8003a96: f8c4 30fc str.w r3, [r4, #252] ; 0xfc
- 8003a9a: 4815 ldr r0, [pc, #84] ; (8003af0 <main+0x47c>)
- 8003a9c: f006 f966 bl 8009d6c <memcpy>
- 8003aa0: 4b14 ldr r3, [pc, #80] ; (8003af4 <main+0x480>)
- 8003aa2: 4915 ldr r1, [pc, #84] ; (8003af8 <main+0x484>)
- 8003aa4: e9d3 2502 ldrd r2, r5, [r3, #8]
- 8003aa8: 682b ldr r3, [r5, #0]
- 8003aaa: 9201 str r2, [sp, #4]
- 8003aac: 681b ldr r3, [r3, #0]
- 8003aae: 428b cmp r3, r1
- 8003ab0: f040 83da bne.w 8004268 <main+0xbf4>
- 8003ab4: 2a63 cmp r2, #99 ; 0x63
- 8003ab6: dd21 ble.n 8003afc <main+0x488>
- 8003ab8: f895 3680 ldrb.w r3, [r5, #1664] ; 0x680
- 8003abc: 2b00 cmp r3, #0
- 8003abe: d0ab beq.n 8003a18 <main+0x3a4>
- 8003ac0: e01c b.n 8003afc <main+0x488>
- 8003ac2: bf00 nop
- 8003ac4: 200000a0 .word 0x200000a0
- 8003ac8: 20000e9c .word 0x20000e9c
- 8003acc: 20000000 .word 0x20000000
- 8003ad0: 20000cf0 .word 0x20000cf0
- 8003ad4: 20000434 .word 0x20000434
- 8003ad8: 20000e80 .word 0x20000e80
- 8003adc: 20000b0c .word 0x20000b0c
- 8003ae0: 20000b54 .word 0x20000b54
- 8003ae4: 20000cfc .word 0x20000cfc
- 8003ae8: 20000b90 .word 0x20000b90
- 8003aec: 20000c48 .word 0x20000c48
- 8003af0: 20000df0 .word 0x20000df0
- 8003af4: 20000cdc .word 0x20000cdc
- 8003af8: 080032d9 .word 0x080032d9
- 8003afc: 68e0 ldr r0, [r4, #12]
- 8003afe: 0a39 lsrs r1, r7, #8
- 8003b00: 6923 ldr r3, [r4, #16]
- 8003b02: 0c3a lsrs r2, r7, #16
- 8003b04: ea4f 2c10 mov.w ip, r0, lsr #8
- 8003b08: f885 03af strb.w r0, [r5, #943] ; 0x3af
- 8003b0c: f885 33b3 strb.w r3, [r5, #947] ; 0x3b3
- 8003b10: f885 c3b0 strb.w ip, [r5, #944] ; 0x3b0
- 8003b14: ea4f 4c10 mov.w ip, r0, lsr #16
- 8003b18: 0e00 lsrs r0, r0, #24
- 8003b1a: f885 73ab strb.w r7, [r5, #939] ; 0x3ab
- 8003b1e: f885 c3b1 strb.w ip, [r5, #945] ; 0x3b1
- 8003b22: ea4f 2c13 mov.w ip, r3, lsr #8
- 8003b26: f885 03b2 strb.w r0, [r5, #946] ; 0x3b2
- 8003b2a: 0c18 lsrs r0, r3, #16
- 8003b2c: 0e1b lsrs r3, r3, #24
- 8003b2e: f885 c3b4 strb.w ip, [r5, #948] ; 0x3b4
- 8003b32: 0e3f lsrs r7, r7, #24
- 8003b34: f885 03b5 strb.w r0, [r5, #949] ; 0x3b5
- 8003b38: f885 33b6 strb.w r3, [r5, #950] ; 0x3b6
- 8003b3c: f205 33ab addw r3, r5, #939 ; 0x3ab
- 8003b40: 4650 mov r0, sl
- 8003b42: f885 13ac strb.w r1, [r5, #940] ; 0x3ac
- 8003b46: f885 23ad strb.w r2, [r5, #941] ; 0x3ad
- 8003b4a: f885 73ae strb.w r7, [r5, #942] ; 0x3ae
- 8003b4e: 9300 str r3, [sp, #0]
- 8003b50: f7fc fb72 bl 8000238 <strlen>
- 8003b54: 4607 mov r7, r0
- 8003b56: 4651 mov r1, sl
- 8003b58: f205 30bb addw r0, r5, #955 ; 0x3bb
- 8003b5c: 0a3b lsrs r3, r7, #8
- 8003b5e: f885 73b7 strb.w r7, [r5, #951] ; 0x3b7
- 8003b62: 0c3a lsrs r2, r7, #16
- 8003b64: f107 0a10 add.w sl, r7, #16
- 8003b68: f885 33b8 strb.w r3, [r5, #952] ; 0x3b8
- 8003b6c: 0e3b lsrs r3, r7, #24
- 8003b6e: f885 23b9 strb.w r2, [r5, #953] ; 0x3b9
- 8003b72: 463a mov r2, r7
- 8003b74: f885 33ba strb.w r3, [r5, #954] ; 0x3ba
- 8003b78: f006 f8f8 bl 8009d6c <memcpy>
- 8003b7c: 4648 mov r0, r9
- 8003b7e: f7fc fb5b bl 8000238 <strlen>
- 8003b82: 4681 mov r9, r0
- 8003b84: 9800 ldr r0, [sp, #0]
- 8003b86: ea4f 2119 mov.w r1, r9, lsr #8
- 8003b8a: 19c3 adds r3, r0, r7
- 8003b8c: f800 900a strb.w r9, [r0, sl]
- 8003b90: 3714 adds r7, #20
- 8003b92: ea4f 4219 mov.w r2, r9, lsr #16
- 8003b96: 7459 strb r1, [r3, #17]
- 8003b98: ea4f 6119 mov.w r1, r9, lsr #24
- 8003b9c: 749a strb r2, [r3, #18]
- 8003b9e: 4438 add r0, r7
- 8003ba0: 74d9 strb r1, [r3, #19]
- 8003ba2: 464a mov r2, r9
- 8003ba4: 69a1 ldr r1, [r4, #24]
- 8003ba6: eb09 0a07 add.w sl, r9, r7
- 8003baa: f006 f8df bl 8009d6c <memcpy>
- 8003bae: edd4 7a0a vldr s15, [r4, #40] ; 0x28
- 8003bb2: 9800 ldr r0, [sp, #0]
- 8003bb4: ee17 2a90 vmov r2, s15
- 8003bb8: eb00 030a add.w r3, r0, sl
- 8003bbc: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003bc0: 2900 cmp r1, #0
- 8003bc2: f000 834f beq.w 8004264 <main+0xbf0>
- 8003bc6: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003bca: 0108 lsls r0, r1, #4
- 8003bcc: 0909 lsrs r1, r1, #4
- 8003bce: b240 sxtb r0, r0
- 8003bd0: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003bd4: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003bd8: 2700 movs r7, #0
- 8003bda: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003bde: ea40 090c orr.w r9, r0, ip
- 8003be2: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003be6: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003bea: ea4f 22e2 mov.w r2, r2, asr #11
- 8003bee: 9800 ldr r0, [sp, #0]
- 8003bf0: bf48 it mi
- 8003bf2: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003bf6: f800 700a strb.w r7, [r0, sl]
- 8003bfa: 715a strb r2, [r3, #5]
- 8003bfc: 71d9 strb r1, [r3, #7]
- 8003bfe: f883 9006 strb.w r9, [r3, #6]
- 8003c02: 705f strb r7, [r3, #1]
- 8003c04: 709f strb r7, [r3, #2]
- 8003c06: f883 e003 strb.w lr, [r3, #3]
- 8003c0a: f883 c004 strb.w ip, [r3, #4]
- 8003c0e: edd4 7a0b vldr s15, [r4, #44] ; 0x2c
- 8003c12: ee17 2a90 vmov r2, s15
- 8003c16: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003c1a: 2900 cmp r1, #0
- 8003c1c: f000 8320 beq.w 8004260 <main+0xbec>
- 8003c20: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003c24: 0108 lsls r0, r1, #4
- 8003c26: 0909 lsrs r1, r1, #4
- 8003c28: b240 sxtb r0, r0
- 8003c2a: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003c2e: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003c32: 2700 movs r7, #0
- 8003c34: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003c38: ea40 000c orr.w r0, r0, ip
- 8003c3c: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003c40: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003c44: ea4f 22e2 mov.w r2, r2, asr #11
- 8003c48: 721f strb r7, [r3, #8]
- 8003c4a: 735a strb r2, [r3, #13]
- 8003c4c: bf48 it mi
- 8003c4e: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003c52: 7398 strb r0, [r3, #14]
- 8003c54: 725f strb r7, [r3, #9]
- 8003c56: 73d9 strb r1, [r3, #15]
- 8003c58: 729f strb r7, [r3, #10]
- 8003c5a: f883 e00b strb.w lr, [r3, #11]
- 8003c5e: f883 c00c strb.w ip, [r3, #12]
- 8003c62: edd4 7a0c vldr s15, [r4, #48] ; 0x30
- 8003c66: ee17 2a90 vmov r2, s15
- 8003c6a: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003c6e: 2900 cmp r1, #0
- 8003c70: f000 82f4 beq.w 800425c <main+0xbe8>
- 8003c74: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003c78: 0108 lsls r0, r1, #4
- 8003c7a: 0909 lsrs r1, r1, #4
- 8003c7c: b240 sxtb r0, r0
- 8003c7e: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003c82: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003c86: 2700 movs r7, #0
- 8003c88: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003c8c: ea40 000c orr.w r0, r0, ip
- 8003c90: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003c94: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003c98: ea4f 22e2 mov.w r2, r2, asr #11
- 8003c9c: 741f strb r7, [r3, #16]
- 8003c9e: 755a strb r2, [r3, #21]
- 8003ca0: bf48 it mi
- 8003ca2: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003ca6: 7598 strb r0, [r3, #22]
- 8003ca8: 745f strb r7, [r3, #17]
- 8003caa: 75d9 strb r1, [r3, #23]
- 8003cac: 749f strb r7, [r3, #18]
- 8003cae: f883 e013 strb.w lr, [r3, #19]
- 8003cb2: f883 c014 strb.w ip, [r3, #20]
- 8003cb6: edd4 7a0e vldr s15, [r4, #56] ; 0x38
- 8003cba: ee17 2a90 vmov r2, s15
- 8003cbe: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003cc2: 2900 cmp r1, #0
- 8003cc4: f000 82c8 beq.w 8004258 <main+0xbe4>
- 8003cc8: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003ccc: 0108 lsls r0, r1, #4
- 8003cce: 0909 lsrs r1, r1, #4
- 8003cd0: b240 sxtb r0, r0
- 8003cd2: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003cd6: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003cda: 2700 movs r7, #0
- 8003cdc: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003ce0: ea40 000c orr.w r0, r0, ip
- 8003ce4: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003ce8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003cec: ea4f 22e2 mov.w r2, r2, asr #11
- 8003cf0: 761f strb r7, [r3, #24]
- 8003cf2: 775a strb r2, [r3, #29]
- 8003cf4: bf48 it mi
- 8003cf6: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003cfa: 7798 strb r0, [r3, #30]
- 8003cfc: 765f strb r7, [r3, #25]
- 8003cfe: 77d9 strb r1, [r3, #31]
- 8003d00: 769f strb r7, [r3, #26]
- 8003d02: f883 e01b strb.w lr, [r3, #27]
- 8003d06: f883 c01c strb.w ip, [r3, #28]
- 8003d0a: edd4 7a0f vldr s15, [r4, #60] ; 0x3c
- 8003d0e: ee17 2a90 vmov r2, s15
- 8003d12: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003d16: 2900 cmp r1, #0
- 8003d18: f000 829c beq.w 8004254 <main+0xbe0>
- 8003d1c: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003d20: 0108 lsls r0, r1, #4
- 8003d22: 0909 lsrs r1, r1, #4
- 8003d24: b240 sxtb r0, r0
- 8003d26: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003d2a: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003d2e: 2700 movs r7, #0
- 8003d30: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003d34: ea40 000c orr.w r0, r0, ip
- 8003d38: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003d3c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003d40: ea4f 22e2 mov.w r2, r2, asr #11
- 8003d44: f883 7020 strb.w r7, [r3, #32]
- 8003d48: f883 2025 strb.w r2, [r3, #37] ; 0x25
- 8003d4c: bf48 it mi
- 8003d4e: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003d52: f883 0026 strb.w r0, [r3, #38] ; 0x26
- 8003d56: f883 7021 strb.w r7, [r3, #33] ; 0x21
- 8003d5a: f883 1027 strb.w r1, [r3, #39] ; 0x27
- 8003d5e: f883 7022 strb.w r7, [r3, #34] ; 0x22
- 8003d62: f883 e023 strb.w lr, [r3, #35] ; 0x23
- 8003d66: f883 c024 strb.w ip, [r3, #36] ; 0x24
- 8003d6a: edd4 7a10 vldr s15, [r4, #64] ; 0x40
- 8003d6e: ee17 2a90 vmov r2, s15
- 8003d72: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003d76: 2900 cmp r1, #0
- 8003d78: f000 826a beq.w 8004250 <main+0xbdc>
- 8003d7c: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003d80: 0108 lsls r0, r1, #4
- 8003d82: 0909 lsrs r1, r1, #4
- 8003d84: b240 sxtb r0, r0
- 8003d86: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003d8a: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003d8e: 2700 movs r7, #0
- 8003d90: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003d94: ea40 000c orr.w r0, r0, ip
- 8003d98: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003d9c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003da0: ea4f 22e2 mov.w r2, r2, asr #11
- 8003da4: f883 7028 strb.w r7, [r3, #40] ; 0x28
- 8003da8: f883 202d strb.w r2, [r3, #45] ; 0x2d
- 8003dac: bf48 it mi
- 8003dae: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003db2: f883 002e strb.w r0, [r3, #46] ; 0x2e
- 8003db6: f883 7029 strb.w r7, [r3, #41] ; 0x29
- 8003dba: f883 102f strb.w r1, [r3, #47] ; 0x2f
- 8003dbe: f883 702a strb.w r7, [r3, #42] ; 0x2a
- 8003dc2: f883 e02b strb.w lr, [r3, #43] ; 0x2b
- 8003dc6: f883 c02c strb.w ip, [r3, #44] ; 0x2c
- 8003dca: edd4 7a11 vldr s15, [r4, #68] ; 0x44
- 8003dce: ee17 2a90 vmov r2, s15
- 8003dd2: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003dd6: 2900 cmp r1, #0
- 8003dd8: f000 8238 beq.w 800424c <main+0xbd8>
- 8003ddc: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003de0: 0108 lsls r0, r1, #4
- 8003de2: 0909 lsrs r1, r1, #4
- 8003de4: b240 sxtb r0, r0
- 8003de6: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003dea: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003dee: 2700 movs r7, #0
- 8003df0: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003df4: ea40 000c orr.w r0, r0, ip
- 8003df8: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003dfc: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003e00: f883 7030 strb.w r7, [r3, #48] ; 0x30
- 8003e04: ea4f 22e2 mov.w r2, r2, asr #11
- 8003e08: f883 7031 strb.w r7, [r3, #49] ; 0x31
- 8003e0c: f883 7032 strb.w r7, [r3, #50] ; 0x32
- 8003e10: f04f 0700 mov.w r7, #0
- 8003e14: f883 c034 strb.w ip, [r3, #52] ; 0x34
- 8003e18: bf48 it mi
- 8003e1a: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003e1e: f8df c594 ldr.w ip, [pc, #1428] ; 80043b4 <main+0xd40>
- 8003e22: f883 0036 strb.w r0, [r3, #54] ; 0x36
- 8003e26: f883 e033 strb.w lr, [r3, #51] ; 0x33
- 8003e2a: f883 2035 strb.w r2, [r3, #53] ; 0x35
- 8003e2e: f883 1037 strb.w r1, [r3, #55] ; 0x37
- 8003e32: ecfc 7a01 vldmia ip!, {s15}
- 8003e36: ee17 2a90 vmov r2, s15
- 8003e3a: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003e3e: 4608 mov r0, r1
- 8003e40: f501 7e60 add.w lr, r1, #896 ; 0x380
- 8003e44: b121 cbz r1, 8003e50 <main+0x7dc>
- 8003e46: ea4f 110e mov.w r1, lr, lsl #4
- 8003e4a: ea4f 101e mov.w r0, lr, lsr #4
- 8003e4e: b249 sxtb r1, r1
- 8003e50: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003e54: f3c2 4ec3 ubfx lr, r2, #19, #4
- 8003e58: ea4f 1942 mov.w r9, r2, lsl #5
- 8003e5c: f883 7038 strb.w r7, [r3, #56] ; 0x38
- 8003e60: ea41 010e orr.w r1, r1, lr
- 8003e64: ea4f 0ee2 mov.w lr, r2, asr #3
- 8003e68: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003e6c: ea4f 22e2 mov.w r2, r2, asr #11
- 8003e70: f883 7039 strb.w r7, [r3, #57] ; 0x39
- 8003e74: f103 0308 add.w r3, r3, #8
- 8003e78: f883 7032 strb.w r7, [r3, #50] ; 0x32
- 8003e7c: bf48 it mi
- 8003e7e: f060 007f ornmi r0, r0, #127 ; 0x7f
- 8003e82: 45dc cmp ip, fp
- 8003e84: f883 1036 strb.w r1, [r3, #54] ; 0x36
- 8003e88: f883 9033 strb.w r9, [r3, #51] ; 0x33
- 8003e8c: f883 e034 strb.w lr, [r3, #52] ; 0x34
- 8003e90: f883 2035 strb.w r2, [r3, #53] ; 0x35
- 8003e94: f883 0037 strb.w r0, [r3, #55] ; 0x37
- 8003e98: d1cb bne.n 8003e32 <main+0x7be>
- 8003e9a: edd4 7a39 vldr s15, [r4, #228] ; 0xe4
- 8003e9e: f50a 7cac add.w ip, sl, #344 ; 0x158
- 8003ea2: 9b00 ldr r3, [sp, #0]
- 8003ea4: ee17 2a90 vmov r2, s15
- 8003ea8: 4463 add r3, ip
- 8003eaa: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003eae: 2900 cmp r1, #0
- 8003eb0: f000 81ca beq.w 8004248 <main+0xbd4>
- 8003eb4: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003eb8: 010f lsls r7, r1, #4
- 8003eba: 0909 lsrs r1, r1, #4
- 8003ebc: fa4f fe87 sxtb.w lr, r7
- 8003ec0: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003ec4: f3c2 47c3 ubfx r7, r2, #19, #4
- 8003ec8: 2000 movs r0, #0
- 8003eca: ea4e 0907 orr.w r9, lr, r7
- 8003ece: 9f00 ldr r7, [sp, #0]
- 8003ed0: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003ed4: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003ed8: f807 000c strb.w r0, [r7, ip]
- 8003edc: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003ee0: ea4f 22e2 mov.w r2, r2, asr #11
- 8003ee4: f883 9006 strb.w r9, [r3, #6]
- 8003ee8: bf48 it mi
- 8003eea: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003eee: 7058 strb r0, [r3, #1]
- 8003ef0: 715a strb r2, [r3, #5]
- 8003ef2: 71d9 strb r1, [r3, #7]
- 8003ef4: 7098 strb r0, [r3, #2]
- 8003ef6: f883 e003 strb.w lr, [r3, #3]
- 8003efa: f883 c004 strb.w ip, [r3, #4]
- 8003efe: edd4 7a3a vldr s15, [r4, #232] ; 0xe8
- 8003f02: ee17 2a90 vmov r2, s15
- 8003f06: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003f0a: 2900 cmp r1, #0
- 8003f0c: f000 819a beq.w 8004244 <main+0xbd0>
- 8003f10: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003f14: 0108 lsls r0, r1, #4
- 8003f16: 0909 lsrs r1, r1, #4
- 8003f18: b240 sxtb r0, r0
- 8003f1a: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003f1e: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003f22: 2700 movs r7, #0
- 8003f24: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003f28: ea40 000c orr.w r0, r0, ip
- 8003f2c: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003f30: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003f34: ea4f 22e2 mov.w r2, r2, asr #11
- 8003f38: 721f strb r7, [r3, #8]
- 8003f3a: 735a strb r2, [r3, #13]
- 8003f3c: bf48 it mi
- 8003f3e: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003f42: 7398 strb r0, [r3, #14]
- 8003f44: 725f strb r7, [r3, #9]
- 8003f46: 73d9 strb r1, [r3, #15]
- 8003f48: 729f strb r7, [r3, #10]
- 8003f4a: f883 e00b strb.w lr, [r3, #11]
- 8003f4e: f883 c00c strb.w ip, [r3, #12]
- 8003f52: edd4 7a3b vldr s15, [r4, #236] ; 0xec
- 8003f56: ee17 2a90 vmov r2, s15
- 8003f5a: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003f5e: 2900 cmp r1, #0
- 8003f60: f000 816e beq.w 8004240 <main+0xbcc>
- 8003f64: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003f68: 0108 lsls r0, r1, #4
- 8003f6a: 0909 lsrs r1, r1, #4
- 8003f6c: b240 sxtb r0, r0
- 8003f6e: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003f72: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003f76: 2700 movs r7, #0
- 8003f78: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003f7c: ea40 000c orr.w r0, r0, ip
- 8003f80: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003f84: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003f88: ea4f 22e2 mov.w r2, r2, asr #11
- 8003f8c: 741f strb r7, [r3, #16]
- 8003f8e: 755a strb r2, [r3, #21]
- 8003f90: bf48 it mi
- 8003f92: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003f96: 7598 strb r0, [r3, #22]
- 8003f98: 745f strb r7, [r3, #17]
- 8003f9a: 75d9 strb r1, [r3, #23]
- 8003f9c: 749f strb r7, [r3, #18]
- 8003f9e: f883 e013 strb.w lr, [r3, #19]
- 8003fa2: f883 c014 strb.w ip, [r3, #20]
- 8003fa6: edd4 7a3d vldr s15, [r4, #244] ; 0xf4
- 8003faa: ee17 2a90 vmov r2, s15
- 8003fae: f3c2 51c7 ubfx r1, r2, #23, #8
- 8003fb2: 2900 cmp r1, #0
- 8003fb4: f000 8142 beq.w 800423c <main+0xbc8>
- 8003fb8: f501 7160 add.w r1, r1, #896 ; 0x380
- 8003fbc: 0108 lsls r0, r1, #4
- 8003fbe: 0909 lsrs r1, r1, #4
- 8003fc0: b240 sxtb r0, r0
- 8003fc2: eef5 7ac0 vcmpe.f32 s15, #0.0
- 8003fc6: f3c2 4cc3 ubfx ip, r2, #19, #4
- 8003fca: 2700 movs r7, #0
- 8003fcc: ea4f 1e42 mov.w lr, r2, lsl #5
- 8003fd0: ea40 000c orr.w r0, r0, ip
- 8003fd4: ea4f 0ce2 mov.w ip, r2, asr #3
- 8003fd8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8003fdc: ea4f 22e2 mov.w r2, r2, asr #11
- 8003fe0: 761f strb r7, [r3, #24]
- 8003fe2: 775a strb r2, [r3, #29]
- 8003fe4: bf48 it mi
- 8003fe6: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8003fea: 7798 strb r0, [r3, #30]
- 8003fec: 765f strb r7, [r3, #25]
- 8003fee: 77d9 strb r1, [r3, #31]
- 8003ff0: 769f strb r7, [r3, #26]
- 8003ff2: f883 e01b strb.w lr, [r3, #27]
- 8003ff6: f883 c01c strb.w ip, [r3, #28]
- 8003ffa: edd4 7a3e vldr s15, [r4, #248] ; 0xf8
- 8003ffe: ee17 2a90 vmov r2, s15
- 8004002: f3c2 51c7 ubfx r1, r2, #23, #8
- 8004006: 2900 cmp r1, #0
- 8004008: f000 8116 beq.w 8004238 <main+0xbc4>
- 800400c: f501 7160 add.w r1, r1, #896 ; 0x380
- 8004010: 0108 lsls r0, r1, #4
- 8004012: 0909 lsrs r1, r1, #4
- 8004014: b240 sxtb r0, r0
- 8004016: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800401a: f3c2 4cc3 ubfx ip, r2, #19, #4
- 800401e: 2700 movs r7, #0
- 8004020: ea4f 1e42 mov.w lr, r2, lsl #5
- 8004024: ea40 000c orr.w r0, r0, ip
- 8004028: ea4f 0ce2 mov.w ip, r2, asr #3
- 800402c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8004030: ea4f 22e2 mov.w r2, r2, asr #11
- 8004034: f883 7020 strb.w r7, [r3, #32]
- 8004038: f883 2025 strb.w r2, [r3, #37] ; 0x25
- 800403c: bf48 it mi
- 800403e: f061 017f ornmi r1, r1, #127 ; 0x7f
- 8004042: f883 0026 strb.w r0, [r3, #38] ; 0x26
- 8004046: f883 7021 strb.w r7, [r3, #33] ; 0x21
- 800404a: f883 1027 strb.w r1, [r3, #39] ; 0x27
- 800404e: f883 7022 strb.w r7, [r3, #34] ; 0x22
- 8004052: f883 e023 strb.w lr, [r3, #35] ; 0x23
- 8004056: f883 c024 strb.w ip, [r3, #36] ; 0x24
- 800405a: edd4 7a3f vldr s15, [r4, #252] ; 0xfc
- 800405e: ee17 2a90 vmov r2, s15
- 8004062: f3c2 51c7 ubfx r1, r2, #23, #8
- 8004066: 2900 cmp r1, #0
- 8004068: f000 80e4 beq.w 8004234 <main+0xbc0>
- 800406c: f501 7160 add.w r1, r1, #896 ; 0x380
- 8004070: 0108 lsls r0, r1, #4
- 8004072: 0909 lsrs r1, r1, #4
- 8004074: b240 sxtb r0, r0
- 8004076: eef5 7ac0 vcmpe.f32 s15, #0.0
- 800407a: f3c2 4cc3 ubfx ip, r2, #19, #4
- 800407e: 2700 movs r7, #0
- 8004080: ea4f 1e42 mov.w lr, r2, lsl #5
- 8004084: ea40 000c orr.w r0, r0, ip
- 8004088: ea4f 0ce2 mov.w ip, r2, asr #3
- 800408c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8004090: f883 7028 strb.w r7, [r3, #40] ; 0x28
- 8004094: ea4f 22e2 mov.w r2, r2, asr #11
- 8004098: f883 7029 strb.w r7, [r3, #41] ; 0x29
- 800409c: f883 702a strb.w r7, [r3, #42] ; 0x2a
- 80040a0: f04f 0700 mov.w r7, #0
- 80040a4: f883 c02c strb.w ip, [r3, #44] ; 0x2c
- 80040a8: bf48 it mi
- 80040aa: f061 017f ornmi r1, r1, #127 ; 0x7f
- 80040ae: f8df c308 ldr.w ip, [pc, #776] ; 80043b8 <main+0xd44>
- 80040b2: f883 002e strb.w r0, [r3, #46] ; 0x2e
- 80040b6: f883 e02b strb.w lr, [r3, #43] ; 0x2b
- 80040ba: f883 202d strb.w r2, [r3, #45] ; 0x2d
- 80040be: f883 102f strb.w r1, [r3, #47] ; 0x2f
- 80040c2: ecfc 7a01 vldmia ip!, {s15}
- 80040c6: ee17 2a90 vmov r2, s15
- 80040ca: f3c2 51c7 ubfx r1, r2, #23, #8
- 80040ce: 4608 mov r0, r1
- 80040d0: f501 7e60 add.w lr, r1, #896 ; 0x380
- 80040d4: b121 cbz r1, 80040e0 <main+0xa6c>
- 80040d6: ea4f 110e mov.w r1, lr, lsl #4
- 80040da: ea4f 101e mov.w r0, lr, lsr #4
- 80040de: b249 sxtb r1, r1
- 80040e0: eef5 7ac0 vcmpe.f32 s15, #0.0
- 80040e4: f3c2 4ec3 ubfx lr, r2, #19, #4
- 80040e8: ea4f 1942 mov.w r9, r2, lsl #5
- 80040ec: f883 7030 strb.w r7, [r3, #48] ; 0x30
- 80040f0: ea41 010e orr.w r1, r1, lr
- 80040f4: ea4f 0ee2 mov.w lr, r2, asr #3
- 80040f8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80040fc: ea4f 22e2 mov.w r2, r2, asr #11
- 8004100: f883 7031 strb.w r7, [r3, #49] ; 0x31
- 8004104: f103 0308 add.w r3, r3, #8
- 8004108: f883 702a strb.w r7, [r3, #42] ; 0x2a
- 800410c: bf48 it mi
- 800410e: f060 007f ornmi r0, r0, #127 ; 0x7f
- 8004112: 45e0 cmp r8, ip
- 8004114: f883 102e strb.w r1, [r3, #46] ; 0x2e
- 8004118: f883 902b strb.w r9, [r3, #43] ; 0x2b
- 800411c: f883 e02c strb.w lr, [r3, #44] ; 0x2c
- 8004120: f883 202d strb.w r2, [r3, #45] ; 0x2d
- 8004124: f883 002f strb.w r0, [r3, #47] ; 0x2f
- 8004128: d1cb bne.n 80040c2 <main+0xa4e>
- 800412a: 9901 ldr r1, [sp, #4]
- 800412c: f50a 732a add.w r3, sl, #680 ; 0x2a8
- 8004130: f46f 702a mvn.w r0, #680 ; 0x2a8
- 8004134: f64f 67ff movw r7, #65279 ; 0xfeff
- 8004138: f341 2207 sbfx r2, r1, #8, #8
- 800413c: f885 13a9 strb.w r1, [r5, #937] ; 0x3a9
- 8004140: b2d9 uxtb r1, r3
- 8004142: f3c3 2307 ubfx r3, r3, #8, #8
- 8004146: f885 23aa strb.w r2, [r5, #938] ; 0x3aa
- 800414a: 4582 cmp sl, r0
- 800414c: eb01 0203 add.w r2, r1, r3
- 8004150: f885 33a7 strb.w r3, [r5, #935] ; 0x3a7
- 8004154: f885 13a6 strb.w r1, [r5, #934] ; 0x3a6
- 8004158: ea6f 0302 mvn.w r3, r2
- 800415c: f8a5 73a4 strh.w r7, [r5, #932] ; 0x3a4
- 8004160: f885 33a8 strb.w r3, [r5, #936] ; 0x3a8
- 8004164: f2c0 8086 blt.w 8004274 <main+0xc00>
- 8004168: f205 6052 addw r0, r5, #1618 ; 0x652
- 800416c: f505 736a add.w r3, r5, #936 ; 0x3a8
- 8004170: 2200 movs r2, #0
- 8004172: 4450 add r0, sl
- 8004174: f813 1f01 ldrb.w r1, [r3, #1]!
- 8004178: 4283 cmp r3, r0
- 800417a: 440a add r2, r1
- 800417c: d1fa bne.n 8004174 <main+0xb00>
- 800417e: 43d3 mvns r3, r2
- 8004180: b2db uxtb r3, r3
- 8004182: eb05 020a add.w r2, r5, sl
- 8004186: f50a 7a2c add.w sl, sl, #688 ; 0x2b0
- 800418a: f5ba 7f00 cmp.w sl, #512 ; 0x200
- 800418e: f882 3653 strb.w r3, [r2, #1619] ; 0x653
- 8004192: dc75 bgt.n 8004280 <main+0xc0c>
- 8004194: f8d5 218c ldr.w r2, [r5, #396] ; 0x18c
- 8004198: f5ba 7f80 cmp.w sl, #256 ; 0x100
- 800419c: f505 7369 add.w r3, r5, #932 ; 0x3a4
- 80041a0: f105 0904 add.w r9, r5, #4
- 80041a4: f5c2 7780 rsb r7, r2, #256 ; 0x100
- 80041a8: bfa8 it ge
- 80041aa: f44f 7a80 movge.w sl, #256 ; 0x100
- 80041ae: 3288 adds r2, #136 ; 0x88
- 80041b0: 4619 mov r1, r3
- 80041b2: 4557 cmp r7, sl
- 80041b4: 9300 str r3, [sp, #0]
- 80041b6: eb09 0002 add.w r0, r9, r2
- 80041ba: bf28 it cs
- 80041bc: 4657 movcs r7, sl
- 80041be: 463a mov r2, r7
- 80041c0: f005 fdd4 bl 8009d6c <memcpy>
- 80041c4: f8d5 218c ldr.w r2, [r5, #396] ; 0x18c
- 80041c8: 45ba cmp sl, r7
- 80041ca: 4452 add r2, sl
- 80041cc: b2d2 uxtb r2, r2
- 80041ce: f8c5 218c str.w r2, [r5, #396] ; 0x18c
- 80041d2: d007 beq.n 80041e4 <main+0xb70>
- 80041d4: 9b00 ldr r3, [sp, #0]
- 80041d6: ebaa 0207 sub.w r2, sl, r7
- 80041da: f105 008c add.w r0, r5, #140 ; 0x8c
- 80041de: 19d9 adds r1, r3, r7
- 80041e0: f005 fdc4 bl 8009d6c <memcpy>
- 80041e4: 6868 ldr r0, [r5, #4]
- 80041e6: 6f43 ldr r3, [r0, #116] ; 0x74
- 80041e8: 2b20 cmp r3, #32
- 80041ea: f47f ac15 bne.w 8003a18 <main+0x3a4>
- 80041ee: 4b6a ldr r3, [pc, #424] ; (8004398 <main+0xd24>)
- 80041f0: 781b ldrb r3, [r3, #0]
- 80041f2: 2b00 cmp r3, #0
- 80041f4: f47f ac10 bne.w 8003a18 <main+0x3a4>
- 80041f8: f8d5 218c ldr.w r2, [r5, #396] ; 0x18c
- 80041fc: 2101 movs r1, #1
- 80041fe: f8d5 3190 ldr.w r3, [r5, #400] ; 0x190
- 8004202: 4f65 ldr r7, [pc, #404] ; (8004398 <main+0xd24>)
- 8004204: 429a cmp r2, r3
- 8004206: 7039 strb r1, [r7, #0]
- 8004208: d00f beq.n 800422a <main+0xbb6>
- 800420a: b29f uxth r7, r3
- 800420c: d934 bls.n 8004278 <main+0xc04>
- 800420e: 1bd2 subs r2, r2, r7
- 8004210: b297 uxth r7, r2
- 8004212: 3388 adds r3, #136 ; 0x88
- 8004214: 463a mov r2, r7
- 8004216: eb09 0103 add.w r1, r9, r3
- 800421a: f003 fdc9 bl 8007db0 <HAL_UART_Transmit_DMA>
- 800421e: f8d5 3190 ldr.w r3, [r5, #400] ; 0x190
- 8004222: 443b add r3, r7
- 8004224: b2db uxtb r3, r3
- 8004226: f8c5 3190 str.w r3, [r5, #400] ; 0x190
- 800422a: 2300 movs r3, #0
- 800422c: 4a5a ldr r2, [pc, #360] ; (8004398 <main+0xd24>)
- 800422e: 7013 strb r3, [r2, #0]
- 8004230: f7ff bbf2 b.w 8003a18 <main+0x3a4>
- 8004234: 4608 mov r0, r1
- 8004236: e71e b.n 8004076 <main+0xa02>
- 8004238: 4608 mov r0, r1
- 800423a: e6ec b.n 8004016 <main+0x9a2>
- 800423c: 4608 mov r0, r1
- 800423e: e6c0 b.n 8003fc2 <main+0x94e>
- 8004240: 4608 mov r0, r1
- 8004242: e694 b.n 8003f6e <main+0x8fa>
- 8004244: 4608 mov r0, r1
- 8004246: e668 b.n 8003f1a <main+0x8a6>
- 8004248: 468e mov lr, r1
- 800424a: e639 b.n 8003ec0 <main+0x84c>
- 800424c: 4608 mov r0, r1
- 800424e: e5ca b.n 8003de6 <main+0x772>
- 8004250: 4608 mov r0, r1
- 8004252: e598 b.n 8003d86 <main+0x712>
- 8004254: 4608 mov r0, r1
- 8004256: e566 b.n 8003d26 <main+0x6b2>
- 8004258: 4608 mov r0, r1
- 800425a: e53a b.n 8003cd2 <main+0x65e>
- 800425c: 4608 mov r0, r1
- 800425e: e50e b.n 8003c7e <main+0x60a>
- 8004260: 4608 mov r0, r1
- 8004262: e4e2 b.n 8003c2a <main+0x5b6>
- 8004264: 4608 mov r0, r1
- 8004266: e4b3 b.n 8003bd0 <main+0x55c>
- 8004268: 4611 mov r1, r2
- 800426a: 4628 mov r0, r5
- 800426c: 4a4b ldr r2, [pc, #300] ; (800439c <main+0xd28>)
- 800426e: 4798 blx r3
- 8004270: f7ff bbd2 b.w 8003a18 <main+0x3a4>
- 8004274: 23ff movs r3, #255 ; 0xff
- 8004276: e784 b.n 8004182 <main+0xb0e>
- 8004278: f5c7 7780 rsb r7, r7, #256 ; 0x100
- 800427c: b2bf uxth r7, r7
- 800427e: e7c8 b.n 8004212 <main+0xb9e>
- 8004280: 4a47 ldr r2, [pc, #284] ; (80043a0 <main+0xd2c>)
- 8004282: 2303 movs r3, #3
- 8004284: 9211 str r2, [sp, #68] ; 0x44
- 8004286: 4a47 ldr r2, [pc, #284] ; (80043a4 <main+0xd30>)
- 8004288: f88d 3048 strb.w r3, [sp, #72] ; 0x48
- 800428c: 9213 str r2, [sp, #76] ; 0x4c
- 800428e: 682b ldr r3, [r5, #0]
- 8004290: 4a45 ldr r2, [pc, #276] ; (80043a8 <main+0xd34>)
- 8004292: 681b ldr r3, [r3, #0]
- 8004294: 4293 cmp r3, r2
- 8004296: d178 bne.n 800438a <main+0xd16>
- 8004298: f643 0203 movw r2, #14339 ; 0x3803
- 800429c: 2300 movs r3, #0
- 800429e: 4f41 ldr r7, [pc, #260] ; (80043a4 <main+0xd30>)
- 80042a0: f505 7c6c add.w ip, r5, #944 ; 0x3b0
- 80042a4: f8c5 23ab str.w r2, [r5, #939] ; 0x3ab
- 80042a8: f885 33af strb.w r3, [r5, #943] ; 0x3af
- 80042ac: 46be mov lr, r7
- 80042ae: f10c 0c10 add.w ip, ip, #16
- 80042b2: 3710 adds r7, #16
- 80042b4: e8be 000f ldmia.w lr!, {r0, r1, r2, r3}
- 80042b8: f84c 3c04 str.w r3, [ip, #-4]
- 80042bc: 4b3b ldr r3, [pc, #236] ; (80043ac <main+0xd38>)
- 80042be: f84c 0c10 str.w r0, [ip, #-16]
- 80042c2: 459e cmp lr, r3
- 80042c4: f84c 1c0c str.w r1, [ip, #-12]
- 80042c8: f84c 2c08 str.w r2, [ip, #-8]
- 80042cc: d1ee bne.n 80042ac <main+0xc38>
- 80042ce: f04f 0e00 mov.w lr, #0
- 80042d2: f240 79c2 movw r9, #1986 ; 0x7c2
- 80042d6: f505 726a add.w r2, r5, #936 ; 0x3a8
- 80042da: 4673 mov r3, lr
- 80042dc: cf03 ldmia r7!, {r0, r1}
- 80042de: f8cc 0000 str.w r0, [ip]
- 80042e2: f205 30e7 addw r0, r5, #999 ; 0x3e7
- 80042e6: f8cc 1004 str.w r1, [ip, #4]
- 80042ea: 4931 ldr r1, [pc, #196] ; (80043b0 <main+0xd3c>)
- 80042ec: f885 e3aa strb.w lr, [r5, #938] ; 0x3aa
- 80042f0: f8c5 13a4 str.w r1, [r5, #932] ; 0x3a4
- 80042f4: f8a5 93a8 strh.w r9, [r5, #936] ; 0x3a8
- 80042f8: f812 1f01 ldrb.w r1, [r2, #1]!
- 80042fc: 4290 cmp r0, r2
- 80042fe: 440b add r3, r1
- 8004300: d1fa bne.n 80042f8 <main+0xc84>
- 8004302: f8d5 218c ldr.w r2, [r5, #396] ; 0x18c
- 8004306: 43db mvns r3, r3
- 8004308: f105 0904 add.w r9, r5, #4
- 800430c: f505 7769 add.w r7, r5, #932 ; 0x3a4
- 8004310: f5c2 7a80 rsb sl, r2, #256 ; 0x100
- 8004314: f885 33e8 strb.w r3, [r5, #1000] ; 0x3e8
- 8004318: 3288 adds r2, #136 ; 0x88
- 800431a: 4639 mov r1, r7
- 800431c: 4653 mov r3, sl
- 800431e: eb09 0002 add.w r0, r9, r2
- 8004322: 2b45 cmp r3, #69 ; 0x45
- 8004324: bf28 it cs
- 8004326: 2345 movcs r3, #69 ; 0x45
- 8004328: 461a mov r2, r3
- 800432a: 9300 str r3, [sp, #0]
- 800432c: f005 fd1e bl 8009d6c <memcpy>
- 8004330: f8d5 218c ldr.w r2, [r5, #396] ; 0x18c
- 8004334: f1ba 0f44 cmp.w sl, #68 ; 0x44
- 8004338: f102 0245 add.w r2, r2, #69 ; 0x45
- 800433c: b2d2 uxtb r2, r2
- 800433e: f8c5 218c str.w r2, [r5, #396] ; 0x18c
- 8004342: d807 bhi.n 8004354 <main+0xce0>
- 8004344: 9b00 ldr r3, [sp, #0]
- 8004346: f105 008c add.w r0, r5, #140 ; 0x8c
- 800434a: 18f9 adds r1, r7, r3
- 800434c: f1c3 0245 rsb r2, r3, #69 ; 0x45
- 8004350: f005 fd0c bl 8009d6c <memcpy>
- 8004354: 6868 ldr r0, [r5, #4]
- 8004356: 6f43 ldr r3, [r0, #116] ; 0x74
- 8004358: 2b20 cmp r3, #32
- 800435a: f47f ab5d bne.w 8003a18 <main+0x3a4>
- 800435e: 4b0e ldr r3, [pc, #56] ; (8004398 <main+0xd24>)
- 8004360: 781b ldrb r3, [r3, #0]
- 8004362: 2b00 cmp r3, #0
- 8004364: f47f ab58 bne.w 8003a18 <main+0x3a4>
- 8004368: f8d5 118c ldr.w r1, [r5, #396] ; 0x18c
- 800436c: 2201 movs r2, #1
- 800436e: f8d5 3190 ldr.w r3, [r5, #400] ; 0x190
- 8004372: 4f09 ldr r7, [pc, #36] ; (8004398 <main+0xd24>)
- 8004374: 4299 cmp r1, r3
- 8004376: 703a strb r2, [r7, #0]
- 8004378: f43f af57 beq.w 800422a <main+0xbb6>
- 800437c: b29a uxth r2, r3
- 800437e: bf8c ite hi
- 8004380: 1a8a subhi r2, r1, r2
- 8004382: f5c2 7280 rsbls r2, r2, #256 ; 0x100
- 8004386: b297 uxth r7, r2
- 8004388: e743 b.n 8004212 <main+0xb9e>
- 800438a: 4628 mov r0, r5
- 800438c: aa11 add r2, sp, #68 ; 0x44
- 800438e: 2107 movs r1, #7
- 8004390: 4798 blx r3
- 8004392: f7ff bb41 b.w 8003a18 <main+0x3a4>
- 8004396: bf00 nop
- 8004398: 2000009c .word 0x2000009c
- 800439c: 20000cf0 .word 0x20000cf0
- 80043a0: 0800a010 .word 0x0800a010
- 80043a4: 0800a380 .word 0x0800a380
- 80043a8: 080032d9 .word 0x080032d9
- 80043ac: 0800a3b0 .word 0x0800a3b0
- 80043b0: 003dfeff .word 0x003dfeff
- 80043b4: 20000d38 .word 0x20000d38
- 80043b8: 20000df0 .word 0x20000df0
-
-080043bc <HAL_UART_TxCpltCallback>:
- 80043bc: b570 push {r4, r5, r6, lr}
- 80043be: 4c13 ldr r4, [pc, #76] ; (800440c <HAL_UART_TxCpltCallback+0x50>)
- 80043c0: 6860 ldr r0, [r4, #4]
- 80043c2: 6f43 ldr r3, [r0, #116] ; 0x74
- 80043c4: 2b20 cmp r3, #32
- 80043c6: d000 beq.n 80043ca <HAL_UART_TxCpltCallback+0xe>
- 80043c8: bd70 pop {r4, r5, r6, pc}
- 80043ca: 4d11 ldr r5, [pc, #68] ; (8004410 <HAL_UART_TxCpltCallback+0x54>)
- 80043cc: 782b ldrb r3, [r5, #0]
- 80043ce: 2b00 cmp r3, #0
- 80043d0: d1fa bne.n 80043c8 <HAL_UART_TxCpltCallback+0xc>
- 80043d2: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 80043d6: 2201 movs r2, #1
- 80043d8: f8d4 1190 ldr.w r1, [r4, #400] ; 0x190
- 80043dc: 702a strb r2, [r5, #0]
- 80043de: 428b cmp r3, r1
- 80043e0: d011 beq.n 8004406 <HAL_UART_TxCpltCallback+0x4a>
- 80043e2: b28e uxth r6, r1
- 80043e4: f101 018c add.w r1, r1, #140 ; 0x8c
- 80043e8: bf8c ite hi
- 80043ea: 1b9e subhi r6, r3, r6
- 80043ec: f5c6 7680 rsbls r6, r6, #256 ; 0x100
- 80043f0: 4421 add r1, r4
- 80043f2: b2b6 uxth r6, r6
- 80043f4: 4632 mov r2, r6
- 80043f6: f003 fcdb bl 8007db0 <HAL_UART_Transmit_DMA>
- 80043fa: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 80043fe: 441e add r6, r3
- 8004400: b2f6 uxtb r6, r6
- 8004402: f8c4 6190 str.w r6, [r4, #400] ; 0x190
- 8004406: 2300 movs r3, #0
- 8004408: 702b strb r3, [r5, #0]
- 800440a: bd70 pop {r4, r5, r6, pc}
- 800440c: 20000450 .word 0x20000450
- 8004410: 2000009c .word 0x2000009c
-
-08004414 <HAL_UART_RxCpltCallback>:
- 8004414: 4b03 ldr r3, [pc, #12] ; (8004424 <HAL_UART_RxCpltCallback+0x10>)
- 8004416: 2280 movs r2, #128 ; 0x80
- 8004418: f103 0108 add.w r1, r3, #8
- 800441c: 6858 ldr r0, [r3, #4]
- 800441e: f003 bd19 b.w 8007e54 <HAL_UART_Receive_DMA>
- 8004422: bf00 nop
- 8004424: 20000450 .word 0x20000450
-
-08004428 <Error_Handler>:
- 8004428: 4770 bx lr
- 800442a: bf00 nop
-
-0800442c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv>:
- 800442c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
- 8004430: 4d3f ldr r5, [pc, #252] ; (8004530 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0x104>)
- 8004432: b084 sub sp, #16
- 8004434: 6801 ldr r1, [r0, #0]
- 8004436: 2300 movs r3, #0
- 8004438: 4a3e ldr r2, [pc, #248] ; (8004534 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0x108>)
- 800443a: 4604 mov r4, r0
- 800443c: 9501 str r5, [sp, #4]
- 800443e: 680d ldr r5, [r1, #0]
- 8004440: 4295 cmp r5, r2
- 8004442: e9cd 3302 strd r3, r3, [sp, #8]
- 8004446: d169 bne.n 800451c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0xf0>
- 8004448: f8d0 018c ldr.w r0, [r0, #396] ; 0x18c
- 800444c: f640 21f7 movw r1, #2807 ; 0xaf7
- 8004450: f8df e0e8 ldr.w lr, [pc, #232] ; 800453c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0x110>
- 8004454: f06f 0c0a mvn.w ip, #10
- 8004458: f5c0 7680 rsb r6, r0, #256 ; 0x100
- 800445c: 1d25 adds r5, r4, #4
- 800445e: 3088 adds r0, #136 ; 0x88
- 8004460: f504 7869 add.w r8, r4, #932 ; 0x3a4
- 8004464: 2e10 cmp r6, #16
- 8004466: 4637 mov r7, r6
- 8004468: f8c4 33ac str.w r3, [r4, #940] ; 0x3ac
- 800446c: 4428 add r0, r5
- 800446e: bf28 it cs
- 8004470: 2710 movcs r7, #16
- 8004472: f8a4 33b0 strh.w r3, [r4, #944] ; 0x3b0
- 8004476: f884 33b2 strb.w r3, [r4, #946] ; 0x3b2
- 800447a: f8c4 13a8 str.w r1, [r4, #936] ; 0x3a8
- 800447e: 463a mov r2, r7
- 8004480: f8c4 e3a4 str.w lr, [r4, #932] ; 0x3a4
- 8004484: 4641 mov r1, r8
- 8004486: f884 c3b3 strb.w ip, [r4, #947] ; 0x3b3
- 800448a: f005 fc6f bl 8009d6c <memcpy>
- 800448e: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8004492: 2e0f cmp r6, #15
- 8004494: f103 0310 add.w r3, r3, #16
- 8004498: b2db uxtb r3, r3
- 800449a: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 800449e: d90a bls.n 80044b6 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0x8a>
- 80044a0: 6860 ldr r0, [r4, #4]
- 80044a2: 6f43 ldr r3, [r0, #116] ; 0x74
- 80044a4: 2b20 cmp r3, #32
- 80044a6: d012 beq.n 80044ce <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0xa2>
- 80044a8: f001 fe54 bl 8006154 <HAL_GetTick>
- 80044ac: f8c4 0194 str.w r0, [r4, #404] ; 0x194
- 80044b0: b004 add sp, #16
- 80044b2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 80044b6: eb08 0107 add.w r1, r8, r7
- 80044ba: f1c7 0210 rsb r2, r7, #16
- 80044be: f104 008c add.w r0, r4, #140 ; 0x8c
- 80044c2: f005 fc53 bl 8009d6c <memcpy>
- 80044c6: 6860 ldr r0, [r4, #4]
- 80044c8: 6f43 ldr r3, [r0, #116] ; 0x74
- 80044ca: 2b20 cmp r3, #32
- 80044cc: d1ec bne.n 80044a8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0x7c>
- 80044ce: 4e1a ldr r6, [pc, #104] ; (8004538 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0x10c>)
- 80044d0: 7833 ldrb r3, [r6, #0]
- 80044d2: 2b00 cmp r3, #0
- 80044d4: d1e8 bne.n 80044a8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0x7c>
- 80044d6: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 80044da: 2301 movs r3, #1
- 80044dc: f8d4 2190 ldr.w r2, [r4, #400] ; 0x190
- 80044e0: 7033 strb r3, [r6, #0]
- 80044e2: 4291 cmp r1, r2
- 80044e4: d011 beq.n 800450a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv+0xde>
- 80044e6: b293 uxth r3, r2
- 80044e8: bf8c ite hi
- 80044ea: 1acb subhi r3, r1, r3
- 80044ec: f5c3 7380 rsbls r3, r3, #256 ; 0x100
- 80044f0: f102 0188 add.w r1, r2, #136 ; 0x88
- 80044f4: b29f uxth r7, r3
- 80044f6: 4429 add r1, r5
- 80044f8: 463a mov r2, r7
- 80044fa: f003 fc59 bl 8007db0 <HAL_UART_Transmit_DMA>
- 80044fe: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8004502: 443b add r3, r7
- 8004504: b2db uxtb r3, r3
- 8004506: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 800450a: 2300 movs r3, #0
- 800450c: 7033 strb r3, [r6, #0]
- 800450e: f001 fe21 bl 8006154 <HAL_GetTick>
- 8004512: f8c4 0194 str.w r0, [r4, #404] ; 0x194
- 8004516: b004 add sp, #16
- 8004518: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 800451c: aa01 add r2, sp, #4
- 800451e: 210a movs r1, #10
- 8004520: 47a8 blx r5
- 8004522: f001 fe17 bl 8006154 <HAL_GetTick>
- 8004526: f8c4 0194 str.w r0, [r4, #404] ; 0x194
- 800452a: b004 add sp, #16
- 800452c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8004530: 08009fe0 .word 0x08009fe0
- 8004534: 080032d9 .word 0x080032d9
- 8004538: 2000009c .word 0x2000009c
- 800453c: 0008feff .word 0x0008feff
-
-08004540 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv>:
- 8004540: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 8004544: 2200 movs r2, #0
- 8004546: b08f sub sp, #60 ; 0x3c
- 8004548: 4b8f ldr r3, [pc, #572] ; (8004788 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x248>)
- 800454a: 4604 mov r4, r0
- 800454c: 498f ldr r1, [pc, #572] ; (800478c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x24c>)
- 800454e: f500 65b4 add.w r5, r0, #1440 ; 0x5a0
- 8004552: f200 6004 addw r0, r0, #1540 ; 0x604
- 8004556: f8ad 2024 strh.w r2, [sp, #36] ; 0x24
- 800455a: 9108 str r1, [sp, #32]
- 800455c: 9001 str r0, [sp, #4]
- 800455e: 920d str r2, [sp, #52] ; 0x34
- 8004560: 930c str r3, [sp, #48] ; 0x30
- 8004562: e9cd 330a strd r3, r3, [sp, #40] ; 0x28
- 8004566: f855 3f04 ldr.w r3, [r5, #4]!
- 800456a: 2b00 cmp r3, #0
- 800456c: f000 80d9 beq.w 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 8004570: 681a ldr r2, [r3, #0]
- 8004572: e9d3 0101 ldrd r0, r1, [r3, #4]
- 8004576: 6806 ldr r6, [r0, #0]
- 8004578: f8ad 1024 strh.w r1, [sp, #36] ; 0x24
- 800457c: 68b3 ldr r3, [r6, #8]
- 800457e: 920a str r2, [sp, #40] ; 0x28
- 8004580: 4798 blx r3
- 8004582: 682b ldr r3, [r5, #0]
- 8004584: 900b str r0, [sp, #44] ; 0x2c
- 8004586: 6858 ldr r0, [r3, #4]
- 8004588: 6803 ldr r3, [r0, #0]
- 800458a: 68db ldr r3, [r3, #12]
- 800458c: 4798 blx r3
- 800458e: 682a ldr r2, [r5, #0]
- 8004590: 6823 ldr r3, [r4, #0]
- 8004592: f44f 7100 mov.w r1, #512 ; 0x200
- 8004596: f8d2 a010 ldr.w sl, [r2, #16]
- 800459a: 4681 mov r9, r0
- 800459c: 681b ldr r3, [r3, #0]
- 800459e: 4a7c ldr r2, [pc, #496] ; (8004790 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x250>)
- 80045a0: 4293 cmp r3, r2
- 80045a2: e9cd 010c strd r0, r1, [sp, #48] ; 0x30
- 80045a6: f040 8200 bne.w 80049aa <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x46a>
- 80045aa: f1ba 0f63 cmp.w sl, #99 ; 0x63
- 80045ae: dd04 ble.n 80045ba <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x7a>
- 80045b0: f894 3680 ldrb.w r3, [r4, #1664] ; 0x680
- 80045b4: 2b00 cmp r3, #0
- 80045b6: f000 80b4 beq.w 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 80045ba: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24
- 80045be: f204 37ab addw r7, r4, #939 ; 0x3ab
- 80045c2: 9e0a ldr r6, [sp, #40] ; 0x28
- 80045c4: 0a1a lsrs r2, r3, #8
- 80045c6: f884 33ab strb.w r3, [r4, #939] ; 0x3ab
- 80045ca: 4630 mov r0, r6
- 80045cc: f884 23ac strb.w r2, [r4, #940] ; 0x3ac
- 80045d0: f7fb fe32 bl 8000238 <strlen>
- 80045d4: 4680 mov r8, r0
- 80045d6: 4631 mov r1, r6
- 80045d8: f204 30b1 addw r0, r4, #945 ; 0x3b1
- 80045dc: 4642 mov r2, r8
- 80045de: ea4f 2618 mov.w r6, r8, lsr #8
- 80045e2: ea4f 4318 mov.w r3, r8, lsr #16
- 80045e6: f884 83ad strb.w r8, [r4, #941] ; 0x3ad
- 80045ea: f884 63ae strb.w r6, [r4, #942] ; 0x3ae
- 80045ee: 0e16 lsrs r6, r2, #24
- 80045f0: f884 33af strb.w r3, [r4, #943] ; 0x3af
- 80045f4: 1d93 adds r3, r2, #6
- 80045f6: f884 63b0 strb.w r6, [r4, #944] ; 0x3b0
- 80045fa: f108 0b0a add.w fp, r8, #10
- 80045fe: 9303 str r3, [sp, #12]
- 8004600: f005 fbb4 bl 8009d6c <memcpy>
- 8004604: 990b ldr r1, [sp, #44] ; 0x2c
- 8004606: 44b8 add r8, r7
- 8004608: 4608 mov r0, r1
- 800460a: 9102 str r1, [sp, #8]
- 800460c: f7fb fe14 bl 8000238 <strlen>
- 8004610: 9b03 ldr r3, [sp, #12]
- 8004612: 4606 mov r6, r0
- 8004614: 0a00 lsrs r0, r0, #8
- 8004616: 9902 ldr r1, [sp, #8]
- 8004618: 54fe strb r6, [r7, r3]
- 800461a: 0c32 lsrs r2, r6, #16
- 800461c: 0e33 lsrs r3, r6, #24
- 800461e: f888 0007 strb.w r0, [r8, #7]
- 8004622: f888 2008 strb.w r2, [r8, #8]
- 8004626: eb07 000b add.w r0, r7, fp
- 800462a: f888 3009 strb.w r3, [r8, #9]
- 800462e: 4632 mov r2, r6
- 8004630: f005 fb9c bl 8009d6c <memcpy>
- 8004634: 4648 mov r0, r9
- 8004636: f7fb fdff bl 8000238 <strlen>
- 800463a: 445e add r6, fp
- 800463c: 4680 mov r8, r0
- 800463e: ea4f 2c10 mov.w ip, r0, lsr #8
- 8004642: 19bb adds r3, r7, r6
- 8004644: f106 0b04 add.w fp, r6, #4
- 8004648: ea4f 6218 mov.w r2, r8, lsr #24
- 800464c: 55b8 strb r0, [r7, r6]
- 800464e: 0c00 lsrs r0, r0, #16
- 8004650: f883 c001 strb.w ip, [r3, #1]
- 8004654: 70da strb r2, [r3, #3]
- 8004656: 4642 mov r2, r8
- 8004658: 44d8 add r8, fp
- 800465a: 7098 strb r0, [r3, #2]
- 800465c: 4649 mov r1, r9
- 800465e: eb07 000b add.w r0, r7, fp
- 8004662: f108 0604 add.w r6, r8, #4
- 8004666: f005 fb81 bl 8009d6c <memcpy>
- 800466a: f44f 7300 mov.w r3, #512 ; 0x200
- 800466e: f34a 2c07 sbfx ip, sl, #8, #8
- 8004672: f3c6 2207 ubfx r2, r6, #8, #8
- 8004676: b2f1 uxtb r1, r6
- 8004678: f847 3008 str.w r3, [r7, r8]
- 800467c: f64f 60ff movw r0, #65279 ; 0xfeff
- 8004680: 188b adds r3, r1, r2
- 8004682: f884 23a7 strb.w r2, [r4, #935] ; 0x3a7
- 8004686: 1c72 adds r2, r6, #1
- 8004688: f884 a3a9 strb.w sl, [r4, #937] ; 0x3a9
- 800468c: ea6f 0303 mvn.w r3, r3
- 8004690: f884 c3aa strb.w ip, [r4, #938] ; 0x3aa
- 8004694: f884 13a6 strb.w r1, [r4, #934] ; 0x3a6
- 8004698: f8a4 03a4 strh.w r0, [r4, #932] ; 0x3a4
- 800469c: f884 33a8 strb.w r3, [r4, #936] ; 0x3a8
- 80046a0: f2c0 818f blt.w 80049c2 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x482>
- 80046a4: f204 30ae addw r0, r4, #942 ; 0x3ae
- 80046a8: f504 736a add.w r3, r4, #936 ; 0x3a8
- 80046ac: 2100 movs r1, #0
- 80046ae: 4440 add r0, r8
- 80046b0: f813 2f01 ldrb.w r2, [r3, #1]!
- 80046b4: 4298 cmp r0, r3
- 80046b6: 4411 add r1, r2
- 80046b8: d1fa bne.n 80046b0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x170>
- 80046ba: 43c9 mvns r1, r1
- 80046bc: b2c9 uxtb r1, r1
- 80046be: 19a3 adds r3, r4, r6
- 80046c0: 3608 adds r6, #8
- 80046c2: f5b6 7f00 cmp.w r6, #512 ; 0x200
- 80046c6: f883 13ab strb.w r1, [r3, #939] ; 0x3ab
- 80046ca: f300 8210 bgt.w 8004aee <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x5ae>
- 80046ce: f8d4 018c ldr.w r0, [r4, #396] ; 0x18c
- 80046d2: f5b6 7f80 cmp.w r6, #256 ; 0x100
- 80046d6: f104 0804 add.w r8, r4, #4
- 80046da: f504 7969 add.w r9, r4, #932 ; 0x3a4
- 80046de: f5c0 7780 rsb r7, r0, #256 ; 0x100
- 80046e2: bfa8 it ge
- 80046e4: f44f 7680 movge.w r6, #256 ; 0x100
- 80046e8: 3088 adds r0, #136 ; 0x88
- 80046ea: 4649 mov r1, r9
- 80046ec: 42b7 cmp r7, r6
- 80046ee: 4440 add r0, r8
- 80046f0: bf28 it cs
- 80046f2: 4637 movcs r7, r6
- 80046f4: 463a mov r2, r7
- 80046f6: f005 fb39 bl 8009d6c <memcpy>
- 80046fa: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 80046fe: 42be cmp r6, r7
- 8004700: 4433 add r3, r6
- 8004702: b2db uxtb r3, r3
- 8004704: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 8004708: d006 beq.n 8004718 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1d8>
- 800470a: 1bf2 subs r2, r6, r7
- 800470c: eb09 0107 add.w r1, r9, r7
- 8004710: f104 008c add.w r0, r4, #140 ; 0x8c
- 8004714: f005 fb2a bl 8009d6c <memcpy>
- 8004718: 6860 ldr r0, [r4, #4]
- 800471a: 6f43 ldr r3, [r0, #116] ; 0x74
- 800471c: 2b20 cmp r3, #32
- 800471e: f000 8103 beq.w 8004928 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3e8>
- 8004722: 9b01 ldr r3, [sp, #4]
- 8004724: 42ab cmp r3, r5
- 8004726: f47f af1e bne.w 8004566 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x26>
- 800472a: 461e mov r6, r3
- 800472c: f504 68cd add.w r8, r4, #1640 ; 0x668
- 8004730: f856 3f04 ldr.w r3, [r6, #4]!
- 8004734: 2b00 cmp r3, #0
- 8004736: f000 80ee beq.w 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 800473a: 6859 ldr r1, [r3, #4]
- 800473c: 4618 mov r0, r3
- 800473e: 689a ldr r2, [r3, #8]
- 8004740: 681b ldr r3, [r3, #0]
- 8004742: f8ad 1024 strh.w r1, [sp, #36] ; 0x24
- 8004746: 920a str r2, [sp, #40] ; 0x28
- 8004748: 689b ldr r3, [r3, #8]
- 800474a: 4798 blx r3
- 800474c: 6833 ldr r3, [r6, #0]
- 800474e: 900b str r0, [sp, #44] ; 0x2c
- 8004750: 681a ldr r2, [r3, #0]
- 8004752: 4618 mov r0, r3
- 8004754: 68d3 ldr r3, [r2, #12]
- 8004756: 4798 blx r3
- 8004758: 6833 ldr r3, [r6, #0]
- 800475a: 6825 ldr r5, [r4, #0]
- 800475c: f44f 7200 mov.w r2, #512 ; 0x200
- 8004760: 6819 ldr r1, [r3, #0]
- 8004762: 682d ldr r5, [r5, #0]
- 8004764: 900c str r0, [sp, #48] ; 0x30
- 8004766: 4618 mov r0, r3
- 8004768: 684b ldr r3, [r1, #4]
- 800476a: 920d str r2, [sp, #52] ; 0x34
- 800476c: 4798 blx r3
- 800476e: 4b08 ldr r3, [pc, #32] ; (8004790 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x250>)
- 8004770: 4681 mov r9, r0
- 8004772: 429d cmp r5, r3
- 8004774: f040 811e bne.w 80049b4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x474>
- 8004778: 2863 cmp r0, #99 ; 0x63
- 800477a: dd0b ble.n 8004794 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x254>
- 800477c: f894 3680 ldrb.w r3, [r4, #1664] ; 0x680
- 8004780: 2b00 cmp r3, #0
- 8004782: f000 80c8 beq.w 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 8004786: e005 b.n 8004794 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x254>
- 8004788: 0800a3b8 .word 0x0800a3b8
- 800478c: 08009ff8 .word 0x08009ff8
- 8004790: 080032d9 .word 0x080032d9
- 8004794: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24
- 8004798: f204 35ab addw r5, r4, #939 ; 0x3ab
- 800479c: f8dd a028 ldr.w sl, [sp, #40] ; 0x28
- 80047a0: 0a1a lsrs r2, r3, #8
- 80047a2: f884 33ab strb.w r3, [r4, #939] ; 0x3ab
- 80047a6: 4650 mov r0, sl
- 80047a8: f884 23ac strb.w r2, [r4, #940] ; 0x3ac
- 80047ac: f7fb fd44 bl 8000238 <strlen>
- 80047b0: 4607 mov r7, r0
- 80047b2: 4651 mov r1, sl
- 80047b4: f204 30b1 addw r0, r4, #945 ; 0x3b1
- 80047b8: ea4f 2e17 mov.w lr, r7, lsr #8
- 80047bc: 463a mov r2, r7
- 80047be: ea4f 4c17 mov.w ip, r7, lsr #16
- 80047c2: f884 73ad strb.w r7, [r4, #941] ; 0x3ad
- 80047c6: 0e3b lsrs r3, r7, #24
- 80047c8: f884 e3ae strb.w lr, [r4, #942] ; 0x3ae
- 80047cc: f884 c3af strb.w ip, [r4, #943] ; 0x3af
- 80047d0: f107 0a06 add.w sl, r7, #6
- 80047d4: f884 33b0 strb.w r3, [r4, #944] ; 0x3b0
- 80047d8: f107 0b0a add.w fp, r7, #10
- 80047dc: f005 fac6 bl 8009d6c <memcpy>
- 80047e0: 990b ldr r1, [sp, #44] ; 0x2c
- 80047e2: 442f add r7, r5
- 80047e4: 4608 mov r0, r1
- 80047e6: 9101 str r1, [sp, #4]
- 80047e8: f7fb fd26 bl 8000238 <strlen>
- 80047ec: 4602 mov r2, r0
- 80047ee: ea4f 2e10 mov.w lr, r0, lsr #8
- 80047f2: f805 000a strb.w r0, [r5, sl]
- 80047f6: ea4f 4c10 mov.w ip, r0, lsr #16
- 80047fa: 9901 ldr r1, [sp, #4]
- 80047fc: 0e13 lsrs r3, r2, #24
- 80047fe: f887 e007 strb.w lr, [r7, #7]
- 8004802: f887 c008 strb.w ip, [r7, #8]
- 8004806: eb05 000b add.w r0, r5, fp
- 800480a: 727b strb r3, [r7, #9]
- 800480c: 4493 add fp, r2
- 800480e: f005 faad bl 8009d6c <memcpy>
- 8004812: 990c ldr r1, [sp, #48] ; 0x30
- 8004814: f10b 0a04 add.w sl, fp, #4
- 8004818: 4608 mov r0, r1
- 800481a: 9101 str r1, [sp, #4]
- 800481c: f7fb fd0c bl 8000238 <strlen>
- 8004820: 4607 mov r7, r0
- 8004822: eb05 030b add.w r3, r5, fp
- 8004826: ea4f 2e10 mov.w lr, r0, lsr #8
- 800482a: ea4f 6c17 mov.w ip, r7, lsr #24
- 800482e: f805 000b strb.w r0, [r5, fp]
- 8004832: 0c02 lsrs r2, r0, #16
- 8004834: f883 e001 strb.w lr, [r3, #1]
- 8004838: eb05 000a add.w r0, r5, sl
- 800483c: f883 c003 strb.w ip, [r3, #3]
- 8004840: 709a strb r2, [r3, #2]
- 8004842: 463a mov r2, r7
- 8004844: 9901 ldr r1, [sp, #4]
- 8004846: f005 fa91 bl 8009d6c <memcpy>
- 800484a: eb07 020a add.w r2, r7, sl
- 800484e: 9b0d ldr r3, [sp, #52] ; 0x34
- 8004850: f349 2c07 sbfx ip, r9, #8, #8
- 8004854: 1d17 adds r7, r2, #4
- 8004856: 18a8 adds r0, r5, r2
- 8004858: 54ab strb r3, [r5, r2]
- 800485a: 0a19 lsrs r1, r3, #8
- 800485c: fa5f fe87 uxtb.w lr, r7
- 8004860: f3c7 2507 ubfx r5, r7, #8, #8
- 8004864: 7041 strb r1, [r0, #1]
- 8004866: ea4f 4a13 mov.w sl, r3, lsr #16
- 800486a: eb0e 0105 add.w r1, lr, r5
- 800486e: 0e1b lsrs r3, r3, #24
- 8004870: f880 a002 strb.w sl, [r0, #2]
- 8004874: f64f 6aff movw sl, #65279 ; 0xfeff
- 8004878: 70c3 strb r3, [r0, #3]
- 800487a: 43c9 mvns r1, r1
- 800487c: 1c7b adds r3, r7, #1
- 800487e: f884 e3a6 strb.w lr, [r4, #934] ; 0x3a6
- 8004882: f884 13a8 strb.w r1, [r4, #936] ; 0x3a8
- 8004886: f884 53a7 strb.w r5, [r4, #935] ; 0x3a7
- 800488a: f884 93a9 strb.w r9, [r4, #937] ; 0x3a9
- 800488e: f884 c3aa strb.w ip, [r4, #938] ; 0x3aa
- 8004892: f8a4 a3a4 strh.w sl, [r4, #932] ; 0x3a4
- 8004896: f2c0 8092 blt.w 80049be <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x47e>
- 800489a: f204 30ae addw r0, r4, #942 ; 0x3ae
- 800489e: f504 736a add.w r3, r4, #936 ; 0x3a8
- 80048a2: 2100 movs r1, #0
- 80048a4: 4410 add r0, r2
- 80048a6: f813 2f01 ldrb.w r2, [r3, #1]!
- 80048aa: 4298 cmp r0, r3
- 80048ac: 4411 add r1, r2
- 80048ae: d1fa bne.n 80048a6 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x366>
- 80048b0: 43c9 mvns r1, r1
- 80048b2: b2c9 uxtb r1, r1
- 80048b4: 19e3 adds r3, r4, r7
- 80048b6: 3708 adds r7, #8
- 80048b8: f5b7 7f00 cmp.w r7, #512 ; 0x200
- 80048bc: f883 13ab strb.w r1, [r3, #939] ; 0x3ab
- 80048c0: f300 8087 bgt.w 80049d2 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x492>
- 80048c4: f8d4 018c ldr.w r0, [r4, #396] ; 0x18c
- 80048c8: f5b7 7f80 cmp.w r7, #256 ; 0x100
- 80048cc: f104 0904 add.w r9, r4, #4
- 80048d0: f504 7a69 add.w sl, r4, #932 ; 0x3a4
- 80048d4: f5c0 7580 rsb r5, r0, #256 ; 0x100
- 80048d8: bfa8 it ge
- 80048da: f44f 7780 movge.w r7, #256 ; 0x100
- 80048de: 3088 adds r0, #136 ; 0x88
- 80048e0: 4651 mov r1, sl
- 80048e2: 42bd cmp r5, r7
- 80048e4: 4448 add r0, r9
- 80048e6: bf28 it cs
- 80048e8: 463d movcs r5, r7
- 80048ea: 462a mov r2, r5
- 80048ec: f005 fa3e bl 8009d6c <memcpy>
- 80048f0: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 80048f4: 42af cmp r7, r5
- 80048f6: 443b add r3, r7
- 80048f8: b2db uxtb r3, r3
- 80048fa: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 80048fe: d006 beq.n 800490e <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3ce>
- 8004900: 1b7a subs r2, r7, r5
- 8004902: eb0a 0105 add.w r1, sl, r5
- 8004906: f104 008c add.w r0, r4, #140 ; 0x8c
- 800490a: f005 fa2f bl 8009d6c <memcpy>
- 800490e: 6860 ldr r0, [r4, #4]
- 8004910: 6f43 ldr r3, [r0, #116] ; 0x74
- 8004912: 2b20 cmp r3, #32
- 8004914: d029 beq.n 800496a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x42a>
- 8004916: 45b0 cmp r8, r6
- 8004918: f47f af0a bne.w 8004730 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1f0>
- 800491c: 2301 movs r3, #1
- 800491e: f884 3680 strb.w r3, [r4, #1664] ; 0x680
- 8004922: b00f add sp, #60 ; 0x3c
- 8004924: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 8004928: 4ebd ldr r6, [pc, #756] ; (8004c20 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e0>)
- 800492a: 7833 ldrb r3, [r6, #0]
- 800492c: 2b00 cmp r3, #0
- 800492e: f47f aef8 bne.w 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 8004932: f8d4 218c ldr.w r2, [r4, #396] ; 0x18c
- 8004936: 2101 movs r1, #1
- 8004938: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 800493c: 7031 strb r1, [r6, #0]
- 800493e: 429a cmp r2, r3
- 8004940: d010 beq.n 8004964 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x424>
- 8004942: b29f uxth r7, r3
- 8004944: d842 bhi.n 80049cc <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x48c>
- 8004946: f5c7 7780 rsb r7, r7, #256 ; 0x100
- 800494a: b2bf uxth r7, r7
- 800494c: 3388 adds r3, #136 ; 0x88
- 800494e: 463a mov r2, r7
- 8004950: eb08 0103 add.w r1, r8, r3
- 8004954: f003 fa2c bl 8007db0 <HAL_UART_Transmit_DMA>
- 8004958: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 800495c: 443b add r3, r7
- 800495e: b2db uxtb r3, r3
- 8004960: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 8004964: 2300 movs r3, #0
- 8004966: 7033 strb r3, [r6, #0]
- 8004968: e6db b.n 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 800496a: 4dad ldr r5, [pc, #692] ; (8004c20 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e0>)
- 800496c: 782b ldrb r3, [r5, #0]
- 800496e: 2b00 cmp r3, #0
- 8004970: d1d1 bne.n 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 8004972: f8d4 218c ldr.w r2, [r4, #396] ; 0x18c
- 8004976: 2101 movs r1, #1
- 8004978: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 800497c: 7029 strb r1, [r5, #0]
- 800497e: 429a cmp r2, r3
- 8004980: d010 beq.n 80049a4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x464>
- 8004982: b29f uxth r7, r3
- 8004984: d81f bhi.n 80049c6 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x486>
- 8004986: f5c7 7780 rsb r7, r7, #256 ; 0x100
- 800498a: b2bf uxth r7, r7
- 800498c: 3388 adds r3, #136 ; 0x88
- 800498e: 463a mov r2, r7
- 8004990: eb09 0103 add.w r1, r9, r3
- 8004994: f003 fa0c bl 8007db0 <HAL_UART_Transmit_DMA>
- 8004998: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 800499c: 443b add r3, r7
- 800499e: b2db uxtb r3, r3
- 80049a0: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 80049a4: 2300 movs r3, #0
- 80049a6: 702b strb r3, [r5, #0]
- 80049a8: e7b5 b.n 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 80049aa: 4651 mov r1, sl
- 80049ac: aa08 add r2, sp, #32
- 80049ae: 4620 mov r0, r4
- 80049b0: 4798 blx r3
- 80049b2: e6b6 b.n 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 80049b4: 4601 mov r1, r0
- 80049b6: aa08 add r2, sp, #32
- 80049b8: 4620 mov r0, r4
- 80049ba: 47a8 blx r5
- 80049bc: e7ab b.n 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 80049be: 21ff movs r1, #255 ; 0xff
- 80049c0: e778 b.n 80048b4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x374>
- 80049c2: 21ff movs r1, #255 ; 0xff
- 80049c4: e67b b.n 80046be <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x17e>
- 80049c6: 1bd2 subs r2, r2, r7
- 80049c8: b297 uxth r7, r2
- 80049ca: e7df b.n 800498c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x44c>
- 80049cc: 1bd2 subs r2, r2, r7
- 80049ce: b297 uxth r7, r2
- 80049d0: e7bc b.n 800494c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x40c>
- 80049d2: 2203 movs r2, #3
- 80049d4: 6823 ldr r3, [r4, #0]
- 80049d6: 4d93 ldr r5, [pc, #588] ; (8004c24 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e4>)
- 80049d8: f88d 2018 strb.w r2, [sp, #24]
- 80049dc: 4a92 ldr r2, [pc, #584] ; (8004c28 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e8>)
- 80049de: 681b ldr r3, [r3, #0]
- 80049e0: 9205 str r2, [sp, #20]
- 80049e2: 4a92 ldr r2, [pc, #584] ; (8004c2c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6ec>)
- 80049e4: 9507 str r5, [sp, #28]
- 80049e6: 4293 cmp r3, r2
- 80049e8: f040 8114 bne.w 8004c14 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6d4>
- 80049ec: f643 0203 movw r2, #14339 ; 0x3803
- 80049f0: 2300 movs r3, #0
- 80049f2: f504 7c6c add.w ip, r4, #944 ; 0x3b0
- 80049f6: f105 0e30 add.w lr, r5, #48 ; 0x30
- 80049fa: f8c4 23ab str.w r2, [r4, #939] ; 0x3ab
- 80049fe: f884 33af strb.w r3, [r4, #943] ; 0x3af
- 8004a02: 462f mov r7, r5
- 8004a04: f10c 0c10 add.w ip, ip, #16
- 8004a08: 3510 adds r5, #16
- 8004a0a: cf0f ldmia r7!, {r0, r1, r2, r3}
- 8004a0c: 4577 cmp r7, lr
- 8004a0e: f84c 0c10 str.w r0, [ip, #-16]
- 8004a12: f84c 1c0c str.w r1, [ip, #-12]
- 8004a16: f84c 2c08 str.w r2, [ip, #-8]
- 8004a1a: f84c 3c04 str.w r3, [ip, #-4]
- 8004a1e: d1f0 bne.n 8004a02 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x4c2>
- 8004a20: 2700 movs r7, #0
- 8004a22: f240 7ec2 movw lr, #1986 ; 0x7c2
- 8004a26: f504 736a add.w r3, r4, #936 ; 0x3a8
- 8004a2a: 463a mov r2, r7
- 8004a2c: cd03 ldmia r5!, {r0, r1}
- 8004a2e: f8cc 0000 str.w r0, [ip]
- 8004a32: f204 30e7 addw r0, r4, #999 ; 0x3e7
- 8004a36: f8cc 1004 str.w r1, [ip, #4]
- 8004a3a: 497d ldr r1, [pc, #500] ; (8004c30 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6f0>)
- 8004a3c: f884 73aa strb.w r7, [r4, #938] ; 0x3aa
- 8004a40: f8c4 13a4 str.w r1, [r4, #932] ; 0x3a4
- 8004a44: f8a4 e3a8 strh.w lr, [r4, #936] ; 0x3a8
- 8004a48: f813 1f01 ldrb.w r1, [r3, #1]!
- 8004a4c: 4298 cmp r0, r3
- 8004a4e: 440a add r2, r1
- 8004a50: d1fa bne.n 8004a48 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x508>
- 8004a52: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8004a56: 43d2 mvns r2, r2
- 8004a58: 1d27 adds r7, r4, #4
- 8004a5a: f504 7969 add.w r9, r4, #932 ; 0x3a4
- 8004a5e: f5c3 7580 rsb r5, r3, #256 ; 0x100
- 8004a62: 3388 adds r3, #136 ; 0x88
- 8004a64: f884 23e8 strb.w r2, [r4, #1000] ; 0x3e8
- 8004a68: 4649 mov r1, r9
- 8004a6a: 2d45 cmp r5, #69 ; 0x45
- 8004a6c: 46aa mov sl, r5
- 8004a6e: eb07 0003 add.w r0, r7, r3
- 8004a72: bf28 it cs
- 8004a74: f04f 0a45 movcs.w sl, #69 ; 0x45
- 8004a78: 4652 mov r2, sl
- 8004a7a: f005 f977 bl 8009d6c <memcpy>
- 8004a7e: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8004a82: 2d44 cmp r5, #68 ; 0x44
- 8004a84: f103 0345 add.w r3, r3, #69 ; 0x45
- 8004a88: b2db uxtb r3, r3
- 8004a8a: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 8004a8e: d807 bhi.n 8004aa0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x560>
- 8004a90: eb09 010a add.w r1, r9, sl
- 8004a94: f1ca 0245 rsb r2, sl, #69 ; 0x45
- 8004a98: f104 008c add.w r0, r4, #140 ; 0x8c
- 8004a9c: f005 f966 bl 8009d6c <memcpy>
- 8004aa0: 6860 ldr r0, [r4, #4]
- 8004aa2: 6f43 ldr r3, [r0, #116] ; 0x74
- 8004aa4: 2b20 cmp r3, #32
- 8004aa6: f47f af36 bne.w 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 8004aaa: 4d5d ldr r5, [pc, #372] ; (8004c20 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e0>)
- 8004aac: 782b ldrb r3, [r5, #0]
- 8004aae: 2b00 cmp r3, #0
- 8004ab0: f47f af31 bne.w 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 8004ab4: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 8004ab8: 2201 movs r2, #1
- 8004aba: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8004abe: 702a strb r2, [r5, #0]
- 8004ac0: 4299 cmp r1, r3
- 8004ac2: f43f af6f beq.w 80049a4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x464>
- 8004ac6: b29a uxth r2, r3
- 8004ac8: f103 0388 add.w r3, r3, #136 ; 0x88
- 8004acc: bf8c ite hi
- 8004ace: 1a8a subhi r2, r1, r2
- 8004ad0: f5c2 7280 rsbls r2, r2, #256 ; 0x100
- 8004ad4: 18f9 adds r1, r7, r3
- 8004ad6: fa1f f982 uxth.w r9, r2
- 8004ada: 464a mov r2, r9
- 8004adc: f003 f968 bl 8007db0 <HAL_UART_Transmit_DMA>
- 8004ae0: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8004ae4: 444b add r3, r9
- 8004ae6: b2db uxtb r3, r3
- 8004ae8: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 8004aec: e75a b.n 80049a4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x464>
- 8004aee: 2203 movs r2, #3
- 8004af0: 6823 ldr r3, [r4, #0]
- 8004af2: 4e4c ldr r6, [pc, #304] ; (8004c24 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e4>)
- 8004af4: f88d 2018 strb.w r2, [sp, #24]
- 8004af8: 4a4b ldr r2, [pc, #300] ; (8004c28 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e8>)
- 8004afa: 681b ldr r3, [r3, #0]
- 8004afc: 9205 str r2, [sp, #20]
- 8004afe: 4a4b ldr r2, [pc, #300] ; (8004c2c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6ec>)
- 8004b00: 9607 str r6, [sp, #28]
- 8004b02: 4293 cmp r3, r2
- 8004b04: f040 8081 bne.w 8004c0a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6ca>
- 8004b08: f643 0203 movw r2, #14339 ; 0x3803
- 8004b0c: 2300 movs r3, #0
- 8004b0e: f504 7c6c add.w ip, r4, #944 ; 0x3b0
- 8004b12: f106 0e30 add.w lr, r6, #48 ; 0x30
- 8004b16: f8c4 23ab str.w r2, [r4, #939] ; 0x3ab
- 8004b1a: f884 33af strb.w r3, [r4, #943] ; 0x3af
- 8004b1e: 4637 mov r7, r6
- 8004b20: f10c 0c10 add.w ip, ip, #16
- 8004b24: 3610 adds r6, #16
- 8004b26: cf0f ldmia r7!, {r0, r1, r2, r3}
- 8004b28: 4577 cmp r7, lr
- 8004b2a: f84c 0c10 str.w r0, [ip, #-16]
- 8004b2e: f84c 1c0c str.w r1, [ip, #-12]
- 8004b32: f84c 2c08 str.w r2, [ip, #-8]
- 8004b36: f84c 3c04 str.w r3, [ip, #-4]
- 8004b3a: d1f0 bne.n 8004b1e <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x5de>
- 8004b3c: 2700 movs r7, #0
- 8004b3e: f240 7ec2 movw lr, #1986 ; 0x7c2
- 8004b42: f504 736a add.w r3, r4, #936 ; 0x3a8
- 8004b46: 463a mov r2, r7
- 8004b48: ce03 ldmia r6!, {r0, r1}
- 8004b4a: f8cc 0000 str.w r0, [ip]
- 8004b4e: f204 30e7 addw r0, r4, #999 ; 0x3e7
- 8004b52: f8cc 1004 str.w r1, [ip, #4]
- 8004b56: 4936 ldr r1, [pc, #216] ; (8004c30 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6f0>)
- 8004b58: f884 73aa strb.w r7, [r4, #938] ; 0x3aa
- 8004b5c: f8c4 13a4 str.w r1, [r4, #932] ; 0x3a4
- 8004b60: f8a4 e3a8 strh.w lr, [r4, #936] ; 0x3a8
- 8004b64: f813 1f01 ldrb.w r1, [r3, #1]!
- 8004b68: 4298 cmp r0, r3
- 8004b6a: 440a add r2, r1
- 8004b6c: d1fa bne.n 8004b64 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x624>
- 8004b6e: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8004b72: 43d2 mvns r2, r2
- 8004b74: 1d27 adds r7, r4, #4
- 8004b76: f504 7869 add.w r8, r4, #932 ; 0x3a4
- 8004b7a: f5c3 7680 rsb r6, r3, #256 ; 0x100
- 8004b7e: 3388 adds r3, #136 ; 0x88
- 8004b80: f884 23e8 strb.w r2, [r4, #1000] ; 0x3e8
- 8004b84: 4641 mov r1, r8
- 8004b86: 2e45 cmp r6, #69 ; 0x45
- 8004b88: 46b1 mov r9, r6
- 8004b8a: eb07 0003 add.w r0, r7, r3
- 8004b8e: bf28 it cs
- 8004b90: f04f 0945 movcs.w r9, #69 ; 0x45
- 8004b94: 464a mov r2, r9
- 8004b96: f005 f8e9 bl 8009d6c <memcpy>
- 8004b9a: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8004b9e: 2e44 cmp r6, #68 ; 0x44
- 8004ba0: f103 0345 add.w r3, r3, #69 ; 0x45
- 8004ba4: b2db uxtb r3, r3
- 8004ba6: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 8004baa: d807 bhi.n 8004bbc <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x67c>
- 8004bac: eb08 0109 add.w r1, r8, r9
- 8004bb0: f1c9 0245 rsb r2, r9, #69 ; 0x45
- 8004bb4: f104 008c add.w r0, r4, #140 ; 0x8c
- 8004bb8: f005 f8d8 bl 8009d6c <memcpy>
- 8004bbc: 6860 ldr r0, [r4, #4]
- 8004bbe: 6f43 ldr r3, [r0, #116] ; 0x74
- 8004bc0: 2b20 cmp r3, #32
- 8004bc2: f47f adae bne.w 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 8004bc6: 4e16 ldr r6, [pc, #88] ; (8004c20 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x6e0>)
- 8004bc8: 7833 ldrb r3, [r6, #0]
- 8004bca: 2b00 cmp r3, #0
- 8004bcc: f47f ada9 bne.w 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 8004bd0: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 8004bd4: 2201 movs r2, #1
- 8004bd6: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8004bda: 7032 strb r2, [r6, #0]
- 8004bdc: 4299 cmp r1, r3
- 8004bde: f43f aec1 beq.w 8004964 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x424>
- 8004be2: b29a uxth r2, r3
- 8004be4: f103 0388 add.w r3, r3, #136 ; 0x88
- 8004be8: bf8c ite hi
- 8004bea: 1a8a subhi r2, r1, r2
- 8004bec: f5c2 7280 rsbls r2, r2, #256 ; 0x100
- 8004bf0: 18f9 adds r1, r7, r3
- 8004bf2: fa1f f882 uxth.w r8, r2
- 8004bf6: 4642 mov r2, r8
- 8004bf8: f003 f8da bl 8007db0 <HAL_UART_Transmit_DMA>
- 8004bfc: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8004c00: 4443 add r3, r8
- 8004c02: b2db uxtb r3, r3
- 8004c04: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 8004c08: e6ac b.n 8004964 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x424>
- 8004c0a: aa05 add r2, sp, #20
- 8004c0c: 2107 movs r1, #7
- 8004c0e: 4620 mov r0, r4
- 8004c10: 4798 blx r3
- 8004c12: e586 b.n 8004722 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x1e2>
- 8004c14: aa05 add r2, sp, #20
- 8004c16: 2107 movs r1, #7
- 8004c18: 4620 mov r0, r4
- 8004c1a: 4798 blx r3
- 8004c1c: e67b b.n 8004916 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv+0x3d6>
- 8004c1e: bf00 nop
- 8004c20: 2000009c .word 0x2000009c
- 8004c24: 0800a380 .word 0x0800a380
- 8004c28: 0800a010 .word 0x0800a010
- 8004c2c: 080032d9 .word 0x080032d9
- 8004c30: 003dfeff .word 0x003dfeff
-
-08004c34 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv>:
- 8004c34: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 8004c38: 4604 mov r4, r0
- 8004c3a: b089 sub sp, #36 ; 0x24
- 8004c3c: f001 fa8a bl 8006154 <HAL_GetTick>
- 8004c40: f642 22f8 movw r2, #11000 ; 0x2af8
- 8004c44: f8d4 3688 ldr.w r3, [r4, #1672] ; 0x688
- 8004c48: 4605 mov r5, r0
- 8004c4a: 1ac3 subs r3, r0, r3
- 8004c4c: 4293 cmp r3, r2
- 8004c4e: d902 bls.n 8004c56 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x22>
- 8004c50: 2300 movs r3, #0
- 8004c52: f884 3680 strb.w r3, [r4, #1664] ; 0x680
- 8004c56: f8d4 366c ldr.w r3, [r4, #1644] ; 0x66c
- 8004c5a: b133 cbz r3, 8004c6a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x36>
- 8004c5c: f8d4 368c ldr.w r3, [r4, #1676] ; 0x68c
- 8004c60: 42ab cmp r3, r5
- 8004c62: d202 bcs.n 8004c6a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x36>
- 8004c64: 2300 movs r3, #0
- 8004c66: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 8004c6a: f8d4 11a0 ldr.w r1, [r4, #416] ; 0x1a0
- 8004c6e: f8df b438 ldr.w fp, [pc, #1080] ; 80050a8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x474>
- 8004c72: f8df a438 ldr.w sl, [pc, #1080] ; 80050ac <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x478>
- 8004c76: bb39 cbnz r1, 8004cc8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x94>
- 8004c78: 6862 ldr r2, [r4, #4]
- 8004c7a: f8d4 3088 ldr.w r3, [r4, #136] ; 0x88
- 8004c7e: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 8004c80: 6812 ldr r2, [r2, #0]
- 8004c82: 6852 ldr r2, [r2, #4]
- 8004c84: 4252 negs r2, r2
- 8004c86: f002 027f and.w r2, r2, #127 ; 0x7f
- 8004c8a: 4293 cmp r3, r2
- 8004c8c: f000 80e1 beq.w 8004e52 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x21e>
- 8004c90: 18e0 adds r0, r4, r3
- 8004c92: f8d4 267c ldr.w r2, [r4, #1660] ; 0x67c
- 8004c96: 3301 adds r3, #1
- 8004c98: f8d4 666c ldr.w r6, [r4, #1644] ; 0x66c
- 8004c9c: 7a00 ldrb r0, [r0, #8]
- 8004c9e: f003 037f and.w r3, r3, #127 ; 0x7f
- 8004ca2: 2e07 cmp r6, #7
- 8004ca4: 4402 add r2, r0
- 8004ca6: f8c4 3088 str.w r3, [r4, #136] ; 0x88
- 8004caa: f8c4 267c str.w r2, [r4, #1660] ; 0x67c
- 8004cae: d017 beq.n 8004ce0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0xac>
- 8004cb0: bb5e cbnz r6, 8004d0a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0xd6>
- 8004cb2: 28ff cmp r0, #255 ; 0xff
- 8004cb4: d163 bne.n 8004d7e <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x14a>
- 8004cb6: 2201 movs r2, #1
- 8004cb8: f105 0314 add.w r3, r5, #20
- 8004cbc: f8c4 266c str.w r2, [r4, #1644] ; 0x66c
- 8004cc0: f8c4 368c str.w r3, [r4, #1676] ; 0x68c
- 8004cc4: 2900 cmp r1, #0
- 8004cc6: d0d7 beq.n 8004c78 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x44>
- 8004cc8: f001 fa44 bl 8006154 <HAL_GetTick>
- 8004ccc: f8d4 11a0 ldr.w r1, [r4, #416] ; 0x1a0
- 8004cd0: 1b40 subs r0, r0, r5
- 8004cd2: 4288 cmp r0, r1
- 8004cd4: d9d0 bls.n 8004c78 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x44>
- 8004cd6: f06f 0001 mvn.w r0, #1
- 8004cda: b009 add sp, #36 ; 0x24
- 8004cdc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 8004ce0: f8d4 3678 ldr.w r3, [r4, #1656] ; 0x678
- 8004ce4: 1c5a adds r2, r3, #1
- 8004ce6: 4423 add r3, r4
- 8004ce8: f8c4 2678 str.w r2, [r4, #1656] ; 0x678
- 8004cec: f883 01a4 strb.w r0, [r3, #420] ; 0x1a4
- 8004cf0: f8d4 3670 ldr.w r3, [r4, #1648] ; 0x670
- 8004cf4: 3b01 subs r3, #1
- 8004cf6: f8c4 3670 str.w r3, [r4, #1648] ; 0x670
- 8004cfa: 2b00 cmp r3, #0
- 8004cfc: d13c bne.n 8004d78 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x144>
- 8004cfe: f8d4 11a0 ldr.w r1, [r4, #416] ; 0x1a0
- 8004d02: 2308 movs r3, #8
- 8004d04: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 8004d08: e7b5 b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004d0a: 2e01 cmp r6, #1
- 8004d0c: d045 beq.n 8004d9a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x166>
- 8004d0e: 2e02 cmp r6, #2
- 8004d10: f000 808a beq.w 8004e28 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x1f4>
- 8004d14: 2e03 cmp r6, #3
- 8004d16: f000 8092 beq.w 8004e3e <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x20a>
- 8004d1a: 2e04 cmp r6, #4
- 8004d1c: f000 80ad beq.w 8004e7a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x246>
- 8004d20: 2e05 cmp r6, #5
- 8004d22: f000 80c5 beq.w 8004eb0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x27c>
- 8004d26: 2e06 cmp r6, #6
- 8004d28: f000 80b3 beq.w 8004e92 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x25e>
- 8004d2c: 2e08 cmp r6, #8
- 8004d2e: d1a2 bne.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004d30: 4253 negs r3, r2
- 8004d32: b2d2 uxtb r2, r2
- 8004d34: f04f 0000 mov.w r0, #0
- 8004d38: b2db uxtb r3, r3
- 8004d3a: f8c4 066c str.w r0, [r4, #1644] ; 0x66c
- 8004d3e: bf58 it pl
- 8004d40: 425a negpl r2, r3
- 8004d42: 2aff cmp r2, #255 ; 0xff
- 8004d44: d197 bne.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004d46: f8d4 3674 ldr.w r3, [r4, #1652] ; 0x674
- 8004d4a: 2b00 cmp r3, #0
- 8004d4c: f000 82ae beq.w 80052ac <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x678>
- 8004d50: 2b0a cmp r3, #10
- 8004d52: f000 8136 beq.w 8004fc2 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x38e>
- 8004d56: 2b06 cmp r3, #6
- 8004d58: f000 81aa beq.w 80050b0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x47c>
- 8004d5c: 2b0b cmp r3, #11
- 8004d5e: f000 8198 beq.w 8005092 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x45e>
- 8004d62: f503 738f add.w r3, r3, #286 ; 0x11e
- 8004d66: f854 0023 ldr.w r0, [r4, r3, lsl #2]
- 8004d6a: 2800 cmp r0, #0
- 8004d6c: d083 beq.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004d6e: 6803 ldr r3, [r0, #0]
- 8004d70: f504 71d2 add.w r1, r4, #420 ; 0x1a4
- 8004d74: 681b ldr r3, [r3, #0]
- 8004d76: 4798 blx r3
- 8004d78: f8d4 11a0 ldr.w r1, [r4, #416] ; 0x1a0
- 8004d7c: e77b b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004d7e: f001 f9e9 bl 8006154 <HAL_GetTick>
- 8004d82: f241 3388 movw r3, #5000 ; 0x1388
- 8004d86: 1b40 subs r0, r0, r5
- 8004d88: 4298 cmp r0, r3
- 8004d8a: d9f5 bls.n 8004d78 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x144>
- 8004d8c: f06f 0001 mvn.w r0, #1
- 8004d90: f884 6680 strb.w r6, [r4, #1664] ; 0x680
- 8004d94: b009 add sp, #36 ; 0x24
- 8004d96: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 8004d9a: 28fe cmp r0, #254 ; 0xfe
- 8004d9c: d069 beq.n 8004e72 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x23e>
- 8004d9e: 2200 movs r2, #0
- 8004da0: f894 3680 ldrb.w r3, [r4, #1664] ; 0x680
- 8004da4: f8c4 266c str.w r2, [r4, #1644] ; 0x66c
- 8004da8: 2b00 cmp r3, #0
- 8004daa: f47f af64 bne.w 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004dae: 6822 ldr r2, [r4, #0]
- 8004db0: 49b9 ldr r1, [pc, #740] ; (8005098 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x464>)
- 8004db2: 6816 ldr r6, [r2, #0]
- 8004db4: 4ab9 ldr r2, [pc, #740] ; (800509c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x468>)
- 8004db6: 9105 str r1, [sp, #20]
- 8004db8: 4296 cmp r6, r2
- 8004dba: e9cd 3306 strd r3, r3, [sp, #24]
- 8004dbe: f040 80fb bne.w 8004fb8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x384>
- 8004dc2: f8d4 018c ldr.w r0, [r4, #396] ; 0x18c
- 8004dc6: f640 2cf7 movw ip, #2807 ; 0xaf7
- 8004dca: 4ab5 ldr r2, [pc, #724] ; (80050a0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x46c>)
- 8004dcc: f04f 4175 mov.w r1, #4110417920 ; 0xf5000000
- 8004dd0: f5c0 7680 rsb r6, r0, #256 ; 0x100
- 8004dd4: 1d27 adds r7, r4, #4
- 8004dd6: 3088 adds r0, #136 ; 0x88
- 8004dd8: f504 7969 add.w r9, r4, #932 ; 0x3a4
- 8004ddc: 2e10 cmp r6, #16
- 8004dde: 46b0 mov r8, r6
- 8004de0: f8c4 33ac str.w r3, [r4, #940] ; 0x3ac
- 8004de4: 4438 add r0, r7
- 8004de6: bf28 it cs
- 8004de8: f04f 0810 movcs.w r8, #16
- 8004dec: f8c4 23a4 str.w r2, [r4, #932] ; 0x3a4
- 8004df0: f8c4 13b0 str.w r1, [r4, #944] ; 0x3b0
- 8004df4: 4649 mov r1, r9
- 8004df6: 4642 mov r2, r8
- 8004df8: f8c4 c3a8 str.w ip, [r4, #936] ; 0x3a8
- 8004dfc: f004 ffb6 bl 8009d6c <memcpy>
- 8004e00: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8004e04: 2e0f cmp r6, #15
- 8004e06: f103 0310 add.w r3, r3, #16
- 8004e0a: b2db uxtb r3, r3
- 8004e0c: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 8004e10: d956 bls.n 8004ec0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x28c>
- 8004e12: 6860 ldr r0, [r4, #4]
- 8004e14: 6f43 ldr r3, [r0, #116] ; 0x74
- 8004e16: 2b20 cmp r3, #32
- 8004e18: d05e beq.n 8004ed8 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x2a4>
- 8004e1a: f001 f99b bl 8006154 <HAL_GetTick>
- 8004e1e: f8d4 11a0 ldr.w r1, [r4, #416] ; 0x1a0
- 8004e22: f8c4 0194 str.w r0, [r4, #404] ; 0x194
- 8004e26: e726 b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004e28: 2200 movs r2, #0
- 8004e2a: 2303 movs r3, #3
- 8004e2c: f8c4 0670 str.w r0, [r4, #1648] ; 0x670
- 8004e30: f8c4 067c str.w r0, [r4, #1660] ; 0x67c
- 8004e34: f8c4 2678 str.w r2, [r4, #1656] ; 0x678
- 8004e38: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 8004e3c: e71b b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004e3e: f8d4 3670 ldr.w r3, [r4, #1648] ; 0x670
- 8004e42: 2204 movs r2, #4
- 8004e44: eb03 2000 add.w r0, r3, r0, lsl #8
- 8004e48: f8c4 266c str.w r2, [r4, #1644] ; 0x66c
- 8004e4c: f8c4 0670 str.w r0, [r4, #1648] ; 0x670
- 8004e50: e711 b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004e52: f894 0680 ldrb.w r0, [r4, #1664] ; 0x680
- 8004e56: 2800 cmp r0, #0
- 8004e58: f43f af3f beq.w 8004cda <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0xa6>
- 8004e5c: f8d4 3684 ldr.w r3, [r4, #1668] ; 0x684
- 8004e60: f640 12c4 movw r2, #2500 ; 0x9c4
- 8004e64: 1aeb subs r3, r5, r3
- 8004e66: 4293 cmp r3, r2
- 8004e68: d858 bhi.n 8004f1c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x2e8>
- 8004e6a: 2000 movs r0, #0
- 8004e6c: b009 add sp, #36 ; 0x24
- 8004e6e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 8004e72: 2302 movs r3, #2
- 8004e74: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 8004e78: e6fd b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004e7a: 4253 negs r3, r2
- 8004e7c: b2d2 uxtb r2, r2
- 8004e7e: b2db uxtb r3, r3
- 8004e80: bf58 it pl
- 8004e82: 425a negpl r2, r3
- 8004e84: 2aff cmp r2, #255 ; 0xff
- 8004e86: bf0c ite eq
- 8004e88: 2305 moveq r3, #5
- 8004e8a: 2300 movne r3, #0
- 8004e8c: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 8004e90: e6f1 b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004e92: f8d4 3674 ldr.w r3, [r4, #1652] ; 0x674
- 8004e96: 2607 movs r6, #7
- 8004e98: f8d4 2670 ldr.w r2, [r4, #1648] ; 0x670
- 8004e9c: eb03 2300 add.w r3, r3, r0, lsl #8
- 8004ea0: f8c4 666c str.w r6, [r4, #1644] ; 0x66c
- 8004ea4: f8c4 3674 str.w r3, [r4, #1652] ; 0x674
- 8004ea8: 2a00 cmp r2, #0
- 8004eaa: f43f af2a beq.w 8004d02 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0xce>
- 8004eae: e6e2 b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004eb0: 2306 movs r3, #6
- 8004eb2: f8c4 0674 str.w r0, [r4, #1652] ; 0x674
- 8004eb6: f8c4 067c str.w r0, [r4, #1660] ; 0x67c
- 8004eba: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 8004ebe: e6da b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8004ec0: eb09 0108 add.w r1, r9, r8
- 8004ec4: f1c8 0210 rsb r2, r8, #16
- 8004ec8: f104 008c add.w r0, r4, #140 ; 0x8c
- 8004ecc: f004 ff4e bl 8009d6c <memcpy>
- 8004ed0: 6860 ldr r0, [r4, #4]
- 8004ed2: 6f43 ldr r3, [r0, #116] ; 0x74
- 8004ed4: 2b20 cmp r3, #32
- 8004ed6: d1a0 bne.n 8004e1a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x1e6>
- 8004ed8: 4e72 ldr r6, [pc, #456] ; (80050a4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x470>)
- 8004eda: 7833 ldrb r3, [r6, #0]
- 8004edc: 2b00 cmp r3, #0
- 8004ede: d19c bne.n 8004e1a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x1e6>
- 8004ee0: f8d4 218c ldr.w r2, [r4, #396] ; 0x18c
- 8004ee4: 2101 movs r1, #1
- 8004ee6: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8004eea: 7031 strb r1, [r6, #0]
- 8004eec: 429a cmp r2, r3
- 8004eee: d012 beq.n 8004f16 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x2e2>
- 8004ef0: fa1f f883 uxth.w r8, r3
- 8004ef4: f240 80c8 bls.w 8005088 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x454>
- 8004ef8: eba2 0208 sub.w r2, r2, r8
- 8004efc: fa1f f882 uxth.w r8, r2
- 8004f00: 3388 adds r3, #136 ; 0x88
- 8004f02: 4642 mov r2, r8
- 8004f04: 18f9 adds r1, r7, r3
- 8004f06: f002 ff53 bl 8007db0 <HAL_UART_Transmit_DMA>
- 8004f0a: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8004f0e: 4443 add r3, r8
- 8004f10: b2db uxtb r3, r3
- 8004f12: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 8004f16: 2300 movs r3, #0
- 8004f18: 7033 strb r3, [r6, #0]
- 8004f1a: e77e b.n 8004e1a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x1e6>
- 8004f1c: 6822 ldr r2, [r4, #0]
- 8004f1e: 2300 movs r3, #0
- 8004f20: 495d ldr r1, [pc, #372] ; (8005098 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x464>)
- 8004f22: 6816 ldr r6, [r2, #0]
- 8004f24: 4a5d ldr r2, [pc, #372] ; (800509c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x468>)
- 8004f26: 9307 str r3, [sp, #28]
- 8004f28: 4296 cmp r6, r2
- 8004f2a: e9cd 1305 strd r1, r3, [sp, #20]
- 8004f2e: f040 80a6 bne.w 800507e <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x44a>
- 8004f32: f8d4 018c ldr.w r0, [r4, #396] ; 0x18c
- 8004f36: f640 21f7 movw r1, #2807 ; 0xaf7
- 8004f3a: f8df e164 ldr.w lr, [pc, #356] ; 80050a0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x46c>
- 8004f3e: f06f 0c0a mvn.w ip, #10
- 8004f42: f5c0 7780 rsb r7, r0, #256 ; 0x100
- 8004f46: 1d26 adds r6, r4, #4
- 8004f48: 3088 adds r0, #136 ; 0x88
- 8004f4a: f504 7969 add.w r9, r4, #932 ; 0x3a4
- 8004f4e: 2f10 cmp r7, #16
- 8004f50: 46b8 mov r8, r7
- 8004f52: f8c4 33ac str.w r3, [r4, #940] ; 0x3ac
- 8004f56: 4430 add r0, r6
- 8004f58: bf28 it cs
- 8004f5a: f04f 0810 movcs.w r8, #16
- 8004f5e: f8a4 33b0 strh.w r3, [r4, #944] ; 0x3b0
- 8004f62: f884 33b2 strb.w r3, [r4, #946] ; 0x3b2
- 8004f66: f8c4 13a8 str.w r1, [r4, #936] ; 0x3a8
- 8004f6a: 4642 mov r2, r8
- 8004f6c: f8c4 e3a4 str.w lr, [r4, #932] ; 0x3a4
- 8004f70: 4649 mov r1, r9
- 8004f72: f884 c3b3 strb.w ip, [r4, #947] ; 0x3b3
- 8004f76: f004 fef9 bl 8009d6c <memcpy>
- 8004f7a: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8004f7e: 2f0f cmp r7, #15
- 8004f80: f103 0310 add.w r3, r3, #16
- 8004f84: b2db uxtb r3, r3
- 8004f86: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 8004f8a: d807 bhi.n 8004f9c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x368>
- 8004f8c: eb09 0108 add.w r1, r9, r8
- 8004f90: f1c8 0210 rsb r2, r8, #16
- 8004f94: f104 008c add.w r0, r4, #140 ; 0x8c
- 8004f98: f004 fee8 bl 8009d6c <memcpy>
- 8004f9c: 6860 ldr r0, [r4, #4]
- 8004f9e: 6f43 ldr r3, [r0, #116] ; 0x74
- 8004fa0: 2b20 cmp r3, #32
- 8004fa2: d047 beq.n 8005034 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x400>
- 8004fa4: f001 f8d6 bl 8006154 <HAL_GetTick>
- 8004fa8: f8c4 0194 str.w r0, [r4, #404] ; 0x194
- 8004fac: 2000 movs r0, #0
- 8004fae: f8c4 5684 str.w r5, [r4, #1668] ; 0x684
- 8004fb2: b009 add sp, #36 ; 0x24
- 8004fb4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 8004fb8: aa05 add r2, sp, #20
- 8004fba: 210a movs r1, #10
- 8004fbc: 4620 mov r0, r4
- 8004fbe: 47b0 blx r6
- 8004fc0: e72b b.n 8004e1a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x1e6>
- 8004fc2: f001 f8c7 bl 8006154 <HAL_GetTick>
- 8004fc6: f8d4 6194 ldr.w r6, [r4, #404] ; 0x194
- 8004fca: f8d4 31a4 ldr.w r3, [r4, #420] ; 0x1a4
- 8004fce: 1b86 subs r6, r0, r6
- 8004fd0: f8d4 71a8 ldr.w r7, [r4, #424] ; 0x1a8
- 8004fd4: f103 38ff add.w r8, r3, #4294967295 ; 0xffffffff
- 8004fd8: f001 f8bc bl 8006154 <HAL_GetTick>
- 8004fdc: f107 576e add.w r7, r7, #998244352 ; 0x3b800000
- 8004fe0: 4601 mov r1, r0
- 8004fe2: fbab 2306 umull r2, r3, fp, r6
- 8004fe6: f44f 727a mov.w r2, #1000 ; 0x3e8
- 8004fea: fbab ec01 umull lr, ip, fp, r1
- 8004fee: f507 17d6 add.w r7, r7, #1753088 ; 0x1ac000
- 8004ff2: 099b lsrs r3, r3, #6
- 8004ff4: f504 70cc add.w r0, r4, #408 ; 0x198
- 8004ff8: ea4f 1c9c mov.w ip, ip, lsr #6
- 8004ffc: f507 6720 add.w r7, r7, #2560 ; 0xa00
- 8005000: fb02 6613 mls r6, r2, r3, r6
- 8005004: 4443 add r3, r8
- 8005006: fb02 121c mls r2, r2, ip, r1
- 800500a: f504 71ce add.w r1, r4, #412 ; 0x19c
- 800500e: fb0a 7606 mla r6, sl, r6, r7
- 8005012: eba3 030c sub.w r3, r3, ip
- 8005016: fb0a 6212 mls r2, sl, r2, r6
- 800501a: f8c4 3198 str.w r3, [r4, #408] ; 0x198
- 800501e: f8c4 219c str.w r2, [r4, #412] ; 0x19c
- 8005022: f001 f81d bl 8006060 <_ZN3ros16normalizeSecNSecERmS0_>
- 8005026: f001 f895 bl 8006154 <HAL_GetTick>
- 800502a: f8d4 11a0 ldr.w r1, [r4, #416] ; 0x1a0
- 800502e: f8c4 0688 str.w r0, [r4, #1672] ; 0x688
- 8005032: e620 b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8005034: f8df 806c ldr.w r8, [pc, #108] ; 80050a4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x470>
- 8005038: f898 3000 ldrb.w r3, [r8]
- 800503c: 2b00 cmp r3, #0
- 800503e: d1b1 bne.n 8004fa4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x370>
- 8005040: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 8005044: 2301 movs r3, #1
- 8005046: f8d4 2190 ldr.w r2, [r4, #400] ; 0x190
- 800504a: f888 3000 strb.w r3, [r8]
- 800504e: 4291 cmp r1, r2
- 8005050: d011 beq.n 8005076 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x442>
- 8005052: b293 uxth r3, r2
- 8005054: bf8c ite hi
- 8005056: 1acb subhi r3, r1, r3
- 8005058: f5c3 7380 rsbls r3, r3, #256 ; 0x100
- 800505c: f102 0188 add.w r1, r2, #136 ; 0x88
- 8005060: b29f uxth r7, r3
- 8005062: 4431 add r1, r6
- 8005064: 463a mov r2, r7
- 8005066: f002 fea3 bl 8007db0 <HAL_UART_Transmit_DMA>
- 800506a: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 800506e: 443b add r3, r7
- 8005070: b2db uxtb r3, r3
- 8005072: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 8005076: 2300 movs r3, #0
- 8005078: f888 3000 strb.w r3, [r8]
- 800507c: e792 b.n 8004fa4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x370>
- 800507e: aa05 add r2, sp, #20
- 8005080: 210a movs r1, #10
- 8005082: 4620 mov r0, r4
- 8005084: 47b0 blx r6
- 8005086: e78d b.n 8004fa4 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x370>
- 8005088: f5c8 7880 rsb r8, r8, #256 ; 0x100
- 800508c: fa1f f888 uxth.w r8, r8
- 8005090: e736 b.n 8004f00 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x2cc>
- 8005092: f884 0680 strb.w r0, [r4, #1664] ; 0x680
- 8005096: e5ee b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 8005098: 08009fe0 .word 0x08009fe0
- 800509c: 080032d9 .word 0x080032d9
- 80050a0: 0008feff .word 0x0008feff
- 80050a4: 2000009c .word 0x2000009c
- 80050a8: 10624dd3 .word 0x10624dd3
- 80050ac: 000f4240 .word 0x000f4240
- 80050b0: f8d4 71a4 ldr.w r7, [r4, #420] ; 0x1a4
- 80050b4: f504 78d2 add.w r8, r4, #420 ; 0x1a4
- 80050b8: f8d4 3698 ldr.w r3, [r4, #1688] ; 0x698
- 80050bc: 429f cmp r7, r3
- 80050be: d906 bls.n 80050ce <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x49a>
- 80050c0: 00b9 lsls r1, r7, #2
- 80050c2: f8d4 06a0 ldr.w r0, [r4, #1696] ; 0x6a0
- 80050c6: f004 fe7d bl 8009dc4 <realloc>
- 80050ca: f8c4 06a0 str.w r0, [r4, #1696] ; 0x6a0
- 80050ce: f8c4 7698 str.w r7, [r4, #1688] ; 0x698
- 80050d2: 2f00 cmp r7, #0
- 80050d4: f000 80db beq.w 800528e <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x65a>
- 80050d8: 4640 mov r0, r8
- 80050da: f04f 0e04 mov.w lr, #4
- 80050de: 2600 movs r6, #0
- 80050e0: 7983 ldrb r3, [r0, #6]
- 80050e2: f10e 0c04 add.w ip, lr, #4
- 80050e6: 7941 ldrb r1, [r0, #5]
- 80050e8: 4677 mov r7, lr
- 80050ea: 041b lsls r3, r3, #16
- 80050ec: 7902 ldrb r2, [r0, #4]
- 80050ee: 46e6 mov lr, ip
- 80050f0: 3004 adds r0, #4
- 80050f2: ea43 2301 orr.w r3, r3, r1, lsl #8
- 80050f6: 78c1 ldrb r1, [r0, #3]
- 80050f8: 4313 orrs r3, r2
- 80050fa: f8d4 26a0 ldr.w r2, [r4, #1696] ; 0x6a0
- 80050fe: ea43 6301 orr.w r3, r3, r1, lsl #24
- 8005102: f8c4 369c str.w r3, [r4, #1692] ; 0x69c
- 8005106: f842 3026 str.w r3, [r2, r6, lsl #2]
- 800510a: 3601 adds r6, #1
- 800510c: f8d4 3698 ldr.w r3, [r4, #1688] ; 0x698
- 8005110: 42b3 cmp r3, r6
- 8005112: d8e5 bhi.n 80050e0 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x4ac>
- 8005114: f107 0209 add.w r2, r7, #9
- 8005118: f107 0308 add.w r3, r7, #8
- 800511c: f107 010b add.w r1, r7, #11
- 8005120: 1d78 adds r0, r7, #5
- 8005122: f107 0e06 add.w lr, r7, #6
- 8005126: f107 0907 add.w r9, r7, #7
- 800512a: 9200 str r2, [sp, #0]
- 800512c: 461e mov r6, r3
- 800512e: f107 020a add.w r2, r7, #10
- 8005132: 370c adds r7, #12
- 8005134: 9101 str r1, [sp, #4]
- 8005136: f818 100e ldrb.w r1, [r8, lr]
- 800513a: f818 0000 ldrb.w r0, [r8, r0]
- 800513e: 0409 lsls r1, r1, #16
- 8005140: f818 e00c ldrb.w lr, [r8, ip]
- 8005144: f818 c009 ldrb.w ip, [r8, r9]
- 8005148: ea41 2100 orr.w r1, r1, r0, lsl #8
- 800514c: f8d4 06a4 ldr.w r0, [r4, #1700] ; 0x6a4
- 8005150: ea41 0e0e orr.w lr, r1, lr
- 8005154: ea4e 690c orr.w r9, lr, ip, lsl #24
- 8005158: 4581 cmp r9, r0
- 800515a: d90b bls.n 8005174 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x540>
- 800515c: ea4f 0189 mov.w r1, r9, lsl #2
- 8005160: f8d4 06ac ldr.w r0, [r4, #1708] ; 0x6ac
- 8005164: e9cd 3202 strd r3, r2, [sp, #8]
- 8005168: f004 fe2c bl 8009dc4 <realloc>
- 800516c: f8c4 06ac str.w r0, [r4, #1708] ; 0x6ac
- 8005170: e9dd 3202 ldrd r3, r2, [sp, #8]
- 8005174: f8c4 96a4 str.w r9, [r4, #1700] ; 0x6a4
- 8005178: f1b9 0f00 cmp.w r9, #0
- 800517c: d026 beq.n 80051cc <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x598>
- 800517e: eb08 0106 add.w r1, r8, r6
- 8005182: 2000 movs r0, #0
- 8005184: f204 6c94 addw ip, r4, #1684 ; 0x694
- 8005188: 788a ldrb r2, [r1, #2]
- 800518a: 1d33 adds r3, r6, #4
- 800518c: f891 9001 ldrb.w r9, [r1, #1]
- 8005190: 4637 mov r7, r6
- 8005192: 0412 lsls r2, r2, #16
- 8005194: f891 e000 ldrb.w lr, [r1]
- 8005198: 78ce ldrb r6, [r1, #3]
- 800519a: 3104 adds r1, #4
- 800519c: ea42 2209 orr.w r2, r2, r9, lsl #8
- 80051a0: ea42 020e orr.w r2, r2, lr
- 80051a4: f8d4 e6ac ldr.w lr, [r4, #1708] ; 0x6ac
- 80051a8: ea42 6206 orr.w r2, r2, r6, lsl #24
- 80051ac: 461e mov r6, r3
- 80051ae: f8cc 2014 str.w r2, [ip, #20]
- 80051b2: f84e 2020 str.w r2, [lr, r0, lsl #2]
- 80051b6: 3001 adds r0, #1
- 80051b8: f8d4 26a4 ldr.w r2, [r4, #1700] ; 0x6a4
- 80051bc: 4282 cmp r2, r0
- 80051be: d8e3 bhi.n 8005188 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x554>
- 80051c0: 1d7a adds r2, r7, #5
- 80051c2: 1df9 adds r1, r7, #7
- 80051c4: 9200 str r2, [sp, #0]
- 80051c6: 1dba adds r2, r7, #6
- 80051c8: 3708 adds r7, #8
- 80051ca: 9101 str r1, [sp, #4]
- 80051cc: f818 6002 ldrb.w r6, [r8, r2]
- 80051d0: 9a00 ldr r2, [sp, #0]
- 80051d2: 0436 lsls r6, r6, #16
- 80051d4: f818 1003 ldrb.w r1, [r8, r3]
- 80051d8: f818 0002 ldrb.w r0, [r8, r2]
- 80051dc: 9b01 ldr r3, [sp, #4]
- 80051de: ea46 2600 orr.w r6, r6, r0, lsl #8
- 80051e2: f818 2003 ldrb.w r2, [r8, r3]
- 80051e6: 430e orrs r6, r1
- 80051e8: f8d4 36b0 ldr.w r3, [r4, #1712] ; 0x6b0
- 80051ec: ea46 6602 orr.w r6, r6, r2, lsl #24
- 80051f0: 429e cmp r6, r3
- 80051f2: d906 bls.n 8005202 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x5ce>
- 80051f4: 00b1 lsls r1, r6, #2
- 80051f6: f8d4 06b8 ldr.w r0, [r4, #1720] ; 0x6b8
- 80051fa: f004 fde3 bl 8009dc4 <realloc>
- 80051fe: f8c4 06b8 str.w r0, [r4, #1720] ; 0x6b8
- 8005202: f8c4 66b0 str.w r6, [r4, #1712] ; 0x6b0
- 8005206: 2e00 cmp r6, #0
- 8005208: d03b beq.n 8005282 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x64e>
- 800520a: f04f 0900 mov.w r9, #0
- 800520e: 9500 str r5, [sp, #0]
- 8005210: eb08 0507 add.w r5, r8, r7
- 8005214: f818 e007 ldrb.w lr, [r8, r7]
- 8005218: f06f 0c03 mvn.w ip, #3
- 800521c: f507 71d4 add.w r1, r7, #424 ; 0x1a8
- 8005220: 78ab ldrb r3, [r5, #2]
- 8005222: f207 10a7 addw r0, r7, #423 ; 0x1a7
- 8005226: 786e ldrb r6, [r5, #1]
- 8005228: ebac 0c07 sub.w ip, ip, r7
- 800522c: 041b lsls r3, r3, #16
- 800522e: 78ed ldrb r5, [r5, #3]
- 8005230: 1d7a adds r2, r7, #5
- 8005232: 4421 add r1, r4
- 8005234: ea43 2306 orr.w r3, r3, r6, lsl #8
- 8005238: 1d3e adds r6, r7, #4
- 800523a: 4420 add r0, r4
- 800523c: ea43 030e orr.w r3, r3, lr
- 8005240: ea43 6505 orr.w r5, r3, r5, lsl #24
- 8005244: 4435 add r5, r6
- 8005246: 42b5 cmp r5, r6
- 8005248: 44ac add ip, r5
- 800524a: 462f mov r7, r5
- 800524c: d905 bls.n 800525a <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x626>
- 800524e: 4295 cmp r5, r2
- 8005250: bf2c ite cs
- 8005252: 4662 movcs r2, ip
- 8005254: 2201 movcc r2, #1
- 8005256: f004 fd94 bl 8009d82 <memmove>
- 800525a: f04f 0200 mov.w r2, #0
- 800525e: 4445 add r5, r8
- 8005260: 1e73 subs r3, r6, #1
- 8005262: f805 2c01 strb.w r2, [r5, #-1]
- 8005266: 4443 add r3, r8
- 8005268: f8d4 26b8 ldr.w r2, [r4, #1720] ; 0x6b8
- 800526c: f8c4 36b4 str.w r3, [r4, #1716] ; 0x6b4
- 8005270: f842 3029 str.w r3, [r2, r9, lsl #2]
- 8005274: f109 0901 add.w r9, r9, #1
- 8005278: f8d4 36b0 ldr.w r3, [r4, #1712] ; 0x6b0
- 800527c: 454b cmp r3, r9
- 800527e: d8c7 bhi.n 8005210 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x5dc>
- 8005280: 9d00 ldr r5, [sp, #0]
- 8005282: 2301 movs r3, #1
- 8005284: f8d4 11a0 ldr.w r1, [r4, #416] ; 0x1a0
- 8005288: f884 3690 strb.w r3, [r4, #1680] ; 0x690
- 800528c: e4f3 b.n 8004c76 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x42>
- 800528e: 230b movs r3, #11
- 8005290: 270c movs r7, #12
- 8005292: 220a movs r2, #10
- 8005294: f04f 0907 mov.w r9, #7
- 8005298: 9301 str r3, [sp, #4]
- 800529a: 2309 movs r3, #9
- 800529c: f04f 0e06 mov.w lr, #6
- 80052a0: 2005 movs r0, #5
- 80052a2: 9300 str r3, [sp, #0]
- 80052a4: f04f 0c04 mov.w ip, #4
- 80052a8: 2308 movs r3, #8
- 80052aa: e744 b.n 8005136 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0x502>
- 80052ac: 4620 mov r0, r4
- 80052ae: f7ff f8bd bl 800442c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv>
- 80052b2: 4620 mov r0, r4
- 80052b4: f7ff f944 bl 8004540 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv>
- 80052b8: f8c4 5684 str.w r5, [r4, #1668] ; 0x684
- 80052bc: f8c4 5688 str.w r5, [r4, #1672] ; 0x688
- 80052c0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 80052c4: e509 b.n 8004cda <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE8spinOnceEv+0xa6>
- 80052c6: bf00 nop
-
-080052c8 <HAL_TIM_PeriodElapsedCallback>:
- 80052c8: 6802 ldr r2, [r0, #0]
- 80052ca: 4bc8 ldr r3, [pc, #800] ; (80055ec <HAL_TIM_PeriodElapsedCallback+0x324>)
- 80052cc: 429a cmp r2, r3
- 80052ce: d000 beq.n 80052d2 <HAL_TIM_PeriodElapsedCallback+0xa>
- 80052d0: 4770 bx lr
- 80052d2: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 80052d6: 48c6 ldr r0, [pc, #792] ; (80055f0 <HAL_TIM_PeriodElapsedCallback+0x328>)
- 80052d8: b085 sub sp, #20
- 80052da: f7fb f957 bl 800058c <_ZN7Encoder17GetLinearVelocityEv>
- 80052de: 4bc5 ldr r3, [pc, #788] ; (80055f4 <HAL_TIM_PeriodElapsedCallback+0x32c>)
- 80052e0: 48c5 ldr r0, [pc, #788] ; (80055f8 <HAL_TIM_PeriodElapsedCallback+0x330>)
- 80052e2: ed83 0a00 vstr s0, [r3]
- 80052e6: f7fb f951 bl 800058c <_ZN7Encoder17GetLinearVelocityEv>
- 80052ea: 4bc4 ldr r3, [pc, #784] ; (80055fc <HAL_TIM_PeriodElapsedCallback+0x334>)
- 80052ec: 4dc4 ldr r5, [pc, #784] ; (8005600 <HAL_TIM_PeriodElapsedCallback+0x338>)
- 80052ee: 68dc ldr r4, [r3, #12]
- 80052f0: 49c4 ldr r1, [pc, #784] ; (8005604 <HAL_TIM_PeriodElapsedCallback+0x33c>)
- 80052f2: 6822 ldr r2, [r4, #0]
- 80052f4: f8d3 8008 ldr.w r8, [r3, #8]
- 80052f8: 6816 ldr r6, [r2, #0]
- 80052fa: ed81 0a00 vstr s0, [r1]
- 80052fe: 42ae cmp r6, r5
- 8005300: f040 8232 bne.w 8005768 <HAL_TIM_PeriodElapsedCallback+0x4a0>
- 8005304: f1b8 0f63 cmp.w r8, #99 ; 0x63
- 8005308: dd03 ble.n 8005312 <HAL_TIM_PeriodElapsedCallback+0x4a>
- 800530a: f894 3680 ldrb.w r3, [r4, #1664] ; 0x680
- 800530e: 2b00 cmp r3, #0
- 8005310: d071 beq.n 80053f6 <HAL_TIM_PeriodElapsedCallback+0x12e>
- 8005312: 4bbd ldr r3, [pc, #756] ; (8005608 <HAL_TIM_PeriodElapsedCallback+0x340>)
- 8005314: 685e ldr r6, [r3, #4]
- 8005316: 4630 mov r0, r6
- 8005318: f7fa ff8e bl 8000238 <strlen>
- 800531c: 2300 movs r3, #0
- 800531e: 4631 mov r1, r6
- 8005320: 0a06 lsrs r6, r0, #8
- 8005322: f360 0307 bfi r3, r0, #0, #8
- 8005326: 4607 mov r7, r0
- 8005328: 4602 mov r2, r0
- 800532a: 0c00 lsrs r0, r0, #16
- 800532c: f366 230f bfi r3, r6, #8, #8
- 8005330: 0e3e lsrs r6, r7, #24
- 8005332: f360 4317 bfi r3, r0, #16, #8
- 8005336: f204 30af addw r0, r4, #943 ; 0x3af
- 800533a: f366 631f bfi r3, r6, #24, #8
- 800533e: 1d3e adds r6, r7, #4
- 8005340: f8c4 33ab str.w r3, [r4, #939] ; 0x3ab
- 8005344: f004 fd12 bl 8009d6c <memcpy>
- 8005348: f3c6 2207 ubfx r2, r6, #8, #8
- 800534c: b2f1 uxtb r1, r6
- 800534e: f348 2c07 sbfx ip, r8, #8, #8
- 8005352: f64f 60ff movw r0, #65279 ; 0xfeff
- 8005356: f884 83a9 strb.w r8, [r4, #937] ; 0x3a9
- 800535a: 188b adds r3, r1, r2
- 800535c: f884 c3aa strb.w ip, [r4, #938] ; 0x3aa
- 8005360: f884 13a6 strb.w r1, [r4, #934] ; 0x3a6
- 8005364: 43db mvns r3, r3
- 8005366: f884 23a7 strb.w r2, [r4, #935] ; 0x3a7
- 800536a: f8a4 03a4 strh.w r0, [r4, #932] ; 0x3a4
- 800536e: f884 33a8 strb.w r3, [r4, #936] ; 0x3a8
- 8005372: 1c73 adds r3, r6, #1
- 8005374: f2c0 821f blt.w 80057b6 <HAL_TIM_PeriodElapsedCallback+0x4ee>
- 8005378: f204 30ae addw r0, r4, #942 ; 0x3ae
- 800537c: f504 736a add.w r3, r4, #936 ; 0x3a8
- 8005380: 2200 movs r2, #0
- 8005382: 4438 add r0, r7
- 8005384: f813 1f01 ldrb.w r1, [r3, #1]!
- 8005388: 4283 cmp r3, r0
- 800538a: 440a add r2, r1
- 800538c: d1fa bne.n 8005384 <HAL_TIM_PeriodElapsedCallback+0xbc>
- 800538e: 43d2 mvns r2, r2
- 8005390: b2d2 uxtb r2, r2
- 8005392: 19a3 adds r3, r4, r6
- 8005394: 3608 adds r6, #8
- 8005396: f5b6 7f00 cmp.w r6, #512 ; 0x200
- 800539a: f883 23ab strb.w r2, [r3, #939] ; 0x3ab
- 800539e: f300 8233 bgt.w 8005808 <HAL_TIM_PeriodElapsedCallback+0x540>
- 80053a2: f8d4 018c ldr.w r0, [r4, #396] ; 0x18c
- 80053a6: f5b6 7f80 cmp.w r6, #256 ; 0x100
- 80053aa: f104 0704 add.w r7, r4, #4
- 80053ae: f504 7869 add.w r8, r4, #932 ; 0x3a4
- 80053b2: f5c0 7580 rsb r5, r0, #256 ; 0x100
- 80053b6: bfa8 it ge
- 80053b8: f44f 7680 movge.w r6, #256 ; 0x100
- 80053bc: 3088 adds r0, #136 ; 0x88
- 80053be: 4641 mov r1, r8
- 80053c0: 42b5 cmp r5, r6
- 80053c2: 4438 add r0, r7
- 80053c4: bf28 it cs
- 80053c6: 4635 movcs r5, r6
- 80053c8: 462a mov r2, r5
- 80053ca: f004 fccf bl 8009d6c <memcpy>
- 80053ce: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 80053d2: 42ae cmp r6, r5
- 80053d4: 4433 add r3, r6
- 80053d6: b2db uxtb r3, r3
- 80053d8: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 80053dc: d006 beq.n 80053ec <HAL_TIM_PeriodElapsedCallback+0x124>
- 80053de: 1b72 subs r2, r6, r5
- 80053e0: eb08 0105 add.w r1, r8, r5
- 80053e4: f104 008c add.w r0, r4, #140 ; 0x8c
- 80053e8: f004 fcc0 bl 8009d6c <memcpy>
- 80053ec: 6860 ldr r0, [r4, #4]
- 80053ee: 6f43 ldr r3, [r0, #116] ; 0x74
- 80053f0: 2b20 cmp r3, #32
- 80053f2: f000 8197 beq.w 8005724 <HAL_TIM_PeriodElapsedCallback+0x45c>
- 80053f6: 4c85 ldr r4, [pc, #532] ; (800560c <HAL_TIM_PeriodElapsedCallback+0x344>)
- 80053f8: f000 feac bl 8006154 <HAL_GetTick>
- 80053fc: f642 22f8 movw r2, #11000 ; 0x2af8
- 8005400: 4605 mov r5, r0
- 8005402: f8d4 3688 ldr.w r3, [r4, #1672] ; 0x688
- 8005406: 1ac3 subs r3, r0, r3
- 8005408: 4293 cmp r3, r2
- 800540a: d902 bls.n 8005412 <HAL_TIM_PeriodElapsedCallback+0x14a>
- 800540c: 2300 movs r3, #0
- 800540e: f884 3680 strb.w r3, [r4, #1664] ; 0x680
- 8005412: f8d4 366c ldr.w r3, [r4, #1644] ; 0x66c
- 8005416: b123 cbz r3, 8005422 <HAL_TIM_PeriodElapsedCallback+0x15a>
- 8005418: f8d4 368c ldr.w r3, [r4, #1676] ; 0x68c
- 800541c: 429d cmp r5, r3
- 800541e: f200 8165 bhi.w 80056ec <HAL_TIM_PeriodElapsedCallback+0x424>
- 8005422: 4e7b ldr r6, [pc, #492] ; (8005610 <HAL_TIM_PeriodElapsedCallback+0x348>)
- 8005424: f8df b1f4 ldr.w fp, [pc, #500] ; 800561c <HAL_TIM_PeriodElapsedCallback+0x354>
- 8005428: f1a6 0a0c sub.w sl, r6, #12
- 800542c: f8d4 31a0 ldr.w r3, [r4, #416] ; 0x1a0
- 8005430: bb4b cbnz r3, 8005486 <HAL_TIM_PeriodElapsedCallback+0x1be>
- 8005432: 6862 ldr r2, [r4, #4]
- 8005434: f8d4 3088 ldr.w r3, [r4, #136] ; 0x88
- 8005438: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 800543a: 6812 ldr r2, [r2, #0]
- 800543c: 6852 ldr r2, [r2, #4]
- 800543e: 4252 negs r2, r2
- 8005440: f002 027f and.w r2, r2, #127 ; 0x7f
- 8005444: 4293 cmp r3, r2
- 8005446: f000 80eb beq.w 8005620 <HAL_TIM_PeriodElapsedCallback+0x358>
- 800544a: 18e1 adds r1, r4, r3
- 800544c: f8d4 267c ldr.w r2, [r4, #1660] ; 0x67c
- 8005450: 3301 adds r3, #1
- 8005452: f8d4 766c ldr.w r7, [r4, #1644] ; 0x66c
- 8005456: 7a09 ldrb r1, [r1, #8]
- 8005458: f003 037f and.w r3, r3, #127 ; 0x7f
- 800545c: 2f07 cmp r7, #7
- 800545e: 440a add r2, r1
- 8005460: f8c4 3088 str.w r3, [r4, #136] ; 0x88
- 8005464: f8c4 267c str.w r2, [r4, #1660] ; 0x67c
- 8005468: d017 beq.n 800549a <HAL_TIM_PeriodElapsedCallback+0x1d2>
- 800546a: bb4f cbnz r7, 80054c0 <HAL_TIM_PeriodElapsedCallback+0x1f8>
- 800546c: 29ff cmp r1, #255 ; 0xff
- 800546e: d15d bne.n 800552c <HAL_TIM_PeriodElapsedCallback+0x264>
- 8005470: f105 0314 add.w r3, r5, #20
- 8005474: 2201 movs r2, #1
- 8005476: f8c4 368c str.w r3, [r4, #1676] ; 0x68c
- 800547a: f8d4 31a0 ldr.w r3, [r4, #416] ; 0x1a0
- 800547e: f8c4 266c str.w r2, [r4, #1644] ; 0x66c
- 8005482: 2b00 cmp r3, #0
- 8005484: d0d5 beq.n 8005432 <HAL_TIM_PeriodElapsedCallback+0x16a>
- 8005486: f000 fe65 bl 8006154 <HAL_GetTick>
- 800548a: f8d4 31a0 ldr.w r3, [r4, #416] ; 0x1a0
- 800548e: 1b40 subs r0, r0, r5
- 8005490: 4298 cmp r0, r3
- 8005492: d9ce bls.n 8005432 <HAL_TIM_PeriodElapsedCallback+0x16a>
- 8005494: b005 add sp, #20
- 8005496: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 800549a: f8d4 2678 ldr.w r2, [r4, #1656] ; 0x678
- 800549e: f8d4 3670 ldr.w r3, [r4, #1648] ; 0x670
- 80054a2: 1c50 adds r0, r2, #1
- 80054a4: 4422 add r2, r4
- 80054a6: 3b01 subs r3, #1
- 80054a8: f8c4 0678 str.w r0, [r4, #1656] ; 0x678
- 80054ac: f882 11a4 strb.w r1, [r2, #420] ; 0x1a4
- 80054b0: f8c4 3670 str.w r3, [r4, #1648] ; 0x670
- 80054b4: 2b00 cmp r3, #0
- 80054b6: d1b9 bne.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80054b8: 2308 movs r3, #8
- 80054ba: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 80054be: e7b5 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80054c0: 2f01 cmp r7, #1
- 80054c2: d03e beq.n 8005542 <HAL_TIM_PeriodElapsedCallback+0x27a>
- 80054c4: 2f02 cmp r7, #2
- 80054c6: d07b beq.n 80055c0 <HAL_TIM_PeriodElapsedCallback+0x2f8>
- 80054c8: 2f03 cmp r7, #3
- 80054ca: f000 8084 beq.w 80055d6 <HAL_TIM_PeriodElapsedCallback+0x30e>
- 80054ce: 2f04 cmp r7, #4
- 80054d0: f000 80f8 beq.w 80056c4 <HAL_TIM_PeriodElapsedCallback+0x3fc>
- 80054d4: 2f05 cmp r7, #5
- 80054d6: f000 8101 beq.w 80056dc <HAL_TIM_PeriodElapsedCallback+0x414>
- 80054da: 2f06 cmp r7, #6
- 80054dc: f000 8113 beq.w 8005706 <HAL_TIM_PeriodElapsedCallback+0x43e>
- 80054e0: 2f08 cmp r7, #8
- 80054e2: d1a3 bne.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80054e4: 4253 negs r3, r2
- 80054e6: b2d2 uxtb r2, r2
- 80054e8: f04f 0100 mov.w r1, #0
- 80054ec: b2db uxtb r3, r3
- 80054ee: f8c4 166c str.w r1, [r4, #1644] ; 0x66c
- 80054f2: bf58 it pl
- 80054f4: 425a negpl r2, r3
- 80054f6: 2aff cmp r2, #255 ; 0xff
- 80054f8: d198 bne.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80054fa: f8d4 3674 ldr.w r3, [r4, #1652] ; 0x674
- 80054fe: 2b00 cmp r3, #0
- 8005500: f000 822e beq.w 8005960 <HAL_TIM_PeriodElapsedCallback+0x698>
- 8005504: 2b0a cmp r3, #10
- 8005506: f000 81eb beq.w 80058e0 <HAL_TIM_PeriodElapsedCallback+0x618>
- 800550a: 2b06 cmp r3, #6
- 800550c: f000 821b beq.w 8005946 <HAL_TIM_PeriodElapsedCallback+0x67e>
- 8005510: 2b0b cmp r3, #11
- 8005512: f000 81e2 beq.w 80058da <HAL_TIM_PeriodElapsedCallback+0x612>
- 8005516: f503 738f add.w r3, r3, #286 ; 0x11e
- 800551a: f854 0023 ldr.w r0, [r4, r3, lsl #2]
- 800551e: 2800 cmp r0, #0
- 8005520: d084 beq.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 8005522: 6803 ldr r3, [r0, #0]
- 8005524: 4631 mov r1, r6
- 8005526: 681b ldr r3, [r3, #0]
- 8005528: 4798 blx r3
- 800552a: e77f b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 800552c: f000 fe12 bl 8006154 <HAL_GetTick>
- 8005530: f241 3388 movw r3, #5000 ; 0x1388
- 8005534: 1b40 subs r0, r0, r5
- 8005536: 4298 cmp r0, r3
- 8005538: f67f af78 bls.w 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 800553c: f884 7680 strb.w r7, [r4, #1664] ; 0x680
- 8005540: e7a8 b.n 8005494 <HAL_TIM_PeriodElapsedCallback+0x1cc>
- 8005542: 29fe cmp r1, #254 ; 0xfe
- 8005544: f000 80ba beq.w 80056bc <HAL_TIM_PeriodElapsedCallback+0x3f4>
- 8005548: 2200 movs r2, #0
- 800554a: f894 3680 ldrb.w r3, [r4, #1664] ; 0x680
- 800554e: f8c4 266c str.w r2, [r4, #1644] ; 0x66c
- 8005552: 2b00 cmp r3, #0
- 8005554: f47f af6a bne.w 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 8005558: f8d4 018c ldr.w r0, [r4, #396] ; 0x18c
- 800555c: f640 2cf7 movw ip, #2807 ; 0xaf7
- 8005560: f8df e0b0 ldr.w lr, [pc, #176] ; 8005614 <HAL_TIM_PeriodElapsedCallback+0x34c>
- 8005564: f5c0 7780 rsb r7, r0, #256 ; 0x100
- 8005568: f8c4 33ac str.w r3, [r4, #940] ; 0x3ac
- 800556c: f8df 80a8 ldr.w r8, [pc, #168] ; 8005618 <HAL_TIM_PeriodElapsedCallback+0x350>
- 8005570: f04f 4375 mov.w r3, #4110417920 ; 0xf5000000
- 8005574: 2f10 cmp r7, #16
- 8005576: 46b9 mov r9, r7
- 8005578: f100 008c add.w r0, r0, #140 ; 0x8c
- 800557c: f8c4 33b0 str.w r3, [r4, #944] ; 0x3b0
- 8005580: bf28 it cs
- 8005582: f04f 0910 movcs.w r9, #16
- 8005586: 4641 mov r1, r8
- 8005588: 4420 add r0, r4
- 800558a: f8c4 e3a4 str.w lr, [r4, #932] ; 0x3a4
- 800558e: 464a mov r2, r9
- 8005590: f8c4 c3a8 str.w ip, [r4, #936] ; 0x3a8
- 8005594: f004 fbea bl 8009d6c <memcpy>
- 8005598: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 800559c: 2f0f cmp r7, #15
- 800559e: f103 0310 add.w r3, r3, #16
- 80055a2: b2db uxtb r3, r3
- 80055a4: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 80055a8: f240 80a4 bls.w 80056f4 <HAL_TIM_PeriodElapsedCallback+0x42c>
- 80055ac: 6860 ldr r0, [r4, #4]
- 80055ae: 6f43 ldr r3, [r0, #116] ; 0x74
- 80055b0: 2b20 cmp r3, #32
- 80055b2: f000 80de beq.w 8005772 <HAL_TIM_PeriodElapsedCallback+0x4aa>
- 80055b6: f000 fdcd bl 8006154 <HAL_GetTick>
- 80055ba: f8c4 0194 str.w r0, [r4, #404] ; 0x194
- 80055be: e735 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80055c0: 2200 movs r2, #0
- 80055c2: 2303 movs r3, #3
- 80055c4: f8c4 1670 str.w r1, [r4, #1648] ; 0x670
- 80055c8: f8c4 167c str.w r1, [r4, #1660] ; 0x67c
- 80055cc: f8c4 2678 str.w r2, [r4, #1656] ; 0x678
- 80055d0: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 80055d4: e72a b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80055d6: f8d4 3670 ldr.w r3, [r4, #1648] ; 0x670
- 80055da: 2204 movs r2, #4
- 80055dc: eb03 2101 add.w r1, r3, r1, lsl #8
- 80055e0: f8c4 266c str.w r2, [r4, #1644] ; 0x66c
- 80055e4: f8c4 1670 str.w r1, [r4, #1648] ; 0x670
- 80055e8: e720 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80055ea: bf00 nop
- 80055ec: 40000400 .word 0x40000400
- 80055f0: 20000434 .word 0x20000434
- 80055f4: 20000ea4 .word 0x20000ea4
- 80055f8: 20000e80 .word 0x20000e80
- 80055fc: 200000a0 .word 0x200000a0
- 8005600: 080032d9 .word 0x080032d9
- 8005604: 20000ea8 .word 0x20000ea8
- 8005608: 20000e9c .word 0x20000e9c
- 800560c: 20000450 .word 0x20000450
- 8005610: 200005f4 .word 0x200005f4
- 8005614: 0008feff .word 0x0008feff
- 8005618: 200007f4 .word 0x200007f4
- 800561c: 10624dd3 .word 0x10624dd3
- 8005620: f894 3680 ldrb.w r3, [r4, #1664] ; 0x680
- 8005624: 2b00 cmp r3, #0
- 8005626: f43f af35 beq.w 8005494 <HAL_TIM_PeriodElapsedCallback+0x1cc>
- 800562a: f8d4 3684 ldr.w r3, [r4, #1668] ; 0x684
- 800562e: f640 12c4 movw r2, #2500 ; 0x9c4
- 8005632: 1aeb subs r3, r5, r3
- 8005634: 4293 cmp r3, r2
- 8005636: f67f af2d bls.w 8005494 <HAL_TIM_PeriodElapsedCallback+0x1cc>
- 800563a: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 800563e: f640 2cf7 movw ip, #2807 ; 0xaf7
- 8005642: 4acd ldr r2, [pc, #820] ; (8005978 <HAL_TIM_PeriodElapsedCallback+0x6b0>)
- 8005644: f5c3 7680 rsb r6, r3, #256 ; 0x100
- 8005648: 338c adds r3, #140 ; 0x8c
- 800564a: 4fcc ldr r7, [pc, #816] ; (800597c <HAL_TIM_PeriodElapsedCallback+0x6b4>)
- 800564c: 2e10 cmp r6, #16
- 800564e: 46b0 mov r8, r6
- 8005650: eb04 0003 add.w r0, r4, r3
- 8005654: f04f 0300 mov.w r3, #0
- 8005658: bf28 it cs
- 800565a: f04f 0810 movcs.w r8, #16
- 800565e: f8c4 c3a8 str.w ip, [r4, #936] ; 0x3a8
- 8005662: f06f 0c0a mvn.w ip, #10
- 8005666: f8c4 23a4 str.w r2, [r4, #932] ; 0x3a4
- 800566a: f8c4 33ac str.w r3, [r4, #940] ; 0x3ac
- 800566e: 4639 mov r1, r7
- 8005670: f8a4 33b0 strh.w r3, [r4, #944] ; 0x3b0
- 8005674: 4642 mov r2, r8
- 8005676: f884 33b2 strb.w r3, [r4, #946] ; 0x3b2
- 800567a: f884 c3b3 strb.w ip, [r4, #947] ; 0x3b3
- 800567e: f004 fb75 bl 8009d6c <memcpy>
- 8005682: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 8005686: 2e0f cmp r6, #15
- 8005688: f103 0310 add.w r3, r3, #16
- 800568c: b2db uxtb r3, r3
- 800568e: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 8005692: d807 bhi.n 80056a4 <HAL_TIM_PeriodElapsedCallback+0x3dc>
- 8005694: f1c8 0210 rsb r2, r8, #16
- 8005698: eb07 0108 add.w r1, r7, r8
- 800569c: f5a7 7046 sub.w r0, r7, #792 ; 0x318
- 80056a0: f004 fb64 bl 8009d6c <memcpy>
- 80056a4: 6860 ldr r0, [r4, #4]
- 80056a6: 6f43 ldr r3, [r0, #116] ; 0x74
- 80056a8: 2b20 cmp r3, #32
- 80056aa: f000 8086 beq.w 80057ba <HAL_TIM_PeriodElapsedCallback+0x4f2>
- 80056ae: f000 fd51 bl 8006154 <HAL_GetTick>
- 80056b2: f8c4 5684 str.w r5, [r4, #1668] ; 0x684
- 80056b6: f8c4 0194 str.w r0, [r4, #404] ; 0x194
- 80056ba: e6eb b.n 8005494 <HAL_TIM_PeriodElapsedCallback+0x1cc>
- 80056bc: 2302 movs r3, #2
- 80056be: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 80056c2: e6b3 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80056c4: 4253 negs r3, r2
- 80056c6: b2d2 uxtb r2, r2
- 80056c8: b2db uxtb r3, r3
- 80056ca: bf58 it pl
- 80056cc: 425a negpl r2, r3
- 80056ce: 2aff cmp r2, #255 ; 0xff
- 80056d0: bf0c ite eq
- 80056d2: 2305 moveq r3, #5
- 80056d4: 2300 movne r3, #0
- 80056d6: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 80056da: e6a7 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80056dc: 2306 movs r3, #6
- 80056de: f8c4 1674 str.w r1, [r4, #1652] ; 0x674
- 80056e2: f8c4 167c str.w r1, [r4, #1660] ; 0x67c
- 80056e6: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 80056ea: e69f b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80056ec: 2300 movs r3, #0
- 80056ee: f8c4 366c str.w r3, [r4, #1644] ; 0x66c
- 80056f2: e696 b.n 8005422 <HAL_TIM_PeriodElapsedCallback+0x15a>
- 80056f4: f1c9 0210 rsb r2, r9, #16
- 80056f8: eb08 0109 add.w r1, r8, r9
- 80056fc: f5a8 7046 sub.w r0, r8, #792 ; 0x318
- 8005700: f004 fb34 bl 8009d6c <memcpy>
- 8005704: e752 b.n 80055ac <HAL_TIM_PeriodElapsedCallback+0x2e4>
- 8005706: f8d4 3674 ldr.w r3, [r4, #1652] ; 0x674
- 800570a: 2007 movs r0, #7
- 800570c: f8d4 2670 ldr.w r2, [r4, #1648] ; 0x670
- 8005710: eb03 2301 add.w r3, r3, r1, lsl #8
- 8005714: f8c4 066c str.w r0, [r4, #1644] ; 0x66c
- 8005718: f8c4 3674 str.w r3, [r4, #1652] ; 0x674
- 800571c: 2a00 cmp r2, #0
- 800571e: f43f aecb beq.w 80054b8 <HAL_TIM_PeriodElapsedCallback+0x1f0>
- 8005722: e683 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 8005724: 4e96 ldr r6, [pc, #600] ; (8005980 <HAL_TIM_PeriodElapsedCallback+0x6b8>)
- 8005726: 7833 ldrb r3, [r6, #0]
- 8005728: 2b00 cmp r3, #0
- 800572a: f47f ae64 bne.w 80053f6 <HAL_TIM_PeriodElapsedCallback+0x12e>
- 800572e: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 8005732: 2301 movs r3, #1
- 8005734: f8d4 2190 ldr.w r2, [r4, #400] ; 0x190
- 8005738: 7033 strb r3, [r6, #0]
- 800573a: 4291 cmp r1, r2
- 800573c: d011 beq.n 8005762 <HAL_TIM_PeriodElapsedCallback+0x49a>
- 800573e: b293 uxth r3, r2
- 8005740: bf8c ite hi
- 8005742: 1acb subhi r3, r1, r3
- 8005744: f5c3 7380 rsbls r3, r3, #256 ; 0x100
- 8005748: f102 0188 add.w r1, r2, #136 ; 0x88
- 800574c: b29d uxth r5, r3
- 800574e: 4439 add r1, r7
- 8005750: 462a mov r2, r5
- 8005752: f002 fb2d bl 8007db0 <HAL_UART_Transmit_DMA>
- 8005756: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 800575a: 442b add r3, r5
- 800575c: b2db uxtb r3, r3
- 800575e: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 8005762: 2300 movs r3, #0
- 8005764: 7033 strb r3, [r6, #0]
- 8005766: e646 b.n 80053f6 <HAL_TIM_PeriodElapsedCallback+0x12e>
- 8005768: 4641 mov r1, r8
- 800576a: 4620 mov r0, r4
- 800576c: 4a85 ldr r2, [pc, #532] ; (8005984 <HAL_TIM_PeriodElapsedCallback+0x6bc>)
- 800576e: 47b0 blx r6
- 8005770: e641 b.n 80053f6 <HAL_TIM_PeriodElapsedCallback+0x12e>
- 8005772: 4f83 ldr r7, [pc, #524] ; (8005980 <HAL_TIM_PeriodElapsedCallback+0x6b8>)
- 8005774: 783b ldrb r3, [r7, #0]
- 8005776: 2b00 cmp r3, #0
- 8005778: f47f af1d bne.w 80055b6 <HAL_TIM_PeriodElapsedCallback+0x2ee>
- 800577c: f8d4 218c ldr.w r2, [r4, #396] ; 0x18c
- 8005780: 2101 movs r1, #1
- 8005782: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 8005786: 7039 strb r1, [r7, #0]
- 8005788: 429a cmp r2, r3
- 800578a: d011 beq.n 80057b0 <HAL_TIM_PeriodElapsedCallback+0x4e8>
- 800578c: fa1f f883 uxth.w r8, r3
- 8005790: d935 bls.n 80057fe <HAL_TIM_PeriodElapsedCallback+0x536>
- 8005792: eba2 0208 sub.w r2, r2, r8
- 8005796: fa1f f882 uxth.w r8, r2
- 800579a: 338c adds r3, #140 ; 0x8c
- 800579c: 4642 mov r2, r8
- 800579e: 18e1 adds r1, r4, r3
- 80057a0: f002 fb06 bl 8007db0 <HAL_UART_Transmit_DMA>
- 80057a4: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 80057a8: 4443 add r3, r8
- 80057aa: b2db uxtb r3, r3
- 80057ac: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 80057b0: 2300 movs r3, #0
- 80057b2: 703b strb r3, [r7, #0]
- 80057b4: e6ff b.n 80055b6 <HAL_TIM_PeriodElapsedCallback+0x2ee>
- 80057b6: 22ff movs r2, #255 ; 0xff
- 80057b8: e5eb b.n 8005392 <HAL_TIM_PeriodElapsedCallback+0xca>
- 80057ba: 4e71 ldr r6, [pc, #452] ; (8005980 <HAL_TIM_PeriodElapsedCallback+0x6b8>)
- 80057bc: 7833 ldrb r3, [r6, #0]
- 80057be: 2b00 cmp r3, #0
- 80057c0: f47f af75 bne.w 80056ae <HAL_TIM_PeriodElapsedCallback+0x3e6>
- 80057c4: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c
- 80057c8: 2301 movs r3, #1
- 80057ca: f8d4 2190 ldr.w r2, [r4, #400] ; 0x190
- 80057ce: 7033 strb r3, [r6, #0]
- 80057d0: 4291 cmp r1, r2
- 80057d2: d011 beq.n 80057f8 <HAL_TIM_PeriodElapsedCallback+0x530>
- 80057d4: b293 uxth r3, r2
- 80057d6: bf8c ite hi
- 80057d8: 1acb subhi r3, r1, r3
- 80057da: f5c3 7380 rsbls r3, r3, #256 ; 0x100
- 80057de: f102 018c add.w r1, r2, #140 ; 0x8c
- 80057e2: b29f uxth r7, r3
- 80057e4: 4421 add r1, r4
- 80057e6: 463a mov r2, r7
- 80057e8: f002 fae2 bl 8007db0 <HAL_UART_Transmit_DMA>
- 80057ec: f8d4 3190 ldr.w r3, [r4, #400] ; 0x190
- 80057f0: 443b add r3, r7
- 80057f2: b2db uxtb r3, r3
- 80057f4: f8c4 3190 str.w r3, [r4, #400] ; 0x190
- 80057f8: 2300 movs r3, #0
- 80057fa: 7033 strb r3, [r6, #0]
- 80057fc: e757 b.n 80056ae <HAL_TIM_PeriodElapsedCallback+0x3e6>
- 80057fe: f5c8 7880 rsb r8, r8, #256 ; 0x100
- 8005802: fa1f f888 uxth.w r8, r8
- 8005806: e7c8 b.n 800579a <HAL_TIM_PeriodElapsedCallback+0x4d2>
- 8005808: 4a5f ldr r2, [pc, #380] ; (8005988 <HAL_TIM_PeriodElapsedCallback+0x6c0>)
- 800580a: 2103 movs r1, #3
- 800580c: 4b5f ldr r3, [pc, #380] ; (800598c <HAL_TIM_PeriodElapsedCallback+0x6c4>)
- 800580e: f88d 1008 strb.w r1, [sp, #8]
- 8005812: 9201 str r2, [sp, #4]
- 8005814: 9303 str r3, [sp, #12]
- 8005816: 6822 ldr r2, [r4, #0]
- 8005818: 6816 ldr r6, [r2, #0]
- 800581a: 42ae cmp r6, r5
- 800581c: f040 809b bne.w 8005956 <HAL_TIM_PeriodElapsedCallback+0x68e>
- 8005820: 2038 movs r0, #56 ; 0x38
- 8005822: f884 13ab strb.w r1, [r4, #939] ; 0x3ab
- 8005826: f504 726c add.w r2, r4, #944 ; 0x3b0
- 800582a: f103 0130 add.w r1, r3, #48 ; 0x30
- 800582e: f8c4 03ac str.w r0, [r4, #940] ; 0x3ac
- 8005832: 681f ldr r7, [r3, #0]
- 8005834: 3310 adds r3, #16
- 8005836: f853 6c0c ldr.w r6, [r3, #-12]
- 800583a: 3210 adds r2, #16
- 800583c: f853 5c08 ldr.w r5, [r3, #-8]
- 8005840: f853 0c04 ldr.w r0, [r3, #-4]
- 8005844: 428b cmp r3, r1
- 8005846: f842 7c10 str.w r7, [r2, #-16]
- 800584a: f842 6c0c str.w r6, [r2, #-12]
- 800584e: f842 5c08 str.w r5, [r2, #-8]
- 8005852: f842 0c04 str.w r0, [r2, #-4]
- 8005856: d1ec bne.n 8005832 <HAL_TIM_PeriodElapsedCallback+0x56a>
- 8005858: 681e ldr r6, [r3, #0]
- 800585a: 2100 movs r1, #0
- 800585c: 6858 ldr r0, [r3, #4]
- 800585e: f240 75c2 movw r5, #1986 ; 0x7c2
- 8005862: 6016 str r6, [r2, #0]
- 8005864: 460b mov r3, r1
- 8005866: 6050 str r0, [r2, #4]
- 8005868: f504 726a add.w r2, r4, #936 ; 0x3a8
- 800586c: 4e48 ldr r6, [pc, #288] ; (8005990 <HAL_TIM_PeriodElapsedCallback+0x6c8>)
- 800586e: f204 30e7 addw r0, r4, #999 ; 0x3e7
- 8005872: f884 13aa strb.w r1, [r4, #938] ; 0x3aa
- 8005876: f8c4 63a4 str.w r6, [r4, #932] ; 0x3a4
- 800587a: f8a4 53a8 strh.w r5, [r4, #936] ; 0x3a8
- 800587e: f812 1f01 ldrb.w r1, [r2, #1]!
- 8005882: 4282 cmp r2, r0
- 8005884: 440b add r3, r1
- 8005886: d1fa bne.n 800587e <HAL_TIM_PeriodElapsedCallback+0x5b6>
- 8005888: f8d4 218c ldr.w r2, [r4, #396] ; 0x18c
- 800588c: 43db mvns r3, r3
- 800588e: 1d27 adds r7, r4, #4
- 8005890: f504 7569 add.w r5, r4, #932 ; 0x3a4
- 8005894: f5c2 7680 rsb r6, r2, #256 ; 0x100
- 8005898: 3288 adds r2, #136 ; 0x88
- 800589a: f884 33e8 strb.w r3, [r4, #1000] ; 0x3e8
- 800589e: 4629 mov r1, r5
- 80058a0: 2e45 cmp r6, #69 ; 0x45
- 80058a2: 46b0 mov r8, r6
- 80058a4: eb07 0002 add.w r0, r7, r2
- 80058a8: bf28 it cs
- 80058aa: f04f 0845 movcs.w r8, #69 ; 0x45
- 80058ae: 4642 mov r2, r8
- 80058b0: f004 fa5c bl 8009d6c <memcpy>
- 80058b4: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c
- 80058b8: 2e44 cmp r6, #68 ; 0x44
- 80058ba: f103 0345 add.w r3, r3, #69 ; 0x45
- 80058be: b2db uxtb r3, r3
- 80058c0: f8c4 318c str.w r3, [r4, #396] ; 0x18c
- 80058c4: f63f ad92 bhi.w 80053ec <HAL_TIM_PeriodElapsedCallback+0x124>
- 80058c8: eb05 0108 add.w r1, r5, r8
- 80058cc: f1c8 0245 rsb r2, r8, #69 ; 0x45
- 80058d0: f104 008c add.w r0, r4, #140 ; 0x8c
- 80058d4: f004 fa4a bl 8009d6c <memcpy>
- 80058d8: e588 b.n 80053ec <HAL_TIM_PeriodElapsedCallback+0x124>
- 80058da: f884 1680 strb.w r1, [r4, #1664] ; 0x680
- 80058de: e5a5 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 80058e0: f000 fc38 bl 8006154 <HAL_GetTick>
- 80058e4: f8df 80b8 ldr.w r8, [pc, #184] ; 80059a0 <HAL_TIM_PeriodElapsedCallback+0x6d8>
- 80058e8: f8d4 31a8 ldr.w r3, [r4, #424] ; 0x1a8
- 80058ec: f8d4 21a4 ldr.w r2, [r4, #420] ; 0x1a4
- 80058f0: f8d4 7194 ldr.w r7, [r4, #404] ; 0x194
- 80058f4: 4498 add r8, r3
- 80058f6: f102 39ff add.w r9, r2, #4294967295 ; 0xffffffff
- 80058fa: 1bc7 subs r7, r0, r7
- 80058fc: f000 fc2a bl 8006154 <HAL_GetTick>
- 8005900: 4601 mov r1, r0
- 8005902: 4650 mov r0, sl
- 8005904: fbab 3207 umull r3, r2, fp, r7
- 8005908: f44f 737a mov.w r3, #1000 ; 0x3e8
- 800590c: fbab ec01 umull lr, ip, fp, r1
- 8005910: 0992 lsrs r2, r2, #6
- 8005912: ea4f 1c9c mov.w ip, ip, lsr #6
- 8005916: fb03 7712 mls r7, r3, r2, r7
- 800591a: 444a add r2, r9
- 800591c: fb03 1e1c mls lr, r3, ip, r1
- 8005920: 4b1c ldr r3, [pc, #112] ; (8005994 <HAL_TIM_PeriodElapsedCallback+0x6cc>)
- 8005922: eba2 020c sub.w r2, r2, ip
- 8005926: 1d01 adds r1, r0, #4
- 8005928: fb03 8707 mla r7, r3, r7, r8
- 800592c: f8c4 2198 str.w r2, [r4, #408] ; 0x198
- 8005930: fb03 731e mls r3, r3, lr, r7
- 8005934: f8c4 319c str.w r3, [r4, #412] ; 0x19c
- 8005938: f000 fb92 bl 8006060 <_ZN3ros16normalizeSecNSecERmS0_>
- 800593c: f000 fc0a bl 8006154 <HAL_GetTick>
- 8005940: f8c4 0688 str.w r0, [r4, #1672] ; 0x688
- 8005944: e572 b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 8005946: 4631 mov r1, r6
- 8005948: 4813 ldr r0, [pc, #76] ; (8005998 <HAL_TIM_PeriodElapsedCallback+0x6d0>)
- 800594a: f7fb f965 bl 8000c18 <_ZN14rosserial_msgs20RequestParamResponse11deserializeEPh>
- 800594e: 2301 movs r3, #1
- 8005950: f884 3690 strb.w r3, [r4, #1680] ; 0x690
- 8005954: e56a b.n 800542c <HAL_TIM_PeriodElapsedCallback+0x164>
- 8005956: 4620 mov r0, r4
- 8005958: aa01 add r2, sp, #4
- 800595a: 2107 movs r1, #7
- 800595c: 47b0 blx r6
- 800595e: e54a b.n 80053f6 <HAL_TIM_PeriodElapsedCallback+0x12e>
- 8005960: 480e ldr r0, [pc, #56] ; (800599c <HAL_TIM_PeriodElapsedCallback+0x6d4>)
- 8005962: f7fe fd63 bl 800442c <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15requestSyncTimeEv>
- 8005966: 480d ldr r0, [pc, #52] ; (800599c <HAL_TIM_PeriodElapsedCallback+0x6d4>)
- 8005968: f7fe fdea bl 8004540 <_ZN3ros11NodeHandle_I13STM32HardwareLi25ELi25ELi512ELi512EE15negotiateTopicsEv>
- 800596c: f8c4 5684 str.w r5, [r4, #1668] ; 0x684
- 8005970: f8c4 5688 str.w r5, [r4, #1672] ; 0x688
- 8005974: e58e b.n 8005494 <HAL_TIM_PeriodElapsedCallback+0x1cc>
- 8005976: bf00 nop
- 8005978: 0008feff .word 0x0008feff
- 800597c: 200007f4 .word 0x200007f4
- 8005980: 2000009c .word 0x2000009c
- 8005984: 20000e9c .word 0x20000e9c
- 8005988: 0800a010 .word 0x0800a010
- 800598c: 0800a380 .word 0x0800a380
- 8005990: 003dfeff .word 0x003dfeff
- 8005994: 000f4240 .word 0x000f4240
- 8005998: 20000ae4 .word 0x20000ae4
- 800599c: 20000450 .word 0x20000450
- 80059a0: 3b9aca00 .word 0x3b9aca00
-
-080059a4 <_GLOBAL__sub_I_htim2>:
- 80059a4: b5f8 push {r3, r4, r5, r6, r7, lr}
- 80059a6: 4933 ldr r1, [pc, #204] ; (8005a74 <_GLOBAL__sub_I_htim2+0xd0>)
- 80059a8: 2400 movs r4, #0
- 80059aa: 4833 ldr r0, [pc, #204] ; (8005a78 <_GLOBAL__sub_I_htim2+0xd4>)
- 80059ac: 2664 movs r6, #100 ; 0x64
- 80059ae: f7fa fdcb bl 8000548 <_ZN7EncoderC1EP17TIM_HandleTypeDef>
- 80059b2: 4932 ldr r1, [pc, #200] ; (8005a7c <_GLOBAL__sub_I_htim2+0xd8>)
- 80059b4: 4832 ldr r0, [pc, #200] ; (8005a80 <_GLOBAL__sub_I_htim2+0xdc>)
- 80059b6: f44f 7700 mov.w r7, #512 ; 0x200
- 80059ba: f7fa fdc5 bl 8000548 <_ZN7EncoderC1EP17TIM_HandleTypeDef>
- 80059be: 4d31 ldr r5, [pc, #196] ; (8005a84 <_GLOBAL__sub_I_htim2+0xe0>)
- 80059c0: 4b31 ldr r3, [pc, #196] ; (8005a88 <_GLOBAL__sub_I_htim2+0xe4>)
- 80059c2: 4932 ldr r1, [pc, #200] ; (8005a8c <_GLOBAL__sub_I_htim2+0xe8>)
- 80059c4: 4a32 ldr r2, [pc, #200] ; (8005a90 <_GLOBAL__sub_I_htim2+0xec>)
- 80059c6: f103 003c add.w r0, r3, #60 ; 0x3c
- 80059ca: 611d str r5, [r3, #16]
- 80059cc: 62dd str r5, [r3, #44] ; 0x2c
- 80059ce: 6159 str r1, [r3, #20]
- 80059d0: 6319 str r1, [r3, #48] ; 0x30
- 80059d2: 619a str r2, [r3, #24]
- 80059d4: 635a str r2, [r3, #52] ; 0x34
- 80059d6: 601c str r4, [r3, #0]
- 80059d8: 61dc str r4, [r3, #28]
- 80059da: 4d2e ldr r5, [pc, #184] ; (8005a94 <_GLOBAL__sub_I_htim2+0xf0>)
- 80059dc: f7fd fda8 bl 8003530 <_ZN8nav_msgs8OdometryC1Ev>
- 80059e0: 4b2d ldr r3, [pc, #180] ; (8005a98 <_GLOBAL__sub_I_htim2+0xf4>)
- 80059e2: 4621 mov r1, r4
- 80059e4: 4a2d ldr r2, [pc, #180] ; (8005a9c <_GLOBAL__sub_I_htim2+0xf8>)
- 80059e6: f205 50a4 addw r0, r5, #1444 ; 0x5a4
- 80059ea: 606b str r3, [r5, #4]
- 80059ec: 4b2c ldr r3, [pc, #176] ; (8005aa0 <_GLOBAL__sub_I_htim2+0xfc>)
- 80059ee: 602a str r2, [r5, #0]
- 80059f0: 4632 mov r2, r6
- 80059f2: f8c5 3694 str.w r3, [r5, #1684] ; 0x694
- 80059f6: f8c5 4088 str.w r4, [r5, #136] ; 0x88
- 80059fa: f8c5 418c str.w r4, [r5, #396] ; 0x18c
- 80059fe: f8c5 4190 str.w r4, [r5, #400] ; 0x190
- 8005a02: f8c5 46b0 str.w r4, [r5, #1712] ; 0x6b0
- 8005a06: f8c5 46b8 str.w r4, [r5, #1720] ; 0x6b8
- 8005a0a: f885 4680 strb.w r4, [r5, #1664] ; 0x680
- 8005a0e: f004 f9d1 bl 8009db4 <memset>
- 8005a12: 4632 mov r2, r6
- 8005a14: 4621 mov r1, r4
- 8005a16: f505 60c1 add.w r0, r5, #1544 ; 0x608
- 8005a1a: 4e22 ldr r6, [pc, #136] ; (8005aa4 <_GLOBAL__sub_I_htim2+0x100>)
- 8005a1c: f004 f9ca bl 8009db4 <memset>
- 8005a20: 4621 mov r1, r4
- 8005a22: f505 70d2 add.w r0, r5, #420 ; 0x1a4
- 8005a26: 463a mov r2, r7
- 8005a28: f004 f9c4 bl 8009db4 <memset>
- 8005a2c: 463a mov r2, r7
- 8005a2e: 4621 mov r1, r4
- 8005a30: f505 7069 add.w r0, r5, #932 ; 0x3a4
- 8005a34: f004 f9be bl 8009db4 <memset>
- 8005a38: 4a1b ldr r2, [pc, #108] ; (8005aa8 <_GLOBAL__sub_I_htim2+0x104>)
- 8005a3a: 491c ldr r1, [pc, #112] ; (8005aac <_GLOBAL__sub_I_htim2+0x108>)
- 8005a3c: 4630 mov r0, r6
- 8005a3e: 4b1c ldr r3, [pc, #112] ; (8005ab0 <_GLOBAL__sub_I_htim2+0x10c>)
- 8005a40: 6011 str r1, [r2, #0]
- 8005a42: f8c5 4698 str.w r4, [r5, #1688] ; 0x698
- 8005a46: f8c5 46a0 str.w r4, [r5, #1696] ; 0x6a0
- 8005a4a: f8c5 46a4 str.w r4, [r5, #1700] ; 0x6a4
- 8005a4e: f8c5 46ac str.w r4, [r5, #1708] ; 0x6ac
- 8005a52: f8c5 41a0 str.w r4, [r5, #416] ; 0x1a0
- 8005a56: 4917 ldr r1, [pc, #92] ; (8005ab4 <_GLOBAL__sub_I_htim2+0x110>)
- 8005a58: 4d17 ldr r5, [pc, #92] ; (8005ab8 <_GLOBAL__sub_I_htim2+0x114>)
- 8005a5a: 6053 str r3, [r2, #4]
- 8005a5c: 6114 str r4, [r2, #16]
- 8005a5e: e9c3 5100 strd r5, r1, [r3]
- 8005a62: f7fd fd65 bl 8003530 <_ZN8nav_msgs8OdometryC1Ev>
- 8005a66: 4b15 ldr r3, [pc, #84] ; (8005abc <_GLOBAL__sub_I_htim2+0x118>)
- 8005a68: 4a15 ldr r2, [pc, #84] ; (8005ac0 <_GLOBAL__sub_I_htim2+0x11c>)
- 8005a6a: 611c str r4, [r3, #16]
- 8005a6c: e9c3 2600 strd r2, r6, [r3]
- 8005a70: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8005a72: bf00 nop
- 8005a74: 20000234 .word 0x20000234
- 8005a78: 20000434 .word 0x20000434
- 8005a7c: 200002f4 .word 0x200002f4
- 8005a80: 20000e80 .word 0x20000e80
- 8005a84: 00012110 .word 0x00012110
- 8005a88: 20000b0c .word 0x20000b0c
- 8005a8c: 40490fd0 .word 0x40490fd0
- 8005a90: 3f40ff97 .word 0x3f40ff97
- 8005a94: 20000450 .word 0x20000450
- 8005a98: 200003b4 .word 0x200003b4
- 8005a9c: 0800a118 .word 0x0800a118
- 8005aa0: 0800a028 .word 0x0800a028
- 8005aa4: 20000cf0 .word 0x20000cf0
- 8005aa8: 200000a0 .word 0x200000a0
- 8005aac: 0800a124 .word 0x0800a124
- 8005ab0: 20000e9c .word 0x20000e9c
- 8005ab4: 0800a3b8 .word 0x0800a3b8
- 8005ab8: 08009fc8 .word 0x08009fc8
- 8005abc: 20000cdc .word 0x20000cdc
- 8005ac0: 0800a12c .word 0x0800a12c
-
-08005ac4 <_ZN12OdometryCalc21OdometryUpdateMessageEv>:
- 8005ac4: b510 push {r4, lr}
- 8005ac6: 4604 mov r4, r0
- 8005ac8: f850 3b1c ldr.w r3, [r0], #28
- 8005acc: 681b ldr r3, [r3, #0]
- 8005ace: ed2d 8b0e vpush {d8-d14}
- 8005ad2: 6a5b ldr r3, [r3, #36] ; 0x24
- 8005ad4: f7fa fd5a bl 800058c <_ZN7Encoder17GetLinearVelocityEv>
- 8005ad8: eddf 9a3f vldr s19, [pc, #252] ; 8005bd8 <_ZN12OdometryCalc21OdometryUpdateMessageEv+0x114>
- 8005adc: eef0 6a40 vmov.f32 s13, s0
- 8005ae0: ed94 aa19 vldr s20, [r4, #100] ; 0x64
- 8005ae4: eeb6 ea00 vmov.f32 s28, #96 ; 0x3f000000 0.5
- 8005ae8: eeb4 0a69 vcmp.f32 s0, s19
- 8005aec: ed94 9a1a vldr s18, [r4, #104] ; 0x68
- 8005af0: ee30 6a29 vadd.f32 s12, s0, s19
- 8005af4: edd4 8a0e vldr s17, [r4, #56] ; 0x38
- 8005af8: eeb0 da4a vmov.f32 s26, s20
- 8005afc: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8005b00: ee86 8a26 vdiv.f32 s16, s12, s13
- 8005b04: eef0 aa49 vmov.f32 s21, s18
- 8005b08: ee26 ea0e vmul.f32 s28, s12, s28
- 8005b0c: e9d4 2301 ldrd r2, r3, [r4, #4]
- 8005b10: eba3 0302 sub.w r3, r3, r2
- 8005b14: ee07 3a90 vmov s15, r3
- 8005b18: eeb8 7a67 vcvt.f32.u32 s14, s15
- 8005b1c: edd4 7a73 vldr s15, [r4, #460] ; 0x1cc
- 8005b20: bf18 it ne
- 8005b22: eec0 9a27 vdivne.f32 s19, s0, s15
- 8005b26: eeb0 0a68 vmov.f32 s0, s17
- 8005b2a: ee89 ba87 vdiv.f32 s22, s19, s14
- 8005b2e: eeb6 7a00 vmov.f32 s14, #96 ; 0x3f000000 0.5
- 8005b32: ee67 7a87 vmul.f32 s15, s15, s14
- 8005b36: ee27 8a88 vmul.f32 s16, s15, s16
- 8005b3a: f002 fdf1 bl 8008720 <sinf>
- 8005b3e: eea8 da40 vfms.f32 s26, s16, s0
- 8005b42: eeb0 0a68 vmov.f32 s0, s17
- 8005b46: ee78 8a8b vadd.f32 s17, s17, s22
- 8005b4a: f002 fda9 bl 80086a0 <cosf>
- 8005b4e: eee8 aa00 vfma.f32 s21, s16, s0
- 8005b52: eeb0 0a4b vmov.f32 s0, s22
- 8005b56: f002 fda3 bl 80086a0 <cosf>
- 8005b5a: eef0 da40 vmov.f32 s27, s0
- 8005b5e: eeb0 0a4b vmov.f32 s0, s22
- 8005b62: f002 fddd bl 8008720 <sinf>
- 8005b66: eeb7 bae8 vcvt.f64.f32 d11, s17
- 8005b6a: eeb6 7b00 vmov.f64 d7, #96 ; 0x3f000000 0.5
- 8005b6e: edc4 8a0e vstr s17, [r4, #56] ; 0x38
- 8005b72: ee39 9a6a vsub.f32 s18, s18, s21
- 8005b76: ee3a aa4d vsub.f32 s20, s20, s26
- 8005b7a: ee2b bb07 vmul.f64 d11, d11, d7
- 8005b7e: ee29 8a00 vmul.f32 s16, s18, s0
- 8005b82: eeb0 0b4b vmov.f64 d0, d11
- 8005b86: f002 fd4f bl 8008628 <sin>
- 8005b8a: eeb0 cb40 vmov.f64 d12, d0
- 8005b8e: eeb0 0b4b vmov.f64 d0, d11
- 8005b92: f002 fd0d bl 80085b0 <cos>
- 8005b96: eef0 7a48 vmov.f32 s15, s16
- 8005b9a: ee9a 8a2d vfnms.f32 s16, s20, s27
- 8005b9e: 2300 movs r3, #0
- 8005ba0: eeb7 cbcc vcvt.f32.f64 s24, d12
- 8005ba4: ed84 ea48 vstr s28, [r4, #288] ; 0x120
- 8005ba8: eee9 7a2d vfma.f32 s15, s18, s27
- 8005bac: edc4 9a4e vstr s19, [r4, #312] ; 0x138
- 8005bb0: eeb7 0bc0 vcvt.f32.f64 s0, d0
- 8005bb4: 6763 str r3, [r4, #116] ; 0x74
- 8005bb6: ed84 ca1f vstr s24, [r4, #124] ; 0x7c
- 8005bba: 67a3 str r3, [r4, #120] ; 0x78
- 8005bbc: ee38 8a0d vadd.f32 s16, s16, s26
- 8005bc0: ed84 0a20 vstr s0, [r4, #128] ; 0x80
- 8005bc4: ee77 7aaa vadd.f32 s15, s15, s21
- 8005bc8: ed84 8a19 vstr s16, [r4, #100] ; 0x64
- 8005bcc: ecbd 8b0e vpop {d8-d14}
- 8005bd0: edc4 7a1a vstr s15, [r4, #104] ; 0x68
- 8005bd4: bd10 pop {r4, pc}
- 8005bd6: bf00 nop
- 8005bd8: 00000000 .word 0x00000000
-
-08005bdc <HAL_MspInit>:
- 8005bdc: 4b0a ldr r3, [pc, #40] ; (8005c08 <HAL_MspInit+0x2c>)
- 8005bde: b082 sub sp, #8
- 8005be0: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005be2: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
- 8005be6: 641a str r2, [r3, #64] ; 0x40
- 8005be8: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005bea: f002 5280 and.w r2, r2, #268435456 ; 0x10000000
- 8005bee: 9200 str r2, [sp, #0]
- 8005bf0: 9a00 ldr r2, [sp, #0]
- 8005bf2: 6c5a ldr r2, [r3, #68] ; 0x44
- 8005bf4: f442 4280 orr.w r2, r2, #16384 ; 0x4000
- 8005bf8: 645a str r2, [r3, #68] ; 0x44
- 8005bfa: 6c5b ldr r3, [r3, #68] ; 0x44
- 8005bfc: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8005c00: 9301 str r3, [sp, #4]
- 8005c02: 9b01 ldr r3, [sp, #4]
- 8005c04: b002 add sp, #8
- 8005c06: 4770 bx lr
- 8005c08: 40023800 .word 0x40023800
-
-08005c0c <HAL_TIM_Encoder_MspInit>:
- 8005c0c: 6803 ldr r3, [r0, #0]
- 8005c0e: b570 push {r4, r5, r6, lr}
- 8005c10: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 8005c14: b08a sub sp, #40 ; 0x28
- 8005c16: f04f 0400 mov.w r4, #0
- 8005c1a: e9cd 4405 strd r4, r4, [sp, #20]
- 8005c1e: e9cd 4407 strd r4, r4, [sp, #28]
- 8005c22: 9409 str r4, [sp, #36] ; 0x24
- 8005c24: d022 beq.n 8005c6c <HAL_TIM_Encoder_MspInit+0x60>
- 8005c26: 4a28 ldr r2, [pc, #160] ; (8005cc8 <HAL_TIM_Encoder_MspInit+0xbc>)
- 8005c28: 4293 cmp r3, r2
- 8005c2a: d001 beq.n 8005c30 <HAL_TIM_Encoder_MspInit+0x24>
- 8005c2c: b00a add sp, #40 ; 0x28
- 8005c2e: bd70 pop {r4, r5, r6, pc}
- 8005c30: 4b26 ldr r3, [pc, #152] ; (8005ccc <HAL_TIM_Encoder_MspInit+0xc0>)
- 8005c32: 2402 movs r4, #2
- 8005c34: 2503 movs r5, #3
- 8005c36: a905 add r1, sp, #20
- 8005c38: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005c3a: 4825 ldr r0, [pc, #148] ; (8005cd0 <HAL_TIM_Encoder_MspInit+0xc4>)
- 8005c3c: f042 0208 orr.w r2, r2, #8
- 8005c40: 641a str r2, [r3, #64] ; 0x40
- 8005c42: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005c44: f002 0208 and.w r2, r2, #8
- 8005c48: 9203 str r2, [sp, #12]
- 8005c4a: 9a03 ldr r2, [sp, #12]
- 8005c4c: 6b1a ldr r2, [r3, #48] ; 0x30
- 8005c4e: f042 0201 orr.w r2, r2, #1
- 8005c52: 631a str r2, [r3, #48] ; 0x30
- 8005c54: 6b1b ldr r3, [r3, #48] ; 0x30
- 8005c56: 9505 str r5, [sp, #20]
- 8005c58: f003 0301 and.w r3, r3, #1
- 8005c5c: 9406 str r4, [sp, #24]
- 8005c5e: 9409 str r4, [sp, #36] ; 0x24
- 8005c60: 9304 str r3, [sp, #16]
- 8005c62: 9b04 ldr r3, [sp, #16]
- 8005c64: f000 fcb8 bl 80065d8 <HAL_GPIO_Init>
- 8005c68: b00a add sp, #40 ; 0x28
- 8005c6a: bd70 pop {r4, r5, r6, pc}
- 8005c6c: f503 330e add.w r3, r3, #145408 ; 0x23800
- 8005c70: 2501 movs r5, #1
- 8005c72: 2602 movs r6, #2
- 8005c74: 2020 movs r0, #32
- 8005c76: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005c78: a905 add r1, sp, #20
- 8005c7a: 432a orrs r2, r5
- 8005c7c: 641a str r2, [r3, #64] ; 0x40
- 8005c7e: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005c80: 402a ands r2, r5
- 8005c82: 9200 str r2, [sp, #0]
- 8005c84: 9a00 ldr r2, [sp, #0]
- 8005c86: 6b1a ldr r2, [r3, #48] ; 0x30
- 8005c88: 432a orrs r2, r5
- 8005c8a: 631a str r2, [r3, #48] ; 0x30
- 8005c8c: 6b1a ldr r2, [r3, #48] ; 0x30
- 8005c8e: 402a ands r2, r5
- 8005c90: 9201 str r2, [sp, #4]
- 8005c92: 9a01 ldr r2, [sp, #4]
- 8005c94: 6b1a ldr r2, [r3, #48] ; 0x30
- 8005c96: 4332 orrs r2, r6
- 8005c98: 631a str r2, [r3, #48] ; 0x30
- 8005c9a: 6b1b ldr r3, [r3, #48] ; 0x30
- 8005c9c: 9005 str r0, [sp, #20]
- 8005c9e: 4033 ands r3, r6
- 8005ca0: 480b ldr r0, [pc, #44] ; (8005cd0 <HAL_TIM_Encoder_MspInit+0xc4>)
- 8005ca2: 9606 str r6, [sp, #24]
- 8005ca4: 9302 str r3, [sp, #8]
- 8005ca6: 9b02 ldr r3, [sp, #8]
- 8005ca8: 9509 str r5, [sp, #36] ; 0x24
- 8005caa: f000 fc95 bl 80065d8 <HAL_GPIO_Init>
- 8005cae: 2308 movs r3, #8
- 8005cb0: a905 add r1, sp, #20
- 8005cb2: 4808 ldr r0, [pc, #32] ; (8005cd4 <HAL_TIM_Encoder_MspInit+0xc8>)
- 8005cb4: 9606 str r6, [sp, #24]
- 8005cb6: 9509 str r5, [sp, #36] ; 0x24
- 8005cb8: 9305 str r3, [sp, #20]
- 8005cba: e9cd 4407 strd r4, r4, [sp, #28]
- 8005cbe: f000 fc8b bl 80065d8 <HAL_GPIO_Init>
- 8005cc2: b00a add sp, #40 ; 0x28
- 8005cc4: bd70 pop {r4, r5, r6, pc}
- 8005cc6: bf00 nop
- 8005cc8: 40000c00 .word 0x40000c00
- 8005ccc: 40023800 .word 0x40023800
- 8005cd0: 40020000 .word 0x40020000
- 8005cd4: 40020400 .word 0x40020400
-
-08005cd8 <HAL_TIM_Base_MspInit>:
- 8005cd8: 6803 ldr r3, [r0, #0]
- 8005cda: 4a14 ldr r2, [pc, #80] ; (8005d2c <HAL_TIM_Base_MspInit+0x54>)
- 8005cdc: 4293 cmp r3, r2
- 8005cde: b510 push {r4, lr}
- 8005ce0: b082 sub sp, #8
- 8005ce2: d00e beq.n 8005d02 <HAL_TIM_Base_MspInit+0x2a>
- 8005ce4: 4a12 ldr r2, [pc, #72] ; (8005d30 <HAL_TIM_Base_MspInit+0x58>)
- 8005ce6: 4293 cmp r3, r2
- 8005ce8: d109 bne.n 8005cfe <HAL_TIM_Base_MspInit+0x26>
- 8005cea: 4b12 ldr r3, [pc, #72] ; (8005d34 <HAL_TIM_Base_MspInit+0x5c>)
- 8005cec: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005cee: f042 0204 orr.w r2, r2, #4
- 8005cf2: 641a str r2, [r3, #64] ; 0x40
- 8005cf4: 6c1b ldr r3, [r3, #64] ; 0x40
- 8005cf6: f003 0304 and.w r3, r3, #4
- 8005cfa: 9301 str r3, [sp, #4]
- 8005cfc: 9b01 ldr r3, [sp, #4]
- 8005cfe: b002 add sp, #8
- 8005d00: bd10 pop {r4, pc}
- 8005d02: 4b0c ldr r3, [pc, #48] ; (8005d34 <HAL_TIM_Base_MspInit+0x5c>)
- 8005d04: 2200 movs r2, #0
- 8005d06: 201d movs r0, #29
- 8005d08: 6c1c ldr r4, [r3, #64] ; 0x40
- 8005d0a: 4611 mov r1, r2
- 8005d0c: f044 0402 orr.w r4, r4, #2
- 8005d10: 641c str r4, [r3, #64] ; 0x40
- 8005d12: 6c1b ldr r3, [r3, #64] ; 0x40
- 8005d14: f003 0302 and.w r3, r3, #2
- 8005d18: 9300 str r3, [sp, #0]
- 8005d1a: 9b00 ldr r3, [sp, #0]
- 8005d1c: f000 fa34 bl 8006188 <HAL_NVIC_SetPriority>
- 8005d20: 201d movs r0, #29
- 8005d22: b002 add sp, #8
- 8005d24: e8bd 4010 ldmia.w sp!, {r4, lr}
- 8005d28: f000 ba64 b.w 80061f4 <HAL_NVIC_EnableIRQ>
- 8005d2c: 40000400 .word 0x40000400
- 8005d30: 40000800 .word 0x40000800
- 8005d34: 40023800 .word 0x40023800
-
-08005d38 <HAL_TIM_MspPostInit>:
- 8005d38: 6801 ldr r1, [r0, #0]
- 8005d3a: 2300 movs r3, #0
- 8005d3c: 4a10 ldr r2, [pc, #64] ; (8005d80 <HAL_TIM_MspPostInit+0x48>)
- 8005d3e: b530 push {r4, r5, lr}
- 8005d40: 4291 cmp r1, r2
- 8005d42: b087 sub sp, #28
- 8005d44: e9cd 3301 strd r3, r3, [sp, #4]
- 8005d48: e9cd 3303 strd r3, r3, [sp, #12]
- 8005d4c: 9305 str r3, [sp, #20]
- 8005d4e: d001 beq.n 8005d54 <HAL_TIM_MspPostInit+0x1c>
- 8005d50: b007 add sp, #28
- 8005d52: bd30 pop {r4, r5, pc}
- 8005d54: 4b0b ldr r3, [pc, #44] ; (8005d84 <HAL_TIM_MspPostInit+0x4c>)
- 8005d56: 2402 movs r4, #2
- 8005d58: f44f 4540 mov.w r5, #49152 ; 0xc000
- 8005d5c: a901 add r1, sp, #4
- 8005d5e: 6b1a ldr r2, [r3, #48] ; 0x30
- 8005d60: 4809 ldr r0, [pc, #36] ; (8005d88 <HAL_TIM_MspPostInit+0x50>)
- 8005d62: f042 0208 orr.w r2, r2, #8
- 8005d66: 631a str r2, [r3, #48] ; 0x30
- 8005d68: 6b1b ldr r3, [r3, #48] ; 0x30
- 8005d6a: 9501 str r5, [sp, #4]
- 8005d6c: f003 0308 and.w r3, r3, #8
- 8005d70: 9402 str r4, [sp, #8]
- 8005d72: 9405 str r4, [sp, #20]
- 8005d74: 9300 str r3, [sp, #0]
- 8005d76: 9b00 ldr r3, [sp, #0]
- 8005d78: f000 fc2e bl 80065d8 <HAL_GPIO_Init>
- 8005d7c: b007 add sp, #28
- 8005d7e: bd30 pop {r4, r5, pc}
- 8005d80: 40000800 .word 0x40000800
- 8005d84: 40023800 .word 0x40023800
- 8005d88: 40020c00 .word 0x40020c00
-
-08005d8c <HAL_UART_MspInit>:
- 8005d8c: 4a66 ldr r2, [pc, #408] ; (8005f28 <HAL_UART_MspInit+0x19c>)
- 8005d8e: 6803 ldr r3, [r0, #0]
- 8005d90: b5f0 push {r4, r5, r6, r7, lr}
- 8005d92: 4293 cmp r3, r2
- 8005d94: b08b sub sp, #44 ; 0x2c
- 8005d96: f04f 0400 mov.w r4, #0
- 8005d9a: 4605 mov r5, r0
- 8005d9c: e9cd 4405 strd r4, r4, [sp, #20]
- 8005da0: e9cd 4407 strd r4, r4, [sp, #28]
- 8005da4: 9409 str r4, [sp, #36] ; 0x24
- 8005da6: d004 beq.n 8005db2 <HAL_UART_MspInit+0x26>
- 8005da8: 4a60 ldr r2, [pc, #384] ; (8005f2c <HAL_UART_MspInit+0x1a0>)
- 8005daa: 4293 cmp r3, r2
- 8005dac: d05c beq.n 8005e68 <HAL_UART_MspInit+0xdc>
- 8005dae: b00b add sp, #44 ; 0x2c
- 8005db0: bdf0 pop {r4, r5, r6, r7, pc}
- 8005db2: 4b5f ldr r3, [pc, #380] ; (8005f30 <HAL_UART_MspInit+0x1a4>)
- 8005db4: 2602 movs r6, #2
- 8005db6: 2003 movs r0, #3
- 8005db8: f44f 7740 mov.w r7, #768 ; 0x300
- 8005dbc: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005dbe: a905 add r1, sp, #20
- 8005dc0: f442 2280 orr.w r2, r2, #262144 ; 0x40000
- 8005dc4: 641a str r2, [r3, #64] ; 0x40
- 8005dc6: 6c1a ldr r2, [r3, #64] ; 0x40
- 8005dc8: f402 2280 and.w r2, r2, #262144 ; 0x40000
- 8005dcc: 9201 str r2, [sp, #4]
- 8005dce: 9a01 ldr r2, [sp, #4]
- 8005dd0: 6b1a ldr r2, [r3, #48] ; 0x30
- 8005dd2: f042 0208 orr.w r2, r2, #8
- 8005dd6: 631a str r2, [r3, #48] ; 0x30
- 8005dd8: 2207 movs r2, #7
- 8005dda: 6b1b ldr r3, [r3, #48] ; 0x30
- 8005ddc: 9606 str r6, [sp, #24]
- 8005dde: f003 0308 and.w r3, r3, #8
- 8005de2: 4e54 ldr r6, [pc, #336] ; (8005f34 <HAL_UART_MspInit+0x1a8>)
- 8005de4: 9008 str r0, [sp, #32]
- 8005de6: 9302 str r3, [sp, #8]
- 8005de8: 4853 ldr r0, [pc, #332] ; (8005f38 <HAL_UART_MspInit+0x1ac>)
- 8005dea: 9b02 ldr r3, [sp, #8]
- 8005dec: 9209 str r2, [sp, #36] ; 0x24
- 8005dee: 9705 str r7, [sp, #20]
- 8005df0: f000 fbf2 bl 80065d8 <HAL_GPIO_Init>
- 8005df4: 4951 ldr r1, [pc, #324] ; (8005f3c <HAL_UART_MspInit+0x1b0>)
- 8005df6: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 8005dfa: f44f 6380 mov.w r3, #1024 ; 0x400
- 8005dfe: 4630 mov r0, r6
- 8005e00: 6274 str r4, [r6, #36] ; 0x24
- 8005e02: 6133 str r3, [r6, #16]
- 8005e04: e9c6 4402 strd r4, r4, [r6, #8]
- 8005e08: e9c6 4405 strd r4, r4, [r6, #20]
- 8005e0c: e9c6 4407 strd r4, r4, [r6, #28]
- 8005e10: e9c6 1200 strd r1, r2, [r6]
- 8005e14: f000 fa14 bl 8006240 <HAL_DMA_Init>
- 8005e18: 2800 cmp r0, #0
- 8005e1a: d17c bne.n 8005f16 <HAL_UART_MspInit+0x18a>
- 8005e1c: 4c48 ldr r4, [pc, #288] ; (8005f40 <HAL_UART_MspInit+0x1b4>)
- 8005e1e: 2300 movs r3, #0
- 8005e20: 4848 ldr r0, [pc, #288] ; (8005f44 <HAL_UART_MspInit+0x1b8>)
- 8005e22: f04f 6700 mov.w r7, #134217728 ; 0x8000000
- 8005e26: 2140 movs r1, #64 ; 0x40
- 8005e28: f44f 6280 mov.w r2, #1024 ; 0x400
- 8005e2c: 6020 str r0, [r4, #0]
- 8005e2e: 4620 mov r0, r4
- 8005e30: 66ee str r6, [r5, #108] ; 0x6c
- 8005e32: 63b5 str r5, [r6, #56] ; 0x38
- 8005e34: 6263 str r3, [r4, #36] ; 0x24
- 8005e36: e9c4 7101 strd r7, r1, [r4, #4]
- 8005e3a: e9c4 3203 strd r3, r2, [r4, #12]
- 8005e3e: e9c4 3305 strd r3, r3, [r4, #20]
- 8005e42: e9c4 3307 strd r3, r3, [r4, #28]
- 8005e46: f000 f9fb bl 8006240 <HAL_DMA_Init>
- 8005e4a: b108 cbz r0, 8005e50 <HAL_UART_MspInit+0xc4>
- 8005e4c: f7fe faec bl 8004428 <Error_Handler>
- 8005e50: 2200 movs r2, #0
- 8005e52: 66ac str r4, [r5, #104] ; 0x68
- 8005e54: 2027 movs r0, #39 ; 0x27
- 8005e56: 63a5 str r5, [r4, #56] ; 0x38
- 8005e58: 4611 mov r1, r2
- 8005e5a: f000 f995 bl 8006188 <HAL_NVIC_SetPriority>
- 8005e5e: 2027 movs r0, #39 ; 0x27
- 8005e60: f000 f9c8 bl 80061f4 <HAL_NVIC_EnableIRQ>
- 8005e64: b00b add sp, #44 ; 0x2c
- 8005e66: bdf0 pop {r4, r5, r6, r7, pc}
- 8005e68: 4b31 ldr r3, [pc, #196] ; (8005f30 <HAL_UART_MspInit+0x1a4>)
- 8005e6a: 2602 movs r6, #2
- 8005e6c: 2003 movs r0, #3
- 8005e6e: 27c0 movs r7, #192 ; 0xc0
- 8005e70: 6c5a ldr r2, [r3, #68] ; 0x44
- 8005e72: a905 add r1, sp, #20
- 8005e74: f042 0220 orr.w r2, r2, #32
- 8005e78: 645a str r2, [r3, #68] ; 0x44
- 8005e7a: 6c5a ldr r2, [r3, #68] ; 0x44
- 8005e7c: f002 0220 and.w r2, r2, #32
- 8005e80: 9203 str r2, [sp, #12]
- 8005e82: 9a03 ldr r2, [sp, #12]
- 8005e84: 6b1a ldr r2, [r3, #48] ; 0x30
- 8005e86: f042 0204 orr.w r2, r2, #4
- 8005e8a: 631a str r2, [r3, #48] ; 0x30
- 8005e8c: 2208 movs r2, #8
- 8005e8e: 6b1b ldr r3, [r3, #48] ; 0x30
- 8005e90: 9606 str r6, [sp, #24]
- 8005e92: f003 0304 and.w r3, r3, #4
- 8005e96: 4e2c ldr r6, [pc, #176] ; (8005f48 <HAL_UART_MspInit+0x1bc>)
- 8005e98: 9008 str r0, [sp, #32]
- 8005e9a: 9304 str r3, [sp, #16]
- 8005e9c: 482b ldr r0, [pc, #172] ; (8005f4c <HAL_UART_MspInit+0x1c0>)
- 8005e9e: 9b04 ldr r3, [sp, #16]
- 8005ea0: 9209 str r2, [sp, #36] ; 0x24
- 8005ea2: 9705 str r7, [sp, #20]
- 8005ea4: f000 fb98 bl 80065d8 <HAL_GPIO_Init>
- 8005ea8: 4929 ldr r1, [pc, #164] ; (8005f50 <HAL_UART_MspInit+0x1c4>)
- 8005eaa: f04f 6220 mov.w r2, #167772160 ; 0xa000000
- 8005eae: f44f 6380 mov.w r3, #1024 ; 0x400
- 8005eb2: 4630 mov r0, r6
- 8005eb4: 6274 str r4, [r6, #36] ; 0x24
- 8005eb6: 6133 str r3, [r6, #16]
- 8005eb8: e9c6 4402 strd r4, r4, [r6, #8]
- 8005ebc: e9c6 4405 strd r4, r4, [r6, #20]
- 8005ec0: e9c6 4407 strd r4, r4, [r6, #28]
- 8005ec4: e9c6 1200 strd r1, r2, [r6]
- 8005ec8: f000 f9ba bl 8006240 <HAL_DMA_Init>
- 8005ecc: bb48 cbnz r0, 8005f22 <HAL_UART_MspInit+0x196>
- 8005ece: 4c21 ldr r4, [pc, #132] ; (8005f54 <HAL_UART_MspInit+0x1c8>)
- 8005ed0: 2300 movs r3, #0
- 8005ed2: 4821 ldr r0, [pc, #132] ; (8005f58 <HAL_UART_MspInit+0x1cc>)
- 8005ed4: f04f 6720 mov.w r7, #167772160 ; 0xa000000
- 8005ed8: 2140 movs r1, #64 ; 0x40
- 8005eda: f44f 6280 mov.w r2, #1024 ; 0x400
- 8005ede: 6020 str r0, [r4, #0]
- 8005ee0: 4620 mov r0, r4
- 8005ee2: 66ee str r6, [r5, #108] ; 0x6c
- 8005ee4: 63b5 str r5, [r6, #56] ; 0x38
- 8005ee6: 6263 str r3, [r4, #36] ; 0x24
- 8005ee8: e9c4 7101 strd r7, r1, [r4, #4]
- 8005eec: e9c4 3203 strd r3, r2, [r4, #12]
- 8005ef0: e9c4 3305 strd r3, r3, [r4, #20]
- 8005ef4: e9c4 3307 strd r3, r3, [r4, #28]
- 8005ef8: f000 f9a2 bl 8006240 <HAL_DMA_Init>
- 8005efc: b970 cbnz r0, 8005f1c <HAL_UART_MspInit+0x190>
- 8005efe: 2200 movs r2, #0
- 8005f00: 66ac str r4, [r5, #104] ; 0x68
- 8005f02: 2047 movs r0, #71 ; 0x47
- 8005f04: 63a5 str r5, [r4, #56] ; 0x38
- 8005f06: 4611 mov r1, r2
- 8005f08: f000 f93e bl 8006188 <HAL_NVIC_SetPriority>
- 8005f0c: 2047 movs r0, #71 ; 0x47
- 8005f0e: f000 f971 bl 80061f4 <HAL_NVIC_EnableIRQ>
- 8005f12: b00b add sp, #44 ; 0x2c
- 8005f14: bdf0 pop {r4, r5, r6, r7, pc}
- 8005f16: f7fe fa87 bl 8004428 <Error_Handler>
- 8005f1a: e77f b.n 8005e1c <HAL_UART_MspInit+0x90>
- 8005f1c: f7fe fa84 bl 8004428 <Error_Handler>
- 8005f20: e7ed b.n 8005efe <HAL_UART_MspInit+0x172>
- 8005f22: f7fe fa81 bl 8004428 <Error_Handler>
- 8005f26: e7d2 b.n 8005ece <HAL_UART_MspInit+0x142>
- 8005f28: 40004800 .word 0x40004800
- 8005f2c: 40011400 .word 0x40011400
- 8005f30: 40023800 .word 0x40023800
- 8005f34: 200000b4 .word 0x200000b4
- 8005f38: 40020c00 .word 0x40020c00
- 8005f3c: 40026028 .word 0x40026028
- 8005f40: 20000114 .word 0x20000114
- 8005f44: 40026058 .word 0x40026058
- 8005f48: 20000174 .word 0x20000174
- 8005f4c: 40020800 .word 0x40020800
- 8005f50: 40026428 .word 0x40026428
- 8005f54: 200001d4 .word 0x200001d4
- 8005f58: 400264a0 .word 0x400264a0
-
-08005f5c <NMI_Handler>:
- 8005f5c: 4770 bx lr
- 8005f5e: bf00 nop
-
-08005f60 <HardFault_Handler>:
- 8005f60: e7fe b.n 8005f60 <HardFault_Handler>
- 8005f62: bf00 nop
-
-08005f64 <MemManage_Handler>:
- 8005f64: e7fe b.n 8005f64 <MemManage_Handler>
- 8005f66: bf00 nop
-
-08005f68 <BusFault_Handler>:
- 8005f68: e7fe b.n 8005f68 <BusFault_Handler>
- 8005f6a: bf00 nop
-
-08005f6c <UsageFault_Handler>:
- 8005f6c: e7fe b.n 8005f6c <UsageFault_Handler>
- 8005f6e: bf00 nop
-
-08005f70 <SVC_Handler>:
- 8005f70: 4770 bx lr
- 8005f72: bf00 nop
-
-08005f74 <DebugMon_Handler>:
- 8005f74: 4770 bx lr
- 8005f76: bf00 nop
-
-08005f78 <PendSV_Handler>:
- 8005f78: 4770 bx lr
- 8005f7a: bf00 nop
-
-08005f7c <SysTick_Handler>:
- 8005f7c: f000 b8de b.w 800613c <HAL_IncTick>
-
-08005f80 <DMA1_Stream1_IRQHandler>:
- 8005f80: 4801 ldr r0, [pc, #4] ; (8005f88 <DMA1_Stream1_IRQHandler+0x8>)
- 8005f82: f000 ba53 b.w 800642c <HAL_DMA_IRQHandler>
- 8005f86: bf00 nop
- 8005f88: 200000b4 .word 0x200000b4
-
-08005f8c <DMA1_Stream3_IRQHandler>:
- 8005f8c: 4801 ldr r0, [pc, #4] ; (8005f94 <DMA1_Stream3_IRQHandler+0x8>)
- 8005f8e: f000 ba4d b.w 800642c <HAL_DMA_IRQHandler>
- 8005f92: bf00 nop
- 8005f94: 20000114 .word 0x20000114
-
-08005f98 <TIM3_IRQHandler>:
- 8005f98: 4801 ldr r0, [pc, #4] ; (8005fa0 <TIM3_IRQHandler+0x8>)
- 8005f9a: f001 be1b b.w 8007bd4 <HAL_TIM_IRQHandler>
- 8005f9e: bf00 nop
- 8005fa0: 20000274 .word 0x20000274
-
-08005fa4 <USART3_IRQHandler>:
- 8005fa4: 4801 ldr r0, [pc, #4] ; (8005fac <USART3_IRQHandler+0x8>)
- 8005fa6: f002 b82b b.w 8008000 <HAL_UART_IRQHandler>
- 8005faa: bf00 nop
- 8005fac: 20000334 .word 0x20000334
-
-08005fb0 <DMA2_Stream1_IRQHandler>:
- 8005fb0: 4801 ldr r0, [pc, #4] ; (8005fb8 <DMA2_Stream1_IRQHandler+0x8>)
- 8005fb2: f000 ba3b b.w 800642c <HAL_DMA_IRQHandler>
- 8005fb6: bf00 nop
- 8005fb8: 20000174 .word 0x20000174
-
-08005fbc <DMA2_Stream6_IRQHandler>:
- 8005fbc: 4801 ldr r0, [pc, #4] ; (8005fc4 <DMA2_Stream6_IRQHandler+0x8>)
- 8005fbe: f000 ba35 b.w 800642c <HAL_DMA_IRQHandler>
- 8005fc2: bf00 nop
- 8005fc4: 200001d4 .word 0x200001d4
-
-08005fc8 <USART6_IRQHandler>:
- 8005fc8: 4801 ldr r0, [pc, #4] ; (8005fd0 <USART6_IRQHandler+0x8>)
- 8005fca: f002 b819 b.w 8008000 <HAL_UART_IRQHandler>
- 8005fce: bf00 nop
- 8005fd0: 200003b4 .word 0x200003b4
-
-08005fd4 <_sbrk>:
- 8005fd4: 4a0c ldr r2, [pc, #48] ; (8006008 <_sbrk+0x34>)
- 8005fd6: b508 push {r3, lr}
- 8005fd8: 6813 ldr r3, [r2, #0]
- 8005fda: b133 cbz r3, 8005fea <_sbrk+0x16>
- 8005fdc: 4418 add r0, r3
- 8005fde: 4669 mov r1, sp
- 8005fe0: 4288 cmp r0, r1
- 8005fe2: d809 bhi.n 8005ff8 <_sbrk+0x24>
- 8005fe4: 6010 str r0, [r2, #0]
- 8005fe6: 4618 mov r0, r3
- 8005fe8: bd08 pop {r3, pc}
- 8005fea: 4908 ldr r1, [pc, #32] ; (800600c <_sbrk+0x38>)
- 8005fec: 460b mov r3, r1
- 8005fee: 6011 str r1, [r2, #0]
- 8005ff0: 4669 mov r1, sp
- 8005ff2: 4418 add r0, r3
- 8005ff4: 4288 cmp r0, r1
- 8005ff6: d9f5 bls.n 8005fe4 <_sbrk+0x10>
- 8005ff8: f003 fe8e bl 8009d18 <__errno>
- 8005ffc: 220c movs r2, #12
- 8005ffe: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
- 8006002: 6002 str r2, [r0, #0]
- 8006004: 4618 mov r0, r3
- 8006006: bd08 pop {r3, pc}
- 8006008: 20000eac .word 0x20000eac
- 800600c: 20000ec0 .word 0x20000ec0
-
-08006010 <SystemInit>:
- 8006010: 4a0f ldr r2, [pc, #60] ; (8006050 <SystemInit+0x40>)
- 8006012: 4b10 ldr r3, [pc, #64] ; (8006054 <SystemInit+0x44>)
- 8006014: f8d2 0088 ldr.w r0, [r2, #136] ; 0x88
- 8006018: 490f ldr r1, [pc, #60] ; (8006058 <SystemInit+0x48>)
- 800601a: f440 0070 orr.w r0, r0, #15728640 ; 0xf00000
- 800601e: b470 push {r4, r5, r6}
- 8006020: f8c2 0088 str.w r0, [r2, #136] ; 0x88
- 8006024: 2400 movs r4, #0
- 8006026: 6818 ldr r0, [r3, #0]
- 8006028: f04f 6500 mov.w r5, #134217728 ; 0x8000000
- 800602c: 4e0b ldr r6, [pc, #44] ; (800605c <SystemInit+0x4c>)
- 800602e: f040 0001 orr.w r0, r0, #1
- 8006032: 6018 str r0, [r3, #0]
- 8006034: 609c str r4, [r3, #8]
- 8006036: 6818 ldr r0, [r3, #0]
- 8006038: 4001 ands r1, r0
- 800603a: 6019 str r1, [r3, #0]
- 800603c: 605e str r6, [r3, #4]
- 800603e: 6819 ldr r1, [r3, #0]
- 8006040: f421 2180 bic.w r1, r1, #262144 ; 0x40000
- 8006044: 6019 str r1, [r3, #0]
- 8006046: 60dc str r4, [r3, #12]
- 8006048: 6095 str r5, [r2, #8]
- 800604a: bc70 pop {r4, r5, r6}
- 800604c: 4770 bx lr
- 800604e: bf00 nop
- 8006050: e000ed00 .word 0xe000ed00
- 8006054: 40023800 .word 0x40023800
- 8006058: fef6ffff .word 0xfef6ffff
- 800605c: 24003010 .word 0x24003010
-
-08006060 <_ZN3ros16normalizeSecNSecERmS0_>:
- 8006060: b470 push {r4, r5, r6}
- 8006062: 680d ldr r5, [r1, #0]
- 8006064: 4b06 ldr r3, [pc, #24] ; (8006080 <_ZN3ros16normalizeSecNSecERmS0_+0x20>)
- 8006066: 0a6a lsrs r2, r5, #9
- 8006068: 6804 ldr r4, [r0, #0]
- 800606a: 4e06 ldr r6, [pc, #24] ; (8006084 <_ZN3ros16normalizeSecNSecERmS0_+0x24>)
- 800606c: fba3 3202 umull r3, r2, r3, r2
- 8006070: 09d3 lsrs r3, r2, #7
- 8006072: 441c add r4, r3
- 8006074: fb06 5313 mls r3, r6, r3, r5
- 8006078: 6004 str r4, [r0, #0]
- 800607a: 600b str r3, [r1, #0]
- 800607c: bc70 pop {r4, r5, r6}
- 800607e: 4770 bx lr
- 8006080: 00044b83 .word 0x00044b83
- 8006084: 3b9aca00 .word 0x3b9aca00
-
-08006088 <Reset_Handler>:
- 8006088: f8df d034 ldr.w sp, [pc, #52] ; 80060c0 <LoopFillZerobss+0x14>
- 800608c: 2100 movs r1, #0
- 800608e: e003 b.n 8006098 <LoopCopyDataInit>
-
-08006090 <CopyDataInit>:
- 8006090: 4b0c ldr r3, [pc, #48] ; (80060c4 <LoopFillZerobss+0x18>)
- 8006092: 585b ldr r3, [r3, r1]
- 8006094: 5043 str r3, [r0, r1]
- 8006096: 3104 adds r1, #4
-
-08006098 <LoopCopyDataInit>:
- 8006098: 480b ldr r0, [pc, #44] ; (80060c8 <LoopFillZerobss+0x1c>)
- 800609a: 4b0c ldr r3, [pc, #48] ; (80060cc <LoopFillZerobss+0x20>)
- 800609c: 1842 adds r2, r0, r1
- 800609e: 429a cmp r2, r3
- 80060a0: d3f6 bcc.n 8006090 <CopyDataInit>
- 80060a2: 4a0b ldr r2, [pc, #44] ; (80060d0 <LoopFillZerobss+0x24>)
- 80060a4: e002 b.n 80060ac <LoopFillZerobss>
-
-080060a6 <FillZerobss>:
- 80060a6: 2300 movs r3, #0
- 80060a8: f842 3b04 str.w r3, [r2], #4
-
-080060ac <LoopFillZerobss>:
- 80060ac: 4b09 ldr r3, [pc, #36] ; (80060d4 <LoopFillZerobss+0x28>)
- 80060ae: 429a cmp r2, r3
- 80060b0: d3f9 bcc.n 80060a6 <FillZerobss>
- 80060b2: f7ff ffad bl 8006010 <SystemInit>
- 80060b6: f003 fe35 bl 8009d24 <__libc_init_array>
- 80060ba: f7fd fadb bl 8003674 <main>
- 80060be: 4770 bx lr
- 80060c0: 20080000 .word 0x20080000
- 80060c4: 0800aa84 .word 0x0800aa84
- 80060c8: 20000000 .word 0x20000000
- 80060cc: 20000080 .word 0x20000080
- 80060d0: 20000080 .word 0x20000080
- 80060d4: 20000ec0 .word 0x20000ec0
-
-080060d8 <ADC_IRQHandler>:
- 80060d8: e7fe b.n 80060d8 <ADC_IRQHandler>
- ...
-
-080060dc <HAL_InitTick>:
- 80060dc: 4a0e ldr r2, [pc, #56] ; (8006118 <HAL_InitTick+0x3c>)
- 80060de: f44f 737a mov.w r3, #1000 ; 0x3e8
- 80060e2: 490e ldr r1, [pc, #56] ; (800611c <HAL_InitTick+0x40>)
- 80060e4: 7812 ldrb r2, [r2, #0]
- 80060e6: fbb3 f3f2 udiv r3, r3, r2
- 80060ea: b510 push {r4, lr}
- 80060ec: 4604 mov r4, r0
- 80060ee: 6808 ldr r0, [r1, #0]
- 80060f0: fbb0 f0f3 udiv r0, r0, r3
- 80060f4: f000 f88c bl 8006210 <HAL_SYSTICK_Config>
- 80060f8: b908 cbnz r0, 80060fe <HAL_InitTick+0x22>
- 80060fa: 2c0f cmp r4, #15
- 80060fc: d901 bls.n 8006102 <HAL_InitTick+0x26>
- 80060fe: 2001 movs r0, #1
- 8006100: bd10 pop {r4, pc}
- 8006102: 2200 movs r2, #0
- 8006104: 4621 mov r1, r4
- 8006106: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 800610a: f000 f83d bl 8006188 <HAL_NVIC_SetPriority>
- 800610e: 4b04 ldr r3, [pc, #16] ; (8006120 <HAL_InitTick+0x44>)
- 8006110: 2000 movs r0, #0
- 8006112: 601c str r4, [r3, #0]
- 8006114: bd10 pop {r4, pc}
- 8006116: bf00 nop
- 8006118: 20000014 .word 0x20000014
- 800611c: 20000010 .word 0x20000010
- 8006120: 20000018 .word 0x20000018
-
-08006124 <HAL_Init>:
- 8006124: b508 push {r3, lr}
- 8006126: 2003 movs r0, #3
- 8006128: f000 f81a bl 8006160 <HAL_NVIC_SetPriorityGrouping>
- 800612c: 2000 movs r0, #0
- 800612e: f7ff ffd5 bl 80060dc <HAL_InitTick>
- 8006132: f7ff fd53 bl 8005bdc <HAL_MspInit>
- 8006136: 2000 movs r0, #0
- 8006138: bd08 pop {r3, pc}
- 800613a: bf00 nop
-
-0800613c <HAL_IncTick>:
- 800613c: 4a03 ldr r2, [pc, #12] ; (800614c <HAL_IncTick+0x10>)
- 800613e: 4b04 ldr r3, [pc, #16] ; (8006150 <HAL_IncTick+0x14>)
- 8006140: 6811 ldr r1, [r2, #0]
- 8006142: 781b ldrb r3, [r3, #0]
- 8006144: 440b add r3, r1
- 8006146: 6013 str r3, [r2, #0]
- 8006148: 4770 bx lr
- 800614a: bf00 nop
- 800614c: 20000eb8 .word 0x20000eb8
- 8006150: 20000014 .word 0x20000014
-
-08006154 <HAL_GetTick>:
- 8006154: 4b01 ldr r3, [pc, #4] ; (800615c <HAL_GetTick+0x8>)
- 8006156: 6818 ldr r0, [r3, #0]
- 8006158: 4770 bx lr
- 800615a: bf00 nop
- 800615c: 20000eb8 .word 0x20000eb8
-
-08006160 <HAL_NVIC_SetPriorityGrouping>:
- 8006160: 4907 ldr r1, [pc, #28] ; (8006180 <HAL_NVIC_SetPriorityGrouping+0x20>)
- 8006162: 0200 lsls r0, r0, #8
- 8006164: 4b07 ldr r3, [pc, #28] ; (8006184 <HAL_NVIC_SetPriorityGrouping+0x24>)
- 8006166: 68ca ldr r2, [r1, #12]
- 8006168: f400 60e0 and.w r0, r0, #1792 ; 0x700
- 800616c: b410 push {r4}
- 800616e: f64f 04ff movw r4, #63743 ; 0xf8ff
- 8006172: 4022 ands r2, r4
- 8006174: f85d 4b04 ldr.w r4, [sp], #4
- 8006178: 4313 orrs r3, r2
- 800617a: 4318 orrs r0, r3
- 800617c: 60c8 str r0, [r1, #12]
- 800617e: 4770 bx lr
- 8006180: e000ed00 .word 0xe000ed00
- 8006184: 05fa0000 .word 0x05fa0000
-
-08006188 <HAL_NVIC_SetPriority>:
- 8006188: 4b17 ldr r3, [pc, #92] ; (80061e8 <HAL_NVIC_SetPriority+0x60>)
- 800618a: 68db ldr r3, [r3, #12]
- 800618c: f3c3 2302 ubfx r3, r3, #8, #3
- 8006190: b430 push {r4, r5}
- 8006192: f1c3 0507 rsb r5, r3, #7
- 8006196: 1d1c adds r4, r3, #4
- 8006198: 2d04 cmp r5, #4
- 800619a: bf28 it cs
- 800619c: 2504 movcs r5, #4
- 800619e: 2c06 cmp r4, #6
- 80061a0: d918 bls.n 80061d4 <HAL_NVIC_SetPriority+0x4c>
- 80061a2: 3b03 subs r3, #3
- 80061a4: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff
- 80061a8: 409c lsls r4, r3
- 80061aa: ea22 0404 bic.w r4, r2, r4
- 80061ae: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 80061b2: 2800 cmp r0, #0
- 80061b4: fa02 f205 lsl.w r2, r2, r5
- 80061b8: ea21 0102 bic.w r1, r1, r2
- 80061bc: fa01 f203 lsl.w r2, r1, r3
- 80061c0: ea42 0204 orr.w r2, r2, r4
- 80061c4: ea4f 1202 mov.w r2, r2, lsl #4
- 80061c8: b2d2 uxtb r2, r2
- 80061ca: db06 blt.n 80061da <HAL_NVIC_SetPriority+0x52>
- 80061cc: 4b07 ldr r3, [pc, #28] ; (80061ec <HAL_NVIC_SetPriority+0x64>)
- 80061ce: 541a strb r2, [r3, r0]
- 80061d0: bc30 pop {r4, r5}
- 80061d2: 4770 bx lr
- 80061d4: 2400 movs r4, #0
- 80061d6: 4623 mov r3, r4
- 80061d8: e7e9 b.n 80061ae <HAL_NVIC_SetPriority+0x26>
- 80061da: f000 000f and.w r0, r0, #15
- 80061de: 4b04 ldr r3, [pc, #16] ; (80061f0 <HAL_NVIC_SetPriority+0x68>)
- 80061e0: 541a strb r2, [r3, r0]
- 80061e2: bc30 pop {r4, r5}
- 80061e4: 4770 bx lr
- 80061e6: bf00 nop
- 80061e8: e000ed00 .word 0xe000ed00
- 80061ec: e000e400 .word 0xe000e400
- 80061f0: e000ed14 .word 0xe000ed14
-
-080061f4 <HAL_NVIC_EnableIRQ>:
- 80061f4: 2800 cmp r0, #0
- 80061f6: db07 blt.n 8006208 <HAL_NVIC_EnableIRQ+0x14>
- 80061f8: f000 011f and.w r1, r0, #31
- 80061fc: 2301 movs r3, #1
- 80061fe: 0940 lsrs r0, r0, #5
- 8006200: 4a02 ldr r2, [pc, #8] ; (800620c <HAL_NVIC_EnableIRQ+0x18>)
- 8006202: 408b lsls r3, r1
- 8006204: f842 3020 str.w r3, [r2, r0, lsl #2]
- 8006208: 4770 bx lr
- 800620a: bf00 nop
- 800620c: e000e100 .word 0xe000e100
-
-08006210 <HAL_SYSTICK_Config>:
- 8006210: 3801 subs r0, #1
- 8006212: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000
- 8006216: d20d bcs.n 8006234 <HAL_SYSTICK_Config+0x24>
- 8006218: 4b07 ldr r3, [pc, #28] ; (8006238 <HAL_SYSTICK_Config+0x28>)
- 800621a: 2200 movs r2, #0
- 800621c: 2107 movs r1, #7
- 800621e: b430 push {r4, r5}
- 8006220: 25f0 movs r5, #240 ; 0xf0
- 8006222: 4c06 ldr r4, [pc, #24] ; (800623c <HAL_SYSTICK_Config+0x2c>)
- 8006224: 6058 str r0, [r3, #4]
- 8006226: 4610 mov r0, r2
- 8006228: f884 5023 strb.w r5, [r4, #35] ; 0x23
- 800622c: 609a str r2, [r3, #8]
- 800622e: 6019 str r1, [r3, #0]
- 8006230: bc30 pop {r4, r5}
- 8006232: 4770 bx lr
- 8006234: 2001 movs r0, #1
- 8006236: 4770 bx lr
- 8006238: e000e010 .word 0xe000e010
- 800623c: e000ed00 .word 0xe000ed00
-
-08006240 <HAL_DMA_Init>:
- 8006240: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8006242: 4604 mov r4, r0
- 8006244: f7ff ff86 bl 8006154 <HAL_GetTick>
- 8006248: 2c00 cmp r4, #0
- 800624a: d053 beq.n 80062f4 <HAL_DMA_Init+0xb4>
- 800624c: 2202 movs r2, #2
- 800624e: 6823 ldr r3, [r4, #0]
- 8006250: 2100 movs r1, #0
- 8006252: 4605 mov r5, r0
- 8006254: f884 2035 strb.w r2, [r4, #53] ; 0x35
- 8006258: 681a ldr r2, [r3, #0]
- 800625a: f884 1034 strb.w r1, [r4, #52] ; 0x34
- 800625e: f022 0201 bic.w r2, r2, #1
- 8006262: 601a str r2, [r3, #0]
- 8006264: e005 b.n 8006272 <HAL_DMA_Init+0x32>
- 8006266: f7ff ff75 bl 8006154 <HAL_GetTick>
- 800626a: 1b40 subs r0, r0, r5
- 800626c: 2805 cmp r0, #5
- 800626e: d83a bhi.n 80062e6 <HAL_DMA_Init+0xa6>
- 8006270: 6823 ldr r3, [r4, #0]
- 8006272: 681a ldr r2, [r3, #0]
- 8006274: 07d1 lsls r1, r2, #31
- 8006276: d4f6 bmi.n 8006266 <HAL_DMA_Init+0x26>
- 8006278: e9d4 2001 ldrd r2, r0, [r4, #4]
- 800627c: 68e1 ldr r1, [r4, #12]
- 800627e: 4302 orrs r2, r0
- 8006280: 681f ldr r7, [r3, #0]
- 8006282: e9d4 0504 ldrd r0, r5, [r4, #16]
- 8006286: 430a orrs r2, r1
- 8006288: 4302 orrs r2, r0
- 800628a: 6a20 ldr r0, [r4, #32]
- 800628c: e9d4 6106 ldrd r6, r1, [r4, #24]
- 8006290: 432a orrs r2, r5
- 8006292: 4d35 ldr r5, [pc, #212] ; (8006368 <HAL_DMA_Init+0x128>)
- 8006294: 4332 orrs r2, r6
- 8006296: 403d ands r5, r7
- 8006298: 430a orrs r2, r1
- 800629a: 6a61 ldr r1, [r4, #36] ; 0x24
- 800629c: 4302 orrs r2, r0
- 800629e: 2904 cmp r1, #4
- 80062a0: ea42 0205 orr.w r2, r2, r5
- 80062a4: d028 beq.n 80062f8 <HAL_DMA_Init+0xb8>
- 80062a6: 601a str r2, [r3, #0]
- 80062a8: 695a ldr r2, [r3, #20]
- 80062aa: f022 0207 bic.w r2, r2, #7
- 80062ae: 4311 orrs r1, r2
- 80062b0: b2da uxtb r2, r3
- 80062b2: 4d2e ldr r5, [pc, #184] ; (800636c <HAL_DMA_Init+0x12c>)
- 80062b4: 6159 str r1, [r3, #20]
- 80062b6: 3a10 subs r2, #16
- 80062b8: 492d ldr r1, [pc, #180] ; (8006370 <HAL_DMA_Init+0x130>)
- 80062ba: 482e ldr r0, [pc, #184] ; (8006374 <HAL_DMA_Init+0x134>)
- 80062bc: fba5 5202 umull r5, r2, r5, r2
- 80062c0: 4019 ands r1, r3
- 80062c2: 2501 movs r5, #1
- 80062c4: 0913 lsrs r3, r2, #4
- 80062c6: 2200 movs r2, #0
- 80062c8: 5cc0 ldrb r0, [r0, r3]
- 80062ca: 2b03 cmp r3, #3
- 80062cc: f04f 033f mov.w r3, #63 ; 0x3f
- 80062d0: bf88 it hi
- 80062d2: 3104 addhi r1, #4
- 80062d4: 65e0 str r0, [r4, #92] ; 0x5c
- 80062d6: 4083 lsls r3, r0
- 80062d8: 4610 mov r0, r2
- 80062da: 65a1 str r1, [r4, #88] ; 0x58
- 80062dc: 608b str r3, [r1, #8]
- 80062de: 6562 str r2, [r4, #84] ; 0x54
- 80062e0: f884 5035 strb.w r5, [r4, #53] ; 0x35
- 80062e4: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 80062e6: 2303 movs r3, #3
- 80062e8: 2220 movs r2, #32
- 80062ea: 4618 mov r0, r3
- 80062ec: 6562 str r2, [r4, #84] ; 0x54
- 80062ee: f884 3035 strb.w r3, [r4, #53] ; 0x35
- 80062f2: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 80062f4: 2001 movs r0, #1
- 80062f6: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 80062f8: e9d4 510b ldrd r5, r1, [r4, #44] ; 0x2c
- 80062fc: 6aa7 ldr r7, [r4, #40] ; 0x28
- 80062fe: ea45 0001 orr.w r0, r5, r1
- 8006302: f047 0104 orr.w r1, r7, #4
- 8006306: 4302 orrs r2, r0
- 8006308: 601a str r2, [r3, #0]
- 800630a: 695a ldr r2, [r3, #20]
- 800630c: f022 0207 bic.w r2, r2, #7
- 8006310: 4311 orrs r1, r2
- 8006312: 2d00 cmp r5, #0
- 8006314: d0cc beq.n 80062b0 <HAL_DMA_Init+0x70>
- 8006316: b17e cbz r6, 8006338 <HAL_DMA_Init+0xf8>
- 8006318: f5b6 5f00 cmp.w r6, #8192 ; 0x2000
- 800631c: d016 beq.n 800634c <HAL_DMA_Init+0x10c>
- 800631e: 2f02 cmp r7, #2
- 8006320: d903 bls.n 800632a <HAL_DMA_Init+0xea>
- 8006322: 2f03 cmp r7, #3
- 8006324: d1c4 bne.n 80062b0 <HAL_DMA_Init+0x70>
- 8006326: 01ea lsls r2, r5, #7
- 8006328: d5c2 bpl.n 80062b0 <HAL_DMA_Init+0x70>
- 800632a: 2301 movs r3, #1
- 800632c: 2240 movs r2, #64 ; 0x40
- 800632e: 4618 mov r0, r3
- 8006330: 6562 str r2, [r4, #84] ; 0x54
- 8006332: f884 3035 strb.w r3, [r4, #53] ; 0x35
- 8006336: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8006338: 2f01 cmp r7, #1
- 800633a: d003 beq.n 8006344 <HAL_DMA_Init+0x104>
- 800633c: d3f3 bcc.n 8006326 <HAL_DMA_Init+0xe6>
- 800633e: 2f02 cmp r7, #2
- 8006340: d1b6 bne.n 80062b0 <HAL_DMA_Init+0x70>
- 8006342: e7f0 b.n 8006326 <HAL_DMA_Init+0xe6>
- 8006344: f1b5 7fc0 cmp.w r5, #25165824 ; 0x1800000
- 8006348: d1b2 bne.n 80062b0 <HAL_DMA_Init+0x70>
- 800634a: e7ee b.n 800632a <HAL_DMA_Init+0xea>
- 800634c: 2f03 cmp r7, #3
- 800634e: d8af bhi.n 80062b0 <HAL_DMA_Init+0x70>
- 8006350: a201 add r2, pc, #4 ; (adr r2, 8006358 <HAL_DMA_Init+0x118>)
- 8006352: f852 f027 ldr.w pc, [r2, r7, lsl #2]
- 8006356: bf00 nop
- 8006358: 0800632b .word 0x0800632b
- 800635c: 08006327 .word 0x08006327
- 8006360: 0800632b .word 0x0800632b
- 8006364: 08006345 .word 0x08006345
- 8006368: e010803f .word 0xe010803f
- 800636c: aaaaaaab .word 0xaaaaaaab
- 8006370: fffffc00 .word 0xfffffc00
- 8006374: 0800a4a8 .word 0x0800a4a8
-
-08006378 <HAL_DMA_Start_IT>:
- 8006378: b4f0 push {r4, r5, r6, r7}
- 800637a: f890 4034 ldrb.w r4, [r0, #52] ; 0x34
- 800637e: 2c01 cmp r4, #1
- 8006380: d038 beq.n 80063f4 <HAL_DMA_Start_IT+0x7c>
- 8006382: 2501 movs r5, #1
- 8006384: f890 4035 ldrb.w r4, [r0, #53] ; 0x35
- 8006388: 6d86 ldr r6, [r0, #88] ; 0x58
- 800638a: 42ac cmp r4, r5
- 800638c: f880 5034 strb.w r5, [r0, #52] ; 0x34
- 8006390: d129 bne.n 80063e6 <HAL_DMA_Start_IT+0x6e>
- 8006392: 6804 ldr r4, [r0, #0]
- 8006394: 2702 movs r7, #2
- 8006396: 2500 movs r5, #0
- 8006398: f880 7035 strb.w r7, [r0, #53] ; 0x35
- 800639c: 6545 str r5, [r0, #84] ; 0x54
- 800639e: 6887 ldr r7, [r0, #8]
- 80063a0: 6825 ldr r5, [r4, #0]
- 80063a2: 2f40 cmp r7, #64 ; 0x40
- 80063a4: f425 2580 bic.w r5, r5, #262144 ; 0x40000
- 80063a8: 6025 str r5, [r4, #0]
- 80063aa: 6063 str r3, [r4, #4]
- 80063ac: d026 beq.n 80063fc <HAL_DMA_Start_IT+0x84>
- 80063ae: 60a1 str r1, [r4, #8]
- 80063b0: 60e2 str r2, [r4, #12]
- 80063b2: 6dc1 ldr r1, [r0, #92] ; 0x5c
- 80063b4: 233f movs r3, #63 ; 0x3f
- 80063b6: 6c02 ldr r2, [r0, #64] ; 0x40
- 80063b8: 408b lsls r3, r1
- 80063ba: 60b3 str r3, [r6, #8]
- 80063bc: 6823 ldr r3, [r4, #0]
- 80063be: f043 0316 orr.w r3, r3, #22
- 80063c2: 6023 str r3, [r4, #0]
- 80063c4: 6963 ldr r3, [r4, #20]
- 80063c6: f043 0380 orr.w r3, r3, #128 ; 0x80
- 80063ca: 6163 str r3, [r4, #20]
- 80063cc: b11a cbz r2, 80063d6 <HAL_DMA_Start_IT+0x5e>
- 80063ce: 6823 ldr r3, [r4, #0]
- 80063d0: f043 0308 orr.w r3, r3, #8
- 80063d4: 6023 str r3, [r4, #0]
- 80063d6: 6822 ldr r2, [r4, #0]
- 80063d8: 2300 movs r3, #0
- 80063da: f042 0201 orr.w r2, r2, #1
- 80063de: 4618 mov r0, r3
- 80063e0: 6022 str r2, [r4, #0]
- 80063e2: bcf0 pop {r4, r5, r6, r7}
- 80063e4: 4770 bx lr
- 80063e6: 2200 movs r2, #0
- 80063e8: 2302 movs r3, #2
- 80063ea: f880 2034 strb.w r2, [r0, #52] ; 0x34
- 80063ee: 4618 mov r0, r3
- 80063f0: bcf0 pop {r4, r5, r6, r7}
- 80063f2: 4770 bx lr
- 80063f4: 2302 movs r3, #2
- 80063f6: bcf0 pop {r4, r5, r6, r7}
- 80063f8: 4618 mov r0, r3
- 80063fa: 4770 bx lr
- 80063fc: 60a2 str r2, [r4, #8]
- 80063fe: 60e1 str r1, [r4, #12]
- 8006400: e7d7 b.n 80063b2 <HAL_DMA_Start_IT+0x3a>
- 8006402: bf00 nop
-
-08006404 <HAL_DMA_Abort_IT>:
- 8006404: f890 2035 ldrb.w r2, [r0, #53] ; 0x35
- 8006408: 4603 mov r3, r0
- 800640a: 2a02 cmp r2, #2
- 800640c: d003 beq.n 8006416 <HAL_DMA_Abort_IT+0x12>
- 800640e: 2280 movs r2, #128 ; 0x80
- 8006410: 2001 movs r0, #1
- 8006412: 655a str r2, [r3, #84] ; 0x54
- 8006414: 4770 bx lr
- 8006416: 6802 ldr r2, [r0, #0]
- 8006418: 2105 movs r1, #5
- 800641a: 2000 movs r0, #0
- 800641c: f883 1035 strb.w r1, [r3, #53] ; 0x35
- 8006420: 6813 ldr r3, [r2, #0]
- 8006422: f023 0301 bic.w r3, r3, #1
- 8006426: 6013 str r3, [r2, #0]
- 8006428: 4770 bx lr
- 800642a: bf00 nop
-
-0800642c <HAL_DMA_IRQHandler>:
- 800642c: b5f0 push {r4, r5, r6, r7, lr}
- 800642e: 4604 mov r4, r0
- 8006430: b083 sub sp, #12
- 8006432: 2000 movs r0, #0
- 8006434: 2208 movs r2, #8
- 8006436: 4966 ldr r1, [pc, #408] ; (80065d0 <HAL_DMA_IRQHandler+0x1a4>)
- 8006438: 9001 str r0, [sp, #4]
- 800643a: 680e ldr r6, [r1, #0]
- 800643c: e9d4 7316 ldrd r7, r3, [r4, #88] ; 0x58
- 8006440: 409a lsls r2, r3
- 8006442: 683d ldr r5, [r7, #0]
- 8006444: 422a tst r2, r5
- 8006446: d003 beq.n 8006450 <HAL_DMA_IRQHandler+0x24>
- 8006448: 6821 ldr r1, [r4, #0]
- 800644a: 6808 ldr r0, [r1, #0]
- 800644c: 0740 lsls r0, r0, #29
- 800644e: d459 bmi.n 8006504 <HAL_DMA_IRQHandler+0xd8>
- 8006450: 2201 movs r2, #1
- 8006452: 409a lsls r2, r3
- 8006454: 422a tst r2, r5
- 8006456: d003 beq.n 8006460 <HAL_DMA_IRQHandler+0x34>
- 8006458: 6821 ldr r1, [r4, #0]
- 800645a: 6949 ldr r1, [r1, #20]
- 800645c: 0608 lsls r0, r1, #24
- 800645e: d474 bmi.n 800654a <HAL_DMA_IRQHandler+0x11e>
- 8006460: 2204 movs r2, #4
- 8006462: 409a lsls r2, r3
- 8006464: 422a tst r2, r5
- 8006466: d003 beq.n 8006470 <HAL_DMA_IRQHandler+0x44>
- 8006468: 6821 ldr r1, [r4, #0]
- 800646a: 6809 ldr r1, [r1, #0]
- 800646c: 0789 lsls r1, r1, #30
- 800646e: d466 bmi.n 800653e <HAL_DMA_IRQHandler+0x112>
- 8006470: 2210 movs r2, #16
- 8006472: 409a lsls r2, r3
- 8006474: 422a tst r2, r5
- 8006476: d003 beq.n 8006480 <HAL_DMA_IRQHandler+0x54>
- 8006478: 6821 ldr r1, [r4, #0]
- 800647a: 6808 ldr r0, [r1, #0]
- 800647c: 0700 lsls r0, r0, #28
- 800647e: d44b bmi.n 8006518 <HAL_DMA_IRQHandler+0xec>
- 8006480: 2220 movs r2, #32
- 8006482: 409a lsls r2, r3
- 8006484: 422a tst r2, r5
- 8006486: d014 beq.n 80064b2 <HAL_DMA_IRQHandler+0x86>
- 8006488: 6821 ldr r1, [r4, #0]
- 800648a: 6808 ldr r0, [r1, #0]
- 800648c: 06c0 lsls r0, r0, #27
- 800648e: d510 bpl.n 80064b2 <HAL_DMA_IRQHandler+0x86>
- 8006490: 60ba str r2, [r7, #8]
- 8006492: f894 2035 ldrb.w r2, [r4, #53] ; 0x35
- 8006496: 2a05 cmp r2, #5
- 8006498: d063 beq.n 8006562 <HAL_DMA_IRQHandler+0x136>
- 800649a: 680b ldr r3, [r1, #0]
- 800649c: f413 2f80 tst.w r3, #262144 ; 0x40000
- 80064a0: 680b ldr r3, [r1, #0]
- 80064a2: d07e beq.n 80065a2 <HAL_DMA_IRQHandler+0x176>
- 80064a4: 0319 lsls r1, r3, #12
- 80064a6: f140 8089 bpl.w 80065bc <HAL_DMA_IRQHandler+0x190>
- 80064aa: 6be3 ldr r3, [r4, #60] ; 0x3c
- 80064ac: b10b cbz r3, 80064b2 <HAL_DMA_IRQHandler+0x86>
- 80064ae: 4620 mov r0, r4
- 80064b0: 4798 blx r3
- 80064b2: 6d63 ldr r3, [r4, #84] ; 0x54
- 80064b4: b323 cbz r3, 8006500 <HAL_DMA_IRQHandler+0xd4>
- 80064b6: 6d63 ldr r3, [r4, #84] ; 0x54
- 80064b8: 07da lsls r2, r3, #31
- 80064ba: d51a bpl.n 80064f2 <HAL_DMA_IRQHandler+0xc6>
- 80064bc: 6822 ldr r2, [r4, #0]
- 80064be: 2105 movs r1, #5
- 80064c0: 4b44 ldr r3, [pc, #272] ; (80065d4 <HAL_DMA_IRQHandler+0x1a8>)
- 80064c2: f884 1035 strb.w r1, [r4, #53] ; 0x35
- 80064c6: fba3 3606 umull r3, r6, r3, r6
- 80064ca: 6813 ldr r3, [r2, #0]
- 80064cc: f023 0301 bic.w r3, r3, #1
- 80064d0: 0ab6 lsrs r6, r6, #10
- 80064d2: 6013 str r3, [r2, #0]
- 80064d4: e002 b.n 80064dc <HAL_DMA_IRQHandler+0xb0>
- 80064d6: 6813 ldr r3, [r2, #0]
- 80064d8: 07db lsls r3, r3, #31
- 80064da: d504 bpl.n 80064e6 <HAL_DMA_IRQHandler+0xba>
- 80064dc: 9b01 ldr r3, [sp, #4]
- 80064de: 3301 adds r3, #1
- 80064e0: 42b3 cmp r3, r6
- 80064e2: 9301 str r3, [sp, #4]
- 80064e4: d9f7 bls.n 80064d6 <HAL_DMA_IRQHandler+0xaa>
- 80064e6: 2200 movs r2, #0
- 80064e8: 2301 movs r3, #1
- 80064ea: f884 2034 strb.w r2, [r4, #52] ; 0x34
- 80064ee: f884 3035 strb.w r3, [r4, #53] ; 0x35
- 80064f2: 6ce3 ldr r3, [r4, #76] ; 0x4c
- 80064f4: b123 cbz r3, 8006500 <HAL_DMA_IRQHandler+0xd4>
- 80064f6: 4620 mov r0, r4
- 80064f8: b003 add sp, #12
- 80064fa: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr}
- 80064fe: 4718 bx r3
- 8006500: b003 add sp, #12
- 8006502: bdf0 pop {r4, r5, r6, r7, pc}
- 8006504: 6808 ldr r0, [r1, #0]
- 8006506: f020 0004 bic.w r0, r0, #4
- 800650a: 6008 str r0, [r1, #0]
- 800650c: 60ba str r2, [r7, #8]
- 800650e: 6d62 ldr r2, [r4, #84] ; 0x54
- 8006510: f042 0201 orr.w r2, r2, #1
- 8006514: 6562 str r2, [r4, #84] ; 0x54
- 8006516: e79b b.n 8006450 <HAL_DMA_IRQHandler+0x24>
- 8006518: 60ba str r2, [r7, #8]
- 800651a: 680a ldr r2, [r1, #0]
- 800651c: f412 2f80 tst.w r2, #262144 ; 0x40000
- 8006520: 680a ldr r2, [r1, #0]
- 8006522: d118 bne.n 8006556 <HAL_DMA_IRQHandler+0x12a>
- 8006524: 05d2 lsls r2, r2, #23
- 8006526: d403 bmi.n 8006530 <HAL_DMA_IRQHandler+0x104>
- 8006528: 680a ldr r2, [r1, #0]
- 800652a: f022 0208 bic.w r2, r2, #8
- 800652e: 600a str r2, [r1, #0]
- 8006530: 6c22 ldr r2, [r4, #64] ; 0x40
- 8006532: 2a00 cmp r2, #0
- 8006534: d0a4 beq.n 8006480 <HAL_DMA_IRQHandler+0x54>
- 8006536: 4620 mov r0, r4
- 8006538: 4790 blx r2
- 800653a: 6de3 ldr r3, [r4, #92] ; 0x5c
- 800653c: e7a0 b.n 8006480 <HAL_DMA_IRQHandler+0x54>
- 800653e: 60ba str r2, [r7, #8]
- 8006540: 6d62 ldr r2, [r4, #84] ; 0x54
- 8006542: f042 0204 orr.w r2, r2, #4
- 8006546: 6562 str r2, [r4, #84] ; 0x54
- 8006548: e792 b.n 8006470 <HAL_DMA_IRQHandler+0x44>
- 800654a: 60ba str r2, [r7, #8]
- 800654c: 6d62 ldr r2, [r4, #84] ; 0x54
- 800654e: f042 0202 orr.w r2, r2, #2
- 8006552: 6562 str r2, [r4, #84] ; 0x54
- 8006554: e784 b.n 8006460 <HAL_DMA_IRQHandler+0x34>
- 8006556: 0311 lsls r1, r2, #12
- 8006558: d5ea bpl.n 8006530 <HAL_DMA_IRQHandler+0x104>
- 800655a: 6ca2 ldr r2, [r4, #72] ; 0x48
- 800655c: 2a00 cmp r2, #0
- 800655e: d1ea bne.n 8006536 <HAL_DMA_IRQHandler+0x10a>
- 8006560: e78e b.n 8006480 <HAL_DMA_IRQHandler+0x54>
- 8006562: 680a ldr r2, [r1, #0]
- 8006564: 6c20 ldr r0, [r4, #64] ; 0x40
- 8006566: f022 0216 bic.w r2, r2, #22
- 800656a: 600a str r2, [r1, #0]
- 800656c: 694a ldr r2, [r1, #20]
- 800656e: f022 0280 bic.w r2, r2, #128 ; 0x80
- 8006572: 614a str r2, [r1, #20]
- 8006574: b338 cbz r0, 80065c6 <HAL_DMA_IRQHandler+0x19a>
- 8006576: 680a ldr r2, [r1, #0]
- 8006578: f022 0208 bic.w r2, r2, #8
- 800657c: 600a str r2, [r1, #0]
- 800657e: 223f movs r2, #63 ; 0x3f
- 8006580: 2000 movs r0, #0
- 8006582: 2101 movs r1, #1
- 8006584: fa02 f303 lsl.w r3, r2, r3
- 8006588: 6d22 ldr r2, [r4, #80] ; 0x50
- 800658a: 60bb str r3, [r7, #8]
- 800658c: f884 0034 strb.w r0, [r4, #52] ; 0x34
- 8006590: f884 1035 strb.w r1, [r4, #53] ; 0x35
- 8006594: 2a00 cmp r2, #0
- 8006596: d0b3 beq.n 8006500 <HAL_DMA_IRQHandler+0xd4>
- 8006598: 4620 mov r0, r4
- 800659a: b003 add sp, #12
- 800659c: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr}
- 80065a0: 4710 bx r2
- 80065a2: f413 7380 ands.w r3, r3, #256 ; 0x100
- 80065a6: d180 bne.n 80064aa <HAL_DMA_IRQHandler+0x7e>
- 80065a8: 680a ldr r2, [r1, #0]
- 80065aa: 2001 movs r0, #1
- 80065ac: f022 0210 bic.w r2, r2, #16
- 80065b0: 600a str r2, [r1, #0]
- 80065b2: f884 3034 strb.w r3, [r4, #52] ; 0x34
- 80065b6: f884 0035 strb.w r0, [r4, #53] ; 0x35
- 80065ba: e776 b.n 80064aa <HAL_DMA_IRQHandler+0x7e>
- 80065bc: 6c63 ldr r3, [r4, #68] ; 0x44
- 80065be: 2b00 cmp r3, #0
- 80065c0: f47f af75 bne.w 80064ae <HAL_DMA_IRQHandler+0x82>
- 80065c4: e775 b.n 80064b2 <HAL_DMA_IRQHandler+0x86>
- 80065c6: 6ca2 ldr r2, [r4, #72] ; 0x48
- 80065c8: 2a00 cmp r2, #0
- 80065ca: d1d4 bne.n 8006576 <HAL_DMA_IRQHandler+0x14a>
- 80065cc: e7d7 b.n 800657e <HAL_DMA_IRQHandler+0x152>
- 80065ce: bf00 nop
- 80065d0: 20000010 .word 0x20000010
- 80065d4: 1b4e81b5 .word 0x1b4e81b5
-
-080065d8 <HAL_GPIO_Init>:
- 80065d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 80065dc: f8df c22c ldr.w ip, [pc, #556] ; 800680c <HAL_GPIO_Init+0x234>
- 80065e0: b083 sub sp, #12
- 80065e2: 468e mov lr, r1
- 80065e4: 2500 movs r5, #0
- 80065e6: f8df 9228 ldr.w r9, [pc, #552] ; 8006810 <HAL_GPIO_Init+0x238>
- 80065ea: f8d1 8000 ldr.w r8, [r1]
- 80065ee: e003 b.n 80065f8 <HAL_GPIO_Init+0x20>
- 80065f0: 3501 adds r5, #1
- 80065f2: 2d10 cmp r5, #16
- 80065f4: f000 80b6 beq.w 8006764 <HAL_GPIO_Init+0x18c>
- 80065f8: 2301 movs r3, #1
- 80065fa: 40ab lsls r3, r5
- 80065fc: ea08 0103 and.w r1, r8, r3
- 8006600: 428b cmp r3, r1
- 8006602: d1f5 bne.n 80065f0 <HAL_GPIO_Init+0x18>
- 8006604: f8de 4004 ldr.w r4, [lr, #4]
- 8006608: f024 0710 bic.w r7, r4, #16
- 800660c: 2f02 cmp r7, #2
- 800660e: f040 80ac bne.w 800676a <HAL_GPIO_Init+0x192>
- 8006612: 08ef lsrs r7, r5, #3
- 8006614: f005 0a07 and.w sl, r5, #7
- 8006618: f04f 0b0f mov.w fp, #15
- 800661c: f8de 2010 ldr.w r2, [lr, #16]
- 8006620: eb00 0787 add.w r7, r0, r7, lsl #2
- 8006624: ea4f 0a8a mov.w sl, sl, lsl #2
- 8006628: 6a3e ldr r6, [r7, #32]
- 800662a: fa0b fb0a lsl.w fp, fp, sl
- 800662e: fa02 f20a lsl.w r2, r2, sl
- 8006632: ea4f 0a45 mov.w sl, r5, lsl #1
- 8006636: ea26 060b bic.w r6, r6, fp
- 800663a: f04f 0b03 mov.w fp, #3
- 800663e: 4332 orrs r2, r6
- 8006640: fa0b fb0a lsl.w fp, fp, sl
- 8006644: f004 0603 and.w r6, r4, #3
- 8006648: 623a str r2, [r7, #32]
- 800664a: ea6f 020b mvn.w r2, fp
- 800664e: 6807 ldr r7, [r0, #0]
- 8006650: fa06 f60a lsl.w r6, r6, sl
- 8006654: 4017 ands r7, r2
- 8006656: 433e orrs r6, r7
- 8006658: 6006 str r6, [r0, #0]
- 800665a: 6886 ldr r6, [r0, #8]
- 800665c: f3c4 1700 ubfx r7, r4, #4, #1
- 8006660: ea06 0b02 and.w fp, r6, r2
- 8006664: f8de 600c ldr.w r6, [lr, #12]
- 8006668: 40af lsls r7, r5
- 800666a: fa06 f60a lsl.w r6, r6, sl
- 800666e: ea46 060b orr.w r6, r6, fp
- 8006672: 6086 str r6, [r0, #8]
- 8006674: 6846 ldr r6, [r0, #4]
- 8006676: ea26 0303 bic.w r3, r6, r3
- 800667a: 431f orrs r7, r3
- 800667c: 6047 str r7, [r0, #4]
- 800667e: 68c6 ldr r6, [r0, #12]
- 8006680: 00e7 lsls r7, r4, #3
- 8006682: f8de 3008 ldr.w r3, [lr, #8]
- 8006686: ea02 0206 and.w r2, r2, r6
- 800668a: fa03 f30a lsl.w r3, r3, sl
- 800668e: ea43 0302 orr.w r3, r3, r2
- 8006692: 60c3 str r3, [r0, #12]
- 8006694: d5ac bpl.n 80065f0 <HAL_GPIO_Init+0x18>
- 8006696: f8d9 6044 ldr.w r6, [r9, #68] ; 0x44
- 800669a: f025 0703 bic.w r7, r5, #3
- 800669e: f005 0303 and.w r3, r5, #3
- 80066a2: 220f movs r2, #15
- 80066a4: f446 4680 orr.w r6, r6, #16384 ; 0x4000
- 80066a8: f107 4780 add.w r7, r7, #1073741824 ; 0x40000000
- 80066ac: 009b lsls r3, r3, #2
- 80066ae: f8c9 6044 str.w r6, [r9, #68] ; 0x44
- 80066b2: f507 379c add.w r7, r7, #79872 ; 0x13800
- 80066b6: f8d9 6044 ldr.w r6, [r9, #68] ; 0x44
- 80066ba: fa02 fa03 lsl.w sl, r2, r3
- 80066be: f406 4680 and.w r6, r6, #16384 ; 0x4000
- 80066c2: 9601 str r6, [sp, #4]
- 80066c4: 4e48 ldr r6, [pc, #288] ; (80067e8 <HAL_GPIO_Init+0x210>)
- 80066c6: 9a01 ldr r2, [sp, #4]
- 80066c8: 42b0 cmp r0, r6
- 80066ca: 68ba ldr r2, [r7, #8]
- 80066cc: ea22 020a bic.w r2, r2, sl
- 80066d0: d020 beq.n 8006714 <HAL_GPIO_Init+0x13c>
- 80066d2: f506 6680 add.w r6, r6, #1024 ; 0x400
- 80066d6: 42b0 cmp r0, r6
- 80066d8: d05e beq.n 8006798 <HAL_GPIO_Init+0x1c0>
- 80066da: 4e44 ldr r6, [pc, #272] ; (80067ec <HAL_GPIO_Init+0x214>)
- 80066dc: 42b0 cmp r0, r6
- 80066de: d060 beq.n 80067a2 <HAL_GPIO_Init+0x1ca>
- 80066e0: 4e43 ldr r6, [pc, #268] ; (80067f0 <HAL_GPIO_Init+0x218>)
- 80066e2: 42b0 cmp r0, r6
- 80066e4: d062 beq.n 80067ac <HAL_GPIO_Init+0x1d4>
- 80066e6: 4e43 ldr r6, [pc, #268] ; (80067f4 <HAL_GPIO_Init+0x21c>)
- 80066e8: 42b0 cmp r0, r6
- 80066ea: d064 beq.n 80067b6 <HAL_GPIO_Init+0x1de>
- 80066ec: 4e42 ldr r6, [pc, #264] ; (80067f8 <HAL_GPIO_Init+0x220>)
- 80066ee: 42b0 cmp r0, r6
- 80066f0: d06b beq.n 80067ca <HAL_GPIO_Init+0x1f2>
- 80066f2: 4e42 ldr r6, [pc, #264] ; (80067fc <HAL_GPIO_Init+0x224>)
- 80066f4: 42b0 cmp r0, r6
- 80066f6: d06d beq.n 80067d4 <HAL_GPIO_Init+0x1fc>
- 80066f8: 4e41 ldr r6, [pc, #260] ; (8006800 <HAL_GPIO_Init+0x228>)
- 80066fa: 42b0 cmp r0, r6
- 80066fc: d060 beq.n 80067c0 <HAL_GPIO_Init+0x1e8>
- 80066fe: 4e41 ldr r6, [pc, #260] ; (8006804 <HAL_GPIO_Init+0x22c>)
- 8006700: 42b0 cmp r0, r6
- 8006702: d06c beq.n 80067de <HAL_GPIO_Init+0x206>
- 8006704: 4e40 ldr r6, [pc, #256] ; (8006808 <HAL_GPIO_Init+0x230>)
- 8006706: 42b0 cmp r0, r6
- 8006708: bf0c ite eq
- 800670a: 2609 moveq r6, #9
- 800670c: 260a movne r6, #10
- 800670e: fa06 f303 lsl.w r3, r6, r3
- 8006712: 431a orrs r2, r3
- 8006714: 60ba str r2, [r7, #8]
- 8006716: 03e6 lsls r6, r4, #15
- 8006718: f8dc 3000 ldr.w r3, [ip]
- 800671c: ea6f 0201 mvn.w r2, r1
- 8006720: f105 0501 add.w r5, r5, #1
- 8006724: bf54 ite pl
- 8006726: 4013 andpl r3, r2
- 8006728: 430b orrmi r3, r1
- 800672a: 03a7 lsls r7, r4, #14
- 800672c: f8cc 3000 str.w r3, [ip]
- 8006730: f8dc 3004 ldr.w r3, [ip, #4]
- 8006734: bf54 ite pl
- 8006736: 4013 andpl r3, r2
- 8006738: 430b orrmi r3, r1
- 800673a: 02e6 lsls r6, r4, #11
- 800673c: f8cc 3004 str.w r3, [ip, #4]
- 8006740: f8dc 3008 ldr.w r3, [ip, #8]
- 8006744: bf54 ite pl
- 8006746: 4013 andpl r3, r2
- 8006748: 430b orrmi r3, r1
- 800674a: 02a4 lsls r4, r4, #10
- 800674c: f8cc 3008 str.w r3, [ip, #8]
- 8006750: f8dc 300c ldr.w r3, [ip, #12]
- 8006754: bf54 ite pl
- 8006756: 4013 andpl r3, r2
- 8006758: 430b orrmi r3, r1
- 800675a: 2d10 cmp r5, #16
- 800675c: f8cc 300c str.w r3, [ip, #12]
- 8006760: f47f af4a bne.w 80065f8 <HAL_GPIO_Init+0x20>
- 8006764: b003 add sp, #12
- 8006766: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 800676a: ea4f 0a45 mov.w sl, r5, lsl #1
- 800676e: 2203 movs r2, #3
- 8006770: f8d0 b000 ldr.w fp, [r0]
- 8006774: 3f01 subs r7, #1
- 8006776: ea04 0602 and.w r6, r4, r2
- 800677a: fa02 f20a lsl.w r2, r2, sl
- 800677e: 2f01 cmp r7, #1
- 8006780: ea6f 0202 mvn.w r2, r2
- 8006784: fa06 f60a lsl.w r6, r6, sl
- 8006788: ea02 0b0b and.w fp, r2, fp
- 800678c: ea46 060b orr.w r6, r6, fp
- 8006790: 6006 str r6, [r0, #0]
- 8006792: f63f af74 bhi.w 800667e <HAL_GPIO_Init+0xa6>
- 8006796: e760 b.n 800665a <HAL_GPIO_Init+0x82>
- 8006798: 2601 movs r6, #1
- 800679a: fa06 f303 lsl.w r3, r6, r3
- 800679e: 431a orrs r2, r3
- 80067a0: e7b8 b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067a2: 2602 movs r6, #2
- 80067a4: fa06 f303 lsl.w r3, r6, r3
- 80067a8: 431a orrs r2, r3
- 80067aa: e7b3 b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067ac: 2603 movs r6, #3
- 80067ae: fa06 f303 lsl.w r3, r6, r3
- 80067b2: 431a orrs r2, r3
- 80067b4: e7ae b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067b6: 2604 movs r6, #4
- 80067b8: fa06 f303 lsl.w r3, r6, r3
- 80067bc: 431a orrs r2, r3
- 80067be: e7a9 b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067c0: 2607 movs r6, #7
- 80067c2: fa06 f303 lsl.w r3, r6, r3
- 80067c6: 431a orrs r2, r3
- 80067c8: e7a4 b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067ca: 2605 movs r6, #5
- 80067cc: fa06 f303 lsl.w r3, r6, r3
- 80067d0: 431a orrs r2, r3
- 80067d2: e79f b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067d4: 2606 movs r6, #6
- 80067d6: fa06 f303 lsl.w r3, r6, r3
- 80067da: 431a orrs r2, r3
- 80067dc: e79a b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067de: 2608 movs r6, #8
- 80067e0: fa06 f303 lsl.w r3, r6, r3
- 80067e4: 431a orrs r2, r3
- 80067e6: e795 b.n 8006714 <HAL_GPIO_Init+0x13c>
- 80067e8: 40020000 .word 0x40020000
- 80067ec: 40020800 .word 0x40020800
- 80067f0: 40020c00 .word 0x40020c00
- 80067f4: 40021000 .word 0x40021000
- 80067f8: 40021400 .word 0x40021400
- 80067fc: 40021800 .word 0x40021800
- 8006800: 40021c00 .word 0x40021c00
- 8006804: 40022000 .word 0x40022000
- 8006808: 40022400 .word 0x40022400
- 800680c: 40013c00 .word 0x40013c00
- 8006810: 40023800 .word 0x40023800
-
-08006814 <HAL_GPIO_WritePin>:
- 8006814: b902 cbnz r2, 8006818 <HAL_GPIO_WritePin+0x4>
- 8006816: 0409 lsls r1, r1, #16
- 8006818: 6181 str r1, [r0, #24]
- 800681a: 4770 bx lr
-
-0800681c <HAL_RCC_OscConfig>:
- 800681c: 2800 cmp r0, #0
- 800681e: f000 8134 beq.w 8006a8a <HAL_RCC_OscConfig+0x26e>
- 8006822: 6803 ldr r3, [r0, #0]
- 8006824: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
- 8006828: 07dd lsls r5, r3, #31
- 800682a: b082 sub sp, #8
- 800682c: 4604 mov r4, r0
- 800682e: d535 bpl.n 800689c <HAL_RCC_OscConfig+0x80>
- 8006830: 49ab ldr r1, [pc, #684] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006832: 688a ldr r2, [r1, #8]
- 8006834: f002 020c and.w r2, r2, #12
- 8006838: 2a04 cmp r2, #4
- 800683a: f000 80fe beq.w 8006a3a <HAL_RCC_OscConfig+0x21e>
- 800683e: 688a ldr r2, [r1, #8]
- 8006840: f002 020c and.w r2, r2, #12
- 8006844: 2a08 cmp r2, #8
- 8006846: f000 80f4 beq.w 8006a32 <HAL_RCC_OscConfig+0x216>
- 800684a: 6863 ldr r3, [r4, #4]
- 800684c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8006850: d010 beq.n 8006874 <HAL_RCC_OscConfig+0x58>
- 8006852: 2b00 cmp r3, #0
- 8006854: f000 811b beq.w 8006a8e <HAL_RCC_OscConfig+0x272>
- 8006858: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 800685c: 4ba0 ldr r3, [pc, #640] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 800685e: 681a ldr r2, [r3, #0]
- 8006860: f000 8162 beq.w 8006b28 <HAL_RCC_OscConfig+0x30c>
- 8006864: f422 3280 bic.w r2, r2, #65536 ; 0x10000
- 8006868: 601a str r2, [r3, #0]
- 800686a: 681a ldr r2, [r3, #0]
- 800686c: f422 2280 bic.w r2, r2, #262144 ; 0x40000
- 8006870: 601a str r2, [r3, #0]
- 8006872: e004 b.n 800687e <HAL_RCC_OscConfig+0x62>
- 8006874: 4a9a ldr r2, [pc, #616] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006876: 6813 ldr r3, [r2, #0]
- 8006878: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 800687c: 6013 str r3, [r2, #0]
- 800687e: f7ff fc69 bl 8006154 <HAL_GetTick>
- 8006882: 4d97 ldr r5, [pc, #604] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006884: 4606 mov r6, r0
- 8006886: e005 b.n 8006894 <HAL_RCC_OscConfig+0x78>
- 8006888: f7ff fc64 bl 8006154 <HAL_GetTick>
- 800688c: 1b80 subs r0, r0, r6
- 800688e: 2864 cmp r0, #100 ; 0x64
- 8006890: f200 80ee bhi.w 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006894: 682b ldr r3, [r5, #0]
- 8006896: 039a lsls r2, r3, #14
- 8006898: d5f6 bpl.n 8006888 <HAL_RCC_OscConfig+0x6c>
- 800689a: 6823 ldr r3, [r4, #0]
- 800689c: 079f lsls r7, r3, #30
- 800689e: d442 bmi.n 8006926 <HAL_RCC_OscConfig+0x10a>
- 80068a0: 071a lsls r2, r3, #28
- 80068a2: d517 bpl.n 80068d4 <HAL_RCC_OscConfig+0xb8>
- 80068a4: 6963 ldr r3, [r4, #20]
- 80068a6: 2b00 cmp r3, #0
- 80068a8: f000 80b0 beq.w 8006a0c <HAL_RCC_OscConfig+0x1f0>
- 80068ac: 4b8c ldr r3, [pc, #560] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 80068ae: 6f5a ldr r2, [r3, #116] ; 0x74
- 80068b0: 461d mov r5, r3
- 80068b2: f042 0201 orr.w r2, r2, #1
- 80068b6: 675a str r2, [r3, #116] ; 0x74
- 80068b8: f7ff fc4c bl 8006154 <HAL_GetTick>
- 80068bc: 4606 mov r6, r0
- 80068be: e005 b.n 80068cc <HAL_RCC_OscConfig+0xb0>
- 80068c0: f7ff fc48 bl 8006154 <HAL_GetTick>
- 80068c4: 1b80 subs r0, r0, r6
- 80068c6: 2802 cmp r0, #2
- 80068c8: f200 80d2 bhi.w 8006a70 <HAL_RCC_OscConfig+0x254>
- 80068cc: 6f6b ldr r3, [r5, #116] ; 0x74
- 80068ce: 079b lsls r3, r3, #30
- 80068d0: d5f6 bpl.n 80068c0 <HAL_RCC_OscConfig+0xa4>
- 80068d2: 6823 ldr r3, [r4, #0]
- 80068d4: 075d lsls r5, r3, #29
- 80068d6: d56b bpl.n 80069b0 <HAL_RCC_OscConfig+0x194>
- 80068d8: 4b81 ldr r3, [pc, #516] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 80068da: 6c1a ldr r2, [r3, #64] ; 0x40
- 80068dc: 00d0 lsls r0, r2, #3
- 80068de: f100 80ed bmi.w 8006abc <HAL_RCC_OscConfig+0x2a0>
- 80068e2: 6c1a ldr r2, [r3, #64] ; 0x40
- 80068e4: 2501 movs r5, #1
- 80068e6: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
- 80068ea: 641a str r2, [r3, #64] ; 0x40
- 80068ec: 6c1b ldr r3, [r3, #64] ; 0x40
- 80068ee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80068f2: 9301 str r3, [sp, #4]
- 80068f4: 9b01 ldr r3, [sp, #4]
- 80068f6: 4b7b ldr r3, [pc, #492] ; (8006ae4 <HAL_RCC_OscConfig+0x2c8>)
- 80068f8: 681a ldr r2, [r3, #0]
- 80068fa: 05d1 lsls r1, r2, #23
- 80068fc: f140 80a7 bpl.w 8006a4e <HAL_RCC_OscConfig+0x232>
- 8006900: 68a3 ldr r3, [r4, #8]
- 8006902: 2b01 cmp r3, #1
- 8006904: d039 beq.n 800697a <HAL_RCC_OscConfig+0x15e>
- 8006906: 2b00 cmp r3, #0
- 8006908: f000 80da beq.w 8006ac0 <HAL_RCC_OscConfig+0x2a4>
- 800690c: 2b05 cmp r3, #5
- 800690e: 4b74 ldr r3, [pc, #464] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006910: 6f1a ldr r2, [r3, #112] ; 0x70
- 8006912: f000 8111 beq.w 8006b38 <HAL_RCC_OscConfig+0x31c>
- 8006916: f022 0201 bic.w r2, r2, #1
- 800691a: 671a str r2, [r3, #112] ; 0x70
- 800691c: 6f1a ldr r2, [r3, #112] ; 0x70
- 800691e: f022 0204 bic.w r2, r2, #4
- 8006922: 671a str r2, [r3, #112] ; 0x70
- 8006924: e02e b.n 8006984 <HAL_RCC_OscConfig+0x168>
- 8006926: 4a6e ldr r2, [pc, #440] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006928: 6891 ldr r1, [r2, #8]
- 800692a: f011 0f0c tst.w r1, #12
- 800692e: d062 beq.n 80069f6 <HAL_RCC_OscConfig+0x1da>
- 8006930: 6891 ldr r1, [r2, #8]
- 8006932: f001 010c and.w r1, r1, #12
- 8006936: 2908 cmp r1, #8
- 8006938: d05a beq.n 80069f0 <HAL_RCC_OscConfig+0x1d4>
- 800693a: 68e3 ldr r3, [r4, #12]
- 800693c: 2b00 cmp r3, #0
- 800693e: f000 80df beq.w 8006b00 <HAL_RCC_OscConfig+0x2e4>
- 8006942: 4b67 ldr r3, [pc, #412] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006944: 681a ldr r2, [r3, #0]
- 8006946: 461d mov r5, r3
- 8006948: f042 0201 orr.w r2, r2, #1
- 800694c: 601a str r2, [r3, #0]
- 800694e: f7ff fc01 bl 8006154 <HAL_GetTick>
- 8006952: 4606 mov r6, r0
- 8006954: e005 b.n 8006962 <HAL_RCC_OscConfig+0x146>
- 8006956: f7ff fbfd bl 8006154 <HAL_GetTick>
- 800695a: 1b80 subs r0, r0, r6
- 800695c: 2802 cmp r0, #2
- 800695e: f200 8087 bhi.w 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006962: 682b ldr r3, [r5, #0]
- 8006964: 0798 lsls r0, r3, #30
- 8006966: d5f6 bpl.n 8006956 <HAL_RCC_OscConfig+0x13a>
- 8006968: 682b ldr r3, [r5, #0]
- 800696a: 6922 ldr r2, [r4, #16]
- 800696c: f023 03f8 bic.w r3, r3, #248 ; 0xf8
- 8006970: ea43 03c2 orr.w r3, r3, r2, lsl #3
- 8006974: 602b str r3, [r5, #0]
- 8006976: 6823 ldr r3, [r4, #0]
- 8006978: e792 b.n 80068a0 <HAL_RCC_OscConfig+0x84>
- 800697a: 4a59 ldr r2, [pc, #356] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 800697c: 6f13 ldr r3, [r2, #112] ; 0x70
- 800697e: f043 0301 orr.w r3, r3, #1
- 8006982: 6713 str r3, [r2, #112] ; 0x70
- 8006984: f7ff fbe6 bl 8006154 <HAL_GetTick>
- 8006988: 4e55 ldr r6, [pc, #340] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 800698a: 4680 mov r8, r0
- 800698c: f241 3788 movw r7, #5000 ; 0x1388
- 8006990: e005 b.n 800699e <HAL_RCC_OscConfig+0x182>
- 8006992: f7ff fbdf bl 8006154 <HAL_GetTick>
- 8006996: eba0 0008 sub.w r0, r0, r8
- 800699a: 42b8 cmp r0, r7
- 800699c: d868 bhi.n 8006a70 <HAL_RCC_OscConfig+0x254>
- 800699e: 6f33 ldr r3, [r6, #112] ; 0x70
- 80069a0: 079b lsls r3, r3, #30
- 80069a2: d5f6 bpl.n 8006992 <HAL_RCC_OscConfig+0x176>
- 80069a4: b125 cbz r5, 80069b0 <HAL_RCC_OscConfig+0x194>
- 80069a6: 4a4e ldr r2, [pc, #312] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 80069a8: 6c13 ldr r3, [r2, #64] ; 0x40
- 80069aa: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 80069ae: 6413 str r3, [r2, #64] ; 0x40
- 80069b0: 69a3 ldr r3, [r4, #24]
- 80069b2: b1cb cbz r3, 80069e8 <HAL_RCC_OscConfig+0x1cc>
- 80069b4: 4a4a ldr r2, [pc, #296] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 80069b6: 6891 ldr r1, [r2, #8]
- 80069b8: f001 010c and.w r1, r1, #12
- 80069bc: 2908 cmp r1, #8
- 80069be: d021 beq.n 8006a04 <HAL_RCC_OscConfig+0x1e8>
- 80069c0: 2b02 cmp r3, #2
- 80069c2: 6813 ldr r3, [r2, #0]
- 80069c4: f000 80c0 beq.w 8006b48 <HAL_RCC_OscConfig+0x32c>
- 80069c8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80069cc: 4614 mov r4, r2
- 80069ce: 6013 str r3, [r2, #0]
- 80069d0: f7ff fbc0 bl 8006154 <HAL_GetTick>
- 80069d4: 4605 mov r5, r0
- 80069d6: e004 b.n 80069e2 <HAL_RCC_OscConfig+0x1c6>
- 80069d8: f7ff fbbc bl 8006154 <HAL_GetTick>
- 80069dc: 1b40 subs r0, r0, r5
- 80069de: 2802 cmp r0, #2
- 80069e0: d846 bhi.n 8006a70 <HAL_RCC_OscConfig+0x254>
- 80069e2: 6823 ldr r3, [r4, #0]
- 80069e4: 019b lsls r3, r3, #6
- 80069e6: d4f7 bmi.n 80069d8 <HAL_RCC_OscConfig+0x1bc>
- 80069e8: 2000 movs r0, #0
- 80069ea: b002 add sp, #8
- 80069ec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 80069f0: 6852 ldr r2, [r2, #4]
- 80069f2: 0256 lsls r6, r2, #9
- 80069f4: d4a1 bmi.n 800693a <HAL_RCC_OscConfig+0x11e>
- 80069f6: 4a3a ldr r2, [pc, #232] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 80069f8: 6812 ldr r2, [r2, #0]
- 80069fa: 0795 lsls r5, r2, #30
- 80069fc: d53c bpl.n 8006a78 <HAL_RCC_OscConfig+0x25c>
- 80069fe: 68e2 ldr r2, [r4, #12]
- 8006a00: 2a01 cmp r2, #1
- 8006a02: d039 beq.n 8006a78 <HAL_RCC_OscConfig+0x25c>
- 8006a04: 2001 movs r0, #1
- 8006a06: b002 add sp, #8
- 8006a08: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8006a0c: 4b34 ldr r3, [pc, #208] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006a0e: 6f5a ldr r2, [r3, #116] ; 0x74
- 8006a10: 461d mov r5, r3
- 8006a12: f022 0201 bic.w r2, r2, #1
- 8006a16: 675a str r2, [r3, #116] ; 0x74
- 8006a18: f7ff fb9c bl 8006154 <HAL_GetTick>
- 8006a1c: 4606 mov r6, r0
- 8006a1e: e004 b.n 8006a2a <HAL_RCC_OscConfig+0x20e>
- 8006a20: f7ff fb98 bl 8006154 <HAL_GetTick>
- 8006a24: 1b80 subs r0, r0, r6
- 8006a26: 2802 cmp r0, #2
- 8006a28: d822 bhi.n 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006a2a: 6f6b ldr r3, [r5, #116] ; 0x74
- 8006a2c: 079f lsls r7, r3, #30
- 8006a2e: d4f7 bmi.n 8006a20 <HAL_RCC_OscConfig+0x204>
- 8006a30: e74f b.n 80068d2 <HAL_RCC_OscConfig+0xb6>
- 8006a32: 684a ldr r2, [r1, #4]
- 8006a34: 0250 lsls r0, r2, #9
- 8006a36: f57f af08 bpl.w 800684a <HAL_RCC_OscConfig+0x2e>
- 8006a3a: 4a29 ldr r2, [pc, #164] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006a3c: 6812 ldr r2, [r2, #0]
- 8006a3e: 0391 lsls r1, r2, #14
- 8006a40: f57f af2c bpl.w 800689c <HAL_RCC_OscConfig+0x80>
- 8006a44: 6862 ldr r2, [r4, #4]
- 8006a46: 2a00 cmp r2, #0
- 8006a48: f47f af28 bne.w 800689c <HAL_RCC_OscConfig+0x80>
- 8006a4c: e7da b.n 8006a04 <HAL_RCC_OscConfig+0x1e8>
- 8006a4e: 681a ldr r2, [r3, #0]
- 8006a50: 461e mov r6, r3
- 8006a52: f442 7280 orr.w r2, r2, #256 ; 0x100
- 8006a56: 601a str r2, [r3, #0]
- 8006a58: f7ff fb7c bl 8006154 <HAL_GetTick>
- 8006a5c: 4607 mov r7, r0
- 8006a5e: 6833 ldr r3, [r6, #0]
- 8006a60: 05da lsls r2, r3, #23
- 8006a62: f53f af4d bmi.w 8006900 <HAL_RCC_OscConfig+0xe4>
- 8006a66: f7ff fb75 bl 8006154 <HAL_GetTick>
- 8006a6a: 1bc0 subs r0, r0, r7
- 8006a6c: 2864 cmp r0, #100 ; 0x64
- 8006a6e: d9f6 bls.n 8006a5e <HAL_RCC_OscConfig+0x242>
- 8006a70: 2003 movs r0, #3
- 8006a72: b002 add sp, #8
- 8006a74: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8006a78: 4919 ldr r1, [pc, #100] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006a7a: 6920 ldr r0, [r4, #16]
- 8006a7c: 680a ldr r2, [r1, #0]
- 8006a7e: f022 02f8 bic.w r2, r2, #248 ; 0xf8
- 8006a82: ea42 02c0 orr.w r2, r2, r0, lsl #3
- 8006a86: 600a str r2, [r1, #0]
- 8006a88: e70a b.n 80068a0 <HAL_RCC_OscConfig+0x84>
- 8006a8a: 2001 movs r0, #1
- 8006a8c: 4770 bx lr
- 8006a8e: 4b14 ldr r3, [pc, #80] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006a90: 681a ldr r2, [r3, #0]
- 8006a92: 461d mov r5, r3
- 8006a94: f422 3280 bic.w r2, r2, #65536 ; 0x10000
- 8006a98: 601a str r2, [r3, #0]
- 8006a9a: 681a ldr r2, [r3, #0]
- 8006a9c: f422 2280 bic.w r2, r2, #262144 ; 0x40000
- 8006aa0: 601a str r2, [r3, #0]
- 8006aa2: f7ff fb57 bl 8006154 <HAL_GetTick>
- 8006aa6: 4606 mov r6, r0
- 8006aa8: e004 b.n 8006ab4 <HAL_RCC_OscConfig+0x298>
- 8006aaa: f7ff fb53 bl 8006154 <HAL_GetTick>
- 8006aae: 1b80 subs r0, r0, r6
- 8006ab0: 2864 cmp r0, #100 ; 0x64
- 8006ab2: d8dd bhi.n 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006ab4: 682b ldr r3, [r5, #0]
- 8006ab6: 039b lsls r3, r3, #14
- 8006ab8: d4f7 bmi.n 8006aaa <HAL_RCC_OscConfig+0x28e>
- 8006aba: e6ee b.n 800689a <HAL_RCC_OscConfig+0x7e>
- 8006abc: 2500 movs r5, #0
- 8006abe: e71a b.n 80068f6 <HAL_RCC_OscConfig+0xda>
- 8006ac0: 4b07 ldr r3, [pc, #28] ; (8006ae0 <HAL_RCC_OscConfig+0x2c4>)
- 8006ac2: f241 3888 movw r8, #5000 ; 0x1388
- 8006ac6: 6f1a ldr r2, [r3, #112] ; 0x70
- 8006ac8: 461e mov r6, r3
- 8006aca: f022 0201 bic.w r2, r2, #1
- 8006ace: 671a str r2, [r3, #112] ; 0x70
- 8006ad0: 6f1a ldr r2, [r3, #112] ; 0x70
- 8006ad2: f022 0204 bic.w r2, r2, #4
- 8006ad6: 671a str r2, [r3, #112] ; 0x70
- 8006ad8: f7ff fb3c bl 8006154 <HAL_GetTick>
- 8006adc: 4607 mov r7, r0
- 8006ade: e008 b.n 8006af2 <HAL_RCC_OscConfig+0x2d6>
- 8006ae0: 40023800 .word 0x40023800
- 8006ae4: 40007000 .word 0x40007000
- 8006ae8: f7ff fb34 bl 8006154 <HAL_GetTick>
- 8006aec: 1bc0 subs r0, r0, r7
- 8006aee: 4540 cmp r0, r8
- 8006af0: d8be bhi.n 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006af2: 6f33 ldr r3, [r6, #112] ; 0x70
- 8006af4: 0798 lsls r0, r3, #30
- 8006af6: d4f7 bmi.n 8006ae8 <HAL_RCC_OscConfig+0x2cc>
- 8006af8: 2d00 cmp r5, #0
- 8006afa: f43f af59 beq.w 80069b0 <HAL_RCC_OscConfig+0x194>
- 8006afe: e752 b.n 80069a6 <HAL_RCC_OscConfig+0x18a>
- 8006b00: 4b2c ldr r3, [pc, #176] ; (8006bb4 <HAL_RCC_OscConfig+0x398>)
- 8006b02: 681a ldr r2, [r3, #0]
- 8006b04: 461d mov r5, r3
- 8006b06: f022 0201 bic.w r2, r2, #1
- 8006b0a: 601a str r2, [r3, #0]
- 8006b0c: f7ff fb22 bl 8006154 <HAL_GetTick>
- 8006b10: 4606 mov r6, r0
- 8006b12: e004 b.n 8006b1e <HAL_RCC_OscConfig+0x302>
- 8006b14: f7ff fb1e bl 8006154 <HAL_GetTick>
- 8006b18: 1b80 subs r0, r0, r6
- 8006b1a: 2802 cmp r0, #2
- 8006b1c: d8a8 bhi.n 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006b1e: 682b ldr r3, [r5, #0]
- 8006b20: 0799 lsls r1, r3, #30
- 8006b22: d4f7 bmi.n 8006b14 <HAL_RCC_OscConfig+0x2f8>
- 8006b24: 6823 ldr r3, [r4, #0]
- 8006b26: e6bb b.n 80068a0 <HAL_RCC_OscConfig+0x84>
- 8006b28: f442 2280 orr.w r2, r2, #262144 ; 0x40000
- 8006b2c: 601a str r2, [r3, #0]
- 8006b2e: 681a ldr r2, [r3, #0]
- 8006b30: f442 3280 orr.w r2, r2, #65536 ; 0x10000
- 8006b34: 601a str r2, [r3, #0]
- 8006b36: e6a2 b.n 800687e <HAL_RCC_OscConfig+0x62>
- 8006b38: f042 0204 orr.w r2, r2, #4
- 8006b3c: 671a str r2, [r3, #112] ; 0x70
- 8006b3e: 6f1a ldr r2, [r3, #112] ; 0x70
- 8006b40: f042 0201 orr.w r2, r2, #1
- 8006b44: 671a str r2, [r3, #112] ; 0x70
- 8006b46: e71d b.n 8006984 <HAL_RCC_OscConfig+0x168>
- 8006b48: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8006b4c: 4615 mov r5, r2
- 8006b4e: 6013 str r3, [r2, #0]
- 8006b50: f7ff fb00 bl 8006154 <HAL_GetTick>
- 8006b54: 4606 mov r6, r0
- 8006b56: e004 b.n 8006b62 <HAL_RCC_OscConfig+0x346>
- 8006b58: f7ff fafc bl 8006154 <HAL_GetTick>
- 8006b5c: 1b80 subs r0, r0, r6
- 8006b5e: 2802 cmp r0, #2
- 8006b60: d886 bhi.n 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006b62: 682b ldr r3, [r5, #0]
- 8006b64: 0199 lsls r1, r3, #6
- 8006b66: d4f7 bmi.n 8006b58 <HAL_RCC_OscConfig+0x33c>
- 8006b68: e9d4 3207 ldrd r3, r2, [r4, #28]
- 8006b6c: 6a61 ldr r1, [r4, #36] ; 0x24
- 8006b6e: 4313 orrs r3, r2
- 8006b70: e9d4 200a ldrd r2, r0, [r4, #40] ; 0x28
- 8006b74: ea43 1381 orr.w r3, r3, r1, lsl #6
- 8006b78: 6b21 ldr r1, [r4, #48] ; 0x30
- 8006b7a: 0852 lsrs r2, r2, #1
- 8006b7c: 4c0d ldr r4, [pc, #52] ; (8006bb4 <HAL_RCC_OscConfig+0x398>)
- 8006b7e: ea43 6300 orr.w r3, r3, r0, lsl #24
- 8006b82: 3a01 subs r2, #1
- 8006b84: ea43 7301 orr.w r3, r3, r1, lsl #28
- 8006b88: ea43 4302 orr.w r3, r3, r2, lsl #16
- 8006b8c: 606b str r3, [r5, #4]
- 8006b8e: 682b ldr r3, [r5, #0]
- 8006b90: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 8006b94: 602b str r3, [r5, #0]
- 8006b96: f7ff fadd bl 8006154 <HAL_GetTick>
- 8006b9a: 4605 mov r5, r0
- 8006b9c: e005 b.n 8006baa <HAL_RCC_OscConfig+0x38e>
- 8006b9e: f7ff fad9 bl 8006154 <HAL_GetTick>
- 8006ba2: 1b40 subs r0, r0, r5
- 8006ba4: 2802 cmp r0, #2
- 8006ba6: f63f af63 bhi.w 8006a70 <HAL_RCC_OscConfig+0x254>
- 8006baa: 6823 ldr r3, [r4, #0]
- 8006bac: 019a lsls r2, r3, #6
- 8006bae: d5f6 bpl.n 8006b9e <HAL_RCC_OscConfig+0x382>
- 8006bb0: e71a b.n 80069e8 <HAL_RCC_OscConfig+0x1cc>
- 8006bb2: bf00 nop
- 8006bb4: 40023800 .word 0x40023800
-
-08006bb8 <HAL_RCC_ClockConfig>:
- 8006bb8: b178 cbz r0, 8006bda <HAL_RCC_ClockConfig+0x22>
- 8006bba: 4a5e ldr r2, [pc, #376] ; (8006d34 <HAL_RCC_ClockConfig+0x17c>)
- 8006bbc: 6813 ldr r3, [r2, #0]
- 8006bbe: f003 030f and.w r3, r3, #15
- 8006bc2: 428b cmp r3, r1
- 8006bc4: d20b bcs.n 8006bde <HAL_RCC_ClockConfig+0x26>
- 8006bc6: 6813 ldr r3, [r2, #0]
- 8006bc8: f023 030f bic.w r3, r3, #15
- 8006bcc: 430b orrs r3, r1
- 8006bce: 6013 str r3, [r2, #0]
- 8006bd0: 6813 ldr r3, [r2, #0]
- 8006bd2: f003 030f and.w r3, r3, #15
- 8006bd6: 428b cmp r3, r1
- 8006bd8: d001 beq.n 8006bde <HAL_RCC_ClockConfig+0x26>
- 8006bda: 2001 movs r0, #1
- 8006bdc: 4770 bx lr
- 8006bde: 6803 ldr r3, [r0, #0]
- 8006be0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
- 8006be4: 079d lsls r5, r3, #30
- 8006be6: d514 bpl.n 8006c12 <HAL_RCC_ClockConfig+0x5a>
- 8006be8: 075c lsls r4, r3, #29
- 8006bea: d504 bpl.n 8006bf6 <HAL_RCC_ClockConfig+0x3e>
- 8006bec: 4c52 ldr r4, [pc, #328] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006bee: 68a2 ldr r2, [r4, #8]
- 8006bf0: f442 52e0 orr.w r2, r2, #7168 ; 0x1c00
- 8006bf4: 60a2 str r2, [r4, #8]
- 8006bf6: 071a lsls r2, r3, #28
- 8006bf8: d504 bpl.n 8006c04 <HAL_RCC_ClockConfig+0x4c>
- 8006bfa: 4c4f ldr r4, [pc, #316] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006bfc: 68a2 ldr r2, [r4, #8]
- 8006bfe: f442 4260 orr.w r2, r2, #57344 ; 0xe000
- 8006c02: 60a2 str r2, [r4, #8]
- 8006c04: 4c4c ldr r4, [pc, #304] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006c06: 6885 ldr r5, [r0, #8]
- 8006c08: 68a2 ldr r2, [r4, #8]
- 8006c0a: f022 02f0 bic.w r2, r2, #240 ; 0xf0
- 8006c0e: 432a orrs r2, r5
- 8006c10: 60a2 str r2, [r4, #8]
- 8006c12: 07df lsls r7, r3, #31
- 8006c14: 4604 mov r4, r0
- 8006c16: 460d mov r5, r1
- 8006c18: d521 bpl.n 8006c5e <HAL_RCC_ClockConfig+0xa6>
- 8006c1a: 6842 ldr r2, [r0, #4]
- 8006c1c: 4b46 ldr r3, [pc, #280] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006c1e: 2a01 cmp r2, #1
- 8006c20: 681b ldr r3, [r3, #0]
- 8006c22: d063 beq.n 8006cec <HAL_RCC_ClockConfig+0x134>
- 8006c24: 2a02 cmp r2, #2
- 8006c26: d078 beq.n 8006d1a <HAL_RCC_ClockConfig+0x162>
- 8006c28: 0799 lsls r1, r3, #30
- 8006c2a: d528 bpl.n 8006c7e <HAL_RCC_ClockConfig+0xc6>
- 8006c2c: 4942 ldr r1, [pc, #264] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006c2e: f241 3888 movw r8, #5000 ; 0x1388
- 8006c32: 688b ldr r3, [r1, #8]
- 8006c34: 460e mov r6, r1
- 8006c36: f023 0303 bic.w r3, r3, #3
- 8006c3a: 4313 orrs r3, r2
- 8006c3c: 608b str r3, [r1, #8]
- 8006c3e: f7ff fa89 bl 8006154 <HAL_GetTick>
- 8006c42: 4607 mov r7, r0
- 8006c44: e004 b.n 8006c50 <HAL_RCC_ClockConfig+0x98>
- 8006c46: f7ff fa85 bl 8006154 <HAL_GetTick>
- 8006c4a: 1bc0 subs r0, r0, r7
- 8006c4c: 4540 cmp r0, r8
- 8006c4e: d862 bhi.n 8006d16 <HAL_RCC_ClockConfig+0x15e>
- 8006c50: 68b3 ldr r3, [r6, #8]
- 8006c52: 6862 ldr r2, [r4, #4]
- 8006c54: f003 030c and.w r3, r3, #12
- 8006c58: ebb3 0f82 cmp.w r3, r2, lsl #2
- 8006c5c: d1f3 bne.n 8006c46 <HAL_RCC_ClockConfig+0x8e>
- 8006c5e: 4a35 ldr r2, [pc, #212] ; (8006d34 <HAL_RCC_ClockConfig+0x17c>)
- 8006c60: 6813 ldr r3, [r2, #0]
- 8006c62: f003 030f and.w r3, r3, #15
- 8006c66: 42ab cmp r3, r5
- 8006c68: d90c bls.n 8006c84 <HAL_RCC_ClockConfig+0xcc>
- 8006c6a: 6813 ldr r3, [r2, #0]
- 8006c6c: f023 030f bic.w r3, r3, #15
- 8006c70: 432b orrs r3, r5
- 8006c72: 6013 str r3, [r2, #0]
- 8006c74: 6813 ldr r3, [r2, #0]
- 8006c76: f003 030f and.w r3, r3, #15
- 8006c7a: 42ab cmp r3, r5
- 8006c7c: d002 beq.n 8006c84 <HAL_RCC_ClockConfig+0xcc>
- 8006c7e: 2001 movs r0, #1
- 8006c80: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8006c84: 6823 ldr r3, [r4, #0]
- 8006c86: 075a lsls r2, r3, #29
- 8006c88: d506 bpl.n 8006c98 <HAL_RCC_ClockConfig+0xe0>
- 8006c8a: 492b ldr r1, [pc, #172] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006c8c: 68e0 ldr r0, [r4, #12]
- 8006c8e: 688a ldr r2, [r1, #8]
- 8006c90: f422 52e0 bic.w r2, r2, #7168 ; 0x1c00
- 8006c94: 4302 orrs r2, r0
- 8006c96: 608a str r2, [r1, #8]
- 8006c98: 071b lsls r3, r3, #28
- 8006c9a: d507 bpl.n 8006cac <HAL_RCC_ClockConfig+0xf4>
- 8006c9c: 4a26 ldr r2, [pc, #152] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006c9e: 6921 ldr r1, [r4, #16]
- 8006ca0: 6893 ldr r3, [r2, #8]
- 8006ca2: f423 4360 bic.w r3, r3, #57344 ; 0xe000
- 8006ca6: ea43 03c1 orr.w r3, r3, r1, lsl #3
- 8006caa: 6093 str r3, [r2, #8]
- 8006cac: 4922 ldr r1, [pc, #136] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006cae: 688b ldr r3, [r1, #8]
- 8006cb0: f003 030c and.w r3, r3, #12
- 8006cb4: 2b04 cmp r3, #4
- 8006cb6: d01c beq.n 8006cf2 <HAL_RCC_ClockConfig+0x13a>
- 8006cb8: 2b08 cmp r3, #8
- 8006cba: d12a bne.n 8006d12 <HAL_RCC_ClockConfig+0x15a>
- 8006cbc: 684a ldr r2, [r1, #4]
- 8006cbe: 684b ldr r3, [r1, #4]
- 8006cc0: f002 023f and.w r2, r2, #63 ; 0x3f
- 8006cc4: 6849 ldr r1, [r1, #4]
- 8006cc6: f413 0380 ands.w r3, r3, #4194304 ; 0x400000
- 8006cca: d129 bne.n 8006d20 <HAL_RCC_ClockConfig+0x168>
- 8006ccc: 481b ldr r0, [pc, #108] ; (8006d3c <HAL_RCC_ClockConfig+0x184>)
- 8006cce: f3c1 1188 ubfx r1, r1, #6, #9
- 8006cd2: fba1 0100 umull r0, r1, r1, r0
- 8006cd6: f7f9 fab7 bl 8000248 <__aeabi_uldivmod>
- 8006cda: 4b17 ldr r3, [pc, #92] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006cdc: 685b ldr r3, [r3, #4]
- 8006cde: f3c3 4301 ubfx r3, r3, #16, #2
- 8006ce2: 3301 adds r3, #1
- 8006ce4: 005b lsls r3, r3, #1
- 8006ce6: fbb0 f3f3 udiv r3, r0, r3
- 8006cea: e003 b.n 8006cf4 <HAL_RCC_ClockConfig+0x13c>
- 8006cec: 039e lsls r6, r3, #14
- 8006cee: d49d bmi.n 8006c2c <HAL_RCC_ClockConfig+0x74>
- 8006cf0: e7c5 b.n 8006c7e <HAL_RCC_ClockConfig+0xc6>
- 8006cf2: 4b13 ldr r3, [pc, #76] ; (8006d40 <HAL_RCC_ClockConfig+0x188>)
- 8006cf4: 4a10 ldr r2, [pc, #64] ; (8006d38 <HAL_RCC_ClockConfig+0x180>)
- 8006cf6: 2000 movs r0, #0
- 8006cf8: 4c12 ldr r4, [pc, #72] ; (8006d44 <HAL_RCC_ClockConfig+0x18c>)
- 8006cfa: 6892 ldr r2, [r2, #8]
- 8006cfc: 4912 ldr r1, [pc, #72] ; (8006d48 <HAL_RCC_ClockConfig+0x190>)
- 8006cfe: f3c2 1203 ubfx r2, r2, #4, #4
- 8006d02: 5ca2 ldrb r2, [r4, r2]
- 8006d04: 40d3 lsrs r3, r2
- 8006d06: 600b str r3, [r1, #0]
- 8006d08: f7ff f9e8 bl 80060dc <HAL_InitTick>
- 8006d0c: 2000 movs r0, #0
- 8006d0e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8006d12: 4b0a ldr r3, [pc, #40] ; (8006d3c <HAL_RCC_ClockConfig+0x184>)
- 8006d14: e7ee b.n 8006cf4 <HAL_RCC_ClockConfig+0x13c>
- 8006d16: 2003 movs r0, #3
- 8006d18: e7b2 b.n 8006c80 <HAL_RCC_ClockConfig+0xc8>
- 8006d1a: 0198 lsls r0, r3, #6
- 8006d1c: d486 bmi.n 8006c2c <HAL_RCC_ClockConfig+0x74>
- 8006d1e: e7ae b.n 8006c7e <HAL_RCC_ClockConfig+0xc6>
- 8006d20: 4807 ldr r0, [pc, #28] ; (8006d40 <HAL_RCC_ClockConfig+0x188>)
- 8006d22: f3c1 1188 ubfx r1, r1, #6, #9
- 8006d26: 2300 movs r3, #0
- 8006d28: fba1 0100 umull r0, r1, r1, r0
- 8006d2c: f7f9 fa8c bl 8000248 <__aeabi_uldivmod>
- 8006d30: e7d3 b.n 8006cda <HAL_RCC_ClockConfig+0x122>
- 8006d32: bf00 nop
- 8006d34: 40023c00 .word 0x40023c00
- 8006d38: 40023800 .word 0x40023800
- 8006d3c: 00f42400 .word 0x00f42400
- 8006d40: 017d7840 .word 0x017d7840
- 8006d44: 0800a490 .word 0x0800a490
- 8006d48: 20000010 .word 0x20000010
-
-08006d4c <HAL_RCC_GetSysClockFreq>:
- 8006d4c: 4916 ldr r1, [pc, #88] ; (8006da8 <HAL_RCC_GetSysClockFreq+0x5c>)
- 8006d4e: b508 push {r3, lr}
- 8006d50: 688b ldr r3, [r1, #8]
- 8006d52: f003 030c and.w r3, r3, #12
- 8006d56: 2b04 cmp r3, #4
- 8006d58: d01b beq.n 8006d92 <HAL_RCC_GetSysClockFreq+0x46>
- 8006d5a: 2b08 cmp r3, #8
- 8006d5c: d117 bne.n 8006d8e <HAL_RCC_GetSysClockFreq+0x42>
- 8006d5e: 684a ldr r2, [r1, #4]
- 8006d60: 684b ldr r3, [r1, #4]
- 8006d62: f002 023f and.w r2, r2, #63 ; 0x3f
- 8006d66: 6849 ldr r1, [r1, #4]
- 8006d68: f413 0380 ands.w r3, r3, #4194304 ; 0x400000
- 8006d6c: d113 bne.n 8006d96 <HAL_RCC_GetSysClockFreq+0x4a>
- 8006d6e: 480f ldr r0, [pc, #60] ; (8006dac <HAL_RCC_GetSysClockFreq+0x60>)
- 8006d70: f3c1 1188 ubfx r1, r1, #6, #9
- 8006d74: fba1 0100 umull r0, r1, r1, r0
- 8006d78: f7f9 fa66 bl 8000248 <__aeabi_uldivmod>
- 8006d7c: 4b0a ldr r3, [pc, #40] ; (8006da8 <HAL_RCC_GetSysClockFreq+0x5c>)
- 8006d7e: 685b ldr r3, [r3, #4]
- 8006d80: f3c3 4301 ubfx r3, r3, #16, #2
- 8006d84: 3301 adds r3, #1
- 8006d86: 005b lsls r3, r3, #1
- 8006d88: fbb0 f0f3 udiv r0, r0, r3
- 8006d8c: bd08 pop {r3, pc}
- 8006d8e: 4807 ldr r0, [pc, #28] ; (8006dac <HAL_RCC_GetSysClockFreq+0x60>)
- 8006d90: bd08 pop {r3, pc}
- 8006d92: 4807 ldr r0, [pc, #28] ; (8006db0 <HAL_RCC_GetSysClockFreq+0x64>)
- 8006d94: bd08 pop {r3, pc}
- 8006d96: 4806 ldr r0, [pc, #24] ; (8006db0 <HAL_RCC_GetSysClockFreq+0x64>)
- 8006d98: f3c1 1188 ubfx r1, r1, #6, #9
- 8006d9c: 2300 movs r3, #0
- 8006d9e: fba1 0100 umull r0, r1, r1, r0
- 8006da2: f7f9 fa51 bl 8000248 <__aeabi_uldivmod>
- 8006da6: e7e9 b.n 8006d7c <HAL_RCC_GetSysClockFreq+0x30>
- 8006da8: 40023800 .word 0x40023800
- 8006dac: 00f42400 .word 0x00f42400
- 8006db0: 017d7840 .word 0x017d7840
-
-08006db4 <HAL_RCC_GetPCLK1Freq>:
- 8006db4: 4b04 ldr r3, [pc, #16] ; (8006dc8 <HAL_RCC_GetPCLK1Freq+0x14>)
- 8006db6: 4a05 ldr r2, [pc, #20] ; (8006dcc <HAL_RCC_GetPCLK1Freq+0x18>)
- 8006db8: 689b ldr r3, [r3, #8]
- 8006dba: 4905 ldr r1, [pc, #20] ; (8006dd0 <HAL_RCC_GetPCLK1Freq+0x1c>)
- 8006dbc: f3c3 2382 ubfx r3, r3, #10, #3
- 8006dc0: 6808 ldr r0, [r1, #0]
- 8006dc2: 5cd3 ldrb r3, [r2, r3]
- 8006dc4: 40d8 lsrs r0, r3
- 8006dc6: 4770 bx lr
- 8006dc8: 40023800 .word 0x40023800
- 8006dcc: 0800a4a0 .word 0x0800a4a0
- 8006dd0: 20000010 .word 0x20000010
-
-08006dd4 <HAL_RCC_GetPCLK2Freq>:
- 8006dd4: 4b04 ldr r3, [pc, #16] ; (8006de8 <HAL_RCC_GetPCLK2Freq+0x14>)
- 8006dd6: 4a05 ldr r2, [pc, #20] ; (8006dec <HAL_RCC_GetPCLK2Freq+0x18>)
- 8006dd8: 689b ldr r3, [r3, #8]
- 8006dda: 4905 ldr r1, [pc, #20] ; (8006df0 <HAL_RCC_GetPCLK2Freq+0x1c>)
- 8006ddc: f3c3 3342 ubfx r3, r3, #13, #3
- 8006de0: 6808 ldr r0, [r1, #0]
- 8006de2: 5cd3 ldrb r3, [r2, r3]
- 8006de4: 40d8 lsrs r0, r3
- 8006de6: 4770 bx lr
- 8006de8: 40023800 .word 0x40023800
- 8006dec: 0800a4a0 .word 0x0800a4a0
- 8006df0: 20000010 .word 0x20000010
-
-08006df4 <HAL_RCCEx_PeriphCLKConfig>:
- 8006df4: 6803 ldr r3, [r0, #0]
- 8006df6: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
- 8006dfa: f013 0601 ands.w r6, r3, #1
- 8006dfe: b083 sub sp, #12
- 8006e00: 4604 mov r4, r0
- 8006e02: d00b beq.n 8006e1c <HAL_RCCEx_PeriphCLKConfig+0x28>
- 8006e04: 4a9f ldr r2, [pc, #636] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006e06: 6891 ldr r1, [r2, #8]
- 8006e08: f421 0100 bic.w r1, r1, #8388608 ; 0x800000
- 8006e0c: 6091 str r1, [r2, #8]
- 8006e0e: 6b46 ldr r6, [r0, #52] ; 0x34
- 8006e10: 6891 ldr r1, [r2, #8]
- 8006e12: 4331 orrs r1, r6
- 8006e14: fab6 f686 clz r6, r6
- 8006e18: 0976 lsrs r6, r6, #5
- 8006e1a: 6091 str r1, [r2, #8]
- 8006e1c: f413 2500 ands.w r5, r3, #524288 ; 0x80000
- 8006e20: d010 beq.n 8006e44 <HAL_RCCEx_PeriphCLKConfig+0x50>
- 8006e22: 4998 ldr r1, [pc, #608] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006e24: 6be5 ldr r5, [r4, #60] ; 0x3c
- 8006e26: f8d1 208c ldr.w r2, [r1, #140] ; 0x8c
- 8006e2a: f5b5 1f80 cmp.w r5, #1048576 ; 0x100000
- 8006e2e: f422 1240 bic.w r2, r2, #3145728 ; 0x300000
- 8006e32: ea42 0205 orr.w r2, r2, r5
- 8006e36: f8c1 208c str.w r2, [r1, #140] ; 0x8c
- 8006e3a: f000 81d4 beq.w 80071e6 <HAL_RCCEx_PeriphCLKConfig+0x3f2>
- 8006e3e: fab5 f585 clz r5, r5
- 8006e42: 096d lsrs r5, r5, #5
- 8006e44: 02d9 lsls r1, r3, #11
- 8006e46: d510 bpl.n 8006e6a <HAL_RCCEx_PeriphCLKConfig+0x76>
- 8006e48: 488e ldr r0, [pc, #568] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006e4a: 6c21 ldr r1, [r4, #64] ; 0x40
- 8006e4c: f8d0 208c ldr.w r2, [r0, #140] ; 0x8c
- 8006e50: f5b1 0f80 cmp.w r1, #4194304 ; 0x400000
- 8006e54: f422 0240 bic.w r2, r2, #12582912 ; 0xc00000
- 8006e58: ea42 0201 orr.w r2, r2, r1
- 8006e5c: f8c0 208c str.w r2, [r0, #140] ; 0x8c
- 8006e60: f000 81bf beq.w 80071e2 <HAL_RCCEx_PeriphCLKConfig+0x3ee>
- 8006e64: 2900 cmp r1, #0
- 8006e66: bf08 it eq
- 8006e68: 2501 moveq r5, #1
- 8006e6a: f013 7f80 tst.w r3, #16777216 ; 0x1000000
- 8006e6e: bf18 it ne
- 8006e70: 2601 movne r6, #1
- 8006e72: 069a lsls r2, r3, #26
- 8006e74: f100 816d bmi.w 8007152 <HAL_RCCEx_PeriphCLKConfig+0x35e>
- 8006e78: 06da lsls r2, r3, #27
- 8006e7a: d50c bpl.n 8006e96 <HAL_RCCEx_PeriphCLKConfig+0xa2>
- 8006e7c: 4a81 ldr r2, [pc, #516] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006e7e: f8d2 108c ldr.w r1, [r2, #140] ; 0x8c
- 8006e82: f021 7180 bic.w r1, r1, #16777216 ; 0x1000000
- 8006e86: f8c2 108c str.w r1, [r2, #140] ; 0x8c
- 8006e8a: f8d2 108c ldr.w r1, [r2, #140] ; 0x8c
- 8006e8e: 6ba0 ldr r0, [r4, #56] ; 0x38
- 8006e90: 4301 orrs r1, r0
- 8006e92: f8c2 108c str.w r1, [r2, #140] ; 0x8c
- 8006e96: 045f lsls r7, r3, #17
- 8006e98: d508 bpl.n 8006eac <HAL_RCCEx_PeriphCLKConfig+0xb8>
- 8006e9a: 497a ldr r1, [pc, #488] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006e9c: 6e60 ldr r0, [r4, #100] ; 0x64
- 8006e9e: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006ea2: f422 3240 bic.w r2, r2, #196608 ; 0x30000
- 8006ea6: 4302 orrs r2, r0
- 8006ea8: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006eac: 0418 lsls r0, r3, #16
- 8006eae: d508 bpl.n 8006ec2 <HAL_RCCEx_PeriphCLKConfig+0xce>
- 8006eb0: 4974 ldr r1, [pc, #464] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006eb2: 6ea0 ldr r0, [r4, #104] ; 0x68
- 8006eb4: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006eb8: f422 2240 bic.w r2, r2, #786432 ; 0xc0000
- 8006ebc: 4302 orrs r2, r0
- 8006ebe: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006ec2: 03d9 lsls r1, r3, #15
- 8006ec4: d508 bpl.n 8006ed8 <HAL_RCCEx_PeriphCLKConfig+0xe4>
- 8006ec6: 496f ldr r1, [pc, #444] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006ec8: 6ee0 ldr r0, [r4, #108] ; 0x6c
- 8006eca: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006ece: f422 1240 bic.w r2, r2, #3145728 ; 0x300000
- 8006ed2: 4302 orrs r2, r0
- 8006ed4: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006ed8: 039a lsls r2, r3, #14
- 8006eda: d508 bpl.n 8006eee <HAL_RCCEx_PeriphCLKConfig+0xfa>
- 8006edc: 4969 ldr r1, [pc, #420] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006ede: 6f20 ldr r0, [r4, #112] ; 0x70
- 8006ee0: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006ee4: f422 0240 bic.w r2, r2, #12582912 ; 0xc00000
- 8006ee8: 4302 orrs r2, r0
- 8006eea: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006eee: 065f lsls r7, r3, #25
- 8006ef0: d508 bpl.n 8006f04 <HAL_RCCEx_PeriphCLKConfig+0x110>
- 8006ef2: 4964 ldr r1, [pc, #400] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006ef4: 6c60 ldr r0, [r4, #68] ; 0x44
- 8006ef6: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006efa: f022 0203 bic.w r2, r2, #3
- 8006efe: 4302 orrs r2, r0
- 8006f00: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f04: 0618 lsls r0, r3, #24
- 8006f06: d508 bpl.n 8006f1a <HAL_RCCEx_PeriphCLKConfig+0x126>
- 8006f08: 495e ldr r1, [pc, #376] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006f0a: 6ca0 ldr r0, [r4, #72] ; 0x48
- 8006f0c: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006f10: f022 020c bic.w r2, r2, #12
- 8006f14: 4302 orrs r2, r0
- 8006f16: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f1a: 05d9 lsls r1, r3, #23
- 8006f1c: d508 bpl.n 8006f30 <HAL_RCCEx_PeriphCLKConfig+0x13c>
- 8006f1e: 4959 ldr r1, [pc, #356] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006f20: 6ce0 ldr r0, [r4, #76] ; 0x4c
- 8006f22: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006f26: f022 0230 bic.w r2, r2, #48 ; 0x30
- 8006f2a: 4302 orrs r2, r0
- 8006f2c: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f30: 059a lsls r2, r3, #22
- 8006f32: d508 bpl.n 8006f46 <HAL_RCCEx_PeriphCLKConfig+0x152>
- 8006f34: 4953 ldr r1, [pc, #332] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006f36: 6d20 ldr r0, [r4, #80] ; 0x50
- 8006f38: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006f3c: f022 02c0 bic.w r2, r2, #192 ; 0xc0
- 8006f40: 4302 orrs r2, r0
- 8006f42: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f46: 055f lsls r7, r3, #21
- 8006f48: d508 bpl.n 8006f5c <HAL_RCCEx_PeriphCLKConfig+0x168>
- 8006f4a: 494e ldr r1, [pc, #312] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006f4c: 6d60 ldr r0, [r4, #84] ; 0x54
- 8006f4e: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006f52: f422 7240 bic.w r2, r2, #768 ; 0x300
- 8006f56: 4302 orrs r2, r0
- 8006f58: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f5c: 0518 lsls r0, r3, #20
- 8006f5e: d508 bpl.n 8006f72 <HAL_RCCEx_PeriphCLKConfig+0x17e>
- 8006f60: 4948 ldr r1, [pc, #288] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006f62: 6da0 ldr r0, [r4, #88] ; 0x58
- 8006f64: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006f68: f422 6240 bic.w r2, r2, #3072 ; 0xc00
- 8006f6c: 4302 orrs r2, r0
- 8006f6e: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f72: 04d9 lsls r1, r3, #19
- 8006f74: d508 bpl.n 8006f88 <HAL_RCCEx_PeriphCLKConfig+0x194>
- 8006f76: 4943 ldr r1, [pc, #268] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006f78: 6de0 ldr r0, [r4, #92] ; 0x5c
- 8006f7a: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006f7e: f422 5240 bic.w r2, r2, #12288 ; 0x3000
- 8006f82: 4302 orrs r2, r0
- 8006f84: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f88: 049a lsls r2, r3, #18
- 8006f8a: d508 bpl.n 8006f9e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8006f8c: 493d ldr r1, [pc, #244] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006f8e: 6e20 ldr r0, [r4, #96] ; 0x60
- 8006f90: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006f94: f422 4240 bic.w r2, r2, #49152 ; 0xc000
- 8006f98: 4302 orrs r2, r0
- 8006f9a: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006f9e: 025f lsls r7, r3, #9
- 8006fa0: d508 bpl.n 8006fb4 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
- 8006fa2: 4938 ldr r1, [pc, #224] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006fa4: 6fa0 ldr r0, [r4, #120] ; 0x78
- 8006fa6: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006faa: f022 6280 bic.w r2, r2, #67108864 ; 0x4000000
- 8006fae: 4302 orrs r2, r0
- 8006fb0: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006fb4: 0298 lsls r0, r3, #10
- 8006fb6: d50c bpl.n 8006fd2 <HAL_RCCEx_PeriphCLKConfig+0x1de>
- 8006fb8: 4932 ldr r1, [pc, #200] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006fba: 6fe0 ldr r0, [r4, #124] ; 0x7c
- 8006fbc: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006fc0: f1b0 6f00 cmp.w r0, #134217728 ; 0x8000000
- 8006fc4: f022 6200 bic.w r2, r2, #134217728 ; 0x8000000
- 8006fc8: bf08 it eq
- 8006fca: 2501 moveq r5, #1
- 8006fcc: 4302 orrs r2, r0
- 8006fce: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006fd2: f013 0f08 tst.w r3, #8
- 8006fd6: bf18 it ne
- 8006fd8: 2501 movne r5, #1
- 8006fda: 0359 lsls r1, r3, #13
- 8006fdc: d508 bpl.n 8006ff0 <HAL_RCCEx_PeriphCLKConfig+0x1fc>
- 8006fde: 4929 ldr r1, [pc, #164] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006fe0: 6f60 ldr r0, [r4, #116] ; 0x74
- 8006fe2: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006fe6: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
- 8006fea: 4302 orrs r2, r0
- 8006fec: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8006ff0: 021a lsls r2, r3, #8
- 8006ff2: d509 bpl.n 8007008 <HAL_RCCEx_PeriphCLKConfig+0x214>
- 8006ff4: 4923 ldr r1, [pc, #140] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8006ff6: f8d4 0080 ldr.w r0, [r4, #128] ; 0x80
- 8006ffa: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8006ffe: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
- 8007002: 4302 orrs r2, r0
- 8007004: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8007008: 015f lsls r7, r3, #5
- 800700a: d509 bpl.n 8007020 <HAL_RCCEx_PeriphCLKConfig+0x22c>
- 800700c: 491d ldr r1, [pc, #116] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 800700e: f8d4 0084 ldr.w r0, [r4, #132] ; 0x84
- 8007012: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90
- 8007016: f022 5200 bic.w r2, r2, #536870912 ; 0x20000000
- 800701a: 4302 orrs r2, r0
- 800701c: f8c1 2090 str.w r2, [r1, #144] ; 0x90
- 8007020: 0118 lsls r0, r3, #4
- 8007022: d509 bpl.n 8007038 <HAL_RCCEx_PeriphCLKConfig+0x244>
- 8007024: 4917 ldr r1, [pc, #92] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8007026: f8d4 0088 ldr.w r0, [r4, #136] ; 0x88
- 800702a: f8d1 208c ldr.w r2, [r1, #140] ; 0x8c
- 800702e: f022 7200 bic.w r2, r2, #33554432 ; 0x2000000
- 8007032: 4302 orrs r2, r0
- 8007034: f8c1 208c str.w r2, [r1, #140] ; 0x8c
- 8007038: 00d9 lsls r1, r3, #3
- 800703a: d40b bmi.n 8007054 <HAL_RCCEx_PeriphCLKConfig+0x260>
- 800703c: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 8007040: d016 beq.n 8007070 <HAL_RCCEx_PeriphCLKConfig+0x27c>
- 8007042: 07f2 lsls r2, r6, #31
- 8007044: d414 bmi.n 8007070 <HAL_RCCEx_PeriphCLKConfig+0x27c>
- 8007046: 2d01 cmp r5, #1
- 8007048: f000 80d0 beq.w 80071ec <HAL_RCCEx_PeriphCLKConfig+0x3f8>
- 800704c: 2000 movs r0, #0
- 800704e: b003 add sp, #12
- 8007050: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
- 8007054: 490b ldr r1, [pc, #44] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8007056: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 800705a: f8d4 008c ldr.w r0, [r4, #140] ; 0x8c
- 800705e: f8d1 208c ldr.w r2, [r1, #140] ; 0x8c
- 8007062: f022 6280 bic.w r2, r2, #67108864 ; 0x4000000
- 8007066: ea42 0200 orr.w r2, r2, r0
- 800706a: f8c1 208c str.w r2, [r1, #140] ; 0x8c
- 800706e: d1e8 bne.n 8007042 <HAL_RCCEx_PeriphCLKConfig+0x24e>
- 8007070: 4b04 ldr r3, [pc, #16] ; (8007084 <HAL_RCCEx_PeriphCLKConfig+0x290>)
- 8007072: 681a ldr r2, [r3, #0]
- 8007074: 461e mov r6, r3
- 8007076: f022 6280 bic.w r2, r2, #67108864 ; 0x4000000
- 800707a: 601a str r2, [r3, #0]
- 800707c: f7ff f86a bl 8006154 <HAL_GetTick>
- 8007080: 4607 mov r7, r0
- 8007082: e006 b.n 8007092 <HAL_RCCEx_PeriphCLKConfig+0x29e>
- 8007084: 40023800 .word 0x40023800
- 8007088: f7ff f864 bl 8006154 <HAL_GetTick>
- 800708c: 1bc0 subs r0, r0, r7
- 800708e: 2864 cmp r0, #100 ; 0x64
- 8007090: d85b bhi.n 800714a <HAL_RCCEx_PeriphCLKConfig+0x356>
- 8007092: 6833 ldr r3, [r6, #0]
- 8007094: 011b lsls r3, r3, #4
- 8007096: d4f7 bmi.n 8007088 <HAL_RCCEx_PeriphCLKConfig+0x294>
- 8007098: 6823 ldr r3, [r4, #0]
- 800709a: 07df lsls r7, r3, #31
- 800709c: d512 bpl.n 80070c4 <HAL_RCCEx_PeriphCLKConfig+0x2d0>
- 800709e: 6b62 ldr r2, [r4, #52] ; 0x34
- 80070a0: b982 cbnz r2, 80070c4 <HAL_RCCEx_PeriphCLKConfig+0x2d0>
- 80070a2: f8d6 2084 ldr.w r2, [r6, #132] ; 0x84
- 80070a6: f8d6 7084 ldr.w r7, [r6, #132] ; 0x84
- 80070aa: f402 3240 and.w r2, r2, #196608 ; 0x30000
- 80070ae: 6860 ldr r0, [r4, #4]
- 80070b0: f007 6770 and.w r7, r7, #251658240 ; 0xf000000
- 80070b4: 68a1 ldr r1, [r4, #8]
- 80070b6: 433a orrs r2, r7
- 80070b8: ea42 1280 orr.w r2, r2, r0, lsl #6
- 80070bc: ea42 7201 orr.w r2, r2, r1, lsl #28
- 80070c0: f8c6 2084 str.w r2, [r6, #132] ; 0x84
- 80070c4: 031e lsls r6, r3, #12
- 80070c6: f100 810f bmi.w 80072e8 <HAL_RCCEx_PeriphCLKConfig+0x4f4>
- 80070ca: 02d8 lsls r0, r3, #11
- 80070cc: d504 bpl.n 80070d8 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
- 80070ce: 6c22 ldr r2, [r4, #64] ; 0x40
- 80070d0: f5b2 0f80 cmp.w r2, #4194304 ; 0x400000
- 80070d4: f000 810d beq.w 80072f2 <HAL_RCCEx_PeriphCLKConfig+0x4fe>
- 80070d8: 01d9 lsls r1, r3, #7
- 80070da: d511 bpl.n 8007100 <HAL_RCCEx_PeriphCLKConfig+0x30c>
- 80070dc: 4ea4 ldr r6, [pc, #656] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 80070de: 6860 ldr r0, [r4, #4]
- 80070e0: f8d6 2084 ldr.w r2, [r6, #132] ; 0x84
- 80070e4: f8d6 7084 ldr.w r7, [r6, #132] ; 0x84
- 80070e8: f002 6270 and.w r2, r2, #251658240 ; 0xf000000
- 80070ec: 6921 ldr r1, [r4, #16]
- 80070ee: f007 47e0 and.w r7, r7, #1879048192 ; 0x70000000
- 80070f2: 433a orrs r2, r7
- 80070f4: ea42 1280 orr.w r2, r2, r0, lsl #6
- 80070f8: ea42 4201 orr.w r2, r2, r1, lsl #16
- 80070fc: f8c6 2084 str.w r2, [r6, #132] ; 0x84
- 8007100: 019a lsls r2, r3, #6
- 8007102: d50d bpl.n 8007120 <HAL_RCCEx_PeriphCLKConfig+0x32c>
- 8007104: 6923 ldr r3, [r4, #16]
- 8007106: 6862 ldr r2, [r4, #4]
- 8007108: 041b lsls r3, r3, #16
- 800710a: e9d4 1002 ldrd r1, r0, [r4, #8]
- 800710e: ea43 1382 orr.w r3, r3, r2, lsl #6
- 8007112: 4a97 ldr r2, [pc, #604] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 8007114: ea43 6300 orr.w r3, r3, r0, lsl #24
- 8007118: ea43 7301 orr.w r3, r3, r1, lsl #28
- 800711c: f8c2 3084 str.w r3, [r2, #132] ; 0x84
- 8007120: 4b93 ldr r3, [pc, #588] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 8007122: 681a ldr r2, [r3, #0]
- 8007124: 461e mov r6, r3
- 8007126: f042 6280 orr.w r2, r2, #67108864 ; 0x4000000
- 800712a: 601a str r2, [r3, #0]
- 800712c: f7ff f812 bl 8006154 <HAL_GetTick>
- 8007130: 4607 mov r7, r0
- 8007132: e004 b.n 800713e <HAL_RCCEx_PeriphCLKConfig+0x34a>
- 8007134: f7ff f80e bl 8006154 <HAL_GetTick>
- 8007138: 1bc0 subs r0, r0, r7
- 800713a: 2864 cmp r0, #100 ; 0x64
- 800713c: d805 bhi.n 800714a <HAL_RCCEx_PeriphCLKConfig+0x356>
- 800713e: 6833 ldr r3, [r6, #0]
- 8007140: 011b lsls r3, r3, #4
- 8007142: d5f7 bpl.n 8007134 <HAL_RCCEx_PeriphCLKConfig+0x340>
- 8007144: 2d01 cmp r5, #1
- 8007146: d181 bne.n 800704c <HAL_RCCEx_PeriphCLKConfig+0x258>
- 8007148: e050 b.n 80071ec <HAL_RCCEx_PeriphCLKConfig+0x3f8>
- 800714a: 2003 movs r0, #3
- 800714c: b003 add sp, #12
- 800714e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
- 8007152: 4a87 ldr r2, [pc, #540] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 8007154: 4b87 ldr r3, [pc, #540] ; (8007374 <HAL_RCCEx_PeriphCLKConfig+0x580>)
- 8007156: 6c11 ldr r1, [r2, #64] ; 0x40
- 8007158: 461f mov r7, r3
- 800715a: f041 5180 orr.w r1, r1, #268435456 ; 0x10000000
- 800715e: 6411 str r1, [r2, #64] ; 0x40
- 8007160: 6c12 ldr r2, [r2, #64] ; 0x40
- 8007162: f002 5280 and.w r2, r2, #268435456 ; 0x10000000
- 8007166: 9201 str r2, [sp, #4]
- 8007168: 9a01 ldr r2, [sp, #4]
- 800716a: 681a ldr r2, [r3, #0]
- 800716c: f442 7280 orr.w r2, r2, #256 ; 0x100
- 8007170: 601a str r2, [r3, #0]
- 8007172: f7fe ffef bl 8006154 <HAL_GetTick>
- 8007176: 4680 mov r8, r0
- 8007178: e005 b.n 8007186 <HAL_RCCEx_PeriphCLKConfig+0x392>
- 800717a: f7fe ffeb bl 8006154 <HAL_GetTick>
- 800717e: eba0 0008 sub.w r0, r0, r8
- 8007182: 2864 cmp r0, #100 ; 0x64
- 8007184: d8e1 bhi.n 800714a <HAL_RCCEx_PeriphCLKConfig+0x356>
- 8007186: 683b ldr r3, [r7, #0]
- 8007188: 05db lsls r3, r3, #23
- 800718a: d5f6 bpl.n 800717a <HAL_RCCEx_PeriphCLKConfig+0x386>
- 800718c: 4a78 ldr r2, [pc, #480] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 800718e: 6b23 ldr r3, [r4, #48] ; 0x30
- 8007190: 6f11 ldr r1, [r2, #112] ; 0x70
- 8007192: f403 7040 and.w r0, r3, #768 ; 0x300
- 8007196: f411 7140 ands.w r1, r1, #768 ; 0x300
- 800719a: d011 beq.n 80071c0 <HAL_RCCEx_PeriphCLKConfig+0x3cc>
- 800719c: 4281 cmp r1, r0
- 800719e: d00f beq.n 80071c0 <HAL_RCCEx_PeriphCLKConfig+0x3cc>
- 80071a0: 6f11 ldr r1, [r2, #112] ; 0x70
- 80071a2: 6f17 ldr r7, [r2, #112] ; 0x70
- 80071a4: f421 7140 bic.w r1, r1, #768 ; 0x300
- 80071a8: f447 3780 orr.w r7, r7, #65536 ; 0x10000
- 80071ac: 6717 str r7, [r2, #112] ; 0x70
- 80071ae: 6f17 ldr r7, [r2, #112] ; 0x70
- 80071b0: f427 3780 bic.w r7, r7, #65536 ; 0x10000
- 80071b4: 6717 str r7, [r2, #112] ; 0x70
- 80071b6: 6711 str r1, [r2, #112] ; 0x70
- 80071b8: 6f11 ldr r1, [r2, #112] ; 0x70
- 80071ba: 07cf lsls r7, r1, #31
- 80071bc: f100 80c3 bmi.w 8007346 <HAL_RCCEx_PeriphCLKConfig+0x552>
- 80071c0: f5b0 7f40 cmp.w r0, #768 ; 0x300
- 80071c4: f000 80b1 beq.w 800732a <HAL_RCCEx_PeriphCLKConfig+0x536>
- 80071c8: 4969 ldr r1, [pc, #420] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 80071ca: 688a ldr r2, [r1, #8]
- 80071cc: f422 12f8 bic.w r2, r2, #2031616 ; 0x1f0000
- 80071d0: 608a str r2, [r1, #8]
- 80071d2: 4a67 ldr r2, [pc, #412] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 80071d4: f3c3 030b ubfx r3, r3, #0, #12
- 80071d8: 6f11 ldr r1, [r2, #112] ; 0x70
- 80071da: 430b orrs r3, r1
- 80071dc: 6713 str r3, [r2, #112] ; 0x70
- 80071de: 6823 ldr r3, [r4, #0]
- 80071e0: e64a b.n 8006e78 <HAL_RCCEx_PeriphCLKConfig+0x84>
- 80071e2: 2601 movs r6, #1
- 80071e4: e641 b.n 8006e6a <HAL_RCCEx_PeriphCLKConfig+0x76>
- 80071e6: 2500 movs r5, #0
- 80071e8: 2601 movs r6, #1
- 80071ea: e62b b.n 8006e44 <HAL_RCCEx_PeriphCLKConfig+0x50>
- 80071ec: 4b60 ldr r3, [pc, #384] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 80071ee: 681a ldr r2, [r3, #0]
- 80071f0: 461d mov r5, r3
- 80071f2: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
- 80071f6: 601a str r2, [r3, #0]
- 80071f8: f7fe ffac bl 8006154 <HAL_GetTick>
- 80071fc: 4606 mov r6, r0
- 80071fe: e004 b.n 800720a <HAL_RCCEx_PeriphCLKConfig+0x416>
- 8007200: f7fe ffa8 bl 8006154 <HAL_GetTick>
- 8007204: 1b80 subs r0, r0, r6
- 8007206: 2864 cmp r0, #100 ; 0x64
- 8007208: d89f bhi.n 800714a <HAL_RCCEx_PeriphCLKConfig+0x356>
- 800720a: 682b ldr r3, [r5, #0]
- 800720c: 009f lsls r7, r3, #2
- 800720e: d4f7 bmi.n 8007200 <HAL_RCCEx_PeriphCLKConfig+0x40c>
- 8007210: 6823 ldr r3, [r4, #0]
- 8007212: 031d lsls r5, r3, #12
- 8007214: f100 8092 bmi.w 800733c <HAL_RCCEx_PeriphCLKConfig+0x548>
- 8007218: 02d8 lsls r0, r3, #11
- 800721a: d51d bpl.n 8007258 <HAL_RCCEx_PeriphCLKConfig+0x464>
- 800721c: 6c22 ldr r2, [r4, #64] ; 0x40
- 800721e: b9da cbnz r2, 8007258 <HAL_RCCEx_PeriphCLKConfig+0x464>
- 8007220: 4953 ldr r1, [pc, #332] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 8007222: 6965 ldr r5, [r4, #20]
- 8007224: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88
- 8007228: f8d1 6088 ldr.w r6, [r1, #136] ; 0x88
- 800722c: f402 3240 and.w r2, r2, #196608 ; 0x30000
- 8007230: 69a0 ldr r0, [r4, #24]
- 8007232: f006 46e0 and.w r6, r6, #1879048192 ; 0x70000000
- 8007236: 4332 orrs r2, r6
- 8007238: ea42 1285 orr.w r2, r2, r5, lsl #6
- 800723c: ea42 6200 orr.w r2, r2, r0, lsl #24
- 8007240: f8c1 2088 str.w r2, [r1, #136] ; 0x88
- 8007244: f8d1 208c ldr.w r2, [r1, #140] ; 0x8c
- 8007248: 6aa0 ldr r0, [r4, #40] ; 0x28
- 800724a: f422 52f8 bic.w r2, r2, #7936 ; 0x1f00
- 800724e: 3801 subs r0, #1
- 8007250: ea42 2200 orr.w r2, r2, r0, lsl #8
- 8007254: f8c1 208c str.w r2, [r1, #140] ; 0x8c
- 8007258: 0299 lsls r1, r3, #10
- 800725a: d515 bpl.n 8007288 <HAL_RCCEx_PeriphCLKConfig+0x494>
- 800725c: 6fe2 ldr r2, [r4, #124] ; 0x7c
- 800725e: f1b2 6f00 cmp.w r2, #134217728 ; 0x8000000
- 8007262: d111 bne.n 8007288 <HAL_RCCEx_PeriphCLKConfig+0x494>
- 8007264: 4942 ldr r1, [pc, #264] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 8007266: 6965 ldr r5, [r4, #20]
- 8007268: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88
- 800726c: f8d1 6088 ldr.w r6, [r1, #136] ; 0x88
- 8007270: f002 6270 and.w r2, r2, #251658240 ; 0xf000000
- 8007274: 6a20 ldr r0, [r4, #32]
- 8007276: f006 46e0 and.w r6, r6, #1879048192 ; 0x70000000
- 800727a: 4332 orrs r2, r6
- 800727c: ea42 1285 orr.w r2, r2, r5, lsl #6
- 8007280: ea42 4200 orr.w r2, r2, r0, lsl #16
- 8007284: f8c1 2088 str.w r2, [r1, #136] ; 0x88
- 8007288: 071a lsls r2, r3, #28
- 800728a: d519 bpl.n 80072c0 <HAL_RCCEx_PeriphCLKConfig+0x4cc>
- 800728c: 4a38 ldr r2, [pc, #224] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 800728e: 6965 ldr r5, [r4, #20]
- 8007290: f8d2 1088 ldr.w r1, [r2, #136] ; 0x88
- 8007294: f8d2 3088 ldr.w r3, [r2, #136] ; 0x88
- 8007298: f001 6170 and.w r1, r1, #251658240 ; 0xf000000
- 800729c: 69e0 ldr r0, [r4, #28]
- 800729e: f403 3340 and.w r3, r3, #196608 ; 0x30000
- 80072a2: 430b orrs r3, r1
- 80072a4: ea43 1385 orr.w r3, r3, r5, lsl #6
- 80072a8: ea43 7300 orr.w r3, r3, r0, lsl #28
- 80072ac: f8c2 3088 str.w r3, [r2, #136] ; 0x88
- 80072b0: f8d2 308c ldr.w r3, [r2, #140] ; 0x8c
- 80072b4: 6ae1 ldr r1, [r4, #44] ; 0x2c
- 80072b6: f423 3340 bic.w r3, r3, #196608 ; 0x30000
- 80072ba: 430b orrs r3, r1
- 80072bc: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 80072c0: 4b2b ldr r3, [pc, #172] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 80072c2: 681a ldr r2, [r3, #0]
- 80072c4: 461c mov r4, r3
- 80072c6: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
- 80072ca: 601a str r2, [r3, #0]
- 80072cc: f7fe ff42 bl 8006154 <HAL_GetTick>
- 80072d0: 4605 mov r5, r0
- 80072d2: e005 b.n 80072e0 <HAL_RCCEx_PeriphCLKConfig+0x4ec>
- 80072d4: f7fe ff3e bl 8006154 <HAL_GetTick>
- 80072d8: 1b40 subs r0, r0, r5
- 80072da: 2864 cmp r0, #100 ; 0x64
- 80072dc: f63f af35 bhi.w 800714a <HAL_RCCEx_PeriphCLKConfig+0x356>
- 80072e0: 6823 ldr r3, [r4, #0]
- 80072e2: 009b lsls r3, r3, #2
- 80072e4: d5f6 bpl.n 80072d4 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
- 80072e6: e6b1 b.n 800704c <HAL_RCCEx_PeriphCLKConfig+0x258>
- 80072e8: 6be2 ldr r2, [r4, #60] ; 0x3c
- 80072ea: f5b2 1f80 cmp.w r2, #1048576 ; 0x100000
- 80072ee: f47f aeec bne.w 80070ca <HAL_RCCEx_PeriphCLKConfig+0x2d6>
- 80072f2: 4e1f ldr r6, [pc, #124] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 80072f4: 6860 ldr r0, [r4, #4]
- 80072f6: f8d6 2084 ldr.w r2, [r6, #132] ; 0x84
- 80072fa: f8d6 7084 ldr.w r7, [r6, #132] ; 0x84
- 80072fe: f402 3240 and.w r2, r2, #196608 ; 0x30000
- 8007302: 68e1 ldr r1, [r4, #12]
- 8007304: f007 47e0 and.w r7, r7, #1879048192 ; 0x70000000
- 8007308: 433a orrs r2, r7
- 800730a: ea42 1280 orr.w r2, r2, r0, lsl #6
- 800730e: ea42 6201 orr.w r2, r2, r1, lsl #24
- 8007312: f8c6 2084 str.w r2, [r6, #132] ; 0x84
- 8007316: f8d6 108c ldr.w r1, [r6, #140] ; 0x8c
- 800731a: 6a62 ldr r2, [r4, #36] ; 0x24
- 800731c: f021 011f bic.w r1, r1, #31
- 8007320: 3a01 subs r2, #1
- 8007322: 430a orrs r2, r1
- 8007324: f8c6 208c str.w r2, [r6, #140] ; 0x8c
- 8007328: e6d6 b.n 80070d8 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
- 800732a: 4811 ldr r0, [pc, #68] ; (8007370 <HAL_RCCEx_PeriphCLKConfig+0x57c>)
- 800732c: 4912 ldr r1, [pc, #72] ; (8007378 <HAL_RCCEx_PeriphCLKConfig+0x584>)
- 800732e: 6882 ldr r2, [r0, #8]
- 8007330: 4019 ands r1, r3
- 8007332: f422 12f8 bic.w r2, r2, #2031616 ; 0x1f0000
- 8007336: 430a orrs r2, r1
- 8007338: 6082 str r2, [r0, #8]
- 800733a: e74a b.n 80071d2 <HAL_RCCEx_PeriphCLKConfig+0x3de>
- 800733c: 6be2 ldr r2, [r4, #60] ; 0x3c
- 800733e: 2a00 cmp r2, #0
- 8007340: f43f af6e beq.w 8007220 <HAL_RCCEx_PeriphCLKConfig+0x42c>
- 8007344: e768 b.n 8007218 <HAL_RCCEx_PeriphCLKConfig+0x424>
- 8007346: 4617 mov r7, r2
- 8007348: f241 3888 movw r8, #5000 ; 0x1388
- 800734c: f7fe ff02 bl 8006154 <HAL_GetTick>
- 8007350: 4681 mov r9, r0
- 8007352: e006 b.n 8007362 <HAL_RCCEx_PeriphCLKConfig+0x56e>
- 8007354: f7fe fefe bl 8006154 <HAL_GetTick>
- 8007358: eba0 0009 sub.w r0, r0, r9
- 800735c: 4540 cmp r0, r8
- 800735e: f63f aef4 bhi.w 800714a <HAL_RCCEx_PeriphCLKConfig+0x356>
- 8007362: 6f3b ldr r3, [r7, #112] ; 0x70
- 8007364: 0799 lsls r1, r3, #30
- 8007366: d5f5 bpl.n 8007354 <HAL_RCCEx_PeriphCLKConfig+0x560>
- 8007368: 6b23 ldr r3, [r4, #48] ; 0x30
- 800736a: f403 7040 and.w r0, r3, #768 ; 0x300
- 800736e: e727 b.n 80071c0 <HAL_RCCEx_PeriphCLKConfig+0x3cc>
- 8007370: 40023800 .word 0x40023800
- 8007374: 40007000 .word 0x40007000
- 8007378: 0ffffcff .word 0x0ffffcff
-
-0800737c <HAL_TIM_Base_Init>:
- 800737c: 2800 cmp r0, #0
- 800737e: d065 beq.n 800744c <HAL_TIM_Base_Init+0xd0>
- 8007380: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8007382: f890 303d ldrb.w r3, [r0, #61] ; 0x3d
- 8007386: 4604 mov r4, r0
- 8007388: f003 02ff and.w r2, r3, #255 ; 0xff
- 800738c: 2b00 cmp r3, #0
- 800738e: d03b beq.n 8007408 <HAL_TIM_Base_Init+0x8c>
- 8007390: 6822 ldr r2, [r4, #0]
- 8007392: 2002 movs r0, #2
- 8007394: 4e36 ldr r6, [pc, #216] ; (8007470 <HAL_TIM_Base_Init+0xf4>)
- 8007396: 4f37 ldr r7, [pc, #220] ; (8007474 <HAL_TIM_Base_Init+0xf8>)
- 8007398: f1b2 4f80 cmp.w r2, #1073741824 ; 0x40000000
- 800739c: eba2 0606 sub.w r6, r2, r6
- 80073a0: f884 003d strb.w r0, [r4, #61] ; 0x3d
- 80073a4: eba2 0707 sub.w r7, r2, r7
- 80073a8: 6813 ldr r3, [r2, #0]
- 80073aa: fab6 f686 clz r6, r6
- 80073ae: fab7 f787 clz r7, r7
- 80073b2: ea4f 1656 mov.w r6, r6, lsr #5
- 80073b6: ea4f 1757 mov.w r7, r7, lsr #5
- 80073ba: d02a beq.n 8007412 <HAL_TIM_Base_Init+0x96>
- 80073bc: bb4e cbnz r6, 8007412 <HAL_TIM_Base_Init+0x96>
- 80073be: 492e ldr r1, [pc, #184] ; (8007478 <HAL_TIM_Base_Init+0xfc>)
- 80073c0: 428a cmp r2, r1
- 80073c2: d045 beq.n 8007450 <HAL_TIM_Base_Init+0xd4>
- 80073c4: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80073c8: 428a cmp r2, r1
- 80073ca: d041 beq.n 8007450 <HAL_TIM_Base_Init+0xd4>
- 80073cc: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80073d0: 428a cmp r2, r1
- 80073d2: d042 beq.n 800745a <HAL_TIM_Base_Init+0xde>
- 80073d4: 2f00 cmp r7, #0
- 80073d6: d140 bne.n 800745a <HAL_TIM_Base_Init+0xde>
- 80073d8: 4928 ldr r1, [pc, #160] ; (800747c <HAL_TIM_Base_Init+0x100>)
- 80073da: 428a cmp r2, r1
- 80073dc: d01e beq.n 800741c <HAL_TIM_Base_Init+0xa0>
- 80073de: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80073e2: 428a cmp r2, r1
- 80073e4: d01a beq.n 800741c <HAL_TIM_Base_Init+0xa0>
- 80073e6: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80073ea: 428a cmp r2, r1
- 80073ec: d016 beq.n 800741c <HAL_TIM_Base_Init+0xa0>
- 80073ee: f5a1 3198 sub.w r1, r1, #77824 ; 0x13000
- 80073f2: 428a cmp r2, r1
- 80073f4: d012 beq.n 800741c <HAL_TIM_Base_Init+0xa0>
- 80073f6: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80073fa: 428a cmp r2, r1
- 80073fc: d00e beq.n 800741c <HAL_TIM_Base_Init+0xa0>
- 80073fe: f501 6180 add.w r1, r1, #1024 ; 0x400
- 8007402: 428a cmp r2, r1
- 8007404: d10e bne.n 8007424 <HAL_TIM_Base_Init+0xa8>
- 8007406: e009 b.n 800741c <HAL_TIM_Base_Init+0xa0>
- 8007408: f880 203c strb.w r2, [r0, #60] ; 0x3c
- 800740c: f7fe fc64 bl 8005cd8 <HAL_TIM_Base_MspInit>
- 8007410: e7be b.n 8007390 <HAL_TIM_Base_Init+0x14>
- 8007412: f023 0570 bic.w r5, r3, #112 ; 0x70
- 8007416: 68a0 ldr r0, [r4, #8]
- 8007418: ea45 0300 orr.w r3, r5, r0
- 800741c: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8007420: 6920 ldr r0, [r4, #16]
- 8007422: 4303 orrs r3, r0
- 8007424: 69a1 ldr r1, [r4, #24]
- 8007426: f023 0380 bic.w r3, r3, #128 ; 0x80
- 800742a: 68e0 ldr r0, [r4, #12]
- 800742c: 430b orrs r3, r1
- 800742e: 6861 ldr r1, [r4, #4]
- 8007430: 6013 str r3, [r2, #0]
- 8007432: 62d0 str r0, [r2, #44] ; 0x2c
- 8007434: 6291 str r1, [r2, #40] ; 0x28
- 8007436: b936 cbnz r6, 8007446 <HAL_TIM_Base_Init+0xca>
- 8007438: b92f cbnz r7, 8007446 <HAL_TIM_Base_Init+0xca>
- 800743a: 2301 movs r3, #1
- 800743c: 2000 movs r0, #0
- 800743e: 6153 str r3, [r2, #20]
- 8007440: f884 303d strb.w r3, [r4, #61] ; 0x3d
- 8007444: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8007446: 6963 ldr r3, [r4, #20]
- 8007448: 6313 str r3, [r2, #48] ; 0x30
- 800744a: e7f6 b.n 800743a <HAL_TIM_Base_Init+0xbe>
- 800744c: 2001 movs r0, #1
- 800744e: 4770 bx lr
- 8007450: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8007454: 68a1 ldr r1, [r4, #8]
- 8007456: 430b orrs r3, r1
- 8007458: e7e0 b.n 800741c <HAL_TIM_Base_Init+0xa0>
- 800745a: 4909 ldr r1, [pc, #36] ; (8007480 <HAL_TIM_Base_Init+0x104>)
- 800745c: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8007460: 68a0 ldr r0, [r4, #8]
- 8007462: 428a cmp r2, r1
- 8007464: ea43 0300 orr.w r3, r3, r0
- 8007468: d0d8 beq.n 800741c <HAL_TIM_Base_Init+0xa0>
- 800746a: 2f00 cmp r7, #0
- 800746c: d1d6 bne.n 800741c <HAL_TIM_Base_Init+0xa0>
- 800746e: e7b3 b.n 80073d8 <HAL_TIM_Base_Init+0x5c>
- 8007470: 40010000 .word 0x40010000
- 8007474: 40010400 .word 0x40010400
- 8007478: 40000400 .word 0x40000400
- 800747c: 40014000 .word 0x40014000
- 8007480: 40000c00 .word 0x40000c00
-
-08007484 <HAL_TIM_PWM_MspInit>:
- 8007484: 4770 bx lr
- 8007486: bf00 nop
-
-08007488 <HAL_TIM_PWM_Init>:
- 8007488: 2800 cmp r0, #0
- 800748a: d065 beq.n 8007558 <HAL_TIM_PWM_Init+0xd0>
- 800748c: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800748e: f890 303d ldrb.w r3, [r0, #61] ; 0x3d
- 8007492: 4604 mov r4, r0
- 8007494: f003 02ff and.w r2, r3, #255 ; 0xff
- 8007498: 2b00 cmp r3, #0
- 800749a: d03b beq.n 8007514 <HAL_TIM_PWM_Init+0x8c>
- 800749c: 6822 ldr r2, [r4, #0]
- 800749e: 2002 movs r0, #2
- 80074a0: 4e36 ldr r6, [pc, #216] ; (800757c <HAL_TIM_PWM_Init+0xf4>)
- 80074a2: 4f37 ldr r7, [pc, #220] ; (8007580 <HAL_TIM_PWM_Init+0xf8>)
- 80074a4: f1b2 4f80 cmp.w r2, #1073741824 ; 0x40000000
- 80074a8: eba2 0606 sub.w r6, r2, r6
- 80074ac: f884 003d strb.w r0, [r4, #61] ; 0x3d
- 80074b0: eba2 0707 sub.w r7, r2, r7
- 80074b4: 6813 ldr r3, [r2, #0]
- 80074b6: fab6 f686 clz r6, r6
- 80074ba: fab7 f787 clz r7, r7
- 80074be: ea4f 1656 mov.w r6, r6, lsr #5
- 80074c2: ea4f 1757 mov.w r7, r7, lsr #5
- 80074c6: d02a beq.n 800751e <HAL_TIM_PWM_Init+0x96>
- 80074c8: bb4e cbnz r6, 800751e <HAL_TIM_PWM_Init+0x96>
- 80074ca: 492e ldr r1, [pc, #184] ; (8007584 <HAL_TIM_PWM_Init+0xfc>)
- 80074cc: 428a cmp r2, r1
- 80074ce: d045 beq.n 800755c <HAL_TIM_PWM_Init+0xd4>
- 80074d0: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80074d4: 428a cmp r2, r1
- 80074d6: d041 beq.n 800755c <HAL_TIM_PWM_Init+0xd4>
- 80074d8: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80074dc: 428a cmp r2, r1
- 80074de: d042 beq.n 8007566 <HAL_TIM_PWM_Init+0xde>
- 80074e0: 2f00 cmp r7, #0
- 80074e2: d140 bne.n 8007566 <HAL_TIM_PWM_Init+0xde>
- 80074e4: 4928 ldr r1, [pc, #160] ; (8007588 <HAL_TIM_PWM_Init+0x100>)
- 80074e6: 428a cmp r2, r1
- 80074e8: d01e beq.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 80074ea: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80074ee: 428a cmp r2, r1
- 80074f0: d01a beq.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 80074f2: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80074f6: 428a cmp r2, r1
- 80074f8: d016 beq.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 80074fa: f5a1 3198 sub.w r1, r1, #77824 ; 0x13000
- 80074fe: 428a cmp r2, r1
- 8007500: d012 beq.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 8007502: f501 6180 add.w r1, r1, #1024 ; 0x400
- 8007506: 428a cmp r2, r1
- 8007508: d00e beq.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 800750a: f501 6180 add.w r1, r1, #1024 ; 0x400
- 800750e: 428a cmp r2, r1
- 8007510: d10e bne.n 8007530 <HAL_TIM_PWM_Init+0xa8>
- 8007512: e009 b.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 8007514: f880 203c strb.w r2, [r0, #60] ; 0x3c
- 8007518: f7ff ffb4 bl 8007484 <HAL_TIM_PWM_MspInit>
- 800751c: e7be b.n 800749c <HAL_TIM_PWM_Init+0x14>
- 800751e: f023 0570 bic.w r5, r3, #112 ; 0x70
- 8007522: 68a0 ldr r0, [r4, #8]
- 8007524: ea45 0300 orr.w r3, r5, r0
- 8007528: f423 7340 bic.w r3, r3, #768 ; 0x300
- 800752c: 6920 ldr r0, [r4, #16]
- 800752e: 4303 orrs r3, r0
- 8007530: 69a1 ldr r1, [r4, #24]
- 8007532: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8007536: 68e0 ldr r0, [r4, #12]
- 8007538: 430b orrs r3, r1
- 800753a: 6861 ldr r1, [r4, #4]
- 800753c: 6013 str r3, [r2, #0]
- 800753e: 62d0 str r0, [r2, #44] ; 0x2c
- 8007540: 6291 str r1, [r2, #40] ; 0x28
- 8007542: b936 cbnz r6, 8007552 <HAL_TIM_PWM_Init+0xca>
- 8007544: b92f cbnz r7, 8007552 <HAL_TIM_PWM_Init+0xca>
- 8007546: 2301 movs r3, #1
- 8007548: 2000 movs r0, #0
- 800754a: 6153 str r3, [r2, #20]
- 800754c: f884 303d strb.w r3, [r4, #61] ; 0x3d
- 8007550: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8007552: 6963 ldr r3, [r4, #20]
- 8007554: 6313 str r3, [r2, #48] ; 0x30
- 8007556: e7f6 b.n 8007546 <HAL_TIM_PWM_Init+0xbe>
- 8007558: 2001 movs r0, #1
- 800755a: 4770 bx lr
- 800755c: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8007560: 68a1 ldr r1, [r4, #8]
- 8007562: 430b orrs r3, r1
- 8007564: e7e0 b.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 8007566: 4909 ldr r1, [pc, #36] ; (800758c <HAL_TIM_PWM_Init+0x104>)
- 8007568: f023 0370 bic.w r3, r3, #112 ; 0x70
- 800756c: 68a0 ldr r0, [r4, #8]
- 800756e: 428a cmp r2, r1
- 8007570: ea43 0300 orr.w r3, r3, r0
- 8007574: d0d8 beq.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 8007576: 2f00 cmp r7, #0
- 8007578: d1d6 bne.n 8007528 <HAL_TIM_PWM_Init+0xa0>
- 800757a: e7b3 b.n 80074e4 <HAL_TIM_PWM_Init+0x5c>
- 800757c: 40010000 .word 0x40010000
- 8007580: 40010400 .word 0x40010400
- 8007584: 40000400 .word 0x40000400
- 8007588: 40014000 .word 0x40014000
- 800758c: 40000c00 .word 0x40000c00
-
-08007590 <HAL_TIM_Encoder_Init>:
- 8007590: 2800 cmp r0, #0
- 8007592: f000 809f beq.w 80076d4 <HAL_TIM_Encoder_Init+0x144>
- 8007596: f890 303d ldrb.w r3, [r0, #61] ; 0x3d
- 800759a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 800759e: f003 02ff and.w r2, r3, #255 ; 0xff
- 80075a2: 4605 mov r5, r0
- 80075a4: 460e mov r6, r1
- 80075a6: 2b00 cmp r3, #0
- 80075a8: f000 808c beq.w 80076c4 <HAL_TIM_Encoder_Init+0x134>
- 80075ac: 682b ldr r3, [r5, #0]
- 80075ae: 2102 movs r1, #2
- 80075b0: 4f4f ldr r7, [pc, #316] ; (80076f0 <HAL_TIM_Encoder_Init+0x160>)
- 80075b2: 4c50 ldr r4, [pc, #320] ; (80076f4 <HAL_TIM_Encoder_Init+0x164>)
- 80075b4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 80075b8: f885 103d strb.w r1, [r5, #61] ; 0x3d
- 80075bc: eba3 0707 sub.w r7, r3, r7
- 80075c0: 6899 ldr r1, [r3, #8]
- 80075c2: eba3 0404 sub.w r4, r3, r4
- 80075c6: 4a4c ldr r2, [pc, #304] ; (80076f8 <HAL_TIM_Encoder_Init+0x168>)
- 80075c8: fab7 f787 clz r7, r7
- 80075cc: fab4 f484 clz r4, r4
- 80075d0: ea02 0201 and.w r2, r2, r1
- 80075d4: ea4f 1757 mov.w r7, r7, lsr #5
- 80075d8: ea4f 1454 mov.w r4, r4, lsr #5
- 80075dc: 609a str r2, [r3, #8]
- 80075de: 681a ldr r2, [r3, #0]
- 80075e0: d025 beq.n 800762e <HAL_TIM_Encoder_Init+0x9e>
- 80075e2: bb27 cbnz r7, 800762e <HAL_TIM_Encoder_Init+0x9e>
- 80075e4: 4945 ldr r1, [pc, #276] ; (80076fc <HAL_TIM_Encoder_Init+0x16c>)
- 80075e6: 428b cmp r3, r1
- 80075e8: d021 beq.n 800762e <HAL_TIM_Encoder_Init+0x9e>
- 80075ea: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80075ee: 428b cmp r3, r1
- 80075f0: d01d beq.n 800762e <HAL_TIM_Encoder_Init+0x9e>
- 80075f2: f501 6180 add.w r1, r1, #1024 ; 0x400
- 80075f6: 428b cmp r3, r1
- 80075f8: d06e beq.n 80076d8 <HAL_TIM_Encoder_Init+0x148>
- 80075fa: 2c00 cmp r4, #0
- 80075fc: d16c bne.n 80076d8 <HAL_TIM_Encoder_Init+0x148>
- 80075fe: 4940 ldr r1, [pc, #256] ; (8007700 <HAL_TIM_Encoder_Init+0x170>)
- 8007600: 428b cmp r3, r1
- 8007602: d018 beq.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 8007604: f501 6180 add.w r1, r1, #1024 ; 0x400
- 8007608: 428b cmp r3, r1
- 800760a: d014 beq.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 800760c: f501 6180 add.w r1, r1, #1024 ; 0x400
- 8007610: 428b cmp r3, r1
- 8007612: d010 beq.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 8007614: f5a1 3198 sub.w r1, r1, #77824 ; 0x13000
- 8007618: 428b cmp r3, r1
- 800761a: d00c beq.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 800761c: f501 6180 add.w r1, r1, #1024 ; 0x400
- 8007620: 428b cmp r3, r1
- 8007622: d008 beq.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 8007624: f501 6180 add.w r1, r1, #1024 ; 0x400
- 8007628: 428b cmp r3, r1
- 800762a: d108 bne.n 800763e <HAL_TIM_Encoder_Init+0xae>
- 800762c: e003 b.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 800762e: f022 0270 bic.w r2, r2, #112 ; 0x70
- 8007632: 68a9 ldr r1, [r5, #8]
- 8007634: 430a orrs r2, r1
- 8007636: f422 7240 bic.w r2, r2, #768 ; 0x300
- 800763a: 6929 ldr r1, [r5, #16]
- 800763c: 430a orrs r2, r1
- 800763e: 69a9 ldr r1, [r5, #24]
- 8007640: f022 0280 bic.w r2, r2, #128 ; 0x80
- 8007644: 68e8 ldr r0, [r5, #12]
- 8007646: 430a orrs r2, r1
- 8007648: 6869 ldr r1, [r5, #4]
- 800764a: 601a str r2, [r3, #0]
- 800764c: 62d8 str r0, [r3, #44] ; 0x2c
- 800764e: 6299 str r1, [r3, #40] ; 0x28
- 8007650: 2f00 cmp r7, #0
- 8007652: d13c bne.n 80076ce <HAL_TIM_Encoder_Init+0x13e>
- 8007654: 2c00 cmp r4, #0
- 8007656: d13a bne.n 80076ce <HAL_TIM_Encoder_Init+0x13e>
- 8007658: 6932 ldr r2, [r6, #16]
- 800765a: 2701 movs r7, #1
- 800765c: f8d6 9018 ldr.w r9, [r6, #24]
- 8007660: 2000 movs r0, #0
- 8007662: ea4f 1e02 mov.w lr, r2, lsl #4
- 8007666: 68b2 ldr r2, [r6, #8]
- 8007668: 615f str r7, [r3, #20]
- 800766a: ea42 2909 orr.w r9, r2, r9, lsl #8
- 800766e: 689c ldr r4, [r3, #8]
- 8007670: 69f2 ldr r2, [r6, #28]
- 8007672: 6999 ldr r1, [r3, #24]
- 8007674: f8df c094 ldr.w ip, [pc, #148] ; 800770c <HAL_TIM_Encoder_Init+0x17c>
- 8007678: ea4e 2202 orr.w r2, lr, r2, lsl #8
- 800767c: f8d6 8000 ldr.w r8, [r6]
- 8007680: ea01 0c0c and.w ip, r1, ip
- 8007684: 68f1 ldr r1, [r6, #12]
- 8007686: f8d6 a020 ldr.w sl, [r6, #32]
- 800768a: ea44 0408 orr.w r4, r4, r8
- 800768e: f8d3 e020 ldr.w lr, [r3, #32]
- 8007692: ea49 0c0c orr.w ip, r9, ip
- 8007696: 4311 orrs r1, r2
- 8007698: f8d6 9004 ldr.w r9, [r6, #4]
- 800769c: 6972 ldr r2, [r6, #20]
- 800769e: f02e 0eaa bic.w lr, lr, #170 ; 0xaa
- 80076a2: 4e18 ldr r6, [pc, #96] ; (8007704 <HAL_TIM_Encoder_Init+0x174>)
- 80076a4: ea41 310a orr.w r1, r1, sl, lsl #12
- 80076a8: ea49 1202 orr.w r2, r9, r2, lsl #4
- 80076ac: 609c str r4, [r3, #8]
- 80076ae: ea0c 0606 and.w r6, ip, r6
- 80076b2: ea42 020e orr.w r2, r2, lr
- 80076b6: 4331 orrs r1, r6
- 80076b8: 6199 str r1, [r3, #24]
- 80076ba: 621a str r2, [r3, #32]
- 80076bc: f885 703d strb.w r7, [r5, #61] ; 0x3d
- 80076c0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 80076c4: f880 203c strb.w r2, [r0, #60] ; 0x3c
- 80076c8: f7fe faa0 bl 8005c0c <HAL_TIM_Encoder_MspInit>
- 80076cc: e76e b.n 80075ac <HAL_TIM_Encoder_Init+0x1c>
- 80076ce: 696a ldr r2, [r5, #20]
- 80076d0: 631a str r2, [r3, #48] ; 0x30
- 80076d2: e7c1 b.n 8007658 <HAL_TIM_Encoder_Init+0xc8>
- 80076d4: 2001 movs r0, #1
- 80076d6: 4770 bx lr
- 80076d8: 490b ldr r1, [pc, #44] ; (8007708 <HAL_TIM_Encoder_Init+0x178>)
- 80076da: f022 0270 bic.w r2, r2, #112 ; 0x70
- 80076de: 68a8 ldr r0, [r5, #8]
- 80076e0: 428b cmp r3, r1
- 80076e2: ea42 0200 orr.w r2, r2, r0
- 80076e6: d0a6 beq.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 80076e8: 2c00 cmp r4, #0
- 80076ea: d1a4 bne.n 8007636 <HAL_TIM_Encoder_Init+0xa6>
- 80076ec: e787 b.n 80075fe <HAL_TIM_Encoder_Init+0x6e>
- 80076ee: bf00 nop
- 80076f0: 40010000 .word 0x40010000
- 80076f4: 40010400 .word 0x40010400
- 80076f8: fffebff8 .word 0xfffebff8
- 80076fc: 40000400 .word 0x40000400
- 8007700: 40014000 .word 0x40014000
- 8007704: ffff0303 .word 0xffff0303
- 8007708: 40000c00 .word 0x40000c00
- 800770c: fffffcfc .word 0xfffffcfc
-
-08007710 <HAL_TIM_Encoder_Start>:
- 8007710: 6803 ldr r3, [r0, #0]
- 8007712: b1c1 cbz r1, 8007746 <HAL_TIM_Encoder_Start+0x36>
- 8007714: 2904 cmp r1, #4
- 8007716: d10d bne.n 8007734 <HAL_TIM_Encoder_Start+0x24>
- 8007718: 6a1a ldr r2, [r3, #32]
- 800771a: f022 0210 bic.w r2, r2, #16
- 800771e: 621a str r2, [r3, #32]
- 8007720: 6a1a ldr r2, [r3, #32]
- 8007722: f042 0210 orr.w r2, r2, #16
- 8007726: 621a str r2, [r3, #32]
- 8007728: 681a ldr r2, [r3, #0]
- 800772a: 2000 movs r0, #0
- 800772c: f042 0201 orr.w r2, r2, #1
- 8007730: 601a str r2, [r3, #0]
- 8007732: 4770 bx lr
- 8007734: 6a1a ldr r2, [r3, #32]
- 8007736: f022 0201 bic.w r2, r2, #1
- 800773a: 621a str r2, [r3, #32]
- 800773c: 6a1a ldr r2, [r3, #32]
- 800773e: f042 0201 orr.w r2, r2, #1
- 8007742: 621a str r2, [r3, #32]
- 8007744: e7e8 b.n 8007718 <HAL_TIM_Encoder_Start+0x8>
- 8007746: 6a1a ldr r2, [r3, #32]
- 8007748: f022 0201 bic.w r2, r2, #1
- 800774c: 621a str r2, [r3, #32]
- 800774e: 6a1a ldr r2, [r3, #32]
- 8007750: f042 0201 orr.w r2, r2, #1
- 8007754: 621a str r2, [r3, #32]
- 8007756: e7e7 b.n 8007728 <HAL_TIM_Encoder_Start+0x18>
-
-08007758 <HAL_TIM_PWM_ConfigChannel>:
- 8007758: 4603 mov r3, r0
- 800775a: f890 003c ldrb.w r0, [r0, #60] ; 0x3c
- 800775e: 2801 cmp r0, #1
- 8007760: f000 813e beq.w 80079e0 <HAL_TIM_PWM_ConfigChannel+0x288>
- 8007764: 2002 movs r0, #2
- 8007766: b4f0 push {r4, r5, r6, r7}
- 8007768: 2401 movs r4, #1
- 800776a: f883 003d strb.w r0, [r3, #61] ; 0x3d
- 800776e: f883 403c strb.w r4, [r3, #60] ; 0x3c
- 8007772: 2a14 cmp r2, #20
- 8007774: d843 bhi.n 80077fe <HAL_TIM_PWM_ConfigChannel+0xa6>
- 8007776: e8df f012 tbh [pc, r2, lsl #1]
- 800777a: 0015 .short 0x0015
- 800777c: 00420042 .word 0x00420042
- 8007780: 007b0042 .word 0x007b0042
- 8007784: 00420042 .word 0x00420042
- 8007788: 00da0042 .word 0x00da0042
- 800778c: 00420042 .word 0x00420042
- 8007790: 00aa0042 .word 0x00aa0042
- 8007794: 00420042 .word 0x00420042
- 8007798: 01060042 .word 0x01060042
- 800779c: 00420042 .word 0x00420042
- 80077a0: 004b0042 .word 0x004b0042
- 80077a4: 681a ldr r2, [r3, #0]
- 80077a6: f8d1 c008 ldr.w ip, [r1, #8]
- 80077aa: 6a15 ldr r5, [r2, #32]
- 80077ac: 680f ldr r7, [r1, #0]
- 80077ae: f025 0501 bic.w r5, r5, #1
- 80077b2: 4cab ldr r4, [pc, #684] ; (8007a60 <HAL_TIM_PWM_ConfigChannel+0x308>)
- 80077b4: 6215 str r5, [r2, #32]
- 80077b6: 6a10 ldr r0, [r2, #32]
- 80077b8: 6856 ldr r6, [r2, #4]
- 80077ba: 6995 ldr r5, [r2, #24]
- 80077bc: f020 0002 bic.w r0, r0, #2
- 80077c0: 402c ands r4, r5
- 80077c2: 4da8 ldr r5, [pc, #672] ; (8007a64 <HAL_TIM_PWM_ConfigChannel+0x30c>)
- 80077c4: ea40 000c orr.w r0, r0, ip
- 80077c8: 42aa cmp r2, r5
- 80077ca: ea44 0407 orr.w r4, r4, r7
- 80077ce: f000 8115 beq.w 80079fc <HAL_TIM_PWM_ConfigChannel+0x2a4>
- 80077d2: f505 6580 add.w r5, r5, #1024 ; 0x400
- 80077d6: 42aa cmp r2, r5
- 80077d8: f000 8110 beq.w 80079fc <HAL_TIM_PWM_ConfigChannel+0x2a4>
- 80077dc: 684d ldr r5, [r1, #4]
- 80077de: 6056 str r6, [r2, #4]
- 80077e0: 6194 str r4, [r2, #24]
- 80077e2: 6355 str r5, [r2, #52] ; 0x34
- 80077e4: 6210 str r0, [r2, #32]
- 80077e6: 6990 ldr r0, [r2, #24]
- 80077e8: 690c ldr r4, [r1, #16]
- 80077ea: f040 0008 orr.w r0, r0, #8
- 80077ee: 6190 str r0, [r2, #24]
- 80077f0: 6990 ldr r0, [r2, #24]
- 80077f2: f020 0004 bic.w r0, r0, #4
- 80077f6: 6190 str r0, [r2, #24]
- 80077f8: 6991 ldr r1, [r2, #24]
- 80077fa: 4321 orrs r1, r4
- 80077fc: 6191 str r1, [r2, #24]
- 80077fe: 2200 movs r2, #0
- 8007800: 2101 movs r1, #1
- 8007802: 4610 mov r0, r2
- 8007804: f883 103d strb.w r1, [r3, #61] ; 0x3d
- 8007808: f883 203c strb.w r2, [r3, #60] ; 0x3c
- 800780c: bcf0 pop {r4, r5, r6, r7}
- 800780e: 4770 bx lr
- 8007810: 681a ldr r2, [r3, #0]
- 8007812: 688e ldr r6, [r1, #8]
- 8007814: 6a15 ldr r5, [r2, #32]
- 8007816: 680f ldr r7, [r1, #0]
- 8007818: f425 1580 bic.w r5, r5, #1048576 ; 0x100000
- 800781c: 4c92 ldr r4, [pc, #584] ; (8007a68 <HAL_TIM_PWM_ConfigChannel+0x310>)
- 800781e: 6215 str r5, [r2, #32]
- 8007820: 6a10 ldr r0, [r2, #32]
- 8007822: 6855 ldr r5, [r2, #4]
- 8007824: f420 1000 bic.w r0, r0, #2097152 ; 0x200000
- 8007828: f8d2 c054 ldr.w ip, [r2, #84] ; 0x54
- 800782c: ea40 5006 orr.w r0, r0, r6, lsl #20
- 8007830: 4e8c ldr r6, [pc, #560] ; (8007a64 <HAL_TIM_PWM_ConfigChannel+0x30c>)
- 8007832: ea0c 0404 and.w r4, ip, r4
- 8007836: 42b2 cmp r2, r6
- 8007838: ea44 2407 orr.w r4, r4, r7, lsl #8
- 800783c: f000 80d2 beq.w 80079e4 <HAL_TIM_PWM_ConfigChannel+0x28c>
- 8007840: f506 6680 add.w r6, r6, #1024 ; 0x400
- 8007844: 42b2 cmp r2, r6
- 8007846: f000 80cd beq.w 80079e4 <HAL_TIM_PWM_ConfigChannel+0x28c>
- 800784a: 684e ldr r6, [r1, #4]
- 800784c: 6055 str r5, [r2, #4]
- 800784e: 6554 str r4, [r2, #84] ; 0x54
- 8007850: 65d6 str r6, [r2, #92] ; 0x5c
- 8007852: 6210 str r0, [r2, #32]
- 8007854: 6d50 ldr r0, [r2, #84] ; 0x54
- 8007856: 690c ldr r4, [r1, #16]
- 8007858: f440 6000 orr.w r0, r0, #2048 ; 0x800
- 800785c: 6550 str r0, [r2, #84] ; 0x54
- 800785e: 6d50 ldr r0, [r2, #84] ; 0x54
- 8007860: f420 6080 bic.w r0, r0, #1024 ; 0x400
- 8007864: 6550 str r0, [r2, #84] ; 0x54
- 8007866: 6d51 ldr r1, [r2, #84] ; 0x54
- 8007868: ea41 2104 orr.w r1, r1, r4, lsl #8
- 800786c: 6551 str r1, [r2, #84] ; 0x54
- 800786e: e7c6 b.n 80077fe <HAL_TIM_PWM_ConfigChannel+0xa6>
- 8007870: 681a ldr r2, [r3, #0]
- 8007872: f8d1 c008 ldr.w ip, [r1, #8]
- 8007876: 6a15 ldr r5, [r2, #32]
- 8007878: 680f ldr r7, [r1, #0]
- 800787a: f025 0510 bic.w r5, r5, #16
- 800787e: 4c7b ldr r4, [pc, #492] ; (8007a6c <HAL_TIM_PWM_ConfigChannel+0x314>)
- 8007880: 6215 str r5, [r2, #32]
- 8007882: 6a10 ldr r0, [r2, #32]
- 8007884: 6856 ldr r6, [r2, #4]
- 8007886: 6995 ldr r5, [r2, #24]
- 8007888: f020 0020 bic.w r0, r0, #32
- 800788c: 402c ands r4, r5
- 800788e: 4d75 ldr r5, [pc, #468] ; (8007a64 <HAL_TIM_PWM_ConfigChannel+0x30c>)
- 8007890: ea40 100c orr.w r0, r0, ip, lsl #4
- 8007894: 42aa cmp r2, r5
- 8007896: ea44 2407 orr.w r4, r4, r7, lsl #8
- 800789a: f000 80c3 beq.w 8007a24 <HAL_TIM_PWM_ConfigChannel+0x2cc>
- 800789e: f505 6580 add.w r5, r5, #1024 ; 0x400
- 80078a2: 42aa cmp r2, r5
- 80078a4: f000 80be beq.w 8007a24 <HAL_TIM_PWM_ConfigChannel+0x2cc>
- 80078a8: 684d ldr r5, [r1, #4]
- 80078aa: 6056 str r6, [r2, #4]
- 80078ac: 6194 str r4, [r2, #24]
- 80078ae: 6395 str r5, [r2, #56] ; 0x38
- 80078b0: 6210 str r0, [r2, #32]
- 80078b2: 6990 ldr r0, [r2, #24]
- 80078b4: 690c ldr r4, [r1, #16]
- 80078b6: f440 6000 orr.w r0, r0, #2048 ; 0x800
- 80078ba: 6190 str r0, [r2, #24]
- 80078bc: 6990 ldr r0, [r2, #24]
- 80078be: f420 6080 bic.w r0, r0, #1024 ; 0x400
- 80078c2: 6190 str r0, [r2, #24]
- 80078c4: 6991 ldr r1, [r2, #24]
- 80078c6: ea41 2104 orr.w r1, r1, r4, lsl #8
- 80078ca: 6191 str r1, [r2, #24]
- 80078cc: e797 b.n 80077fe <HAL_TIM_PWM_ConfigChannel+0xa6>
- 80078ce: 681a ldr r2, [r3, #0]
- 80078d0: 688e ldr r6, [r1, #8]
- 80078d2: 6a15 ldr r5, [r2, #32]
- 80078d4: 680f ldr r7, [r1, #0]
- 80078d6: f425 5580 bic.w r5, r5, #4096 ; 0x1000
- 80078da: 4c64 ldr r4, [pc, #400] ; (8007a6c <HAL_TIM_PWM_ConfigChannel+0x314>)
- 80078dc: 6215 str r5, [r2, #32]
- 80078de: 6a10 ldr r0, [r2, #32]
- 80078e0: 6855 ldr r5, [r2, #4]
- 80078e2: f420 5000 bic.w r0, r0, #8192 ; 0x2000
- 80078e6: f8d2 c01c ldr.w ip, [r2, #28]
- 80078ea: ea40 3006 orr.w r0, r0, r6, lsl #12
- 80078ee: 4e5d ldr r6, [pc, #372] ; (8007a64 <HAL_TIM_PWM_ConfigChannel+0x30c>)
- 80078f0: ea0c 0404 and.w r4, ip, r4
- 80078f4: 42b2 cmp r2, r6
- 80078f6: ea44 2407 orr.w r4, r4, r7, lsl #8
- 80078fa: f000 808d beq.w 8007a18 <HAL_TIM_PWM_ConfigChannel+0x2c0>
- 80078fe: f506 6680 add.w r6, r6, #1024 ; 0x400
- 8007902: 42b2 cmp r2, r6
- 8007904: f000 8088 beq.w 8007a18 <HAL_TIM_PWM_ConfigChannel+0x2c0>
- 8007908: 684e ldr r6, [r1, #4]
- 800790a: 6055 str r5, [r2, #4]
- 800790c: 61d4 str r4, [r2, #28]
- 800790e: 6416 str r6, [r2, #64] ; 0x40
- 8007910: 6210 str r0, [r2, #32]
- 8007912: 69d0 ldr r0, [r2, #28]
- 8007914: 690c ldr r4, [r1, #16]
- 8007916: f440 6000 orr.w r0, r0, #2048 ; 0x800
- 800791a: 61d0 str r0, [r2, #28]
- 800791c: 69d0 ldr r0, [r2, #28]
- 800791e: f420 6080 bic.w r0, r0, #1024 ; 0x400
- 8007922: 61d0 str r0, [r2, #28]
- 8007924: 69d1 ldr r1, [r2, #28]
- 8007926: ea41 2104 orr.w r1, r1, r4, lsl #8
- 800792a: 61d1 str r1, [r2, #28]
- 800792c: e767 b.n 80077fe <HAL_TIM_PWM_ConfigChannel+0xa6>
- 800792e: 681a ldr r2, [r3, #0]
- 8007930: f8d1 c008 ldr.w ip, [r1, #8]
- 8007934: 6a15 ldr r5, [r2, #32]
- 8007936: 680f ldr r7, [r1, #0]
- 8007938: f425 7580 bic.w r5, r5, #256 ; 0x100
- 800793c: 4c48 ldr r4, [pc, #288] ; (8007a60 <HAL_TIM_PWM_ConfigChannel+0x308>)
- 800793e: 6215 str r5, [r2, #32]
- 8007940: 6a10 ldr r0, [r2, #32]
- 8007942: 6856 ldr r6, [r2, #4]
- 8007944: 69d5 ldr r5, [r2, #28]
- 8007946: f420 7000 bic.w r0, r0, #512 ; 0x200
- 800794a: 402c ands r4, r5
- 800794c: 4d45 ldr r5, [pc, #276] ; (8007a64 <HAL_TIM_PWM_ConfigChannel+0x30c>)
- 800794e: ea40 200c orr.w r0, r0, ip, lsl #8
- 8007952: 42aa cmp r2, r5
- 8007954: ea44 0407 orr.w r4, r4, r7
- 8007958: d073 beq.n 8007a42 <HAL_TIM_PWM_ConfigChannel+0x2ea>
- 800795a: f505 6580 add.w r5, r5, #1024 ; 0x400
- 800795e: 42aa cmp r2, r5
- 8007960: d06f beq.n 8007a42 <HAL_TIM_PWM_ConfigChannel+0x2ea>
- 8007962: 684d ldr r5, [r1, #4]
- 8007964: 6056 str r6, [r2, #4]
- 8007966: 61d4 str r4, [r2, #28]
- 8007968: 63d5 str r5, [r2, #60] ; 0x3c
- 800796a: 6210 str r0, [r2, #32]
- 800796c: 69d0 ldr r0, [r2, #28]
- 800796e: 690c ldr r4, [r1, #16]
- 8007970: f040 0008 orr.w r0, r0, #8
- 8007974: 61d0 str r0, [r2, #28]
- 8007976: 69d0 ldr r0, [r2, #28]
- 8007978: f020 0004 bic.w r0, r0, #4
- 800797c: 61d0 str r0, [r2, #28]
- 800797e: 69d1 ldr r1, [r2, #28]
- 8007980: 4321 orrs r1, r4
- 8007982: 61d1 str r1, [r2, #28]
- 8007984: e73b b.n 80077fe <HAL_TIM_PWM_ConfigChannel+0xa6>
- 8007986: 681a ldr r2, [r3, #0]
- 8007988: 688e ldr r6, [r1, #8]
- 800798a: 6a15 ldr r5, [r2, #32]
- 800798c: 680f ldr r7, [r1, #0]
- 800798e: f425 3580 bic.w r5, r5, #65536 ; 0x10000
- 8007992: 4c37 ldr r4, [pc, #220] ; (8007a70 <HAL_TIM_PWM_ConfigChannel+0x318>)
- 8007994: 6215 str r5, [r2, #32]
- 8007996: 6a10 ldr r0, [r2, #32]
- 8007998: 6855 ldr r5, [r2, #4]
- 800799a: f420 3000 bic.w r0, r0, #131072 ; 0x20000
- 800799e: f8d2 c054 ldr.w ip, [r2, #84] ; 0x54
- 80079a2: ea40 4006 orr.w r0, r0, r6, lsl #16
- 80079a6: 4e2f ldr r6, [pc, #188] ; (8007a64 <HAL_TIM_PWM_ConfigChannel+0x30c>)
- 80079a8: ea0c 0404 and.w r4, ip, r4
- 80079ac: 42b2 cmp r2, r6
- 80079ae: ea44 0407 orr.w r4, r4, r7
- 80079b2: d01d beq.n 80079f0 <HAL_TIM_PWM_ConfigChannel+0x298>
- 80079b4: f506 6680 add.w r6, r6, #1024 ; 0x400
- 80079b8: 42b2 cmp r2, r6
- 80079ba: d019 beq.n 80079f0 <HAL_TIM_PWM_ConfigChannel+0x298>
- 80079bc: 684e ldr r6, [r1, #4]
- 80079be: 6055 str r5, [r2, #4]
- 80079c0: 6554 str r4, [r2, #84] ; 0x54
- 80079c2: 6596 str r6, [r2, #88] ; 0x58
- 80079c4: 6210 str r0, [r2, #32]
- 80079c6: 6d50 ldr r0, [r2, #84] ; 0x54
- 80079c8: 690c ldr r4, [r1, #16]
- 80079ca: f040 0008 orr.w r0, r0, #8
- 80079ce: 6550 str r0, [r2, #84] ; 0x54
- 80079d0: 6d50 ldr r0, [r2, #84] ; 0x54
- 80079d2: f020 0004 bic.w r0, r0, #4
- 80079d6: 6550 str r0, [r2, #84] ; 0x54
- 80079d8: 6d51 ldr r1, [r2, #84] ; 0x54
- 80079da: 4321 orrs r1, r4
- 80079dc: 6551 str r1, [r2, #84] ; 0x54
- 80079de: e70e b.n 80077fe <HAL_TIM_PWM_ConfigChannel+0xa6>
- 80079e0: 2002 movs r0, #2
- 80079e2: 4770 bx lr
- 80079e4: f425 2580 bic.w r5, r5, #262144 ; 0x40000
- 80079e8: 694e ldr r6, [r1, #20]
- 80079ea: ea45 2586 orr.w r5, r5, r6, lsl #10
- 80079ee: e72c b.n 800784a <HAL_TIM_PWM_ConfigChannel+0xf2>
- 80079f0: f425 3580 bic.w r5, r5, #65536 ; 0x10000
- 80079f4: 694e ldr r6, [r1, #20]
- 80079f6: ea45 2506 orr.w r5, r5, r6, lsl #8
- 80079fa: e7df b.n 80079bc <HAL_TIM_PWM_ConfigChannel+0x264>
- 80079fc: f426 7c40 bic.w ip, r6, #768 ; 0x300
- 8007a00: f020 0008 bic.w r0, r0, #8
- 8007a04: 698e ldr r6, [r1, #24]
- 8007a06: 68cf ldr r7, [r1, #12]
- 8007a08: 694d ldr r5, [r1, #20]
- 8007a0a: 4338 orrs r0, r7
- 8007a0c: 4335 orrs r5, r6
- 8007a0e: f020 0004 bic.w r0, r0, #4
- 8007a12: ea45 060c orr.w r6, r5, ip
- 8007a16: e6e1 b.n 80077dc <HAL_TIM_PWM_ConfigChannel+0x84>
- 8007a18: f425 4580 bic.w r5, r5, #16384 ; 0x4000
- 8007a1c: 694e ldr r6, [r1, #20]
- 8007a1e: ea45 1586 orr.w r5, r5, r6, lsl #6
- 8007a22: e771 b.n 8007908 <HAL_TIM_PWM_ConfigChannel+0x1b0>
- 8007a24: f426 6c40 bic.w ip, r6, #3072 ; 0xc00
- 8007a28: f020 0080 bic.w r0, r0, #128 ; 0x80
- 8007a2c: 698e ldr r6, [r1, #24]
- 8007a2e: 68cf ldr r7, [r1, #12]
- 8007a30: 694d ldr r5, [r1, #20]
- 8007a32: ea40 1007 orr.w r0, r0, r7, lsl #4
- 8007a36: 4335 orrs r5, r6
- 8007a38: f020 0040 bic.w r0, r0, #64 ; 0x40
- 8007a3c: ea4c 0685 orr.w r6, ip, r5, lsl #2
- 8007a40: e732 b.n 80078a8 <HAL_TIM_PWM_ConfigChannel+0x150>
- 8007a42: f426 5c40 bic.w ip, r6, #12288 ; 0x3000
- 8007a46: f420 6000 bic.w r0, r0, #2048 ; 0x800
- 8007a4a: 698e ldr r6, [r1, #24]
- 8007a4c: 68cf ldr r7, [r1, #12]
- 8007a4e: 694d ldr r5, [r1, #20]
- 8007a50: ea40 2007 orr.w r0, r0, r7, lsl #8
- 8007a54: 4335 orrs r5, r6
- 8007a56: f420 6080 bic.w r0, r0, #1024 ; 0x400
- 8007a5a: ea4c 1605 orr.w r6, ip, r5, lsl #4
- 8007a5e: e780 b.n 8007962 <HAL_TIM_PWM_ConfigChannel+0x20a>
- 8007a60: fffeff8c .word 0xfffeff8c
- 8007a64: 40010000 .word 0x40010000
- 8007a68: feff8fff .word 0xfeff8fff
- 8007a6c: feff8cff .word 0xfeff8cff
- 8007a70: fffeff8f .word 0xfffeff8f
-
-08007a74 <HAL_TIM_ConfigClockSource>:
- 8007a74: f890 303c ldrb.w r3, [r0, #60] ; 0x3c
- 8007a78: 2b01 cmp r3, #1
- 8007a7a: d05b beq.n 8007b34 <HAL_TIM_ConfigClockSource+0xc0>
- 8007a7c: 4602 mov r2, r0
- 8007a7e: 2002 movs r0, #2
- 8007a80: 6813 ldr r3, [r2, #0]
- 8007a82: b470 push {r4, r5, r6}
- 8007a84: f882 003d strb.w r0, [r2, #61] ; 0x3d
- 8007a88: 2501 movs r5, #1
- 8007a8a: 6898 ldr r0, [r3, #8]
- 8007a8c: 4c4c ldr r4, [pc, #304] ; (8007bc0 <HAL_TIM_ConfigClockSource+0x14c>)
- 8007a8e: f882 503c strb.w r5, [r2, #60] ; 0x3c
- 8007a92: 4004 ands r4, r0
- 8007a94: 6808 ldr r0, [r1, #0]
- 8007a96: 2840 cmp r0, #64 ; 0x40
- 8007a98: 609c str r4, [r3, #8]
- 8007a9a: d076 beq.n 8007b8a <HAL_TIM_ConfigClockSource+0x116>
- 8007a9c: d94c bls.n 8007b38 <HAL_TIM_ConfigClockSource+0xc4>
- 8007a9e: 2860 cmp r0, #96 ; 0x60
- 8007aa0: d02f beq.n 8007b02 <HAL_TIM_ConfigClockSource+0x8e>
- 8007aa2: d958 bls.n 8007b56 <HAL_TIM_ConfigClockSource+0xe2>
- 8007aa4: 2870 cmp r0, #112 ; 0x70
- 8007aa6: d01b beq.n 8007ae0 <HAL_TIM_ConfigClockSource+0x6c>
- 8007aa8: f5b0 5f00 cmp.w r0, #8192 ; 0x2000
- 8007aac: d10f bne.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007aae: 68cc ldr r4, [r1, #12]
- 8007ab0: e9d1 5001 ldrd r5, r0, [r1, #4]
- 8007ab4: ea40 0105 orr.w r1, r0, r5
- 8007ab8: 6898 ldr r0, [r3, #8]
- 8007aba: ea41 2104 orr.w r1, r1, r4, lsl #8
- 8007abe: f420 407f bic.w r0, r0, #65280 ; 0xff00
- 8007ac2: 4301 orrs r1, r0
- 8007ac4: 6099 str r1, [r3, #8]
- 8007ac6: 6899 ldr r1, [r3, #8]
- 8007ac8: f441 4180 orr.w r1, r1, #16384 ; 0x4000
- 8007acc: 6099 str r1, [r3, #8]
- 8007ace: 2300 movs r3, #0
- 8007ad0: 2101 movs r1, #1
- 8007ad2: 4618 mov r0, r3
- 8007ad4: f882 103d strb.w r1, [r2, #61] ; 0x3d
- 8007ad8: f882 303c strb.w r3, [r2, #60] ; 0x3c
- 8007adc: bc70 pop {r4, r5, r6}
- 8007ade: 4770 bx lr
- 8007ae0: e9d1 5001 ldrd r5, r0, [r1, #4]
- 8007ae4: 68cc ldr r4, [r1, #12]
- 8007ae6: ea40 0105 orr.w r1, r0, r5
- 8007aea: 6898 ldr r0, [r3, #8]
- 8007aec: ea41 2104 orr.w r1, r1, r4, lsl #8
- 8007af0: f420 407f bic.w r0, r0, #65280 ; 0xff00
- 8007af4: 4301 orrs r1, r0
- 8007af6: 6099 str r1, [r3, #8]
- 8007af8: 6899 ldr r1, [r3, #8]
- 8007afa: f041 0177 orr.w r1, r1, #119 ; 0x77
- 8007afe: 6099 str r1, [r3, #8]
- 8007b00: e7e5 b.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007b02: 6a1c ldr r4, [r3, #32]
- 8007b04: 684d ldr r5, [r1, #4]
- 8007b06: f024 0410 bic.w r4, r4, #16
- 8007b0a: 68ce ldr r6, [r1, #12]
- 8007b0c: 621c str r4, [r3, #32]
- 8007b0e: 6998 ldr r0, [r3, #24]
- 8007b10: 6a19 ldr r1, [r3, #32]
- 8007b12: f420 4070 bic.w r0, r0, #61440 ; 0xf000
- 8007b16: f021 01a0 bic.w r1, r1, #160 ; 0xa0
- 8007b1a: ea40 3006 orr.w r0, r0, r6, lsl #12
- 8007b1e: ea41 1105 orr.w r1, r1, r5, lsl #4
- 8007b22: 6198 str r0, [r3, #24]
- 8007b24: 6219 str r1, [r3, #32]
- 8007b26: 6899 ldr r1, [r3, #8]
- 8007b28: f021 0170 bic.w r1, r1, #112 ; 0x70
- 8007b2c: f041 0167 orr.w r1, r1, #103 ; 0x67
- 8007b30: 6099 str r1, [r3, #8]
- 8007b32: e7cc b.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007b34: 2002 movs r0, #2
- 8007b36: 4770 bx lr
- 8007b38: 2810 cmp r0, #16
- 8007b3a: d004 beq.n 8007b46 <HAL_TIM_ConfigClockSource+0xd2>
- 8007b3c: d93d bls.n 8007bba <HAL_TIM_ConfigClockSource+0x146>
- 8007b3e: 2820 cmp r0, #32
- 8007b40: d001 beq.n 8007b46 <HAL_TIM_ConfigClockSource+0xd2>
- 8007b42: 2830 cmp r0, #48 ; 0x30
- 8007b44: d1c3 bne.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007b46: 6899 ldr r1, [r3, #8]
- 8007b48: f040 0007 orr.w r0, r0, #7
- 8007b4c: f021 0170 bic.w r1, r1, #112 ; 0x70
- 8007b50: 4308 orrs r0, r1
- 8007b52: 6098 str r0, [r3, #8]
- 8007b54: e7bb b.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007b56: 2850 cmp r0, #80 ; 0x50
- 8007b58: d1b9 bne.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007b5a: 6a1d ldr r5, [r3, #32]
- 8007b5c: 6a1c ldr r4, [r3, #32]
- 8007b5e: 6848 ldr r0, [r1, #4]
- 8007b60: f025 050a bic.w r5, r5, #10
- 8007b64: f024 0401 bic.w r4, r4, #1
- 8007b68: 68ce ldr r6, [r1, #12]
- 8007b6a: 4328 orrs r0, r5
- 8007b6c: 621c str r4, [r3, #32]
- 8007b6e: 6999 ldr r1, [r3, #24]
- 8007b70: f021 01f0 bic.w r1, r1, #240 ; 0xf0
- 8007b74: ea41 1106 orr.w r1, r1, r6, lsl #4
- 8007b78: 6199 str r1, [r3, #24]
- 8007b7a: 6218 str r0, [r3, #32]
- 8007b7c: 6899 ldr r1, [r3, #8]
- 8007b7e: f021 0170 bic.w r1, r1, #112 ; 0x70
- 8007b82: f041 0157 orr.w r1, r1, #87 ; 0x57
- 8007b86: 6099 str r1, [r3, #8]
- 8007b88: e7a1 b.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007b8a: 6a1d ldr r5, [r3, #32]
- 8007b8c: 6a1c ldr r4, [r3, #32]
- 8007b8e: 6848 ldr r0, [r1, #4]
- 8007b90: f025 050a bic.w r5, r5, #10
- 8007b94: f024 0401 bic.w r4, r4, #1
- 8007b98: 68ce ldr r6, [r1, #12]
- 8007b9a: 4328 orrs r0, r5
- 8007b9c: 621c str r4, [r3, #32]
- 8007b9e: 6999 ldr r1, [r3, #24]
- 8007ba0: f021 01f0 bic.w r1, r1, #240 ; 0xf0
- 8007ba4: ea41 1106 orr.w r1, r1, r6, lsl #4
- 8007ba8: 6199 str r1, [r3, #24]
- 8007baa: 6218 str r0, [r3, #32]
- 8007bac: 6899 ldr r1, [r3, #8]
- 8007bae: f021 0170 bic.w r1, r1, #112 ; 0x70
- 8007bb2: f041 0147 orr.w r1, r1, #71 ; 0x47
- 8007bb6: 6099 str r1, [r3, #8]
- 8007bb8: e789 b.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007bba: 2800 cmp r0, #0
- 8007bbc: d0c3 beq.n 8007b46 <HAL_TIM_ConfigClockSource+0xd2>
- 8007bbe: e786 b.n 8007ace <HAL_TIM_ConfigClockSource+0x5a>
- 8007bc0: fffe0088 .word 0xfffe0088
-
-08007bc4 <HAL_TIM_OC_DelayElapsedCallback>:
- 8007bc4: 4770 bx lr
- 8007bc6: bf00 nop
-
-08007bc8 <HAL_TIM_IC_CaptureCallback>:
- 8007bc8: 4770 bx lr
- 8007bca: bf00 nop
-
-08007bcc <HAL_TIM_PWM_PulseFinishedCallback>:
- 8007bcc: 4770 bx lr
- 8007bce: bf00 nop
-
-08007bd0 <HAL_TIM_TriggerCallback>:
- 8007bd0: 4770 bx lr
- 8007bd2: bf00 nop
-
-08007bd4 <HAL_TIM_IRQHandler>:
- 8007bd4: 6803 ldr r3, [r0, #0]
- 8007bd6: 691a ldr r2, [r3, #16]
- 8007bd8: 0791 lsls r1, r2, #30
- 8007bda: b510 push {r4, lr}
- 8007bdc: 4604 mov r4, r0
- 8007bde: d502 bpl.n 8007be6 <HAL_TIM_IRQHandler+0x12>
- 8007be0: 68da ldr r2, [r3, #12]
- 8007be2: 0792 lsls r2, r2, #30
- 8007be4: d468 bmi.n 8007cb8 <HAL_TIM_IRQHandler+0xe4>
- 8007be6: 691a ldr r2, [r3, #16]
- 8007be8: 0752 lsls r2, r2, #29
- 8007bea: d502 bpl.n 8007bf2 <HAL_TIM_IRQHandler+0x1e>
- 8007bec: 68da ldr r2, [r3, #12]
- 8007bee: 0750 lsls r0, r2, #29
- 8007bf0: d44f bmi.n 8007c92 <HAL_TIM_IRQHandler+0xbe>
- 8007bf2: 691a ldr r2, [r3, #16]
- 8007bf4: 0711 lsls r1, r2, #28
- 8007bf6: d502 bpl.n 8007bfe <HAL_TIM_IRQHandler+0x2a>
- 8007bf8: 68da ldr r2, [r3, #12]
- 8007bfa: 0712 lsls r2, r2, #28
- 8007bfc: d437 bmi.n 8007c6e <HAL_TIM_IRQHandler+0x9a>
- 8007bfe: 691a ldr r2, [r3, #16]
- 8007c00: 06d0 lsls r0, r2, #27
- 8007c02: d502 bpl.n 8007c0a <HAL_TIM_IRQHandler+0x36>
- 8007c04: 68da ldr r2, [r3, #12]
- 8007c06: 06d1 lsls r1, r2, #27
- 8007c08: d41e bmi.n 8007c48 <HAL_TIM_IRQHandler+0x74>
- 8007c0a: 691a ldr r2, [r3, #16]
- 8007c0c: 07d2 lsls r2, r2, #31
- 8007c0e: d502 bpl.n 8007c16 <HAL_TIM_IRQHandler+0x42>
- 8007c10: 68da ldr r2, [r3, #12]
- 8007c12: 07d0 lsls r0, r2, #31
- 8007c14: d469 bmi.n 8007cea <HAL_TIM_IRQHandler+0x116>
- 8007c16: 691a ldr r2, [r3, #16]
- 8007c18: 0611 lsls r1, r2, #24
- 8007c1a: d502 bpl.n 8007c22 <HAL_TIM_IRQHandler+0x4e>
- 8007c1c: 68da ldr r2, [r3, #12]
- 8007c1e: 0612 lsls r2, r2, #24
- 8007c20: d46b bmi.n 8007cfa <HAL_TIM_IRQHandler+0x126>
- 8007c22: 691a ldr r2, [r3, #16]
- 8007c24: 05d0 lsls r0, r2, #23
- 8007c26: d502 bpl.n 8007c2e <HAL_TIM_IRQHandler+0x5a>
- 8007c28: 68da ldr r2, [r3, #12]
- 8007c2a: 0611 lsls r1, r2, #24
- 8007c2c: d46d bmi.n 8007d0a <HAL_TIM_IRQHandler+0x136>
- 8007c2e: 691a ldr r2, [r3, #16]
- 8007c30: 0652 lsls r2, r2, #25
- 8007c32: d502 bpl.n 8007c3a <HAL_TIM_IRQHandler+0x66>
- 8007c34: 68da ldr r2, [r3, #12]
- 8007c36: 0650 lsls r0, r2, #25
- 8007c38: d46f bmi.n 8007d1a <HAL_TIM_IRQHandler+0x146>
- 8007c3a: 691a ldr r2, [r3, #16]
- 8007c3c: 0691 lsls r1, r2, #26
- 8007c3e: d502 bpl.n 8007c46 <HAL_TIM_IRQHandler+0x72>
- 8007c40: 68da ldr r2, [r3, #12]
- 8007c42: 0692 lsls r2, r2, #26
- 8007c44: d449 bmi.n 8007cda <HAL_TIM_IRQHandler+0x106>
- 8007c46: bd10 pop {r4, pc}
- 8007c48: f06f 0110 mvn.w r1, #16
- 8007c4c: 2208 movs r2, #8
- 8007c4e: 4620 mov r0, r4
- 8007c50: 6119 str r1, [r3, #16]
- 8007c52: 69db ldr r3, [r3, #28]
- 8007c54: 7722 strb r2, [r4, #28]
- 8007c56: f413 7f40 tst.w r3, #768 ; 0x300
- 8007c5a: d16f bne.n 8007d3c <HAL_TIM_IRQHandler+0x168>
- 8007c5c: f7ff ffb2 bl 8007bc4 <HAL_TIM_OC_DelayElapsedCallback>
- 8007c60: 4620 mov r0, r4
- 8007c62: f7ff ffb3 bl 8007bcc <HAL_TIM_PWM_PulseFinishedCallback>
- 8007c66: 2200 movs r2, #0
- 8007c68: 6823 ldr r3, [r4, #0]
- 8007c6a: 7722 strb r2, [r4, #28]
- 8007c6c: e7cd b.n 8007c0a <HAL_TIM_IRQHandler+0x36>
- 8007c6e: f06f 0108 mvn.w r1, #8
- 8007c72: 2204 movs r2, #4
- 8007c74: 4620 mov r0, r4
- 8007c76: 6119 str r1, [r3, #16]
- 8007c78: 69db ldr r3, [r3, #28]
- 8007c7a: 7722 strb r2, [r4, #28]
- 8007c7c: 079b lsls r3, r3, #30
- 8007c7e: d15a bne.n 8007d36 <HAL_TIM_IRQHandler+0x162>
- 8007c80: f7ff ffa0 bl 8007bc4 <HAL_TIM_OC_DelayElapsedCallback>
- 8007c84: 4620 mov r0, r4
- 8007c86: f7ff ffa1 bl 8007bcc <HAL_TIM_PWM_PulseFinishedCallback>
- 8007c8a: 2200 movs r2, #0
- 8007c8c: 6823 ldr r3, [r4, #0]
- 8007c8e: 7722 strb r2, [r4, #28]
- 8007c90: e7b5 b.n 8007bfe <HAL_TIM_IRQHandler+0x2a>
- 8007c92: f06f 0104 mvn.w r1, #4
- 8007c96: 2202 movs r2, #2
- 8007c98: 4620 mov r0, r4
- 8007c9a: 6119 str r1, [r3, #16]
- 8007c9c: 699b ldr r3, [r3, #24]
- 8007c9e: 7722 strb r2, [r4, #28]
- 8007ca0: f413 7f40 tst.w r3, #768 ; 0x300
- 8007ca4: d144 bne.n 8007d30 <HAL_TIM_IRQHandler+0x15c>
- 8007ca6: f7ff ff8d bl 8007bc4 <HAL_TIM_OC_DelayElapsedCallback>
- 8007caa: 4620 mov r0, r4
- 8007cac: f7ff ff8e bl 8007bcc <HAL_TIM_PWM_PulseFinishedCallback>
- 8007cb0: 2200 movs r2, #0
- 8007cb2: 6823 ldr r3, [r4, #0]
- 8007cb4: 7722 strb r2, [r4, #28]
- 8007cb6: e79c b.n 8007bf2 <HAL_TIM_IRQHandler+0x1e>
- 8007cb8: f06f 0102 mvn.w r1, #2
- 8007cbc: 2201 movs r2, #1
- 8007cbe: 6119 str r1, [r3, #16]
- 8007cc0: 699b ldr r3, [r3, #24]
- 8007cc2: 7702 strb r2, [r0, #28]
- 8007cc4: 0799 lsls r1, r3, #30
- 8007cc6: d130 bne.n 8007d2a <HAL_TIM_IRQHandler+0x156>
- 8007cc8: f7ff ff7c bl 8007bc4 <HAL_TIM_OC_DelayElapsedCallback>
- 8007ccc: 4620 mov r0, r4
- 8007cce: f7ff ff7d bl 8007bcc <HAL_TIM_PWM_PulseFinishedCallback>
- 8007cd2: 2200 movs r2, #0
- 8007cd4: 6823 ldr r3, [r4, #0]
- 8007cd6: 7722 strb r2, [r4, #28]
- 8007cd8: e785 b.n 8007be6 <HAL_TIM_IRQHandler+0x12>
- 8007cda: f06f 0220 mvn.w r2, #32
- 8007cde: 4620 mov r0, r4
- 8007ce0: 611a str r2, [r3, #16]
- 8007ce2: e8bd 4010 ldmia.w sp!, {r4, lr}
- 8007ce6: f000 b85d b.w 8007da4 <HAL_TIMEx_CommutCallback>
- 8007cea: f06f 0201 mvn.w r2, #1
- 8007cee: 4620 mov r0, r4
- 8007cf0: 611a str r2, [r3, #16]
- 8007cf2: f7fd fae9 bl 80052c8 <HAL_TIM_PeriodElapsedCallback>
- 8007cf6: 6823 ldr r3, [r4, #0]
- 8007cf8: e78d b.n 8007c16 <HAL_TIM_IRQHandler+0x42>
- 8007cfa: f06f 0280 mvn.w r2, #128 ; 0x80
- 8007cfe: 4620 mov r0, r4
- 8007d00: 611a str r2, [r3, #16]
- 8007d02: f000 f851 bl 8007da8 <HAL_TIMEx_BreakCallback>
- 8007d06: 6823 ldr r3, [r4, #0]
- 8007d08: e78b b.n 8007c22 <HAL_TIM_IRQHandler+0x4e>
- 8007d0a: f46f 7280 mvn.w r2, #256 ; 0x100
- 8007d0e: 4620 mov r0, r4
- 8007d10: 611a str r2, [r3, #16]
- 8007d12: f000 f84b bl 8007dac <HAL_TIMEx_Break2Callback>
- 8007d16: 6823 ldr r3, [r4, #0]
- 8007d18: e789 b.n 8007c2e <HAL_TIM_IRQHandler+0x5a>
- 8007d1a: f06f 0240 mvn.w r2, #64 ; 0x40
- 8007d1e: 4620 mov r0, r4
- 8007d20: 611a str r2, [r3, #16]
- 8007d22: f7ff ff55 bl 8007bd0 <HAL_TIM_TriggerCallback>
- 8007d26: 6823 ldr r3, [r4, #0]
- 8007d28: e787 b.n 8007c3a <HAL_TIM_IRQHandler+0x66>
- 8007d2a: f7ff ff4d bl 8007bc8 <HAL_TIM_IC_CaptureCallback>
- 8007d2e: e7d0 b.n 8007cd2 <HAL_TIM_IRQHandler+0xfe>
- 8007d30: f7ff ff4a bl 8007bc8 <HAL_TIM_IC_CaptureCallback>
- 8007d34: e7bc b.n 8007cb0 <HAL_TIM_IRQHandler+0xdc>
- 8007d36: f7ff ff47 bl 8007bc8 <HAL_TIM_IC_CaptureCallback>
- 8007d3a: e7a6 b.n 8007c8a <HAL_TIM_IRQHandler+0xb6>
- 8007d3c: f7ff ff44 bl 8007bc8 <HAL_TIM_IC_CaptureCallback>
- 8007d40: e791 b.n 8007c66 <HAL_TIM_IRQHandler+0x92>
- 8007d42: bf00 nop
-
-08007d44 <HAL_TIMEx_MasterConfigSynchronization>:
- 8007d44: f890 303c ldrb.w r3, [r0, #60] ; 0x3c
- 8007d48: 2b01 cmp r3, #1
- 8007d4a: d025 beq.n 8007d98 <HAL_TIMEx_MasterConfigSynchronization+0x54>
- 8007d4c: 6802 ldr r2, [r0, #0]
- 8007d4e: 2302 movs r3, #2
- 8007d50: b470 push {r4, r5, r6}
- 8007d52: 4d13 ldr r5, [pc, #76] ; (8007da0 <HAL_TIMEx_MasterConfigSynchronization+0x5c>)
- 8007d54: f880 303d strb.w r3, [r0, #61] ; 0x3d
- 8007d58: 42aa cmp r2, r5
- 8007d5a: 6853 ldr r3, [r2, #4]
- 8007d5c: 6894 ldr r4, [r2, #8]
- 8007d5e: d016 beq.n 8007d8e <HAL_TIMEx_MasterConfigSynchronization+0x4a>
- 8007d60: f505 6580 add.w r5, r5, #1024 ; 0x400
- 8007d64: 42aa cmp r2, r5
- 8007d66: d012 beq.n 8007d8e <HAL_TIMEx_MasterConfigSynchronization+0x4a>
- 8007d68: 680d ldr r5, [r1, #0]
- 8007d6a: f024 0480 bic.w r4, r4, #128 ; 0x80
- 8007d6e: 6889 ldr r1, [r1, #8]
- 8007d70: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8007d74: 2601 movs r6, #1
- 8007d76: 432b orrs r3, r5
- 8007d78: 4321 orrs r1, r4
- 8007d7a: 2500 movs r5, #0
- 8007d7c: 6053 str r3, [r2, #4]
- 8007d7e: 6091 str r1, [r2, #8]
- 8007d80: f880 603d strb.w r6, [r0, #61] ; 0x3d
- 8007d84: f880 503c strb.w r5, [r0, #60] ; 0x3c
- 8007d88: 4628 mov r0, r5
- 8007d8a: bc70 pop {r4, r5, r6}
- 8007d8c: 4770 bx lr
- 8007d8e: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 8007d92: 684d ldr r5, [r1, #4]
- 8007d94: 432b orrs r3, r5
- 8007d96: e7e7 b.n 8007d68 <HAL_TIMEx_MasterConfigSynchronization+0x24>
- 8007d98: 2302 movs r3, #2
- 8007d9a: 4618 mov r0, r3
- 8007d9c: 4770 bx lr
- 8007d9e: bf00 nop
- 8007da0: 40010000 .word 0x40010000
-
-08007da4 <HAL_TIMEx_CommutCallback>:
- 8007da4: 4770 bx lr
- 8007da6: bf00 nop
-
-08007da8 <HAL_TIMEx_BreakCallback>:
- 8007da8: 4770 bx lr
- 8007daa: bf00 nop
-
-08007dac <HAL_TIMEx_Break2Callback>:
- 8007dac: 4770 bx lr
- 8007dae: bf00 nop
-
-08007db0 <HAL_UART_Transmit_DMA>:
- 8007db0: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8007db2: 6f46 ldr r6, [r0, #116] ; 0x74
- 8007db4: 2e20 cmp r6, #32
- 8007db6: d13b bne.n 8007e30 <HAL_UART_Transmit_DMA+0x80>
- 8007db8: 2900 cmp r1, #0
- 8007dba: d03b beq.n 8007e34 <HAL_UART_Transmit_DMA+0x84>
- 8007dbc: fab2 f782 clz r7, r2
- 8007dc0: 097f lsrs r7, r7, #5
- 8007dc2: 2f00 cmp r7, #0
- 8007dc4: d136 bne.n 8007e34 <HAL_UART_Transmit_DMA+0x84>
- 8007dc6: f890 4070 ldrb.w r4, [r0, #112] ; 0x70
- 8007dca: 2c01 cmp r4, #1
- 8007dcc: d030 beq.n 8007e30 <HAL_UART_Transmit_DMA+0x80>
- 8007dce: 4613 mov r3, r2
- 8007dd0: 4605 mov r5, r0
- 8007dd2: 2221 movs r2, #33 ; 0x21
- 8007dd4: 2401 movs r4, #1
- 8007dd6: f8d0 e068 ldr.w lr, [r0, #104] ; 0x68
- 8007dda: f8a0 3052 strh.w r3, [r0, #82] ; 0x52
- 8007dde: 64e9 str r1, [r5, #76] ; 0x4c
- 8007de0: 67c7 str r7, [r0, #124] ; 0x7c
- 8007de2: f8a0 3050 strh.w r3, [r0, #80] ; 0x50
- 8007de6: 6742 str r2, [r0, #116] ; 0x74
- 8007de8: f880 4070 strb.w r4, [r0, #112] ; 0x70
- 8007dec: 6802 ldr r2, [r0, #0]
- 8007dee: f1be 0f00 cmp.w lr, #0
- 8007df2: d012 beq.n 8007e1a <HAL_UART_Transmit_DMA+0x6a>
- 8007df4: f8df c054 ldr.w ip, [pc, #84] ; 8007e4c <HAL_UART_Transmit_DMA+0x9c>
- 8007df8: 3228 adds r2, #40 ; 0x28
- 8007dfa: 4813 ldr r0, [pc, #76] ; (8007e48 <HAL_UART_Transmit_DMA+0x98>)
- 8007dfc: f8ce c040 str.w ip, [lr, #64] ; 0x40
- 8007e00: f8df c04c ldr.w ip, [pc, #76] ; 8007e50 <HAL_UART_Transmit_DMA+0xa0>
- 8007e04: f8ce 003c str.w r0, [lr, #60] ; 0x3c
- 8007e08: 4670 mov r0, lr
- 8007e0a: f8ce 7050 str.w r7, [lr, #80] ; 0x50
- 8007e0e: f8ce c04c str.w ip, [lr, #76] ; 0x4c
- 8007e12: f7fe fab1 bl 8006378 <HAL_DMA_Start_IT>
- 8007e16: b978 cbnz r0, 8007e38 <HAL_UART_Transmit_DMA+0x88>
- 8007e18: 682a ldr r2, [r5, #0]
- 8007e1a: 2340 movs r3, #64 ; 0x40
- 8007e1c: 2100 movs r1, #0
- 8007e1e: 6213 str r3, [r2, #32]
- 8007e20: 4608 mov r0, r1
- 8007e22: 6893 ldr r3, [r2, #8]
- 8007e24: f885 1070 strb.w r1, [r5, #112] ; 0x70
- 8007e28: f043 0380 orr.w r3, r3, #128 ; 0x80
- 8007e2c: 6093 str r3, [r2, #8]
- 8007e2e: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8007e30: 2002 movs r0, #2
- 8007e32: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8007e34: 2001 movs r0, #1
- 8007e36: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8007e38: 2310 movs r3, #16
- 8007e3a: f885 7070 strb.w r7, [r5, #112] ; 0x70
- 8007e3e: 4620 mov r0, r4
- 8007e40: 67eb str r3, [r5, #124] ; 0x7c
- 8007e42: 676e str r6, [r5, #116] ; 0x74
- 8007e44: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8007e46: bf00 nop
- 8007e48: 08007f19 .word 0x08007f19
- 8007e4c: 08007f49 .word 0x08007f49
- 8007e50: 08007fa1 .word 0x08007fa1
-
-08007e54 <HAL_UART_Receive_DMA>:
- 8007e54: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
- 8007e58: 6f86 ldr r6, [r0, #120] ; 0x78
- 8007e5a: 2e20 cmp r6, #32
- 8007e5c: d149 bne.n 8007ef2 <HAL_UART_Receive_DMA+0x9e>
- 8007e5e: 2900 cmp r1, #0
- 8007e60: d04a beq.n 8007ef8 <HAL_UART_Receive_DMA+0xa4>
- 8007e62: fab2 f782 clz r7, r2
- 8007e66: 097f lsrs r7, r7, #5
- 8007e68: 2f00 cmp r7, #0
- 8007e6a: d145 bne.n 8007ef8 <HAL_UART_Receive_DMA+0xa4>
- 8007e6c: f890 3070 ldrb.w r3, [r0, #112] ; 0x70
- 8007e70: 2b01 cmp r3, #1
- 8007e72: d03e beq.n 8007ef2 <HAL_UART_Receive_DMA+0x9e>
- 8007e74: 4613 mov r3, r2
- 8007e76: 2401 movs r4, #1
- 8007e78: 2222 movs r2, #34 ; 0x22
- 8007e7a: f8d0 e06c ldr.w lr, [r0, #108] ; 0x6c
- 8007e7e: 67c7 str r7, [r0, #124] ; 0x7c
- 8007e80: 4605 mov r5, r0
- 8007e82: 6541 str r1, [r0, #84] ; 0x54
- 8007e84: f8a0 3058 strh.w r3, [r0, #88] ; 0x58
- 8007e88: f880 4070 strb.w r4, [r0, #112] ; 0x70
- 8007e8c: 6782 str r2, [r0, #120] ; 0x78
- 8007e8e: f8d0 c000 ldr.w ip, [r0]
- 8007e92: f1be 0f00 cmp.w lr, #0
- 8007e96: d015 beq.n 8007ec4 <HAL_UART_Receive_DMA+0x70>
- 8007e98: 481c ldr r0, [pc, #112] ; (8007f0c <HAL_UART_Receive_DMA+0xb8>)
- 8007e9a: 460a mov r2, r1
- 8007e9c: f8df 8070 ldr.w r8, [pc, #112] ; 8007f10 <HAL_UART_Receive_DMA+0xbc>
- 8007ea0: f10c 0124 add.w r1, ip, #36 ; 0x24
- 8007ea4: f8df c06c ldr.w ip, [pc, #108] ; 8007f14 <HAL_UART_Receive_DMA+0xc0>
- 8007ea8: f8ce 003c str.w r0, [lr, #60] ; 0x3c
- 8007eac: 4670 mov r0, lr
- 8007eae: f8ce 7050 str.w r7, [lr, #80] ; 0x50
- 8007eb2: f8ce 8040 str.w r8, [lr, #64] ; 0x40
- 8007eb6: f8ce c04c str.w ip, [lr, #76] ; 0x4c
- 8007eba: f7fe fa5d bl 8006378 <HAL_DMA_Start_IT>
- 8007ebe: b9f0 cbnz r0, 8007efe <HAL_UART_Receive_DMA+0xaa>
- 8007ec0: f8d5 c000 ldr.w ip, [r5]
- 8007ec4: f8dc 3000 ldr.w r3, [ip]
- 8007ec8: 2000 movs r0, #0
- 8007eca: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8007ece: f885 0070 strb.w r0, [r5, #112] ; 0x70
- 8007ed2: f8cc 3000 str.w r3, [ip]
- 8007ed6: f8dc 3008 ldr.w r3, [ip, #8]
- 8007eda: f043 0301 orr.w r3, r3, #1
- 8007ede: f8cc 3008 str.w r3, [ip, #8]
- 8007ee2: f8dc 3008 ldr.w r3, [ip, #8]
- 8007ee6: f043 0340 orr.w r3, r3, #64 ; 0x40
- 8007eea: f8cc 3008 str.w r3, [ip, #8]
- 8007eee: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8007ef2: 2002 movs r0, #2
- 8007ef4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8007ef8: 2001 movs r0, #1
- 8007efa: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
- 8007efe: 2310 movs r3, #16
- 8007f00: f885 7070 strb.w r7, [r5, #112] ; 0x70
- 8007f04: 4620 mov r0, r4
- 8007f06: 67eb str r3, [r5, #124] ; 0x7c
- 8007f08: 676e str r6, [r5, #116] ; 0x74
- 8007f0a: e7f3 b.n 8007ef4 <HAL_UART_Receive_DMA+0xa0>
- 8007f0c: 08007f55 .word 0x08007f55
- 8007f10: 08007f91 .word 0x08007f91
- 8007f14: 08007fa1 .word 0x08007fa1
-
-08007f18 <UART_DMATransmitCplt>:
- 8007f18: b508 push {r3, lr}
- 8007f1a: 69c3 ldr r3, [r0, #28]
- 8007f1c: 6b80 ldr r0, [r0, #56] ; 0x38
- 8007f1e: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8007f22: d00c beq.n 8007f3e <UART_DMATransmitCplt+0x26>
- 8007f24: 6803 ldr r3, [r0, #0]
- 8007f26: 2200 movs r2, #0
- 8007f28: f8a0 2052 strh.w r2, [r0, #82] ; 0x52
- 8007f2c: 689a ldr r2, [r3, #8]
- 8007f2e: f022 0280 bic.w r2, r2, #128 ; 0x80
- 8007f32: 609a str r2, [r3, #8]
- 8007f34: 681a ldr r2, [r3, #0]
- 8007f36: f042 0240 orr.w r2, r2, #64 ; 0x40
- 8007f3a: 601a str r2, [r3, #0]
- 8007f3c: bd08 pop {r3, pc}
- 8007f3e: f7fc fa3d bl 80043bc <HAL_UART_TxCpltCallback>
- 8007f42: bd08 pop {r3, pc}
-
-08007f44 <HAL_UART_TxHalfCpltCallback>:
- 8007f44: 4770 bx lr
- 8007f46: bf00 nop
-
-08007f48 <UART_DMATxHalfCplt>:
- 8007f48: b508 push {r3, lr}
- 8007f4a: 6b80 ldr r0, [r0, #56] ; 0x38
- 8007f4c: f7ff fffa bl 8007f44 <HAL_UART_TxHalfCpltCallback>
- 8007f50: bd08 pop {r3, pc}
- 8007f52: bf00 nop
-
-08007f54 <UART_DMAReceiveCplt>:
- 8007f54: b508 push {r3, lr}
- 8007f56: 69c3 ldr r3, [r0, #28]
- 8007f58: 6b80 ldr r0, [r0, #56] ; 0x38
- 8007f5a: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8007f5e: d011 beq.n 8007f84 <UART_DMAReceiveCplt+0x30>
- 8007f60: 6803 ldr r3, [r0, #0]
- 8007f62: 2200 movs r2, #0
- 8007f64: 2120 movs r1, #32
- 8007f66: f8a0 205a strh.w r2, [r0, #90] ; 0x5a
- 8007f6a: 681a ldr r2, [r3, #0]
- 8007f6c: f422 7280 bic.w r2, r2, #256 ; 0x100
- 8007f70: 601a str r2, [r3, #0]
- 8007f72: 689a ldr r2, [r3, #8]
- 8007f74: f022 0201 bic.w r2, r2, #1
- 8007f78: 609a str r2, [r3, #8]
- 8007f7a: 689a ldr r2, [r3, #8]
- 8007f7c: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8007f80: 609a str r2, [r3, #8]
- 8007f82: 6781 str r1, [r0, #120] ; 0x78
- 8007f84: f7fc fa46 bl 8004414 <HAL_UART_RxCpltCallback>
- 8007f88: bd08 pop {r3, pc}
- 8007f8a: bf00 nop
-
-08007f8c <HAL_UART_RxHalfCpltCallback>:
- 8007f8c: 4770 bx lr
- 8007f8e: bf00 nop
-
-08007f90 <UART_DMARxHalfCplt>:
- 8007f90: b508 push {r3, lr}
- 8007f92: 6b80 ldr r0, [r0, #56] ; 0x38
- 8007f94: f7ff fffa bl 8007f8c <HAL_UART_RxHalfCpltCallback>
- 8007f98: bd08 pop {r3, pc}
- 8007f9a: bf00 nop
-
-08007f9c <HAL_UART_ErrorCallback>:
- 8007f9c: 4770 bx lr
- 8007f9e: bf00 nop
-
-08007fa0 <UART_DMAError>:
- 8007fa0: 6b83 ldr r3, [r0, #56] ; 0x38
- 8007fa2: 681a ldr r2, [r3, #0]
- 8007fa4: b510 push {r4, lr}
- 8007fa6: 6f5c ldr r4, [r3, #116] ; 0x74
- 8007fa8: 6f98 ldr r0, [r3, #120] ; 0x78
- 8007faa: 6891 ldr r1, [r2, #8]
- 8007fac: 0609 lsls r1, r1, #24
- 8007fae: d501 bpl.n 8007fb4 <UART_DMAError+0x14>
- 8007fb0: 2c21 cmp r4, #33 ; 0x21
- 8007fb2: d01b beq.n 8007fec <UART_DMAError+0x4c>
- 8007fb4: 6891 ldr r1, [r2, #8]
- 8007fb6: 0649 lsls r1, r1, #25
- 8007fb8: d501 bpl.n 8007fbe <UART_DMAError+0x1e>
- 8007fba: 2822 cmp r0, #34 ; 0x22
- 8007fbc: d007 beq.n 8007fce <UART_DMAError+0x2e>
- 8007fbe: 6fda ldr r2, [r3, #124] ; 0x7c
- 8007fc0: 4618 mov r0, r3
- 8007fc2: f042 0210 orr.w r2, r2, #16
- 8007fc6: 67da str r2, [r3, #124] ; 0x7c
- 8007fc8: f7ff ffe8 bl 8007f9c <HAL_UART_ErrorCallback>
- 8007fcc: bd10 pop {r4, pc}
- 8007fce: 2000 movs r0, #0
- 8007fd0: 2420 movs r4, #32
- 8007fd2: f8a3 005a strh.w r0, [r3, #90] ; 0x5a
- 8007fd6: 6811 ldr r1, [r2, #0]
- 8007fd8: f421 7190 bic.w r1, r1, #288 ; 0x120
- 8007fdc: 6011 str r1, [r2, #0]
- 8007fde: 6891 ldr r1, [r2, #8]
- 8007fe0: f021 0101 bic.w r1, r1, #1
- 8007fe4: 6091 str r1, [r2, #8]
- 8007fe6: 6618 str r0, [r3, #96] ; 0x60
- 8007fe8: 679c str r4, [r3, #120] ; 0x78
- 8007fea: e7e8 b.n 8007fbe <UART_DMAError+0x1e>
- 8007fec: 2100 movs r1, #0
- 8007fee: 2420 movs r4, #32
- 8007ff0: f8a3 1052 strh.w r1, [r3, #82] ; 0x52
- 8007ff4: 6811 ldr r1, [r2, #0]
- 8007ff6: f021 01c0 bic.w r1, r1, #192 ; 0xc0
- 8007ffa: 6011 str r1, [r2, #0]
- 8007ffc: 675c str r4, [r3, #116] ; 0x74
- 8007ffe: e7d9 b.n 8007fb4 <UART_DMAError+0x14>
-
-08008000 <HAL_UART_IRQHandler>:
- 8008000: 6803 ldr r3, [r0, #0]
- 8008002: 69da ldr r2, [r3, #28]
- 8008004: b570 push {r4, r5, r6, lr}
- 8008006: 0716 lsls r6, r2, #28
- 8008008: 681d ldr r5, [r3, #0]
- 800800a: 4604 mov r4, r0
- 800800c: 6899 ldr r1, [r3, #8]
- 800800e: d047 beq.n 80080a0 <HAL_UART_IRQHandler+0xa0>
- 8008010: f011 0101 ands.w r1, r1, #1
- 8008014: d04b beq.n 80080ae <HAL_UART_IRQHandler+0xae>
- 8008016: 07d0 lsls r0, r2, #31
- 8008018: d507 bpl.n 800802a <HAL_UART_IRQHandler+0x2a>
- 800801a: 05ee lsls r6, r5, #23
- 800801c: d505 bpl.n 800802a <HAL_UART_IRQHandler+0x2a>
- 800801e: 2001 movs r0, #1
- 8008020: 6218 str r0, [r3, #32]
- 8008022: 6fe0 ldr r0, [r4, #124] ; 0x7c
- 8008024: f040 0001 orr.w r0, r0, #1
- 8008028: 67e0 str r0, [r4, #124] ; 0x7c
- 800802a: 0790 lsls r0, r2, #30
- 800802c: d45d bmi.n 80080ea <HAL_UART_IRQHandler+0xea>
- 800802e: 0750 lsls r0, r2, #29
- 8008030: d501 bpl.n 8008036 <HAL_UART_IRQHandler+0x36>
- 8008032: 2900 cmp r1, #0
- 8008034: d163 bne.n 80080fe <HAL_UART_IRQHandler+0xfe>
- 8008036: 0716 lsls r6, r2, #28
- 8008038: d503 bpl.n 8008042 <HAL_UART_IRQHandler+0x42>
- 800803a: 06a8 lsls r0, r5, #26
- 800803c: d466 bmi.n 800810c <HAL_UART_IRQHandler+0x10c>
- 800803e: 2900 cmp r1, #0
- 8008040: d164 bne.n 800810c <HAL_UART_IRQHandler+0x10c>
- 8008042: 6fe1 ldr r1, [r4, #124] ; 0x7c
- 8008044: 2900 cmp r1, #0
- 8008046: d031 beq.n 80080ac <HAL_UART_IRQHandler+0xac>
- 8008048: 0696 lsls r6, r2, #26
- 800804a: d501 bpl.n 8008050 <HAL_UART_IRQHandler+0x50>
- 800804c: 06a8 lsls r0, r5, #26
- 800804e: d468 bmi.n 8008122 <HAL_UART_IRQHandler+0x122>
- 8008050: 6fe5 ldr r5, [r4, #124] ; 0x7c
- 8008052: 6899 ldr r1, [r3, #8]
- 8008054: 0649 lsls r1, r1, #25
- 8008056: d402 bmi.n 800805e <HAL_UART_IRQHandler+0x5e>
- 8008058: f015 0508 ands.w r5, r5, #8
- 800805c: d068 beq.n 8008130 <HAL_UART_IRQHandler+0x130>
- 800805e: 681a ldr r2, [r3, #0]
- 8008060: 2020 movs r0, #32
- 8008062: 2100 movs r1, #0
- 8008064: f422 7290 bic.w r2, r2, #288 ; 0x120
- 8008068: 601a str r2, [r3, #0]
- 800806a: 689a ldr r2, [r3, #8]
- 800806c: f022 0201 bic.w r2, r2, #1
- 8008070: 609a str r2, [r3, #8]
- 8008072: 67a0 str r0, [r4, #120] ; 0x78
- 8008074: 689a ldr r2, [r3, #8]
- 8008076: 6621 str r1, [r4, #96] ; 0x60
- 8008078: 0652 lsls r2, r2, #25
- 800807a: d54e bpl.n 800811a <HAL_UART_IRQHandler+0x11a>
- 800807c: 689a ldr r2, [r3, #8]
- 800807e: 6ee1 ldr r1, [r4, #108] ; 0x6c
- 8008080: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8008084: 609a str r2, [r3, #8]
- 8008086: 2900 cmp r1, #0
- 8008088: d047 beq.n 800811a <HAL_UART_IRQHandler+0x11a>
- 800808a: 4b2c ldr r3, [pc, #176] ; (800813c <HAL_UART_IRQHandler+0x13c>)
- 800808c: 4608 mov r0, r1
- 800808e: 650b str r3, [r1, #80] ; 0x50
- 8008090: f7fe f9b8 bl 8006404 <HAL_DMA_Abort_IT>
- 8008094: b150 cbz r0, 80080ac <HAL_UART_IRQHandler+0xac>
- 8008096: 6ee0 ldr r0, [r4, #108] ; 0x6c
- 8008098: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
- 800809c: 6d03 ldr r3, [r0, #80] ; 0x50
- 800809e: 4718 bx r3
- 80080a0: 0691 lsls r1, r2, #26
- 80080a2: d507 bpl.n 80080b4 <HAL_UART_IRQHandler+0xb4>
- 80080a4: 06ae lsls r6, r5, #26
- 80080a6: d505 bpl.n 80080b4 <HAL_UART_IRQHandler+0xb4>
- 80080a8: 6e03 ldr r3, [r0, #96] ; 0x60
- 80080aa: b9db cbnz r3, 80080e4 <HAL_UART_IRQHandler+0xe4>
- 80080ac: bd70 pop {r4, r5, r6, pc}
- 80080ae: f415 7f90 tst.w r5, #288 ; 0x120
- 80080b2: d1b0 bne.n 8008016 <HAL_UART_IRQHandler+0x16>
- 80080b4: 0616 lsls r6, r2, #24
- 80080b6: d40f bmi.n 80080d8 <HAL_UART_IRQHandler+0xd8>
- 80080b8: 0651 lsls r1, r2, #25
- 80080ba: d5f7 bpl.n 80080ac <HAL_UART_IRQHandler+0xac>
- 80080bc: 066a lsls r2, r5, #25
- 80080be: d5f5 bpl.n 80080ac <HAL_UART_IRQHandler+0xac>
- 80080c0: 681a ldr r2, [r3, #0]
- 80080c2: 2520 movs r5, #32
- 80080c4: 2100 movs r1, #0
- 80080c6: 4620 mov r0, r4
- 80080c8: f022 0240 bic.w r2, r2, #64 ; 0x40
- 80080cc: 601a str r2, [r3, #0]
- 80080ce: 6765 str r5, [r4, #116] ; 0x74
- 80080d0: 6661 str r1, [r4, #100] ; 0x64
- 80080d2: f7fc f973 bl 80043bc <HAL_UART_TxCpltCallback>
- 80080d6: bd70 pop {r4, r5, r6, pc}
- 80080d8: 0628 lsls r0, r5, #24
- 80080da: d5ed bpl.n 80080b8 <HAL_UART_IRQHandler+0xb8>
- 80080dc: 6e63 ldr r3, [r4, #100] ; 0x64
- 80080de: 2b00 cmp r3, #0
- 80080e0: d0e4 beq.n 80080ac <HAL_UART_IRQHandler+0xac>
- 80080e2: 4620 mov r0, r4
- 80080e4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
- 80080e8: 4718 bx r3
- 80080ea: 2900 cmp r1, #0
- 80080ec: d0a3 beq.n 8008036 <HAL_UART_IRQHandler+0x36>
- 80080ee: 2002 movs r0, #2
- 80080f0: 0756 lsls r6, r2, #29
- 80080f2: 6218 str r0, [r3, #32]
- 80080f4: 6fe0 ldr r0, [r4, #124] ; 0x7c
- 80080f6: f040 0004 orr.w r0, r0, #4
- 80080fa: 67e0 str r0, [r4, #124] ; 0x7c
- 80080fc: d59b bpl.n 8008036 <HAL_UART_IRQHandler+0x36>
- 80080fe: 2004 movs r0, #4
- 8008100: 6218 str r0, [r3, #32]
- 8008102: 6fe0 ldr r0, [r4, #124] ; 0x7c
- 8008104: f040 0002 orr.w r0, r0, #2
- 8008108: 67e0 str r0, [r4, #124] ; 0x7c
- 800810a: e794 b.n 8008036 <HAL_UART_IRQHandler+0x36>
- 800810c: 2108 movs r1, #8
- 800810e: 6219 str r1, [r3, #32]
- 8008110: 6fe1 ldr r1, [r4, #124] ; 0x7c
- 8008112: f041 0108 orr.w r1, r1, #8
- 8008116: 67e1 str r1, [r4, #124] ; 0x7c
- 8008118: e793 b.n 8008042 <HAL_UART_IRQHandler+0x42>
- 800811a: 4620 mov r0, r4
- 800811c: f7ff ff3e bl 8007f9c <HAL_UART_ErrorCallback>
- 8008120: bd70 pop {r4, r5, r6, pc}
- 8008122: 6e22 ldr r2, [r4, #96] ; 0x60
- 8008124: 2a00 cmp r2, #0
- 8008126: d093 beq.n 8008050 <HAL_UART_IRQHandler+0x50>
- 8008128: 4620 mov r0, r4
- 800812a: 4790 blx r2
- 800812c: 6823 ldr r3, [r4, #0]
- 800812e: e78f b.n 8008050 <HAL_UART_IRQHandler+0x50>
- 8008130: 4620 mov r0, r4
- 8008132: f7ff ff33 bl 8007f9c <HAL_UART_ErrorCallback>
- 8008136: 67e5 str r5, [r4, #124] ; 0x7c
- 8008138: bd70 pop {r4, r5, r6, pc}
- 800813a: bf00 nop
- 800813c: 08008141 .word 0x08008141
-
-08008140 <UART_DMAAbortOnError>:
- 8008140: b508 push {r3, lr}
- 8008142: 2200 movs r2, #0
- 8008144: 6b83 ldr r3, [r0, #56] ; 0x38
- 8008146: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- 800814a: 4618 mov r0, r3
- 800814c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
- 8008150: f7ff ff24 bl 8007f9c <HAL_UART_ErrorCallback>
- 8008154: bd08 pop {r3, pc}
- 8008156: bf00 nop
-
-08008158 <UART_AdvFeatureConfig>:
- 8008158: 6a43 ldr r3, [r0, #36] ; 0x24
- 800815a: 07da lsls r2, r3, #31
- 800815c: b410 push {r4}
- 800815e: d506 bpl.n 800816e <UART_AdvFeatureConfig+0x16>
- 8008160: 6801 ldr r1, [r0, #0]
- 8008162: 6a84 ldr r4, [r0, #40] ; 0x28
- 8008164: 684a ldr r2, [r1, #4]
- 8008166: f422 3200 bic.w r2, r2, #131072 ; 0x20000
- 800816a: 4322 orrs r2, r4
- 800816c: 604a str r2, [r1, #4]
- 800816e: 079c lsls r4, r3, #30
- 8008170: d506 bpl.n 8008180 <UART_AdvFeatureConfig+0x28>
- 8008172: 6801 ldr r1, [r0, #0]
- 8008174: 6ac4 ldr r4, [r0, #44] ; 0x2c
- 8008176: 684a ldr r2, [r1, #4]
- 8008178: f422 3280 bic.w r2, r2, #65536 ; 0x10000
- 800817c: 4322 orrs r2, r4
- 800817e: 604a str r2, [r1, #4]
- 8008180: 0759 lsls r1, r3, #29
- 8008182: d506 bpl.n 8008192 <UART_AdvFeatureConfig+0x3a>
- 8008184: 6801 ldr r1, [r0, #0]
- 8008186: 6b04 ldr r4, [r0, #48] ; 0x30
- 8008188: 684a ldr r2, [r1, #4]
- 800818a: f422 2280 bic.w r2, r2, #262144 ; 0x40000
- 800818e: 4322 orrs r2, r4
- 8008190: 604a str r2, [r1, #4]
- 8008192: 071a lsls r2, r3, #28
- 8008194: d506 bpl.n 80081a4 <UART_AdvFeatureConfig+0x4c>
- 8008196: 6801 ldr r1, [r0, #0]
- 8008198: 6b44 ldr r4, [r0, #52] ; 0x34
- 800819a: 684a ldr r2, [r1, #4]
- 800819c: f422 4200 bic.w r2, r2, #32768 ; 0x8000
- 80081a0: 4322 orrs r2, r4
- 80081a2: 604a str r2, [r1, #4]
- 80081a4: 06dc lsls r4, r3, #27
- 80081a6: d506 bpl.n 80081b6 <UART_AdvFeatureConfig+0x5e>
- 80081a8: 6801 ldr r1, [r0, #0]
- 80081aa: 6b84 ldr r4, [r0, #56] ; 0x38
- 80081ac: 688a ldr r2, [r1, #8]
- 80081ae: f422 5280 bic.w r2, r2, #4096 ; 0x1000
- 80081b2: 4322 orrs r2, r4
- 80081b4: 608a str r2, [r1, #8]
- 80081b6: 0699 lsls r1, r3, #26
- 80081b8: d506 bpl.n 80081c8 <UART_AdvFeatureConfig+0x70>
- 80081ba: 6801 ldr r1, [r0, #0]
- 80081bc: 6bc4 ldr r4, [r0, #60] ; 0x3c
- 80081be: 688a ldr r2, [r1, #8]
- 80081c0: f422 5200 bic.w r2, r2, #8192 ; 0x2000
- 80081c4: 4322 orrs r2, r4
- 80081c6: 608a str r2, [r1, #8]
- 80081c8: 065a lsls r2, r3, #25
- 80081ca: d50a bpl.n 80081e2 <UART_AdvFeatureConfig+0x8a>
- 80081cc: 6801 ldr r1, [r0, #0]
- 80081ce: 6c04 ldr r4, [r0, #64] ; 0x40
- 80081d0: 684a ldr r2, [r1, #4]
- 80081d2: f5b4 1f80 cmp.w r4, #1048576 ; 0x100000
- 80081d6: f422 1280 bic.w r2, r2, #1048576 ; 0x100000
- 80081da: ea42 0204 orr.w r2, r2, r4
- 80081de: 604a str r2, [r1, #4]
- 80081e0: d00b beq.n 80081fa <UART_AdvFeatureConfig+0xa2>
- 80081e2: 061b lsls r3, r3, #24
- 80081e4: d506 bpl.n 80081f4 <UART_AdvFeatureConfig+0x9c>
- 80081e6: 6802 ldr r2, [r0, #0]
- 80081e8: 6c81 ldr r1, [r0, #72] ; 0x48
- 80081ea: 6853 ldr r3, [r2, #4]
- 80081ec: f423 2300 bic.w r3, r3, #524288 ; 0x80000
- 80081f0: 430b orrs r3, r1
- 80081f2: 6053 str r3, [r2, #4]
- 80081f4: f85d 4b04 ldr.w r4, [sp], #4
- 80081f8: 4770 bx lr
- 80081fa: 684a ldr r2, [r1, #4]
- 80081fc: 6c44 ldr r4, [r0, #68] ; 0x44
- 80081fe: f422 02c0 bic.w r2, r2, #6291456 ; 0x600000
- 8008202: 4322 orrs r2, r4
- 8008204: 604a str r2, [r1, #4]
- 8008206: e7ec b.n 80081e2 <UART_AdvFeatureConfig+0x8a>
-
-08008208 <HAL_UART_Init>:
- 8008208: 2800 cmp r0, #0
- 800820a: d04f beq.n 80082ac <HAL_UART_Init+0xa4>
- 800820c: 6f43 ldr r3, [r0, #116] ; 0x74
- 800820e: b570 push {r4, r5, r6, lr}
- 8008210: 4604 mov r4, r0
- 8008212: 2b00 cmp r3, #0
- 8008214: d045 beq.n 80082a2 <HAL_UART_Init+0x9a>
- 8008216: 6823 ldr r3, [r4, #0]
- 8008218: 2124 movs r1, #36 ; 0x24
- 800821a: 6920 ldr r0, [r4, #16]
- 800821c: 6761 str r1, [r4, #116] ; 0x74
- 800821e: 68a2 ldr r2, [r4, #8]
- 8008220: 6819 ldr r1, [r3, #0]
- 8008222: 4302 orrs r2, r0
- 8008224: 6960 ldr r0, [r4, #20]
- 8008226: f021 0101 bic.w r1, r1, #1
- 800822a: 4dbe ldr r5, [pc, #760] ; (8008524 <HAL_UART_Init+0x31c>)
- 800822c: 4302 orrs r2, r0
- 800822e: 69e0 ldr r0, [r4, #28]
- 8008230: 6019 str r1, [r3, #0]
- 8008232: 6819 ldr r1, [r3, #0]
- 8008234: 4302 orrs r2, r0
- 8008236: 68e6 ldr r6, [r4, #12]
- 8008238: 400d ands r5, r1
- 800823a: 69a1 ldr r1, [r4, #24]
- 800823c: 432a orrs r2, r5
- 800823e: 6a25 ldr r5, [r4, #32]
- 8008240: 601a str r2, [r3, #0]
- 8008242: ea41 0205 orr.w r2, r1, r5
- 8008246: 6859 ldr r1, [r3, #4]
- 8008248: 4db7 ldr r5, [pc, #732] ; (8008528 <HAL_UART_Init+0x320>)
- 800824a: f421 5140 bic.w r1, r1, #12288 ; 0x3000
- 800824e: 42ab cmp r3, r5
- 8008250: ea41 0106 orr.w r1, r1, r6
- 8008254: 6059 str r1, [r3, #4]
- 8008256: 6899 ldr r1, [r3, #8]
- 8008258: f421 6130 bic.w r1, r1, #2816 ; 0xb00
- 800825c: ea42 0201 orr.w r2, r2, r1
- 8008260: 609a str r2, [r3, #8]
- 8008262: d025 beq.n 80082b0 <HAL_UART_Init+0xa8>
- 8008264: 4ab1 ldr r2, [pc, #708] ; (800852c <HAL_UART_Init+0x324>)
- 8008266: 4293 cmp r3, r2
- 8008268: d044 beq.n 80082f4 <HAL_UART_Init+0xec>
- 800826a: 4ab1 ldr r2, [pc, #708] ; (8008530 <HAL_UART_Init+0x328>)
- 800826c: 4293 cmp r3, r2
- 800826e: f000 80d3 beq.w 8008418 <HAL_UART_Init+0x210>
- 8008272: 4ab0 ldr r2, [pc, #704] ; (8008534 <HAL_UART_Init+0x32c>)
- 8008274: 4293 cmp r3, r2
- 8008276: d045 beq.n 8008304 <HAL_UART_Init+0xfc>
- 8008278: 4aaf ldr r2, [pc, #700] ; (8008538 <HAL_UART_Init+0x330>)
- 800827a: 4293 cmp r3, r2
- 800827c: f000 80e1 beq.w 8008442 <HAL_UART_Init+0x23a>
- 8008280: 4aae ldr r2, [pc, #696] ; (800853c <HAL_UART_Init+0x334>)
- 8008282: 4293 cmp r3, r2
- 8008284: f000 816a beq.w 800855c <HAL_UART_Init+0x354>
- 8008288: 4aad ldr r2, [pc, #692] ; (8008540 <HAL_UART_Init+0x338>)
- 800828a: 4293 cmp r3, r2
- 800828c: f000 8179 beq.w 8008582 <HAL_UART_Init+0x37a>
- 8008290: 4aac ldr r2, [pc, #688] ; (8008544 <HAL_UART_Init+0x33c>)
- 8008292: 4293 cmp r3, r2
- 8008294: f000 8135 beq.w 8008502 <HAL_UART_Init+0x2fa>
- 8008298: 2300 movs r3, #0
- 800829a: 2001 movs r0, #1
- 800829c: e9c4 3318 strd r3, r3, [r4, #96] ; 0x60
- 80082a0: bd70 pop {r4, r5, r6, pc}
- 80082a2: f880 3070 strb.w r3, [r0, #112] ; 0x70
- 80082a6: f7fd fd71 bl 8005d8c <HAL_UART_MspInit>
- 80082aa: e7b4 b.n 8008216 <HAL_UART_Init+0xe>
- 80082ac: 2001 movs r0, #1
- 80082ae: 4770 bx lr
- 80082b0: 4ba5 ldr r3, [pc, #660] ; (8008548 <HAL_UART_Init+0x340>)
- 80082b2: 4aa6 ldr r2, [pc, #664] ; (800854c <HAL_UART_Init+0x344>)
- 80082b4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80082b8: f003 0303 and.w r3, r3, #3
- 80082bc: 5cd3 ldrb r3, [r2, r3]
- 80082be: f5b0 4f00 cmp.w r0, #32768 ; 0x8000
- 80082c2: d02f beq.n 8008324 <HAL_UART_Init+0x11c>
- 80082c4: 2b08 cmp r3, #8
- 80082c6: d8e7 bhi.n 8008298 <HAL_UART_Init+0x90>
- 80082c8: a201 add r2, pc, #4 ; (adr r2, 80082d0 <HAL_UART_Init+0xc8>)
- 80082ca: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 80082ce: bf00 nop
- 80082d0: 08008407 .word 0x08008407
- 80082d4: 08008361 .word 0x08008361
- 80082d8: 08008433 .word 0x08008433
- 80082dc: 08008299 .word 0x08008299
- 80082e0: 08008459 .word 0x08008459
- 80082e4: 08008299 .word 0x08008299
- 80082e8: 08008299 .word 0x08008299
- 80082ec: 08008299 .word 0x08008299
- 80082f0: 0800846b .word 0x0800846b
- 80082f4: 4b94 ldr r3, [pc, #592] ; (8008548 <HAL_UART_Init+0x340>)
- 80082f6: 4a96 ldr r2, [pc, #600] ; (8008550 <HAL_UART_Init+0x348>)
- 80082f8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80082fc: f003 030c and.w r3, r3, #12
- 8008300: 5cd3 ldrb r3, [r2, r3]
- 8008302: e7dc b.n 80082be <HAL_UART_Init+0xb6>
- 8008304: 4b90 ldr r3, [pc, #576] ; (8008548 <HAL_UART_Init+0x340>)
- 8008306: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800830a: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 800830e: 2b40 cmp r3, #64 ; 0x40
- 8008310: f000 809f beq.w 8008452 <HAL_UART_Init+0x24a>
- 8008314: d971 bls.n 80083fa <HAL_UART_Init+0x1f2>
- 8008316: 2b80 cmp r3, #128 ; 0x80
- 8008318: f000 8088 beq.w 800842c <HAL_UART_Init+0x224>
- 800831c: 2bc0 cmp r3, #192 ; 0xc0
- 800831e: f000 80b9 beq.w 8008494 <HAL_UART_Init+0x28c>
- 8008322: e7b9 b.n 8008298 <HAL_UART_Init+0x90>
- 8008324: 2b08 cmp r3, #8
- 8008326: d8b7 bhi.n 8008298 <HAL_UART_Init+0x90>
- 8008328: a201 add r2, pc, #4 ; (adr r2, 8008330 <HAL_UART_Init+0x128>)
- 800832a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 800832e: bf00 nop
- 8008330: 080084fd .word 0x080084fd
- 8008334: 080084d3 .word 0x080084d3
- 8008338: 080084ed .word 0x080084ed
- 800833c: 08008299 .word 0x08008299
- 8008340: 080084e7 .word 0x080084e7
- 8008344: 08008299 .word 0x08008299
- 8008348: 08008299 .word 0x08008299
- 800834c: 08008299 .word 0x08008299
- 8008350: 0800849b .word 0x0800849b
- 8008354: 2b00 cmp r3, #0
- 8008356: d19f bne.n 8008298 <HAL_UART_Init+0x90>
- 8008358: f5b0 4f00 cmp.w r0, #32768 ; 0x8000
- 800835c: f000 80b9 beq.w 80084d2 <HAL_UART_Init+0x2ca>
- 8008360: f7fe fd38 bl 8006dd4 <HAL_RCC_GetPCLK2Freq>
- 8008364: 6863 ldr r3, [r4, #4]
- 8008366: eb00 0253 add.w r2, r0, r3, lsr #1
- 800836a: fbb2 f2f3 udiv r2, r2, r3
- 800836e: b292 uxth r2, r2
- 8008370: f1a2 0110 sub.w r1, r2, #16
- 8008374: f64f 73ef movw r3, #65519 ; 0xffef
- 8008378: 4299 cmp r1, r3
- 800837a: d88d bhi.n 8008298 <HAL_UART_Init+0x90>
- 800837c: 6823 ldr r3, [r4, #0]
- 800837e: 2100 movs r1, #0
- 8008380: 60da str r2, [r3, #12]
- 8008382: e9c4 1118 strd r1, r1, [r4, #96] ; 0x60
- 8008386: 6a62 ldr r2, [r4, #36] ; 0x24
- 8008388: 2a00 cmp r2, #0
- 800838a: d176 bne.n 800847a <HAL_UART_Init+0x272>
- 800838c: 685a ldr r2, [r3, #4]
- 800838e: 2100 movs r1, #0
- 8008390: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 8008394: 605a str r2, [r3, #4]
- 8008396: 689a ldr r2, [r3, #8]
- 8008398: f022 022a bic.w r2, r2, #42 ; 0x2a
- 800839c: 609a str r2, [r3, #8]
- 800839e: 681a ldr r2, [r3, #0]
- 80083a0: f042 0201 orr.w r2, r2, #1
- 80083a4: 601a str r2, [r3, #0]
- 80083a6: 67e1 str r1, [r4, #124] ; 0x7c
- 80083a8: f7fd fed4 bl 8006154 <HAL_GetTick>
- 80083ac: 6823 ldr r3, [r4, #0]
- 80083ae: 4606 mov r6, r0
- 80083b0: 681a ldr r2, [r3, #0]
- 80083b2: 0712 lsls r2, r2, #28
- 80083b4: d407 bmi.n 80083c6 <HAL_UART_Init+0x1be>
- 80083b6: 2220 movs r2, #32
- 80083b8: 2300 movs r3, #0
- 80083ba: 6762 str r2, [r4, #116] ; 0x74
- 80083bc: 4618 mov r0, r3
- 80083be: 67a2 str r2, [r4, #120] ; 0x78
- 80083c0: f884 3070 strb.w r3, [r4, #112] ; 0x70
- 80083c4: bd70 pop {r4, r5, r6, pc}
- 80083c6: 69dd ldr r5, [r3, #28]
- 80083c8: f415 1500 ands.w r5, r5, #2097152 ; 0x200000
- 80083cc: d1f3 bne.n 80083b6 <HAL_UART_Init+0x1ae>
- 80083ce: f7fd fec1 bl 8006154 <HAL_GetTick>
- 80083d2: 1b80 subs r0, r0, r6
- 80083d4: 6823 ldr r3, [r4, #0]
- 80083d6: f1b0 7f00 cmp.w r0, #33554432 ; 0x2000000
- 80083da: d3f4 bcc.n 80083c6 <HAL_UART_Init+0x1be>
- 80083dc: 681a ldr r2, [r3, #0]
- 80083de: 2120 movs r1, #32
- 80083e0: 2003 movs r0, #3
- 80083e2: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 80083e6: 601a str r2, [r3, #0]
- 80083e8: 689a ldr r2, [r3, #8]
- 80083ea: f022 0201 bic.w r2, r2, #1
- 80083ee: 609a str r2, [r3, #8]
- 80083f0: 6761 str r1, [r4, #116] ; 0x74
- 80083f2: f884 5070 strb.w r5, [r4, #112] ; 0x70
- 80083f6: 67a1 str r1, [r4, #120] ; 0x78
- 80083f8: bd70 pop {r4, r5, r6, pc}
- 80083fa: 2b00 cmp r3, #0
- 80083fc: f47f af4c bne.w 8008298 <HAL_UART_Init+0x90>
- 8008400: f5b0 4f00 cmp.w r0, #32768 ; 0x8000
- 8008404: d07a beq.n 80084fc <HAL_UART_Init+0x2f4>
- 8008406: f7fe fcd5 bl 8006db4 <HAL_RCC_GetPCLK1Freq>
- 800840a: 6863 ldr r3, [r4, #4]
- 800840c: eb00 0253 add.w r2, r0, r3, lsr #1
- 8008410: fbb2 f2f3 udiv r2, r2, r3
- 8008414: b292 uxth r2, r2
- 8008416: e7ab b.n 8008370 <HAL_UART_Init+0x168>
- 8008418: 4b4b ldr r3, [pc, #300] ; (8008548 <HAL_UART_Init+0x340>)
- 800841a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800841e: f003 0330 and.w r3, r3, #48 ; 0x30
- 8008422: 2b10 cmp r3, #16
- 8008424: d015 beq.n 8008452 <HAL_UART_Init+0x24a>
- 8008426: d9e8 bls.n 80083fa <HAL_UART_Init+0x1f2>
- 8008428: 2b20 cmp r3, #32
- 800842a: d14f bne.n 80084cc <HAL_UART_Init+0x2c4>
- 800842c: f5b0 4f00 cmp.w r0, #32768 ; 0x8000
- 8008430: d05c beq.n 80084ec <HAL_UART_Init+0x2e4>
- 8008432: 6863 ldr r3, [r4, #4]
- 8008434: 4a47 ldr r2, [pc, #284] ; (8008554 <HAL_UART_Init+0x34c>)
- 8008436: eb02 0253 add.w r2, r2, r3, lsr #1
- 800843a: fbb2 f2f3 udiv r2, r2, r3
- 800843e: b292 uxth r2, r2
- 8008440: e796 b.n 8008370 <HAL_UART_Init+0x168>
- 8008442: 4b41 ldr r3, [pc, #260] ; (8008548 <HAL_UART_Init+0x340>)
- 8008444: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8008448: f403 7340 and.w r3, r3, #768 ; 0x300
- 800844c: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8008450: d118 bne.n 8008484 <HAL_UART_Init+0x27c>
- 8008452: f5b0 4f00 cmp.w r0, #32768 ; 0x8000
- 8008456: d046 beq.n 80084e6 <HAL_UART_Init+0x2de>
- 8008458: f7fe fc78 bl 8006d4c <HAL_RCC_GetSysClockFreq>
- 800845c: 6863 ldr r3, [r4, #4]
- 800845e: eb00 0253 add.w r2, r0, r3, lsr #1
- 8008462: fbb2 f2f3 udiv r2, r2, r3
- 8008466: b292 uxth r2, r2
- 8008468: e782 b.n 8008370 <HAL_UART_Init+0x168>
- 800846a: 6863 ldr r3, [r4, #4]
- 800846c: 085a lsrs r2, r3, #1
- 800846e: f502 4200 add.w r2, r2, #32768 ; 0x8000
- 8008472: fbb2 f2f3 udiv r2, r2, r3
- 8008476: b292 uxth r2, r2
- 8008478: e77a b.n 8008370 <HAL_UART_Init+0x168>
- 800847a: 4620 mov r0, r4
- 800847c: f7ff fe6c bl 8008158 <UART_AdvFeatureConfig>
- 8008480: 6823 ldr r3, [r4, #0]
- 8008482: e783 b.n 800838c <HAL_UART_Init+0x184>
- 8008484: d9b9 bls.n 80083fa <HAL_UART_Init+0x1f2>
- 8008486: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 800848a: d0cf beq.n 800842c <HAL_UART_Init+0x224>
- 800848c: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8008490: f47f af02 bne.w 8008298 <HAL_UART_Init+0x90>
- 8008494: f5b0 4f00 cmp.w r0, #32768 ; 0x8000
- 8008498: d1e7 bne.n 800846a <HAL_UART_Init+0x262>
- 800849a: 6862 ldr r2, [r4, #4]
- 800849c: 0853 lsrs r3, r2, #1
- 800849e: f503 3380 add.w r3, r3, #65536 ; 0x10000
- 80084a2: fbb3 f3f2 udiv r3, r3, r2
- 80084a6: b29b uxth r3, r3
- 80084a8: f1a3 0110 sub.w r1, r3, #16
- 80084ac: f64f 72ef movw r2, #65519 ; 0xffef
- 80084b0: 4291 cmp r1, r2
- 80084b2: f63f aef1 bhi.w 8008298 <HAL_UART_Init+0x90>
- 80084b6: f023 010f bic.w r1, r3, #15
- 80084ba: f3c3 0242 ubfx r2, r3, #1, #3
- 80084be: 2000 movs r0, #0
- 80084c0: 6823 ldr r3, [r4, #0]
- 80084c2: 430a orrs r2, r1
- 80084c4: 60da str r2, [r3, #12]
- 80084c6: e9c4 0018 strd r0, r0, [r4, #96] ; 0x60
- 80084ca: e75c b.n 8008386 <HAL_UART_Init+0x17e>
- 80084cc: 2b30 cmp r3, #48 ; 0x30
- 80084ce: d0e1 beq.n 8008494 <HAL_UART_Init+0x28c>
- 80084d0: e6e2 b.n 8008298 <HAL_UART_Init+0x90>
- 80084d2: f7fe fc7f bl 8006dd4 <HAL_RCC_GetPCLK2Freq>
- 80084d6: 6862 ldr r2, [r4, #4]
- 80084d8: 0853 lsrs r3, r2, #1
- 80084da: eb03 0340 add.w r3, r3, r0, lsl #1
- 80084de: fbb3 f3f2 udiv r3, r3, r2
- 80084e2: b29b uxth r3, r3
- 80084e4: e7e0 b.n 80084a8 <HAL_UART_Init+0x2a0>
- 80084e6: f7fe fc31 bl 8006d4c <HAL_RCC_GetSysClockFreq>
- 80084ea: e7f4 b.n 80084d6 <HAL_UART_Init+0x2ce>
- 80084ec: 6862 ldr r2, [r4, #4]
- 80084ee: 4b1a ldr r3, [pc, #104] ; (8008558 <HAL_UART_Init+0x350>)
- 80084f0: eb03 0352 add.w r3, r3, r2, lsr #1
- 80084f4: fbb3 f3f2 udiv r3, r3, r2
- 80084f8: b29b uxth r3, r3
- 80084fa: e7d5 b.n 80084a8 <HAL_UART_Init+0x2a0>
- 80084fc: f7fe fc5a bl 8006db4 <HAL_RCC_GetPCLK1Freq>
- 8008500: e7e9 b.n 80084d6 <HAL_UART_Init+0x2ce>
- 8008502: 4b11 ldr r3, [pc, #68] ; (8008548 <HAL_UART_Init+0x340>)
- 8008504: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8008508: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 800850c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8008510: d09f beq.n 8008452 <HAL_UART_Init+0x24a>
- 8008512: f67f af72 bls.w 80083fa <HAL_UART_Init+0x1f2>
- 8008516: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 800851a: d087 beq.n 800842c <HAL_UART_Init+0x224>
- 800851c: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 8008520: d0b8 beq.n 8008494 <HAL_UART_Init+0x28c>
- 8008522: e6b9 b.n 8008298 <HAL_UART_Init+0x90>
- 8008524: efff69f3 .word 0xefff69f3
- 8008528: 40011000 .word 0x40011000
- 800852c: 40004400 .word 0x40004400
- 8008530: 40004800 .word 0x40004800
- 8008534: 40004c00 .word 0x40004c00
- 8008538: 40005000 .word 0x40005000
- 800853c: 40011400 .word 0x40011400
- 8008540: 40007800 .word 0x40007800
- 8008544: 40007c00 .word 0x40007c00
- 8008548: 40023800 .word 0x40023800
- 800854c: 0800a4b0 .word 0x0800a4b0
- 8008550: 0800a4b4 .word 0x0800a4b4
- 8008554: 00f42400 .word 0x00f42400
- 8008558: 01e84800 .word 0x01e84800
- 800855c: 4b13 ldr r3, [pc, #76] ; (80085ac <HAL_UART_Init+0x3a4>)
- 800855e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8008562: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 8008566: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 800856a: f43f af72 beq.w 8008452 <HAL_UART_Init+0x24a>
- 800856e: f67f aef1 bls.w 8008354 <HAL_UART_Init+0x14c>
- 8008572: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 8008576: f43f af59 beq.w 800842c <HAL_UART_Init+0x224>
- 800857a: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 800857e: d089 beq.n 8008494 <HAL_UART_Init+0x28c>
- 8008580: e68a b.n 8008298 <HAL_UART_Init+0x90>
- 8008582: 4b0a ldr r3, [pc, #40] ; (80085ac <HAL_UART_Init+0x3a4>)
- 8008584: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8008588: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 800858c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8008590: f43f af5f beq.w 8008452 <HAL_UART_Init+0x24a>
- 8008594: f67f af31 bls.w 80083fa <HAL_UART_Init+0x1f2>
- 8008598: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 800859c: f43f af46 beq.w 800842c <HAL_UART_Init+0x224>
- 80085a0: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 80085a4: f43f af76 beq.w 8008494 <HAL_UART_Init+0x28c>
- 80085a8: e676 b.n 8008298 <HAL_UART_Init+0x90>
- 80085aa: bf00 nop
- 80085ac: 40023800 .word 0x40023800
-
-080085b0 <cos>:
- 80085b0: b51f push {r0, r1, r2, r3, r4, lr}
- 80085b2: eeb0 7b40 vmov.f64 d7, d0
- 80085b6: ee17 3a90 vmov r3, s15
- 80085ba: 4a19 ldr r2, [pc, #100] ; (8008620 <cos+0x70>)
- 80085bc: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 80085c0: 4293 cmp r3, r2
- 80085c2: dc04 bgt.n 80085ce <cos+0x1e>
- 80085c4: ed9f 1b14 vldr d1, [pc, #80] ; 8008618 <cos+0x68>
- 80085c8: f000 fb56 bl 8008c78 <__kernel_cos>
- 80085cc: e004 b.n 80085d8 <cos+0x28>
- 80085ce: 4a15 ldr r2, [pc, #84] ; (8008624 <cos+0x74>)
- 80085d0: 4293 cmp r3, r2
- 80085d2: dd04 ble.n 80085de <cos+0x2e>
- 80085d4: ee30 0b40 vsub.f64 d0, d0, d0
- 80085d8: b005 add sp, #20
- 80085da: f85d fb04 ldr.w pc, [sp], #4
- 80085de: 4668 mov r0, sp
- 80085e0: f000 f8e2 bl 80087a8 <__ieee754_rem_pio2>
- 80085e4: f000 0003 and.w r0, r0, #3
- 80085e8: 2801 cmp r0, #1
- 80085ea: ed9d 1b02 vldr d1, [sp, #8]
- 80085ee: ed9d 0b00 vldr d0, [sp]
- 80085f2: d007 beq.n 8008604 <cos+0x54>
- 80085f4: 2802 cmp r0, #2
- 80085f6: d00a beq.n 800860e <cos+0x5e>
- 80085f8: 2800 cmp r0, #0
- 80085fa: d0e5 beq.n 80085c8 <cos+0x18>
- 80085fc: 2001 movs r0, #1
- 80085fe: f000 fe43 bl 8009288 <__kernel_sin>
- 8008602: e7e9 b.n 80085d8 <cos+0x28>
- 8008604: f000 fe40 bl 8009288 <__kernel_sin>
- 8008608: eeb1 0b40 vneg.f64 d0, d0
- 800860c: e7e4 b.n 80085d8 <cos+0x28>
- 800860e: f000 fb33 bl 8008c78 <__kernel_cos>
- 8008612: e7f9 b.n 8008608 <cos+0x58>
- 8008614: f3af 8000 nop.w
- ...
- 8008620: 3fe921fb .word 0x3fe921fb
- 8008624: 7fefffff .word 0x7fefffff
-
-08008628 <sin>:
- 8008628: b51f push {r0, r1, r2, r3, r4, lr}
- 800862a: eeb0 7b40 vmov.f64 d7, d0
- 800862e: ee17 3a90 vmov r3, s15
- 8008632: 4a19 ldr r2, [pc, #100] ; (8008698 <sin+0x70>)
- 8008634: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 8008638: 4293 cmp r3, r2
- 800863a: dc05 bgt.n 8008648 <sin+0x20>
- 800863c: ed9f 1b14 vldr d1, [pc, #80] ; 8008690 <sin+0x68>
- 8008640: 2000 movs r0, #0
- 8008642: f000 fe21 bl 8009288 <__kernel_sin>
- 8008646: e004 b.n 8008652 <sin+0x2a>
- 8008648: 4a14 ldr r2, [pc, #80] ; (800869c <sin+0x74>)
- 800864a: 4293 cmp r3, r2
- 800864c: dd04 ble.n 8008658 <sin+0x30>
- 800864e: ee30 0b40 vsub.f64 d0, d0, d0
- 8008652: b005 add sp, #20
- 8008654: f85d fb04 ldr.w pc, [sp], #4
- 8008658: 4668 mov r0, sp
- 800865a: f000 f8a5 bl 80087a8 <__ieee754_rem_pio2>
- 800865e: f000 0003 and.w r0, r0, #3
- 8008662: 2801 cmp r0, #1
- 8008664: ed9d 1b02 vldr d1, [sp, #8]
- 8008668: ed9d 0b00 vldr d0, [sp]
- 800866c: d004 beq.n 8008678 <sin+0x50>
- 800866e: 2802 cmp r0, #2
- 8008670: d005 beq.n 800867e <sin+0x56>
- 8008672: b950 cbnz r0, 800868a <sin+0x62>
- 8008674: 2001 movs r0, #1
- 8008676: e7e4 b.n 8008642 <sin+0x1a>
- 8008678: f000 fafe bl 8008c78 <__kernel_cos>
- 800867c: e7e9 b.n 8008652 <sin+0x2a>
- 800867e: 2001 movs r0, #1
- 8008680: f000 fe02 bl 8009288 <__kernel_sin>
- 8008684: eeb1 0b40 vneg.f64 d0, d0
- 8008688: e7e3 b.n 8008652 <sin+0x2a>
- 800868a: f000 faf5 bl 8008c78 <__kernel_cos>
- 800868e: e7f9 b.n 8008684 <sin+0x5c>
- ...
- 8008698: 3fe921fb .word 0x3fe921fb
- 800869c: 7fefffff .word 0x7fefffff
-
-080086a0 <cosf>:
- 80086a0: ee10 3a10 vmov r3, s0
- 80086a4: b507 push {r0, r1, r2, lr}
- 80086a6: 4a1c ldr r2, [pc, #112] ; (8008718 <cosf+0x78>)
- 80086a8: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 80086ac: 4293 cmp r3, r2
- 80086ae: dc04 bgt.n 80086ba <cosf+0x1a>
- 80086b0: eddf 0a1a vldr s1, [pc, #104] ; 800871c <cosf+0x7c>
- 80086b4: f000 fe40 bl 8009338 <__kernel_cosf>
- 80086b8: e004 b.n 80086c4 <cosf+0x24>
- 80086ba: f1b3 4fff cmp.w r3, #2139095040 ; 0x7f800000
- 80086be: db04 blt.n 80086ca <cosf+0x2a>
- 80086c0: ee30 0a40 vsub.f32 s0, s0, s0
- 80086c4: b003 add sp, #12
- 80086c6: f85d fb04 ldr.w pc, [sp], #4
- 80086ca: 4668 mov r0, sp
- 80086cc: f000 f9a8 bl 8008a20 <__ieee754_rem_pio2f>
- 80086d0: f000 0003 and.w r0, r0, #3
- 80086d4: 2801 cmp r0, #1
- 80086d6: d007 beq.n 80086e8 <cosf+0x48>
- 80086d8: 2802 cmp r0, #2
- 80086da: d00e beq.n 80086fa <cosf+0x5a>
- 80086dc: b9a0 cbnz r0, 8008708 <cosf+0x68>
- 80086de: eddd 0a01 vldr s1, [sp, #4]
- 80086e2: ed9d 0a00 vldr s0, [sp]
- 80086e6: e7e5 b.n 80086b4 <cosf+0x14>
- 80086e8: eddd 0a01 vldr s1, [sp, #4]
- 80086ec: ed9d 0a00 vldr s0, [sp]
- 80086f0: f001 f902 bl 80098f8 <__kernel_sinf>
- 80086f4: eeb1 0a40 vneg.f32 s0, s0
- 80086f8: e7e4 b.n 80086c4 <cosf+0x24>
- 80086fa: eddd 0a01 vldr s1, [sp, #4]
- 80086fe: ed9d 0a00 vldr s0, [sp]
- 8008702: f000 fe19 bl 8009338 <__kernel_cosf>
- 8008706: e7f5 b.n 80086f4 <cosf+0x54>
- 8008708: 2001 movs r0, #1
- 800870a: eddd 0a01 vldr s1, [sp, #4]
- 800870e: ed9d 0a00 vldr s0, [sp]
- 8008712: f001 f8f1 bl 80098f8 <__kernel_sinf>
- 8008716: e7d5 b.n 80086c4 <cosf+0x24>
- 8008718: 3f490fd8 .word 0x3f490fd8
- 800871c: 00000000 .word 0x00000000
-
-08008720 <sinf>:
- 8008720: ee10 3a10 vmov r3, s0
- 8008724: b507 push {r0, r1, r2, lr}
- 8008726: 4a1d ldr r2, [pc, #116] ; (800879c <sinf+0x7c>)
- 8008728: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 800872c: 4293 cmp r3, r2
- 800872e: dc05 bgt.n 800873c <sinf+0x1c>
- 8008730: eddf 0a1b vldr s1, [pc, #108] ; 80087a0 <sinf+0x80>
- 8008734: 2000 movs r0, #0
- 8008736: f001 f8df bl 80098f8 <__kernel_sinf>
- 800873a: e004 b.n 8008746 <sinf+0x26>
- 800873c: f1b3 4fff cmp.w r3, #2139095040 ; 0x7f800000
- 8008740: db04 blt.n 800874c <sinf+0x2c>
- 8008742: ee30 0a40 vsub.f32 s0, s0, s0
- 8008746: b003 add sp, #12
- 8008748: f85d fb04 ldr.w pc, [sp], #4
- 800874c: 4668 mov r0, sp
- 800874e: f000 f967 bl 8008a20 <__ieee754_rem_pio2f>
- 8008752: f000 0003 and.w r0, r0, #3
- 8008756: 2801 cmp r0, #1
- 8008758: d008 beq.n 800876c <sinf+0x4c>
- 800875a: 2802 cmp r0, #2
- 800875c: d00d beq.n 800877a <sinf+0x5a>
- 800875e: b9b0 cbnz r0, 800878e <sinf+0x6e>
- 8008760: 2001 movs r0, #1
- 8008762: eddd 0a01 vldr s1, [sp, #4]
- 8008766: ed9d 0a00 vldr s0, [sp]
- 800876a: e7e4 b.n 8008736 <sinf+0x16>
- 800876c: eddd 0a01 vldr s1, [sp, #4]
- 8008770: ed9d 0a00 vldr s0, [sp]
- 8008774: f000 fde0 bl 8009338 <__kernel_cosf>
- 8008778: e7e5 b.n 8008746 <sinf+0x26>
- 800877a: 2001 movs r0, #1
- 800877c: eddd 0a01 vldr s1, [sp, #4]
- 8008780: ed9d 0a00 vldr s0, [sp]
- 8008784: f001 f8b8 bl 80098f8 <__kernel_sinf>
- 8008788: eeb1 0a40 vneg.f32 s0, s0
- 800878c: e7db b.n 8008746 <sinf+0x26>
- 800878e: eddd 0a01 vldr s1, [sp, #4]
- 8008792: ed9d 0a00 vldr s0, [sp]
- 8008796: f000 fdcf bl 8009338 <__kernel_cosf>
- 800879a: e7f5 b.n 8008788 <sinf+0x68>
- 800879c: 3f490fd8 .word 0x3f490fd8
- ...
-
-080087a8 <__ieee754_rem_pio2>:
- 80087a8: b570 push {r4, r5, r6, lr}
- 80087aa: eeb0 7b40 vmov.f64 d7, d0
- 80087ae: ee17 5a90 vmov r5, s15
- 80087b2: 4b95 ldr r3, [pc, #596] ; (8008a08 <__ieee754_rem_pio2+0x260>)
- 80087b4: f025 4600 bic.w r6, r5, #2147483648 ; 0x80000000
- 80087b8: 429e cmp r6, r3
- 80087ba: b088 sub sp, #32
- 80087bc: 4604 mov r4, r0
- 80087be: dc07 bgt.n 80087d0 <__ieee754_rem_pio2+0x28>
- 80087c0: 2200 movs r2, #0
- 80087c2: 2300 movs r3, #0
- 80087c4: ed84 0b00 vstr d0, [r4]
- 80087c8: e9c0 2302 strd r2, r3, [r0, #8]
- 80087cc: 2000 movs r0, #0
- 80087ce: e01b b.n 8008808 <__ieee754_rem_pio2+0x60>
- 80087d0: 4b8e ldr r3, [pc, #568] ; (8008a0c <__ieee754_rem_pio2+0x264>)
- 80087d2: 429e cmp r6, r3
- 80087d4: dc3b bgt.n 800884e <__ieee754_rem_pio2+0xa6>
- 80087d6: f5a3 231b sub.w r3, r3, #634880 ; 0x9b000
- 80087da: 2d00 cmp r5, #0
- 80087dc: ed9f 6b7a vldr d6, [pc, #488] ; 80089c8 <__ieee754_rem_pio2+0x220>
- 80087e0: f5a3 63f0 sub.w r3, r3, #1920 ; 0x780
- 80087e4: dd19 ble.n 800881a <__ieee754_rem_pio2+0x72>
- 80087e6: ee30 7b46 vsub.f64 d7, d0, d6
- 80087ea: 429e cmp r6, r3
- 80087ec: d00e beq.n 800880c <__ieee754_rem_pio2+0x64>
- 80087ee: ed9f 6b78 vldr d6, [pc, #480] ; 80089d0 <__ieee754_rem_pio2+0x228>
- 80087f2: ee37 5b46 vsub.f64 d5, d7, d6
- 80087f6: ee37 7b45 vsub.f64 d7, d7, d5
- 80087fa: ed84 5b00 vstr d5, [r4]
- 80087fe: ee37 7b46 vsub.f64 d7, d7, d6
- 8008802: ed84 7b02 vstr d7, [r4, #8]
- 8008806: 2001 movs r0, #1
- 8008808: b008 add sp, #32
- 800880a: bd70 pop {r4, r5, r6, pc}
- 800880c: ed9f 6b72 vldr d6, [pc, #456] ; 80089d8 <__ieee754_rem_pio2+0x230>
- 8008810: ee37 7b46 vsub.f64 d7, d7, d6
- 8008814: ed9f 6b72 vldr d6, [pc, #456] ; 80089e0 <__ieee754_rem_pio2+0x238>
- 8008818: e7eb b.n 80087f2 <__ieee754_rem_pio2+0x4a>
- 800881a: 429e cmp r6, r3
- 800881c: ee30 7b06 vadd.f64 d7, d0, d6
- 8008820: d00e beq.n 8008840 <__ieee754_rem_pio2+0x98>
- 8008822: ed9f 6b6b vldr d6, [pc, #428] ; 80089d0 <__ieee754_rem_pio2+0x228>
- 8008826: ee37 5b06 vadd.f64 d5, d7, d6
- 800882a: ee37 7b45 vsub.f64 d7, d7, d5
- 800882e: ed84 5b00 vstr d5, [r4]
- 8008832: ee37 7b06 vadd.f64 d7, d7, d6
- 8008836: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 800883a: ed84 7b02 vstr d7, [r4, #8]
- 800883e: e7e3 b.n 8008808 <__ieee754_rem_pio2+0x60>
- 8008840: ed9f 6b65 vldr d6, [pc, #404] ; 80089d8 <__ieee754_rem_pio2+0x230>
- 8008844: ee37 7b06 vadd.f64 d7, d7, d6
- 8008848: ed9f 6b65 vldr d6, [pc, #404] ; 80089e0 <__ieee754_rem_pio2+0x238>
- 800884c: e7eb b.n 8008826 <__ieee754_rem_pio2+0x7e>
- 800884e: 4b70 ldr r3, [pc, #448] ; (8008a10 <__ieee754_rem_pio2+0x268>)
- 8008850: 429e cmp r6, r3
- 8008852: dc6c bgt.n 800892e <__ieee754_rem_pio2+0x186>
- 8008854: f001 f898 bl 8009988 <fabs>
- 8008858: eeb6 7b00 vmov.f64 d7, #96 ; 0x3f000000 0.5
- 800885c: ed9f 6b62 vldr d6, [pc, #392] ; 80089e8 <__ieee754_rem_pio2+0x240>
- 8008860: eea0 7b06 vfma.f64 d7, d0, d6
- 8008864: eefd 7bc7 vcvt.s32.f64 s15, d7
- 8008868: eeb8 4be7 vcvt.f64.s32 d4, s15
- 800886c: ee17 0a90 vmov r0, s15
- 8008870: eeb1 5b44 vneg.f64 d5, d4
- 8008874: ed9f 7b54 vldr d7, [pc, #336] ; 80089c8 <__ieee754_rem_pio2+0x220>
- 8008878: eea5 0b07 vfma.f64 d0, d5, d7
- 800887c: ed9f 7b54 vldr d7, [pc, #336] ; 80089d0 <__ieee754_rem_pio2+0x228>
- 8008880: 281f cmp r0, #31
- 8008882: ee24 7b07 vmul.f64 d7, d4, d7
- 8008886: ee30 6b47 vsub.f64 d6, d0, d7
- 800888a: dc08 bgt.n 800889e <__ieee754_rem_pio2+0xf6>
- 800888c: 1e42 subs r2, r0, #1
- 800888e: 4b61 ldr r3, [pc, #388] ; (8008a14 <__ieee754_rem_pio2+0x26c>)
- 8008890: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 8008894: 42b3 cmp r3, r6
- 8008896: d002 beq.n 800889e <__ieee754_rem_pio2+0xf6>
- 8008898: ed84 6b00 vstr d6, [r4]
- 800889c: e022 b.n 80088e4 <__ieee754_rem_pio2+0x13c>
- 800889e: ee16 3a90 vmov r3, s13
- 80088a2: 1536 asrs r6, r6, #20
- 80088a4: f3c3 530a ubfx r3, r3, #20, #11
- 80088a8: 1af3 subs r3, r6, r3
- 80088aa: 2b10 cmp r3, #16
- 80088ac: ddf4 ble.n 8008898 <__ieee754_rem_pio2+0xf0>
- 80088ae: eeb0 6b40 vmov.f64 d6, d0
- 80088b2: ed9f 3b49 vldr d3, [pc, #292] ; 80089d8 <__ieee754_rem_pio2+0x230>
- 80088b6: eea5 6b03 vfma.f64 d6, d5, d3
- 80088ba: ee30 7b46 vsub.f64 d7, d0, d6
- 80088be: eea5 7b03 vfma.f64 d7, d5, d3
- 80088c2: ed9f 3b47 vldr d3, [pc, #284] ; 80089e0 <__ieee754_rem_pio2+0x238>
- 80088c6: ee94 7b03 vfnms.f64 d7, d4, d3
- 80088ca: ee36 3b47 vsub.f64 d3, d6, d7
- 80088ce: ee13 3a90 vmov r3, s7
- 80088d2: f3c3 530a ubfx r3, r3, #20, #11
- 80088d6: 1af6 subs r6, r6, r3
- 80088d8: 2e31 cmp r6, #49 ; 0x31
- 80088da: dc17 bgt.n 800890c <__ieee754_rem_pio2+0x164>
- 80088dc: eeb0 0b46 vmov.f64 d0, d6
- 80088e0: ed84 3b00 vstr d3, [r4]
- 80088e4: ed94 6b00 vldr d6, [r4]
- 80088e8: 2d00 cmp r5, #0
- 80088ea: ee30 0b46 vsub.f64 d0, d0, d6
- 80088ee: ee30 7b47 vsub.f64 d7, d0, d7
- 80088f2: ed84 7b02 vstr d7, [r4, #8]
- 80088f6: da87 bge.n 8008808 <__ieee754_rem_pio2+0x60>
- 80088f8: eeb1 6b46 vneg.f64 d6, d6
- 80088fc: ed84 6b00 vstr d6, [r4]
- 8008900: eeb1 7b47 vneg.f64 d7, d7
- 8008904: 4240 negs r0, r0
- 8008906: ed84 7b02 vstr d7, [r4, #8]
- 800890a: e77d b.n 8008808 <__ieee754_rem_pio2+0x60>
- 800890c: ed9f 3b38 vldr d3, [pc, #224] ; 80089f0 <__ieee754_rem_pio2+0x248>
- 8008910: eeb0 0b46 vmov.f64 d0, d6
- 8008914: eea5 0b03 vfma.f64 d0, d5, d3
- 8008918: ee36 7b40 vsub.f64 d7, d6, d0
- 800891c: ed9f 6b36 vldr d6, [pc, #216] ; 80089f8 <__ieee754_rem_pio2+0x250>
- 8008920: eea5 7b03 vfma.f64 d7, d5, d3
- 8008924: ee94 7b06 vfnms.f64 d7, d4, d6
- 8008928: ee30 6b47 vsub.f64 d6, d0, d7
- 800892c: e7b4 b.n 8008898 <__ieee754_rem_pio2+0xf0>
- 800892e: 4b3a ldr r3, [pc, #232] ; (8008a18 <__ieee754_rem_pio2+0x270>)
- 8008930: 429e cmp r6, r3
- 8008932: dd06 ble.n 8008942 <__ieee754_rem_pio2+0x19a>
- 8008934: ee30 7b40 vsub.f64 d7, d0, d0
- 8008938: ed80 7b02 vstr d7, [r0, #8]
- 800893c: ed80 7b00 vstr d7, [r0]
- 8008940: e744 b.n 80087cc <__ieee754_rem_pio2+0x24>
- 8008942: 1532 asrs r2, r6, #20
- 8008944: f2a2 4216 subw r2, r2, #1046 ; 0x416
- 8008948: ee10 0a10 vmov r0, s0
- 800894c: eba6 5102 sub.w r1, r6, r2, lsl #20
- 8008950: ec41 0b17 vmov d7, r0, r1
- 8008954: eebd 6bc7 vcvt.s32.f64 s12, d7
- 8008958: ed9f 5b29 vldr d5, [pc, #164] ; 8008a00 <__ieee754_rem_pio2+0x258>
- 800895c: eeb8 6bc6 vcvt.f64.s32 d6, s12
- 8008960: ee37 7b46 vsub.f64 d7, d7, d6
- 8008964: ed8d 6b02 vstr d6, [sp, #8]
- 8008968: ee27 7b05 vmul.f64 d7, d7, d5
- 800896c: eebd 6bc7 vcvt.s32.f64 s12, d7
- 8008970: a908 add r1, sp, #32
- 8008972: eeb8 6bc6 vcvt.f64.s32 d6, s12
- 8008976: ee37 7b46 vsub.f64 d7, d7, d6
- 800897a: ed8d 6b04 vstr d6, [sp, #16]
- 800897e: ee27 7b05 vmul.f64 d7, d7, d5
- 8008982: ed8d 7b06 vstr d7, [sp, #24]
- 8008986: 2303 movs r3, #3
- 8008988: ed31 7b02 vldmdb r1!, {d7}
- 800898c: eeb5 7b40 vcmp.f64 d7, #0.0
- 8008990: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8008994: f103 30ff add.w r0, r3, #4294967295 ; 0xffffffff
- 8008998: d013 beq.n 80089c2 <__ieee754_rem_pio2+0x21a>
- 800899a: 4920 ldr r1, [pc, #128] ; (8008a1c <__ieee754_rem_pio2+0x274>)
- 800899c: 9101 str r1, [sp, #4]
- 800899e: 2102 movs r1, #2
- 80089a0: 9100 str r1, [sp, #0]
- 80089a2: a802 add r0, sp, #8
- 80089a4: 4621 mov r1, r4
- 80089a6: f000 f9d3 bl 8008d50 <__kernel_rem_pio2>
- 80089aa: 2d00 cmp r5, #0
- 80089ac: f6bf af2c bge.w 8008808 <__ieee754_rem_pio2+0x60>
- 80089b0: ed94 7b00 vldr d7, [r4]
- 80089b4: eeb1 7b47 vneg.f64 d7, d7
- 80089b8: ed84 7b00 vstr d7, [r4]
- 80089bc: ed94 7b02 vldr d7, [r4, #8]
- 80089c0: e79e b.n 8008900 <__ieee754_rem_pio2+0x158>
- 80089c2: 4603 mov r3, r0
- 80089c4: e7e0 b.n 8008988 <__ieee754_rem_pio2+0x1e0>
- 80089c6: bf00 nop
- 80089c8: 54400000 .word 0x54400000
- 80089cc: 3ff921fb .word 0x3ff921fb
- 80089d0: 1a626331 .word 0x1a626331
- 80089d4: 3dd0b461 .word 0x3dd0b461
- 80089d8: 1a600000 .word 0x1a600000
- 80089dc: 3dd0b461 .word 0x3dd0b461
- 80089e0: 2e037073 .word 0x2e037073
- 80089e4: 3ba3198a .word 0x3ba3198a
- 80089e8: 6dc9c883 .word 0x6dc9c883
- 80089ec: 3fe45f30 .word 0x3fe45f30
- 80089f0: 2e000000 .word 0x2e000000
- 80089f4: 3ba3198a .word 0x3ba3198a
- 80089f8: 252049c1 .word 0x252049c1
- 80089fc: 397b839a .word 0x397b839a
- 8008a00: 00000000 .word 0x00000000
- 8008a04: 41700000 .word 0x41700000
- 8008a08: 3fe921fb .word 0x3fe921fb
- 8008a0c: 4002d97b .word 0x4002d97b
- 8008a10: 413921fb .word 0x413921fb
- 8008a14: 0800a4c4 .word 0x0800a4c4
- 8008a18: 7fefffff .word 0x7fefffff
- 8008a1c: 0800a544 .word 0x0800a544
-
-08008a20 <__ieee754_rem_pio2f>:
- 8008a20: b5f0 push {r4, r5, r6, r7, lr}
- 8008a22: ee10 6a10 vmov r6, s0
- 8008a26: 4b86 ldr r3, [pc, #536] ; (8008c40 <__ieee754_rem_pio2f+0x220>)
- 8008a28: f026 4400 bic.w r4, r6, #2147483648 ; 0x80000000
- 8008a2c: 429c cmp r4, r3
- 8008a2e: b087 sub sp, #28
- 8008a30: 4605 mov r5, r0
- 8008a32: dc05 bgt.n 8008a40 <__ieee754_rem_pio2f+0x20>
- 8008a34: 2300 movs r3, #0
- 8008a36: ed85 0a00 vstr s0, [r5]
- 8008a3a: 6043 str r3, [r0, #4]
- 8008a3c: 2000 movs r0, #0
- 8008a3e: e020 b.n 8008a82 <__ieee754_rem_pio2f+0x62>
- 8008a40: 4b80 ldr r3, [pc, #512] ; (8008c44 <__ieee754_rem_pio2f+0x224>)
- 8008a42: 429c cmp r4, r3
- 8008a44: dc38 bgt.n 8008ab8 <__ieee754_rem_pio2f+0x98>
- 8008a46: 2e00 cmp r6, #0
- 8008a48: f024 040f bic.w r4, r4, #15
- 8008a4c: ed9f 7a7e vldr s14, [pc, #504] ; 8008c48 <__ieee754_rem_pio2f+0x228>
- 8008a50: 4b7e ldr r3, [pc, #504] ; (8008c4c <__ieee754_rem_pio2f+0x22c>)
- 8008a52: dd18 ble.n 8008a86 <__ieee754_rem_pio2f+0x66>
- 8008a54: 429c cmp r4, r3
- 8008a56: ee70 7a47 vsub.f32 s15, s0, s14
- 8008a5a: bf09 itett eq
- 8008a5c: ed9f 7a7c vldreq s14, [pc, #496] ; 8008c50 <__ieee754_rem_pio2f+0x230>
- 8008a60: ed9f 7a7c vldrne s14, [pc, #496] ; 8008c54 <__ieee754_rem_pio2f+0x234>
- 8008a64: ee77 7ac7 vsubeq.f32 s15, s15, s14
- 8008a68: ed9f 7a7b vldreq s14, [pc, #492] ; 8008c58 <__ieee754_rem_pio2f+0x238>
- 8008a6c: ee77 6ac7 vsub.f32 s13, s15, s14
- 8008a70: ee77 7ae6 vsub.f32 s15, s15, s13
- 8008a74: edc0 6a00 vstr s13, [r0]
- 8008a78: ee77 7ac7 vsub.f32 s15, s15, s14
- 8008a7c: edc0 7a01 vstr s15, [r0, #4]
- 8008a80: 2001 movs r0, #1
- 8008a82: b007 add sp, #28
- 8008a84: bdf0 pop {r4, r5, r6, r7, pc}
- 8008a86: 429c cmp r4, r3
- 8008a88: ee70 7a07 vadd.f32 s15, s0, s14
- 8008a8c: bf09 itett eq
- 8008a8e: ed9f 7a70 vldreq s14, [pc, #448] ; 8008c50 <__ieee754_rem_pio2f+0x230>
- 8008a92: ed9f 7a70 vldrne s14, [pc, #448] ; 8008c54 <__ieee754_rem_pio2f+0x234>
- 8008a96: ee77 7a87 vaddeq.f32 s15, s15, s14
- 8008a9a: ed9f 7a6f vldreq s14, [pc, #444] ; 8008c58 <__ieee754_rem_pio2f+0x238>
- 8008a9e: ee77 6a87 vadd.f32 s13, s15, s14
- 8008aa2: ee77 7ae6 vsub.f32 s15, s15, s13
- 8008aa6: edc0 6a00 vstr s13, [r0]
- 8008aaa: ee77 7a87 vadd.f32 s15, s15, s14
- 8008aae: edc0 7a01 vstr s15, [r0, #4]
- 8008ab2: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8008ab6: e7e4 b.n 8008a82 <__ieee754_rem_pio2f+0x62>
- 8008ab8: 4b68 ldr r3, [pc, #416] ; (8008c5c <__ieee754_rem_pio2f+0x23c>)
- 8008aba: 429c cmp r4, r3
- 8008abc: dc71 bgt.n 8008ba2 <__ieee754_rem_pio2f+0x182>
- 8008abe: f001 f865 bl 8009b8c <fabsf>
- 8008ac2: ed9f 7a67 vldr s14, [pc, #412] ; 8008c60 <__ieee754_rem_pio2f+0x240>
- 8008ac6: eef6 7a00 vmov.f32 s15, #96 ; 0x3f000000 0.5
- 8008aca: eee0 7a07 vfma.f32 s15, s0, s14
- 8008ace: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8008ad2: eeb8 6ae7 vcvt.f32.s32 s12, s15
- 8008ad6: ee17 0a90 vmov r0, s15
- 8008ada: eddf 7a5b vldr s15, [pc, #364] ; 8008c48 <__ieee754_rem_pio2f+0x228>
- 8008ade: eeb1 7a46 vneg.f32 s14, s12
- 8008ae2: eea7 0a27 vfma.f32 s0, s14, s15
- 8008ae6: 281f cmp r0, #31
- 8008ae8: eddf 7a5a vldr s15, [pc, #360] ; 8008c54 <__ieee754_rem_pio2f+0x234>
- 8008aec: ee66 7a27 vmul.f32 s15, s12, s15
- 8008af0: ee70 6a67 vsub.f32 s13, s0, s15
- 8008af4: ee16 3a90 vmov r3, s13
- 8008af8: dc1c bgt.n 8008b34 <__ieee754_rem_pio2f+0x114>
- 8008afa: 1e47 subs r7, r0, #1
- 8008afc: 4959 ldr r1, [pc, #356] ; (8008c64 <__ieee754_rem_pio2f+0x244>)
- 8008afe: f851 1027 ldr.w r1, [r1, r7, lsl #2]
- 8008b02: f024 02ff bic.w r2, r4, #255 ; 0xff
- 8008b06: 428a cmp r2, r1
- 8008b08: d014 beq.n 8008b34 <__ieee754_rem_pio2f+0x114>
- 8008b0a: 602b str r3, [r5, #0]
- 8008b0c: ed95 7a00 vldr s14, [r5]
- 8008b10: ee30 0a47 vsub.f32 s0, s0, s14
- 8008b14: 2e00 cmp r6, #0
- 8008b16: ee30 0a67 vsub.f32 s0, s0, s15
- 8008b1a: ed85 0a01 vstr s0, [r5, #4]
- 8008b1e: dab0 bge.n 8008a82 <__ieee754_rem_pio2f+0x62>
- 8008b20: eeb1 7a47 vneg.f32 s14, s14
- 8008b24: eeb1 0a40 vneg.f32 s0, s0
- 8008b28: ed85 7a00 vstr s14, [r5]
- 8008b2c: ed85 0a01 vstr s0, [r5, #4]
- 8008b30: 4240 negs r0, r0
- 8008b32: e7a6 b.n 8008a82 <__ieee754_rem_pio2f+0x62>
- 8008b34: 15e4 asrs r4, r4, #23
- 8008b36: f3c3 52c7 ubfx r2, r3, #23, #8
- 8008b3a: 1aa2 subs r2, r4, r2
- 8008b3c: 2a08 cmp r2, #8
- 8008b3e: dde4 ble.n 8008b0a <__ieee754_rem_pio2f+0xea>
- 8008b40: eddf 7a43 vldr s15, [pc, #268] ; 8008c50 <__ieee754_rem_pio2f+0x230>
- 8008b44: eef0 6a40 vmov.f32 s13, s0
- 8008b48: eee7 6a27 vfma.f32 s13, s14, s15
- 8008b4c: ee30 0a66 vsub.f32 s0, s0, s13
- 8008b50: eea7 0a27 vfma.f32 s0, s14, s15
- 8008b54: eddf 7a40 vldr s15, [pc, #256] ; 8008c58 <__ieee754_rem_pio2f+0x238>
- 8008b58: ee96 0a27 vfnms.f32 s0, s12, s15
- 8008b5c: ee76 5ac0 vsub.f32 s11, s13, s0
- 8008b60: eef0 7a40 vmov.f32 s15, s0
- 8008b64: ee15 3a90 vmov r3, s11
- 8008b68: f3c3 52c7 ubfx r2, r3, #23, #8
- 8008b6c: 1aa4 subs r4, r4, r2
- 8008b6e: 2c19 cmp r4, #25
- 8008b70: dc04 bgt.n 8008b7c <__ieee754_rem_pio2f+0x15c>
- 8008b72: edc5 5a00 vstr s11, [r5]
- 8008b76: eeb0 0a66 vmov.f32 s0, s13
- 8008b7a: e7c7 b.n 8008b0c <__ieee754_rem_pio2f+0xec>
- 8008b7c: eddf 5a3a vldr s11, [pc, #232] ; 8008c68 <__ieee754_rem_pio2f+0x248>
- 8008b80: eeb0 0a66 vmov.f32 s0, s13
- 8008b84: eea7 0a25 vfma.f32 s0, s14, s11
- 8008b88: ee76 7ac0 vsub.f32 s15, s13, s0
- 8008b8c: eee7 7a25 vfma.f32 s15, s14, s11
- 8008b90: ed9f 7a36 vldr s14, [pc, #216] ; 8008c6c <__ieee754_rem_pio2f+0x24c>
- 8008b94: eed6 7a07 vfnms.f32 s15, s12, s14
- 8008b98: ee30 7a67 vsub.f32 s14, s0, s15
- 8008b9c: ed85 7a00 vstr s14, [r5]
- 8008ba0: e7b4 b.n 8008b0c <__ieee754_rem_pio2f+0xec>
- 8008ba2: f1b4 4fff cmp.w r4, #2139095040 ; 0x7f800000
- 8008ba6: db06 blt.n 8008bb6 <__ieee754_rem_pio2f+0x196>
- 8008ba8: ee70 7a40 vsub.f32 s15, s0, s0
- 8008bac: edc0 7a01 vstr s15, [r0, #4]
- 8008bb0: edc0 7a00 vstr s15, [r0]
- 8008bb4: e742 b.n 8008a3c <__ieee754_rem_pio2f+0x1c>
- 8008bb6: 15e2 asrs r2, r4, #23
- 8008bb8: 3a86 subs r2, #134 ; 0x86
- 8008bba: eba4 53c2 sub.w r3, r4, r2, lsl #23
- 8008bbe: ee07 3a90 vmov s15, r3
- 8008bc2: eebd 7ae7 vcvt.s32.f32 s14, s15
- 8008bc6: eddf 6a2a vldr s13, [pc, #168] ; 8008c70 <__ieee754_rem_pio2f+0x250>
- 8008bca: eeb8 7ac7 vcvt.f32.s32 s14, s14
- 8008bce: ee77 7ac7 vsub.f32 s15, s15, s14
- 8008bd2: ed8d 7a03 vstr s14, [sp, #12]
- 8008bd6: ee67 7aa6 vmul.f32 s15, s15, s13
- 8008bda: eebd 7ae7 vcvt.s32.f32 s14, s15
- 8008bde: eeb8 7ac7 vcvt.f32.s32 s14, s14
- 8008be2: ee77 7ac7 vsub.f32 s15, s15, s14
- 8008be6: ed8d 7a04 vstr s14, [sp, #16]
- 8008bea: ee67 7aa6 vmul.f32 s15, s15, s13
- 8008bee: eef5 7a40 vcmp.f32 s15, #0.0
- 8008bf2: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8008bf6: edcd 7a05 vstr s15, [sp, #20]
- 8008bfa: d11e bne.n 8008c3a <__ieee754_rem_pio2f+0x21a>
- 8008bfc: eeb5 7a40 vcmp.f32 s14, #0.0
- 8008c00: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8008c04: bf0c ite eq
- 8008c06: 2301 moveq r3, #1
- 8008c08: 2302 movne r3, #2
- 8008c0a: 491a ldr r1, [pc, #104] ; (8008c74 <__ieee754_rem_pio2f+0x254>)
- 8008c0c: 9101 str r1, [sp, #4]
- 8008c0e: 2102 movs r1, #2
- 8008c10: 9100 str r1, [sp, #0]
- 8008c12: a803 add r0, sp, #12
- 8008c14: 4629 mov r1, r5
- 8008c16: f000 fbed bl 80093f4 <__kernel_rem_pio2f>
- 8008c1a: 2e00 cmp r6, #0
- 8008c1c: f6bf af31 bge.w 8008a82 <__ieee754_rem_pio2f+0x62>
- 8008c20: edd5 7a00 vldr s15, [r5]
- 8008c24: eef1 7a67 vneg.f32 s15, s15
- 8008c28: edc5 7a00 vstr s15, [r5]
- 8008c2c: edd5 7a01 vldr s15, [r5, #4]
- 8008c30: eef1 7a67 vneg.f32 s15, s15
- 8008c34: edc5 7a01 vstr s15, [r5, #4]
- 8008c38: e77a b.n 8008b30 <__ieee754_rem_pio2f+0x110>
- 8008c3a: 2303 movs r3, #3
- 8008c3c: e7e5 b.n 8008c0a <__ieee754_rem_pio2f+0x1ea>
- 8008c3e: bf00 nop
- 8008c40: 3f490fd8 .word 0x3f490fd8
- 8008c44: 4016cbe3 .word 0x4016cbe3
- 8008c48: 3fc90f80 .word 0x3fc90f80
- 8008c4c: 3fc90fd0 .word 0x3fc90fd0
- 8008c50: 37354400 .word 0x37354400
- 8008c54: 37354443 .word 0x37354443
- 8008c58: 2e85a308 .word 0x2e85a308
- 8008c5c: 43490f80 .word 0x43490f80
- 8008c60: 3f22f984 .word 0x3f22f984
- 8008c64: 0800a64c .word 0x0800a64c
- 8008c68: 2e85a300 .word 0x2e85a300
- 8008c6c: 248d3132 .word 0x248d3132
- 8008c70: 43800000 .word 0x43800000
- 8008c74: 0800a6cc .word 0x0800a6cc
-
-08008c78 <__kernel_cos>:
- 8008c78: ee10 1a90 vmov r1, s1
- 8008c7c: eeb7 7b00 vmov.f64 d7, #112 ; 0x3f800000 1.0
- 8008c80: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
- 8008c84: f1b1 5f79 cmp.w r1, #1044381696 ; 0x3e400000
- 8008c88: da05 bge.n 8008c96 <__kernel_cos+0x1e>
- 8008c8a: eefd 6bc0 vcvt.s32.f64 s13, d0
- 8008c8e: ee16 3a90 vmov r3, s13
- 8008c92: 2b00 cmp r3, #0
- 8008c94: d03d beq.n 8008d12 <__kernel_cos+0x9a>
- 8008c96: ee20 4b00 vmul.f64 d4, d0, d0
- 8008c9a: eeb6 6b00 vmov.f64 d6, #96 ; 0x3f000000 0.5
- 8008c9e: ed9f 3b1e vldr d3, [pc, #120] ; 8008d18 <__kernel_cos+0xa0>
- 8008ca2: ee21 1b40 vnmul.f64 d1, d1, d0
- 8008ca6: ee24 6b06 vmul.f64 d6, d4, d6
- 8008caa: ed9f 5b1d vldr d5, [pc, #116] ; 8008d20 <__kernel_cos+0xa8>
- 8008cae: eea4 5b03 vfma.f64 d5, d4, d3
- 8008cb2: ed9f 3b1d vldr d3, [pc, #116] ; 8008d28 <__kernel_cos+0xb0>
- 8008cb6: eea5 3b04 vfma.f64 d3, d5, d4
- 8008cba: ed9f 5b1d vldr d5, [pc, #116] ; 8008d30 <__kernel_cos+0xb8>
- 8008cbe: eea3 5b04 vfma.f64 d5, d3, d4
- 8008cc2: ed9f 3b1d vldr d3, [pc, #116] ; 8008d38 <__kernel_cos+0xc0>
- 8008cc6: 4b20 ldr r3, [pc, #128] ; (8008d48 <__kernel_cos+0xd0>)
- 8008cc8: eea5 3b04 vfma.f64 d3, d5, d4
- 8008ccc: ed9f 5b1c vldr d5, [pc, #112] ; 8008d40 <__kernel_cos+0xc8>
- 8008cd0: 4299 cmp r1, r3
- 8008cd2: eea3 5b04 vfma.f64 d5, d3, d4
- 8008cd6: ee25 5b04 vmul.f64 d5, d5, d4
- 8008cda: eea4 1b05 vfma.f64 d1, d4, d5
- 8008cde: dc04 bgt.n 8008cea <__kernel_cos+0x72>
- 8008ce0: ee36 6b41 vsub.f64 d6, d6, d1
- 8008ce4: ee37 0b46 vsub.f64 d0, d7, d6
- 8008ce8: 4770 bx lr
- 8008cea: 4b18 ldr r3, [pc, #96] ; (8008d4c <__kernel_cos+0xd4>)
- 8008cec: 4299 cmp r1, r3
- 8008cee: dc0d bgt.n 8008d0c <__kernel_cos+0x94>
- 8008cf0: 2200 movs r2, #0
- 8008cf2: f5a1 1300 sub.w r3, r1, #2097152 ; 0x200000
- 8008cf6: ec43 2b15 vmov d5, r2, r3
- 8008cfa: ee37 0b45 vsub.f64 d0, d7, d5
- 8008cfe: ee36 6b45 vsub.f64 d6, d6, d5
- 8008d02: ee36 6b41 vsub.f64 d6, d6, d1
- 8008d06: ee30 0b46 vsub.f64 d0, d0, d6
- 8008d0a: 4770 bx lr
- 8008d0c: eeb5 5b02 vmov.f64 d5, #82 ; 0x3e900000 0.2812500
- 8008d10: e7f3 b.n 8008cfa <__kernel_cos+0x82>
- 8008d12: eeb0 0b47 vmov.f64 d0, d7
- 8008d16: 4770 bx lr
- 8008d18: be8838d4 .word 0xbe8838d4
- 8008d1c: bda8fae9 .word 0xbda8fae9
- 8008d20: bdb4b1c4 .word 0xbdb4b1c4
- 8008d24: 3e21ee9e .word 0x3e21ee9e
- 8008d28: 809c52ad .word 0x809c52ad
- 8008d2c: be927e4f .word 0xbe927e4f
- 8008d30: 19cb1590 .word 0x19cb1590
- 8008d34: 3efa01a0 .word 0x3efa01a0
- 8008d38: 16c15177 .word 0x16c15177
- 8008d3c: bf56c16c .word 0xbf56c16c
- 8008d40: 5555554c .word 0x5555554c
- 8008d44: 3fa55555 .word 0x3fa55555
- 8008d48: 3fd33332 .word 0x3fd33332
- 8008d4c: 3fe90000 .word 0x3fe90000
-
-08008d50 <__kernel_rem_pio2>:
- 8008d50: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 8008d54: ed2d 8b06 vpush {d8-d10}
- 8008d58: f5ad 7d13 sub.w sp, sp, #588 ; 0x24c
- 8008d5c: 469b mov fp, r3
- 8008d5e: 460e mov r6, r1
- 8008d60: 4bc7 ldr r3, [pc, #796] ; (8009080 <__kernel_rem_pio2+0x330>)
- 8008d62: 99a2 ldr r1, [sp, #648] ; 0x288
- 8008d64: 9002 str r0, [sp, #8]
- 8008d66: f853 9021 ldr.w r9, [r3, r1, lsl #2]
- 8008d6a: 98a3 ldr r0, [sp, #652] ; 0x28c
- 8008d6c: 1ed1 subs r1, r2, #3
- 8008d6e: 2318 movs r3, #24
- 8008d70: f06f 0417 mvn.w r4, #23
- 8008d74: fb91 f1f3 sdiv r1, r1, r3
- 8008d78: ea21 71e1 bic.w r1, r1, r1, asr #31
- 8008d7c: f10b 3aff add.w sl, fp, #4294967295 ; 0xffffffff
- 8008d80: fb01 4404 mla r4, r1, r4, r4
- 8008d84: ed9f 6bb8 vldr d6, [pc, #736] ; 8009068 <__kernel_rem_pio2+0x318>
- 8008d88: 4414 add r4, r2
- 8008d8a: eba1 050a sub.w r5, r1, sl
- 8008d8e: aa1a add r2, sp, #104 ; 0x68
- 8008d90: eb09 070a add.w r7, r9, sl
- 8008d94: eb00 0c85 add.w ip, r0, r5, lsl #2
- 8008d98: 4696 mov lr, r2
- 8008d9a: 2300 movs r3, #0
- 8008d9c: 42bb cmp r3, r7
- 8008d9e: dd0f ble.n 8008dc0 <__kernel_rem_pio2+0x70>
- 8008da0: af6a add r7, sp, #424 ; 0x1a8
- 8008da2: 2200 movs r2, #0
- 8008da4: 454a cmp r2, r9
- 8008da6: dc28 bgt.n 8008dfa <__kernel_rem_pio2+0xaa>
- 8008da8: f10d 0c68 add.w ip, sp, #104 ; 0x68
- 8008dac: eb0b 0302 add.w r3, fp, r2
- 8008db0: eb0c 03c3 add.w r3, ip, r3, lsl #3
- 8008db4: 9d02 ldr r5, [sp, #8]
- 8008db6: ed9f 7bac vldr d7, [pc, #688] ; 8009068 <__kernel_rem_pio2+0x318>
- 8008dba: f04f 0c00 mov.w ip, #0
- 8008dbe: e016 b.n 8008dee <__kernel_rem_pio2+0x9e>
- 8008dc0: 42dd cmn r5, r3
- 8008dc2: d409 bmi.n 8008dd8 <__kernel_rem_pio2+0x88>
- 8008dc4: f85c 2023 ldr.w r2, [ip, r3, lsl #2]
- 8008dc8: ee07 2a90 vmov s15, r2
- 8008dcc: eeb8 7be7 vcvt.f64.s32 d7, s15
- 8008dd0: ecae 7b02 vstmia lr!, {d7}
- 8008dd4: 3301 adds r3, #1
- 8008dd6: e7e1 b.n 8008d9c <__kernel_rem_pio2+0x4c>
- 8008dd8: eeb0 7b46 vmov.f64 d7, d6
- 8008ddc: e7f8 b.n 8008dd0 <__kernel_rem_pio2+0x80>
- 8008dde: ecb5 5b02 vldmia r5!, {d5}
- 8008de2: ed33 6b02 vldmdb r3!, {d6}
- 8008de6: f10c 0c01 add.w ip, ip, #1
- 8008dea: eea5 7b06 vfma.f64 d7, d5, d6
- 8008dee: 45d4 cmp ip, sl
- 8008df0: ddf5 ble.n 8008dde <__kernel_rem_pio2+0x8e>
- 8008df2: eca7 7b02 vstmia r7!, {d7}
- 8008df6: 3201 adds r2, #1
- 8008df8: e7d4 b.n 8008da4 <__kernel_rem_pio2+0x54>
- 8008dfa: ab06 add r3, sp, #24
- 8008dfc: eb03 0389 add.w r3, r3, r9, lsl #2
- 8008e00: ed9f 9b9b vldr d9, [pc, #620] ; 8009070 <__kernel_rem_pio2+0x320>
- 8008e04: ed9f ab9c vldr d10, [pc, #624] ; 8009078 <__kernel_rem_pio2+0x328>
- 8008e08: 9304 str r3, [sp, #16]
- 8008e0a: eb00 0381 add.w r3, r0, r1, lsl #2
- 8008e0e: 9303 str r3, [sp, #12]
- 8008e10: 464d mov r5, r9
- 8008e12: ab92 add r3, sp, #584 ; 0x248
- 8008e14: f105 5700 add.w r7, r5, #536870912 ; 0x20000000
- 8008e18: eb03 03c5 add.w r3, r3, r5, lsl #3
- 8008e1c: 3f01 subs r7, #1
- 8008e1e: ed13 0b28 vldr d0, [r3, #-160] ; 0xffffff60
- 8008e22: 00ff lsls r7, r7, #3
- 8008e24: ab92 add r3, sp, #584 ; 0x248
- 8008e26: 19da adds r2, r3, r7
- 8008e28: 3a98 subs r2, #152 ; 0x98
- 8008e2a: 2300 movs r3, #0
- 8008e2c: 1ae9 subs r1, r5, r3
- 8008e2e: 2900 cmp r1, #0
- 8008e30: dc4e bgt.n 8008ed0 <__kernel_rem_pio2+0x180>
- 8008e32: 4620 mov r0, r4
- 8008e34: f000 fe2c bl 8009a90 <scalbn>
- 8008e38: eeb0 8b40 vmov.f64 d8, d0
- 8008e3c: eeb4 0b00 vmov.f64 d0, #64 ; 0x3e000000 0.125
- 8008e40: ee28 0b00 vmul.f64 d0, d8, d0
- 8008e44: f000 fdac bl 80099a0 <floor>
- 8008e48: eeb2 7b00 vmov.f64 d7, #32 ; 0x41000000 8.0
- 8008e4c: eea0 8b47 vfms.f64 d8, d0, d7
- 8008e50: eefd 7bc8 vcvt.s32.f64 s15, d8
- 8008e54: 2c00 cmp r4, #0
- 8008e56: edcd 7a01 vstr s15, [sp, #4]
- 8008e5a: eeb8 7be7 vcvt.f64.s32 d7, s15
- 8008e5e: ee38 8b47 vsub.f64 d8, d8, d7
- 8008e62: dd4a ble.n 8008efa <__kernel_rem_pio2+0x1aa>
- 8008e64: 1e69 subs r1, r5, #1
- 8008e66: ab06 add r3, sp, #24
- 8008e68: f1c4 0018 rsb r0, r4, #24
- 8008e6c: f853 c021 ldr.w ip, [r3, r1, lsl #2]
- 8008e70: 9a01 ldr r2, [sp, #4]
- 8008e72: fa4c f300 asr.w r3, ip, r0
- 8008e76: 441a add r2, r3
- 8008e78: 4083 lsls r3, r0
- 8008e7a: 9201 str r2, [sp, #4]
- 8008e7c: ebac 0203 sub.w r2, ip, r3
- 8008e80: ab06 add r3, sp, #24
- 8008e82: f843 2021 str.w r2, [r3, r1, lsl #2]
- 8008e86: f1c4 0317 rsb r3, r4, #23
- 8008e8a: fa42 f803 asr.w r8, r2, r3
- 8008e8e: f1b8 0f00 cmp.w r8, #0
- 8008e92: dd43 ble.n 8008f1c <__kernel_rem_pio2+0x1cc>
- 8008e94: 9b01 ldr r3, [sp, #4]
- 8008e96: 2000 movs r0, #0
- 8008e98: 3301 adds r3, #1
- 8008e9a: 9301 str r3, [sp, #4]
- 8008e9c: 4601 mov r1, r0
- 8008e9e: f06f 4c7f mvn.w ip, #4278190080 ; 0xff000000
- 8008ea2: 4285 cmp r5, r0
- 8008ea4: dc6e bgt.n 8008f84 <__kernel_rem_pio2+0x234>
- 8008ea6: 2c00 cmp r4, #0
- 8008ea8: dd04 ble.n 8008eb4 <__kernel_rem_pio2+0x164>
- 8008eaa: 2c01 cmp r4, #1
- 8008eac: d07f beq.n 8008fae <__kernel_rem_pio2+0x25e>
- 8008eae: 2c02 cmp r4, #2
- 8008eb0: f000 8087 beq.w 8008fc2 <__kernel_rem_pio2+0x272>
- 8008eb4: f1b8 0f02 cmp.w r8, #2
- 8008eb8: d130 bne.n 8008f1c <__kernel_rem_pio2+0x1cc>
- 8008eba: eeb7 0b00 vmov.f64 d0, #112 ; 0x3f800000 1.0
- 8008ebe: ee30 8b48 vsub.f64 d8, d0, d8
- 8008ec2: b359 cbz r1, 8008f1c <__kernel_rem_pio2+0x1cc>
- 8008ec4: 4620 mov r0, r4
- 8008ec6: f000 fde3 bl 8009a90 <scalbn>
- 8008eca: ee38 8b40 vsub.f64 d8, d8, d0
- 8008ece: e025 b.n 8008f1c <__kernel_rem_pio2+0x1cc>
- 8008ed0: ee20 7b09 vmul.f64 d7, d0, d9
- 8008ed4: eebd 7bc7 vcvt.s32.f64 s14, d7
- 8008ed8: a806 add r0, sp, #24
- 8008eda: eeb8 7bc7 vcvt.f64.s32 d7, s14
- 8008ede: eea7 0b4a vfms.f64 d0, d7, d10
- 8008ee2: eebd 0bc0 vcvt.s32.f64 s0, d0
- 8008ee6: ee10 1a10 vmov r1, s0
- 8008eea: ed32 0b02 vldmdb r2!, {d0}
- 8008eee: f840 1023 str.w r1, [r0, r3, lsl #2]
- 8008ef2: ee37 0b00 vadd.f64 d0, d7, d0
- 8008ef6: 3301 adds r3, #1
- 8008ef8: e798 b.n 8008e2c <__kernel_rem_pio2+0xdc>
- 8008efa: d106 bne.n 8008f0a <__kernel_rem_pio2+0x1ba>
- 8008efc: 1e6b subs r3, r5, #1
- 8008efe: aa06 add r2, sp, #24
- 8008f00: f852 2023 ldr.w r2, [r2, r3, lsl #2]
- 8008f04: ea4f 58e2 mov.w r8, r2, asr #23
- 8008f08: e7c1 b.n 8008e8e <__kernel_rem_pio2+0x13e>
- 8008f0a: eeb6 7b00 vmov.f64 d7, #96 ; 0x3f000000 0.5
- 8008f0e: eeb4 8bc7 vcmpe.f64 d8, d7
- 8008f12: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8008f16: da32 bge.n 8008f7e <__kernel_rem_pio2+0x22e>
- 8008f18: f04f 0800 mov.w r8, #0
- 8008f1c: eeb5 8b40 vcmp.f64 d8, #0.0
- 8008f20: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8008f24: f040 80b0 bne.w 8009088 <__kernel_rem_pio2+0x338>
- 8008f28: 1e6b subs r3, r5, #1
- 8008f2a: 4618 mov r0, r3
- 8008f2c: 2200 movs r2, #0
- 8008f2e: 4548 cmp r0, r9
- 8008f30: da4e bge.n 8008fd0 <__kernel_rem_pio2+0x280>
- 8008f32: 2a00 cmp r2, #0
- 8008f34: f000 8088 beq.w 8009048 <__kernel_rem_pio2+0x2f8>
- 8008f38: aa06 add r2, sp, #24
- 8008f3a: 3c18 subs r4, #24
- 8008f3c: f852 1023 ldr.w r1, [r2, r3, lsl #2]
- 8008f40: 2900 cmp r1, #0
- 8008f42: f000 808e beq.w 8009062 <__kernel_rem_pio2+0x312>
- 8008f46: eeb7 0b00 vmov.f64 d0, #112 ; 0x3f800000 1.0
- 8008f4a: 4620 mov r0, r4
- 8008f4c: 9302 str r3, [sp, #8]
- 8008f4e: f000 fd9f bl 8009a90 <scalbn>
- 8008f52: 9b02 ldr r3, [sp, #8]
- 8008f54: aa6a add r2, sp, #424 ; 0x1a8
- 8008f56: 00d9 lsls r1, r3, #3
- 8008f58: ed9f 6b45 vldr d6, [pc, #276] ; 8009070 <__kernel_rem_pio2+0x320>
- 8008f5c: 1850 adds r0, r2, r1
- 8008f5e: f100 0508 add.w r5, r0, #8
- 8008f62: 461c mov r4, r3
- 8008f64: 2c00 cmp r4, #0
- 8008f66: f280 80bd bge.w 80090e4 <__kernel_rem_pio2+0x394>
- 8008f6a: 2500 movs r5, #0
- 8008f6c: 1b5c subs r4, r3, r5
- 8008f6e: 2c00 cmp r4, #0
- 8008f70: f2c0 80dd blt.w 800912e <__kernel_rem_pio2+0x3de>
- 8008f74: 4f43 ldr r7, [pc, #268] ; (8009084 <__kernel_rem_pio2+0x334>)
- 8008f76: ed9f 7b3c vldr d7, [pc, #240] ; 8009068 <__kernel_rem_pio2+0x318>
- 8008f7a: 2400 movs r4, #0
- 8008f7c: e0cb b.n 8009116 <__kernel_rem_pio2+0x3c6>
- 8008f7e: f04f 0802 mov.w r8, #2
- 8008f82: e787 b.n 8008e94 <__kernel_rem_pio2+0x144>
- 8008f84: ab06 add r3, sp, #24
- 8008f86: f853 3020 ldr.w r3, [r3, r0, lsl #2]
- 8008f8a: b949 cbnz r1, 8008fa0 <__kernel_rem_pio2+0x250>
- 8008f8c: b12b cbz r3, 8008f9a <__kernel_rem_pio2+0x24a>
- 8008f8e: aa06 add r2, sp, #24
- 8008f90: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000
- 8008f94: f842 3020 str.w r3, [r2, r0, lsl #2]
- 8008f98: 2301 movs r3, #1
- 8008f9a: 3001 adds r0, #1
- 8008f9c: 4619 mov r1, r3
- 8008f9e: e780 b.n 8008ea2 <__kernel_rem_pio2+0x152>
- 8008fa0: aa06 add r2, sp, #24
- 8008fa2: ebac 0303 sub.w r3, ip, r3
- 8008fa6: f842 3020 str.w r3, [r2, r0, lsl #2]
- 8008faa: 460b mov r3, r1
- 8008fac: e7f5 b.n 8008f9a <__kernel_rem_pio2+0x24a>
- 8008fae: 1e68 subs r0, r5, #1
- 8008fb0: ab06 add r3, sp, #24
- 8008fb2: f853 3020 ldr.w r3, [r3, r0, lsl #2]
- 8008fb6: f3c3 0316 ubfx r3, r3, #0, #23
- 8008fba: aa06 add r2, sp, #24
- 8008fbc: f842 3020 str.w r3, [r2, r0, lsl #2]
- 8008fc0: e778 b.n 8008eb4 <__kernel_rem_pio2+0x164>
- 8008fc2: 1e68 subs r0, r5, #1
- 8008fc4: ab06 add r3, sp, #24
- 8008fc6: f853 3020 ldr.w r3, [r3, r0, lsl #2]
- 8008fca: f3c3 0315 ubfx r3, r3, #0, #22
- 8008fce: e7f4 b.n 8008fba <__kernel_rem_pio2+0x26a>
- 8008fd0: a906 add r1, sp, #24
- 8008fd2: f851 1020 ldr.w r1, [r1, r0, lsl #2]
- 8008fd6: 3801 subs r0, #1
- 8008fd8: 430a orrs r2, r1
- 8008fda: e7a8 b.n 8008f2e <__kernel_rem_pio2+0x1de>
- 8008fdc: f10c 0c01 add.w ip, ip, #1
- 8008fe0: f853 2d04 ldr.w r2, [r3, #-4]!
- 8008fe4: 2a00 cmp r2, #0
- 8008fe6: d0f9 beq.n 8008fdc <__kernel_rem_pio2+0x28c>
- 8008fe8: eb0b 0305 add.w r3, fp, r5
- 8008fec: aa1a add r2, sp, #104 ; 0x68
- 8008fee: 00db lsls r3, r3, #3
- 8008ff0: 1898 adds r0, r3, r2
- 8008ff2: 3008 adds r0, #8
- 8008ff4: 1c69 adds r1, r5, #1
- 8008ff6: 3708 adds r7, #8
- 8008ff8: 2200 movs r2, #0
- 8008ffa: 4465 add r5, ip
- 8008ffc: 9005 str r0, [sp, #20]
- 8008ffe: 428d cmp r5, r1
- 8009000: f6ff af07 blt.w 8008e12 <__kernel_rem_pio2+0xc2>
- 8009004: a81a add r0, sp, #104 ; 0x68
- 8009006: eb02 0c03 add.w ip, r2, r3
- 800900a: 4484 add ip, r0
- 800900c: 9803 ldr r0, [sp, #12]
- 800900e: f8dd e008 ldr.w lr, [sp, #8]
- 8009012: f850 0021 ldr.w r0, [r0, r1, lsl #2]
- 8009016: 9001 str r0, [sp, #4]
- 8009018: ee07 0a90 vmov s15, r0
- 800901c: eeb8 7be7 vcvt.f64.s32 d7, s15
- 8009020: 9805 ldr r0, [sp, #20]
- 8009022: ed8c 7b00 vstr d7, [ip]
- 8009026: ed9f 7b10 vldr d7, [pc, #64] ; 8009068 <__kernel_rem_pio2+0x318>
- 800902a: eb00 0802 add.w r8, r0, r2
- 800902e: f04f 0c00 mov.w ip, #0
- 8009032: 45d4 cmp ip, sl
- 8009034: dd0c ble.n 8009050 <__kernel_rem_pio2+0x300>
- 8009036: eb02 0c07 add.w ip, r2, r7
- 800903a: a86a add r0, sp, #424 ; 0x1a8
- 800903c: 4484 add ip, r0
- 800903e: ed8c 7b02 vstr d7, [ip, #8]
- 8009042: 3101 adds r1, #1
- 8009044: 3208 adds r2, #8
- 8009046: e7da b.n 8008ffe <__kernel_rem_pio2+0x2ae>
- 8009048: 9b04 ldr r3, [sp, #16]
- 800904a: f04f 0c01 mov.w ip, #1
- 800904e: e7c7 b.n 8008fe0 <__kernel_rem_pio2+0x290>
- 8009050: ecbe 5b02 vldmia lr!, {d5}
- 8009054: ed38 6b02 vldmdb r8!, {d6}
- 8009058: f10c 0c01 add.w ip, ip, #1
- 800905c: eea5 7b06 vfma.f64 d7, d5, d6
- 8009060: e7e7 b.n 8009032 <__kernel_rem_pio2+0x2e2>
- 8009062: 3b01 subs r3, #1
- 8009064: e768 b.n 8008f38 <__kernel_rem_pio2+0x1e8>
- 8009066: bf00 nop
- ...
- 8009074: 3e700000 .word 0x3e700000
- 8009078: 00000000 .word 0x00000000
- 800907c: 41700000 .word 0x41700000
- 8009080: 0800aa28 .word 0x0800aa28
- 8009084: 0800a9e8 .word 0x0800a9e8
- 8009088: 4260 negs r0, r4
- 800908a: eeb0 0b48 vmov.f64 d0, d8
- 800908e: f000 fcff bl 8009a90 <scalbn>
- 8009092: ed9f 6b77 vldr d6, [pc, #476] ; 8009270 <__kernel_rem_pio2+0x520>
- 8009096: eeb4 0bc6 vcmpe.f64 d0, d6
- 800909a: eef1 fa10 vmrs APSR_nzcv, fpscr
- 800909e: db18 blt.n 80090d2 <__kernel_rem_pio2+0x382>
- 80090a0: ed9f 7b75 vldr d7, [pc, #468] ; 8009278 <__kernel_rem_pio2+0x528>
- 80090a4: ee20 7b07 vmul.f64 d7, d0, d7
- 80090a8: eebd 7bc7 vcvt.s32.f64 s14, d7
- 80090ac: aa06 add r2, sp, #24
- 80090ae: eeb8 5bc7 vcvt.f64.s32 d5, s14
- 80090b2: eea5 0b46 vfms.f64 d0, d5, d6
- 80090b6: eebd 0bc0 vcvt.s32.f64 s0, d0
- 80090ba: a906 add r1, sp, #24
- 80090bc: ee10 3a10 vmov r3, s0
- 80090c0: f842 3025 str.w r3, [r2, r5, lsl #2]
- 80090c4: 1c6b adds r3, r5, #1
- 80090c6: ee17 2a10 vmov r2, s14
- 80090ca: 3418 adds r4, #24
- 80090cc: f841 2023 str.w r2, [r1, r3, lsl #2]
- 80090d0: e739 b.n 8008f46 <__kernel_rem_pio2+0x1f6>
- 80090d2: eebd 0bc0 vcvt.s32.f64 s0, d0
- 80090d6: aa06 add r2, sp, #24
- 80090d8: ee10 3a10 vmov r3, s0
- 80090dc: f842 3025 str.w r3, [r2, r5, lsl #2]
- 80090e0: 462b mov r3, r5
- 80090e2: e730 b.n 8008f46 <__kernel_rem_pio2+0x1f6>
- 80090e4: aa06 add r2, sp, #24
- 80090e6: f852 2024 ldr.w r2, [r2, r4, lsl #2]
- 80090ea: 9202 str r2, [sp, #8]
- 80090ec: ee07 2a90 vmov s15, r2
- 80090f0: 3c01 subs r4, #1
- 80090f2: eeb8 7be7 vcvt.f64.s32 d7, s15
- 80090f6: ee27 7b00 vmul.f64 d7, d7, d0
- 80090fa: ee20 0b06 vmul.f64 d0, d0, d6
- 80090fe: ed25 7b02 vstmdb r5!, {d7}
- 8009102: e72f b.n 8008f64 <__kernel_rem_pio2+0x214>
- 8009104: eb00 0cc4 add.w ip, r0, r4, lsl #3
- 8009108: ecb7 5b02 vldmia r7!, {d5}
- 800910c: ed9c 6b00 vldr d6, [ip]
- 8009110: 3401 adds r4, #1
- 8009112: eea5 7b06 vfma.f64 d7, d5, d6
- 8009116: 454c cmp r4, r9
- 8009118: dc01 bgt.n 800911e <__kernel_rem_pio2+0x3ce>
- 800911a: 42a5 cmp r5, r4
- 800911c: daf2 bge.n 8009104 <__kernel_rem_pio2+0x3b4>
- 800911e: aa42 add r2, sp, #264 ; 0x108
- 8009120: eb02 04c5 add.w r4, r2, r5, lsl #3
- 8009124: ed84 7b00 vstr d7, [r4]
- 8009128: 3501 adds r5, #1
- 800912a: 3808 subs r0, #8
- 800912c: e71e b.n 8008f6c <__kernel_rem_pio2+0x21c>
- 800912e: 9aa2 ldr r2, [sp, #648] ; 0x288
- 8009130: 2a03 cmp r2, #3
- 8009132: d84e bhi.n 80091d2 <__kernel_rem_pio2+0x482>
- 8009134: e8df f002 tbb [pc, r2]
- 8009138: 021f1f3e .word 0x021f1f3e
- 800913c: 3108 adds r1, #8
- 800913e: aa42 add r2, sp, #264 ; 0x108
- 8009140: 4411 add r1, r2
- 8009142: 4608 mov r0, r1
- 8009144: 461c mov r4, r3
- 8009146: 2c00 cmp r4, #0
- 8009148: dc61 bgt.n 800920e <__kernel_rem_pio2+0x4be>
- 800914a: 4608 mov r0, r1
- 800914c: 461c mov r4, r3
- 800914e: 2c01 cmp r4, #1
- 8009150: dc6d bgt.n 800922e <__kernel_rem_pio2+0x4de>
- 8009152: ed9f 7b4b vldr d7, [pc, #300] ; 8009280 <__kernel_rem_pio2+0x530>
- 8009156: 2b01 cmp r3, #1
- 8009158: dc79 bgt.n 800924e <__kernel_rem_pio2+0x4fe>
- 800915a: ed9d 5b42 vldr d5, [sp, #264] ; 0x108
- 800915e: ed9d 6b44 vldr d6, [sp, #272] ; 0x110
- 8009162: f1b8 0f00 cmp.w r8, #0
- 8009166: d178 bne.n 800925a <__kernel_rem_pio2+0x50a>
- 8009168: ed86 5b00 vstr d5, [r6]
- 800916c: ed86 6b02 vstr d6, [r6, #8]
- 8009170: ed86 7b04 vstr d7, [r6, #16]
- 8009174: e02d b.n 80091d2 <__kernel_rem_pio2+0x482>
- 8009176: ed9f 6b42 vldr d6, [pc, #264] ; 8009280 <__kernel_rem_pio2+0x530>
- 800917a: 3108 adds r1, #8
- 800917c: aa42 add r2, sp, #264 ; 0x108
- 800917e: 4411 add r1, r2
- 8009180: 4618 mov r0, r3
- 8009182: 2800 cmp r0, #0
- 8009184: da34 bge.n 80091f0 <__kernel_rem_pio2+0x4a0>
- 8009186: f1b8 0f00 cmp.w r8, #0
- 800918a: d037 beq.n 80091fc <__kernel_rem_pio2+0x4ac>
- 800918c: eeb1 7b46 vneg.f64 d7, d6
- 8009190: ed86 7b00 vstr d7, [r6]
- 8009194: ed9d 7b42 vldr d7, [sp, #264] ; 0x108
- 8009198: a844 add r0, sp, #272 ; 0x110
- 800919a: 2101 movs r1, #1
- 800919c: ee37 7b46 vsub.f64 d7, d7, d6
- 80091a0: 428b cmp r3, r1
- 80091a2: da2e bge.n 8009202 <__kernel_rem_pio2+0x4b2>
- 80091a4: f1b8 0f00 cmp.w r8, #0
- 80091a8: d001 beq.n 80091ae <__kernel_rem_pio2+0x45e>
- 80091aa: eeb1 7b47 vneg.f64 d7, d7
- 80091ae: ed86 7b02 vstr d7, [r6, #8]
- 80091b2: e00e b.n 80091d2 <__kernel_rem_pio2+0x482>
- 80091b4: aa92 add r2, sp, #584 ; 0x248
- 80091b6: ed9f 7b32 vldr d7, [pc, #200] ; 8009280 <__kernel_rem_pio2+0x530>
- 80091ba: 4411 add r1, r2
- 80091bc: f5a1 719c sub.w r1, r1, #312 ; 0x138
- 80091c0: 2b00 cmp r3, #0
- 80091c2: da0f bge.n 80091e4 <__kernel_rem_pio2+0x494>
- 80091c4: f1b8 0f00 cmp.w r8, #0
- 80091c8: d001 beq.n 80091ce <__kernel_rem_pio2+0x47e>
- 80091ca: eeb1 7b47 vneg.f64 d7, d7
- 80091ce: ed86 7b00 vstr d7, [r6]
- 80091d2: 9b01 ldr r3, [sp, #4]
- 80091d4: f003 0007 and.w r0, r3, #7
- 80091d8: f50d 7d13 add.w sp, sp, #588 ; 0x24c
- 80091dc: ecbd 8b06 vpop {d8-d10}
- 80091e0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 80091e4: ed31 6b02 vldmdb r1!, {d6}
- 80091e8: 3b01 subs r3, #1
- 80091ea: ee37 7b06 vadd.f64 d7, d7, d6
- 80091ee: e7e7 b.n 80091c0 <__kernel_rem_pio2+0x470>
- 80091f0: ed31 7b02 vldmdb r1!, {d7}
- 80091f4: 3801 subs r0, #1
- 80091f6: ee36 6b07 vadd.f64 d6, d6, d7
- 80091fa: e7c2 b.n 8009182 <__kernel_rem_pio2+0x432>
- 80091fc: eeb0 7b46 vmov.f64 d7, d6
- 8009200: e7c6 b.n 8009190 <__kernel_rem_pio2+0x440>
- 8009202: ecb0 6b02 vldmia r0!, {d6}
- 8009206: 3101 adds r1, #1
- 8009208: ee37 7b06 vadd.f64 d7, d7, d6
- 800920c: e7c8 b.n 80091a0 <__kernel_rem_pio2+0x450>
- 800920e: ed10 7b04 vldr d7, [r0, #-16]
- 8009212: ed30 5b02 vldmdb r0!, {d5}
- 8009216: 3c01 subs r4, #1
- 8009218: ee37 6b05 vadd.f64 d6, d7, d5
- 800921c: ee37 7b46 vsub.f64 d7, d7, d6
- 8009220: ed00 6b02 vstr d6, [r0, #-8]
- 8009224: ee37 7b05 vadd.f64 d7, d7, d5
- 8009228: ed80 7b00 vstr d7, [r0]
- 800922c: e78b b.n 8009146 <__kernel_rem_pio2+0x3f6>
- 800922e: ed10 7b04 vldr d7, [r0, #-16]
- 8009232: ed30 5b02 vldmdb r0!, {d5}
- 8009236: 3c01 subs r4, #1
- 8009238: ee37 6b05 vadd.f64 d6, d7, d5
- 800923c: ee37 7b46 vsub.f64 d7, d7, d6
- 8009240: ed00 6b02 vstr d6, [r0, #-8]
- 8009244: ee37 7b05 vadd.f64 d7, d7, d5
- 8009248: ed80 7b00 vstr d7, [r0]
- 800924c: e77f b.n 800914e <__kernel_rem_pio2+0x3fe>
- 800924e: ed31 6b02 vldmdb r1!, {d6}
- 8009252: 3b01 subs r3, #1
- 8009254: ee37 7b06 vadd.f64 d7, d7, d6
- 8009258: e77d b.n 8009156 <__kernel_rem_pio2+0x406>
- 800925a: eeb1 5b45 vneg.f64 d5, d5
- 800925e: eeb1 6b46 vneg.f64 d6, d6
- 8009262: ed86 5b00 vstr d5, [r6]
- 8009266: eeb1 7b47 vneg.f64 d7, d7
- 800926a: ed86 6b02 vstr d6, [r6, #8]
- 800926e: e77f b.n 8009170 <__kernel_rem_pio2+0x420>
- 8009270: 00000000 .word 0x00000000
- 8009274: 41700000 .word 0x41700000
- 8009278: 00000000 .word 0x00000000
- 800927c: 3e700000 .word 0x3e700000
- ...
-
-08009288 <__kernel_sin>:
- 8009288: ee10 3a90 vmov r3, s1
- 800928c: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 8009290: f1b3 5f79 cmp.w r3, #1044381696 ; 0x3e400000
- 8009294: da04 bge.n 80092a0 <__kernel_sin+0x18>
- 8009296: eefd 7bc0 vcvt.s32.f64 s15, d0
- 800929a: ee17 3a90 vmov r3, s15
- 800929e: b35b cbz r3, 80092f8 <__kernel_sin+0x70>
- 80092a0: ee20 6b00 vmul.f64 d6, d0, d0
- 80092a4: ee20 5b06 vmul.f64 d5, d0, d6
- 80092a8: ed9f 7b15 vldr d7, [pc, #84] ; 8009300 <__kernel_sin+0x78>
- 80092ac: ed9f 4b16 vldr d4, [pc, #88] ; 8009308 <__kernel_sin+0x80>
- 80092b0: eea6 4b07 vfma.f64 d4, d6, d7
- 80092b4: ed9f 7b16 vldr d7, [pc, #88] ; 8009310 <__kernel_sin+0x88>
- 80092b8: eea4 7b06 vfma.f64 d7, d4, d6
- 80092bc: ed9f 4b16 vldr d4, [pc, #88] ; 8009318 <__kernel_sin+0x90>
- 80092c0: eea7 4b06 vfma.f64 d4, d7, d6
- 80092c4: ed9f 7b16 vldr d7, [pc, #88] ; 8009320 <__kernel_sin+0x98>
- 80092c8: eea4 7b06 vfma.f64 d7, d4, d6
- 80092cc: b930 cbnz r0, 80092dc <__kernel_sin+0x54>
- 80092ce: ed9f 4b16 vldr d4, [pc, #88] ; 8009328 <__kernel_sin+0xa0>
- 80092d2: eea6 4b07 vfma.f64 d4, d6, d7
- 80092d6: eea4 0b05 vfma.f64 d0, d4, d5
- 80092da: 4770 bx lr
- 80092dc: ee27 7b45 vnmul.f64 d7, d7, d5
- 80092e0: eeb6 4b00 vmov.f64 d4, #96 ; 0x3f000000 0.5
- 80092e4: eea1 7b04 vfma.f64 d7, d1, d4
- 80092e8: ee97 1b06 vfnms.f64 d1, d7, d6
- 80092ec: ed9f 7b10 vldr d7, [pc, #64] ; 8009330 <__kernel_sin+0xa8>
- 80092f0: eea5 1b07 vfma.f64 d1, d5, d7
- 80092f4: ee30 0b41 vsub.f64 d0, d0, d1
- 80092f8: 4770 bx lr
- 80092fa: bf00 nop
- 80092fc: f3af 8000 nop.w
- 8009300: 5acfd57c .word 0x5acfd57c
- 8009304: 3de5d93a .word 0x3de5d93a
- 8009308: 8a2b9ceb .word 0x8a2b9ceb
- 800930c: be5ae5e6 .word 0xbe5ae5e6
- 8009310: 57b1fe7d .word 0x57b1fe7d
- 8009314: 3ec71de3 .word 0x3ec71de3
- 8009318: 19c161d5 .word 0x19c161d5
- 800931c: bf2a01a0 .word 0xbf2a01a0
- 8009320: 1110f8a6 .word 0x1110f8a6
- 8009324: 3f811111 .word 0x3f811111
- 8009328: 55555549 .word 0x55555549
- 800932c: bfc55555 .word 0xbfc55555
- 8009330: 55555549 .word 0x55555549
- 8009334: 3fc55555 .word 0x3fc55555
-
-08009338 <__kernel_cosf>:
- 8009338: ee10 3a10 vmov r3, s0
- 800933c: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 8009340: f1b3 5f48 cmp.w r3, #838860800 ; 0x32000000
- 8009344: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0
- 8009348: da05 bge.n 8009356 <__kernel_cosf+0x1e>
- 800934a: eefd 7ac0 vcvt.s32.f32 s15, s0
- 800934e: ee17 2a90 vmov r2, s15
- 8009352: 2a00 cmp r2, #0
- 8009354: d03b beq.n 80093ce <__kernel_cosf+0x96>
- 8009356: ee20 6a00 vmul.f32 s12, s0, s0
- 800935a: eeb6 7a00 vmov.f32 s14, #96 ; 0x3f000000 0.5
- 800935e: eddf 5a1d vldr s11, [pc, #116] ; 80093d4 <__kernel_cosf+0x9c>
- 8009362: 4a1d ldr r2, [pc, #116] ; (80093d8 <__kernel_cosf+0xa0>)
- 8009364: ee66 7a07 vmul.f32 s15, s12, s14
- 8009368: ed9f 7a1c vldr s14, [pc, #112] ; 80093dc <__kernel_cosf+0xa4>
- 800936c: eea6 7a25 vfma.f32 s14, s12, s11
- 8009370: 4293 cmp r3, r2
- 8009372: eddf 5a1b vldr s11, [pc, #108] ; 80093e0 <__kernel_cosf+0xa8>
- 8009376: eee7 5a06 vfma.f32 s11, s14, s12
- 800937a: ed9f 7a1a vldr s14, [pc, #104] ; 80093e4 <__kernel_cosf+0xac>
- 800937e: eea5 7a86 vfma.f32 s14, s11, s12
- 8009382: eddf 5a19 vldr s11, [pc, #100] ; 80093e8 <__kernel_cosf+0xb0>
- 8009386: eee7 5a06 vfma.f32 s11, s14, s12
- 800938a: ed9f 7a18 vldr s14, [pc, #96] ; 80093ec <__kernel_cosf+0xb4>
- 800938e: eea5 7a86 vfma.f32 s14, s11, s12
- 8009392: ee60 0ac0 vnmul.f32 s1, s1, s0
- 8009396: ee27 7a06 vmul.f32 s14, s14, s12
- 800939a: eee6 0a07 vfma.f32 s1, s12, s14
- 800939e: dc04 bgt.n 80093aa <__kernel_cosf+0x72>
- 80093a0: ee77 0ae0 vsub.f32 s1, s15, s1
- 80093a4: ee36 0ae0 vsub.f32 s0, s13, s1
- 80093a8: 4770 bx lr
- 80093aa: 4a11 ldr r2, [pc, #68] ; (80093f0 <__kernel_cosf+0xb8>)
- 80093ac: 4293 cmp r3, r2
- 80093ae: bfda itte le
- 80093b0: f103 437f addle.w r3, r3, #4278190080 ; 0xff000000
- 80093b4: ee07 3a10 vmovle s14, r3
- 80093b8: eeb5 7a02 vmovgt.f32 s14, #82 ; 0x3e900000 0.2812500
- 80093bc: ee77 7ac7 vsub.f32 s15, s15, s14
- 80093c0: ee36 0ac7 vsub.f32 s0, s13, s14
- 80093c4: ee77 7ae0 vsub.f32 s15, s15, s1
- 80093c8: ee30 0a67 vsub.f32 s0, s0, s15
- 80093cc: 4770 bx lr
- 80093ce: eeb0 0a66 vmov.f32 s0, s13
- 80093d2: 4770 bx lr
- 80093d4: ad47d74e .word 0xad47d74e
- 80093d8: 3e999999 .word 0x3e999999
- 80093dc: 310f74f6 .word 0x310f74f6
- 80093e0: b493f27c .word 0xb493f27c
- 80093e4: 37d00d01 .word 0x37d00d01
- 80093e8: bab60b61 .word 0xbab60b61
- 80093ec: 3d2aaaab .word 0x3d2aaaab
- 80093f0: 3f480000 .word 0x3f480000
-
-080093f4 <__kernel_rem_pio2f>:
- 80093f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
- 80093f8: ed2d 8b04 vpush {d8-d9}
- 80093fc: b0d7 sub sp, #348 ; 0x15c
- 80093fe: 469b mov fp, r3
- 8009400: 460e mov r6, r1
- 8009402: 4bbe ldr r3, [pc, #760] ; (80096fc <__kernel_rem_pio2f+0x308>)
- 8009404: 9964 ldr r1, [sp, #400] ; 0x190
- 8009406: 9002 str r0, [sp, #8]
- 8009408: f853 9021 ldr.w r9, [r3, r1, lsl #2]
- 800940c: 9865 ldr r0, [sp, #404] ; 0x194
- 800940e: ed9f 7abf vldr s14, [pc, #764] ; 800970c <__kernel_rem_pio2f+0x318>
- 8009412: 1ed1 subs r1, r2, #3
- 8009414: 2308 movs r3, #8
- 8009416: fb91 f1f3 sdiv r1, r1, r3
- 800941a: ea21 71e1 bic.w r1, r1, r1, asr #31
- 800941e: f10b 3aff add.w sl, fp, #4294967295 ; 0xffffffff
- 8009422: 1c4c adds r4, r1, #1
- 8009424: eba2 04c4 sub.w r4, r2, r4, lsl #3
- 8009428: eba1 050a sub.w r5, r1, sl
- 800942c: aa1a add r2, sp, #104 ; 0x68
- 800942e: eb09 070a add.w r7, r9, sl
- 8009432: eb00 0c85 add.w ip, r0, r5, lsl #2
- 8009436: 4696 mov lr, r2
- 8009438: 2300 movs r3, #0
- 800943a: 42bb cmp r3, r7
- 800943c: dd0f ble.n 800945e <__kernel_rem_pio2f+0x6a>
- 800943e: af42 add r7, sp, #264 ; 0x108
- 8009440: 2200 movs r2, #0
- 8009442: 454a cmp r2, r9
- 8009444: dc27 bgt.n 8009496 <__kernel_rem_pio2f+0xa2>
- 8009446: f10d 0c68 add.w ip, sp, #104 ; 0x68
- 800944a: eb0b 0302 add.w r3, fp, r2
- 800944e: eb0c 0383 add.w r3, ip, r3, lsl #2
- 8009452: 9d02 ldr r5, [sp, #8]
- 8009454: eddf 7aad vldr s15, [pc, #692] ; 800970c <__kernel_rem_pio2f+0x318>
- 8009458: f04f 0c00 mov.w ip, #0
- 800945c: e015 b.n 800948a <__kernel_rem_pio2f+0x96>
- 800945e: 42dd cmn r5, r3
- 8009460: bf5d ittte pl
- 8009462: f85c 2023 ldrpl.w r2, [ip, r3, lsl #2]
- 8009466: ee07 2a90 vmovpl s15, r2
- 800946a: eef8 7ae7 vcvtpl.f32.s32 s15, s15
- 800946e: eef0 7a47 vmovmi.f32 s15, s14
- 8009472: ecee 7a01 vstmia lr!, {s15}
- 8009476: 3301 adds r3, #1
- 8009478: e7df b.n 800943a <__kernel_rem_pio2f+0x46>
- 800947a: ecf5 6a01 vldmia r5!, {s13}
- 800947e: ed33 7a01 vldmdb r3!, {s14}
- 8009482: eee6 7a87 vfma.f32 s15, s13, s14
- 8009486: f10c 0c01 add.w ip, ip, #1
- 800948a: 45d4 cmp ip, sl
- 800948c: ddf5 ble.n 800947a <__kernel_rem_pio2f+0x86>
- 800948e: ece7 7a01 vstmia r7!, {s15}
- 8009492: 3201 adds r2, #1
- 8009494: e7d5 b.n 8009442 <__kernel_rem_pio2f+0x4e>
- 8009496: ab06 add r3, sp, #24
- 8009498: eb03 0389 add.w r3, r3, r9, lsl #2
- 800949c: 9304 str r3, [sp, #16]
- 800949e: eddf 8a9a vldr s17, [pc, #616] ; 8009708 <__kernel_rem_pio2f+0x314>
- 80094a2: ed9f 9a98 vldr s18, [pc, #608] ; 8009704 <__kernel_rem_pio2f+0x310>
- 80094a6: eb00 0381 add.w r3, r0, r1, lsl #2
- 80094aa: 9303 str r3, [sp, #12]
- 80094ac: 464d mov r5, r9
- 80094ae: ab56 add r3, sp, #344 ; 0x158
- 80094b0: f105 4780 add.w r7, r5, #1073741824 ; 0x40000000
- 80094b4: eb03 0385 add.w r3, r3, r5, lsl #2
- 80094b8: 3f01 subs r7, #1
- 80094ba: ed13 0a14 vldr s0, [r3, #-80] ; 0xffffffb0
- 80094be: 00bf lsls r7, r7, #2
- 80094c0: ab56 add r3, sp, #344 ; 0x158
- 80094c2: 19da adds r2, r3, r7
- 80094c4: 3a4c subs r2, #76 ; 0x4c
- 80094c6: 2300 movs r3, #0
- 80094c8: 1ae9 subs r1, r5, r3
- 80094ca: 2900 cmp r1, #0
- 80094cc: dc4c bgt.n 8009568 <__kernel_rem_pio2f+0x174>
- 80094ce: 4620 mov r0, r4
- 80094d0: f000 fba6 bl 8009c20 <scalbnf>
- 80094d4: eeb0 8a40 vmov.f32 s16, s0
- 80094d8: eeb4 0a00 vmov.f32 s0, #64 ; 0x3e000000 0.125
- 80094dc: ee28 0a00 vmul.f32 s0, s16, s0
- 80094e0: f000 fb5c bl 8009b9c <floorf>
- 80094e4: eef2 7a00 vmov.f32 s15, #32 ; 0x41000000 8.0
- 80094e8: eea0 8a67 vfms.f32 s16, s0, s15
- 80094ec: 2c00 cmp r4, #0
- 80094ee: eefd 7ac8 vcvt.s32.f32 s15, s16
- 80094f2: edcd 7a01 vstr s15, [sp, #4]
- 80094f6: eef8 7ae7 vcvt.f32.s32 s15, s15
- 80094fa: ee38 8a67 vsub.f32 s16, s16, s15
- 80094fe: dd48 ble.n 8009592 <__kernel_rem_pio2f+0x19e>
- 8009500: 1e69 subs r1, r5, #1
- 8009502: ab06 add r3, sp, #24
- 8009504: f1c4 0008 rsb r0, r4, #8
- 8009508: f853 c021 ldr.w ip, [r3, r1, lsl #2]
- 800950c: 9a01 ldr r2, [sp, #4]
- 800950e: fa4c f300 asr.w r3, ip, r0
- 8009512: 441a add r2, r3
- 8009514: 4083 lsls r3, r0
- 8009516: 9201 str r2, [sp, #4]
- 8009518: ebac 0203 sub.w r2, ip, r3
- 800951c: ab06 add r3, sp, #24
- 800951e: f843 2021 str.w r2, [r3, r1, lsl #2]
- 8009522: f1c4 0307 rsb r3, r4, #7
- 8009526: fa42 f803 asr.w r8, r2, r3
- 800952a: f1b8 0f00 cmp.w r8, #0
- 800952e: dd41 ble.n 80095b4 <__kernel_rem_pio2f+0x1c0>
- 8009530: 9b01 ldr r3, [sp, #4]
- 8009532: 2000 movs r0, #0
- 8009534: 3301 adds r3, #1
- 8009536: 9301 str r3, [sp, #4]
- 8009538: 4601 mov r1, r0
- 800953a: 4285 cmp r5, r0
- 800953c: dc6d bgt.n 800961a <__kernel_rem_pio2f+0x226>
- 800953e: 2c00 cmp r4, #0
- 8009540: dd04 ble.n 800954c <__kernel_rem_pio2f+0x158>
- 8009542: 2c01 cmp r4, #1
- 8009544: d07e beq.n 8009644 <__kernel_rem_pio2f+0x250>
- 8009546: 2c02 cmp r4, #2
- 8009548: f000 8086 beq.w 8009658 <__kernel_rem_pio2f+0x264>
- 800954c: f1b8 0f02 cmp.w r8, #2
- 8009550: d130 bne.n 80095b4 <__kernel_rem_pio2f+0x1c0>
- 8009552: eeb7 0a00 vmov.f32 s0, #112 ; 0x3f800000 1.0
- 8009556: ee30 8a48 vsub.f32 s16, s0, s16
- 800955a: b359 cbz r1, 80095b4 <__kernel_rem_pio2f+0x1c0>
- 800955c: 4620 mov r0, r4
- 800955e: f000 fb5f bl 8009c20 <scalbnf>
- 8009562: ee38 8a40 vsub.f32 s16, s16, s0
- 8009566: e025 b.n 80095b4 <__kernel_rem_pio2f+0x1c0>
- 8009568: ee60 7a28 vmul.f32 s15, s0, s17
- 800956c: a806 add r0, sp, #24
- 800956e: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8009572: eef8 7ae7 vcvt.f32.s32 s15, s15
- 8009576: eea7 0ac9 vfms.f32 s0, s15, s18
- 800957a: eebd 0ac0 vcvt.s32.f32 s0, s0
- 800957e: ee10 1a10 vmov r1, s0
- 8009582: ed32 0a01 vldmdb r2!, {s0}
- 8009586: f840 1023 str.w r1, [r0, r3, lsl #2]
- 800958a: ee37 0a80 vadd.f32 s0, s15, s0
- 800958e: 3301 adds r3, #1
- 8009590: e79a b.n 80094c8 <__kernel_rem_pio2f+0xd4>
- 8009592: d106 bne.n 80095a2 <__kernel_rem_pio2f+0x1ae>
- 8009594: 1e6b subs r3, r5, #1
- 8009596: aa06 add r2, sp, #24
- 8009598: f852 2023 ldr.w r2, [r2, r3, lsl #2]
- 800959c: ea4f 2822 mov.w r8, r2, asr #8
- 80095a0: e7c3 b.n 800952a <__kernel_rem_pio2f+0x136>
- 80095a2: eef6 7a00 vmov.f32 s15, #96 ; 0x3f000000 0.5
- 80095a6: eeb4 8ae7 vcmpe.f32 s16, s15
- 80095aa: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80095ae: da31 bge.n 8009614 <__kernel_rem_pio2f+0x220>
- 80095b0: f04f 0800 mov.w r8, #0
- 80095b4: eeb5 8a40 vcmp.f32 s16, #0.0
- 80095b8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80095bc: f040 80a8 bne.w 8009710 <__kernel_rem_pio2f+0x31c>
- 80095c0: 1e6b subs r3, r5, #1
- 80095c2: 4618 mov r0, r3
- 80095c4: 2200 movs r2, #0
- 80095c6: 4548 cmp r0, r9
- 80095c8: da4d bge.n 8009666 <__kernel_rem_pio2f+0x272>
- 80095ca: 2a00 cmp r2, #0
- 80095cc: f000 8087 beq.w 80096de <__kernel_rem_pio2f+0x2ea>
- 80095d0: aa06 add r2, sp, #24
- 80095d2: 3c08 subs r4, #8
- 80095d4: f852 1023 ldr.w r1, [r2, r3, lsl #2]
- 80095d8: 2900 cmp r1, #0
- 80095da: f000 808d beq.w 80096f8 <__kernel_rem_pio2f+0x304>
- 80095de: 4620 mov r0, r4
- 80095e0: eeb7 0a00 vmov.f32 s0, #112 ; 0x3f800000 1.0
- 80095e4: 9302 str r3, [sp, #8]
- 80095e6: f000 fb1b bl 8009c20 <scalbnf>
- 80095ea: 9b02 ldr r3, [sp, #8]
- 80095ec: ed9f 7a46 vldr s14, [pc, #280] ; 8009708 <__kernel_rem_pio2f+0x314>
- 80095f0: 0099 lsls r1, r3, #2
- 80095f2: aa42 add r2, sp, #264 ; 0x108
- 80095f4: 1850 adds r0, r2, r1
- 80095f6: 1d05 adds r5, r0, #4
- 80095f8: 461c mov r4, r3
- 80095fa: 2c00 cmp r4, #0
- 80095fc: f280 80b8 bge.w 8009770 <__kernel_rem_pio2f+0x37c>
- 8009600: 2500 movs r5, #0
- 8009602: 1b5c subs r4, r3, r5
- 8009604: 2c00 cmp r4, #0
- 8009606: f2c0 80d8 blt.w 80097ba <__kernel_rem_pio2f+0x3c6>
- 800960a: 4f3d ldr r7, [pc, #244] ; (8009700 <__kernel_rem_pio2f+0x30c>)
- 800960c: eddf 7a3f vldr s15, [pc, #252] ; 800970c <__kernel_rem_pio2f+0x318>
- 8009610: 2400 movs r4, #0
- 8009612: e0c6 b.n 80097a2 <__kernel_rem_pio2f+0x3ae>
- 8009614: f04f 0802 mov.w r8, #2
- 8009618: e78a b.n 8009530 <__kernel_rem_pio2f+0x13c>
- 800961a: ab06 add r3, sp, #24
- 800961c: f853 3020 ldr.w r3, [r3, r0, lsl #2]
- 8009620: b949 cbnz r1, 8009636 <__kernel_rem_pio2f+0x242>
- 8009622: b12b cbz r3, 8009630 <__kernel_rem_pio2f+0x23c>
- 8009624: aa06 add r2, sp, #24
- 8009626: f5c3 7380 rsb r3, r3, #256 ; 0x100
- 800962a: f842 3020 str.w r3, [r2, r0, lsl #2]
- 800962e: 2301 movs r3, #1
- 8009630: 3001 adds r0, #1
- 8009632: 4619 mov r1, r3
- 8009634: e781 b.n 800953a <__kernel_rem_pio2f+0x146>
- 8009636: aa06 add r2, sp, #24
- 8009638: f1c3 03ff rsb r3, r3, #255 ; 0xff
- 800963c: f842 3020 str.w r3, [r2, r0, lsl #2]
- 8009640: 460b mov r3, r1
- 8009642: e7f5 b.n 8009630 <__kernel_rem_pio2f+0x23c>
- 8009644: 1e68 subs r0, r5, #1
- 8009646: ab06 add r3, sp, #24
- 8009648: f853 3020 ldr.w r3, [r3, r0, lsl #2]
- 800964c: f003 037f and.w r3, r3, #127 ; 0x7f
- 8009650: aa06 add r2, sp, #24
- 8009652: f842 3020 str.w r3, [r2, r0, lsl #2]
- 8009656: e779 b.n 800954c <__kernel_rem_pio2f+0x158>
- 8009658: 1e68 subs r0, r5, #1
- 800965a: ab06 add r3, sp, #24
- 800965c: f853 3020 ldr.w r3, [r3, r0, lsl #2]
- 8009660: f003 033f and.w r3, r3, #63 ; 0x3f
- 8009664: e7f4 b.n 8009650 <__kernel_rem_pio2f+0x25c>
- 8009666: a906 add r1, sp, #24
- 8009668: f851 1020 ldr.w r1, [r1, r0, lsl #2]
- 800966c: 3801 subs r0, #1
- 800966e: 430a orrs r2, r1
- 8009670: e7a9 b.n 80095c6 <__kernel_rem_pio2f+0x1d2>
- 8009672: f10c 0c01 add.w ip, ip, #1
- 8009676: f853 2d04 ldr.w r2, [r3, #-4]!
- 800967a: 2a00 cmp r2, #0
- 800967c: d0f9 beq.n 8009672 <__kernel_rem_pio2f+0x27e>
- 800967e: eb0b 0305 add.w r3, fp, r5
- 8009682: aa1a add r2, sp, #104 ; 0x68
- 8009684: 009b lsls r3, r3, #2
- 8009686: 1898 adds r0, r3, r2
- 8009688: 3004 adds r0, #4
- 800968a: 1c69 adds r1, r5, #1
- 800968c: 3704 adds r7, #4
- 800968e: 2200 movs r2, #0
- 8009690: 4465 add r5, ip
- 8009692: 9005 str r0, [sp, #20]
- 8009694: 428d cmp r5, r1
- 8009696: f6ff af0a blt.w 80094ae <__kernel_rem_pio2f+0xba>
- 800969a: a81a add r0, sp, #104 ; 0x68
- 800969c: eb02 0c03 add.w ip, r2, r3
- 80096a0: 4484 add ip, r0
- 80096a2: 9803 ldr r0, [sp, #12]
- 80096a4: f8dd e008 ldr.w lr, [sp, #8]
- 80096a8: f850 0021 ldr.w r0, [r0, r1, lsl #2]
- 80096ac: 9001 str r0, [sp, #4]
- 80096ae: ee07 0a90 vmov s15, r0
- 80096b2: eef8 7ae7 vcvt.f32.s32 s15, s15
- 80096b6: 9805 ldr r0, [sp, #20]
- 80096b8: edcc 7a00 vstr s15, [ip]
- 80096bc: eddf 7a13 vldr s15, [pc, #76] ; 800970c <__kernel_rem_pio2f+0x318>
- 80096c0: eb00 0802 add.w r8, r0, r2
- 80096c4: f04f 0c00 mov.w ip, #0
- 80096c8: 45d4 cmp ip, sl
- 80096ca: dd0c ble.n 80096e6 <__kernel_rem_pio2f+0x2f2>
- 80096cc: eb02 0c07 add.w ip, r2, r7
- 80096d0: a842 add r0, sp, #264 ; 0x108
- 80096d2: 4484 add ip, r0
- 80096d4: edcc 7a01 vstr s15, [ip, #4]
- 80096d8: 3101 adds r1, #1
- 80096da: 3204 adds r2, #4
- 80096dc: e7da b.n 8009694 <__kernel_rem_pio2f+0x2a0>
- 80096de: 9b04 ldr r3, [sp, #16]
- 80096e0: f04f 0c01 mov.w ip, #1
- 80096e4: e7c7 b.n 8009676 <__kernel_rem_pio2f+0x282>
- 80096e6: ecfe 6a01 vldmia lr!, {s13}
- 80096ea: ed38 7a01 vldmdb r8!, {s14}
- 80096ee: f10c 0c01 add.w ip, ip, #1
- 80096f2: eee6 7a87 vfma.f32 s15, s13, s14
- 80096f6: e7e7 b.n 80096c8 <__kernel_rem_pio2f+0x2d4>
- 80096f8: 3b01 subs r3, #1
- 80096fa: e769 b.n 80095d0 <__kernel_rem_pio2f+0x1dc>
- 80096fc: 0800aa64 .word 0x0800aa64
- 8009700: 0800aa38 .word 0x0800aa38
- 8009704: 43800000 .word 0x43800000
- 8009708: 3b800000 .word 0x3b800000
- 800970c: 00000000 .word 0x00000000
- 8009710: 4260 negs r0, r4
- 8009712: eeb0 0a48 vmov.f32 s0, s16
- 8009716: f000 fa83 bl 8009c20 <scalbnf>
- 800971a: ed1f 7a06 vldr s14, [pc, #-24] ; 8009704 <__kernel_rem_pio2f+0x310>
- 800971e: eeb4 0ac7 vcmpe.f32 s0, s14
- 8009722: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8009726: db1a blt.n 800975e <__kernel_rem_pio2f+0x36a>
- 8009728: ed5f 7a09 vldr s15, [pc, #-36] ; 8009708 <__kernel_rem_pio2f+0x314>
- 800972c: ee60 7a27 vmul.f32 s15, s0, s15
- 8009730: aa06 add r2, sp, #24
- 8009732: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8009736: a906 add r1, sp, #24
- 8009738: eef8 7ae7 vcvt.f32.s32 s15, s15
- 800973c: 3408 adds r4, #8
- 800973e: eea7 0ac7 vfms.f32 s0, s15, s14
- 8009742: eefd 7ae7 vcvt.s32.f32 s15, s15
- 8009746: eebd 0ac0 vcvt.s32.f32 s0, s0
- 800974a: ee10 3a10 vmov r3, s0
- 800974e: f842 3025 str.w r3, [r2, r5, lsl #2]
- 8009752: 1c6b adds r3, r5, #1
- 8009754: ee17 2a90 vmov r2, s15
- 8009758: f841 2023 str.w r2, [r1, r3, lsl #2]
- 800975c: e73f b.n 80095de <__kernel_rem_pio2f+0x1ea>
- 800975e: eebd 0ac0 vcvt.s32.f32 s0, s0
- 8009762: aa06 add r2, sp, #24
- 8009764: ee10 3a10 vmov r3, s0
- 8009768: f842 3025 str.w r3, [r2, r5, lsl #2]
- 800976c: 462b mov r3, r5
- 800976e: e736 b.n 80095de <__kernel_rem_pio2f+0x1ea>
- 8009770: aa06 add r2, sp, #24
- 8009772: f852 2024 ldr.w r2, [r2, r4, lsl #2]
- 8009776: 9202 str r2, [sp, #8]
- 8009778: ee07 2a90 vmov s15, r2
- 800977c: eef8 7ae7 vcvt.f32.s32 s15, s15
- 8009780: 3c01 subs r4, #1
- 8009782: ee67 7a80 vmul.f32 s15, s15, s0
- 8009786: ee20 0a07 vmul.f32 s0, s0, s14
- 800978a: ed65 7a01 vstmdb r5!, {s15}
- 800978e: e734 b.n 80095fa <__kernel_rem_pio2f+0x206>
- 8009790: eb00 0c84 add.w ip, r0, r4, lsl #2
- 8009794: ecf7 6a01 vldmia r7!, {s13}
- 8009798: ed9c 7a00 vldr s14, [ip]
- 800979c: eee6 7a87 vfma.f32 s15, s13, s14
- 80097a0: 3401 adds r4, #1
- 80097a2: 454c cmp r4, r9
- 80097a4: dc01 bgt.n 80097aa <__kernel_rem_pio2f+0x3b6>
- 80097a6: 42a5 cmp r5, r4
- 80097a8: daf2 bge.n 8009790 <__kernel_rem_pio2f+0x39c>
- 80097aa: aa56 add r2, sp, #344 ; 0x158
- 80097ac: eb02 0485 add.w r4, r2, r5, lsl #2
- 80097b0: ed44 7a28 vstr s15, [r4, #-160] ; 0xffffff60
- 80097b4: 3501 adds r5, #1
- 80097b6: 3804 subs r0, #4
- 80097b8: e723 b.n 8009602 <__kernel_rem_pio2f+0x20e>
- 80097ba: 9a64 ldr r2, [sp, #400] ; 0x190
- 80097bc: 2a03 cmp r2, #3
- 80097be: d84d bhi.n 800985c <__kernel_rem_pio2f+0x468>
- 80097c0: e8df f002 tbb [pc, r2]
- 80097c4: 021f1f3e .word 0x021f1f3e
- 80097c8: aa56 add r2, sp, #344 ; 0x158
- 80097ca: 4411 add r1, r2
- 80097cc: 399c subs r1, #156 ; 0x9c
- 80097ce: 4608 mov r0, r1
- 80097d0: 461c mov r4, r3
- 80097d2: 2c00 cmp r4, #0
- 80097d4: dc5f bgt.n 8009896 <__kernel_rem_pio2f+0x4a2>
- 80097d6: 4608 mov r0, r1
- 80097d8: 461c mov r4, r3
- 80097da: 2c01 cmp r4, #1
- 80097dc: dc6b bgt.n 80098b6 <__kernel_rem_pio2f+0x4c2>
- 80097de: ed5f 7a35 vldr s15, [pc, #-212] ; 800970c <__kernel_rem_pio2f+0x318>
- 80097e2: 2b01 cmp r3, #1
- 80097e4: dc77 bgt.n 80098d6 <__kernel_rem_pio2f+0x4e2>
- 80097e6: eddd 6a2e vldr s13, [sp, #184] ; 0xb8
- 80097ea: ed9d 7a2f vldr s14, [sp, #188] ; 0xbc
- 80097ee: f1b8 0f00 cmp.w r8, #0
- 80097f2: d176 bne.n 80098e2 <__kernel_rem_pio2f+0x4ee>
- 80097f4: edc6 6a00 vstr s13, [r6]
- 80097f8: ed86 7a01 vstr s14, [r6, #4]
- 80097fc: edc6 7a02 vstr s15, [r6, #8]
- 8009800: e02c b.n 800985c <__kernel_rem_pio2f+0x468>
- 8009802: aa56 add r2, sp, #344 ; 0x158
- 8009804: 4411 add r1, r2
- 8009806: ed1f 7a3f vldr s14, [pc, #-252] ; 800970c <__kernel_rem_pio2f+0x318>
- 800980a: 399c subs r1, #156 ; 0x9c
- 800980c: 4618 mov r0, r3
- 800980e: 2800 cmp r0, #0
- 8009810: da32 bge.n 8009878 <__kernel_rem_pio2f+0x484>
- 8009812: f1b8 0f00 cmp.w r8, #0
- 8009816: d035 beq.n 8009884 <__kernel_rem_pio2f+0x490>
- 8009818: eef1 7a47 vneg.f32 s15, s14
- 800981c: edc6 7a00 vstr s15, [r6]
- 8009820: eddd 7a2e vldr s15, [sp, #184] ; 0xb8
- 8009824: ee77 7ac7 vsub.f32 s15, s15, s14
- 8009828: a82f add r0, sp, #188 ; 0xbc
- 800982a: 2101 movs r1, #1
- 800982c: 428b cmp r3, r1
- 800982e: da2c bge.n 800988a <__kernel_rem_pio2f+0x496>
- 8009830: f1b8 0f00 cmp.w r8, #0
- 8009834: d001 beq.n 800983a <__kernel_rem_pio2f+0x446>
- 8009836: eef1 7a67 vneg.f32 s15, s15
- 800983a: edc6 7a01 vstr s15, [r6, #4]
- 800983e: e00d b.n 800985c <__kernel_rem_pio2f+0x468>
- 8009840: aa56 add r2, sp, #344 ; 0x158
- 8009842: 4411 add r1, r2
- 8009844: ed5f 7a4f vldr s15, [pc, #-316] ; 800970c <__kernel_rem_pio2f+0x318>
- 8009848: 399c subs r1, #156 ; 0x9c
- 800984a: 2b00 cmp r3, #0
- 800984c: da0e bge.n 800986c <__kernel_rem_pio2f+0x478>
- 800984e: f1b8 0f00 cmp.w r8, #0
- 8009852: d001 beq.n 8009858 <__kernel_rem_pio2f+0x464>
- 8009854: eef1 7a67 vneg.f32 s15, s15
- 8009858: edc6 7a00 vstr s15, [r6]
- 800985c: 9b01 ldr r3, [sp, #4]
- 800985e: f003 0007 and.w r0, r3, #7
- 8009862: b057 add sp, #348 ; 0x15c
- 8009864: ecbd 8b04 vpop {d8-d9}
- 8009868: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
- 800986c: ed31 7a01 vldmdb r1!, {s14}
- 8009870: 3b01 subs r3, #1
- 8009872: ee77 7a87 vadd.f32 s15, s15, s14
- 8009876: e7e8 b.n 800984a <__kernel_rem_pio2f+0x456>
- 8009878: ed71 7a01 vldmdb r1!, {s15}
- 800987c: 3801 subs r0, #1
- 800987e: ee37 7a27 vadd.f32 s14, s14, s15
- 8009882: e7c4 b.n 800980e <__kernel_rem_pio2f+0x41a>
- 8009884: eef0 7a47 vmov.f32 s15, s14
- 8009888: e7c8 b.n 800981c <__kernel_rem_pio2f+0x428>
- 800988a: ecb0 7a01 vldmia r0!, {s14}
- 800988e: 3101 adds r1, #1
- 8009890: ee77 7a87 vadd.f32 s15, s15, s14
- 8009894: e7ca b.n 800982c <__kernel_rem_pio2f+0x438>
- 8009896: ed50 7a02 vldr s15, [r0, #-8]
- 800989a: ed70 6a01 vldmdb r0!, {s13}
- 800989e: ee37 7aa6 vadd.f32 s14, s15, s13
- 80098a2: 3c01 subs r4, #1
- 80098a4: ee77 7ac7 vsub.f32 s15, s15, s14
- 80098a8: ed00 7a01 vstr s14, [r0, #-4]
- 80098ac: ee77 7aa6 vadd.f32 s15, s15, s13
- 80098b0: edc0 7a00 vstr s15, [r0]
- 80098b4: e78d b.n 80097d2 <__kernel_rem_pio2f+0x3de>
- 80098b6: ed50 7a02 vldr s15, [r0, #-8]
- 80098ba: ed70 6a01 vldmdb r0!, {s13}
- 80098be: ee37 7aa6 vadd.f32 s14, s15, s13
- 80098c2: 3c01 subs r4, #1
- 80098c4: ee77 7ac7 vsub.f32 s15, s15, s14
- 80098c8: ed00 7a01 vstr s14, [r0, #-4]
- 80098cc: ee77 7aa6 vadd.f32 s15, s15, s13
- 80098d0: edc0 7a00 vstr s15, [r0]
- 80098d4: e781 b.n 80097da <__kernel_rem_pio2f+0x3e6>
- 80098d6: ed31 7a01 vldmdb r1!, {s14}
- 80098da: 3b01 subs r3, #1
- 80098dc: ee77 7a87 vadd.f32 s15, s15, s14
- 80098e0: e77f b.n 80097e2 <__kernel_rem_pio2f+0x3ee>
- 80098e2: eef1 6a66 vneg.f32 s13, s13
- 80098e6: eeb1 7a47 vneg.f32 s14, s14
- 80098ea: edc6 6a00 vstr s13, [r6]
- 80098ee: ed86 7a01 vstr s14, [r6, #4]
- 80098f2: eef1 7a67 vneg.f32 s15, s15
- 80098f6: e781 b.n 80097fc <__kernel_rem_pio2f+0x408>
-
-080098f8 <__kernel_sinf>:
- 80098f8: ee10 3a10 vmov r3, s0
- 80098fc: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 8009900: f1b3 5f48 cmp.w r3, #838860800 ; 0x32000000
- 8009904: da04 bge.n 8009910 <__kernel_sinf+0x18>
- 8009906: eefd 7ac0 vcvt.s32.f32 s15, s0
- 800990a: ee17 3a90 vmov r3, s15
- 800990e: b35b cbz r3, 8009968 <__kernel_sinf+0x70>
- 8009910: ee20 7a00 vmul.f32 s14, s0, s0
- 8009914: eddf 7a15 vldr s15, [pc, #84] ; 800996c <__kernel_sinf+0x74>
- 8009918: ed9f 6a15 vldr s12, [pc, #84] ; 8009970 <__kernel_sinf+0x78>
- 800991c: eea7 6a27 vfma.f32 s12, s14, s15
- 8009920: eddf 7a14 vldr s15, [pc, #80] ; 8009974 <__kernel_sinf+0x7c>
- 8009924: eee6 7a07 vfma.f32 s15, s12, s14
- 8009928: ed9f 6a13 vldr s12, [pc, #76] ; 8009978 <__kernel_sinf+0x80>
- 800992c: eea7 6a87 vfma.f32 s12, s15, s14
- 8009930: eddf 7a12 vldr s15, [pc, #72] ; 800997c <__kernel_sinf+0x84>
- 8009934: ee60 6a07 vmul.f32 s13, s0, s14
- 8009938: eee6 7a07 vfma.f32 s15, s12, s14
- 800993c: b930 cbnz r0, 800994c <__kernel_sinf+0x54>
- 800993e: ed9f 6a10 vldr s12, [pc, #64] ; 8009980 <__kernel_sinf+0x88>
- 8009942: eea7 6a27 vfma.f32 s12, s14, s15
- 8009946: eea6 0a26 vfma.f32 s0, s12, s13
- 800994a: 4770 bx lr
- 800994c: ee67 7ae6 vnmul.f32 s15, s15, s13
- 8009950: eeb6 6a00 vmov.f32 s12, #96 ; 0x3f000000 0.5
- 8009954: eee0 7a86 vfma.f32 s15, s1, s12
- 8009958: eed7 0a87 vfnms.f32 s1, s15, s14
- 800995c: eddf 7a09 vldr s15, [pc, #36] ; 8009984 <__kernel_sinf+0x8c>
- 8009960: eee6 0aa7 vfma.f32 s1, s13, s15
- 8009964: ee30 0a60 vsub.f32 s0, s0, s1
- 8009968: 4770 bx lr
- 800996a: bf00 nop
- 800996c: 2f2ec9d3 .word 0x2f2ec9d3
- 8009970: b2d72f34 .word 0xb2d72f34
- 8009974: 3638ef1b .word 0x3638ef1b
- 8009978: b9500d01 .word 0xb9500d01
- 800997c: 3c088889 .word 0x3c088889
- 8009980: be2aaaab .word 0xbe2aaaab
- 8009984: 3e2aaaab .word 0x3e2aaaab
-
-08009988 <fabs>:
- 8009988: ec51 0b10 vmov r0, r1, d0
- 800998c: ee10 2a10 vmov r2, s0
- 8009990: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000
- 8009994: ec43 2b10 vmov d0, r2, r3
- 8009998: 4770 bx lr
- 800999a: 0000 movs r0, r0
- 800999c: 0000 movs r0, r0
- ...
-
-080099a0 <floor>:
- 80099a0: ee10 1a90 vmov r1, s1
- 80099a4: f3c1 520a ubfx r2, r1, #20, #11
- 80099a8: f2a2 33ff subw r3, r2, #1023 ; 0x3ff
- 80099ac: 2b13 cmp r3, #19
- 80099ae: b530 push {r4, r5, lr}
- 80099b0: ee10 0a10 vmov r0, s0
- 80099b4: ee10 5a10 vmov r5, s0
- 80099b8: dc33 bgt.n 8009a22 <floor+0x82>
- 80099ba: 2b00 cmp r3, #0
- 80099bc: da17 bge.n 80099ee <floor+0x4e>
- 80099be: ed9f 7b30 vldr d7, [pc, #192] ; 8009a80 <floor+0xe0>
- 80099c2: ee30 0b07 vadd.f64 d0, d0, d7
- 80099c6: eeb5 0bc0 vcmpe.f64 d0, #0.0
- 80099ca: eef1 fa10 vmrs APSR_nzcv, fpscr
- 80099ce: dd09 ble.n 80099e4 <floor+0x44>
- 80099d0: 2900 cmp r1, #0
- 80099d2: da50 bge.n 8009a76 <floor+0xd6>
- 80099d4: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000
- 80099d8: 4a2b ldr r2, [pc, #172] ; (8009a88 <floor+0xe8>)
- 80099da: 4303 orrs r3, r0
- 80099dc: 2000 movs r0, #0
- 80099de: 4283 cmp r3, r0
- 80099e0: bf18 it ne
- 80099e2: 4611 movne r1, r2
- 80099e4: 460b mov r3, r1
- 80099e6: 4602 mov r2, r0
- 80099e8: ec43 2b10 vmov d0, r2, r3
- 80099ec: e020 b.n 8009a30 <floor+0x90>
- 80099ee: 4a27 ldr r2, [pc, #156] ; (8009a8c <floor+0xec>)
- 80099f0: 411a asrs r2, r3
- 80099f2: ea01 0402 and.w r4, r1, r2
- 80099f6: 4304 orrs r4, r0
- 80099f8: d01a beq.n 8009a30 <floor+0x90>
- 80099fa: ed9f 7b21 vldr d7, [pc, #132] ; 8009a80 <floor+0xe0>
- 80099fe: ee30 0b07 vadd.f64 d0, d0, d7
- 8009a02: eeb5 0bc0 vcmpe.f64 d0, #0.0
- 8009a06: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8009a0a: ddeb ble.n 80099e4 <floor+0x44>
- 8009a0c: 2900 cmp r1, #0
- 8009a0e: bfbe ittt lt
- 8009a10: f44f 1080 movlt.w r0, #1048576 ; 0x100000
- 8009a14: fa40 f303 asrlt.w r3, r0, r3
- 8009a18: 18c9 addlt r1, r1, r3
- 8009a1a: ea21 0102 bic.w r1, r1, r2
- 8009a1e: 2000 movs r0, #0
- 8009a20: e7e0 b.n 80099e4 <floor+0x44>
- 8009a22: 2b33 cmp r3, #51 ; 0x33
- 8009a24: dd05 ble.n 8009a32 <floor+0x92>
- 8009a26: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 8009a2a: d101 bne.n 8009a30 <floor+0x90>
- 8009a2c: ee30 0b00 vadd.f64 d0, d0, d0
- 8009a30: bd30 pop {r4, r5, pc}
- 8009a32: f2a2 4413 subw r4, r2, #1043 ; 0x413
- 8009a36: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8009a3a: 40e2 lsrs r2, r4
- 8009a3c: 4202 tst r2, r0
- 8009a3e: d0f7 beq.n 8009a30 <floor+0x90>
- 8009a40: ed9f 7b0f vldr d7, [pc, #60] ; 8009a80 <floor+0xe0>
- 8009a44: ee30 0b07 vadd.f64 d0, d0, d7
- 8009a48: eeb5 0bc0 vcmpe.f64 d0, #0.0
- 8009a4c: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8009a50: ddc8 ble.n 80099e4 <floor+0x44>
- 8009a52: 2900 cmp r1, #0
- 8009a54: da02 bge.n 8009a5c <floor+0xbc>
- 8009a56: 2b14 cmp r3, #20
- 8009a58: d103 bne.n 8009a62 <floor+0xc2>
- 8009a5a: 3101 adds r1, #1
- 8009a5c: ea20 0002 bic.w r0, r0, r2
- 8009a60: e7c0 b.n 80099e4 <floor+0x44>
- 8009a62: 2401 movs r4, #1
- 8009a64: f1c3 0334 rsb r3, r3, #52 ; 0x34
- 8009a68: fa04 f303 lsl.w r3, r4, r3
- 8009a6c: 4418 add r0, r3
- 8009a6e: 42a8 cmp r0, r5
- 8009a70: bf38 it cc
- 8009a72: 1909 addcc r1, r1, r4
- 8009a74: e7f2 b.n 8009a5c <floor+0xbc>
- 8009a76: 2000 movs r0, #0
- 8009a78: 4601 mov r1, r0
- 8009a7a: e7b3 b.n 80099e4 <floor+0x44>
- 8009a7c: f3af 8000 nop.w
- 8009a80: 8800759c .word 0x8800759c
- 8009a84: 7e37e43c .word 0x7e37e43c
- 8009a88: bff00000 .word 0xbff00000
- 8009a8c: 000fffff .word 0x000fffff
-
-08009a90 <scalbn>:
- 8009a90: b500 push {lr}
- 8009a92: ed2d 8b02 vpush {d8}
- 8009a96: b083 sub sp, #12
- 8009a98: ed8d 0b00 vstr d0, [sp]
- 8009a9c: 9b01 ldr r3, [sp, #4]
- 8009a9e: f3c3 520a ubfx r2, r3, #20, #11
- 8009aa2: b9a2 cbnz r2, 8009ace <scalbn+0x3e>
- 8009aa4: 9a00 ldr r2, [sp, #0]
- 8009aa6: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 8009aaa: 4313 orrs r3, r2
- 8009aac: d03a beq.n 8009b24 <scalbn+0x94>
- 8009aae: ed9f 7b2e vldr d7, [pc, #184] ; 8009b68 <scalbn+0xd8>
- 8009ab2: 4b35 ldr r3, [pc, #212] ; (8009b88 <scalbn+0xf8>)
- 8009ab4: ee20 7b07 vmul.f64 d7, d0, d7
- 8009ab8: 4298 cmp r0, r3
- 8009aba: ed8d 7b00 vstr d7, [sp]
- 8009abe: da11 bge.n 8009ae4 <scalbn+0x54>
- 8009ac0: ed9f 7b2b vldr d7, [pc, #172] ; 8009b70 <scalbn+0xe0>
- 8009ac4: ed9d 6b00 vldr d6, [sp]
- 8009ac8: ee27 7b06 vmul.f64 d7, d7, d6
- 8009acc: e007 b.n 8009ade <scalbn+0x4e>
- 8009ace: f240 71ff movw r1, #2047 ; 0x7ff
- 8009ad2: 428a cmp r2, r1
- 8009ad4: d10a bne.n 8009aec <scalbn+0x5c>
- 8009ad6: ed9d 7b00 vldr d7, [sp]
- 8009ada: ee37 7b07 vadd.f64 d7, d7, d7
- 8009ade: ed8d 7b00 vstr d7, [sp]
- 8009ae2: e01f b.n 8009b24 <scalbn+0x94>
- 8009ae4: 9b01 ldr r3, [sp, #4]
- 8009ae6: f3c3 520a ubfx r2, r3, #20, #11
- 8009aea: 3a36 subs r2, #54 ; 0x36
- 8009aec: 4402 add r2, r0
- 8009aee: f240 71fe movw r1, #2046 ; 0x7fe
- 8009af2: 428a cmp r2, r1
- 8009af4: dd0a ble.n 8009b0c <scalbn+0x7c>
- 8009af6: ed9f 8b20 vldr d8, [pc, #128] ; 8009b78 <scalbn+0xe8>
- 8009afa: eeb0 0b48 vmov.f64 d0, d8
- 8009afe: ed9d 1b00 vldr d1, [sp]
- 8009b02: f000 f8ed bl 8009ce0 <copysign>
- 8009b06: ee20 7b08 vmul.f64 d7, d0, d8
- 8009b0a: e7e8 b.n 8009ade <scalbn+0x4e>
- 8009b0c: 2a00 cmp r2, #0
- 8009b0e: dd10 ble.n 8009b32 <scalbn+0xa2>
- 8009b10: e9dd 0100 ldrd r0, r1, [sp]
- 8009b14: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000
- 8009b18: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000
- 8009b1c: ea43 5102 orr.w r1, r3, r2, lsl #20
- 8009b20: e9cd 0100 strd r0, r1, [sp]
- 8009b24: ed9d 0b00 vldr d0, [sp]
- 8009b28: b003 add sp, #12
- 8009b2a: ecbd 8b02 vpop {d8}
- 8009b2e: f85d fb04 ldr.w pc, [sp], #4
- 8009b32: f112 0f35 cmn.w r2, #53 ; 0x35
- 8009b36: da06 bge.n 8009b46 <scalbn+0xb6>
- 8009b38: f24c 3350 movw r3, #50000 ; 0xc350
- 8009b3c: 4298 cmp r0, r3
- 8009b3e: dcda bgt.n 8009af6 <scalbn+0x66>
- 8009b40: ed9f 8b0b vldr d8, [pc, #44] ; 8009b70 <scalbn+0xe0>
- 8009b44: e7d9 b.n 8009afa <scalbn+0x6a>
- 8009b46: e9dd 0100 ldrd r0, r1, [sp]
- 8009b4a: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000
- 8009b4e: 3236 adds r2, #54 ; 0x36
- 8009b50: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000
- 8009b54: ea43 5102 orr.w r1, r3, r2, lsl #20
- 8009b58: ec41 0b17 vmov d7, r0, r1
- 8009b5c: ed9f 6b08 vldr d6, [pc, #32] ; 8009b80 <scalbn+0xf0>
- 8009b60: e7b2 b.n 8009ac8 <scalbn+0x38>
- 8009b62: bf00 nop
- 8009b64: f3af 8000 nop.w
- 8009b68: 00000000 .word 0x00000000
- 8009b6c: 43500000 .word 0x43500000
- 8009b70: c2f8f359 .word 0xc2f8f359
- 8009b74: 01a56e1f .word 0x01a56e1f
- 8009b78: 8800759c .word 0x8800759c
- 8009b7c: 7e37e43c .word 0x7e37e43c
- 8009b80: 00000000 .word 0x00000000
- 8009b84: 3c900000 .word 0x3c900000
- 8009b88: ffff3cb0 .word 0xffff3cb0
-
-08009b8c <fabsf>:
- 8009b8c: ee10 3a10 vmov r3, s0
- 8009b90: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 8009b94: ee00 3a10 vmov s0, r3
- 8009b98: 4770 bx lr
- ...
-
-08009b9c <floorf>:
- 8009b9c: ee10 3a10 vmov r3, s0
- 8009ba0: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000
- 8009ba4: 0dca lsrs r2, r1, #23
- 8009ba6: 3a7f subs r2, #127 ; 0x7f
- 8009ba8: 2a16 cmp r2, #22
- 8009baa: dc2a bgt.n 8009c02 <floorf+0x66>
- 8009bac: 2a00 cmp r2, #0
- 8009bae: da11 bge.n 8009bd4 <floorf+0x38>
- 8009bb0: eddf 7a18 vldr s15, [pc, #96] ; 8009c14 <floorf+0x78>
- 8009bb4: ee30 0a27 vadd.f32 s0, s0, s15
- 8009bb8: eeb5 0ac0 vcmpe.f32 s0, #0.0
- 8009bbc: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8009bc0: dd05 ble.n 8009bce <floorf+0x32>
- 8009bc2: 2b00 cmp r3, #0
- 8009bc4: da23 bge.n 8009c0e <floorf+0x72>
- 8009bc6: 4a14 ldr r2, [pc, #80] ; (8009c18 <floorf+0x7c>)
- 8009bc8: 2900 cmp r1, #0
- 8009bca: bf18 it ne
- 8009bcc: 4613 movne r3, r2
- 8009bce: ee00 3a10 vmov s0, r3
- 8009bd2: 4770 bx lr
- 8009bd4: 4911 ldr r1, [pc, #68] ; (8009c1c <floorf+0x80>)
- 8009bd6: 4111 asrs r1, r2
- 8009bd8: 420b tst r3, r1
- 8009bda: d0fa beq.n 8009bd2 <floorf+0x36>
- 8009bdc: eddf 7a0d vldr s15, [pc, #52] ; 8009c14 <floorf+0x78>
- 8009be0: ee30 0a27 vadd.f32 s0, s0, s15
- 8009be4: eeb5 0ac0 vcmpe.f32 s0, #0.0
- 8009be8: eef1 fa10 vmrs APSR_nzcv, fpscr
- 8009bec: ddef ble.n 8009bce <floorf+0x32>
- 8009bee: 2b00 cmp r3, #0
- 8009bf0: bfbe ittt lt
- 8009bf2: f44f 0000 movlt.w r0, #8388608 ; 0x800000
- 8009bf6: fa40 f202 asrlt.w r2, r0, r2
- 8009bfa: 189b addlt r3, r3, r2
- 8009bfc: ea23 0301 bic.w r3, r3, r1
- 8009c00: e7e5 b.n 8009bce <floorf+0x32>
- 8009c02: f1b1 4fff cmp.w r1, #2139095040 ; 0x7f800000
- 8009c06: d3e4 bcc.n 8009bd2 <floorf+0x36>
- 8009c08: ee30 0a00 vadd.f32 s0, s0, s0
- 8009c0c: 4770 bx lr
- 8009c0e: 2300 movs r3, #0
- 8009c10: e7dd b.n 8009bce <floorf+0x32>
- 8009c12: bf00 nop
- 8009c14: 7149f2ca .word 0x7149f2ca
- 8009c18: bf800000 .word 0xbf800000
- 8009c1c: 007fffff .word 0x007fffff
-
-08009c20 <scalbnf>:
- 8009c20: b508 push {r3, lr}
- 8009c22: ee10 2a10 vmov r2, s0
- 8009c26: f032 4300 bics.w r3, r2, #2147483648 ; 0x80000000
- 8009c2a: ed2d 8b02 vpush {d8}
- 8009c2e: eef0 0a40 vmov.f32 s1, s0
- 8009c32: d004 beq.n 8009c3e <scalbnf+0x1e>
- 8009c34: f1b3 4fff cmp.w r3, #2139095040 ; 0x7f800000
- 8009c38: d306 bcc.n 8009c48 <scalbnf+0x28>
- 8009c3a: ee70 0a00 vadd.f32 s1, s0, s0
- 8009c3e: ecbd 8b02 vpop {d8}
- 8009c42: eeb0 0a60 vmov.f32 s0, s1
- 8009c46: bd08 pop {r3, pc}
- 8009c48: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
- 8009c4c: d21c bcs.n 8009c88 <scalbnf+0x68>
- 8009c4e: 4b1f ldr r3, [pc, #124] ; (8009ccc <scalbnf+0xac>)
- 8009c50: eddf 7a1f vldr s15, [pc, #124] ; 8009cd0 <scalbnf+0xb0>
- 8009c54: 4298 cmp r0, r3
- 8009c56: ee60 0a27 vmul.f32 s1, s0, s15
- 8009c5a: db10 blt.n 8009c7e <scalbnf+0x5e>
- 8009c5c: ee10 2a90 vmov r2, s1
- 8009c60: f3c2 53c7 ubfx r3, r2, #23, #8
- 8009c64: 3b19 subs r3, #25
- 8009c66: 4403 add r3, r0
- 8009c68: 2bfe cmp r3, #254 ; 0xfe
- 8009c6a: dd0f ble.n 8009c8c <scalbnf+0x6c>
- 8009c6c: ed9f 8a19 vldr s16, [pc, #100] ; 8009cd4 <scalbnf+0xb4>
- 8009c70: eeb0 0a48 vmov.f32 s0, s16
- 8009c74: f000 f843 bl 8009cfe <copysignf>
- 8009c78: ee60 0a08 vmul.f32 s1, s0, s16
- 8009c7c: e7df b.n 8009c3e <scalbnf+0x1e>
- 8009c7e: eddf 7a16 vldr s15, [pc, #88] ; 8009cd8 <scalbnf+0xb8>
- 8009c82: ee60 0aa7 vmul.f32 s1, s1, s15
- 8009c86: e7da b.n 8009c3e <scalbnf+0x1e>
- 8009c88: 0ddb lsrs r3, r3, #23
- 8009c8a: e7ec b.n 8009c66 <scalbnf+0x46>
- 8009c8c: 2b00 cmp r3, #0
- 8009c8e: dd06 ble.n 8009c9e <scalbnf+0x7e>
- 8009c90: f022 42ff bic.w r2, r2, #2139095040 ; 0x7f800000
- 8009c94: ea42 53c3 orr.w r3, r2, r3, lsl #23
- 8009c98: ee00 3a90 vmov s1, r3
- 8009c9c: e7cf b.n 8009c3e <scalbnf+0x1e>
- 8009c9e: f113 0f16 cmn.w r3, #22
- 8009ca2: da06 bge.n 8009cb2 <scalbnf+0x92>
- 8009ca4: f24c 3350 movw r3, #50000 ; 0xc350
- 8009ca8: 4298 cmp r0, r3
- 8009caa: dcdf bgt.n 8009c6c <scalbnf+0x4c>
- 8009cac: ed9f 8a0a vldr s16, [pc, #40] ; 8009cd8 <scalbnf+0xb8>
- 8009cb0: e7de b.n 8009c70 <scalbnf+0x50>
- 8009cb2: 3319 adds r3, #25
- 8009cb4: f022 42ff bic.w r2, r2, #2139095040 ; 0x7f800000
- 8009cb8: ea42 53c3 orr.w r3, r2, r3, lsl #23
- 8009cbc: eddf 7a07 vldr s15, [pc, #28] ; 8009cdc <scalbnf+0xbc>
- 8009cc0: ee07 3a10 vmov s14, r3
- 8009cc4: ee67 0a27 vmul.f32 s1, s14, s15
- 8009cc8: e7b9 b.n 8009c3e <scalbnf+0x1e>
- 8009cca: bf00 nop
- 8009ccc: ffff3cb0 .word 0xffff3cb0
- 8009cd0: 4c000000 .word 0x4c000000
- 8009cd4: 7149f2ca .word 0x7149f2ca
- 8009cd8: 0da24260 .word 0x0da24260
- 8009cdc: 33000000 .word 0x33000000
-
-08009ce0 <copysign>:
- 8009ce0: ec51 0b10 vmov r0, r1, d0
- 8009ce4: ee11 0a90 vmov r0, s3
- 8009ce8: ee10 2a10 vmov r2, s0
- 8009cec: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
- 8009cf0: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
- 8009cf4: ea41 0300 orr.w r3, r1, r0
- 8009cf8: ec43 2b10 vmov d0, r2, r3
- 8009cfc: 4770 bx lr
-
-08009cfe <copysignf>:
- 8009cfe: ee10 3a10 vmov r3, s0
- 8009d02: ee10 2a90 vmov r2, s1
- 8009d06: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
- 8009d0a: f002 4200 and.w r2, r2, #2147483648 ; 0x80000000
- 8009d0e: 4313 orrs r3, r2
- 8009d10: ee00 3a10 vmov s0, r3
- 8009d14: 4770 bx lr
- ...
-
-08009d18 <__errno>:
- 8009d18: 4b01 ldr r3, [pc, #4] ; (8009d20 <__errno+0x8>)
- 8009d1a: 6818 ldr r0, [r3, #0]
- 8009d1c: 4770 bx lr
- 8009d1e: bf00 nop
- 8009d20: 2000001c .word 0x2000001c
-
-08009d24 <__libc_init_array>:
- 8009d24: b570 push {r4, r5, r6, lr}
- 8009d26: 4e0d ldr r6, [pc, #52] ; (8009d5c <__libc_init_array+0x38>)
- 8009d28: 4c0d ldr r4, [pc, #52] ; (8009d60 <__libc_init_array+0x3c>)
- 8009d2a: 1ba4 subs r4, r4, r6
- 8009d2c: 10a4 asrs r4, r4, #2
- 8009d2e: 2500 movs r5, #0
- 8009d30: 42a5 cmp r5, r4
- 8009d32: d109 bne.n 8009d48 <__libc_init_array+0x24>
- 8009d34: 4e0b ldr r6, [pc, #44] ; (8009d64 <__libc_init_array+0x40>)
- 8009d36: 4c0c ldr r4, [pc, #48] ; (8009d68 <__libc_init_array+0x44>)
- 8009d38: f000 f934 bl 8009fa4 <_init>
- 8009d3c: 1ba4 subs r4, r4, r6
- 8009d3e: 10a4 asrs r4, r4, #2
- 8009d40: 2500 movs r5, #0
- 8009d42: 42a5 cmp r5, r4
- 8009d44: d105 bne.n 8009d52 <__libc_init_array+0x2e>
- 8009d46: bd70 pop {r4, r5, r6, pc}
- 8009d48: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8009d4c: 4798 blx r3
- 8009d4e: 3501 adds r5, #1
- 8009d50: e7ee b.n 8009d30 <__libc_init_array+0xc>
- 8009d52: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8009d56: 4798 blx r3
- 8009d58: 3501 adds r5, #1
- 8009d5a: e7f2 b.n 8009d42 <__libc_init_array+0x1e>
- 8009d5c: 0800aa78 .word 0x0800aa78
- 8009d60: 0800aa78 .word 0x0800aa78
- 8009d64: 0800aa78 .word 0x0800aa78
- 8009d68: 0800aa80 .word 0x0800aa80
-
-08009d6c <memcpy>:
- 8009d6c: b510 push {r4, lr}
- 8009d6e: 1e43 subs r3, r0, #1
- 8009d70: 440a add r2, r1
- 8009d72: 4291 cmp r1, r2
- 8009d74: d100 bne.n 8009d78 <memcpy+0xc>
- 8009d76: bd10 pop {r4, pc}
- 8009d78: f811 4b01 ldrb.w r4, [r1], #1
- 8009d7c: f803 4f01 strb.w r4, [r3, #1]!
- 8009d80: e7f7 b.n 8009d72 <memcpy+0x6>
-
-08009d82 <memmove>:
- 8009d82: 4288 cmp r0, r1
- 8009d84: b510 push {r4, lr}
- 8009d86: eb01 0302 add.w r3, r1, r2
- 8009d8a: d807 bhi.n 8009d9c <memmove+0x1a>
- 8009d8c: 1e42 subs r2, r0, #1
- 8009d8e: 4299 cmp r1, r3
- 8009d90: d00a beq.n 8009da8 <memmove+0x26>
- 8009d92: f811 4b01 ldrb.w r4, [r1], #1
- 8009d96: f802 4f01 strb.w r4, [r2, #1]!
- 8009d9a: e7f8 b.n 8009d8e <memmove+0xc>
- 8009d9c: 4283 cmp r3, r0
- 8009d9e: d9f5 bls.n 8009d8c <memmove+0xa>
- 8009da0: 1881 adds r1, r0, r2
- 8009da2: 1ad2 subs r2, r2, r3
- 8009da4: 42d3 cmn r3, r2
- 8009da6: d100 bne.n 8009daa <memmove+0x28>
- 8009da8: bd10 pop {r4, pc}
- 8009daa: f813 4d01 ldrb.w r4, [r3, #-1]!
- 8009dae: f801 4d01 strb.w r4, [r1, #-1]!
- 8009db2: e7f7 b.n 8009da4 <memmove+0x22>
-
-08009db4 <memset>:
- 8009db4: 4402 add r2, r0
- 8009db6: 4603 mov r3, r0
- 8009db8: 4293 cmp r3, r2
- 8009dba: d100 bne.n 8009dbe <memset+0xa>
- 8009dbc: 4770 bx lr
- 8009dbe: f803 1b01 strb.w r1, [r3], #1
- 8009dc2: e7f9 b.n 8009db8 <memset+0x4>
-
-08009dc4 <realloc>:
- 8009dc4: 4b02 ldr r3, [pc, #8] ; (8009dd0 <realloc+0xc>)
- 8009dc6: 460a mov r2, r1
- 8009dc8: 4601 mov r1, r0
- 8009dca: 6818 ldr r0, [r3, #0]
- 8009dcc: f000 b802 b.w 8009dd4 <_realloc_r>
- 8009dd0: 2000001c .word 0x2000001c
-
-08009dd4 <_realloc_r>:
- 8009dd4: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8009dd6: 4607 mov r7, r0
- 8009dd8: 4614 mov r4, r2
- 8009dda: 460e mov r6, r1
- 8009ddc: b921 cbnz r1, 8009de8 <_realloc_r+0x14>
- 8009dde: 4611 mov r1, r2
- 8009de0: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
- 8009de4: f000 b86a b.w 8009ebc <_malloc_r>
- 8009de8: b922 cbnz r2, 8009df4 <_realloc_r+0x20>
- 8009dea: f000 f819 bl 8009e20 <_free_r>
- 8009dee: 4625 mov r5, r4
- 8009df0: 4628 mov r0, r5
- 8009df2: bdf8 pop {r3, r4, r5, r6, r7, pc}
- 8009df4: f000 f8bc bl 8009f70 <_malloc_usable_size_r>
- 8009df8: 42a0 cmp r0, r4
- 8009dfa: d20f bcs.n 8009e1c <_realloc_r+0x48>
- 8009dfc: 4621 mov r1, r4
- 8009dfe: 4638 mov r0, r7
- 8009e00: f000 f85c bl 8009ebc <_malloc_r>
- 8009e04: 4605 mov r5, r0
- 8009e06: 2800 cmp r0, #0
- 8009e08: d0f2 beq.n 8009df0 <_realloc_r+0x1c>
- 8009e0a: 4631 mov r1, r6
- 8009e0c: 4622 mov r2, r4
- 8009e0e: f7ff ffad bl 8009d6c <memcpy>
- 8009e12: 4631 mov r1, r6
- 8009e14: 4638 mov r0, r7
- 8009e16: f000 f803 bl 8009e20 <_free_r>
- 8009e1a: e7e9 b.n 8009df0 <_realloc_r+0x1c>
- 8009e1c: 4635 mov r5, r6
- 8009e1e: e7e7 b.n 8009df0 <_realloc_r+0x1c>
-
-08009e20 <_free_r>:
- 8009e20: b538 push {r3, r4, r5, lr}
- 8009e22: 4605 mov r5, r0
- 8009e24: 2900 cmp r1, #0
- 8009e26: d045 beq.n 8009eb4 <_free_r+0x94>
- 8009e28: f851 3c04 ldr.w r3, [r1, #-4]
- 8009e2c: 1f0c subs r4, r1, #4
- 8009e2e: 2b00 cmp r3, #0
- 8009e30: bfb8 it lt
- 8009e32: 18e4 addlt r4, r4, r3
- 8009e34: f000 f8b4 bl 8009fa0 <__malloc_lock>
- 8009e38: 4a1f ldr r2, [pc, #124] ; (8009eb8 <_free_r+0x98>)
- 8009e3a: 6813 ldr r3, [r2, #0]
- 8009e3c: 4610 mov r0, r2
- 8009e3e: b933 cbnz r3, 8009e4e <_free_r+0x2e>
- 8009e40: 6063 str r3, [r4, #4]
- 8009e42: 6014 str r4, [r2, #0]
- 8009e44: 4628 mov r0, r5
- 8009e46: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
- 8009e4a: f000 b8aa b.w 8009fa2 <__malloc_unlock>
- 8009e4e: 42a3 cmp r3, r4
- 8009e50: d90c bls.n 8009e6c <_free_r+0x4c>
- 8009e52: 6821 ldr r1, [r4, #0]
- 8009e54: 1862 adds r2, r4, r1
- 8009e56: 4293 cmp r3, r2
- 8009e58: bf04 itt eq
- 8009e5a: 681a ldreq r2, [r3, #0]
- 8009e5c: 685b ldreq r3, [r3, #4]
- 8009e5e: 6063 str r3, [r4, #4]
- 8009e60: bf04 itt eq
- 8009e62: 1852 addeq r2, r2, r1
- 8009e64: 6022 streq r2, [r4, #0]
- 8009e66: 6004 str r4, [r0, #0]
- 8009e68: e7ec b.n 8009e44 <_free_r+0x24>
- 8009e6a: 4613 mov r3, r2
- 8009e6c: 685a ldr r2, [r3, #4]
- 8009e6e: b10a cbz r2, 8009e74 <_free_r+0x54>
- 8009e70: 42a2 cmp r2, r4
- 8009e72: d9fa bls.n 8009e6a <_free_r+0x4a>
- 8009e74: 6819 ldr r1, [r3, #0]
- 8009e76: 1858 adds r0, r3, r1
- 8009e78: 42a0 cmp r0, r4
- 8009e7a: d10b bne.n 8009e94 <_free_r+0x74>
- 8009e7c: 6820 ldr r0, [r4, #0]
- 8009e7e: 4401 add r1, r0
- 8009e80: 1858 adds r0, r3, r1
- 8009e82: 4282 cmp r2, r0
- 8009e84: 6019 str r1, [r3, #0]
- 8009e86: d1dd bne.n 8009e44 <_free_r+0x24>
- 8009e88: 6810 ldr r0, [r2, #0]
- 8009e8a: 6852 ldr r2, [r2, #4]
- 8009e8c: 605a str r2, [r3, #4]
- 8009e8e: 4401 add r1, r0
- 8009e90: 6019 str r1, [r3, #0]
- 8009e92: e7d7 b.n 8009e44 <_free_r+0x24>
- 8009e94: d902 bls.n 8009e9c <_free_r+0x7c>
- 8009e96: 230c movs r3, #12
- 8009e98: 602b str r3, [r5, #0]
- 8009e9a: e7d3 b.n 8009e44 <_free_r+0x24>
- 8009e9c: 6820 ldr r0, [r4, #0]
- 8009e9e: 1821 adds r1, r4, r0
- 8009ea0: 428a cmp r2, r1
- 8009ea2: bf04 itt eq
- 8009ea4: 6811 ldreq r1, [r2, #0]
- 8009ea6: 6852 ldreq r2, [r2, #4]
- 8009ea8: 6062 str r2, [r4, #4]
- 8009eaa: bf04 itt eq
- 8009eac: 1809 addeq r1, r1, r0
- 8009eae: 6021 streq r1, [r4, #0]
- 8009eb0: 605c str r4, [r3, #4]
- 8009eb2: e7c7 b.n 8009e44 <_free_r+0x24>
- 8009eb4: bd38 pop {r3, r4, r5, pc}
- 8009eb6: bf00 nop
- 8009eb8: 20000eb0 .word 0x20000eb0
-
-08009ebc <_malloc_r>:
- 8009ebc: b570 push {r4, r5, r6, lr}
- 8009ebe: 1ccd adds r5, r1, #3
- 8009ec0: f025 0503 bic.w r5, r5, #3
- 8009ec4: 3508 adds r5, #8
- 8009ec6: 2d0c cmp r5, #12
- 8009ec8: bf38 it cc
- 8009eca: 250c movcc r5, #12
- 8009ecc: 2d00 cmp r5, #0
- 8009ece: 4606 mov r6, r0
- 8009ed0: db01 blt.n 8009ed6 <_malloc_r+0x1a>
- 8009ed2: 42a9 cmp r1, r5
- 8009ed4: d903 bls.n 8009ede <_malloc_r+0x22>
- 8009ed6: 230c movs r3, #12
- 8009ed8: 6033 str r3, [r6, #0]
- 8009eda: 2000 movs r0, #0
- 8009edc: bd70 pop {r4, r5, r6, pc}
- 8009ede: f000 f85f bl 8009fa0 <__malloc_lock>
- 8009ee2: 4a21 ldr r2, [pc, #132] ; (8009f68 <_malloc_r+0xac>)
- 8009ee4: 6814 ldr r4, [r2, #0]
- 8009ee6: 4621 mov r1, r4
- 8009ee8: b991 cbnz r1, 8009f10 <_malloc_r+0x54>
- 8009eea: 4c20 ldr r4, [pc, #128] ; (8009f6c <_malloc_r+0xb0>)
- 8009eec: 6823 ldr r3, [r4, #0]
- 8009eee: b91b cbnz r3, 8009ef8 <_malloc_r+0x3c>
- 8009ef0: 4630 mov r0, r6
- 8009ef2: f000 f845 bl 8009f80 <_sbrk_r>
- 8009ef6: 6020 str r0, [r4, #0]
- 8009ef8: 4629 mov r1, r5
- 8009efa: 4630 mov r0, r6
- 8009efc: f000 f840 bl 8009f80 <_sbrk_r>
- 8009f00: 1c43 adds r3, r0, #1
- 8009f02: d124 bne.n 8009f4e <_malloc_r+0x92>
- 8009f04: 230c movs r3, #12
- 8009f06: 6033 str r3, [r6, #0]
- 8009f08: 4630 mov r0, r6
- 8009f0a: f000 f84a bl 8009fa2 <__malloc_unlock>
- 8009f0e: e7e4 b.n 8009eda <_malloc_r+0x1e>
- 8009f10: 680b ldr r3, [r1, #0]
- 8009f12: 1b5b subs r3, r3, r5
- 8009f14: d418 bmi.n 8009f48 <_malloc_r+0x8c>
- 8009f16: 2b0b cmp r3, #11
- 8009f18: d90f bls.n 8009f3a <_malloc_r+0x7e>
- 8009f1a: 600b str r3, [r1, #0]
- 8009f1c: 50cd str r5, [r1, r3]
- 8009f1e: 18cc adds r4, r1, r3
- 8009f20: 4630 mov r0, r6
- 8009f22: f000 f83e bl 8009fa2 <__malloc_unlock>
- 8009f26: f104 000b add.w r0, r4, #11
- 8009f2a: 1d23 adds r3, r4, #4
- 8009f2c: f020 0007 bic.w r0, r0, #7
- 8009f30: 1ac3 subs r3, r0, r3
- 8009f32: d0d3 beq.n 8009edc <_malloc_r+0x20>
- 8009f34: 425a negs r2, r3
- 8009f36: 50e2 str r2, [r4, r3]
- 8009f38: e7d0 b.n 8009edc <_malloc_r+0x20>
- 8009f3a: 428c cmp r4, r1
- 8009f3c: 684b ldr r3, [r1, #4]
- 8009f3e: bf16 itet ne
- 8009f40: 6063 strne r3, [r4, #4]
- 8009f42: 6013 streq r3, [r2, #0]
- 8009f44: 460c movne r4, r1
- 8009f46: e7eb b.n 8009f20 <_malloc_r+0x64>
- 8009f48: 460c mov r4, r1
- 8009f4a: 6849 ldr r1, [r1, #4]
- 8009f4c: e7cc b.n 8009ee8 <_malloc_r+0x2c>
- 8009f4e: 1cc4 adds r4, r0, #3
- 8009f50: f024 0403 bic.w r4, r4, #3
- 8009f54: 42a0 cmp r0, r4
- 8009f56: d005 beq.n 8009f64 <_malloc_r+0xa8>
- 8009f58: 1a21 subs r1, r4, r0
- 8009f5a: 4630 mov r0, r6
- 8009f5c: f000 f810 bl 8009f80 <_sbrk_r>
- 8009f60: 3001 adds r0, #1
- 8009f62: d0cf beq.n 8009f04 <_malloc_r+0x48>
- 8009f64: 6025 str r5, [r4, #0]
- 8009f66: e7db b.n 8009f20 <_malloc_r+0x64>
- 8009f68: 20000eb0 .word 0x20000eb0
- 8009f6c: 20000eb4 .word 0x20000eb4
-
-08009f70 <_malloc_usable_size_r>:
- 8009f70: f851 3c04 ldr.w r3, [r1, #-4]
- 8009f74: 1f18 subs r0, r3, #4
- 8009f76: 2b00 cmp r3, #0
- 8009f78: bfbc itt lt
- 8009f7a: 580b ldrlt r3, [r1, r0]
- 8009f7c: 18c0 addlt r0, r0, r3
- 8009f7e: 4770 bx lr
-
-08009f80 <_sbrk_r>:
- 8009f80: b538 push {r3, r4, r5, lr}
- 8009f82: 4c06 ldr r4, [pc, #24] ; (8009f9c <_sbrk_r+0x1c>)
- 8009f84: 2300 movs r3, #0
- 8009f86: 4605 mov r5, r0
- 8009f88: 4608 mov r0, r1
- 8009f8a: 6023 str r3, [r4, #0]
- 8009f8c: f7fc f822 bl 8005fd4 <_sbrk>
- 8009f90: 1c43 adds r3, r0, #1
- 8009f92: d102 bne.n 8009f9a <_sbrk_r+0x1a>
- 8009f94: 6823 ldr r3, [r4, #0]
- 8009f96: b103 cbz r3, 8009f9a <_sbrk_r+0x1a>
- 8009f98: 602b str r3, [r5, #0]
- 8009f9a: bd38 pop {r3, r4, r5, pc}
- 8009f9c: 20000ebc .word 0x20000ebc
-
-08009fa0 <__malloc_lock>:
- 8009fa0: 4770 bx lr
-
-08009fa2 <__malloc_unlock>:
- 8009fa2: 4770 bx lr
-
-08009fa4 <_init>:
- 8009fa4: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8009fa6: bf00 nop
- 8009fa8: bcf8 pop {r3, r4, r5, r6, r7}
- 8009faa: bc08 pop {r3}
- 8009fac: 469e mov lr, r3
- 8009fae: 4770 bx lr
-
-08009fb0 <_fini>:
- 8009fb0: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8009fb2: bf00 nop
- 8009fb4: bcf8 pop {r3, r4, r5, r6, r7}
- 8009fb6: bc08 pop {r3}
- 8009fb8: 469e mov lr, r3
- 8009fba: 4770 bx lr
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-ELF_SRCS :=
-C_UPPER_SRCS :=
-CXX_SRCS :=
-C++_SRCS :=
-OBJ_SRCS :=
-S_SRCS :=
-CC_SRCS :=
-C_SRCS :=
-CPP_SRCS :=
-S_UPPER_SRCS :=
-O_SRCS :=
-CC_DEPS :=
-SIZE_OUTPUT :=
-OBJDUMP_LIST :=
-C++_DEPS :=
-EXECUTABLES :=
-OBJS :=
-C_UPPER_DEPS :=
-CXX_DEPS :=
-C_DEPS :=
-CPP_DEPS :=
-
-# Every subdirectory with source files must be described here
-SUBDIRS := \
-Core/Src \
-Core/Startup \
-Drivers/STM32F7xx_HAL_Driver/Src \
-
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="system_reset"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_0" value="Enabled=true:Address=0x20000344:Access=Read/Write:Size=Byte:Function=Data Value + PC"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_1" value="Enabled=true:Address=left_velocity:Access=Read/Write:Size=Word:Function=Data Value"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_2" value="Enabled=false:Address=0x0:Access=Read/Write:Size=Word:Function=Data Value"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_3" value="Enabled=false:Address=0x0:Access=Read/Write:Size=Word:Function=Data Value"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.itmports" value="1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1:1"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.itmports_priv" value="1:1:1:1"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.pc_sample" value="1:128"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.timestamps" value="1:1"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.trace_events" value="Cpi=1:Exc=0:Sleep=0:Lsu=0:Fold=0:Exetrc=0"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"> <gdbmemoryBlockExpression address="0" label="left_velocity"/> </memoryBlockExpressionList> "/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>
Mcu.Pin13=PD15
Mcu.Pin14=PC6
Mcu.Pin15=PC7
-Mcu.Pin16=PB3
-Mcu.Pin17=VP_SYS_VS_Systick
-Mcu.Pin18=VP_TIM3_VS_ClockSourceINT
-Mcu.Pin19=VP_TIM4_VS_ClockSourceINT
+Mcu.Pin16=PA13
+Mcu.Pin17=PA14
+Mcu.Pin18=PB3
+Mcu.Pin19=VP_SYS_VS_Systick
Mcu.Pin2=PA0/WKUP
-Mcu.Pin20=VP_TIM6_VS_ClockSourceINT
+Mcu.Pin20=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin21=VP_TIM4_VS_ClockSourceINT
+Mcu.Pin22=VP_TIM6_VS_ClockSourceINT
Mcu.Pin3=PA1
Mcu.Pin4=PA3
Mcu.Pin5=PA5
Mcu.Pin7=PF12
Mcu.Pin8=PF13
Mcu.Pin9=PF14
-Mcu.PinsNb=21
+Mcu.PinsNb=23
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F767ZITx
PA1.GPIO_Label=encoder_sx2
PA1.Locked=true
PA1.Signal=S_TIM5_CH2
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
PA3.GPIOParameters=GPIO_Label
PA3.GPIO_Label=current1
PA3.Locked=true
TIM3.IPParameters=Prescaler,Period
TIM3.IPParametersWithoutCheck=Period
TIM3.Period=159
-TIM3.Prescaler=9999
+TIM3.Prescaler=999
TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
TIM4.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
TIM4.IPParameters=Channel-PWM Generation4 CH4,Channel-PWM Generation3 CH3,Period
+++ /dev/null
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-USER_OBJS :=
-
-LIBS :=
-
+++ /dev/null
-
-uart_test.elf: file format elf32-littlearm
-
-Sections:
-Idx Name Size VMA LMA File off Algn
- 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 00003740 080001f8 080001f8 000101f8 2**2
- CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000018 08003938 08003938 00013938 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 08003950 08003950 0002000c 2**0
- CONTENTS
- 4 .ARM 00000008 08003950 08003950 00013950 2**2
- CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 08003958 08003958 0002000c 2**0
- CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000004 08003958 08003958 00013958 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 0800395c 0800395c 0001395c 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 8 .data 0000000c 20000000 08003960 00020000 2**2
- CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 00000104 2000000c 0800396c 0002000c 2**2
- ALLOC
- 10 ._user_heap_stack 00000600 20000110 0800396c 00020110 2**0
- ALLOC
- 11 .ARM.attributes 0000002e 00000000 00000000 0002000c 2**0
- CONTENTS, READONLY
- 12 .debug_info 0000bff1 00000000 00000000 0002003a 2**0
- CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 000019c5 00000000 00000000 0002c02b 2**0
- CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000c60 00000000 00000000 0002d9f0 2**3
- CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 00000b88 00000000 00000000 0002e650 2**3
- CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 00025f5e 00000000 00000000 0002f1d8 2**0
- CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 00008ef8 00000000 00000000 00055136 2**0
- CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000f0c82 00000000 00000000 0005e02e 2**0
- CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 0014ecb0 2**0
- CONTENTS, READONLY
- 20 .debug_frame 00003400 00000000 00000000 0014ed2c 2**2
- CONTENTS, READONLY, DEBUGGING
-
-Disassembly of section .text:
-
-080001f8 <__do_global_dtors_aux>:
- 80001f8: b510 push {r4, lr}
- 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
- 80001fc: 7823 ldrb r3, [r4, #0]
- 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
- 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
- 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
- 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
- 8000206: f3af 8000 nop.w
- 800020a: 2301 movs r3, #1
- 800020c: 7023 strb r3, [r4, #0]
- 800020e: bd10 pop {r4, pc}
- 8000210: 2000000c .word 0x2000000c
- 8000214: 00000000 .word 0x00000000
- 8000218: 08003920 .word 0x08003920
-
-0800021c <frame_dummy>:
- 800021c: b508 push {r3, lr}
- 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
- 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
- 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
- 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
- 8000226: f3af 8000 nop.w
- 800022a: bd08 pop {r3, pc}
- 800022c: 00000000 .word 0x00000000
- 8000230: 20000010 .word 0x20000010
- 8000234: 08003920 .word 0x08003920
-
-08000238 <__aeabi_uldivmod>:
- 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
- 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
- 800023c: 2900 cmp r1, #0
- 800023e: bf08 it eq
- 8000240: 2800 cmpeq r0, #0
- 8000242: bf1c itt ne
- 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
- 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
- 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0>
- 8000250: f1ad 0c08 sub.w ip, sp, #8
- 8000254: e96d ce04 strd ip, lr, [sp, #-16]!
- 8000258: f000 f806 bl 8000268 <__udivmoddi4>
- 800025c: f8dd e004 ldr.w lr, [sp, #4]
- 8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
- 8000264: b004 add sp, #16
- 8000266: 4770 bx lr
-
-08000268 <__udivmoddi4>:
- 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 800026c: 9e08 ldr r6, [sp, #32]
- 800026e: 4604 mov r4, r0
- 8000270: 4688 mov r8, r1
- 8000272: 2b00 cmp r3, #0
- 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6>
- 8000276: 428a cmp r2, r1
- 8000278: 4615 mov r5, r2
- 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4>
- 800027c: fab2 f282 clz r2, r2
- 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e>
- 8000282: f1c2 0720 rsb r7, r2, #32
- 8000286: fa01 f302 lsl.w r3, r1, r2
- 800028a: fa20 f707 lsr.w r7, r0, r7
- 800028e: 4095 lsls r5, r2
- 8000290: ea47 0803 orr.w r8, r7, r3
- 8000294: 4094 lsls r4, r2
- 8000296: ea4f 4e15 mov.w lr, r5, lsr #16
- 800029a: 0c23 lsrs r3, r4, #16
- 800029c: fbb8 f7fe udiv r7, r8, lr
- 80002a0: fa1f fc85 uxth.w ip, r5
- 80002a4: fb0e 8817 mls r8, lr, r7, r8
- 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16
- 80002ac: fb07 f10c mul.w r1, r7, ip
- 80002b0: 4299 cmp r1, r3
- 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60>
- 80002b4: 18eb adds r3, r5, r3
- 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
- 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c>
- 80002be: 4299 cmp r1, r3
- 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c>
- 80002c4: 3f02 subs r7, #2
- 80002c6: 442b add r3, r5
- 80002c8: 1a5b subs r3, r3, r1
- 80002ca: b2a4 uxth r4, r4
- 80002cc: fbb3 f0fe udiv r0, r3, lr
- 80002d0: fb0e 3310 mls r3, lr, r0, r3
- 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16
- 80002d8: fb00 fc0c mul.w ip, r0, ip
- 80002dc: 45a4 cmp ip, r4
- 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c>
- 80002e0: 192c adds r4, r5, r4
- 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290>
- 80002ea: 45a4 cmp ip, r4
- 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290>
- 80002f0: 3802 subs r0, #2
- 80002f2: 442c add r4, r5
- 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16
- 80002f8: eba4 040c sub.w r4, r4, ip
- 80002fc: 2700 movs r7, #0
- 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0>
- 8000300: 40d4 lsrs r4, r2
- 8000302: 2300 movs r3, #0
- 8000304: e9c6 4300 strd r4, r3, [r6]
- 8000308: 4639 mov r1, r7
- 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 800030e: 428b cmp r3, r1
- 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe>
- 8000312: 2e00 cmp r6, #0
- 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286>
- 8000318: 2700 movs r7, #0
- 800031a: e9c6 0100 strd r0, r1, [r6]
- 800031e: 4638 mov r0, r7
- 8000320: 4639 mov r1, r7
- 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000326: fab3 f783 clz r7, r3
- 800032a: 2f00 cmp r7, #0
- 800032c: d147 bne.n 80003be <__udivmoddi4+0x156>
- 800032e: 428b cmp r3, r1
- 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0>
- 8000332: 4282 cmp r2, r0
- 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4>
- 8000338: 1a84 subs r4, r0, r2
- 800033a: eb61 0303 sbc.w r3, r1, r3
- 800033e: 2001 movs r0, #1
- 8000340: 4698 mov r8, r3
- 8000342: 2e00 cmp r6, #0
- 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0>
- 8000346: e9c6 4800 strd r4, r8, [r6]
- 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0>
- 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8>
- 800034e: deff udf #255 ; 0xff
- 8000350: fab2 f282 clz r2, r2
- 8000354: 2a00 cmp r2, #0
- 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210>
- 800035a: 1b49 subs r1, r1, r5
- 800035c: ea4f 4e15 mov.w lr, r5, lsr #16
- 8000360: fa1f f885 uxth.w r8, r5
- 8000364: 2701 movs r7, #1
- 8000366: fbb1 fcfe udiv ip, r1, lr
- 800036a: 0c23 lsrs r3, r4, #16
- 800036c: fb0e 111c mls r1, lr, ip, r1
- 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16
- 8000374: fb08 f10c mul.w r1, r8, ip
- 8000378: 4299 cmp r1, r3
- 800037a: d907 bls.n 800038c <__udivmoddi4+0x124>
- 800037c: 18eb adds r3, r5, r3
- 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
- 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122>
- 8000384: 4299 cmp r1, r3
- 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc>
- 800038a: 4684 mov ip, r0
- 800038c: 1a59 subs r1, r3, r1
- 800038e: b2a3 uxth r3, r4
- 8000390: fbb1 f0fe udiv r0, r1, lr
- 8000394: fb0e 1410 mls r4, lr, r0, r1
- 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16
- 800039c: fb08 f800 mul.w r8, r8, r0
- 80003a0: 45a0 cmp r8, r4
- 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c>
- 80003a4: 192c adds r4, r5, r4
- 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a>
- 80003ac: 45a0 cmp r8, r4
- 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6>
- 80003b2: 4618 mov r0, r3
- 80003b4: eba4 0408 sub.w r4, r4, r8
- 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16
- 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96>
- 80003be: f1c7 0c20 rsb ip, r7, #32
- 80003c2: 40bb lsls r3, r7
- 80003c4: fa22 fe0c lsr.w lr, r2, ip
- 80003c8: ea4e 0e03 orr.w lr, lr, r3
- 80003cc: fa01 f407 lsl.w r4, r1, r7
- 80003d0: fa20 f50c lsr.w r5, r0, ip
- 80003d4: fa21 f30c lsr.w r3, r1, ip
- 80003d8: ea4f 481e mov.w r8, lr, lsr #16
- 80003dc: 4325 orrs r5, r4
- 80003de: fbb3 f9f8 udiv r9, r3, r8
- 80003e2: 0c2c lsrs r4, r5, #16
- 80003e4: fb08 3319 mls r3, r8, r9, r3
- 80003e8: fa1f fa8e uxth.w sl, lr
- 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16
- 80003f0: fb09 f40a mul.w r4, r9, sl
- 80003f4: 429c cmp r4, r3
- 80003f6: fa02 f207 lsl.w r2, r2, r7
- 80003fa: fa00 f107 lsl.w r1, r0, r7
- 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0>
- 8000400: eb1e 0303 adds.w r3, lr, r3
- 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
- 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2>
- 800040c: 429c cmp r4, r3
- 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2>
- 8000412: f1a9 0902 sub.w r9, r9, #2
- 8000416: 4473 add r3, lr
- 8000418: 1b1b subs r3, r3, r4
- 800041a: b2ad uxth r5, r5
- 800041c: fbb3 f0f8 udiv r0, r3, r8
- 8000420: fb08 3310 mls r3, r8, r0, r3
- 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16
- 8000428: fb00 fa0a mul.w sl, r0, sl
- 800042c: 45a2 cmp sl, r4
- 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da>
- 8000430: eb1e 0404 adds.w r4, lr, r4
- 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
- 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa>
- 800043a: 45a2 cmp sl, r4
- 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa>
- 800043e: 3802 subs r0, #2
- 8000440: 4474 add r4, lr
- 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16
- 8000446: fba0 8902 umull r8, r9, r0, r2
- 800044a: eba4 040a sub.w r4, r4, sl
- 800044e: 454c cmp r4, r9
- 8000450: 46c2 mov sl, r8
- 8000452: 464b mov r3, r9
- 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298>
- 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294>
- 8000458: 2e00 cmp r6, #0
- 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8>
- 800045c: ebb1 050a subs.w r5, r1, sl
- 8000460: eb64 0403 sbc.w r4, r4, r3
- 8000464: fa04 fc0c lsl.w ip, r4, ip
- 8000468: 40fd lsrs r5, r7
- 800046a: 40fc lsrs r4, r7
- 800046c: ea4c 0505 orr.w r5, ip, r5
- 8000470: e9c6 5400 strd r5, r4, [r6]
- 8000474: 2700 movs r7, #0
- 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0>
- 8000478: f1c2 0320 rsb r3, r2, #32
- 800047c: fa20 f703 lsr.w r7, r0, r3
- 8000480: 4095 lsls r5, r2
- 8000482: fa01 f002 lsl.w r0, r1, r2
- 8000486: fa21 f303 lsr.w r3, r1, r3
- 800048a: ea4f 4e15 mov.w lr, r5, lsr #16
- 800048e: 4338 orrs r0, r7
- 8000490: 0c01 lsrs r1, r0, #16
- 8000492: fbb3 f7fe udiv r7, r3, lr
- 8000496: fa1f f885 uxth.w r8, r5
- 800049a: fb0e 3317 mls r3, lr, r7, r3
- 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004a2: fb07 f308 mul.w r3, r7, r8
- 80004a6: 428b cmp r3, r1
- 80004a8: fa04 f402 lsl.w r4, r4, r2
- 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256>
- 80004ae: 1869 adds r1, r5, r1
- 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
- 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae>
- 80004b6: 428b cmp r3, r1
- 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae>
- 80004ba: 3f02 subs r7, #2
- 80004bc: 4429 add r1, r5
- 80004be: 1acb subs r3, r1, r3
- 80004c0: b281 uxth r1, r0
- 80004c2: fbb3 f0fe udiv r0, r3, lr
- 80004c6: fb0e 3310 mls r3, lr, r0, r3
- 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16
- 80004ce: fb00 f308 mul.w r3, r0, r8
- 80004d2: 428b cmp r3, r1
- 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e>
- 80004d6: 1869 adds r1, r5, r1
- 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
- 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6>
- 80004de: 428b cmp r3, r1
- 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6>
- 80004e2: 3802 subs r0, #2
- 80004e4: 4429 add r1, r5
- 80004e6: 1ac9 subs r1, r1, r3
- 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16
- 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe>
- 80004ee: 4637 mov r7, r6
- 80004f0: 4630 mov r0, r6
- 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0>
- 80004f4: 4607 mov r7, r0
- 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60>
- 80004f8: 4618 mov r0, r3
- 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c>
- 80004fc: 4541 cmp r1, r8
- 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0>
- 8000500: ebb8 0a02 subs.w sl, r8, r2
- 8000504: eb69 020e sbc.w r2, r9, lr
- 8000508: 3801 subs r0, #1
- 800050a: 4613 mov r3, r2
- 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0>
- 800050e: 4660 mov r0, ip
- 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e>
- 8000512: 4618 mov r0, r3
- 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da>
- 8000516: 4667 mov r7, ip
- 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256>
- 800051a: 4681 mov r9, r0
- 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0>
- 800051e: 3802 subs r0, #2
- 8000520: 442c add r4, r5
- 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c>
- 8000524: f1ac 0c02 sub.w ip, ip, #2
- 8000528: 442b add r3, r5
- 800052a: e72f b.n 800038c <__udivmoddi4+0x124>
- 800052c: 4638 mov r0, r7
- 800052e: e708 b.n 8000342 <__udivmoddi4+0xda>
- 8000530: 4637 mov r7, r6
- 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0>
-
-08000534 <__aeabi_idiv0>:
- 8000534: 4770 bx lr
- 8000536: bf00 nop
-
-08000538 <main>:
-/**
- * @brief The application entry point.
- * @retval int
- */
-int main(void)
-{
- 8000538: b580 push {r7, lr}
- 800053a: af00 add r7, sp, #0
-
-
- /* MCU Configuration--------------------------------------------------------*/
-
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
- 800053c: f000 fabd bl 8000aba <HAL_Init>
- /* USER CODE BEGIN Init */
-
- /* USER CODE END Init */
-
- /* Configure the system clock */
- SystemClock_Config();
- 8000540: f000 f832 bl 80005a8 <SystemClock_Config>
- /* USER CODE BEGIN SysInit */
-
- /* USER CODE END SysInit */
-
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- 8000544: f000 f92a bl 800079c <MX_GPIO_Init>
- MX_USART6_UART_Init();
- 8000548: f000 f8f6 bl 8000738 <MX_USART6_UART_Init>
- MX_TIM3_Init();
- 800054c: f000 f8a6 bl 800069c <MX_TIM3_Init>
- /* USER CODE BEGIN 2 */
-
- odom_msg.angular_velocity = 0.2;
- 8000550: 4b0d ldr r3, [pc, #52] ; (8000588 <main+0x50>)
- 8000552: 4a0e ldr r2, [pc, #56] ; (800058c <main+0x54>)
- 8000554: 601a str r2, [r3, #0]
- odom_msg.linear_velocity = 1.5;
- 8000556: 4b0c ldr r3, [pc, #48] ; (8000588 <main+0x50>)
- 8000558: f04f 527f mov.w r2, #1069547520 ; 0x3fc00000
- 800055c: 605a str r2, [r3, #4]
- odom_msg.delta_time = 2.6;
- 800055e: 4b0a ldr r3, [pc, #40] ; (8000588 <main+0x50>)
- 8000560: 4a0b ldr r2, [pc, #44] ; (8000590 <main+0x58>)
- 8000562: 609a str r2, [r3, #8]
-
- tx_buffer = (uint8_t *) &odom_msg;
- 8000564: 4b0b ldr r3, [pc, #44] ; (8000594 <main+0x5c>)
- 8000566: 4a08 ldr r2, [pc, #32] ; (8000588 <main+0x50>)
- 8000568: 601a str r2, [r3, #0]
- rx_buffer = (uint8_t*) &vel_msg;
- 800056a: 4b0b ldr r3, [pc, #44] ; (8000598 <main+0x60>)
- 800056c: 4a0b ldr r2, [pc, #44] ; (800059c <main+0x64>)
- 800056e: 601a str r2, [r3, #0]
-
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
- 8000570: 4b09 ldr r3, [pc, #36] ; (8000598 <main+0x60>)
- 8000572: 681b ldr r3, [r3, #0]
- 8000574: 2208 movs r2, #8
- 8000576: 4619 mov r1, r3
- 8000578: 4809 ldr r0, [pc, #36] ; (80005a0 <main+0x68>)
- 800057a: f002 fb2b bl 8002bd4 <HAL_UART_Receive_IT>
-
- HAL_TIM_Base_Start_IT(&htim3);
- 800057e: 4809 ldr r0, [pc, #36] ; (80005a4 <main+0x6c>)
- 8000580: f001 fe68 bl 8002254 <HAL_TIM_Base_Start_IT>
-
- /* USER CODE END 2 */
-
- /* Infinite loop */
- /* USER CODE BEGIN WHILE */
- while (1) {
- 8000584: e7fe b.n 8000584 <main+0x4c>
- 8000586: bf00 nop
- 8000588: 20000030 .word 0x20000030
- 800058c: 3e4ccccd .word 0x3e4ccccd
- 8000590: 40266666 .word 0x40266666
- 8000594: 20000080 .word 0x20000080
- 8000598: 2000007c .word 0x2000007c
- 800059c: 20000028 .word 0x20000028
- 80005a0: 20000084 .word 0x20000084
- 80005a4: 2000003c .word 0x2000003c
-
-080005a8 <SystemClock_Config>:
-/**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void)
-{
- 80005a8: b580 push {r7, lr}
- 80005aa: b0b8 sub sp, #224 ; 0xe0
- 80005ac: af00 add r7, sp, #0
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 80005ae: f107 03ac add.w r3, r7, #172 ; 0xac
- 80005b2: 2234 movs r2, #52 ; 0x34
- 80005b4: 2100 movs r1, #0
- 80005b6: 4618 mov r0, r3
- 80005b8: f003 f9aa bl 8003910 <memset>
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 80005bc: f107 0398 add.w r3, r7, #152 ; 0x98
- 80005c0: 2200 movs r2, #0
- 80005c2: 601a str r2, [r3, #0]
- 80005c4: 605a str r2, [r3, #4]
- 80005c6: 609a str r2, [r3, #8]
- 80005c8: 60da str r2, [r3, #12]
- 80005ca: 611a str r2, [r3, #16]
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
- 80005cc: f107 0308 add.w r3, r7, #8
- 80005d0: 2290 movs r2, #144 ; 0x90
- 80005d2: 2100 movs r1, #0
- 80005d4: 4618 mov r0, r3
- 80005d6: f003 f99b bl 8003910 <memset>
-
- /** Configure the main internal regulator output voltage
- */
- __HAL_RCC_PWR_CLK_ENABLE();
- 80005da: 4b2e ldr r3, [pc, #184] ; (8000694 <SystemClock_Config+0xec>)
- 80005dc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80005de: 4a2d ldr r2, [pc, #180] ; (8000694 <SystemClock_Config+0xec>)
- 80005e0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80005e4: 6413 str r3, [r2, #64] ; 0x40
- 80005e6: 4b2b ldr r3, [pc, #172] ; (8000694 <SystemClock_Config+0xec>)
- 80005e8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80005ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80005ee: 607b str r3, [r7, #4]
- 80005f0: 687b ldr r3, [r7, #4]
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 80005f2: 4b29 ldr r3, [pc, #164] ; (8000698 <SystemClock_Config+0xf0>)
- 80005f4: 681b ldr r3, [r3, #0]
- 80005f6: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 80005fa: 4a27 ldr r2, [pc, #156] ; (8000698 <SystemClock_Config+0xf0>)
- 80005fc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000600: 6013 str r3, [r2, #0]
- 8000602: 4b25 ldr r3, [pc, #148] ; (8000698 <SystemClock_Config+0xf0>)
- 8000604: 681b ldr r3, [r3, #0]
- 8000606: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 800060a: 603b str r3, [r7, #0]
- 800060c: 683b ldr r3, [r7, #0]
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 800060e: 2302 movs r3, #2
- 8000610: f8c7 30ac str.w r3, [r7, #172] ; 0xac
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000614: 2301 movs r3, #1
- 8000616: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 800061a: 2310 movs r3, #16
- 800061c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8000620: 2300 movs r3, #0
- 8000622: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 8000626: f107 03ac add.w r3, r7, #172 ; 0xac
- 800062a: 4618 mov r0, r3
- 800062c: f000 fd80 bl 8001130 <HAL_RCC_OscConfig>
- 8000630: 4603 mov r3, r0
- 8000632: 2b00 cmp r3, #0
- 8000634: d001 beq.n 800063a <SystemClock_Config+0x92>
- {
- Error_Handler();
- 8000636: f000 f901 bl 800083c <Error_Handler>
- }
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 800063a: 230f movs r3, #15
- 800063c: f8c7 3098 str.w r3, [r7, #152] ; 0x98
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 8000640: 2300 movs r3, #0
- 8000642: f8c7 309c str.w r3, [r7, #156] ; 0x9c
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000646: 2300 movs r3, #0
- 8000648: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 800064c: 2300 movs r3, #0
- 800064e: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8000652: 2300 movs r3, #0
- 8000654: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
-
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 8000658: f107 0398 add.w r3, r7, #152 ; 0x98
- 800065c: 2100 movs r1, #0
- 800065e: 4618 mov r0, r3
- 8000660: f000 ffd8 bl 8001614 <HAL_RCC_ClockConfig>
- 8000664: 4603 mov r3, r0
- 8000666: 2b00 cmp r3, #0
- 8000668: d001 beq.n 800066e <SystemClock_Config+0xc6>
- {
- Error_Handler();
- 800066a: f000 f8e7 bl 800083c <Error_Handler>
- }
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
- 800066e: f44f 6300 mov.w r3, #2048 ; 0x800
- 8000672: 60bb str r3, [r7, #8]
- PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
- 8000674: 2300 movs r3, #0
- 8000676: 663b str r3, [r7, #96] ; 0x60
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
- 8000678: f107 0308 add.w r3, r7, #8
- 800067c: 4618 mov r0, r3
- 800067e: f001 f997 bl 80019b0 <HAL_RCCEx_PeriphCLKConfig>
- 8000682: 4603 mov r3, r0
- 8000684: 2b00 cmp r3, #0
- 8000686: d001 beq.n 800068c <SystemClock_Config+0xe4>
- {
- Error_Handler();
- 8000688: f000 f8d8 bl 800083c <Error_Handler>
- }
-}
- 800068c: bf00 nop
- 800068e: 37e0 adds r7, #224 ; 0xe0
- 8000690: 46bd mov sp, r7
- 8000692: bd80 pop {r7, pc}
- 8000694: 40023800 .word 0x40023800
- 8000698: 40007000 .word 0x40007000
-
-0800069c <MX_TIM3_Init>:
- * @brief TIM3 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM3_Init(void)
-{
- 800069c: b580 push {r7, lr}
- 800069e: b088 sub sp, #32
- 80006a0: af00 add r7, sp, #0
-
- /* USER CODE BEGIN TIM3_Init 0 */
-
- /* USER CODE END TIM3_Init 0 */
-
- TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 80006a2: f107 0310 add.w r3, r7, #16
- 80006a6: 2200 movs r2, #0
- 80006a8: 601a str r2, [r3, #0]
- 80006aa: 605a str r2, [r3, #4]
- 80006ac: 609a str r2, [r3, #8]
- 80006ae: 60da str r2, [r3, #12]
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 80006b0: 1d3b adds r3, r7, #4
- 80006b2: 2200 movs r2, #0
- 80006b4: 601a str r2, [r3, #0]
- 80006b6: 605a str r2, [r3, #4]
- 80006b8: 609a str r2, [r3, #8]
-
- /* USER CODE BEGIN TIM3_Init 1 */
-
- /* USER CODE END TIM3_Init 1 */
- htim3.Instance = TIM3;
- 80006ba: 4b1d ldr r3, [pc, #116] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006bc: 4a1d ldr r2, [pc, #116] ; (8000734 <MX_TIM3_Init+0x98>)
- 80006be: 601a str r2, [r3, #0]
- htim3.Init.Prescaler = 39999;
- 80006c0: 4b1b ldr r3, [pc, #108] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006c2: f649 423f movw r2, #39999 ; 0x9c3f
- 80006c6: 605a str r2, [r3, #4]
- htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
- 80006c8: 4b19 ldr r3, [pc, #100] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006ca: 2200 movs r2, #0
- 80006cc: 609a str r2, [r3, #8]
- htim3.Init.Period = 9;
- 80006ce: 4b18 ldr r3, [pc, #96] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006d0: 2209 movs r2, #9
- 80006d2: 60da str r2, [r3, #12]
- htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 80006d4: 4b16 ldr r3, [pc, #88] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006d6: 2200 movs r2, #0
- 80006d8: 611a str r2, [r3, #16]
- htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 80006da: 4b15 ldr r3, [pc, #84] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006dc: 2200 movs r2, #0
- 80006de: 619a str r2, [r3, #24]
- if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
- 80006e0: 4813 ldr r0, [pc, #76] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006e2: f001 fd8b bl 80021fc <HAL_TIM_Base_Init>
- 80006e6: 4603 mov r3, r0
- 80006e8: 2b00 cmp r3, #0
- 80006ea: d001 beq.n 80006f0 <MX_TIM3_Init+0x54>
- {
- Error_Handler();
- 80006ec: f000 f8a6 bl 800083c <Error_Handler>
- }
- sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 80006f0: f44f 5380 mov.w r3, #4096 ; 0x1000
- 80006f4: 613b str r3, [r7, #16]
- if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
- 80006f6: f107 0310 add.w r3, r7, #16
- 80006fa: 4619 mov r1, r3
- 80006fc: 480c ldr r0, [pc, #48] ; (8000730 <MX_TIM3_Init+0x94>)
- 80006fe: f001 fef3 bl 80024e8 <HAL_TIM_ConfigClockSource>
- 8000702: 4603 mov r3, r0
- 8000704: 2b00 cmp r3, #0
- 8000706: d001 beq.n 800070c <MX_TIM3_Init+0x70>
- {
- Error_Handler();
- 8000708: f000 f898 bl 800083c <Error_Handler>
- }
- sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 800070c: 2300 movs r3, #0
- 800070e: 607b str r3, [r7, #4]
- sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000710: 2300 movs r3, #0
- 8000712: 60fb str r3, [r7, #12]
- if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
- 8000714: 1d3b adds r3, r7, #4
- 8000716: 4619 mov r1, r3
- 8000718: 4805 ldr r0, [pc, #20] ; (8000730 <MX_TIM3_Init+0x94>)
- 800071a: f002 f901 bl 8002920 <HAL_TIMEx_MasterConfigSynchronization>
- 800071e: 4603 mov r3, r0
- 8000720: 2b00 cmp r3, #0
- 8000722: d001 beq.n 8000728 <MX_TIM3_Init+0x8c>
- {
- Error_Handler();
- 8000724: f000 f88a bl 800083c <Error_Handler>
- }
- /* USER CODE BEGIN TIM3_Init 2 */
-
- /* USER CODE END TIM3_Init 2 */
-
-}
- 8000728: bf00 nop
- 800072a: 3720 adds r7, #32
- 800072c: 46bd mov sp, r7
- 800072e: bd80 pop {r7, pc}
- 8000730: 2000003c .word 0x2000003c
- 8000734: 40000400 .word 0x40000400
-
-08000738 <MX_USART6_UART_Init>:
- * @brief USART6 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_USART6_UART_Init(void)
-{
- 8000738: b580 push {r7, lr}
- 800073a: af00 add r7, sp, #0
- /* USER CODE END USART6_Init 0 */
-
- /* USER CODE BEGIN USART6_Init 1 */
-
- /* USER CODE END USART6_Init 1 */
- huart6.Instance = USART6;
- 800073c: 4b15 ldr r3, [pc, #84] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 800073e: 4a16 ldr r2, [pc, #88] ; (8000798 <MX_USART6_UART_Init+0x60>)
- 8000740: 601a str r2, [r3, #0]
- huart6.Init.BaudRate = 115200;
- 8000742: 4b14 ldr r3, [pc, #80] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 8000744: f44f 32e1 mov.w r2, #115200 ; 0x1c200
- 8000748: 605a str r2, [r3, #4]
- huart6.Init.WordLength = UART_WORDLENGTH_9B;
- 800074a: 4b12 ldr r3, [pc, #72] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 800074c: f44f 5280 mov.w r2, #4096 ; 0x1000
- 8000750: 609a str r2, [r3, #8]
- huart6.Init.StopBits = UART_STOPBITS_1;
- 8000752: 4b10 ldr r3, [pc, #64] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 8000754: 2200 movs r2, #0
- 8000756: 60da str r2, [r3, #12]
- huart6.Init.Parity = UART_PARITY_ODD;
- 8000758: 4b0e ldr r3, [pc, #56] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 800075a: f44f 62c0 mov.w r2, #1536 ; 0x600
- 800075e: 611a str r2, [r3, #16]
- huart6.Init.Mode = UART_MODE_TX_RX;
- 8000760: 4b0c ldr r3, [pc, #48] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 8000762: 220c movs r2, #12
- 8000764: 615a str r2, [r3, #20]
- huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 8000766: 4b0b ldr r3, [pc, #44] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 8000768: 2200 movs r2, #0
- 800076a: 619a str r2, [r3, #24]
- huart6.Init.OverSampling = UART_OVERSAMPLING_16;
- 800076c: 4b09 ldr r3, [pc, #36] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 800076e: 2200 movs r2, #0
- 8000770: 61da str r2, [r3, #28]
- huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 8000772: 4b08 ldr r3, [pc, #32] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 8000774: 2200 movs r2, #0
- 8000776: 621a str r2, [r3, #32]
- huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 8000778: 4b06 ldr r3, [pc, #24] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 800077a: 2200 movs r2, #0
- 800077c: 625a str r2, [r3, #36] ; 0x24
- if (HAL_UART_Init(&huart6) != HAL_OK)
- 800077e: 4805 ldr r0, [pc, #20] ; (8000794 <MX_USART6_UART_Init+0x5c>)
- 8000780: f002 f948 bl 8002a14 <HAL_UART_Init>
- 8000784: 4603 mov r3, r0
- 8000786: 2b00 cmp r3, #0
- 8000788: d001 beq.n 800078e <MX_USART6_UART_Init+0x56>
- {
- Error_Handler();
- 800078a: f000 f857 bl 800083c <Error_Handler>
- }
- /* USER CODE BEGIN USART6_Init 2 */
-
- /* USER CODE END USART6_Init 2 */
-
-}
- 800078e: bf00 nop
- 8000790: bd80 pop {r7, pc}
- 8000792: bf00 nop
- 8000794: 20000084 .word 0x20000084
- 8000798: 40011400 .word 0x40011400
-
-0800079c <MX_GPIO_Init>:
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void)
-{
- 800079c: b480 push {r7}
- 800079e: b083 sub sp, #12
- 80007a0: af00 add r7, sp, #0
-
- /* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 80007a2: 4b09 ldr r3, [pc, #36] ; (80007c8 <MX_GPIO_Init+0x2c>)
- 80007a4: 6b1b ldr r3, [r3, #48] ; 0x30
- 80007a6: 4a08 ldr r2, [pc, #32] ; (80007c8 <MX_GPIO_Init+0x2c>)
- 80007a8: f043 0304 orr.w r3, r3, #4
- 80007ac: 6313 str r3, [r2, #48] ; 0x30
- 80007ae: 4b06 ldr r3, [pc, #24] ; (80007c8 <MX_GPIO_Init+0x2c>)
- 80007b0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80007b2: f003 0304 and.w r3, r3, #4
- 80007b6: 607b str r3, [r7, #4]
- 80007b8: 687b ldr r3, [r7, #4]
-
-}
- 80007ba: bf00 nop
- 80007bc: 370c adds r7, #12
- 80007be: 46bd mov sp, r7
- 80007c0: f85d 7b04 ldr.w r7, [sp], #4
- 80007c4: 4770 bx lr
- 80007c6: bf00 nop
- 80007c8: 40023800 .word 0x40023800
-
-080007cc <HAL_TIM_PeriodElapsedCallback>:
-
-/* USER CODE BEGIN 4 */
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
- 80007cc: b580 push {r7, lr}
- 80007ce: b082 sub sp, #8
- 80007d0: af00 add r7, sp, #0
- 80007d2: 6078 str r0, [r7, #4]
- if (htim->Instance == TIM3) {
- 80007d4: 687b ldr r3, [r7, #4]
- 80007d6: 681b ldr r3, [r3, #0]
- 80007d8: 4a06 ldr r2, [pc, #24] ; (80007f4 <HAL_TIM_PeriodElapsedCallback+0x28>)
- 80007da: 4293 cmp r3, r2
- 80007dc: d106 bne.n 80007ec <HAL_TIM_PeriodElapsedCallback+0x20>
- HAL_UART_Transmit(&huart6, tx_buffer, 12, 100);
- 80007de: 4b06 ldr r3, [pc, #24] ; (80007f8 <HAL_TIM_PeriodElapsedCallback+0x2c>)
- 80007e0: 6819 ldr r1, [r3, #0]
- 80007e2: 2364 movs r3, #100 ; 0x64
- 80007e4: 220c movs r2, #12
- 80007e6: 4805 ldr r0, [pc, #20] ; (80007fc <HAL_TIM_PeriodElapsedCallback+0x30>)
- 80007e8: f002 f962 bl 8002ab0 <HAL_UART_Transmit>
- }
-}
- 80007ec: bf00 nop
- 80007ee: 3708 adds r7, #8
- 80007f0: 46bd mov sp, r7
- 80007f2: bd80 pop {r7, pc}
- 80007f4: 40000400 .word 0x40000400
- 80007f8: 20000080 .word 0x20000080
- 80007fc: 20000084 .word 0x20000084
-
-08000800 <HAL_UART_RxCpltCallback>:
-
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {
- 8000800: b580 push {r7, lr}
- 8000802: b082 sub sp, #8
- 8000804: af00 add r7, sp, #0
- 8000806: 6078 str r0, [r7, #4]
- HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
- 8000808: 4b05 ldr r3, [pc, #20] ; (8000820 <HAL_UART_RxCpltCallback+0x20>)
- 800080a: 681b ldr r3, [r3, #0]
- 800080c: 2208 movs r2, #8
- 800080e: 4619 mov r1, r3
- 8000810: 4804 ldr r0, [pc, #16] ; (8000824 <HAL_UART_RxCpltCallback+0x24>)
- 8000812: f002 f9df bl 8002bd4 <HAL_UART_Receive_IT>
-}
- 8000816: bf00 nop
- 8000818: 3708 adds r7, #8
- 800081a: 46bd mov sp, r7
- 800081c: bd80 pop {r7, pc}
- 800081e: bf00 nop
- 8000820: 2000007c .word 0x2000007c
- 8000824: 20000084 .word 0x20000084
-
-08000828 <HAL_UART_ErrorCallback>:
-
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle){
- 8000828: b480 push {r7}
- 800082a: b083 sub sp, #12
- 800082c: af00 add r7, sp, #0
- 800082e: 6078 str r0, [r7, #4]
- //TODO
-}
- 8000830: bf00 nop
- 8000832: 370c adds r7, #12
- 8000834: 46bd mov sp, r7
- 8000836: f85d 7b04 ldr.w r7, [sp], #4
- 800083a: 4770 bx lr
-
-0800083c <Error_Handler>:
-/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void)
-{
- 800083c: b480 push {r7}
- 800083e: af00 add r7, sp, #0
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
-
- /* USER CODE END Error_Handler_Debug */
-}
- 8000840: bf00 nop
- 8000842: 46bd mov sp, r7
- 8000844: f85d 7b04 ldr.w r7, [sp], #4
- 8000848: 4770 bx lr
- ...
-
-0800084c <HAL_MspInit>:
-/* USER CODE END 0 */
-/**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- 800084c: b480 push {r7}
- 800084e: b083 sub sp, #12
- 8000850: af00 add r7, sp, #0
- /* USER CODE BEGIN MspInit 0 */
-
- /* USER CODE END MspInit 0 */
-
- __HAL_RCC_PWR_CLK_ENABLE();
- 8000852: 4b0f ldr r3, [pc, #60] ; (8000890 <HAL_MspInit+0x44>)
- 8000854: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000856: 4a0e ldr r2, [pc, #56] ; (8000890 <HAL_MspInit+0x44>)
- 8000858: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 800085c: 6413 str r3, [r2, #64] ; 0x40
- 800085e: 4b0c ldr r3, [pc, #48] ; (8000890 <HAL_MspInit+0x44>)
- 8000860: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000862: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000866: 607b str r3, [r7, #4]
- 8000868: 687b ldr r3, [r7, #4]
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 800086a: 4b09 ldr r3, [pc, #36] ; (8000890 <HAL_MspInit+0x44>)
- 800086c: 6c5b ldr r3, [r3, #68] ; 0x44
- 800086e: 4a08 ldr r2, [pc, #32] ; (8000890 <HAL_MspInit+0x44>)
- 8000870: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000874: 6453 str r3, [r2, #68] ; 0x44
- 8000876: 4b06 ldr r3, [pc, #24] ; (8000890 <HAL_MspInit+0x44>)
- 8000878: 6c5b ldr r3, [r3, #68] ; 0x44
- 800087a: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 800087e: 603b str r3, [r7, #0]
- 8000880: 683b ldr r3, [r7, #0]
- /* System interrupt init*/
-
- /* USER CODE BEGIN MspInit 1 */
-
- /* USER CODE END MspInit 1 */
-}
- 8000882: bf00 nop
- 8000884: 370c adds r7, #12
- 8000886: 46bd mov sp, r7
- 8000888: f85d 7b04 ldr.w r7, [sp], #4
- 800088c: 4770 bx lr
- 800088e: bf00 nop
- 8000890: 40023800 .word 0x40023800
-
-08000894 <HAL_TIM_Base_MspInit>:
-* This function configures the hardware resources used in this example
-* @param htim_base: TIM_Base handle pointer
-* @retval None
-*/
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
- 8000894: b580 push {r7, lr}
- 8000896: b084 sub sp, #16
- 8000898: af00 add r7, sp, #0
- 800089a: 6078 str r0, [r7, #4]
- if(htim_base->Instance==TIM3)
- 800089c: 687b ldr r3, [r7, #4]
- 800089e: 681b ldr r3, [r3, #0]
- 80008a0: 4a0d ldr r2, [pc, #52] ; (80008d8 <HAL_TIM_Base_MspInit+0x44>)
- 80008a2: 4293 cmp r3, r2
- 80008a4: d113 bne.n 80008ce <HAL_TIM_Base_MspInit+0x3a>
- {
- /* USER CODE BEGIN TIM3_MspInit 0 */
-
- /* USER CODE END TIM3_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_TIM3_CLK_ENABLE();
- 80008a6: 4b0d ldr r3, [pc, #52] ; (80008dc <HAL_TIM_Base_MspInit+0x48>)
- 80008a8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80008aa: 4a0c ldr r2, [pc, #48] ; (80008dc <HAL_TIM_Base_MspInit+0x48>)
- 80008ac: f043 0302 orr.w r3, r3, #2
- 80008b0: 6413 str r3, [r2, #64] ; 0x40
- 80008b2: 4b0a ldr r3, [pc, #40] ; (80008dc <HAL_TIM_Base_MspInit+0x48>)
- 80008b4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80008b6: f003 0302 and.w r3, r3, #2
- 80008ba: 60fb str r3, [r7, #12]
- 80008bc: 68fb ldr r3, [r7, #12]
- /* TIM3 interrupt Init */
- HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
- 80008be: 2200 movs r2, #0
- 80008c0: 2100 movs r1, #0
- 80008c2: 201d movs r0, #29
- 80008c4: f000 fa31 bl 8000d2a <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(TIM3_IRQn);
- 80008c8: 201d movs r0, #29
- 80008ca: f000 fa4a bl 8000d62 <HAL_NVIC_EnableIRQ>
- /* USER CODE BEGIN TIM3_MspInit 1 */
-
- /* USER CODE END TIM3_MspInit 1 */
- }
-
-}
- 80008ce: bf00 nop
- 80008d0: 3710 adds r7, #16
- 80008d2: 46bd mov sp, r7
- 80008d4: bd80 pop {r7, pc}
- 80008d6: bf00 nop
- 80008d8: 40000400 .word 0x40000400
- 80008dc: 40023800 .word 0x40023800
-
-080008e0 <HAL_UART_MspInit>:
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
- 80008e0: b580 push {r7, lr}
- 80008e2: b08a sub sp, #40 ; 0x28
- 80008e4: af00 add r7, sp, #0
- 80008e6: 6078 str r0, [r7, #4]
- GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80008e8: f107 0314 add.w r3, r7, #20
- 80008ec: 2200 movs r2, #0
- 80008ee: 601a str r2, [r3, #0]
- 80008f0: 605a str r2, [r3, #4]
- 80008f2: 609a str r2, [r3, #8]
- 80008f4: 60da str r2, [r3, #12]
- 80008f6: 611a str r2, [r3, #16]
- if(huart->Instance==USART6)
- 80008f8: 687b ldr r3, [r7, #4]
- 80008fa: 681b ldr r3, [r3, #0]
- 80008fc: 4a1b ldr r2, [pc, #108] ; (800096c <HAL_UART_MspInit+0x8c>)
- 80008fe: 4293 cmp r3, r2
- 8000900: d12f bne.n 8000962 <HAL_UART_MspInit+0x82>
- {
- /* USER CODE BEGIN USART6_MspInit 0 */
-
- /* USER CODE END USART6_MspInit 0 */
- /* Peripheral clock enable */
- __HAL_RCC_USART6_CLK_ENABLE();
- 8000902: 4b1b ldr r3, [pc, #108] ; (8000970 <HAL_UART_MspInit+0x90>)
- 8000904: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000906: 4a1a ldr r2, [pc, #104] ; (8000970 <HAL_UART_MspInit+0x90>)
- 8000908: f043 0320 orr.w r3, r3, #32
- 800090c: 6453 str r3, [r2, #68] ; 0x44
- 800090e: 4b18 ldr r3, [pc, #96] ; (8000970 <HAL_UART_MspInit+0x90>)
- 8000910: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000912: f003 0320 and.w r3, r3, #32
- 8000916: 613b str r3, [r7, #16]
- 8000918: 693b ldr r3, [r7, #16]
-
- __HAL_RCC_GPIOC_CLK_ENABLE();
- 800091a: 4b15 ldr r3, [pc, #84] ; (8000970 <HAL_UART_MspInit+0x90>)
- 800091c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800091e: 4a14 ldr r2, [pc, #80] ; (8000970 <HAL_UART_MspInit+0x90>)
- 8000920: f043 0304 orr.w r3, r3, #4
- 8000924: 6313 str r3, [r2, #48] ; 0x30
- 8000926: 4b12 ldr r3, [pc, #72] ; (8000970 <HAL_UART_MspInit+0x90>)
- 8000928: 6b1b ldr r3, [r3, #48] ; 0x30
- 800092a: f003 0304 and.w r3, r3, #4
- 800092e: 60fb str r3, [r7, #12]
- 8000930: 68fb ldr r3, [r7, #12]
- /**USART6 GPIO Configuration
- PC6 ------> USART6_TX
- PC7 ------> USART6_RX
- */
- GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 8000932: 23c0 movs r3, #192 ; 0xc0
- 8000934: 617b str r3, [r7, #20]
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8000936: 2302 movs r3, #2
- 8000938: 61bb str r3, [r7, #24]
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800093a: 2300 movs r3, #0
- 800093c: 61fb str r3, [r7, #28]
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 800093e: 2303 movs r3, #3
- 8000940: 623b str r3, [r7, #32]
- GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
- 8000942: 2308 movs r3, #8
- 8000944: 627b str r3, [r7, #36] ; 0x24
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8000946: f107 0314 add.w r3, r7, #20
- 800094a: 4619 mov r1, r3
- 800094c: 4809 ldr r0, [pc, #36] ; (8000974 <HAL_UART_MspInit+0x94>)
- 800094e: f000 fa45 bl 8000ddc <HAL_GPIO_Init>
-
- /* USART6 interrupt Init */
- HAL_NVIC_SetPriority(USART6_IRQn, 0, 0);
- 8000952: 2200 movs r2, #0
- 8000954: 2100 movs r1, #0
- 8000956: 2047 movs r0, #71 ; 0x47
- 8000958: f000 f9e7 bl 8000d2a <HAL_NVIC_SetPriority>
- HAL_NVIC_EnableIRQ(USART6_IRQn);
- 800095c: 2047 movs r0, #71 ; 0x47
- 800095e: f000 fa00 bl 8000d62 <HAL_NVIC_EnableIRQ>
- /* USER CODE BEGIN USART6_MspInit 1 */
-
- /* USER CODE END USART6_MspInit 1 */
- }
-
-}
- 8000962: bf00 nop
- 8000964: 3728 adds r7, #40 ; 0x28
- 8000966: 46bd mov sp, r7
- 8000968: bd80 pop {r7, pc}
- 800096a: bf00 nop
- 800096c: 40011400 .word 0x40011400
- 8000970: 40023800 .word 0x40023800
- 8000974: 40020800 .word 0x40020800
-
-08000978 <NMI_Handler>:
-/******************************************************************************/
-/**
- * @brief This function handles Non maskable interrupt.
- */
-void NMI_Handler(void)
-{
- 8000978: b480 push {r7}
- 800097a: af00 add r7, sp, #0
-
- /* USER CODE END NonMaskableInt_IRQn 0 */
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
- /* USER CODE END NonMaskableInt_IRQn 1 */
-}
- 800097c: bf00 nop
- 800097e: 46bd mov sp, r7
- 8000980: f85d 7b04 ldr.w r7, [sp], #4
- 8000984: 4770 bx lr
-
-08000986 <HardFault_Handler>:
-
-/**
- * @brief This function handles Hard fault interrupt.
- */
-void HardFault_Handler(void)
-{
- 8000986: b480 push {r7}
- 8000988: af00 add r7, sp, #0
- /* USER CODE BEGIN HardFault_IRQn 0 */
-
- /* USER CODE END HardFault_IRQn 0 */
- while (1)
- 800098a: e7fe b.n 800098a <HardFault_Handler+0x4>
-
-0800098c <MemManage_Handler>:
-
-/**
- * @brief This function handles Memory management fault.
- */
-void MemManage_Handler(void)
-{
- 800098c: b480 push {r7}
- 800098e: af00 add r7, sp, #0
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
- /* USER CODE END MemoryManagement_IRQn 0 */
- while (1)
- 8000990: e7fe b.n 8000990 <MemManage_Handler+0x4>
-
-08000992 <BusFault_Handler>:
-
-/**
- * @brief This function handles Pre-fetch fault, memory access fault.
- */
-void BusFault_Handler(void)
-{
- 8000992: b480 push {r7}
- 8000994: af00 add r7, sp, #0
- /* USER CODE BEGIN BusFault_IRQn 0 */
-
- /* USER CODE END BusFault_IRQn 0 */
- while (1)
- 8000996: e7fe b.n 8000996 <BusFault_Handler+0x4>
-
-08000998 <UsageFault_Handler>:
-
-/**
- * @brief This function handles Undefined instruction or illegal state.
- */
-void UsageFault_Handler(void)
-{
- 8000998: b480 push {r7}
- 800099a: af00 add r7, sp, #0
- /* USER CODE BEGIN UsageFault_IRQn 0 */
-
- /* USER CODE END UsageFault_IRQn 0 */
- while (1)
- 800099c: e7fe b.n 800099c <UsageFault_Handler+0x4>
-
-0800099e <SVC_Handler>:
-
-/**
- * @brief This function handles System service call via SWI instruction.
- */
-void SVC_Handler(void)
-{
- 800099e: b480 push {r7}
- 80009a0: af00 add r7, sp, #0
-
- /* USER CODE END SVCall_IRQn 0 */
- /* USER CODE BEGIN SVCall_IRQn 1 */
-
- /* USER CODE END SVCall_IRQn 1 */
-}
- 80009a2: bf00 nop
- 80009a4: 46bd mov sp, r7
- 80009a6: f85d 7b04 ldr.w r7, [sp], #4
- 80009aa: 4770 bx lr
-
-080009ac <DebugMon_Handler>:
-
-/**
- * @brief This function handles Debug monitor.
- */
-void DebugMon_Handler(void)
-{
- 80009ac: b480 push {r7}
- 80009ae: af00 add r7, sp, #0
-
- /* USER CODE END DebugMonitor_IRQn 0 */
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
- /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 80009b0: bf00 nop
- 80009b2: 46bd mov sp, r7
- 80009b4: f85d 7b04 ldr.w r7, [sp], #4
- 80009b8: 4770 bx lr
-
-080009ba <PendSV_Handler>:
-
-/**
- * @brief This function handles Pendable request for system service.
- */
-void PendSV_Handler(void)
-{
- 80009ba: b480 push {r7}
- 80009bc: af00 add r7, sp, #0
-
- /* USER CODE END PendSV_IRQn 0 */
- /* USER CODE BEGIN PendSV_IRQn 1 */
-
- /* USER CODE END PendSV_IRQn 1 */
-}
- 80009be: bf00 nop
- 80009c0: 46bd mov sp, r7
- 80009c2: f85d 7b04 ldr.w r7, [sp], #4
- 80009c6: 4770 bx lr
-
-080009c8 <SysTick_Handler>:
-
-/**
- * @brief This function handles System tick timer.
- */
-void SysTick_Handler(void)
-{
- 80009c8: b580 push {r7, lr}
- 80009ca: af00 add r7, sp, #0
- /* USER CODE BEGIN SysTick_IRQn 0 */
-
- /* USER CODE END SysTick_IRQn 0 */
- HAL_IncTick();
- 80009cc: f000 f8b2 bl 8000b34 <HAL_IncTick>
- /* USER CODE BEGIN SysTick_IRQn 1 */
-
- /* USER CODE END SysTick_IRQn 1 */
-}
- 80009d0: bf00 nop
- 80009d2: bd80 pop {r7, pc}
-
-080009d4 <TIM3_IRQHandler>:
-
-/**
- * @brief This function handles TIM3 global interrupt.
- */
-void TIM3_IRQHandler(void)
-{
- 80009d4: b580 push {r7, lr}
- 80009d6: af00 add r7, sp, #0
- /* USER CODE BEGIN TIM3_IRQn 0 */
-
- /* USER CODE END TIM3_IRQn 0 */
- HAL_TIM_IRQHandler(&htim3);
- 80009d8: 4802 ldr r0, [pc, #8] ; (80009e4 <TIM3_IRQHandler+0x10>)
- 80009da: f001 fc65 bl 80022a8 <HAL_TIM_IRQHandler>
- /* USER CODE BEGIN TIM3_IRQn 1 */
-
- /* USER CODE END TIM3_IRQn 1 */
-}
- 80009de: bf00 nop
- 80009e0: bd80 pop {r7, pc}
- 80009e2: bf00 nop
- 80009e4: 2000003c .word 0x2000003c
-
-080009e8 <USART6_IRQHandler>:
-
-/**
- * @brief This function handles USART6 global interrupt.
- */
-void USART6_IRQHandler(void)
-{
- 80009e8: b580 push {r7, lr}
- 80009ea: af00 add r7, sp, #0
- /* USER CODE BEGIN USART6_IRQn 0 */
-
- /* USER CODE END USART6_IRQn 0 */
- HAL_UART_IRQHandler(&huart6);
- 80009ec: 4802 ldr r0, [pc, #8] ; (80009f8 <USART6_IRQHandler+0x10>)
- 80009ee: f002 f993 bl 8002d18 <HAL_UART_IRQHandler>
- /* USER CODE BEGIN USART6_IRQn 1 */
-
- /* USER CODE END USART6_IRQn 1 */
-}
- 80009f2: bf00 nop
- 80009f4: bd80 pop {r7, pc}
- 80009f6: bf00 nop
- 80009f8: 20000084 .word 0x20000084
-
-080009fc <SystemInit>:
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- 80009fc: b480 push {r7}
- 80009fe: af00 add r7, sp, #0
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 8000a00: 4b15 ldr r3, [pc, #84] ; (8000a58 <SystemInit+0x5c>)
- 8000a02: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8000a06: 4a14 ldr r2, [pc, #80] ; (8000a58 <SystemInit+0x5c>)
- 8000a08: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 8000a0c: f8c2 3088 str.w r3, [r2, #136] ; 0x88
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
- 8000a10: 4b12 ldr r3, [pc, #72] ; (8000a5c <SystemInit+0x60>)
- 8000a12: 681b ldr r3, [r3, #0]
- 8000a14: 4a11 ldr r2, [pc, #68] ; (8000a5c <SystemInit+0x60>)
- 8000a16: f043 0301 orr.w r3, r3, #1
- 8000a1a: 6013 str r3, [r2, #0]
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
- 8000a1c: 4b0f ldr r3, [pc, #60] ; (8000a5c <SystemInit+0x60>)
- 8000a1e: 2200 movs r2, #0
- 8000a20: 609a str r2, [r3, #8]
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8000a22: 4b0e ldr r3, [pc, #56] ; (8000a5c <SystemInit+0x60>)
- 8000a24: 681a ldr r2, [r3, #0]
- 8000a26: 490d ldr r1, [pc, #52] ; (8000a5c <SystemInit+0x60>)
- 8000a28: 4b0d ldr r3, [pc, #52] ; (8000a60 <SystemInit+0x64>)
- 8000a2a: 4013 ands r3, r2
- 8000a2c: 600b str r3, [r1, #0]
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
- 8000a2e: 4b0b ldr r3, [pc, #44] ; (8000a5c <SystemInit+0x60>)
- 8000a30: 4a0c ldr r2, [pc, #48] ; (8000a64 <SystemInit+0x68>)
- 8000a32: 605a str r2, [r3, #4]
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
- 8000a34: 4b09 ldr r3, [pc, #36] ; (8000a5c <SystemInit+0x60>)
- 8000a36: 681b ldr r3, [r3, #0]
- 8000a38: 4a08 ldr r2, [pc, #32] ; (8000a5c <SystemInit+0x60>)
- 8000a3a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8000a3e: 6013 str r3, [r2, #0]
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
- 8000a40: 4b06 ldr r3, [pc, #24] ; (8000a5c <SystemInit+0x60>)
- 8000a42: 2200 movs r2, #0
- 8000a44: 60da str r2, [r3, #12]
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8000a46: 4b04 ldr r3, [pc, #16] ; (8000a58 <SystemInit+0x5c>)
- 8000a48: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 8000a4c: 609a str r2, [r3, #8]
-#endif
-}
- 8000a4e: bf00 nop
- 8000a50: 46bd mov sp, r7
- 8000a52: f85d 7b04 ldr.w r7, [sp], #4
- 8000a56: 4770 bx lr
- 8000a58: e000ed00 .word 0xe000ed00
- 8000a5c: 40023800 .word 0x40023800
- 8000a60: fef6ffff .word 0xfef6ffff
- 8000a64: 24003010 .word 0x24003010
-
-08000a68 <Reset_Handler>:
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
- 8000a68: f8df d034 ldr.w sp, [pc, #52] ; 8000aa0 <LoopFillZerobss+0x14>
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- 8000a6c: 2100 movs r1, #0
- b LoopCopyDataInit
- 8000a6e: e003 b.n 8000a78 <LoopCopyDataInit>
-
-08000a70 <CopyDataInit>:
-
-CopyDataInit:
- ldr r3, =_sidata
- 8000a70: 4b0c ldr r3, [pc, #48] ; (8000aa4 <LoopFillZerobss+0x18>)
- ldr r3, [r3, r1]
- 8000a72: 585b ldr r3, [r3, r1]
- str r3, [r0, r1]
- 8000a74: 5043 str r3, [r0, r1]
- adds r1, r1, #4
- 8000a76: 3104 adds r1, #4
-
-08000a78 <LoopCopyDataInit>:
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- 8000a78: 480b ldr r0, [pc, #44] ; (8000aa8 <LoopFillZerobss+0x1c>)
- ldr r3, =_edata
- 8000a7a: 4b0c ldr r3, [pc, #48] ; (8000aac <LoopFillZerobss+0x20>)
- adds r2, r0, r1
- 8000a7c: 1842 adds r2, r0, r1
- cmp r2, r3
- 8000a7e: 429a cmp r2, r3
- bcc CopyDataInit
- 8000a80: d3f6 bcc.n 8000a70 <CopyDataInit>
- ldr r2, =_sbss
- 8000a82: 4a0b ldr r2, [pc, #44] ; (8000ab0 <LoopFillZerobss+0x24>)
- b LoopFillZerobss
- 8000a84: e002 b.n 8000a8c <LoopFillZerobss>
-
-08000a86 <FillZerobss>:
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- 8000a86: 2300 movs r3, #0
- str r3, [r2], #4
- 8000a88: f842 3b04 str.w r3, [r2], #4
-
-08000a8c <LoopFillZerobss>:
-
-LoopFillZerobss:
- ldr r3, = _ebss
- 8000a8c: 4b09 ldr r3, [pc, #36] ; (8000ab4 <LoopFillZerobss+0x28>)
- cmp r2, r3
- 8000a8e: 429a cmp r2, r3
- bcc FillZerobss
- 8000a90: d3f9 bcc.n 8000a86 <FillZerobss>
-
-/* Call the clock system initialization function.*/
- bl SystemInit
- 8000a92: f7ff ffb3 bl 80009fc <SystemInit>
-/* Call static constructors */
- bl __libc_init_array
- 8000a96: f002 ff17 bl 80038c8 <__libc_init_array>
-/* Call the application's entry point.*/
- bl main
- 8000a9a: f7ff fd4d bl 8000538 <main>
- bx lr
- 8000a9e: 4770 bx lr
- ldr sp, =_estack /* set stack pointer */
- 8000aa0: 20080000 .word 0x20080000
- ldr r3, =_sidata
- 8000aa4: 08003960 .word 0x08003960
- ldr r0, =_sdata
- 8000aa8: 20000000 .word 0x20000000
- ldr r3, =_edata
- 8000aac: 2000000c .word 0x2000000c
- ldr r2, =_sbss
- 8000ab0: 2000000c .word 0x2000000c
- ldr r3, = _ebss
- 8000ab4: 20000110 .word 0x20000110
-
-08000ab8 <ADC_IRQHandler>:
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- 8000ab8: e7fe b.n 8000ab8 <ADC_IRQHandler>
-
-08000aba <HAL_Init>:
- * need to ensure that the SysTick time base is always set to 1 millisecond
- * to have correct HAL operation.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8000aba: b580 push {r7, lr}
- 8000abc: af00 add r7, sp, #0
-#if (PREFETCH_ENABLE != 0U)
- __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8000abe: 2003 movs r0, #3
- 8000ac0: f000 f928 bl 8000d14 <HAL_NVIC_SetPriorityGrouping>
-
- /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
- HAL_InitTick(TICK_INT_PRIORITY);
- 8000ac4: 2000 movs r0, #0
- 8000ac6: f000 f805 bl 8000ad4 <HAL_InitTick>
-
- /* Init the low level hardware */
- HAL_MspInit();
- 8000aca: f7ff febf bl 800084c <HAL_MspInit>
-
- /* Return function status */
- return HAL_OK;
- 8000ace: 2300 movs r3, #0
-}
- 8000ad0: 4618 mov r0, r3
- 8000ad2: bd80 pop {r7, pc}
-
-08000ad4 <HAL_InitTick>:
- * implementation in user file.
- * @param TickPriority Tick interrupt priority.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- 8000ad4: b580 push {r7, lr}
- 8000ad6: b082 sub sp, #8
- 8000ad8: af00 add r7, sp, #0
- 8000ada: 6078 str r0, [r7, #4]
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8000adc: 4b12 ldr r3, [pc, #72] ; (8000b28 <HAL_InitTick+0x54>)
- 8000ade: 681a ldr r2, [r3, #0]
- 8000ae0: 4b12 ldr r3, [pc, #72] ; (8000b2c <HAL_InitTick+0x58>)
- 8000ae2: 781b ldrb r3, [r3, #0]
- 8000ae4: 4619 mov r1, r3
- 8000ae6: f44f 737a mov.w r3, #1000 ; 0x3e8
- 8000aea: fbb3 f3f1 udiv r3, r3, r1
- 8000aee: fbb2 f3f3 udiv r3, r2, r3
- 8000af2: 4618 mov r0, r3
- 8000af4: f000 f943 bl 8000d7e <HAL_SYSTICK_Config>
- 8000af8: 4603 mov r3, r0
- 8000afa: 2b00 cmp r3, #0
- 8000afc: d001 beq.n 8000b02 <HAL_InitTick+0x2e>
- {
- return HAL_ERROR;
- 8000afe: 2301 movs r3, #1
- 8000b00: e00e b.n 8000b20 <HAL_InitTick+0x4c>
- }
-
- /* Configure the SysTick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8000b02: 687b ldr r3, [r7, #4]
- 8000b04: 2b0f cmp r3, #15
- 8000b06: d80a bhi.n 8000b1e <HAL_InitTick+0x4a>
- {
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8000b08: 2200 movs r2, #0
- 8000b0a: 6879 ldr r1, [r7, #4]
- 8000b0c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8000b10: f000 f90b bl 8000d2a <HAL_NVIC_SetPriority>
- uwTickPrio = TickPriority;
- 8000b14: 4a06 ldr r2, [pc, #24] ; (8000b30 <HAL_InitTick+0x5c>)
- 8000b16: 687b ldr r3, [r7, #4]
- 8000b18: 6013 str r3, [r2, #0]
- {
- return HAL_ERROR;
- }
-
- /* Return function status */
- return HAL_OK;
- 8000b1a: 2300 movs r3, #0
- 8000b1c: e000 b.n 8000b20 <HAL_InitTick+0x4c>
- return HAL_ERROR;
- 8000b1e: 2301 movs r3, #1
-}
- 8000b20: 4618 mov r0, r3
- 8000b22: 3708 adds r7, #8
- 8000b24: 46bd mov sp, r7
- 8000b26: bd80 pop {r7, pc}
- 8000b28: 20000000 .word 0x20000000
- 8000b2c: 20000008 .word 0x20000008
- 8000b30: 20000004 .word 0x20000004
-
-08000b34 <HAL_IncTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_IncTick(void)
-{
- 8000b34: b480 push {r7}
- 8000b36: af00 add r7, sp, #0
- uwTick += uwTickFreq;
- 8000b38: 4b06 ldr r3, [pc, #24] ; (8000b54 <HAL_IncTick+0x20>)
- 8000b3a: 781b ldrb r3, [r3, #0]
- 8000b3c: 461a mov r2, r3
- 8000b3e: 4b06 ldr r3, [pc, #24] ; (8000b58 <HAL_IncTick+0x24>)
- 8000b40: 681b ldr r3, [r3, #0]
- 8000b42: 4413 add r3, r2
- 8000b44: 4a04 ldr r2, [pc, #16] ; (8000b58 <HAL_IncTick+0x24>)
- 8000b46: 6013 str r3, [r2, #0]
-}
- 8000b48: bf00 nop
- 8000b4a: 46bd mov sp, r7
- 8000b4c: f85d 7b04 ldr.w r7, [sp], #4
- 8000b50: 4770 bx lr
- 8000b52: bf00 nop
- 8000b54: 20000008 .word 0x20000008
- 8000b58: 2000010c .word 0x2000010c
-
-08000b5c <HAL_GetTick>:
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval tick value
- */
-__weak uint32_t HAL_GetTick(void)
-{
- 8000b5c: b480 push {r7}
- 8000b5e: af00 add r7, sp, #0
- return uwTick;
- 8000b60: 4b03 ldr r3, [pc, #12] ; (8000b70 <HAL_GetTick+0x14>)
- 8000b62: 681b ldr r3, [r3, #0]
-}
- 8000b64: 4618 mov r0, r3
- 8000b66: 46bd mov sp, r7
- 8000b68: f85d 7b04 ldr.w r7, [sp], #4
- 8000b6c: 4770 bx lr
- 8000b6e: bf00 nop
- 8000b70: 2000010c .word 0x2000010c
-
-08000b74 <__NVIC_SetPriorityGrouping>:
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8000b74: b480 push {r7}
- 8000b76: b085 sub sp, #20
- 8000b78: af00 add r7, sp, #0
- 8000b7a: 6078 str r0, [r7, #4]
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8000b7c: 687b ldr r3, [r7, #4]
- 8000b7e: f003 0307 and.w r3, r3, #7
- 8000b82: 60fb str r3, [r7, #12]
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- 8000b84: 4b0b ldr r3, [pc, #44] ; (8000bb4 <__NVIC_SetPriorityGrouping+0x40>)
- 8000b86: 68db ldr r3, [r3, #12]
- 8000b88: 60bb str r3, [r7, #8]
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 8000b8a: 68ba ldr r2, [r7, #8]
- 8000b8c: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8000b90: 4013 ands r3, r2
- 8000b92: 60bb str r3, [r7, #8]
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8000b94: 68fb ldr r3, [r7, #12]
- 8000b96: 021a lsls r2, r3, #8
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8000b98: 68bb ldr r3, [r7, #8]
- 8000b9a: 431a orrs r2, r3
- reg_value = (reg_value |
- 8000b9c: 4b06 ldr r3, [pc, #24] ; (8000bb8 <__NVIC_SetPriorityGrouping+0x44>)
- 8000b9e: 4313 orrs r3, r2
- 8000ba0: 60bb str r3, [r7, #8]
- SCB->AIRCR = reg_value;
- 8000ba2: 4a04 ldr r2, [pc, #16] ; (8000bb4 <__NVIC_SetPriorityGrouping+0x40>)
- 8000ba4: 68bb ldr r3, [r7, #8]
- 8000ba6: 60d3 str r3, [r2, #12]
-}
- 8000ba8: bf00 nop
- 8000baa: 3714 adds r7, #20
- 8000bac: 46bd mov sp, r7
- 8000bae: f85d 7b04 ldr.w r7, [sp], #4
- 8000bb2: 4770 bx lr
- 8000bb4: e000ed00 .word 0xe000ed00
- 8000bb8: 05fa0000 .word 0x05fa0000
-
-08000bbc <__NVIC_GetPriorityGrouping>:
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- 8000bbc: b480 push {r7}
- 8000bbe: af00 add r7, sp, #0
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8000bc0: 4b04 ldr r3, [pc, #16] ; (8000bd4 <__NVIC_GetPriorityGrouping+0x18>)
- 8000bc2: 68db ldr r3, [r3, #12]
- 8000bc4: 0a1b lsrs r3, r3, #8
- 8000bc6: f003 0307 and.w r3, r3, #7
-}
- 8000bca: 4618 mov r0, r3
- 8000bcc: 46bd mov sp, r7
- 8000bce: f85d 7b04 ldr.w r7, [sp], #4
- 8000bd2: 4770 bx lr
- 8000bd4: e000ed00 .word 0xe000ed00
-
-08000bd8 <__NVIC_EnableIRQ>:
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8000bd8: b480 push {r7}
- 8000bda: b083 sub sp, #12
- 8000bdc: af00 add r7, sp, #0
- 8000bde: 4603 mov r3, r0
- 8000be0: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8000be2: f997 3007 ldrsb.w r3, [r7, #7]
- 8000be6: 2b00 cmp r3, #0
- 8000be8: db0b blt.n 8000c02 <__NVIC_EnableIRQ+0x2a>
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 8000bea: 79fb ldrb r3, [r7, #7]
- 8000bec: f003 021f and.w r2, r3, #31
- 8000bf0: 4907 ldr r1, [pc, #28] ; (8000c10 <__NVIC_EnableIRQ+0x38>)
- 8000bf2: f997 3007 ldrsb.w r3, [r7, #7]
- 8000bf6: 095b lsrs r3, r3, #5
- 8000bf8: 2001 movs r0, #1
- 8000bfa: fa00 f202 lsl.w r2, r0, r2
- 8000bfe: f841 2023 str.w r2, [r1, r3, lsl #2]
- }
-}
- 8000c02: bf00 nop
- 8000c04: 370c adds r7, #12
- 8000c06: 46bd mov sp, r7
- 8000c08: f85d 7b04 ldr.w r7, [sp], #4
- 8000c0c: 4770 bx lr
- 8000c0e: bf00 nop
- 8000c10: e000e100 .word 0xe000e100
-
-08000c14 <__NVIC_SetPriority>:
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- 8000c14: b480 push {r7}
- 8000c16: b083 sub sp, #12
- 8000c18: af00 add r7, sp, #0
- 8000c1a: 4603 mov r3, r0
- 8000c1c: 6039 str r1, [r7, #0]
- 8000c1e: 71fb strb r3, [r7, #7]
- if ((int32_t)(IRQn) >= 0)
- 8000c20: f997 3007 ldrsb.w r3, [r7, #7]
- 8000c24: 2b00 cmp r3, #0
- 8000c26: db0a blt.n 8000c3e <__NVIC_SetPriority+0x2a>
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8000c28: 683b ldr r3, [r7, #0]
- 8000c2a: b2da uxtb r2, r3
- 8000c2c: 490c ldr r1, [pc, #48] ; (8000c60 <__NVIC_SetPriority+0x4c>)
- 8000c2e: f997 3007 ldrsb.w r3, [r7, #7]
- 8000c32: 0112 lsls r2, r2, #4
- 8000c34: b2d2 uxtb r2, r2
- 8000c36: 440b add r3, r1
- 8000c38: f883 2300 strb.w r2, [r3, #768] ; 0x300
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
- 8000c3c: e00a b.n 8000c54 <__NVIC_SetPriority+0x40>
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8000c3e: 683b ldr r3, [r7, #0]
- 8000c40: b2da uxtb r2, r3
- 8000c42: 4908 ldr r1, [pc, #32] ; (8000c64 <__NVIC_SetPriority+0x50>)
- 8000c44: 79fb ldrb r3, [r7, #7]
- 8000c46: f003 030f and.w r3, r3, #15
- 8000c4a: 3b04 subs r3, #4
- 8000c4c: 0112 lsls r2, r2, #4
- 8000c4e: b2d2 uxtb r2, r2
- 8000c50: 440b add r3, r1
- 8000c52: 761a strb r2, [r3, #24]
-}
- 8000c54: bf00 nop
- 8000c56: 370c adds r7, #12
- 8000c58: 46bd mov sp, r7
- 8000c5a: f85d 7b04 ldr.w r7, [sp], #4
- 8000c5e: 4770 bx lr
- 8000c60: e000e100 .word 0xe000e100
- 8000c64: e000ed00 .word 0xe000ed00
-
-08000c68 <NVIC_EncodePriority>:
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8000c68: b480 push {r7}
- 8000c6a: b089 sub sp, #36 ; 0x24
- 8000c6c: af00 add r7, sp, #0
- 8000c6e: 60f8 str r0, [r7, #12]
- 8000c70: 60b9 str r1, [r7, #8]
- 8000c72: 607a str r2, [r7, #4]
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8000c74: 68fb ldr r3, [r7, #12]
- 8000c76: f003 0307 and.w r3, r3, #7
- 8000c7a: 61fb str r3, [r7, #28]
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8000c7c: 69fb ldr r3, [r7, #28]
- 8000c7e: f1c3 0307 rsb r3, r3, #7
- 8000c82: 2b04 cmp r3, #4
- 8000c84: bf28 it cs
- 8000c86: 2304 movcs r3, #4
- 8000c88: 61bb str r3, [r7, #24]
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8000c8a: 69fb ldr r3, [r7, #28]
- 8000c8c: 3304 adds r3, #4
- 8000c8e: 2b06 cmp r3, #6
- 8000c90: d902 bls.n 8000c98 <NVIC_EncodePriority+0x30>
- 8000c92: 69fb ldr r3, [r7, #28]
- 8000c94: 3b03 subs r3, #3
- 8000c96: e000 b.n 8000c9a <NVIC_EncodePriority+0x32>
- 8000c98: 2300 movs r3, #0
- 8000c9a: 617b str r3, [r7, #20]
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000c9c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000ca0: 69bb ldr r3, [r7, #24]
- 8000ca2: fa02 f303 lsl.w r3, r2, r3
- 8000ca6: 43da mvns r2, r3
- 8000ca8: 68bb ldr r3, [r7, #8]
- 8000caa: 401a ands r2, r3
- 8000cac: 697b ldr r3, [r7, #20]
- 8000cae: 409a lsls r2, r3
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8000cb0: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 8000cb4: 697b ldr r3, [r7, #20]
- 8000cb6: fa01 f303 lsl.w r3, r1, r3
- 8000cba: 43d9 mvns r1, r3
- 8000cbc: 687b ldr r3, [r7, #4]
- 8000cbe: 400b ands r3, r1
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000cc0: 4313 orrs r3, r2
- );
-}
- 8000cc2: 4618 mov r0, r3
- 8000cc4: 3724 adds r7, #36 ; 0x24
- 8000cc6: 46bd mov sp, r7
- 8000cc8: f85d 7b04 ldr.w r7, [sp], #4
- 8000ccc: 4770 bx lr
- ...
-
-08000cd0 <SysTick_Config>:
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 8000cd0: b580 push {r7, lr}
- 8000cd2: b082 sub sp, #8
- 8000cd4: af00 add r7, sp, #0
- 8000cd6: 6078 str r0, [r7, #4]
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8000cd8: 687b ldr r3, [r7, #4]
- 8000cda: 3b01 subs r3, #1
- 8000cdc: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8000ce0: d301 bcc.n 8000ce6 <SysTick_Config+0x16>
- {
- return (1UL); /* Reload value impossible */
- 8000ce2: 2301 movs r3, #1
- 8000ce4: e00f b.n 8000d06 <SysTick_Config+0x36>
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8000ce6: 4a0a ldr r2, [pc, #40] ; (8000d10 <SysTick_Config+0x40>)
- 8000ce8: 687b ldr r3, [r7, #4]
- 8000cea: 3b01 subs r3, #1
- 8000cec: 6053 str r3, [r2, #4]
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8000cee: 210f movs r1, #15
- 8000cf0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8000cf4: f7ff ff8e bl 8000c14 <__NVIC_SetPriority>
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8000cf8: 4b05 ldr r3, [pc, #20] ; (8000d10 <SysTick_Config+0x40>)
- 8000cfa: 2200 movs r2, #0
- 8000cfc: 609a str r2, [r3, #8]
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8000cfe: 4b04 ldr r3, [pc, #16] ; (8000d10 <SysTick_Config+0x40>)
- 8000d00: 2207 movs r2, #7
- 8000d02: 601a str r2, [r3, #0]
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
- 8000d04: 2300 movs r3, #0
-}
- 8000d06: 4618 mov r0, r3
- 8000d08: 3708 adds r7, #8
- 8000d0a: 46bd mov sp, r7
- 8000d0c: bd80 pop {r7, pc}
- 8000d0e: bf00 nop
- 8000d10: e000e010 .word 0xe000e010
-
-08000d14 <HAL_NVIC_SetPriorityGrouping>:
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
- * The pending IRQ priority will be managed only by the subpriority.
- * @retval None
- */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8000d14: b580 push {r7, lr}
- 8000d16: b082 sub sp, #8
- 8000d18: af00 add r7, sp, #0
- 8000d1a: 6078 str r0, [r7, #4]
- /* Check the parameters */
- assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-
- /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
- NVIC_SetPriorityGrouping(PriorityGroup);
- 8000d1c: 6878 ldr r0, [r7, #4]
- 8000d1e: f7ff ff29 bl 8000b74 <__NVIC_SetPriorityGrouping>
-}
- 8000d22: bf00 nop
- 8000d24: 3708 adds r7, #8
- 8000d26: 46bd mov sp, r7
- 8000d28: bd80 pop {r7, pc}
-
-08000d2a <HAL_NVIC_SetPriority>:
- * This parameter can be a value between 0 and 15
- * A lower priority value indicates a higher priority.
- * @retval None
- */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 8000d2a: b580 push {r7, lr}
- 8000d2c: b086 sub sp, #24
- 8000d2e: af00 add r7, sp, #0
- 8000d30: 4603 mov r3, r0
- 8000d32: 60b9 str r1, [r7, #8]
- 8000d34: 607a str r2, [r7, #4]
- 8000d36: 73fb strb r3, [r7, #15]
- uint32_t prioritygroup = 0x00;
- 8000d38: 2300 movs r3, #0
- 8000d3a: 617b str r3, [r7, #20]
-
- /* Check the parameters */
- assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-
- prioritygroup = NVIC_GetPriorityGrouping();
- 8000d3c: f7ff ff3e bl 8000bbc <__NVIC_GetPriorityGrouping>
- 8000d40: 6178 str r0, [r7, #20]
-
- NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8000d42: 687a ldr r2, [r7, #4]
- 8000d44: 68b9 ldr r1, [r7, #8]
- 8000d46: 6978 ldr r0, [r7, #20]
- 8000d48: f7ff ff8e bl 8000c68 <NVIC_EncodePriority>
- 8000d4c: 4602 mov r2, r0
- 8000d4e: f997 300f ldrsb.w r3, [r7, #15]
- 8000d52: 4611 mov r1, r2
- 8000d54: 4618 mov r0, r3
- 8000d56: f7ff ff5d bl 8000c14 <__NVIC_SetPriority>
-}
- 8000d5a: bf00 nop
- 8000d5c: 3718 adds r7, #24
- 8000d5e: 46bd mov sp, r7
- 8000d60: bd80 pop {r7, pc}
-
-08000d62 <HAL_NVIC_EnableIRQ>:
- * This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
- * @retval None
- */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 8000d62: b580 push {r7, lr}
- 8000d64: b082 sub sp, #8
- 8000d66: af00 add r7, sp, #0
- 8000d68: 4603 mov r3, r0
- 8000d6a: 71fb strb r3, [r7, #7]
- /* Check the parameters */
- assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
- /* Enable interrupt */
- NVIC_EnableIRQ(IRQn);
- 8000d6c: f997 3007 ldrsb.w r3, [r7, #7]
- 8000d70: 4618 mov r0, r3
- 8000d72: f7ff ff31 bl 8000bd8 <__NVIC_EnableIRQ>
-}
- 8000d76: bf00 nop
- 8000d78: 3708 adds r7, #8
- 8000d7a: 46bd mov sp, r7
- 8000d7c: bd80 pop {r7, pc}
-
-08000d7e <HAL_SYSTICK_Config>:
- * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
- * @retval status: - 0 Function succeeded.
- * - 1 Function failed.
- */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 8000d7e: b580 push {r7, lr}
- 8000d80: b082 sub sp, #8
- 8000d82: af00 add r7, sp, #0
- 8000d84: 6078 str r0, [r7, #4]
- return SysTick_Config(TicksNumb);
- 8000d86: 6878 ldr r0, [r7, #4]
- 8000d88: f7ff ffa2 bl 8000cd0 <SysTick_Config>
- 8000d8c: 4603 mov r3, r0
-}
- 8000d8e: 4618 mov r0, r3
- 8000d90: 3708 adds r7, #8
- 8000d92: 46bd mov sp, r7
- 8000d94: bd80 pop {r7, pc}
-
-08000d96 <HAL_DMA_Abort_IT>:
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
- 8000d96: b480 push {r7}
- 8000d98: b083 sub sp, #12
- 8000d9a: af00 add r7, sp, #0
- 8000d9c: 6078 str r0, [r7, #4]
- if(hdma->State != HAL_DMA_STATE_BUSY)
- 8000d9e: 687b ldr r3, [r7, #4]
- 8000da0: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
- 8000da4: b2db uxtb r3, r3
- 8000da6: 2b02 cmp r3, #2
- 8000da8: d004 beq.n 8000db4 <HAL_DMA_Abort_IT+0x1e>
- {
- hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- 8000daa: 687b ldr r3, [r7, #4]
- 8000dac: 2280 movs r2, #128 ; 0x80
- 8000dae: 655a str r2, [r3, #84] ; 0x54
- return HAL_ERROR;
- 8000db0: 2301 movs r3, #1
- 8000db2: e00c b.n 8000dce <HAL_DMA_Abort_IT+0x38>
- }
- else
- {
- /* Set Abort State */
- hdma->State = HAL_DMA_STATE_ABORT;
- 8000db4: 687b ldr r3, [r7, #4]
- 8000db6: 2205 movs r2, #5
- 8000db8: f883 2035 strb.w r2, [r3, #53] ; 0x35
-
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
- 8000dbc: 687b ldr r3, [r7, #4]
- 8000dbe: 681b ldr r3, [r3, #0]
- 8000dc0: 681a ldr r2, [r3, #0]
- 8000dc2: 687b ldr r3, [r7, #4]
- 8000dc4: 681b ldr r3, [r3, #0]
- 8000dc6: f022 0201 bic.w r2, r2, #1
- 8000dca: 601a str r2, [r3, #0]
- }
-
- return HAL_OK;
- 8000dcc: 2300 movs r3, #0
-}
- 8000dce: 4618 mov r0, r3
- 8000dd0: 370c adds r7, #12
- 8000dd2: 46bd mov sp, r7
- 8000dd4: f85d 7b04 ldr.w r7, [sp], #4
- 8000dd8: 4770 bx lr
- ...
-
-08000ddc <HAL_GPIO_Init>:
- * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8000ddc: b480 push {r7}
- 8000dde: b089 sub sp, #36 ; 0x24
- 8000de0: af00 add r7, sp, #0
- 8000de2: 6078 str r0, [r7, #4]
- 8000de4: 6039 str r1, [r7, #0]
- uint32_t position = 0x00;
- 8000de6: 2300 movs r3, #0
- 8000de8: 61fb str r3, [r7, #28]
- uint32_t ioposition = 0x00;
- 8000dea: 2300 movs r3, #0
- 8000dec: 617b str r3, [r7, #20]
- uint32_t iocurrent = 0x00;
- 8000dee: 2300 movs r3, #0
- 8000df0: 613b str r3, [r7, #16]
- uint32_t temp = 0x00;
- 8000df2: 2300 movs r3, #0
- 8000df4: 61bb str r3, [r7, #24]
- assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
- assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-
- /* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
- 8000df6: 2300 movs r3, #0
- 8000df8: 61fb str r3, [r7, #28]
- 8000dfa: e175 b.n 80010e8 <HAL_GPIO_Init+0x30c>
- {
- /* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- 8000dfc: 2201 movs r2, #1
- 8000dfe: 69fb ldr r3, [r7, #28]
- 8000e00: fa02 f303 lsl.w r3, r2, r3
- 8000e04: 617b str r3, [r7, #20]
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8000e06: 683b ldr r3, [r7, #0]
- 8000e08: 681b ldr r3, [r3, #0]
- 8000e0a: 697a ldr r2, [r7, #20]
- 8000e0c: 4013 ands r3, r2
- 8000e0e: 613b str r3, [r7, #16]
-
- if(iocurrent == ioposition)
- 8000e10: 693a ldr r2, [r7, #16]
- 8000e12: 697b ldr r3, [r7, #20]
- 8000e14: 429a cmp r2, r3
- 8000e16: f040 8164 bne.w 80010e2 <HAL_GPIO_Init+0x306>
- {
- /*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8000e1a: 683b ldr r3, [r7, #0]
- 8000e1c: 685b ldr r3, [r3, #4]
- 8000e1e: 2b02 cmp r3, #2
- 8000e20: d003 beq.n 8000e2a <HAL_GPIO_Init+0x4e>
- 8000e22: 683b ldr r3, [r7, #0]
- 8000e24: 685b ldr r3, [r3, #4]
- 8000e26: 2b12 cmp r3, #18
- 8000e28: d123 bne.n 8000e72 <HAL_GPIO_Init+0x96>
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- 8000e2a: 69fb ldr r3, [r7, #28]
- 8000e2c: 08da lsrs r2, r3, #3
- 8000e2e: 687b ldr r3, [r7, #4]
- 8000e30: 3208 adds r2, #8
- 8000e32: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 8000e36: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 8000e38: 69fb ldr r3, [r7, #28]
- 8000e3a: f003 0307 and.w r3, r3, #7
- 8000e3e: 009b lsls r3, r3, #2
- 8000e40: 220f movs r2, #15
- 8000e42: fa02 f303 lsl.w r3, r2, r3
- 8000e46: 43db mvns r3, r3
- 8000e48: 69ba ldr r2, [r7, #24]
- 8000e4a: 4013 ands r3, r2
- 8000e4c: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 8000e4e: 683b ldr r3, [r7, #0]
- 8000e50: 691a ldr r2, [r3, #16]
- 8000e52: 69fb ldr r3, [r7, #28]
- 8000e54: f003 0307 and.w r3, r3, #7
- 8000e58: 009b lsls r3, r3, #2
- 8000e5a: fa02 f303 lsl.w r3, r2, r3
- 8000e5e: 69ba ldr r2, [r7, #24]
- 8000e60: 4313 orrs r3, r2
- 8000e62: 61bb str r3, [r7, #24]
- GPIOx->AFR[position >> 3] = temp;
- 8000e64: 69fb ldr r3, [r7, #28]
- 8000e66: 08da lsrs r2, r3, #3
- 8000e68: 687b ldr r3, [r7, #4]
- 8000e6a: 3208 adds r2, #8
- 8000e6c: 69b9 ldr r1, [r7, #24]
- 8000e6e: f843 1022 str.w r1, [r3, r2, lsl #2]
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- 8000e72: 687b ldr r3, [r7, #4]
- 8000e74: 681b ldr r3, [r3, #0]
- 8000e76: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 8000e78: 69fb ldr r3, [r7, #28]
- 8000e7a: 005b lsls r3, r3, #1
- 8000e7c: 2203 movs r2, #3
- 8000e7e: fa02 f303 lsl.w r3, r2, r3
- 8000e82: 43db mvns r3, r3
- 8000e84: 69ba ldr r2, [r7, #24]
- 8000e86: 4013 ands r3, r2
- 8000e88: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 8000e8a: 683b ldr r3, [r7, #0]
- 8000e8c: 685b ldr r3, [r3, #4]
- 8000e8e: f003 0203 and.w r2, r3, #3
- 8000e92: 69fb ldr r3, [r7, #28]
- 8000e94: 005b lsls r3, r3, #1
- 8000e96: fa02 f303 lsl.w r3, r2, r3
- 8000e9a: 69ba ldr r2, [r7, #24]
- 8000e9c: 4313 orrs r3, r2
- 8000e9e: 61bb str r3, [r7, #24]
- GPIOx->MODER = temp;
- 8000ea0: 687b ldr r3, [r7, #4]
- 8000ea2: 69ba ldr r2, [r7, #24]
- 8000ea4: 601a str r2, [r3, #0]
-
- /* In case of Output or Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8000ea6: 683b ldr r3, [r7, #0]
- 8000ea8: 685b ldr r3, [r3, #4]
- 8000eaa: 2b01 cmp r3, #1
- 8000eac: d00b beq.n 8000ec6 <HAL_GPIO_Init+0xea>
- 8000eae: 683b ldr r3, [r7, #0]
- 8000eb0: 685b ldr r3, [r3, #4]
- 8000eb2: 2b02 cmp r3, #2
- 8000eb4: d007 beq.n 8000ec6 <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8000eb6: 683b ldr r3, [r7, #0]
- 8000eb8: 685b ldr r3, [r3, #4]
- if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8000eba: 2b11 cmp r3, #17
- 8000ebc: d003 beq.n 8000ec6 <HAL_GPIO_Init+0xea>
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8000ebe: 683b ldr r3, [r7, #0]
- 8000ec0: 685b ldr r3, [r3, #4]
- 8000ec2: 2b12 cmp r3, #18
- 8000ec4: d130 bne.n 8000f28 <HAL_GPIO_Init+0x14c>
- {
- /* Check the Speed parameter */
- assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
- /* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- 8000ec6: 687b ldr r3, [r7, #4]
- 8000ec8: 689b ldr r3, [r3, #8]
- 8000eca: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8000ecc: 69fb ldr r3, [r7, #28]
- 8000ece: 005b lsls r3, r3, #1
- 8000ed0: 2203 movs r2, #3
- 8000ed2: fa02 f303 lsl.w r3, r2, r3
- 8000ed6: 43db mvns r3, r3
- 8000ed8: 69ba ldr r2, [r7, #24]
- 8000eda: 4013 ands r3, r2
- 8000edc: 61bb str r3, [r7, #24]
- temp |= (GPIO_Init->Speed << (position * 2));
- 8000ede: 683b ldr r3, [r7, #0]
- 8000ee0: 68da ldr r2, [r3, #12]
- 8000ee2: 69fb ldr r3, [r7, #28]
- 8000ee4: 005b lsls r3, r3, #1
- 8000ee6: fa02 f303 lsl.w r3, r2, r3
- 8000eea: 69ba ldr r2, [r7, #24]
- 8000eec: 4313 orrs r3, r2
- 8000eee: 61bb str r3, [r7, #24]
- GPIOx->OSPEEDR = temp;
- 8000ef0: 687b ldr r3, [r7, #4]
- 8000ef2: 69ba ldr r2, [r7, #24]
- 8000ef4: 609a str r2, [r3, #8]
-
- /* Configure the IO Output Type */
- temp = GPIOx->OTYPER;
- 8000ef6: 687b ldr r3, [r7, #4]
- 8000ef8: 685b ldr r3, [r3, #4]
- 8000efa: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8000efc: 2201 movs r2, #1
- 8000efe: 69fb ldr r3, [r7, #28]
- 8000f00: fa02 f303 lsl.w r3, r2, r3
- 8000f04: 43db mvns r3, r3
- 8000f06: 69ba ldr r2, [r7, #24]
- 8000f08: 4013 ands r3, r2
- 8000f0a: 61bb str r3, [r7, #24]
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 8000f0c: 683b ldr r3, [r7, #0]
- 8000f0e: 685b ldr r3, [r3, #4]
- 8000f10: 091b lsrs r3, r3, #4
- 8000f12: f003 0201 and.w r2, r3, #1
- 8000f16: 69fb ldr r3, [r7, #28]
- 8000f18: fa02 f303 lsl.w r3, r2, r3
- 8000f1c: 69ba ldr r2, [r7, #24]
- 8000f1e: 4313 orrs r3, r2
- 8000f20: 61bb str r3, [r7, #24]
- GPIOx->OTYPER = temp;
- 8000f22: 687b ldr r3, [r7, #4]
- 8000f24: 69ba ldr r2, [r7, #24]
- 8000f26: 605a str r2, [r3, #4]
- }
-
- /* Activate the Pull-up or Pull down resistor for the current IO */
- temp = GPIOx->PUPDR;
- 8000f28: 687b ldr r3, [r7, #4]
- 8000f2a: 68db ldr r3, [r3, #12]
- 8000f2c: 61bb str r3, [r7, #24]
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 8000f2e: 69fb ldr r3, [r7, #28]
- 8000f30: 005b lsls r3, r3, #1
- 8000f32: 2203 movs r2, #3
- 8000f34: fa02 f303 lsl.w r3, r2, r3
- 8000f38: 43db mvns r3, r3
- 8000f3a: 69ba ldr r2, [r7, #24]
- 8000f3c: 4013 ands r3, r2
- 8000f3e: 61bb str r3, [r7, #24]
- temp |= ((GPIO_Init->Pull) << (position * 2));
- 8000f40: 683b ldr r3, [r7, #0]
- 8000f42: 689a ldr r2, [r3, #8]
- 8000f44: 69fb ldr r3, [r7, #28]
- 8000f46: 005b lsls r3, r3, #1
- 8000f48: fa02 f303 lsl.w r3, r2, r3
- 8000f4c: 69ba ldr r2, [r7, #24]
- 8000f4e: 4313 orrs r3, r2
- 8000f50: 61bb str r3, [r7, #24]
- GPIOx->PUPDR = temp;
- 8000f52: 687b ldr r3, [r7, #4]
- 8000f54: 69ba ldr r2, [r7, #24]
- 8000f56: 60da str r2, [r3, #12]
-
- /*--------------------- EXTI Mode Configuration ------------------------*/
- /* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 8000f58: 683b ldr r3, [r7, #0]
- 8000f5a: 685b ldr r3, [r3, #4]
- 8000f5c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000f60: 2b00 cmp r3, #0
- 8000f62: f000 80be beq.w 80010e2 <HAL_GPIO_Init+0x306>
- {
- /* Enable SYSCFG Clock */
- __HAL_RCC_SYSCFG_CLK_ENABLE();
- 8000f66: 4b65 ldr r3, [pc, #404] ; (80010fc <HAL_GPIO_Init+0x320>)
- 8000f68: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000f6a: 4a64 ldr r2, [pc, #400] ; (80010fc <HAL_GPIO_Init+0x320>)
- 8000f6c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000f70: 6453 str r3, [r2, #68] ; 0x44
- 8000f72: 4b62 ldr r3, [pc, #392] ; (80010fc <HAL_GPIO_Init+0x320>)
- 8000f74: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000f76: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8000f7a: 60fb str r3, [r7, #12]
- 8000f7c: 68fb ldr r3, [r7, #12]
-
- temp = SYSCFG->EXTICR[position >> 2];
- 8000f7e: 4a60 ldr r2, [pc, #384] ; (8001100 <HAL_GPIO_Init+0x324>)
- 8000f80: 69fb ldr r3, [r7, #28]
- 8000f82: 089b lsrs r3, r3, #2
- 8000f84: 3302 adds r3, #2
- 8000f86: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 8000f8a: 61bb str r3, [r7, #24]
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 8000f8c: 69fb ldr r3, [r7, #28]
- 8000f8e: f003 0303 and.w r3, r3, #3
- 8000f92: 009b lsls r3, r3, #2
- 8000f94: 220f movs r2, #15
- 8000f96: fa02 f303 lsl.w r3, r2, r3
- 8000f9a: 43db mvns r3, r3
- 8000f9c: 69ba ldr r2, [r7, #24]
- 8000f9e: 4013 ands r3, r2
- 8000fa0: 61bb str r3, [r7, #24]
- temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 8000fa2: 687b ldr r3, [r7, #4]
- 8000fa4: 4a57 ldr r2, [pc, #348] ; (8001104 <HAL_GPIO_Init+0x328>)
- 8000fa6: 4293 cmp r3, r2
- 8000fa8: d037 beq.n 800101a <HAL_GPIO_Init+0x23e>
- 8000faa: 687b ldr r3, [r7, #4]
- 8000fac: 4a56 ldr r2, [pc, #344] ; (8001108 <HAL_GPIO_Init+0x32c>)
- 8000fae: 4293 cmp r3, r2
- 8000fb0: d031 beq.n 8001016 <HAL_GPIO_Init+0x23a>
- 8000fb2: 687b ldr r3, [r7, #4]
- 8000fb4: 4a55 ldr r2, [pc, #340] ; (800110c <HAL_GPIO_Init+0x330>)
- 8000fb6: 4293 cmp r3, r2
- 8000fb8: d02b beq.n 8001012 <HAL_GPIO_Init+0x236>
- 8000fba: 687b ldr r3, [r7, #4]
- 8000fbc: 4a54 ldr r2, [pc, #336] ; (8001110 <HAL_GPIO_Init+0x334>)
- 8000fbe: 4293 cmp r3, r2
- 8000fc0: d025 beq.n 800100e <HAL_GPIO_Init+0x232>
- 8000fc2: 687b ldr r3, [r7, #4]
- 8000fc4: 4a53 ldr r2, [pc, #332] ; (8001114 <HAL_GPIO_Init+0x338>)
- 8000fc6: 4293 cmp r3, r2
- 8000fc8: d01f beq.n 800100a <HAL_GPIO_Init+0x22e>
- 8000fca: 687b ldr r3, [r7, #4]
- 8000fcc: 4a52 ldr r2, [pc, #328] ; (8001118 <HAL_GPIO_Init+0x33c>)
- 8000fce: 4293 cmp r3, r2
- 8000fd0: d019 beq.n 8001006 <HAL_GPIO_Init+0x22a>
- 8000fd2: 687b ldr r3, [r7, #4]
- 8000fd4: 4a51 ldr r2, [pc, #324] ; (800111c <HAL_GPIO_Init+0x340>)
- 8000fd6: 4293 cmp r3, r2
- 8000fd8: d013 beq.n 8001002 <HAL_GPIO_Init+0x226>
- 8000fda: 687b ldr r3, [r7, #4]
- 8000fdc: 4a50 ldr r2, [pc, #320] ; (8001120 <HAL_GPIO_Init+0x344>)
- 8000fde: 4293 cmp r3, r2
- 8000fe0: d00d beq.n 8000ffe <HAL_GPIO_Init+0x222>
- 8000fe2: 687b ldr r3, [r7, #4]
- 8000fe4: 4a4f ldr r2, [pc, #316] ; (8001124 <HAL_GPIO_Init+0x348>)
- 8000fe6: 4293 cmp r3, r2
- 8000fe8: d007 beq.n 8000ffa <HAL_GPIO_Init+0x21e>
- 8000fea: 687b ldr r3, [r7, #4]
- 8000fec: 4a4e ldr r2, [pc, #312] ; (8001128 <HAL_GPIO_Init+0x34c>)
- 8000fee: 4293 cmp r3, r2
- 8000ff0: d101 bne.n 8000ff6 <HAL_GPIO_Init+0x21a>
- 8000ff2: 2309 movs r3, #9
- 8000ff4: e012 b.n 800101c <HAL_GPIO_Init+0x240>
- 8000ff6: 230a movs r3, #10
- 8000ff8: e010 b.n 800101c <HAL_GPIO_Init+0x240>
- 8000ffa: 2308 movs r3, #8
- 8000ffc: e00e b.n 800101c <HAL_GPIO_Init+0x240>
- 8000ffe: 2307 movs r3, #7
- 8001000: e00c b.n 800101c <HAL_GPIO_Init+0x240>
- 8001002: 2306 movs r3, #6
- 8001004: e00a b.n 800101c <HAL_GPIO_Init+0x240>
- 8001006: 2305 movs r3, #5
- 8001008: e008 b.n 800101c <HAL_GPIO_Init+0x240>
- 800100a: 2304 movs r3, #4
- 800100c: e006 b.n 800101c <HAL_GPIO_Init+0x240>
- 800100e: 2303 movs r3, #3
- 8001010: e004 b.n 800101c <HAL_GPIO_Init+0x240>
- 8001012: 2302 movs r3, #2
- 8001014: e002 b.n 800101c <HAL_GPIO_Init+0x240>
- 8001016: 2301 movs r3, #1
- 8001018: e000 b.n 800101c <HAL_GPIO_Init+0x240>
- 800101a: 2300 movs r3, #0
- 800101c: 69fa ldr r2, [r7, #28]
- 800101e: f002 0203 and.w r2, r2, #3
- 8001022: 0092 lsls r2, r2, #2
- 8001024: 4093 lsls r3, r2
- 8001026: 69ba ldr r2, [r7, #24]
- 8001028: 4313 orrs r3, r2
- 800102a: 61bb str r3, [r7, #24]
- SYSCFG->EXTICR[position >> 2] = temp;
- 800102c: 4934 ldr r1, [pc, #208] ; (8001100 <HAL_GPIO_Init+0x324>)
- 800102e: 69fb ldr r3, [r7, #28]
- 8001030: 089b lsrs r3, r3, #2
- 8001032: 3302 adds r3, #2
- 8001034: 69ba ldr r2, [r7, #24]
- 8001036: f841 2023 str.w r2, [r1, r3, lsl #2]
-
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- 800103a: 4b3c ldr r3, [pc, #240] ; (800112c <HAL_GPIO_Init+0x350>)
- 800103c: 681b ldr r3, [r3, #0]
- 800103e: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8001040: 693b ldr r3, [r7, #16]
- 8001042: 43db mvns r3, r3
- 8001044: 69ba ldr r2, [r7, #24]
- 8001046: 4013 ands r3, r2
- 8001048: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 800104a: 683b ldr r3, [r7, #0]
- 800104c: 685b ldr r3, [r3, #4]
- 800104e: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8001052: 2b00 cmp r3, #0
- 8001054: d003 beq.n 800105e <HAL_GPIO_Init+0x282>
- {
- temp |= iocurrent;
- 8001056: 69ba ldr r2, [r7, #24]
- 8001058: 693b ldr r3, [r7, #16]
- 800105a: 4313 orrs r3, r2
- 800105c: 61bb str r3, [r7, #24]
- }
- EXTI->IMR = temp;
- 800105e: 4a33 ldr r2, [pc, #204] ; (800112c <HAL_GPIO_Init+0x350>)
- 8001060: 69bb ldr r3, [r7, #24]
- 8001062: 6013 str r3, [r2, #0]
-
- temp = EXTI->EMR;
- 8001064: 4b31 ldr r3, [pc, #196] ; (800112c <HAL_GPIO_Init+0x350>)
- 8001066: 685b ldr r3, [r3, #4]
- 8001068: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 800106a: 693b ldr r3, [r7, #16]
- 800106c: 43db mvns r3, r3
- 800106e: 69ba ldr r2, [r7, #24]
- 8001070: 4013 ands r3, r2
- 8001072: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 8001074: 683b ldr r3, [r7, #0]
- 8001076: 685b ldr r3, [r3, #4]
- 8001078: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800107c: 2b00 cmp r3, #0
- 800107e: d003 beq.n 8001088 <HAL_GPIO_Init+0x2ac>
- {
- temp |= iocurrent;
- 8001080: 69ba ldr r2, [r7, #24]
- 8001082: 693b ldr r3, [r7, #16]
- 8001084: 4313 orrs r3, r2
- 8001086: 61bb str r3, [r7, #24]
- }
- EXTI->EMR = temp;
- 8001088: 4a28 ldr r2, [pc, #160] ; (800112c <HAL_GPIO_Init+0x350>)
- 800108a: 69bb ldr r3, [r7, #24]
- 800108c: 6053 str r3, [r2, #4]
-
- /* Clear Rising Falling edge configuration */
- temp = EXTI->RTSR;
- 800108e: 4b27 ldr r3, [pc, #156] ; (800112c <HAL_GPIO_Init+0x350>)
- 8001090: 689b ldr r3, [r3, #8]
- 8001092: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 8001094: 693b ldr r3, [r7, #16]
- 8001096: 43db mvns r3, r3
- 8001098: 69ba ldr r2, [r7, #24]
- 800109a: 4013 ands r3, r2
- 800109c: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 800109e: 683b ldr r3, [r7, #0]
- 80010a0: 685b ldr r3, [r3, #4]
- 80010a2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 80010a6: 2b00 cmp r3, #0
- 80010a8: d003 beq.n 80010b2 <HAL_GPIO_Init+0x2d6>
- {
- temp |= iocurrent;
- 80010aa: 69ba ldr r2, [r7, #24]
- 80010ac: 693b ldr r3, [r7, #16]
- 80010ae: 4313 orrs r3, r2
- 80010b0: 61bb str r3, [r7, #24]
- }
- EXTI->RTSR = temp;
- 80010b2: 4a1e ldr r2, [pc, #120] ; (800112c <HAL_GPIO_Init+0x350>)
- 80010b4: 69bb ldr r3, [r7, #24]
- 80010b6: 6093 str r3, [r2, #8]
-
- temp = EXTI->FTSR;
- 80010b8: 4b1c ldr r3, [pc, #112] ; (800112c <HAL_GPIO_Init+0x350>)
- 80010ba: 68db ldr r3, [r3, #12]
- 80010bc: 61bb str r3, [r7, #24]
- temp &= ~((uint32_t)iocurrent);
- 80010be: 693b ldr r3, [r7, #16]
- 80010c0: 43db mvns r3, r3
- 80010c2: 69ba ldr r2, [r7, #24]
- 80010c4: 4013 ands r3, r2
- 80010c6: 61bb str r3, [r7, #24]
- if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 80010c8: 683b ldr r3, [r7, #0]
- 80010ca: 685b ldr r3, [r3, #4]
- 80010cc: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 80010d0: 2b00 cmp r3, #0
- 80010d2: d003 beq.n 80010dc <HAL_GPIO_Init+0x300>
- {
- temp |= iocurrent;
- 80010d4: 69ba ldr r2, [r7, #24]
- 80010d6: 693b ldr r3, [r7, #16]
- 80010d8: 4313 orrs r3, r2
- 80010da: 61bb str r3, [r7, #24]
- }
- EXTI->FTSR = temp;
- 80010dc: 4a13 ldr r2, [pc, #76] ; (800112c <HAL_GPIO_Init+0x350>)
- 80010de: 69bb ldr r3, [r7, #24]
- 80010e0: 60d3 str r3, [r2, #12]
- for(position = 0; position < GPIO_NUMBER; position++)
- 80010e2: 69fb ldr r3, [r7, #28]
- 80010e4: 3301 adds r3, #1
- 80010e6: 61fb str r3, [r7, #28]
- 80010e8: 69fb ldr r3, [r7, #28]
- 80010ea: 2b0f cmp r3, #15
- 80010ec: f67f ae86 bls.w 8000dfc <HAL_GPIO_Init+0x20>
- }
- }
- }
-}
- 80010f0: bf00 nop
- 80010f2: 3724 adds r7, #36 ; 0x24
- 80010f4: 46bd mov sp, r7
- 80010f6: f85d 7b04 ldr.w r7, [sp], #4
- 80010fa: 4770 bx lr
- 80010fc: 40023800 .word 0x40023800
- 8001100: 40013800 .word 0x40013800
- 8001104: 40020000 .word 0x40020000
- 8001108: 40020400 .word 0x40020400
- 800110c: 40020800 .word 0x40020800
- 8001110: 40020c00 .word 0x40020c00
- 8001114: 40021000 .word 0x40021000
- 8001118: 40021400 .word 0x40021400
- 800111c: 40021800 .word 0x40021800
- 8001120: 40021c00 .word 0x40021c00
- 8001124: 40022000 .word 0x40022000
- 8001128: 40022400 .word 0x40022400
- 800112c: 40013c00 .word 0x40013c00
-
-08001130 <HAL_RCC_OscConfig>:
- * supported by this function. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- 8001130: b580 push {r7, lr}
- 8001132: b086 sub sp, #24
- 8001134: af00 add r7, sp, #0
- 8001136: 6078 str r0, [r7, #4]
- uint32_t tickstart;
- FlagStatus pwrclkchanged = RESET;
- 8001138: 2300 movs r3, #0
- 800113a: 75fb strb r3, [r7, #23]
-
- /* Check Null pointer */
- if(RCC_OscInitStruct == NULL)
- 800113c: 687b ldr r3, [r7, #4]
- 800113e: 2b00 cmp r3, #0
- 8001140: d101 bne.n 8001146 <HAL_RCC_OscConfig+0x16>
- {
- return HAL_ERROR;
- 8001142: 2301 movs r3, #1
- 8001144: e25e b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8001146: 687b ldr r3, [r7, #4]
- 8001148: 681b ldr r3, [r3, #0]
- 800114a: f003 0301 and.w r3, r3, #1
- 800114e: 2b00 cmp r3, #0
- 8001150: f000 8087 beq.w 8001262 <HAL_RCC_OscConfig+0x132>
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8001154: 4b96 ldr r3, [pc, #600] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001156: 689b ldr r3, [r3, #8]
- 8001158: f003 030c and.w r3, r3, #12
- 800115c: 2b04 cmp r3, #4
- 800115e: d00c beq.n 800117a <HAL_RCC_OscConfig+0x4a>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 8001160: 4b93 ldr r3, [pc, #588] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001162: 689b ldr r3, [r3, #8]
- 8001164: f003 030c and.w r3, r3, #12
- 8001168: 2b08 cmp r3, #8
- 800116a: d112 bne.n 8001192 <HAL_RCC_OscConfig+0x62>
- 800116c: 4b90 ldr r3, [pc, #576] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800116e: 685b ldr r3, [r3, #4]
- 8001170: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8001174: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8001178: d10b bne.n 8001192 <HAL_RCC_OscConfig+0x62>
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 800117a: 4b8d ldr r3, [pc, #564] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800117c: 681b ldr r3, [r3, #0]
- 800117e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8001182: 2b00 cmp r3, #0
- 8001184: d06c beq.n 8001260 <HAL_RCC_OscConfig+0x130>
- 8001186: 687b ldr r3, [r7, #4]
- 8001188: 685b ldr r3, [r3, #4]
- 800118a: 2b00 cmp r3, #0
- 800118c: d168 bne.n 8001260 <HAL_RCC_OscConfig+0x130>
- {
- return HAL_ERROR;
- 800118e: 2301 movs r3, #1
- 8001190: e238 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 8001192: 687b ldr r3, [r7, #4]
- 8001194: 685b ldr r3, [r3, #4]
- 8001196: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800119a: d106 bne.n 80011aa <HAL_RCC_OscConfig+0x7a>
- 800119c: 4b84 ldr r3, [pc, #528] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800119e: 681b ldr r3, [r3, #0]
- 80011a0: 4a83 ldr r2, [pc, #524] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011a2: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 80011a6: 6013 str r3, [r2, #0]
- 80011a8: e02e b.n 8001208 <HAL_RCC_OscConfig+0xd8>
- 80011aa: 687b ldr r3, [r7, #4]
- 80011ac: 685b ldr r3, [r3, #4]
- 80011ae: 2b00 cmp r3, #0
- 80011b0: d10c bne.n 80011cc <HAL_RCC_OscConfig+0x9c>
- 80011b2: 4b7f ldr r3, [pc, #508] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011b4: 681b ldr r3, [r3, #0]
- 80011b6: 4a7e ldr r2, [pc, #504] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011b8: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 80011bc: 6013 str r3, [r2, #0]
- 80011be: 4b7c ldr r3, [pc, #496] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011c0: 681b ldr r3, [r3, #0]
- 80011c2: 4a7b ldr r2, [pc, #492] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011c4: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 80011c8: 6013 str r3, [r2, #0]
- 80011ca: e01d b.n 8001208 <HAL_RCC_OscConfig+0xd8>
- 80011cc: 687b ldr r3, [r7, #4]
- 80011ce: 685b ldr r3, [r3, #4]
- 80011d0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 80011d4: d10c bne.n 80011f0 <HAL_RCC_OscConfig+0xc0>
- 80011d6: 4b76 ldr r3, [pc, #472] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011d8: 681b ldr r3, [r3, #0]
- 80011da: 4a75 ldr r2, [pc, #468] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011dc: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 80011e0: 6013 str r3, [r2, #0]
- 80011e2: 4b73 ldr r3, [pc, #460] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011e4: 681b ldr r3, [r3, #0]
- 80011e6: 4a72 ldr r2, [pc, #456] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011e8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 80011ec: 6013 str r3, [r2, #0]
- 80011ee: e00b b.n 8001208 <HAL_RCC_OscConfig+0xd8>
- 80011f0: 4b6f ldr r3, [pc, #444] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011f2: 681b ldr r3, [r3, #0]
- 80011f4: 4a6e ldr r2, [pc, #440] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011f6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 80011fa: 6013 str r3, [r2, #0]
- 80011fc: 4b6c ldr r3, [pc, #432] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80011fe: 681b ldr r3, [r3, #0]
- 8001200: 4a6b ldr r2, [pc, #428] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001202: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8001206: 6013 str r3, [r2, #0]
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8001208: 687b ldr r3, [r7, #4]
- 800120a: 685b ldr r3, [r3, #4]
- 800120c: 2b00 cmp r3, #0
- 800120e: d013 beq.n 8001238 <HAL_RCC_OscConfig+0x108>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001210: f7ff fca4 bl 8000b5c <HAL_GetTick>
- 8001214: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8001216: e008 b.n 800122a <HAL_RCC_OscConfig+0xfa>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8001218: f7ff fca0 bl 8000b5c <HAL_GetTick>
- 800121c: 4602 mov r2, r0
- 800121e: 693b ldr r3, [r7, #16]
- 8001220: 1ad3 subs r3, r2, r3
- 8001222: 2b64 cmp r3, #100 ; 0x64
- 8001224: d901 bls.n 800122a <HAL_RCC_OscConfig+0xfa>
- {
- return HAL_TIMEOUT;
- 8001226: 2303 movs r3, #3
- 8001228: e1ec b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800122a: 4b61 ldr r3, [pc, #388] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800122c: 681b ldr r3, [r3, #0]
- 800122e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8001232: 2b00 cmp r3, #0
- 8001234: d0f0 beq.n 8001218 <HAL_RCC_OscConfig+0xe8>
- 8001236: e014 b.n 8001262 <HAL_RCC_OscConfig+0x132>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001238: f7ff fc90 bl 8000b5c <HAL_GetTick>
- 800123c: 6138 str r0, [r7, #16]
-
- /* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 800123e: e008 b.n 8001252 <HAL_RCC_OscConfig+0x122>
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8001240: f7ff fc8c bl 8000b5c <HAL_GetTick>
- 8001244: 4602 mov r2, r0
- 8001246: 693b ldr r3, [r7, #16]
- 8001248: 1ad3 subs r3, r2, r3
- 800124a: 2b64 cmp r3, #100 ; 0x64
- 800124c: d901 bls.n 8001252 <HAL_RCC_OscConfig+0x122>
- {
- return HAL_TIMEOUT;
- 800124e: 2303 movs r3, #3
- 8001250: e1d8 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8001252: 4b57 ldr r3, [pc, #348] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001254: 681b ldr r3, [r3, #0]
- 8001256: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800125a: 2b00 cmp r3, #0
- 800125c: d1f0 bne.n 8001240 <HAL_RCC_OscConfig+0x110>
- 800125e: e000 b.n 8001262 <HAL_RCC_OscConfig+0x132>
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8001260: bf00 nop
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8001262: 687b ldr r3, [r7, #4]
- 8001264: 681b ldr r3, [r3, #0]
- 8001266: f003 0302 and.w r3, r3, #2
- 800126a: 2b00 cmp r3, #0
- 800126c: d069 beq.n 8001342 <HAL_RCC_OscConfig+0x212>
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 800126e: 4b50 ldr r3, [pc, #320] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001270: 689b ldr r3, [r3, #8]
- 8001272: f003 030c and.w r3, r3, #12
- 8001276: 2b00 cmp r3, #0
- 8001278: d00b beq.n 8001292 <HAL_RCC_OscConfig+0x162>
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 800127a: 4b4d ldr r3, [pc, #308] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800127c: 689b ldr r3, [r3, #8]
- 800127e: f003 030c and.w r3, r3, #12
- 8001282: 2b08 cmp r3, #8
- 8001284: d11c bne.n 80012c0 <HAL_RCC_OscConfig+0x190>
- 8001286: 4b4a ldr r3, [pc, #296] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001288: 685b ldr r3, [r3, #4]
- 800128a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800128e: 2b00 cmp r3, #0
- 8001290: d116 bne.n 80012c0 <HAL_RCC_OscConfig+0x190>
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8001292: 4b47 ldr r3, [pc, #284] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001294: 681b ldr r3, [r3, #0]
- 8001296: f003 0302 and.w r3, r3, #2
- 800129a: 2b00 cmp r3, #0
- 800129c: d005 beq.n 80012aa <HAL_RCC_OscConfig+0x17a>
- 800129e: 687b ldr r3, [r7, #4]
- 80012a0: 68db ldr r3, [r3, #12]
- 80012a2: 2b01 cmp r3, #1
- 80012a4: d001 beq.n 80012aa <HAL_RCC_OscConfig+0x17a>
- {
- return HAL_ERROR;
- 80012a6: 2301 movs r3, #1
- 80012a8: e1ac b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80012aa: 4b41 ldr r3, [pc, #260] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80012ac: 681b ldr r3, [r3, #0]
- 80012ae: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 80012b2: 687b ldr r3, [r7, #4]
- 80012b4: 691b ldr r3, [r3, #16]
- 80012b6: 00db lsls r3, r3, #3
- 80012b8: 493d ldr r1, [pc, #244] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80012ba: 4313 orrs r3, r2
- 80012bc: 600b str r3, [r1, #0]
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80012be: e040 b.n 8001342 <HAL_RCC_OscConfig+0x212>
- }
- }
- else
- {
- /* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 80012c0: 687b ldr r3, [r7, #4]
- 80012c2: 68db ldr r3, [r3, #12]
- 80012c4: 2b00 cmp r3, #0
- 80012c6: d023 beq.n 8001310 <HAL_RCC_OscConfig+0x1e0>
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
- 80012c8: 4b39 ldr r3, [pc, #228] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80012ca: 681b ldr r3, [r3, #0]
- 80012cc: 4a38 ldr r2, [pc, #224] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80012ce: f043 0301 orr.w r3, r3, #1
- 80012d2: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80012d4: f7ff fc42 bl 8000b5c <HAL_GetTick>
- 80012d8: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80012da: e008 b.n 80012ee <HAL_RCC_OscConfig+0x1be>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80012dc: f7ff fc3e bl 8000b5c <HAL_GetTick>
- 80012e0: 4602 mov r2, r0
- 80012e2: 693b ldr r3, [r7, #16]
- 80012e4: 1ad3 subs r3, r2, r3
- 80012e6: 2b02 cmp r3, #2
- 80012e8: d901 bls.n 80012ee <HAL_RCC_OscConfig+0x1be>
- {
- return HAL_TIMEOUT;
- 80012ea: 2303 movs r3, #3
- 80012ec: e18a b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80012ee: 4b30 ldr r3, [pc, #192] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80012f0: 681b ldr r3, [r3, #0]
- 80012f2: f003 0302 and.w r3, r3, #2
- 80012f6: 2b00 cmp r3, #0
- 80012f8: d0f0 beq.n 80012dc <HAL_RCC_OscConfig+0x1ac>
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80012fa: 4b2d ldr r3, [pc, #180] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 80012fc: 681b ldr r3, [r3, #0]
- 80012fe: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 8001302: 687b ldr r3, [r7, #4]
- 8001304: 691b ldr r3, [r3, #16]
- 8001306: 00db lsls r3, r3, #3
- 8001308: 4929 ldr r1, [pc, #164] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800130a: 4313 orrs r3, r2
- 800130c: 600b str r3, [r1, #0]
- 800130e: e018 b.n 8001342 <HAL_RCC_OscConfig+0x212>
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
- 8001310: 4b27 ldr r3, [pc, #156] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001312: 681b ldr r3, [r3, #0]
- 8001314: 4a26 ldr r2, [pc, #152] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001316: f023 0301 bic.w r3, r3, #1
- 800131a: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800131c: f7ff fc1e bl 8000b5c <HAL_GetTick>
- 8001320: 6138 str r0, [r7, #16]
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001322: e008 b.n 8001336 <HAL_RCC_OscConfig+0x206>
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8001324: f7ff fc1a bl 8000b5c <HAL_GetTick>
- 8001328: 4602 mov r2, r0
- 800132a: 693b ldr r3, [r7, #16]
- 800132c: 1ad3 subs r3, r2, r3
- 800132e: 2b02 cmp r3, #2
- 8001330: d901 bls.n 8001336 <HAL_RCC_OscConfig+0x206>
- {
- return HAL_TIMEOUT;
- 8001332: 2303 movs r3, #3
- 8001334: e166 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001336: 4b1e ldr r3, [pc, #120] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001338: 681b ldr r3, [r3, #0]
- 800133a: f003 0302 and.w r3, r3, #2
- 800133e: 2b00 cmp r3, #0
- 8001340: d1f0 bne.n 8001324 <HAL_RCC_OscConfig+0x1f4>
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8001342: 687b ldr r3, [r7, #4]
- 8001344: 681b ldr r3, [r3, #0]
- 8001346: f003 0308 and.w r3, r3, #8
- 800134a: 2b00 cmp r3, #0
- 800134c: d038 beq.n 80013c0 <HAL_RCC_OscConfig+0x290>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 800134e: 687b ldr r3, [r7, #4]
- 8001350: 695b ldr r3, [r3, #20]
- 8001352: 2b00 cmp r3, #0
- 8001354: d019 beq.n 800138a <HAL_RCC_OscConfig+0x25a>
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
- 8001356: 4b16 ldr r3, [pc, #88] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001358: 6f5b ldr r3, [r3, #116] ; 0x74
- 800135a: 4a15 ldr r2, [pc, #84] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800135c: f043 0301 orr.w r3, r3, #1
- 8001360: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001362: f7ff fbfb bl 8000b5c <HAL_GetTick>
- 8001366: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8001368: e008 b.n 800137c <HAL_RCC_OscConfig+0x24c>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800136a: f7ff fbf7 bl 8000b5c <HAL_GetTick>
- 800136e: 4602 mov r2, r0
- 8001370: 693b ldr r3, [r7, #16]
- 8001372: 1ad3 subs r3, r2, r3
- 8001374: 2b02 cmp r3, #2
- 8001376: d901 bls.n 800137c <HAL_RCC_OscConfig+0x24c>
- {
- return HAL_TIMEOUT;
- 8001378: 2303 movs r3, #3
- 800137a: e143 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 800137c: 4b0c ldr r3, [pc, #48] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800137e: 6f5b ldr r3, [r3, #116] ; 0x74
- 8001380: f003 0302 and.w r3, r3, #2
- 8001384: 2b00 cmp r3, #0
- 8001386: d0f0 beq.n 800136a <HAL_RCC_OscConfig+0x23a>
- 8001388: e01a b.n 80013c0 <HAL_RCC_OscConfig+0x290>
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
- 800138a: 4b09 ldr r3, [pc, #36] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 800138c: 6f5b ldr r3, [r3, #116] ; 0x74
- 800138e: 4a08 ldr r2, [pc, #32] ; (80013b0 <HAL_RCC_OscConfig+0x280>)
- 8001390: f023 0301 bic.w r3, r3, #1
- 8001394: 6753 str r3, [r2, #116] ; 0x74
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001396: f7ff fbe1 bl 8000b5c <HAL_GetTick>
- 800139a: 6138 str r0, [r7, #16]
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 800139c: e00a b.n 80013b4 <HAL_RCC_OscConfig+0x284>
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800139e: f7ff fbdd bl 8000b5c <HAL_GetTick>
- 80013a2: 4602 mov r2, r0
- 80013a4: 693b ldr r3, [r7, #16]
- 80013a6: 1ad3 subs r3, r2, r3
- 80013a8: 2b02 cmp r3, #2
- 80013aa: d903 bls.n 80013b4 <HAL_RCC_OscConfig+0x284>
- {
- return HAL_TIMEOUT;
- 80013ac: 2303 movs r3, #3
- 80013ae: e129 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- 80013b0: 40023800 .word 0x40023800
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 80013b4: 4b95 ldr r3, [pc, #596] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80013b6: 6f5b ldr r3, [r3, #116] ; 0x74
- 80013b8: f003 0302 and.w r3, r3, #2
- 80013bc: 2b00 cmp r3, #0
- 80013be: d1ee bne.n 800139e <HAL_RCC_OscConfig+0x26e>
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 80013c0: 687b ldr r3, [r7, #4]
- 80013c2: 681b ldr r3, [r3, #0]
- 80013c4: f003 0304 and.w r3, r3, #4
- 80013c8: 2b00 cmp r3, #0
- 80013ca: f000 80a4 beq.w 8001516 <HAL_RCC_OscConfig+0x3e6>
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Update LSE configuration in Backup Domain control register */
- /* Requires to enable write access to Backup Domain of necessary */
- if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80013ce: 4b8f ldr r3, [pc, #572] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80013d0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80013d2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80013d6: 2b00 cmp r3, #0
- 80013d8: d10d bne.n 80013f6 <HAL_RCC_OscConfig+0x2c6>
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 80013da: 4b8c ldr r3, [pc, #560] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80013dc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80013de: 4a8b ldr r2, [pc, #556] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80013e0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80013e4: 6413 str r3, [r2, #64] ; 0x40
- 80013e6: 4b89 ldr r3, [pc, #548] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80013e8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80013ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80013ee: 60fb str r3, [r7, #12]
- 80013f0: 68fb ldr r3, [r7, #12]
- pwrclkchanged = SET;
- 80013f2: 2301 movs r3, #1
- 80013f4: 75fb strb r3, [r7, #23]
- }
-
- if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80013f6: 4b86 ldr r3, [pc, #536] ; (8001610 <HAL_RCC_OscConfig+0x4e0>)
- 80013f8: 681b ldr r3, [r3, #0]
- 80013fa: f403 7380 and.w r3, r3, #256 ; 0x100
- 80013fe: 2b00 cmp r3, #0
- 8001400: d118 bne.n 8001434 <HAL_RCC_OscConfig+0x304>
- {
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 8001402: 4b83 ldr r3, [pc, #524] ; (8001610 <HAL_RCC_OscConfig+0x4e0>)
- 8001404: 681b ldr r3, [r3, #0]
- 8001406: 4a82 ldr r2, [pc, #520] ; (8001610 <HAL_RCC_OscConfig+0x4e0>)
- 8001408: f443 7380 orr.w r3, r3, #256 ; 0x100
- 800140c: 6013 str r3, [r2, #0]
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
- 800140e: f7ff fba5 bl 8000b5c <HAL_GetTick>
- 8001412: 6138 str r0, [r7, #16]
-
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8001414: e008 b.n 8001428 <HAL_RCC_OscConfig+0x2f8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 8001416: f7ff fba1 bl 8000b5c <HAL_GetTick>
- 800141a: 4602 mov r2, r0
- 800141c: 693b ldr r3, [r7, #16]
- 800141e: 1ad3 subs r3, r2, r3
- 8001420: 2b64 cmp r3, #100 ; 0x64
- 8001422: d901 bls.n 8001428 <HAL_RCC_OscConfig+0x2f8>
- {
- return HAL_TIMEOUT;
- 8001424: 2303 movs r3, #3
- 8001426: e0ed b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8001428: 4b79 ldr r3, [pc, #484] ; (8001610 <HAL_RCC_OscConfig+0x4e0>)
- 800142a: 681b ldr r3, [r3, #0]
- 800142c: f403 7380 and.w r3, r3, #256 ; 0x100
- 8001430: 2b00 cmp r3, #0
- 8001432: d0f0 beq.n 8001416 <HAL_RCC_OscConfig+0x2e6>
- }
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8001434: 687b ldr r3, [r7, #4]
- 8001436: 689b ldr r3, [r3, #8]
- 8001438: 2b01 cmp r3, #1
- 800143a: d106 bne.n 800144a <HAL_RCC_OscConfig+0x31a>
- 800143c: 4b73 ldr r3, [pc, #460] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 800143e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001440: 4a72 ldr r2, [pc, #456] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001442: f043 0301 orr.w r3, r3, #1
- 8001446: 6713 str r3, [r2, #112] ; 0x70
- 8001448: e02d b.n 80014a6 <HAL_RCC_OscConfig+0x376>
- 800144a: 687b ldr r3, [r7, #4]
- 800144c: 689b ldr r3, [r3, #8]
- 800144e: 2b00 cmp r3, #0
- 8001450: d10c bne.n 800146c <HAL_RCC_OscConfig+0x33c>
- 8001452: 4b6e ldr r3, [pc, #440] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001454: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001456: 4a6d ldr r2, [pc, #436] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001458: f023 0301 bic.w r3, r3, #1
- 800145c: 6713 str r3, [r2, #112] ; 0x70
- 800145e: 4b6b ldr r3, [pc, #428] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001460: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001462: 4a6a ldr r2, [pc, #424] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001464: f023 0304 bic.w r3, r3, #4
- 8001468: 6713 str r3, [r2, #112] ; 0x70
- 800146a: e01c b.n 80014a6 <HAL_RCC_OscConfig+0x376>
- 800146c: 687b ldr r3, [r7, #4]
- 800146e: 689b ldr r3, [r3, #8]
- 8001470: 2b05 cmp r3, #5
- 8001472: d10c bne.n 800148e <HAL_RCC_OscConfig+0x35e>
- 8001474: 4b65 ldr r3, [pc, #404] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001476: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001478: 4a64 ldr r2, [pc, #400] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 800147a: f043 0304 orr.w r3, r3, #4
- 800147e: 6713 str r3, [r2, #112] ; 0x70
- 8001480: 4b62 ldr r3, [pc, #392] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001482: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001484: 4a61 ldr r2, [pc, #388] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001486: f043 0301 orr.w r3, r3, #1
- 800148a: 6713 str r3, [r2, #112] ; 0x70
- 800148c: e00b b.n 80014a6 <HAL_RCC_OscConfig+0x376>
- 800148e: 4b5f ldr r3, [pc, #380] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001490: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001492: 4a5e ldr r2, [pc, #376] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001494: f023 0301 bic.w r3, r3, #1
- 8001498: 6713 str r3, [r2, #112] ; 0x70
- 800149a: 4b5c ldr r3, [pc, #368] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 800149c: 6f1b ldr r3, [r3, #112] ; 0x70
- 800149e: 4a5b ldr r2, [pc, #364] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80014a0: f023 0304 bic.w r3, r3, #4
- 80014a4: 6713 str r3, [r2, #112] ; 0x70
- /* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 80014a6: 687b ldr r3, [r7, #4]
- 80014a8: 689b ldr r3, [r3, #8]
- 80014aa: 2b00 cmp r3, #0
- 80014ac: d015 beq.n 80014da <HAL_RCC_OscConfig+0x3aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80014ae: f7ff fb55 bl 8000b5c <HAL_GetTick>
- 80014b2: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80014b4: e00a b.n 80014cc <HAL_RCC_OscConfig+0x39c>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80014b6: f7ff fb51 bl 8000b5c <HAL_GetTick>
- 80014ba: 4602 mov r2, r0
- 80014bc: 693b ldr r3, [r7, #16]
- 80014be: 1ad3 subs r3, r2, r3
- 80014c0: f241 3288 movw r2, #5000 ; 0x1388
- 80014c4: 4293 cmp r3, r2
- 80014c6: d901 bls.n 80014cc <HAL_RCC_OscConfig+0x39c>
- {
- return HAL_TIMEOUT;
- 80014c8: 2303 movs r3, #3
- 80014ca: e09b b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80014cc: 4b4f ldr r3, [pc, #316] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80014ce: 6f1b ldr r3, [r3, #112] ; 0x70
- 80014d0: f003 0302 and.w r3, r3, #2
- 80014d4: 2b00 cmp r3, #0
- 80014d6: d0ee beq.n 80014b6 <HAL_RCC_OscConfig+0x386>
- 80014d8: e014 b.n 8001504 <HAL_RCC_OscConfig+0x3d4>
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80014da: f7ff fb3f bl 8000b5c <HAL_GetTick>
- 80014de: 6138 str r0, [r7, #16]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80014e0: e00a b.n 80014f8 <HAL_RCC_OscConfig+0x3c8>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80014e2: f7ff fb3b bl 8000b5c <HAL_GetTick>
- 80014e6: 4602 mov r2, r0
- 80014e8: 693b ldr r3, [r7, #16]
- 80014ea: 1ad3 subs r3, r2, r3
- 80014ec: f241 3288 movw r2, #5000 ; 0x1388
- 80014f0: 4293 cmp r3, r2
- 80014f2: d901 bls.n 80014f8 <HAL_RCC_OscConfig+0x3c8>
- {
- return HAL_TIMEOUT;
- 80014f4: 2303 movs r3, #3
- 80014f6: e085 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80014f8: 4b44 ldr r3, [pc, #272] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80014fa: 6f1b ldr r3, [r3, #112] ; 0x70
- 80014fc: f003 0302 and.w r3, r3, #2
- 8001500: 2b00 cmp r3, #0
- 8001502: d1ee bne.n 80014e2 <HAL_RCC_OscConfig+0x3b2>
- }
- }
- }
-
- /* Restore clock configuration if changed */
- if(pwrclkchanged == SET)
- 8001504: 7dfb ldrb r3, [r7, #23]
- 8001506: 2b01 cmp r3, #1
- 8001508: d105 bne.n 8001516 <HAL_RCC_OscConfig+0x3e6>
- {
- __HAL_RCC_PWR_CLK_DISABLE();
- 800150a: 4b40 ldr r3, [pc, #256] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 800150c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800150e: 4a3f ldr r2, [pc, #252] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001510: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8001514: 6413 str r3, [r2, #64] ; 0x40
- }
- }
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8001516: 687b ldr r3, [r7, #4]
- 8001518: 699b ldr r3, [r3, #24]
- 800151a: 2b00 cmp r3, #0
- 800151c: d071 beq.n 8001602 <HAL_RCC_OscConfig+0x4d2>
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 800151e: 4b3b ldr r3, [pc, #236] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001520: 689b ldr r3, [r3, #8]
- 8001522: f003 030c and.w r3, r3, #12
- 8001526: 2b08 cmp r3, #8
- 8001528: d069 beq.n 80015fe <HAL_RCC_OscConfig+0x4ce>
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 800152a: 687b ldr r3, [r7, #4]
- 800152c: 699b ldr r3, [r3, #24]
- 800152e: 2b02 cmp r3, #2
- 8001530: d14b bne.n 80015ca <HAL_RCC_OscConfig+0x49a>
-#if defined (RCC_PLLCFGR_PLLR)
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-#endif
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 8001532: 4b36 ldr r3, [pc, #216] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001534: 681b ldr r3, [r3, #0]
- 8001536: 4a35 ldr r2, [pc, #212] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001538: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 800153c: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800153e: f7ff fb0d bl 8000b5c <HAL_GetTick>
- 8001542: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001544: e008 b.n 8001558 <HAL_RCC_OscConfig+0x428>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001546: f7ff fb09 bl 8000b5c <HAL_GetTick>
- 800154a: 4602 mov r2, r0
- 800154c: 693b ldr r3, [r7, #16]
- 800154e: 1ad3 subs r3, r2, r3
- 8001550: 2b02 cmp r3, #2
- 8001552: d901 bls.n 8001558 <HAL_RCC_OscConfig+0x428>
- {
- return HAL_TIMEOUT;
- 8001554: 2303 movs r3, #3
- 8001556: e055 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001558: 4b2c ldr r3, [pc, #176] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 800155a: 681b ldr r3, [r3, #0]
- 800155c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8001560: 2b00 cmp r3, #0
- 8001562: d1f0 bne.n 8001546 <HAL_RCC_OscConfig+0x416>
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
-#if defined (RCC_PLLCFGR_PLLR)
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8001564: 687b ldr r3, [r7, #4]
- 8001566: 69da ldr r2, [r3, #28]
- 8001568: 687b ldr r3, [r7, #4]
- 800156a: 6a1b ldr r3, [r3, #32]
- 800156c: 431a orrs r2, r3
- 800156e: 687b ldr r3, [r7, #4]
- 8001570: 6a5b ldr r3, [r3, #36] ; 0x24
- 8001572: 019b lsls r3, r3, #6
- 8001574: 431a orrs r2, r3
- 8001576: 687b ldr r3, [r7, #4]
- 8001578: 6a9b ldr r3, [r3, #40] ; 0x28
- 800157a: 085b lsrs r3, r3, #1
- 800157c: 3b01 subs r3, #1
- 800157e: 041b lsls r3, r3, #16
- 8001580: 431a orrs r2, r3
- 8001582: 687b ldr r3, [r7, #4]
- 8001584: 6adb ldr r3, [r3, #44] ; 0x2c
- 8001586: 061b lsls r3, r3, #24
- 8001588: 431a orrs r2, r3
- 800158a: 687b ldr r3, [r7, #4]
- 800158c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800158e: 071b lsls r3, r3, #28
- 8001590: 491e ldr r1, [pc, #120] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001592: 4313 orrs r3, r2
- 8001594: 604b str r3, [r1, #4]
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ);
-#endif
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
- 8001596: 4b1d ldr r3, [pc, #116] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 8001598: 681b ldr r3, [r3, #0]
- 800159a: 4a1c ldr r2, [pc, #112] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 800159c: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 80015a0: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80015a2: f7ff fadb bl 8000b5c <HAL_GetTick>
- 80015a6: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80015a8: e008 b.n 80015bc <HAL_RCC_OscConfig+0x48c>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80015aa: f7ff fad7 bl 8000b5c <HAL_GetTick>
- 80015ae: 4602 mov r2, r0
- 80015b0: 693b ldr r3, [r7, #16]
- 80015b2: 1ad3 subs r3, r2, r3
- 80015b4: 2b02 cmp r3, #2
- 80015b6: d901 bls.n 80015bc <HAL_RCC_OscConfig+0x48c>
- {
- return HAL_TIMEOUT;
- 80015b8: 2303 movs r3, #3
- 80015ba: e023 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80015bc: 4b13 ldr r3, [pc, #76] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80015be: 681b ldr r3, [r3, #0]
- 80015c0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80015c4: 2b00 cmp r3, #0
- 80015c6: d0f0 beq.n 80015aa <HAL_RCC_OscConfig+0x47a>
- 80015c8: e01b b.n 8001602 <HAL_RCC_OscConfig+0x4d2>
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- 80015ca: 4b10 ldr r3, [pc, #64] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80015cc: 681b ldr r3, [r3, #0]
- 80015ce: 4a0f ldr r2, [pc, #60] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80015d0: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80015d4: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80015d6: f7ff fac1 bl 8000b5c <HAL_GetTick>
- 80015da: 6138 str r0, [r7, #16]
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80015dc: e008 b.n 80015f0 <HAL_RCC_OscConfig+0x4c0>
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80015de: f7ff fabd bl 8000b5c <HAL_GetTick>
- 80015e2: 4602 mov r2, r0
- 80015e4: 693b ldr r3, [r7, #16]
- 80015e6: 1ad3 subs r3, r2, r3
- 80015e8: 2b02 cmp r3, #2
- 80015ea: d901 bls.n 80015f0 <HAL_RCC_OscConfig+0x4c0>
- {
- return HAL_TIMEOUT;
- 80015ec: 2303 movs r3, #3
- 80015ee: e009 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80015f0: 4b06 ldr r3, [pc, #24] ; (800160c <HAL_RCC_OscConfig+0x4dc>)
- 80015f2: 681b ldr r3, [r3, #0]
- 80015f4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80015f8: 2b00 cmp r3, #0
- 80015fa: d1f0 bne.n 80015de <HAL_RCC_OscConfig+0x4ae>
- 80015fc: e001 b.n 8001602 <HAL_RCC_OscConfig+0x4d2>
- }
- }
- }
- else
- {
- return HAL_ERROR;
- 80015fe: 2301 movs r3, #1
- 8001600: e000 b.n 8001604 <HAL_RCC_OscConfig+0x4d4>
- }
- }
- return HAL_OK;
- 8001602: 2300 movs r3, #0
-}
- 8001604: 4618 mov r0, r3
- 8001606: 3718 adds r7, #24
- 8001608: 46bd mov sp, r7
- 800160a: bd80 pop {r7, pc}
- 800160c: 40023800 .word 0x40023800
- 8001610: 40007000 .word 0x40007000
-
-08001614 <HAL_RCC_ClockConfig>:
- * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
- * (for more details refer to section above "Initialization/de-initialization functions")
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 8001614: b580 push {r7, lr}
- 8001616: b084 sub sp, #16
- 8001618: af00 add r7, sp, #0
- 800161a: 6078 str r0, [r7, #4]
- 800161c: 6039 str r1, [r7, #0]
- uint32_t tickstart = 0;
- 800161e: 2300 movs r3, #0
- 8001620: 60fb str r3, [r7, #12]
-
- /* Check Null pointer */
- if(RCC_ClkInitStruct == NULL)
- 8001622: 687b ldr r3, [r7, #4]
- 8001624: 2b00 cmp r3, #0
- 8001626: d101 bne.n 800162c <HAL_RCC_ClockConfig+0x18>
- {
- return HAL_ERROR;
- 8001628: 2301 movs r3, #1
- 800162a: e0ce b.n 80017ca <HAL_RCC_ClockConfig+0x1b6>
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
- /* Increasing the CPU frequency */
- if(FLatency > __HAL_FLASH_GET_LATENCY())
- 800162c: 4b69 ldr r3, [pc, #420] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800162e: 681b ldr r3, [r3, #0]
- 8001630: f003 030f and.w r3, r3, #15
- 8001634: 683a ldr r2, [r7, #0]
- 8001636: 429a cmp r2, r3
- 8001638: d910 bls.n 800165c <HAL_RCC_ClockConfig+0x48>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 800163a: 4b66 ldr r3, [pc, #408] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800163c: 681b ldr r3, [r3, #0]
- 800163e: f023 020f bic.w r2, r3, #15
- 8001642: 4964 ldr r1, [pc, #400] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001644: 683b ldr r3, [r7, #0]
- 8001646: 4313 orrs r3, r2
- 8001648: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800164a: 4b62 ldr r3, [pc, #392] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800164c: 681b ldr r3, [r3, #0]
- 800164e: f003 030f and.w r3, r3, #15
- 8001652: 683a ldr r2, [r7, #0]
- 8001654: 429a cmp r2, r3
- 8001656: d001 beq.n 800165c <HAL_RCC_ClockConfig+0x48>
- {
- return HAL_ERROR;
- 8001658: 2301 movs r3, #1
- 800165a: e0b6 b.n 80017ca <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 800165c: 687b ldr r3, [r7, #4]
- 800165e: 681b ldr r3, [r3, #0]
- 8001660: f003 0302 and.w r3, r3, #2
- 8001664: 2b00 cmp r3, #0
- 8001666: d020 beq.n 80016aa <HAL_RCC_ClockConfig+0x96>
- {
- /* Set the highest APBx dividers in order to ensure that we do not go through
- a non-spec phase whatever we decrease or increase HCLK. */
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001668: 687b ldr r3, [r7, #4]
- 800166a: 681b ldr r3, [r3, #0]
- 800166c: f003 0304 and.w r3, r3, #4
- 8001670: 2b00 cmp r3, #0
- 8001672: d005 beq.n 8001680 <HAL_RCC_ClockConfig+0x6c>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 8001674: 4b58 ldr r3, [pc, #352] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001676: 689b ldr r3, [r3, #8]
- 8001678: 4a57 ldr r2, [pc, #348] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 800167a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 800167e: 6093 str r3, [r2, #8]
- }
-
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8001680: 687b ldr r3, [r7, #4]
- 8001682: 681b ldr r3, [r3, #0]
- 8001684: f003 0308 and.w r3, r3, #8
- 8001688: 2b00 cmp r3, #0
- 800168a: d005 beq.n 8001698 <HAL_RCC_ClockConfig+0x84>
- {
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 800168c: 4b52 ldr r3, [pc, #328] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 800168e: 689b ldr r3, [r3, #8]
- 8001690: 4a51 ldr r2, [pc, #324] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001692: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 8001696: 6093 str r3, [r2, #8]
- }
-
- /* Set the new HCLK clock divider */
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8001698: 4b4f ldr r3, [pc, #316] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 800169a: 689b ldr r3, [r3, #8]
- 800169c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 80016a0: 687b ldr r3, [r7, #4]
- 80016a2: 689b ldr r3, [r3, #8]
- 80016a4: 494c ldr r1, [pc, #304] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80016a6: 4313 orrs r3, r2
- 80016a8: 608b str r3, [r1, #8]
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 80016aa: 687b ldr r3, [r7, #4]
- 80016ac: 681b ldr r3, [r3, #0]
- 80016ae: f003 0301 and.w r3, r3, #1
- 80016b2: 2b00 cmp r3, #0
- 80016b4: d040 beq.n 8001738 <HAL_RCC_ClockConfig+0x124>
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 80016b6: 687b ldr r3, [r7, #4]
- 80016b8: 685b ldr r3, [r3, #4]
- 80016ba: 2b01 cmp r3, #1
- 80016bc: d107 bne.n 80016ce <HAL_RCC_ClockConfig+0xba>
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80016be: 4b46 ldr r3, [pc, #280] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80016c0: 681b ldr r3, [r3, #0]
- 80016c2: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80016c6: 2b00 cmp r3, #0
- 80016c8: d115 bne.n 80016f6 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80016ca: 2301 movs r3, #1
- 80016cc: e07d b.n 80017ca <HAL_RCC_ClockConfig+0x1b6>
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 80016ce: 687b ldr r3, [r7, #4]
- 80016d0: 685b ldr r3, [r3, #4]
- 80016d2: 2b02 cmp r3, #2
- 80016d4: d107 bne.n 80016e6 <HAL_RCC_ClockConfig+0xd2>
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80016d6: 4b40 ldr r3, [pc, #256] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80016d8: 681b ldr r3, [r3, #0]
- 80016da: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80016de: 2b00 cmp r3, #0
- 80016e0: d109 bne.n 80016f6 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80016e2: 2301 movs r3, #1
- 80016e4: e071 b.n 80017ca <HAL_RCC_ClockConfig+0x1b6>
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80016e6: 4b3c ldr r3, [pc, #240] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80016e8: 681b ldr r3, [r3, #0]
- 80016ea: f003 0302 and.w r3, r3, #2
- 80016ee: 2b00 cmp r3, #0
- 80016f0: d101 bne.n 80016f6 <HAL_RCC_ClockConfig+0xe2>
- {
- return HAL_ERROR;
- 80016f2: 2301 movs r3, #1
- 80016f4: e069 b.n 80017ca <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 80016f6: 4b38 ldr r3, [pc, #224] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80016f8: 689b ldr r3, [r3, #8]
- 80016fa: f023 0203 bic.w r2, r3, #3
- 80016fe: 687b ldr r3, [r7, #4]
- 8001700: 685b ldr r3, [r3, #4]
- 8001702: 4935 ldr r1, [pc, #212] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001704: 4313 orrs r3, r2
- 8001706: 608b str r3, [r1, #8]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001708: f7ff fa28 bl 8000b5c <HAL_GetTick>
- 800170c: 60f8 str r0, [r7, #12]
-
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 800170e: e00a b.n 8001726 <HAL_RCC_ClockConfig+0x112>
- {
- if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8001710: f7ff fa24 bl 8000b5c <HAL_GetTick>
- 8001714: 4602 mov r2, r0
- 8001716: 68fb ldr r3, [r7, #12]
- 8001718: 1ad3 subs r3, r2, r3
- 800171a: f241 3288 movw r2, #5000 ; 0x1388
- 800171e: 4293 cmp r3, r2
- 8001720: d901 bls.n 8001726 <HAL_RCC_ClockConfig+0x112>
- {
- return HAL_TIMEOUT;
- 8001722: 2303 movs r3, #3
- 8001724: e051 b.n 80017ca <HAL_RCC_ClockConfig+0x1b6>
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8001726: 4b2c ldr r3, [pc, #176] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001728: 689b ldr r3, [r3, #8]
- 800172a: f003 020c and.w r2, r3, #12
- 800172e: 687b ldr r3, [r7, #4]
- 8001730: 685b ldr r3, [r3, #4]
- 8001732: 009b lsls r3, r3, #2
- 8001734: 429a cmp r2, r3
- 8001736: d1eb bne.n 8001710 <HAL_RCC_ClockConfig+0xfc>
- }
- }
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8001738: 4b26 ldr r3, [pc, #152] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800173a: 681b ldr r3, [r3, #0]
- 800173c: f003 030f and.w r3, r3, #15
- 8001740: 683a ldr r2, [r7, #0]
- 8001742: 429a cmp r2, r3
- 8001744: d210 bcs.n 8001768 <HAL_RCC_ClockConfig+0x154>
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
- 8001746: 4b23 ldr r3, [pc, #140] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001748: 681b ldr r3, [r3, #0]
- 800174a: f023 020f bic.w r2, r3, #15
- 800174e: 4921 ldr r1, [pc, #132] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001750: 683b ldr r3, [r7, #0]
- 8001752: 4313 orrs r3, r2
- 8001754: 600b str r3, [r1, #0]
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8001756: 4b1f ldr r3, [pc, #124] ; (80017d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001758: 681b ldr r3, [r3, #0]
- 800175a: f003 030f and.w r3, r3, #15
- 800175e: 683a ldr r2, [r7, #0]
- 8001760: 429a cmp r2, r3
- 8001762: d001 beq.n 8001768 <HAL_RCC_ClockConfig+0x154>
- {
- return HAL_ERROR;
- 8001764: 2301 movs r3, #1
- 8001766: e030 b.n 80017ca <HAL_RCC_ClockConfig+0x1b6>
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001768: 687b ldr r3, [r7, #4]
- 800176a: 681b ldr r3, [r3, #0]
- 800176c: f003 0304 and.w r3, r3, #4
- 8001770: 2b00 cmp r3, #0
- 8001772: d008 beq.n 8001786 <HAL_RCC_ClockConfig+0x172>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8001774: 4b18 ldr r3, [pc, #96] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001776: 689b ldr r3, [r3, #8]
- 8001778: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 800177c: 687b ldr r3, [r7, #4]
- 800177e: 68db ldr r3, [r3, #12]
- 8001780: 4915 ldr r1, [pc, #84] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001782: 4313 orrs r3, r2
- 8001784: 608b str r3, [r1, #8]
- }
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8001786: 687b ldr r3, [r7, #4]
- 8001788: 681b ldr r3, [r3, #0]
- 800178a: f003 0308 and.w r3, r3, #8
- 800178e: 2b00 cmp r3, #0
- 8001790: d009 beq.n 80017a6 <HAL_RCC_ClockConfig+0x192>
- {
- assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 8001792: 4b11 ldr r3, [pc, #68] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001794: 689b ldr r3, [r3, #8]
- 8001796: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 800179a: 687b ldr r3, [r7, #4]
- 800179c: 691b ldr r3, [r3, #16]
- 800179e: 00db lsls r3, r3, #3
- 80017a0: 490d ldr r1, [pc, #52] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80017a2: 4313 orrs r3, r2
- 80017a4: 608b str r3, [r1, #8]
- }
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 80017a6: f000 f81d bl 80017e4 <HAL_RCC_GetSysClockFreq>
- 80017aa: 4601 mov r1, r0
- 80017ac: 4b0a ldr r3, [pc, #40] ; (80017d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80017ae: 689b ldr r3, [r3, #8]
- 80017b0: 091b lsrs r3, r3, #4
- 80017b2: f003 030f and.w r3, r3, #15
- 80017b6: 4a09 ldr r2, [pc, #36] ; (80017dc <HAL_RCC_ClockConfig+0x1c8>)
- 80017b8: 5cd3 ldrb r3, [r2, r3]
- 80017ba: fa21 f303 lsr.w r3, r1, r3
- 80017be: 4a08 ldr r2, [pc, #32] ; (80017e0 <HAL_RCC_ClockConfig+0x1cc>)
- 80017c0: 6013 str r3, [r2, #0]
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
- 80017c2: 2000 movs r0, #0
- 80017c4: f7ff f986 bl 8000ad4 <HAL_InitTick>
-
- return HAL_OK;
- 80017c8: 2300 movs r3, #0
-}
- 80017ca: 4618 mov r0, r3
- 80017cc: 3710 adds r7, #16
- 80017ce: 46bd mov sp, r7
- 80017d0: bd80 pop {r7, pc}
- 80017d2: bf00 nop
- 80017d4: 40023c00 .word 0x40023c00
- 80017d8: 40023800 .word 0x40023800
- 80017dc: 08003938 .word 0x08003938
- 80017e0: 20000000 .word 0x20000000
-
-080017e4 <HAL_RCC_GetSysClockFreq>:
- *
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- 80017e4: b5f0 push {r4, r5, r6, r7, lr}
- 80017e6: b085 sub sp, #20
- 80017e8: af00 add r7, sp, #0
- uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 80017ea: 2300 movs r3, #0
- 80017ec: 607b str r3, [r7, #4]
- 80017ee: 2300 movs r3, #0
- 80017f0: 60fb str r3, [r7, #12]
- 80017f2: 2300 movs r3, #0
- 80017f4: 603b str r3, [r7, #0]
- uint32_t sysclockfreq = 0;
- 80017f6: 2300 movs r3, #0
- 80017f8: 60bb str r3, [r7, #8]
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (RCC->CFGR & RCC_CFGR_SWS)
- 80017fa: 4b50 ldr r3, [pc, #320] ; (800193c <HAL_RCC_GetSysClockFreq+0x158>)
- 80017fc: 689b ldr r3, [r3, #8]
- 80017fe: f003 030c and.w r3, r3, #12
- 8001802: 2b04 cmp r3, #4
- 8001804: d007 beq.n 8001816 <HAL_RCC_GetSysClockFreq+0x32>
- 8001806: 2b08 cmp r3, #8
- 8001808: d008 beq.n 800181c <HAL_RCC_GetSysClockFreq+0x38>
- 800180a: 2b00 cmp r3, #0
- 800180c: f040 808d bne.w 800192a <HAL_RCC_GetSysClockFreq+0x146>
- {
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- {
- sysclockfreq = HSI_VALUE;
- 8001810: 4b4b ldr r3, [pc, #300] ; (8001940 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8001812: 60bb str r3, [r7, #8]
- break;
- 8001814: e08c b.n 8001930 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- {
- sysclockfreq = HSE_VALUE;
- 8001816: 4b4b ldr r3, [pc, #300] ; (8001944 <HAL_RCC_GetSysClockFreq+0x160>)
- 8001818: 60bb str r3, [r7, #8]
- break;
- 800181a: e089 b.n 8001930 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
- {
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP */
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 800181c: 4b47 ldr r3, [pc, #284] ; (800193c <HAL_RCC_GetSysClockFreq+0x158>)
- 800181e: 685b ldr r3, [r3, #4]
- 8001820: f003 033f and.w r3, r3, #63 ; 0x3f
- 8001824: 607b str r3, [r7, #4]
- if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 8001826: 4b45 ldr r3, [pc, #276] ; (800193c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001828: 685b ldr r3, [r3, #4]
- 800182a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800182e: 2b00 cmp r3, #0
- 8001830: d023 beq.n 800187a <HAL_RCC_GetSysClockFreq+0x96>
- {
- /* HSE used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8001832: 4b42 ldr r3, [pc, #264] ; (800193c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001834: 685b ldr r3, [r3, #4]
- 8001836: 099b lsrs r3, r3, #6
- 8001838: f04f 0400 mov.w r4, #0
- 800183c: f240 11ff movw r1, #511 ; 0x1ff
- 8001840: f04f 0200 mov.w r2, #0
- 8001844: ea03 0501 and.w r5, r3, r1
- 8001848: ea04 0602 and.w r6, r4, r2
- 800184c: 4a3d ldr r2, [pc, #244] ; (8001944 <HAL_RCC_GetSysClockFreq+0x160>)
- 800184e: fb02 f106 mul.w r1, r2, r6
- 8001852: 2200 movs r2, #0
- 8001854: fb02 f205 mul.w r2, r2, r5
- 8001858: 440a add r2, r1
- 800185a: 493a ldr r1, [pc, #232] ; (8001944 <HAL_RCC_GetSysClockFreq+0x160>)
- 800185c: fba5 0101 umull r0, r1, r5, r1
- 8001860: 1853 adds r3, r2, r1
- 8001862: 4619 mov r1, r3
- 8001864: 687b ldr r3, [r7, #4]
- 8001866: f04f 0400 mov.w r4, #0
- 800186a: 461a mov r2, r3
- 800186c: 4623 mov r3, r4
- 800186e: f7fe fce3 bl 8000238 <__aeabi_uldivmod>
- 8001872: 4603 mov r3, r0
- 8001874: 460c mov r4, r1
- 8001876: 60fb str r3, [r7, #12]
- 8001878: e049 b.n 800190e <HAL_RCC_GetSysClockFreq+0x12a>
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 800187a: 4b30 ldr r3, [pc, #192] ; (800193c <HAL_RCC_GetSysClockFreq+0x158>)
- 800187c: 685b ldr r3, [r3, #4]
- 800187e: 099b lsrs r3, r3, #6
- 8001880: f04f 0400 mov.w r4, #0
- 8001884: f240 11ff movw r1, #511 ; 0x1ff
- 8001888: f04f 0200 mov.w r2, #0
- 800188c: ea03 0501 and.w r5, r3, r1
- 8001890: ea04 0602 and.w r6, r4, r2
- 8001894: 4629 mov r1, r5
- 8001896: 4632 mov r2, r6
- 8001898: f04f 0300 mov.w r3, #0
- 800189c: f04f 0400 mov.w r4, #0
- 80018a0: 0154 lsls r4, r2, #5
- 80018a2: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 80018a6: 014b lsls r3, r1, #5
- 80018a8: 4619 mov r1, r3
- 80018aa: 4622 mov r2, r4
- 80018ac: 1b49 subs r1, r1, r5
- 80018ae: eb62 0206 sbc.w r2, r2, r6
- 80018b2: f04f 0300 mov.w r3, #0
- 80018b6: f04f 0400 mov.w r4, #0
- 80018ba: 0194 lsls r4, r2, #6
- 80018bc: ea44 6491 orr.w r4, r4, r1, lsr #26
- 80018c0: 018b lsls r3, r1, #6
- 80018c2: 1a5b subs r3, r3, r1
- 80018c4: eb64 0402 sbc.w r4, r4, r2
- 80018c8: f04f 0100 mov.w r1, #0
- 80018cc: f04f 0200 mov.w r2, #0
- 80018d0: 00e2 lsls r2, r4, #3
- 80018d2: ea42 7253 orr.w r2, r2, r3, lsr #29
- 80018d6: 00d9 lsls r1, r3, #3
- 80018d8: 460b mov r3, r1
- 80018da: 4614 mov r4, r2
- 80018dc: 195b adds r3, r3, r5
- 80018de: eb44 0406 adc.w r4, r4, r6
- 80018e2: f04f 0100 mov.w r1, #0
- 80018e6: f04f 0200 mov.w r2, #0
- 80018ea: 02a2 lsls r2, r4, #10
- 80018ec: ea42 5293 orr.w r2, r2, r3, lsr #22
- 80018f0: 0299 lsls r1, r3, #10
- 80018f2: 460b mov r3, r1
- 80018f4: 4614 mov r4, r2
- 80018f6: 4618 mov r0, r3
- 80018f8: 4621 mov r1, r4
- 80018fa: 687b ldr r3, [r7, #4]
- 80018fc: f04f 0400 mov.w r4, #0
- 8001900: 461a mov r2, r3
- 8001902: 4623 mov r3, r4
- 8001904: f7fe fc98 bl 8000238 <__aeabi_uldivmod>
- 8001908: 4603 mov r3, r0
- 800190a: 460c mov r4, r1
- 800190c: 60fb str r3, [r7, #12]
- }
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 800190e: 4b0b ldr r3, [pc, #44] ; (800193c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001910: 685b ldr r3, [r3, #4]
- 8001912: 0c1b lsrs r3, r3, #16
- 8001914: f003 0303 and.w r3, r3, #3
- 8001918: 3301 adds r3, #1
- 800191a: 005b lsls r3, r3, #1
- 800191c: 603b str r3, [r7, #0]
-
- sysclockfreq = pllvco/pllp;
- 800191e: 68fa ldr r2, [r7, #12]
- 8001920: 683b ldr r3, [r7, #0]
- 8001922: fbb2 f3f3 udiv r3, r2, r3
- 8001926: 60bb str r3, [r7, #8]
- break;
- 8001928: e002 b.n 8001930 <HAL_RCC_GetSysClockFreq+0x14c>
- }
- default:
- {
- sysclockfreq = HSI_VALUE;
- 800192a: 4b05 ldr r3, [pc, #20] ; (8001940 <HAL_RCC_GetSysClockFreq+0x15c>)
- 800192c: 60bb str r3, [r7, #8]
- break;
- 800192e: bf00 nop
- }
- }
- return sysclockfreq;
- 8001930: 68bb ldr r3, [r7, #8]
-}
- 8001932: 4618 mov r0, r3
- 8001934: 3714 adds r7, #20
- 8001936: 46bd mov sp, r7
- 8001938: bdf0 pop {r4, r5, r6, r7, pc}
- 800193a: bf00 nop
- 800193c: 40023800 .word 0x40023800
- 8001940: 00f42400 .word 0x00f42400
- 8001944: 017d7840 .word 0x017d7840
-
-08001948 <HAL_RCC_GetHCLKFreq>:
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
- * @retval HCLK frequency
- */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- 8001948: b480 push {r7}
- 800194a: af00 add r7, sp, #0
- return SystemCoreClock;
- 800194c: 4b03 ldr r3, [pc, #12] ; (800195c <HAL_RCC_GetHCLKFreq+0x14>)
- 800194e: 681b ldr r3, [r3, #0]
-}
- 8001950: 4618 mov r0, r3
- 8001952: 46bd mov sp, r7
- 8001954: f85d 7b04 ldr.w r7, [sp], #4
- 8001958: 4770 bx lr
- 800195a: bf00 nop
- 800195c: 20000000 .word 0x20000000
-
-08001960 <HAL_RCC_GetPCLK1Freq>:
- * @note Each time PCLK1 changes, this function must be called to update the
- * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK1 frequency
- */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- 8001960: b580 push {r7, lr}
- 8001962: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 8001964: f7ff fff0 bl 8001948 <HAL_RCC_GetHCLKFreq>
- 8001968: 4601 mov r1, r0
- 800196a: 4b05 ldr r3, [pc, #20] ; (8001980 <HAL_RCC_GetPCLK1Freq+0x20>)
- 800196c: 689b ldr r3, [r3, #8]
- 800196e: 0a9b lsrs r3, r3, #10
- 8001970: f003 0307 and.w r3, r3, #7
- 8001974: 4a03 ldr r2, [pc, #12] ; (8001984 <HAL_RCC_GetPCLK1Freq+0x24>)
- 8001976: 5cd3 ldrb r3, [r2, r3]
- 8001978: fa21 f303 lsr.w r3, r1, r3
-}
- 800197c: 4618 mov r0, r3
- 800197e: bd80 pop {r7, pc}
- 8001980: 40023800 .word 0x40023800
- 8001984: 08003948 .word 0x08003948
-
-08001988 <HAL_RCC_GetPCLK2Freq>:
- * @note Each time PCLK2 changes, this function must be called to update the
- * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @retval PCLK2 frequency
- */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- 8001988: b580 push {r7, lr}
- 800198a: af00 add r7, sp, #0
- /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 800198c: f7ff ffdc bl 8001948 <HAL_RCC_GetHCLKFreq>
- 8001990: 4601 mov r1, r0
- 8001992: 4b05 ldr r3, [pc, #20] ; (80019a8 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8001994: 689b ldr r3, [r3, #8]
- 8001996: 0b5b lsrs r3, r3, #13
- 8001998: f003 0307 and.w r3, r3, #7
- 800199c: 4a03 ldr r2, [pc, #12] ; (80019ac <HAL_RCC_GetPCLK2Freq+0x24>)
- 800199e: 5cd3 ldrb r3, [r2, r3]
- 80019a0: fa21 f303 lsr.w r3, r1, r3
-}
- 80019a4: 4618 mov r0, r3
- 80019a6: bd80 pop {r7, pc}
- 80019a8: 40023800 .word 0x40023800
- 80019ac: 08003948 .word 0x08003948
-
-080019b0 <HAL_RCCEx_PeriphCLKConfig>:
- * the backup registers) are set to their reset values.
- *
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
-{
- 80019b0: b580 push {r7, lr}
- 80019b2: b088 sub sp, #32
- 80019b4: af00 add r7, sp, #0
- 80019b6: 6078 str r0, [r7, #4]
- uint32_t tickstart = 0;
- 80019b8: 2300 movs r3, #0
- 80019ba: 617b str r3, [r7, #20]
- uint32_t tmpreg0 = 0;
- 80019bc: 2300 movs r3, #0
- 80019be: 613b str r3, [r7, #16]
- uint32_t tmpreg1 = 0;
- 80019c0: 2300 movs r3, #0
- 80019c2: 60fb str r3, [r7, #12]
- uint32_t plli2sused = 0;
- 80019c4: 2300 movs r3, #0
- 80019c6: 61fb str r3, [r7, #28]
- uint32_t pllsaiused = 0;
- 80019c8: 2300 movs r3, #0
- 80019ca: 61bb str r3, [r7, #24]
-
- /* Check the parameters */
- assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
- /*----------------------------------- I2S configuration ----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 80019cc: 687b ldr r3, [r7, #4]
- 80019ce: 681b ldr r3, [r3, #0]
- 80019d0: f003 0301 and.w r3, r3, #1
- 80019d4: 2b00 cmp r3, #0
- 80019d6: d012 beq.n 80019fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure I2S Clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 80019d8: 4b69 ldr r3, [pc, #420] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80019da: 689b ldr r3, [r3, #8]
- 80019dc: 4a68 ldr r2, [pc, #416] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80019de: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
- 80019e2: 6093 str r3, [r2, #8]
- 80019e4: 4b66 ldr r3, [pc, #408] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80019e6: 689a ldr r2, [r3, #8]
- 80019e8: 687b ldr r3, [r7, #4]
- 80019ea: 6b5b ldr r3, [r3, #52] ; 0x34
- 80019ec: 4964 ldr r1, [pc, #400] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80019ee: 4313 orrs r3, r2
- 80019f0: 608b str r3, [r1, #8]
-
- /* Enable the PLLI2S when it's used as clock source for I2S */
- if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 80019f2: 687b ldr r3, [r7, #4]
- 80019f4: 6b5b ldr r3, [r3, #52] ; 0x34
- 80019f6: 2b00 cmp r3, #0
- 80019f8: d101 bne.n 80019fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
- {
- plli2sused = 1;
- 80019fa: 2301 movs r3, #1
- 80019fc: 61fb str r3, [r7, #28]
- }
- }
-
- /*------------------------------------ SAI1 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 80019fe: 687b ldr r3, [r7, #4]
- 8001a00: 681b ldr r3, [r3, #0]
- 8001a02: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8001a06: 2b00 cmp r3, #0
- 8001a08: d017 beq.n 8001a3a <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
- /* Configure SAI1 Clock source */
- __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 8001a0a: 4b5d ldr r3, [pc, #372] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a0c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001a10: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8001a14: 687b ldr r3, [r7, #4]
- 8001a16: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001a18: 4959 ldr r1, [pc, #356] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a1a: 4313 orrs r3, r2
- 8001a1c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8001a20: 687b ldr r3, [r7, #4]
- 8001a22: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001a24: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8001a28: d101 bne.n 8001a2e <HAL_RCCEx_PeriphCLKConfig+0x7e>
- {
- plli2sused = 1;
- 8001a2a: 2301 movs r3, #1
- 8001a2c: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 8001a2e: 687b ldr r3, [r7, #4]
- 8001a30: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001a32: 2b00 cmp r3, #0
- 8001a34: d101 bne.n 8001a3a <HAL_RCCEx_PeriphCLKConfig+0x8a>
- {
- pllsaiused = 1;
- 8001a36: 2301 movs r3, #1
- 8001a38: 61bb str r3, [r7, #24]
- }
- }
-
- /*------------------------------------ SAI2 configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 8001a3a: 687b ldr r3, [r7, #4]
- 8001a3c: 681b ldr r3, [r3, #0]
- 8001a3e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8001a42: 2b00 cmp r3, #0
- 8001a44: d017 beq.n 8001a76 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
- /* Configure SAI2 Clock source */
- __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 8001a46: 4b4e ldr r3, [pc, #312] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a48: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001a4c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8001a50: 687b ldr r3, [r7, #4]
- 8001a52: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a54: 494a ldr r1, [pc, #296] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a56: 4313 orrs r3, r2
- 8001a58: f8c1 308c str.w r3, [r1, #140] ; 0x8c
-
- /* Enable the PLLI2S when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 8001a5c: 687b ldr r3, [r7, #4]
- 8001a5e: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a60: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8001a64: d101 bne.n 8001a6a <HAL_RCCEx_PeriphCLKConfig+0xba>
- {
- plli2sused = 1;
- 8001a66: 2301 movs r3, #1
- 8001a68: 61fb str r3, [r7, #28]
- }
- /* Enable the PLLSAI when it's used as clock source for SAI */
- if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 8001a6a: 687b ldr r3, [r7, #4]
- 8001a6c: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a6e: 2b00 cmp r3, #0
- 8001a70: d101 bne.n 8001a76 <HAL_RCCEx_PeriphCLKConfig+0xc6>
- {
- pllsaiused = 1;
- 8001a72: 2301 movs r3, #1
- 8001a74: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8001a76: 687b ldr r3, [r7, #4]
- 8001a78: 681b ldr r3, [r3, #0]
- 8001a7a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8001a7e: 2b00 cmp r3, #0
- 8001a80: d001 beq.n 8001a86 <HAL_RCCEx_PeriphCLKConfig+0xd6>
- {
- plli2sused = 1;
- 8001a82: 2301 movs r3, #1
- 8001a84: 61fb str r3, [r7, #28]
- }
-
- /*------------------------------------ RTC configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 8001a86: 687b ldr r3, [r7, #4]
- 8001a88: 681b ldr r3, [r3, #0]
- 8001a8a: f003 0320 and.w r3, r3, #32
- 8001a8e: 2b00 cmp r3, #0
- 8001a90: f000 808b beq.w 8001baa <HAL_RCCEx_PeriphCLKConfig+0x1fa>
- {
- /* Check for RTC Parameters used to output RTCCLK */
- assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
- 8001a94: 4b3a ldr r3, [pc, #232] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a96: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001a98: 4a39 ldr r2, [pc, #228] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001a9a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8001a9e: 6413 str r3, [r2, #64] ; 0x40
- 8001aa0: 4b37 ldr r3, [pc, #220] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001aa2: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001aa4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001aa8: 60bb str r3, [r7, #8]
- 8001aaa: 68bb ldr r3, [r7, #8]
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
- 8001aac: 4b35 ldr r3, [pc, #212] ; (8001b84 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8001aae: 681b ldr r3, [r3, #0]
- 8001ab0: 4a34 ldr r2, [pc, #208] ; (8001b84 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8001ab2: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8001ab6: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001ab8: f7ff f850 bl 8000b5c <HAL_GetTick>
- 8001abc: 6178 str r0, [r7, #20]
-
- /* Wait for Backup domain Write protection disable */
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8001abe: e008 b.n 8001ad2 <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8001ac0: f7ff f84c bl 8000b5c <HAL_GetTick>
- 8001ac4: 4602 mov r2, r0
- 8001ac6: 697b ldr r3, [r7, #20]
- 8001ac8: 1ad3 subs r3, r2, r3
- 8001aca: 2b64 cmp r3, #100 ; 0x64
- 8001acc: d901 bls.n 8001ad2 <HAL_RCCEx_PeriphCLKConfig+0x122>
- {
- return HAL_TIMEOUT;
- 8001ace: 2303 movs r3, #3
- 8001ad0: e38d b.n 80021ee <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 8001ad2: 4b2c ldr r3, [pc, #176] ; (8001b84 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 8001ad4: 681b ldr r3, [r3, #0]
- 8001ad6: f403 7380 and.w r3, r3, #256 ; 0x100
- 8001ada: 2b00 cmp r3, #0
- 8001adc: d0f0 beq.n 8001ac0 <HAL_RCCEx_PeriphCLKConfig+0x110>
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 8001ade: 4b28 ldr r3, [pc, #160] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001ae0: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001ae2: f403 7340 and.w r3, r3, #768 ; 0x300
- 8001ae6: 613b str r3, [r7, #16]
-
- if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 8001ae8: 693b ldr r3, [r7, #16]
- 8001aea: 2b00 cmp r3, #0
- 8001aec: d035 beq.n 8001b5a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 8001aee: 687b ldr r3, [r7, #4]
- 8001af0: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001af2: f403 7340 and.w r3, r3, #768 ; 0x300
- 8001af6: 693a ldr r2, [r7, #16]
- 8001af8: 429a cmp r2, r3
- 8001afa: d02e beq.n 8001b5a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 8001afc: 4b20 ldr r3, [pc, #128] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001afe: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001b00: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8001b04: 613b str r3, [r7, #16]
-
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- 8001b06: 4b1e ldr r3, [pc, #120] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b08: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001b0a: 4a1d ldr r2, [pc, #116] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b0c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8001b10: 6713 str r3, [r2, #112] ; 0x70
- __HAL_RCC_BACKUPRESET_RELEASE();
- 8001b12: 4b1b ldr r3, [pc, #108] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b14: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001b16: 4a1a ldr r2, [pc, #104] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b18: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8001b1c: 6713 str r3, [r2, #112] ; 0x70
-
- /* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg0;
- 8001b1e: 4a18 ldr r2, [pc, #96] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b20: 693b ldr r3, [r7, #16]
- 8001b22: 6713 str r3, [r2, #112] ; 0x70
-
- /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
- if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8001b24: 4b16 ldr r3, [pc, #88] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b26: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001b28: f003 0301 and.w r3, r3, #1
- 8001b2c: 2b01 cmp r3, #1
- 8001b2e: d114 bne.n 8001b5a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001b30: f7ff f814 bl 8000b5c <HAL_GetTick>
- 8001b34: 6178 str r0, [r7, #20]
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001b36: e00a b.n 8001b4e <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001b38: f7ff f810 bl 8000b5c <HAL_GetTick>
- 8001b3c: 4602 mov r2, r0
- 8001b3e: 697b ldr r3, [r7, #20]
- 8001b40: 1ad3 subs r3, r2, r3
- 8001b42: f241 3288 movw r2, #5000 ; 0x1388
- 8001b46: 4293 cmp r3, r2
- 8001b48: d901 bls.n 8001b4e <HAL_RCCEx_PeriphCLKConfig+0x19e>
- {
- return HAL_TIMEOUT;
- 8001b4a: 2303 movs r3, #3
- 8001b4c: e34f b.n 80021ee <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001b4e: 4b0c ldr r3, [pc, #48] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b50: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001b52: f003 0302 and.w r3, r3, #2
- 8001b56: 2b00 cmp r3, #0
- 8001b58: d0ee beq.n 8001b38 <HAL_RCCEx_PeriphCLKConfig+0x188>
- }
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8001b5a: 687b ldr r3, [r7, #4]
- 8001b5c: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001b5e: f403 7340 and.w r3, r3, #768 ; 0x300
- 8001b62: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8001b66: d111 bne.n 8001b8c <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8001b68: 4b05 ldr r3, [pc, #20] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b6a: 689b ldr r3, [r3, #8]
- 8001b6c: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
- 8001b70: 687b ldr r3, [r7, #4]
- 8001b72: 6b19 ldr r1, [r3, #48] ; 0x30
- 8001b74: 4b04 ldr r3, [pc, #16] ; (8001b88 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8001b76: 400b ands r3, r1
- 8001b78: 4901 ldr r1, [pc, #4] ; (8001b80 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001b7a: 4313 orrs r3, r2
- 8001b7c: 608b str r3, [r1, #8]
- 8001b7e: e00b b.n 8001b98 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8001b80: 40023800 .word 0x40023800
- 8001b84: 40007000 .word 0x40007000
- 8001b88: 0ffffcff .word 0x0ffffcff
- 8001b8c: 4bb3 ldr r3, [pc, #716] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b8e: 689b ldr r3, [r3, #8]
- 8001b90: 4ab2 ldr r2, [pc, #712] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b92: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
- 8001b96: 6093 str r3, [r2, #8]
- 8001b98: 4bb0 ldr r3, [pc, #704] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b9a: 6f1a ldr r2, [r3, #112] ; 0x70
- 8001b9c: 687b ldr r3, [r7, #4]
- 8001b9e: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001ba0: f3c3 030b ubfx r3, r3, #0, #12
- 8001ba4: 49ad ldr r1, [pc, #692] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ba6: 4313 orrs r3, r2
- 8001ba8: 670b str r3, [r1, #112] ; 0x70
- }
-
- /*------------------------------------ TIM configuration --------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 8001baa: 687b ldr r3, [r7, #4]
- 8001bac: 681b ldr r3, [r3, #0]
- 8001bae: f003 0310 and.w r3, r3, #16
- 8001bb2: 2b00 cmp r3, #0
- 8001bb4: d010 beq.n 8001bd8 <HAL_RCCEx_PeriphCLKConfig+0x228>
- {
- /* Check the parameters */
- assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
-
- /* Configure Timer Prescaler */
- __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 8001bb6: 4ba9 ldr r3, [pc, #676] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bb8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001bbc: 4aa7 ldr r2, [pc, #668] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bbe: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8001bc2: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 8001bc6: 4ba5 ldr r3, [pc, #660] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bc8: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
- 8001bcc: 687b ldr r3, [r7, #4]
- 8001bce: 6b9b ldr r3, [r3, #56] ; 0x38
- 8001bd0: 49a2 ldr r1, [pc, #648] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bd2: 4313 orrs r3, r2
- 8001bd4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*-------------------------------------- I2C1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 8001bd8: 687b ldr r3, [r7, #4]
- 8001bda: 681b ldr r3, [r3, #0]
- 8001bdc: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8001be0: 2b00 cmp r3, #0
- 8001be2: d00a beq.n 8001bfa <HAL_RCCEx_PeriphCLKConfig+0x24a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-
- /* Configure the I2C1 clock source */
- __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8001be4: 4b9d ldr r3, [pc, #628] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001be6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001bea: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8001bee: 687b ldr r3, [r7, #4]
- 8001bf0: 6e5b ldr r3, [r3, #100] ; 0x64
- 8001bf2: 499a ldr r1, [pc, #616] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bf4: 4313 orrs r3, r2
- 8001bf6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 8001bfa: 687b ldr r3, [r7, #4]
- 8001bfc: 681b ldr r3, [r3, #0]
- 8001bfe: f403 4300 and.w r3, r3, #32768 ; 0x8000
- 8001c02: 2b00 cmp r3, #0
- 8001c04: d00a beq.n 8001c1c <HAL_RCCEx_PeriphCLKConfig+0x26c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-
- /* Configure the I2C2 clock source */
- __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8001c06: 4b95 ldr r3, [pc, #596] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c08: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001c0c: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
- 8001c10: 687b ldr r3, [r7, #4]
- 8001c12: 6e9b ldr r3, [r3, #104] ; 0x68
- 8001c14: 4991 ldr r1, [pc, #580] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c16: 4313 orrs r3, r2
- 8001c18: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8001c1c: 687b ldr r3, [r7, #4]
- 8001c1e: 681b ldr r3, [r3, #0]
- 8001c20: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8001c24: 2b00 cmp r3, #0
- 8001c26: d00a beq.n 8001c3e <HAL_RCCEx_PeriphCLKConfig+0x28e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-
- /* Configure the I2C3 clock source */
- __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8001c28: 4b8c ldr r3, [pc, #560] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c2a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001c2e: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8001c32: 687b ldr r3, [r7, #4]
- 8001c34: 6edb ldr r3, [r3, #108] ; 0x6c
- 8001c36: 4989 ldr r1, [pc, #548] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c38: 4313 orrs r3, r2
- 8001c3a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- I2C4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8001c3e: 687b ldr r3, [r7, #4]
- 8001c40: 681b ldr r3, [r3, #0]
- 8001c42: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8001c46: 2b00 cmp r3, #0
- 8001c48: d00a beq.n 8001c60 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
- /* Configure the I2C4 clock source */
- __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8001c4a: 4b84 ldr r3, [pc, #528] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c4c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001c50: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8001c54: 687b ldr r3, [r7, #4]
- 8001c56: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001c58: 4980 ldr r1, [pc, #512] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c5a: 4313 orrs r3, r2
- 8001c5c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8001c60: 687b ldr r3, [r7, #4]
- 8001c62: 681b ldr r3, [r3, #0]
- 8001c64: f003 0340 and.w r3, r3, #64 ; 0x40
- 8001c68: 2b00 cmp r3, #0
- 8001c6a: d00a beq.n 8001c82 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-
- /* Configure the USART1 clock source */
- __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8001c6c: 4b7b ldr r3, [pc, #492] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c6e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001c72: f023 0203 bic.w r2, r3, #3
- 8001c76: 687b ldr r3, [r7, #4]
- 8001c78: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001c7a: 4978 ldr r1, [pc, #480] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c7c: 4313 orrs r3, r2
- 8001c7e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART2 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8001c82: 687b ldr r3, [r7, #4]
- 8001c84: 681b ldr r3, [r3, #0]
- 8001c86: f003 0380 and.w r3, r3, #128 ; 0x80
- 8001c8a: 2b00 cmp r3, #0
- 8001c8c: d00a beq.n 8001ca4 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-
- /* Configure the USART2 clock source */
- __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8001c8e: 4b73 ldr r3, [pc, #460] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c90: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001c94: f023 020c bic.w r2, r3, #12
- 8001c98: 687b ldr r3, [r7, #4]
- 8001c9a: 6c9b ldr r3, [r3, #72] ; 0x48
- 8001c9c: 496f ldr r1, [pc, #444] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c9e: 4313 orrs r3, r2
- 8001ca0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART3 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8001ca4: 687b ldr r3, [r7, #4]
- 8001ca6: 681b ldr r3, [r3, #0]
- 8001ca8: f403 7380 and.w r3, r3, #256 ; 0x100
- 8001cac: 2b00 cmp r3, #0
- 8001cae: d00a beq.n 8001cc6 <HAL_RCCEx_PeriphCLKConfig+0x316>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-
- /* Configure the USART3 clock source */
- __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8001cb0: 4b6a ldr r3, [pc, #424] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001cb2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001cb6: f023 0230 bic.w r2, r3, #48 ; 0x30
- 8001cba: 687b ldr r3, [r7, #4]
- 8001cbc: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8001cbe: 4967 ldr r1, [pc, #412] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001cc0: 4313 orrs r3, r2
- 8001cc2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART4 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8001cc6: 687b ldr r3, [r7, #4]
- 8001cc8: 681b ldr r3, [r3, #0]
- 8001cca: f403 7300 and.w r3, r3, #512 ; 0x200
- 8001cce: 2b00 cmp r3, #0
- 8001cd0: d00a beq.n 8001ce8 <HAL_RCCEx_PeriphCLKConfig+0x338>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-
- /* Configure the UART4 clock source */
- __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8001cd2: 4b62 ldr r3, [pc, #392] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001cd4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001cd8: f023 02c0 bic.w r2, r3, #192 ; 0xc0
- 8001cdc: 687b ldr r3, [r7, #4]
- 8001cde: 6d1b ldr r3, [r3, #80] ; 0x50
- 8001ce0: 495e ldr r1, [pc, #376] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ce2: 4313 orrs r3, r2
- 8001ce4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART5 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8001ce8: 687b ldr r3, [r7, #4]
- 8001cea: 681b ldr r3, [r3, #0]
- 8001cec: f403 6380 and.w r3, r3, #1024 ; 0x400
- 8001cf0: 2b00 cmp r3, #0
- 8001cf2: d00a beq.n 8001d0a <HAL_RCCEx_PeriphCLKConfig+0x35a>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-
- /* Configure the UART5 clock source */
- __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8001cf4: 4b59 ldr r3, [pc, #356] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001cf6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001cfa: f423 7240 bic.w r2, r3, #768 ; 0x300
- 8001cfe: 687b ldr r3, [r7, #4]
- 8001d00: 6d5b ldr r3, [r3, #84] ; 0x54
- 8001d02: 4956 ldr r1, [pc, #344] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d04: 4313 orrs r3, r2
- 8001d06: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- USART6 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8001d0a: 687b ldr r3, [r7, #4]
- 8001d0c: 681b ldr r3, [r3, #0]
- 8001d0e: f403 6300 and.w r3, r3, #2048 ; 0x800
- 8001d12: 2b00 cmp r3, #0
- 8001d14: d00a beq.n 8001d2c <HAL_RCCEx_PeriphCLKConfig+0x37c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
-
- /* Configure the USART6 clock source */
- __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8001d16: 4b51 ldr r3, [pc, #324] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d18: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001d1c: f423 6240 bic.w r2, r3, #3072 ; 0xc00
- 8001d20: 687b ldr r3, [r7, #4]
- 8001d22: 6d9b ldr r3, [r3, #88] ; 0x58
- 8001d24: 494d ldr r1, [pc, #308] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d26: 4313 orrs r3, r2
- 8001d28: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART7 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8001d2c: 687b ldr r3, [r7, #4]
- 8001d2e: 681b ldr r3, [r3, #0]
- 8001d30: f403 5380 and.w r3, r3, #4096 ; 0x1000
- 8001d34: 2b00 cmp r3, #0
- 8001d36: d00a beq.n 8001d4e <HAL_RCCEx_PeriphCLKConfig+0x39e>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
-
- /* Configure the UART7 clock source */
- __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8001d38: 4b48 ldr r3, [pc, #288] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d3a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001d3e: f423 5240 bic.w r2, r3, #12288 ; 0x3000
- 8001d42: 687b ldr r3, [r7, #4]
- 8001d44: 6ddb ldr r3, [r3, #92] ; 0x5c
- 8001d46: 4945 ldr r1, [pc, #276] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d48: 4313 orrs r3, r2
- 8001d4a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- UART8 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 8001d4e: 687b ldr r3, [r7, #4]
- 8001d50: 681b ldr r3, [r3, #0]
- 8001d52: f403 5300 and.w r3, r3, #8192 ; 0x2000
- 8001d56: 2b00 cmp r3, #0
- 8001d58: d00a beq.n 8001d70 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
- {
- /* Check the parameters */
- assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
-
- /* Configure the UART8 clock source */
- __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 8001d5a: 4b40 ldr r3, [pc, #256] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d5c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001d60: f423 4240 bic.w r2, r3, #49152 ; 0xc000
- 8001d64: 687b ldr r3, [r7, #4]
- 8001d66: 6e1b ldr r3, [r3, #96] ; 0x60
- 8001d68: 493c ldr r1, [pc, #240] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d6a: 4313 orrs r3, r2
- 8001d6c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*--------------------------------------- CEC Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 8001d70: 687b ldr r3, [r7, #4]
- 8001d72: 681b ldr r3, [r3, #0]
- 8001d74: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8001d78: 2b00 cmp r3, #0
- 8001d7a: d00a beq.n 8001d92 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
- /* Configure the CEC clock source */
- __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 8001d7c: 4b37 ldr r3, [pc, #220] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d7e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001d82: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8001d86: 687b ldr r3, [r7, #4]
- 8001d88: 6f9b ldr r3, [r3, #120] ; 0x78
- 8001d8a: 4934 ldr r1, [pc, #208] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001d8c: 4313 orrs r3, r2
- 8001d8e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*-------------------------------------- CK48 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 8001d92: 687b ldr r3, [r7, #4]
- 8001d94: 681b ldr r3, [r3, #0]
- 8001d96: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8001d9a: 2b00 cmp r3, #0
- 8001d9c: d011 beq.n 8001dc2 <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- /* Check the parameters */
- assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
-
- /* Configure the CLK48 source */
- __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 8001d9e: 4b2f ldr r3, [pc, #188] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001da0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001da4: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
- 8001da8: 687b ldr r3, [r7, #4]
- 8001daa: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8001dac: 492b ldr r1, [pc, #172] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001dae: 4313 orrs r3, r2
- 8001db0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
-
- /* Enable the PLLSAI when it's used as clock source for CK48 */
- if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 8001db4: 687b ldr r3, [r7, #4]
- 8001db6: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8001db8: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8001dbc: d101 bne.n 8001dc2 <HAL_RCCEx_PeriphCLKConfig+0x412>
- {
- pllsaiused = 1;
- 8001dbe: 2301 movs r3, #1
- 8001dc0: 61bb str r3, [r7, #24]
- }
- }
-
- /*-------------------------------------- LTDC Configuration -----------------------------------*/
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 8001dc2: 687b ldr r3, [r7, #4]
- 8001dc4: 681b ldr r3, [r3, #0]
- 8001dc6: f003 0308 and.w r3, r3, #8
- 8001dca: 2b00 cmp r3, #0
- 8001dcc: d001 beq.n 8001dd2 <HAL_RCCEx_PeriphCLKConfig+0x422>
- {
- pllsaiused = 1;
- 8001dce: 2301 movs r3, #1
- 8001dd0: 61bb str r3, [r7, #24]
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 8001dd2: 687b ldr r3, [r7, #4]
- 8001dd4: 681b ldr r3, [r3, #0]
- 8001dd6: f403 2380 and.w r3, r3, #262144 ; 0x40000
- 8001dda: 2b00 cmp r3, #0
- 8001ddc: d00a beq.n 8001df4 <HAL_RCCEx_PeriphCLKConfig+0x444>
- {
- /* Check the parameters */
- assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
-
- /* Configure the LTPIM1 clock source */
- __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 8001dde: 4b1f ldr r3, [pc, #124] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001de0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001de4: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
- 8001de8: 687b ldr r3, [r7, #4]
- 8001dea: 6f5b ldr r3, [r3, #116] ; 0x74
- 8001dec: 491b ldr r1, [pc, #108] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001dee: 4313 orrs r3, r2
- 8001df0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 8001df4: 687b ldr r3, [r7, #4]
- 8001df6: 681b ldr r3, [r3, #0]
- 8001df8: f403 0300 and.w r3, r3, #8388608 ; 0x800000
- 8001dfc: 2b00 cmp r3, #0
- 8001dfe: d00b beq.n 8001e18 <HAL_RCCEx_PeriphCLKConfig+0x468>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
-
- /* Configure the SDMMC1 clock source */
- __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 8001e00: 4b16 ldr r3, [pc, #88] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e02: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001e06: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
- 8001e0a: 687b ldr r3, [r7, #4]
- 8001e0c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
- 8001e10: 4912 ldr r1, [pc, #72] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e12: 4313 orrs r3, r2
- 8001e14: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
-#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
- /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 8001e18: 687b ldr r3, [r7, #4]
- 8001e1a: 681b ldr r3, [r3, #0]
- 8001e1c: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
- 8001e20: 2b00 cmp r3, #0
- 8001e22: d00b beq.n 8001e3c <HAL_RCCEx_PeriphCLKConfig+0x48c>
- {
- /* Check the parameters */
- assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
-
- /* Configure the SDMMC2 clock source */
- __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 8001e24: 4b0d ldr r3, [pc, #52] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e26: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001e2a: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
- 8001e2e: 687b ldr r3, [r7, #4]
- 8001e30: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001e34: 4909 ldr r1, [pc, #36] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e36: 4313 orrs r3, r2
- 8001e38: f8c1 3090 str.w r3, [r1, #144] ; 0x90
- }
-
- /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 8001e3c: 687b ldr r3, [r7, #4]
- 8001e3e: 681b ldr r3, [r3, #0]
- 8001e40: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8001e44: 2b00 cmp r3, #0
- 8001e46: d00f beq.n 8001e68 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
- /* Configure the DFSDM1 interface clock source */
- __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8001e48: 4b04 ldr r3, [pc, #16] ; (8001e5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001e4a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001e4e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
- 8001e52: 687b ldr r3, [r7, #4]
- 8001e54: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001e58: e002 b.n 8001e60 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 8001e5a: bf00 nop
- 8001e5c: 40023800 .word 0x40023800
- 8001e60: 4985 ldr r1, [pc, #532] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e62: 4313 orrs r3, r2
- 8001e64: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8001e68: 687b ldr r3, [r7, #4]
- 8001e6a: 681b ldr r3, [r3, #0]
- 8001e6c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001e70: 2b00 cmp r3, #0
- 8001e72: d00b beq.n 8001e8c <HAL_RCCEx_PeriphCLKConfig+0x4dc>
- {
- /* Check the parameters */
- assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
- /* Configure the DFSDM interface clock source */
- __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 8001e74: 4b80 ldr r3, [pc, #512] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e76: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001e7a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8001e7e: 687b ldr r3, [r7, #4]
- 8001e80: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001e84: 497c ldr r1, [pc, #496] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e86: 4313 orrs r3, r2
- 8001e88: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
- /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
- /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
- if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 8001e8c: 69fb ldr r3, [r7, #28]
- 8001e8e: 2b01 cmp r3, #1
- 8001e90: d005 beq.n 8001e9e <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 8001e92: 687b ldr r3, [r7, #4]
- 8001e94: 681b ldr r3, [r3, #0]
- 8001e96: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 8001e9a: f040 80d6 bne.w 800204a <HAL_RCCEx_PeriphCLKConfig+0x69a>
- {
- /* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
- 8001e9e: 4b76 ldr r3, [pc, #472] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ea0: 681b ldr r3, [r3, #0]
- 8001ea2: 4a75 ldr r2, [pc, #468] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ea4: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
- 8001ea8: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8001eaa: f7fe fe57 bl 8000b5c <HAL_GetTick>
- 8001eae: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8001eb0: e008 b.n 8001ec4 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8001eb2: f7fe fe53 bl 8000b5c <HAL_GetTick>
- 8001eb6: 4602 mov r2, r0
- 8001eb8: 697b ldr r3, [r7, #20]
- 8001eba: 1ad3 subs r3, r2, r3
- 8001ebc: 2b64 cmp r3, #100 ; 0x64
- 8001ebe: d901 bls.n 8001ec4 <HAL_RCCEx_PeriphCLKConfig+0x514>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8001ec0: 2303 movs r3, #3
- 8001ec2: e194 b.n 80021ee <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8001ec4: 4b6c ldr r3, [pc, #432] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ec6: 681b ldr r3, [r3, #0]
- 8001ec8: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8001ecc: 2b00 cmp r3, #0
- 8001ece: d1f0 bne.n 8001eb2 <HAL_RCCEx_PeriphCLKConfig+0x502>
-
- /* check for common PLLI2S Parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
- /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 8001ed0: 687b ldr r3, [r7, #4]
- 8001ed2: 681b ldr r3, [r3, #0]
- 8001ed4: f003 0301 and.w r3, r3, #1
- 8001ed8: 2b00 cmp r3, #0
- 8001eda: d021 beq.n 8001f20 <HAL_RCCEx_PeriphCLKConfig+0x570>
- 8001edc: 687b ldr r3, [r7, #4]
- 8001ede: 6b5b ldr r3, [r3, #52] ; 0x34
- 8001ee0: 2b00 cmp r3, #0
- 8001ee2: d11d bne.n 8001f20 <HAL_RCCEx_PeriphCLKConfig+0x570>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
- /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8001ee4: 4b64 ldr r3, [pc, #400] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ee6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001eea: 0c1b lsrs r3, r3, #16
- 8001eec: f003 0303 and.w r3, r3, #3
- 8001ef0: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8001ef2: 4b61 ldr r3, [pc, #388] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ef4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001ef8: 0e1b lsrs r3, r3, #24
- 8001efa: f003 030f and.w r3, r3, #15
- 8001efe: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 8001f00: 687b ldr r3, [r7, #4]
- 8001f02: 685b ldr r3, [r3, #4]
- 8001f04: 019a lsls r2, r3, #6
- 8001f06: 693b ldr r3, [r7, #16]
- 8001f08: 041b lsls r3, r3, #16
- 8001f0a: 431a orrs r2, r3
- 8001f0c: 68fb ldr r3, [r7, #12]
- 8001f0e: 061b lsls r3, r3, #24
- 8001f10: 431a orrs r2, r3
- 8001f12: 687b ldr r3, [r7, #4]
- 8001f14: 689b ldr r3, [r3, #8]
- 8001f16: 071b lsls r3, r3, #28
- 8001f18: 4957 ldr r1, [pc, #348] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f1a: 4313 orrs r3, r2
- 8001f1c: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8001f20: 687b ldr r3, [r7, #4]
- 8001f22: 681b ldr r3, [r3, #0]
- 8001f24: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8001f28: 2b00 cmp r3, #0
- 8001f2a: d004 beq.n 8001f36 <HAL_RCCEx_PeriphCLKConfig+0x586>
- 8001f2c: 687b ldr r3, [r7, #4]
- 8001f2e: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001f30: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8001f34: d00a beq.n 8001f4c <HAL_RCCEx_PeriphCLKConfig+0x59c>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8001f36: 687b ldr r3, [r7, #4]
- 8001f38: 681b ldr r3, [r3, #0]
- 8001f3a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8001f3e: 2b00 cmp r3, #0
- 8001f40: d02e beq.n 8001fa0 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8001f42: 687b ldr r3, [r7, #4]
- 8001f44: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001f46: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8001f4a: d129 bne.n 8001fa0 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
- /* Check for PLLI2S/DIVQ parameters */
- assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
- /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8001f4c: 4b4a ldr r3, [pc, #296] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f4e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001f52: 0c1b lsrs r3, r3, #16
- 8001f54: f003 0303 and.w r3, r3, #3
- 8001f58: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8001f5a: 4b47 ldr r3, [pc, #284] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f5c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001f60: 0f1b lsrs r3, r3, #28
- 8001f62: f003 0307 and.w r3, r3, #7
- 8001f66: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
- /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
- /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8001f68: 687b ldr r3, [r7, #4]
- 8001f6a: 685b ldr r3, [r3, #4]
- 8001f6c: 019a lsls r2, r3, #6
- 8001f6e: 693b ldr r3, [r7, #16]
- 8001f70: 041b lsls r3, r3, #16
- 8001f72: 431a orrs r2, r3
- 8001f74: 687b ldr r3, [r7, #4]
- 8001f76: 68db ldr r3, [r3, #12]
- 8001f78: 061b lsls r3, r3, #24
- 8001f7a: 431a orrs r2, r3
- 8001f7c: 68fb ldr r3, [r7, #12]
- 8001f7e: 071b lsls r3, r3, #28
- 8001f80: 493d ldr r1, [pc, #244] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f82: 4313 orrs r3, r2
- 8001f84: f8c1 3084 str.w r3, [r1, #132] ; 0x84
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8001f88: 4b3b ldr r3, [pc, #236] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f8a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001f8e: f023 021f bic.w r2, r3, #31
- 8001f92: 687b ldr r3, [r7, #4]
- 8001f94: 6a5b ldr r3, [r3, #36] ; 0x24
- 8001f96: 3b01 subs r3, #1
- 8001f98: 4937 ldr r1, [pc, #220] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001f9a: 4313 orrs r3, r2
- 8001f9c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8001fa0: 687b ldr r3, [r7, #4]
- 8001fa2: 681b ldr r3, [r3, #0]
- 8001fa4: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8001fa8: 2b00 cmp r3, #0
- 8001faa: d01d beq.n 8001fe8 <HAL_RCCEx_PeriphCLKConfig+0x638>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-
- /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8001fac: 4b32 ldr r3, [pc, #200] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001fae: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001fb2: 0e1b lsrs r3, r3, #24
- 8001fb4: f003 030f and.w r3, r3, #15
- 8001fb8: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8001fba: 4b2f ldr r3, [pc, #188] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001fbc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001fc0: 0f1b lsrs r3, r3, #28
- 8001fc2: f003 0307 and.w r3, r3, #7
- 8001fc6: 60fb str r3, [r7, #12]
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
- /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 8001fc8: 687b ldr r3, [r7, #4]
- 8001fca: 685b ldr r3, [r3, #4]
- 8001fcc: 019a lsls r2, r3, #6
- 8001fce: 687b ldr r3, [r7, #4]
- 8001fd0: 691b ldr r3, [r3, #16]
- 8001fd2: 041b lsls r3, r3, #16
- 8001fd4: 431a orrs r2, r3
- 8001fd6: 693b ldr r3, [r7, #16]
- 8001fd8: 061b lsls r3, r3, #24
- 8001fda: 431a orrs r2, r3
- 8001fdc: 68fb ldr r3, [r7, #12]
- 8001fde: 071b lsls r3, r3, #28
- 8001fe0: 4925 ldr r1, [pc, #148] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001fe2: 4313 orrs r3, r2
- 8001fe4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /*----------------- In Case of PLLI2S is just selected -----------------*/
- if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 8001fe8: 687b ldr r3, [r7, #4]
- 8001fea: 681b ldr r3, [r3, #0]
- 8001fec: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8001ff0: 2b00 cmp r3, #0
- 8001ff2: d011 beq.n 8002018 <HAL_RCCEx_PeriphCLKConfig+0x668>
- assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
- /* Configure the PLLI2S division factors */
- /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
- /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
- __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 8001ff4: 687b ldr r3, [r7, #4]
- 8001ff6: 685b ldr r3, [r3, #4]
- 8001ff8: 019a lsls r2, r3, #6
- 8001ffa: 687b ldr r3, [r7, #4]
- 8001ffc: 691b ldr r3, [r3, #16]
- 8001ffe: 041b lsls r3, r3, #16
- 8002000: 431a orrs r2, r3
- 8002002: 687b ldr r3, [r7, #4]
- 8002004: 68db ldr r3, [r3, #12]
- 8002006: 061b lsls r3, r3, #24
- 8002008: 431a orrs r2, r3
- 800200a: 687b ldr r3, [r7, #4]
- 800200c: 689b ldr r3, [r3, #8]
- 800200e: 071b lsls r3, r3, #28
- 8002010: 4919 ldr r1, [pc, #100] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002012: 4313 orrs r3, r2
- 8002014: f8c1 3084 str.w r3, [r1, #132] ; 0x84
- }
-
- /* Enable the PLLI2S */
- __HAL_RCC_PLLI2S_ENABLE();
- 8002018: 4b17 ldr r3, [pc, #92] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800201a: 681b ldr r3, [r3, #0]
- 800201c: 4a16 ldr r2, [pc, #88] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 800201e: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
- 8002022: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 8002024: f7fe fd9a bl 8000b5c <HAL_GetTick>
- 8002028: 6178 str r0, [r7, #20]
-
- /* Wait till PLLI2S is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 800202a: e008 b.n 800203e <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 800202c: f7fe fd96 bl 8000b5c <HAL_GetTick>
- 8002030: 4602 mov r2, r0
- 8002032: 697b ldr r3, [r7, #20]
- 8002034: 1ad3 subs r3, r2, r3
- 8002036: 2b64 cmp r3, #100 ; 0x64
- 8002038: d901 bls.n 800203e <HAL_RCCEx_PeriphCLKConfig+0x68e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 800203a: 2303 movs r3, #3
- 800203c: e0d7 b.n 80021ee <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 800203e: 4b0e ldr r3, [pc, #56] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002040: 681b ldr r3, [r3, #0]
- 8002042: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8002046: 2b00 cmp r3, #0
- 8002048: d0f0 beq.n 800202c <HAL_RCCEx_PeriphCLKConfig+0x67c>
- }
- }
-
- /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
- /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
- if(pllsaiused == 1)
- 800204a: 69bb ldr r3, [r7, #24]
- 800204c: 2b01 cmp r3, #1
- 800204e: f040 80cd bne.w 80021ec <HAL_RCCEx_PeriphCLKConfig+0x83c>
- {
- /* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
- 8002052: 4b09 ldr r3, [pc, #36] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002054: 681b ldr r3, [r3, #0]
- 8002056: 4a08 ldr r2, [pc, #32] ; (8002078 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8002058: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 800205c: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 800205e: f7fe fd7d bl 8000b5c <HAL_GetTick>
- 8002062: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is disabled */
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8002064: e00a b.n 800207c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8002066: f7fe fd79 bl 8000b5c <HAL_GetTick>
- 800206a: 4602 mov r2, r0
- 800206c: 697b ldr r3, [r7, #20]
- 800206e: 1ad3 subs r3, r2, r3
- 8002070: 2b64 cmp r3, #100 ; 0x64
- 8002072: d903 bls.n 800207c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 8002074: 2303 movs r3, #3
- 8002076: e0ba b.n 80021ee <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 8002078: 40023800 .word 0x40023800
- while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 800207c: 4b5e ldr r3, [pc, #376] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800207e: 681b ldr r3, [r3, #0]
- 8002080: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8002084: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8002088: d0ed beq.n 8002066 <HAL_RCCEx_PeriphCLKConfig+0x6b6>
-
- /* Check the PLLSAI division factors */
- assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
- /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 800208a: 687b ldr r3, [r7, #4]
- 800208c: 681b ldr r3, [r3, #0]
- 800208e: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8002092: 2b00 cmp r3, #0
- 8002094: d003 beq.n 800209e <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 8002096: 687b ldr r3, [r7, #4]
- 8002098: 6bdb ldr r3, [r3, #60] ; 0x3c
- 800209a: 2b00 cmp r3, #0
- 800209c: d009 beq.n 80020b2 <HAL_RCCEx_PeriphCLKConfig+0x702>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 800209e: 687b ldr r3, [r7, #4]
- 80020a0: 681b ldr r3, [r3, #0]
- 80020a2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 80020a6: 2b00 cmp r3, #0
- 80020a8: d02e beq.n 8002108 <HAL_RCCEx_PeriphCLKConfig+0x758>
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 80020aa: 687b ldr r3, [r7, #4]
- 80020ac: 6c1b ldr r3, [r3, #64] ; 0x40
- 80020ae: 2b00 cmp r3, #0
- 80020b0: d12a bne.n 8002108 <HAL_RCCEx_PeriphCLKConfig+0x758>
- assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
- /* check for PLLSAI/DIVQ Parameter */
- assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
- /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 80020b2: 4b51 ldr r3, [pc, #324] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80020b4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80020b8: 0c1b lsrs r3, r3, #16
- 80020ba: f003 0303 and.w r3, r3, #3
- 80020be: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 80020c0: 4b4d ldr r3, [pc, #308] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80020c2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 80020c6: 0f1b lsrs r3, r3, #28
- 80020c8: f003 0307 and.w r3, r3, #7
- 80020cc: 60fb str r3, [r7, #12]
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 80020ce: 687b ldr r3, [r7, #4]
- 80020d0: 695b ldr r3, [r3, #20]
- 80020d2: 019a lsls r2, r3, #6
- 80020d4: 693b ldr r3, [r7, #16]
- 80020d6: 041b lsls r3, r3, #16
- 80020d8: 431a orrs r2, r3
- 80020da: 687b ldr r3, [r7, #4]
- 80020dc: 699b ldr r3, [r3, #24]
- 80020de: 061b lsls r3, r3, #24
- 80020e0: 431a orrs r2, r3
- 80020e2: 68fb ldr r3, [r7, #12]
- 80020e4: 071b lsls r3, r3, #28
- 80020e6: 4944 ldr r1, [pc, #272] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80020e8: 4313 orrs r3, r2
- 80020ea: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 80020ee: 4b42 ldr r3, [pc, #264] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80020f0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80020f4: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
- 80020f8: 687b ldr r3, [r7, #4]
- 80020fa: 6a9b ldr r3, [r3, #40] ; 0x28
- 80020fc: 3b01 subs r3, #1
- 80020fe: 021b lsls r3, r3, #8
- 8002100: 493d ldr r1, [pc, #244] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002102: 4313 orrs r3, r2
- 8002104: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-
- /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
- /* In Case of PLLI2S is selected as source clock for CK48 */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 8002108: 687b ldr r3, [r7, #4]
- 800210a: 681b ldr r3, [r3, #0]
- 800210c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8002110: 2b00 cmp r3, #0
- 8002112: d022 beq.n 800215a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 8002114: 687b ldr r3, [r7, #4]
- 8002116: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002118: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 800211c: d11d bne.n 800215a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- {
- /* check for Parameters */
- assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
- /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 800211e: 4b36 ldr r3, [pc, #216] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002120: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8002124: 0e1b lsrs r3, r3, #24
- 8002126: f003 030f and.w r3, r3, #15
- 800212a: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 800212c: 4b32 ldr r3, [pc, #200] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800212e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8002132: 0f1b lsrs r3, r3, #28
- 8002134: f003 0307 and.w r3, r3, #7
- 8002138: 60fb str r3, [r7, #12]
-
- /* Configure the PLLSAI division factors */
- /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
- /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 800213a: 687b ldr r3, [r7, #4]
- 800213c: 695b ldr r3, [r3, #20]
- 800213e: 019a lsls r2, r3, #6
- 8002140: 687b ldr r3, [r7, #4]
- 8002142: 6a1b ldr r3, [r3, #32]
- 8002144: 041b lsls r3, r3, #16
- 8002146: 431a orrs r2, r3
- 8002148: 693b ldr r3, [r7, #16]
- 800214a: 061b lsls r3, r3, #24
- 800214c: 431a orrs r2, r3
- 800214e: 68fb ldr r3, [r7, #12]
- 8002150: 071b lsls r3, r3, #28
- 8002152: 4929 ldr r1, [pc, #164] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002154: 4313 orrs r3, r2
- 8002156: f8c1 3088 str.w r3, [r1, #136] ; 0x88
- }
-
-#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
- /*---------------------------- LTDC configuration -------------------------------*/
- if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 800215a: 687b ldr r3, [r7, #4]
- 800215c: 681b ldr r3, [r3, #0]
- 800215e: f003 0308 and.w r3, r3, #8
- 8002162: 2b00 cmp r3, #0
- 8002164: d028 beq.n 80021b8 <HAL_RCCEx_PeriphCLKConfig+0x808>
- {
- assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
- assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
- /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 8002166: 4b24 ldr r3, [pc, #144] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002168: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800216c: 0e1b lsrs r3, r3, #24
- 800216e: f003 030f and.w r3, r3, #15
- 8002172: 613b str r3, [r7, #16]
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8002174: 4b20 ldr r3, [pc, #128] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8002176: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800217a: 0c1b lsrs r3, r3, #16
- 800217c: f003 0303 and.w r3, r3, #3
- 8002180: 60fb str r3, [r7, #12]
-
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
- /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
- /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 8002182: 687b ldr r3, [r7, #4]
- 8002184: 695b ldr r3, [r3, #20]
- 8002186: 019a lsls r2, r3, #6
- 8002188: 68fb ldr r3, [r7, #12]
- 800218a: 041b lsls r3, r3, #16
- 800218c: 431a orrs r2, r3
- 800218e: 693b ldr r3, [r7, #16]
- 8002190: 061b lsls r3, r3, #24
- 8002192: 431a orrs r2, r3
- 8002194: 687b ldr r3, [r7, #4]
- 8002196: 69db ldr r3, [r3, #28]
- 8002198: 071b lsls r3, r3, #28
- 800219a: 4917 ldr r1, [pc, #92] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 800219c: 4313 orrs r3, r2
- 800219e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
-
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
- __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 80021a2: 4b15 ldr r3, [pc, #84] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021a4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80021a8: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 80021ac: 687b ldr r3, [r7, #4]
- 80021ae: 6adb ldr r3, [r3, #44] ; 0x2c
- 80021b0: 4911 ldr r1, [pc, #68] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021b2: 4313 orrs r3, r2
- 80021b4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
- }
-#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
-
- /* Enable PLLSAI Clock */
- __HAL_RCC_PLLSAI_ENABLE();
- 80021b8: 4b0f ldr r3, [pc, #60] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021ba: 681b ldr r3, [r3, #0]
- 80021bc: 4a0e ldr r2, [pc, #56] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021be: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80021c2: 6013 str r3, [r2, #0]
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
- 80021c4: f7fe fcca bl 8000b5c <HAL_GetTick>
- 80021c8: 6178 str r0, [r7, #20]
-
- /* Wait till PLLSAI is ready */
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 80021ca: e008 b.n 80021de <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 80021cc: f7fe fcc6 bl 8000b5c <HAL_GetTick>
- 80021d0: 4602 mov r2, r0
- 80021d2: 697b ldr r3, [r7, #20]
- 80021d4: 1ad3 subs r3, r2, r3
- 80021d6: 2b64 cmp r3, #100 ; 0x64
- 80021d8: d901 bls.n 80021de <HAL_RCCEx_PeriphCLKConfig+0x82e>
- {
- /* return in case of Timeout detected */
- return HAL_TIMEOUT;
- 80021da: 2303 movs r3, #3
- 80021dc: e007 b.n 80021ee <HAL_RCCEx_PeriphCLKConfig+0x83e>
- while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 80021de: 4b06 ldr r3, [pc, #24] ; (80021f8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 80021e0: 681b ldr r3, [r3, #0]
- 80021e2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 80021e6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 80021ea: d1ef bne.n 80021cc <HAL_RCCEx_PeriphCLKConfig+0x81c>
- }
- }
- }
- return HAL_OK;
- 80021ec: 2300 movs r3, #0
-}
- 80021ee: 4618 mov r0, r3
- 80021f0: 3720 adds r7, #32
- 80021f2: 46bd mov sp, r7
- 80021f4: bd80 pop {r7, pc}
- 80021f6: bf00 nop
- 80021f8: 40023800 .word 0x40023800
-
-080021fc <HAL_TIM_Base_Init>:
- * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- 80021fc: b580 push {r7, lr}
- 80021fe: b082 sub sp, #8
- 8002200: af00 add r7, sp, #0
- 8002202: 6078 str r0, [r7, #4]
- /* Check the TIM handle allocation */
- if (htim == NULL)
- 8002204: 687b ldr r3, [r7, #4]
- 8002206: 2b00 cmp r3, #0
- 8002208: d101 bne.n 800220e <HAL_TIM_Base_Init+0x12>
- {
- return HAL_ERROR;
- 800220a: 2301 movs r3, #1
- 800220c: e01d b.n 800224a <HAL_TIM_Base_Init+0x4e>
- assert_param(IS_TIM_INSTANCE(htim->Instance));
- assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
- if (htim->State == HAL_TIM_STATE_RESET)
- 800220e: 687b ldr r3, [r7, #4]
- 8002210: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8002214: b2db uxtb r3, r3
- 8002216: 2b00 cmp r3, #0
- 8002218: d106 bne.n 8002228 <HAL_TIM_Base_Init+0x2c>
- {
- /* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
- 800221a: 687b ldr r3, [r7, #4]
- 800221c: 2200 movs r2, #0
- 800221e: f883 203c strb.w r2, [r3, #60] ; 0x3c
- }
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- htim->Base_MspInitCallback(htim);
-#else
- /* Init the low level hardware : GPIO, CLOCK, NVIC */
- HAL_TIM_Base_MspInit(htim);
- 8002222: 6878 ldr r0, [r7, #4]
- 8002224: f7fe fb36 bl 8000894 <HAL_TIM_Base_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
-
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
- 8002228: 687b ldr r3, [r7, #4]
- 800222a: 2202 movs r2, #2
- 800222c: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8002230: 687b ldr r3, [r7, #4]
- 8002232: 681a ldr r2, [r3, #0]
- 8002234: 687b ldr r3, [r7, #4]
- 8002236: 3304 adds r3, #4
- 8002238: 4619 mov r1, r3
- 800223a: 4610 mov r0, r2
- 800223c: f000 fa36 bl 80026ac <TIM_Base_SetConfig>
-
- /* Initialize the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
- 8002240: 687b ldr r3, [r7, #4]
- 8002242: 2201 movs r2, #1
- 8002244: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- return HAL_OK;
- 8002248: 2300 movs r3, #0
-}
- 800224a: 4618 mov r0, r3
- 800224c: 3708 adds r7, #8
- 800224e: 46bd mov sp, r7
- 8002250: bd80 pop {r7, pc}
- ...
-
-08002254 <HAL_TIM_Base_Start_IT>:
- * @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM Base handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- 8002254: b480 push {r7}
- 8002256: b085 sub sp, #20
- 8002258: af00 add r7, sp, #0
- 800225a: 6078 str r0, [r7, #4]
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- 800225c: 687b ldr r3, [r7, #4]
- 800225e: 681b ldr r3, [r3, #0]
- 8002260: 68da ldr r2, [r3, #12]
- 8002262: 687b ldr r3, [r7, #4]
- 8002264: 681b ldr r3, [r3, #0]
- 8002266: f042 0201 orr.w r2, r2, #1
- 800226a: 60da str r2, [r3, #12]
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 800226c: 687b ldr r3, [r7, #4]
- 800226e: 681b ldr r3, [r3, #0]
- 8002270: 689a ldr r2, [r3, #8]
- 8002272: 4b0c ldr r3, [pc, #48] ; (80022a4 <HAL_TIM_Base_Start_IT+0x50>)
- 8002274: 4013 ands r3, r2
- 8002276: 60fb str r3, [r7, #12]
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8002278: 68fb ldr r3, [r7, #12]
- 800227a: 2b06 cmp r3, #6
- 800227c: d00b beq.n 8002296 <HAL_TIM_Base_Start_IT+0x42>
- 800227e: 68fb ldr r3, [r7, #12]
- 8002280: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8002284: d007 beq.n 8002296 <HAL_TIM_Base_Start_IT+0x42>
- {
- __HAL_TIM_ENABLE(htim);
- 8002286: 687b ldr r3, [r7, #4]
- 8002288: 681b ldr r3, [r3, #0]
- 800228a: 681a ldr r2, [r3, #0]
- 800228c: 687b ldr r3, [r7, #4]
- 800228e: 681b ldr r3, [r3, #0]
- 8002290: f042 0201 orr.w r2, r2, #1
- 8002294: 601a str r2, [r3, #0]
- }
-
- /* Return function status */
- return HAL_OK;
- 8002296: 2300 movs r3, #0
-}
- 8002298: 4618 mov r0, r3
- 800229a: 3714 adds r7, #20
- 800229c: 46bd mov sp, r7
- 800229e: f85d 7b04 ldr.w r7, [sp], #4
- 80022a2: 4770 bx lr
- 80022a4: 00010007 .word 0x00010007
-
-080022a8 <HAL_TIM_IRQHandler>:
- * @brief This function handles TIM interrupts requests.
- * @param htim TIM handle
- * @retval None
- */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- 80022a8: b580 push {r7, lr}
- 80022aa: b082 sub sp, #8
- 80022ac: af00 add r7, sp, #0
- 80022ae: 6078 str r0, [r7, #4]
- /* Capture compare 1 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
- 80022b0: 687b ldr r3, [r7, #4]
- 80022b2: 681b ldr r3, [r3, #0]
- 80022b4: 691b ldr r3, [r3, #16]
- 80022b6: f003 0302 and.w r3, r3, #2
- 80022ba: 2b02 cmp r3, #2
- 80022bc: d122 bne.n 8002304 <HAL_TIM_IRQHandler+0x5c>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
- 80022be: 687b ldr r3, [r7, #4]
- 80022c0: 681b ldr r3, [r3, #0]
- 80022c2: 68db ldr r3, [r3, #12]
- 80022c4: f003 0302 and.w r3, r3, #2
- 80022c8: 2b02 cmp r3, #2
- 80022ca: d11b bne.n 8002304 <HAL_TIM_IRQHandler+0x5c>
- {
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
- 80022cc: 687b ldr r3, [r7, #4]
- 80022ce: 681b ldr r3, [r3, #0]
- 80022d0: f06f 0202 mvn.w r2, #2
- 80022d4: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- 80022d6: 687b ldr r3, [r7, #4]
- 80022d8: 2201 movs r2, #1
- 80022da: 771a strb r2, [r3, #28]
-
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- 80022dc: 687b ldr r3, [r7, #4]
- 80022de: 681b ldr r3, [r3, #0]
- 80022e0: 699b ldr r3, [r3, #24]
- 80022e2: f003 0303 and.w r3, r3, #3
- 80022e6: 2b00 cmp r3, #0
- 80022e8: d003 beq.n 80022f2 <HAL_TIM_IRQHandler+0x4a>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 80022ea: 6878 ldr r0, [r7, #4]
- 80022ec: f000 f9c0 bl 8002670 <HAL_TIM_IC_CaptureCallback>
- 80022f0: e005 b.n 80022fe <HAL_TIM_IRQHandler+0x56>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 80022f2: 6878 ldr r0, [r7, #4]
- 80022f4: f000 f9b2 bl 800265c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80022f8: 6878 ldr r0, [r7, #4]
- 80022fa: f000 f9c3 bl 8002684 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80022fe: 687b ldr r3, [r7, #4]
- 8002300: 2200 movs r2, #0
- 8002302: 771a strb r2, [r3, #28]
- }
- }
- }
- /* Capture compare 2 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
- 8002304: 687b ldr r3, [r7, #4]
- 8002306: 681b ldr r3, [r3, #0]
- 8002308: 691b ldr r3, [r3, #16]
- 800230a: f003 0304 and.w r3, r3, #4
- 800230e: 2b04 cmp r3, #4
- 8002310: d122 bne.n 8002358 <HAL_TIM_IRQHandler+0xb0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
- 8002312: 687b ldr r3, [r7, #4]
- 8002314: 681b ldr r3, [r3, #0]
- 8002316: 68db ldr r3, [r3, #12]
- 8002318: f003 0304 and.w r3, r3, #4
- 800231c: 2b04 cmp r3, #4
- 800231e: d11b bne.n 8002358 <HAL_TIM_IRQHandler+0xb0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
- 8002320: 687b ldr r3, [r7, #4]
- 8002322: 681b ldr r3, [r3, #0]
- 8002324: f06f 0204 mvn.w r2, #4
- 8002328: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- 800232a: 687b ldr r3, [r7, #4]
- 800232c: 2202 movs r2, #2
- 800232e: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- 8002330: 687b ldr r3, [r7, #4]
- 8002332: 681b ldr r3, [r3, #0]
- 8002334: 699b ldr r3, [r3, #24]
- 8002336: f403 7340 and.w r3, r3, #768 ; 0x300
- 800233a: 2b00 cmp r3, #0
- 800233c: d003 beq.n 8002346 <HAL_TIM_IRQHandler+0x9e>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 800233e: 6878 ldr r0, [r7, #4]
- 8002340: f000 f996 bl 8002670 <HAL_TIM_IC_CaptureCallback>
- 8002344: e005 b.n 8002352 <HAL_TIM_IRQHandler+0xaa>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 8002346: 6878 ldr r0, [r7, #4]
- 8002348: f000 f988 bl 800265c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 800234c: 6878 ldr r0, [r7, #4]
- 800234e: f000 f999 bl 8002684 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8002352: 687b ldr r3, [r7, #4]
- 8002354: 2200 movs r2, #0
- 8002356: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 3 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- 8002358: 687b ldr r3, [r7, #4]
- 800235a: 681b ldr r3, [r3, #0]
- 800235c: 691b ldr r3, [r3, #16]
- 800235e: f003 0308 and.w r3, r3, #8
- 8002362: 2b08 cmp r3, #8
- 8002364: d122 bne.n 80023ac <HAL_TIM_IRQHandler+0x104>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
- 8002366: 687b ldr r3, [r7, #4]
- 8002368: 681b ldr r3, [r3, #0]
- 800236a: 68db ldr r3, [r3, #12]
- 800236c: f003 0308 and.w r3, r3, #8
- 8002370: 2b08 cmp r3, #8
- 8002372: d11b bne.n 80023ac <HAL_TIM_IRQHandler+0x104>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- 8002374: 687b ldr r3, [r7, #4]
- 8002376: 681b ldr r3, [r3, #0]
- 8002378: f06f 0208 mvn.w r2, #8
- 800237c: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- 800237e: 687b ldr r3, [r7, #4]
- 8002380: 2204 movs r2, #4
- 8002382: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- 8002384: 687b ldr r3, [r7, #4]
- 8002386: 681b ldr r3, [r3, #0]
- 8002388: 69db ldr r3, [r3, #28]
- 800238a: f003 0303 and.w r3, r3, #3
- 800238e: 2b00 cmp r3, #0
- 8002390: d003 beq.n 800239a <HAL_TIM_IRQHandler+0xf2>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 8002392: 6878 ldr r0, [r7, #4]
- 8002394: f000 f96c bl 8002670 <HAL_TIM_IC_CaptureCallback>
- 8002398: e005 b.n 80023a6 <HAL_TIM_IRQHandler+0xfe>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 800239a: 6878 ldr r0, [r7, #4]
- 800239c: f000 f95e bl 800265c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80023a0: 6878 ldr r0, [r7, #4]
- 80023a2: f000 f96f bl 8002684 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80023a6: 687b ldr r3, [r7, #4]
- 80023a8: 2200 movs r2, #0
- 80023aa: 771a strb r2, [r3, #28]
- }
- }
- /* Capture compare 4 event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
- 80023ac: 687b ldr r3, [r7, #4]
- 80023ae: 681b ldr r3, [r3, #0]
- 80023b0: 691b ldr r3, [r3, #16]
- 80023b2: f003 0310 and.w r3, r3, #16
- 80023b6: 2b10 cmp r3, #16
- 80023b8: d122 bne.n 8002400 <HAL_TIM_IRQHandler+0x158>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
- 80023ba: 687b ldr r3, [r7, #4]
- 80023bc: 681b ldr r3, [r3, #0]
- 80023be: 68db ldr r3, [r3, #12]
- 80023c0: f003 0310 and.w r3, r3, #16
- 80023c4: 2b10 cmp r3, #16
- 80023c6: d11b bne.n 8002400 <HAL_TIM_IRQHandler+0x158>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
- 80023c8: 687b ldr r3, [r7, #4]
- 80023ca: 681b ldr r3, [r3, #0]
- 80023cc: f06f 0210 mvn.w r2, #16
- 80023d0: 611a str r2, [r3, #16]
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- 80023d2: 687b ldr r3, [r7, #4]
- 80023d4: 2208 movs r2, #8
- 80023d6: 771a strb r2, [r3, #28]
- /* Input capture event */
- if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- 80023d8: 687b ldr r3, [r7, #4]
- 80023da: 681b ldr r3, [r3, #0]
- 80023dc: 69db ldr r3, [r3, #28]
- 80023de: f403 7340 and.w r3, r3, #768 ; 0x300
- 80023e2: 2b00 cmp r3, #0
- 80023e4: d003 beq.n 80023ee <HAL_TIM_IRQHandler+0x146>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->IC_CaptureCallback(htim);
-#else
- HAL_TIM_IC_CaptureCallback(htim);
- 80023e6: 6878 ldr r0, [r7, #4]
- 80023e8: f000 f942 bl 8002670 <HAL_TIM_IC_CaptureCallback>
- 80023ec: e005 b.n 80023fa <HAL_TIM_IRQHandler+0x152>
- {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->OC_DelayElapsedCallback(htim);
- htim->PWM_PulseFinishedCallback(htim);
-#else
- HAL_TIM_OC_DelayElapsedCallback(htim);
- 80023ee: 6878 ldr r0, [r7, #4]
- 80023f0: f000 f934 bl 800265c <HAL_TIM_OC_DelayElapsedCallback>
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- 80023f4: 6878 ldr r0, [r7, #4]
- 80023f6: f000 f945 bl 8002684 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 80023fa: 687b ldr r3, [r7, #4]
- 80023fc: 2200 movs r2, #0
- 80023fe: 771a strb r2, [r3, #28]
- }
- }
- /* TIM Update event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
- 8002400: 687b ldr r3, [r7, #4]
- 8002402: 681b ldr r3, [r3, #0]
- 8002404: 691b ldr r3, [r3, #16]
- 8002406: f003 0301 and.w r3, r3, #1
- 800240a: 2b01 cmp r3, #1
- 800240c: d10e bne.n 800242c <HAL_TIM_IRQHandler+0x184>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
- 800240e: 687b ldr r3, [r7, #4]
- 8002410: 681b ldr r3, [r3, #0]
- 8002412: 68db ldr r3, [r3, #12]
- 8002414: f003 0301 and.w r3, r3, #1
- 8002418: 2b01 cmp r3, #1
- 800241a: d107 bne.n 800242c <HAL_TIM_IRQHandler+0x184>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
- 800241c: 687b ldr r3, [r7, #4]
- 800241e: 681b ldr r3, [r3, #0]
- 8002420: f06f 0201 mvn.w r2, #1
- 8002424: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->PeriodElapsedCallback(htim);
-#else
- HAL_TIM_PeriodElapsedCallback(htim);
- 8002426: 6878 ldr r0, [r7, #4]
- 8002428: f7fe f9d0 bl 80007cc <HAL_TIM_PeriodElapsedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
- 800242c: 687b ldr r3, [r7, #4]
- 800242e: 681b ldr r3, [r3, #0]
- 8002430: 691b ldr r3, [r3, #16]
- 8002432: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002436: 2b80 cmp r3, #128 ; 0x80
- 8002438: d10e bne.n 8002458 <HAL_TIM_IRQHandler+0x1b0>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 800243a: 687b ldr r3, [r7, #4]
- 800243c: 681b ldr r3, [r3, #0]
- 800243e: 68db ldr r3, [r3, #12]
- 8002440: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002444: 2b80 cmp r3, #128 ; 0x80
- 8002446: d107 bne.n 8002458 <HAL_TIM_IRQHandler+0x1b0>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
- 8002448: 687b ldr r3, [r7, #4]
- 800244a: 681b ldr r3, [r3, #0]
- 800244c: f06f 0280 mvn.w r2, #128 ; 0x80
- 8002450: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->BreakCallback(htim);
-#else
- HAL_TIMEx_BreakCallback(htim);
- 8002452: 6878 ldr r0, [r7, #4]
- 8002454: f000 faca bl 80029ec <HAL_TIMEx_BreakCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Break2 input event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
- 8002458: 687b ldr r3, [r7, #4]
- 800245a: 681b ldr r3, [r3, #0]
- 800245c: 691b ldr r3, [r3, #16]
- 800245e: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002462: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8002466: d10e bne.n 8002486 <HAL_TIM_IRQHandler+0x1de>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
- 8002468: 687b ldr r3, [r7, #4]
- 800246a: 681b ldr r3, [r3, #0]
- 800246c: 68db ldr r3, [r3, #12]
- 800246e: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002472: 2b80 cmp r3, #128 ; 0x80
- 8002474: d107 bne.n 8002486 <HAL_TIM_IRQHandler+0x1de>
- {
- __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- 8002476: 687b ldr r3, [r7, #4]
- 8002478: 681b ldr r3, [r3, #0]
- 800247a: f46f 7280 mvn.w r2, #256 ; 0x100
- 800247e: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->Break2Callback(htim);
-#else
- HAL_TIMEx_Break2Callback(htim);
- 8002480: 6878 ldr r0, [r7, #4]
- 8002482: f000 fabd bl 8002a00 <HAL_TIMEx_Break2Callback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM Trigger detection event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
- 8002486: 687b ldr r3, [r7, #4]
- 8002488: 681b ldr r3, [r3, #0]
- 800248a: 691b ldr r3, [r3, #16]
- 800248c: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002490: 2b40 cmp r3, #64 ; 0x40
- 8002492: d10e bne.n 80024b2 <HAL_TIM_IRQHandler+0x20a>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
- 8002494: 687b ldr r3, [r7, #4]
- 8002496: 681b ldr r3, [r3, #0]
- 8002498: 68db ldr r3, [r3, #12]
- 800249a: f003 0340 and.w r3, r3, #64 ; 0x40
- 800249e: 2b40 cmp r3, #64 ; 0x40
- 80024a0: d107 bne.n 80024b2 <HAL_TIM_IRQHandler+0x20a>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
- 80024a2: 687b ldr r3, [r7, #4]
- 80024a4: 681b ldr r3, [r3, #0]
- 80024a6: f06f 0240 mvn.w r2, #64 ; 0x40
- 80024aa: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->TriggerCallback(htim);
-#else
- HAL_TIM_TriggerCallback(htim);
- 80024ac: 6878 ldr r0, [r7, #4]
- 80024ae: f000 f8f3 bl 8002698 <HAL_TIM_TriggerCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
- /* TIM commutation event */
- if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
- 80024b2: 687b ldr r3, [r7, #4]
- 80024b4: 681b ldr r3, [r3, #0]
- 80024b6: 691b ldr r3, [r3, #16]
- 80024b8: f003 0320 and.w r3, r3, #32
- 80024bc: 2b20 cmp r3, #32
- 80024be: d10e bne.n 80024de <HAL_TIM_IRQHandler+0x236>
- {
- if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
- 80024c0: 687b ldr r3, [r7, #4]
- 80024c2: 681b ldr r3, [r3, #0]
- 80024c4: 68db ldr r3, [r3, #12]
- 80024c6: f003 0320 and.w r3, r3, #32
- 80024ca: 2b20 cmp r3, #32
- 80024cc: d107 bne.n 80024de <HAL_TIM_IRQHandler+0x236>
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- 80024ce: 687b ldr r3, [r7, #4]
- 80024d0: 681b ldr r3, [r3, #0]
- 80024d2: f06f 0220 mvn.w r2, #32
- 80024d6: 611a str r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- htim->CommutationCallback(htim);
-#else
- HAL_TIMEx_CommutCallback(htim);
- 80024d8: 6878 ldr r0, [r7, #4]
- 80024da: f000 fa7d bl 80029d8 <HAL_TIMEx_CommutCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
- }
- }
-}
- 80024de: bf00 nop
- 80024e0: 3708 adds r7, #8
- 80024e2: 46bd mov sp, r7
- 80024e4: bd80 pop {r7, pc}
- ...
-
-080024e8 <HAL_TIM_ConfigClockSource>:
- * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- 80024e8: b580 push {r7, lr}
- 80024ea: b084 sub sp, #16
- 80024ec: af00 add r7, sp, #0
- 80024ee: 6078 str r0, [r7, #4]
- 80024f0: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Process Locked */
- __HAL_LOCK(htim);
- 80024f2: 687b ldr r3, [r7, #4]
- 80024f4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 80024f8: 2b01 cmp r3, #1
- 80024fa: d101 bne.n 8002500 <HAL_TIM_ConfigClockSource+0x18>
- 80024fc: 2302 movs r3, #2
- 80024fe: e0a6 b.n 800264e <HAL_TIM_ConfigClockSource+0x166>
- 8002500: 687b ldr r3, [r7, #4]
- 8002502: 2201 movs r2, #1
- 8002504: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- htim->State = HAL_TIM_STATE_BUSY;
- 8002508: 687b ldr r3, [r7, #4]
- 800250a: 2202 movs r2, #2
- 800250c: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Check the parameters */
- assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
- /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
- tmpsmcr = htim->Instance->SMCR;
- 8002510: 687b ldr r3, [r7, #4]
- 8002512: 681b ldr r3, [r3, #0]
- 8002514: 689b ldr r3, [r3, #8]
- 8002516: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 8002518: 68fa ldr r2, [r7, #12]
- 800251a: 4b4f ldr r3, [pc, #316] ; (8002658 <HAL_TIM_ConfigClockSource+0x170>)
- 800251c: 4013 ands r3, r2
- 800251e: 60fb str r3, [r7, #12]
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8002520: 68fb ldr r3, [r7, #12]
- 8002522: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 8002526: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8002528: 687b ldr r3, [r7, #4]
- 800252a: 681b ldr r3, [r3, #0]
- 800252c: 68fa ldr r2, [r7, #12]
- 800252e: 609a str r2, [r3, #8]
-
- switch (sClockSourceConfig->ClockSource)
- 8002530: 683b ldr r3, [r7, #0]
- 8002532: 681b ldr r3, [r3, #0]
- 8002534: 2b40 cmp r3, #64 ; 0x40
- 8002536: d067 beq.n 8002608 <HAL_TIM_ConfigClockSource+0x120>
- 8002538: 2b40 cmp r3, #64 ; 0x40
- 800253a: d80b bhi.n 8002554 <HAL_TIM_ConfigClockSource+0x6c>
- 800253c: 2b10 cmp r3, #16
- 800253e: d073 beq.n 8002628 <HAL_TIM_ConfigClockSource+0x140>
- 8002540: 2b10 cmp r3, #16
- 8002542: d802 bhi.n 800254a <HAL_TIM_ConfigClockSource+0x62>
- 8002544: 2b00 cmp r3, #0
- 8002546: d06f beq.n 8002628 <HAL_TIM_ConfigClockSource+0x140>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
-
- default:
- break;
- 8002548: e078 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 800254a: 2b20 cmp r3, #32
- 800254c: d06c beq.n 8002628 <HAL_TIM_ConfigClockSource+0x140>
- 800254e: 2b30 cmp r3, #48 ; 0x30
- 8002550: d06a beq.n 8002628 <HAL_TIM_ConfigClockSource+0x140>
- break;
- 8002552: e073 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8002554: 2b70 cmp r3, #112 ; 0x70
- 8002556: d00d beq.n 8002574 <HAL_TIM_ConfigClockSource+0x8c>
- 8002558: 2b70 cmp r3, #112 ; 0x70
- 800255a: d804 bhi.n 8002566 <HAL_TIM_ConfigClockSource+0x7e>
- 800255c: 2b50 cmp r3, #80 ; 0x50
- 800255e: d033 beq.n 80025c8 <HAL_TIM_ConfigClockSource+0xe0>
- 8002560: 2b60 cmp r3, #96 ; 0x60
- 8002562: d041 beq.n 80025e8 <HAL_TIM_ConfigClockSource+0x100>
- break;
- 8002564: e06a b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- switch (sClockSourceConfig->ClockSource)
- 8002566: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 800256a: d066 beq.n 800263a <HAL_TIM_ConfigClockSource+0x152>
- 800256c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8002570: d017 beq.n 80025a2 <HAL_TIM_ConfigClockSource+0xba>
- break;
- 8002572: e063 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 8002574: 687b ldr r3, [r7, #4]
- 8002576: 6818 ldr r0, [r3, #0]
- 8002578: 683b ldr r3, [r7, #0]
- 800257a: 6899 ldr r1, [r3, #8]
- 800257c: 683b ldr r3, [r7, #0]
- 800257e: 685a ldr r2, [r3, #4]
- 8002580: 683b ldr r3, [r7, #0]
- 8002582: 68db ldr r3, [r3, #12]
- 8002584: f000 f9ac bl 80028e0 <TIM_ETR_SetConfig>
- tmpsmcr = htim->Instance->SMCR;
- 8002588: 687b ldr r3, [r7, #4]
- 800258a: 681b ldr r3, [r3, #0]
- 800258c: 689b ldr r3, [r3, #8]
- 800258e: 60fb str r3, [r7, #12]
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8002590: 68fb ldr r3, [r7, #12]
- 8002592: f043 0377 orr.w r3, r3, #119 ; 0x77
- 8002596: 60fb str r3, [r7, #12]
- htim->Instance->SMCR = tmpsmcr;
- 8002598: 687b ldr r3, [r7, #4]
- 800259a: 681b ldr r3, [r3, #0]
- 800259c: 68fa ldr r2, [r7, #12]
- 800259e: 609a str r2, [r3, #8]
- break;
- 80025a0: e04c b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- TIM_ETR_SetConfig(htim->Instance,
- 80025a2: 687b ldr r3, [r7, #4]
- 80025a4: 6818 ldr r0, [r3, #0]
- 80025a6: 683b ldr r3, [r7, #0]
- 80025a8: 6899 ldr r1, [r3, #8]
- 80025aa: 683b ldr r3, [r7, #0]
- 80025ac: 685a ldr r2, [r3, #4]
- 80025ae: 683b ldr r3, [r7, #0]
- 80025b0: 68db ldr r3, [r3, #12]
- 80025b2: f000 f995 bl 80028e0 <TIM_ETR_SetConfig>
- htim->Instance->SMCR |= TIM_SMCR_ECE;
- 80025b6: 687b ldr r3, [r7, #4]
- 80025b8: 681b ldr r3, [r3, #0]
- 80025ba: 689a ldr r2, [r3, #8]
- 80025bc: 687b ldr r3, [r7, #4]
- 80025be: 681b ldr r3, [r3, #0]
- 80025c0: f442 4280 orr.w r2, r2, #16384 ; 0x4000
- 80025c4: 609a str r2, [r3, #8]
- break;
- 80025c6: e039 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 80025c8: 687b ldr r3, [r7, #4]
- 80025ca: 6818 ldr r0, [r3, #0]
- 80025cc: 683b ldr r3, [r7, #0]
- 80025ce: 6859 ldr r1, [r3, #4]
- 80025d0: 683b ldr r3, [r7, #0]
- 80025d2: 68db ldr r3, [r3, #12]
- 80025d4: 461a mov r2, r3
- 80025d6: f000 f909 bl 80027ec <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 80025da: 687b ldr r3, [r7, #4]
- 80025dc: 681b ldr r3, [r3, #0]
- 80025de: 2150 movs r1, #80 ; 0x50
- 80025e0: 4618 mov r0, r3
- 80025e2: f000 f962 bl 80028aa <TIM_ITRx_SetConfig>
- break;
- 80025e6: e029 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI2_ConfigInputStage(htim->Instance,
- 80025e8: 687b ldr r3, [r7, #4]
- 80025ea: 6818 ldr r0, [r3, #0]
- 80025ec: 683b ldr r3, [r7, #0]
- 80025ee: 6859 ldr r1, [r3, #4]
- 80025f0: 683b ldr r3, [r7, #0]
- 80025f2: 68db ldr r3, [r3, #12]
- 80025f4: 461a mov r2, r3
- 80025f6: f000 f928 bl 800284a <TIM_TI2_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 80025fa: 687b ldr r3, [r7, #4]
- 80025fc: 681b ldr r3, [r3, #0]
- 80025fe: 2160 movs r1, #96 ; 0x60
- 8002600: 4618 mov r0, r3
- 8002602: f000 f952 bl 80028aa <TIM_ITRx_SetConfig>
- break;
- 8002606: e019 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- TIM_TI1_ConfigInputStage(htim->Instance,
- 8002608: 687b ldr r3, [r7, #4]
- 800260a: 6818 ldr r0, [r3, #0]
- 800260c: 683b ldr r3, [r7, #0]
- 800260e: 6859 ldr r1, [r3, #4]
- 8002610: 683b ldr r3, [r7, #0]
- 8002612: 68db ldr r3, [r3, #12]
- 8002614: 461a mov r2, r3
- 8002616: f000 f8e9 bl 80027ec <TIM_TI1_ConfigInputStage>
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 800261a: 687b ldr r3, [r7, #4]
- 800261c: 681b ldr r3, [r3, #0]
- 800261e: 2140 movs r1, #64 ; 0x40
- 8002620: 4618 mov r0, r3
- 8002622: f000 f942 bl 80028aa <TIM_ITRx_SetConfig>
- break;
- 8002626: e009 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 8002628: 687b ldr r3, [r7, #4]
- 800262a: 681a ldr r2, [r3, #0]
- 800262c: 683b ldr r3, [r7, #0]
- 800262e: 681b ldr r3, [r3, #0]
- 8002630: 4619 mov r1, r3
- 8002632: 4610 mov r0, r2
- 8002634: f000 f939 bl 80028aa <TIM_ITRx_SetConfig>
- break;
- 8002638: e000 b.n 800263c <HAL_TIM_ConfigClockSource+0x154>
- break;
- 800263a: bf00 nop
- }
- htim->State = HAL_TIM_STATE_READY;
- 800263c: 687b ldr r3, [r7, #4]
- 800263e: 2201 movs r2, #1
- 8002640: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 8002644: 687b ldr r3, [r7, #4]
- 8002646: 2200 movs r2, #0
- 8002648: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 800264c: 2300 movs r3, #0
-}
- 800264e: 4618 mov r0, r3
- 8002650: 3710 adds r7, #16
- 8002652: 46bd mov sp, r7
- 8002654: bd80 pop {r7, pc}
- 8002656: bf00 nop
- 8002658: fffeff88 .word 0xfffeff88
-
-0800265c <HAL_TIM_OC_DelayElapsedCallback>:
- * @brief Output Compare callback in non-blocking mode
- * @param htim TIM OC handle
- * @retval None
- */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- 800265c: b480 push {r7}
- 800265e: b083 sub sp, #12
- 8002660: af00 add r7, sp, #0
- 8002662: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
- */
-}
- 8002664: bf00 nop
- 8002666: 370c adds r7, #12
- 8002668: 46bd mov sp, r7
- 800266a: f85d 7b04 ldr.w r7, [sp], #4
- 800266e: 4770 bx lr
-
-08002670 <HAL_TIM_IC_CaptureCallback>:
- * @brief Input Capture callback in non-blocking mode
- * @param htim TIM IC handle
- * @retval None
- */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- 8002670: b480 push {r7}
- 8002672: b083 sub sp, #12
- 8002674: af00 add r7, sp, #0
- 8002676: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_IC_CaptureCallback could be implemented in the user file
- */
-}
- 8002678: bf00 nop
- 800267a: 370c adds r7, #12
- 800267c: 46bd mov sp, r7
- 800267e: f85d 7b04 ldr.w r7, [sp], #4
- 8002682: 4770 bx lr
-
-08002684 <HAL_TIM_PWM_PulseFinishedCallback>:
- * @brief PWM Pulse finished callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- 8002684: b480 push {r7}
- 8002686: b083 sub sp, #12
- 8002688: af00 add r7, sp, #0
- 800268a: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
- */
-}
- 800268c: bf00 nop
- 800268e: 370c adds r7, #12
- 8002690: 46bd mov sp, r7
- 8002692: f85d 7b04 ldr.w r7, [sp], #4
- 8002696: 4770 bx lr
-
-08002698 <HAL_TIM_TriggerCallback>:
- * @brief Hall Trigger detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- 8002698: b480 push {r7}
- 800269a: b083 sub sp, #12
- 800269c: af00 add r7, sp, #0
- 800269e: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
- */
-}
- 80026a0: bf00 nop
- 80026a2: 370c adds r7, #12
- 80026a4: 46bd mov sp, r7
- 80026a6: f85d 7b04 ldr.w r7, [sp], #4
- 80026aa: 4770 bx lr
-
-080026ac <TIM_Base_SetConfig>:
- * @param TIMx TIM peripheral
- * @param Structure TIM Base configuration structure
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
- 80026ac: b480 push {r7}
- 80026ae: b085 sub sp, #20
- 80026b0: af00 add r7, sp, #0
- 80026b2: 6078 str r0, [r7, #4]
- 80026b4: 6039 str r1, [r7, #0]
- uint32_t tmpcr1;
- tmpcr1 = TIMx->CR1;
- 80026b6: 687b ldr r3, [r7, #4]
- 80026b8: 681b ldr r3, [r3, #0]
- 80026ba: 60fb str r3, [r7, #12]
-
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 80026bc: 687b ldr r3, [r7, #4]
- 80026be: 4a40 ldr r2, [pc, #256] ; (80027c0 <TIM_Base_SetConfig+0x114>)
- 80026c0: 4293 cmp r3, r2
- 80026c2: d013 beq.n 80026ec <TIM_Base_SetConfig+0x40>
- 80026c4: 687b ldr r3, [r7, #4]
- 80026c6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 80026ca: d00f beq.n 80026ec <TIM_Base_SetConfig+0x40>
- 80026cc: 687b ldr r3, [r7, #4]
- 80026ce: 4a3d ldr r2, [pc, #244] ; (80027c4 <TIM_Base_SetConfig+0x118>)
- 80026d0: 4293 cmp r3, r2
- 80026d2: d00b beq.n 80026ec <TIM_Base_SetConfig+0x40>
- 80026d4: 687b ldr r3, [r7, #4]
- 80026d6: 4a3c ldr r2, [pc, #240] ; (80027c8 <TIM_Base_SetConfig+0x11c>)
- 80026d8: 4293 cmp r3, r2
- 80026da: d007 beq.n 80026ec <TIM_Base_SetConfig+0x40>
- 80026dc: 687b ldr r3, [r7, #4]
- 80026de: 4a3b ldr r2, [pc, #236] ; (80027cc <TIM_Base_SetConfig+0x120>)
- 80026e0: 4293 cmp r3, r2
- 80026e2: d003 beq.n 80026ec <TIM_Base_SetConfig+0x40>
- 80026e4: 687b ldr r3, [r7, #4]
- 80026e6: 4a3a ldr r2, [pc, #232] ; (80027d0 <TIM_Base_SetConfig+0x124>)
- 80026e8: 4293 cmp r3, r2
- 80026ea: d108 bne.n 80026fe <TIM_Base_SetConfig+0x52>
- {
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 80026ec: 68fb ldr r3, [r7, #12]
- 80026ee: f023 0370 bic.w r3, r3, #112 ; 0x70
- 80026f2: 60fb str r3, [r7, #12]
- tmpcr1 |= Structure->CounterMode;
- 80026f4: 683b ldr r3, [r7, #0]
- 80026f6: 685b ldr r3, [r3, #4]
- 80026f8: 68fa ldr r2, [r7, #12]
- 80026fa: 4313 orrs r3, r2
- 80026fc: 60fb str r3, [r7, #12]
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 80026fe: 687b ldr r3, [r7, #4]
- 8002700: 4a2f ldr r2, [pc, #188] ; (80027c0 <TIM_Base_SetConfig+0x114>)
- 8002702: 4293 cmp r3, r2
- 8002704: d02b beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 8002706: 687b ldr r3, [r7, #4]
- 8002708: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 800270c: d027 beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 800270e: 687b ldr r3, [r7, #4]
- 8002710: 4a2c ldr r2, [pc, #176] ; (80027c4 <TIM_Base_SetConfig+0x118>)
- 8002712: 4293 cmp r3, r2
- 8002714: d023 beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 8002716: 687b ldr r3, [r7, #4]
- 8002718: 4a2b ldr r2, [pc, #172] ; (80027c8 <TIM_Base_SetConfig+0x11c>)
- 800271a: 4293 cmp r3, r2
- 800271c: d01f beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 800271e: 687b ldr r3, [r7, #4]
- 8002720: 4a2a ldr r2, [pc, #168] ; (80027cc <TIM_Base_SetConfig+0x120>)
- 8002722: 4293 cmp r3, r2
- 8002724: d01b beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 8002726: 687b ldr r3, [r7, #4]
- 8002728: 4a29 ldr r2, [pc, #164] ; (80027d0 <TIM_Base_SetConfig+0x124>)
- 800272a: 4293 cmp r3, r2
- 800272c: d017 beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 800272e: 687b ldr r3, [r7, #4]
- 8002730: 4a28 ldr r2, [pc, #160] ; (80027d4 <TIM_Base_SetConfig+0x128>)
- 8002732: 4293 cmp r3, r2
- 8002734: d013 beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 8002736: 687b ldr r3, [r7, #4]
- 8002738: 4a27 ldr r2, [pc, #156] ; (80027d8 <TIM_Base_SetConfig+0x12c>)
- 800273a: 4293 cmp r3, r2
- 800273c: d00f beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 800273e: 687b ldr r3, [r7, #4]
- 8002740: 4a26 ldr r2, [pc, #152] ; (80027dc <TIM_Base_SetConfig+0x130>)
- 8002742: 4293 cmp r3, r2
- 8002744: d00b beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 8002746: 687b ldr r3, [r7, #4]
- 8002748: 4a25 ldr r2, [pc, #148] ; (80027e0 <TIM_Base_SetConfig+0x134>)
- 800274a: 4293 cmp r3, r2
- 800274c: d007 beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 800274e: 687b ldr r3, [r7, #4]
- 8002750: 4a24 ldr r2, [pc, #144] ; (80027e4 <TIM_Base_SetConfig+0x138>)
- 8002752: 4293 cmp r3, r2
- 8002754: d003 beq.n 800275e <TIM_Base_SetConfig+0xb2>
- 8002756: 687b ldr r3, [r7, #4]
- 8002758: 4a23 ldr r2, [pc, #140] ; (80027e8 <TIM_Base_SetConfig+0x13c>)
- 800275a: 4293 cmp r3, r2
- 800275c: d108 bne.n 8002770 <TIM_Base_SetConfig+0xc4>
- {
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- 800275e: 68fb ldr r3, [r7, #12]
- 8002760: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8002764: 60fb str r3, [r7, #12]
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 8002766: 683b ldr r3, [r7, #0]
- 8002768: 68db ldr r3, [r3, #12]
- 800276a: 68fa ldr r2, [r7, #12]
- 800276c: 4313 orrs r3, r2
- 800276e: 60fb str r3, [r7, #12]
- }
-
- /* Set the auto-reload preload */
- MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8002770: 68fb ldr r3, [r7, #12]
- 8002772: f023 0280 bic.w r2, r3, #128 ; 0x80
- 8002776: 683b ldr r3, [r7, #0]
- 8002778: 695b ldr r3, [r3, #20]
- 800277a: 4313 orrs r3, r2
- 800277c: 60fb str r3, [r7, #12]
-
- TIMx->CR1 = tmpcr1;
- 800277e: 687b ldr r3, [r7, #4]
- 8002780: 68fa ldr r2, [r7, #12]
- 8002782: 601a str r2, [r3, #0]
-
- /* Set the Autoreload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
- 8002784: 683b ldr r3, [r7, #0]
- 8002786: 689a ldr r2, [r3, #8]
- 8002788: 687b ldr r3, [r7, #4]
- 800278a: 62da str r2, [r3, #44] ; 0x2c
-
- /* Set the Prescaler value */
- TIMx->PSC = Structure->Prescaler;
- 800278c: 683b ldr r3, [r7, #0]
- 800278e: 681a ldr r2, [r3, #0]
- 8002790: 687b ldr r3, [r7, #4]
- 8002792: 629a str r2, [r3, #40] ; 0x28
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8002794: 687b ldr r3, [r7, #4]
- 8002796: 4a0a ldr r2, [pc, #40] ; (80027c0 <TIM_Base_SetConfig+0x114>)
- 8002798: 4293 cmp r3, r2
- 800279a: d003 beq.n 80027a4 <TIM_Base_SetConfig+0xf8>
- 800279c: 687b ldr r3, [r7, #4]
- 800279e: 4a0c ldr r2, [pc, #48] ; (80027d0 <TIM_Base_SetConfig+0x124>)
- 80027a0: 4293 cmp r3, r2
- 80027a2: d103 bne.n 80027ac <TIM_Base_SetConfig+0x100>
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
- 80027a4: 683b ldr r3, [r7, #0]
- 80027a6: 691a ldr r2, [r3, #16]
- 80027a8: 687b ldr r3, [r7, #4]
- 80027aa: 631a str r2, [r3, #48] ; 0x30
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter (only for advanced timer) value immediately */
- TIMx->EGR = TIM_EGR_UG;
- 80027ac: 687b ldr r3, [r7, #4]
- 80027ae: 2201 movs r2, #1
- 80027b0: 615a str r2, [r3, #20]
-}
- 80027b2: bf00 nop
- 80027b4: 3714 adds r7, #20
- 80027b6: 46bd mov sp, r7
- 80027b8: f85d 7b04 ldr.w r7, [sp], #4
- 80027bc: 4770 bx lr
- 80027be: bf00 nop
- 80027c0: 40010000 .word 0x40010000
- 80027c4: 40000400 .word 0x40000400
- 80027c8: 40000800 .word 0x40000800
- 80027cc: 40000c00 .word 0x40000c00
- 80027d0: 40010400 .word 0x40010400
- 80027d4: 40014000 .word 0x40014000
- 80027d8: 40014400 .word 0x40014400
- 80027dc: 40014800 .word 0x40014800
- 80027e0: 40001800 .word 0x40001800
- 80027e4: 40001c00 .word 0x40001c00
- 80027e8: 40002000 .word 0x40002000
-
-080027ec <TIM_TI1_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 80027ec: b480 push {r7}
- 80027ee: b087 sub sp, #28
- 80027f0: af00 add r7, sp, #0
- 80027f2: 60f8 str r0, [r7, #12]
- 80027f4: 60b9 str r1, [r7, #8]
- 80027f6: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- tmpccer = TIMx->CCER;
- 80027f8: 68fb ldr r3, [r7, #12]
- 80027fa: 6a1b ldr r3, [r3, #32]
- 80027fc: 617b str r3, [r7, #20]
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 80027fe: 68fb ldr r3, [r7, #12]
- 8002800: 6a1b ldr r3, [r3, #32]
- 8002802: f023 0201 bic.w r2, r3, #1
- 8002806: 68fb ldr r3, [r7, #12]
- 8002808: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 800280a: 68fb ldr r3, [r7, #12]
- 800280c: 699b ldr r3, [r3, #24]
- 800280e: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 8002810: 693b ldr r3, [r7, #16]
- 8002812: f023 03f0 bic.w r3, r3, #240 ; 0xf0
- 8002816: 613b str r3, [r7, #16]
- tmpccmr1 |= (TIM_ICFilter << 4U);
- 8002818: 687b ldr r3, [r7, #4]
- 800281a: 011b lsls r3, r3, #4
- 800281c: 693a ldr r2, [r7, #16]
- 800281e: 4313 orrs r3, r2
- 8002820: 613b str r3, [r7, #16]
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 8002822: 697b ldr r3, [r7, #20]
- 8002824: f023 030a bic.w r3, r3, #10
- 8002828: 617b str r3, [r7, #20]
- tmpccer |= TIM_ICPolarity;
- 800282a: 697a ldr r2, [r7, #20]
- 800282c: 68bb ldr r3, [r7, #8]
- 800282e: 4313 orrs r3, r2
- 8002830: 617b str r3, [r7, #20]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- 8002832: 68fb ldr r3, [r7, #12]
- 8002834: 693a ldr r2, [r7, #16]
- 8002836: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 8002838: 68fb ldr r3, [r7, #12]
- 800283a: 697a ldr r2, [r7, #20]
- 800283c: 621a str r2, [r3, #32]
-}
- 800283e: bf00 nop
- 8002840: 371c adds r7, #28
- 8002842: 46bd mov sp, r7
- 8002844: f85d 7b04 ldr.w r7, [sp], #4
- 8002848: 4770 bx lr
-
-0800284a <TIM_TI2_ConfigInputStage>:
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 800284a: b480 push {r7}
- 800284c: b087 sub sp, #28
- 800284e: af00 add r7, sp, #0
- 8002850: 60f8 str r0, [r7, #12]
- 8002852: 60b9 str r1, [r7, #8]
- 8002854: 607a str r2, [r7, #4]
- uint32_t tmpccmr1;
- uint32_t tmpccer;
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
- 8002856: 68fb ldr r3, [r7, #12]
- 8002858: 6a1b ldr r3, [r3, #32]
- 800285a: f023 0210 bic.w r2, r3, #16
- 800285e: 68fb ldr r3, [r7, #12]
- 8002860: 621a str r2, [r3, #32]
- tmpccmr1 = TIMx->CCMR1;
- 8002862: 68fb ldr r3, [r7, #12]
- 8002864: 699b ldr r3, [r3, #24]
- 8002866: 617b str r3, [r7, #20]
- tmpccer = TIMx->CCER;
- 8002868: 68fb ldr r3, [r7, #12]
- 800286a: 6a1b ldr r3, [r3, #32]
- 800286c: 613b str r3, [r7, #16]
-
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 800286e: 697b ldr r3, [r7, #20]
- 8002870: f423 4370 bic.w r3, r3, #61440 ; 0xf000
- 8002874: 617b str r3, [r7, #20]
- tmpccmr1 |= (TIM_ICFilter << 12U);
- 8002876: 687b ldr r3, [r7, #4]
- 8002878: 031b lsls r3, r3, #12
- 800287a: 697a ldr r2, [r7, #20]
- 800287c: 4313 orrs r3, r2
- 800287e: 617b str r3, [r7, #20]
-
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 8002880: 693b ldr r3, [r7, #16]
- 8002882: f023 03a0 bic.w r3, r3, #160 ; 0xa0
- 8002886: 613b str r3, [r7, #16]
- tmpccer |= (TIM_ICPolarity << 4U);
- 8002888: 68bb ldr r3, [r7, #8]
- 800288a: 011b lsls r3, r3, #4
- 800288c: 693a ldr r2, [r7, #16]
- 800288e: 4313 orrs r3, r2
- 8002890: 613b str r3, [r7, #16]
-
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- 8002892: 68fb ldr r3, [r7, #12]
- 8002894: 697a ldr r2, [r7, #20]
- 8002896: 619a str r2, [r3, #24]
- TIMx->CCER = tmpccer;
- 8002898: 68fb ldr r3, [r7, #12]
- 800289a: 693a ldr r2, [r7, #16]
- 800289c: 621a str r2, [r3, #32]
-}
- 800289e: bf00 nop
- 80028a0: 371c adds r7, #28
- 80028a2: 46bd mov sp, r7
- 80028a4: f85d 7b04 ldr.w r7, [sp], #4
- 80028a8: 4770 bx lr
-
-080028aa <TIM_ITRx_SetConfig>:
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
-{
- 80028aa: b480 push {r7}
- 80028ac: b085 sub sp, #20
- 80028ae: af00 add r7, sp, #0
- 80028b0: 6078 str r0, [r7, #4]
- 80028b2: 6039 str r1, [r7, #0]
- uint32_t tmpsmcr;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- 80028b4: 687b ldr r3, [r7, #4]
- 80028b6: 689b ldr r3, [r3, #8]
- 80028b8: 60fb str r3, [r7, #12]
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- 80028ba: 68fb ldr r3, [r7, #12]
- 80028bc: f023 0370 bic.w r3, r3, #112 ; 0x70
- 80028c0: 60fb str r3, [r7, #12]
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 80028c2: 683a ldr r2, [r7, #0]
- 80028c4: 68fb ldr r3, [r7, #12]
- 80028c6: 4313 orrs r3, r2
- 80028c8: f043 0307 orr.w r3, r3, #7
- 80028cc: 60fb str r3, [r7, #12]
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 80028ce: 687b ldr r3, [r7, #4]
- 80028d0: 68fa ldr r2, [r7, #12]
- 80028d2: 609a str r2, [r3, #8]
-}
- 80028d4: bf00 nop
- 80028d6: 3714 adds r7, #20
- 80028d8: 46bd mov sp, r7
- 80028da: f85d 7b04 ldr.w r7, [sp], #4
- 80028de: 4770 bx lr
-
-080028e0 <TIM_ETR_SetConfig>:
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
- 80028e0: b480 push {r7}
- 80028e2: b087 sub sp, #28
- 80028e4: af00 add r7, sp, #0
- 80028e6: 60f8 str r0, [r7, #12]
- 80028e8: 60b9 str r1, [r7, #8]
- 80028ea: 607a str r2, [r7, #4]
- 80028ec: 603b str r3, [r7, #0]
- uint32_t tmpsmcr;
-
- tmpsmcr = TIMx->SMCR;
- 80028ee: 68fb ldr r3, [r7, #12]
- 80028f0: 689b ldr r3, [r3, #8]
- 80028f2: 617b str r3, [r7, #20]
-
- /* Reset the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 80028f4: 697b ldr r3, [r7, #20]
- 80028f6: f423 437f bic.w r3, r3, #65280 ; 0xff00
- 80028fa: 617b str r3, [r7, #20]
-
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 80028fc: 683b ldr r3, [r7, #0]
- 80028fe: 021a lsls r2, r3, #8
- 8002900: 687b ldr r3, [r7, #4]
- 8002902: 431a orrs r2, r3
- 8002904: 68bb ldr r3, [r7, #8]
- 8002906: 4313 orrs r3, r2
- 8002908: 697a ldr r2, [r7, #20]
- 800290a: 4313 orrs r3, r2
- 800290c: 617b str r3, [r7, #20]
-
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- 800290e: 68fb ldr r3, [r7, #12]
- 8002910: 697a ldr r2, [r7, #20]
- 8002912: 609a str r2, [r3, #8]
-}
- 8002914: bf00 nop
- 8002916: 371c adds r7, #28
- 8002918: 46bd mov sp, r7
- 800291a: f85d 7b04 ldr.w r7, [sp], #4
- 800291e: 4770 bx lr
-
-08002920 <HAL_TIMEx_MasterConfigSynchronization>:
- * mode.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig)
-{
- 8002920: b480 push {r7}
- 8002922: b085 sub sp, #20
- 8002924: af00 add r7, sp, #0
- 8002926: 6078 str r0, [r7, #4]
- 8002928: 6039 str r1, [r7, #0]
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
- assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
- /* Check input state */
- __HAL_LOCK(htim);
- 800292a: 687b ldr r3, [r7, #4]
- 800292c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8002930: 2b01 cmp r3, #1
- 8002932: d101 bne.n 8002938 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 8002934: 2302 movs r3, #2
- 8002936: e045 b.n 80029c4 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 8002938: 687b ldr r3, [r7, #4]
- 800293a: 2201 movs r2, #1
- 800293c: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- /* Change the handler state */
- htim->State = HAL_TIM_STATE_BUSY;
- 8002940: 687b ldr r3, [r7, #4]
- 8002942: 2202 movs r2, #2
- 8002944: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = htim->Instance->CR2;
- 8002948: 687b ldr r3, [r7, #4]
- 800294a: 681b ldr r3, [r3, #0]
- 800294c: 685b ldr r3, [r3, #4]
- 800294e: 60fb str r3, [r7, #12]
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- 8002950: 687b ldr r3, [r7, #4]
- 8002952: 681b ldr r3, [r3, #0]
- 8002954: 689b ldr r3, [r3, #8]
- 8002956: 60bb str r3, [r7, #8]
-
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
- if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 8002958: 687b ldr r3, [r7, #4]
- 800295a: 681b ldr r3, [r3, #0]
- 800295c: 4a1c ldr r2, [pc, #112] ; (80029d0 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 800295e: 4293 cmp r3, r2
- 8002960: d004 beq.n 800296c <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 8002962: 687b ldr r3, [r7, #4]
- 8002964: 681b ldr r3, [r3, #0]
- 8002966: 4a1b ldr r2, [pc, #108] ; (80029d4 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 8002968: 4293 cmp r3, r2
- 800296a: d108 bne.n 800297e <HAL_TIMEx_MasterConfigSynchronization+0x5e>
- {
- /* Check the parameters */
- assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
-
- /* Clear the MMS2 bits */
- tmpcr2 &= ~TIM_CR2_MMS2;
- 800296c: 68fb ldr r3, [r7, #12]
- 800296e: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 8002972: 60fb str r3, [r7, #12]
- /* Select the TRGO2 source*/
- tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 8002974: 683b ldr r3, [r7, #0]
- 8002976: 685b ldr r3, [r3, #4]
- 8002978: 68fa ldr r2, [r7, #12]
- 800297a: 4313 orrs r3, r2
- 800297c: 60fb str r3, [r7, #12]
- }
-
- /* Reset the MMS Bits */
- tmpcr2 &= ~TIM_CR2_MMS;
- 800297e: 68fb ldr r3, [r7, #12]
- 8002980: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8002984: 60fb str r3, [r7, #12]
- /* Select the TRGO source */
- tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 8002986: 683b ldr r3, [r7, #0]
- 8002988: 681b ldr r3, [r3, #0]
- 800298a: 68fa ldr r2, [r7, #12]
- 800298c: 4313 orrs r3, r2
- 800298e: 60fb str r3, [r7, #12]
-
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- 8002990: 68bb ldr r3, [r7, #8]
- 8002992: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8002996: 60bb str r3, [r7, #8]
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 8002998: 683b ldr r3, [r7, #0]
- 800299a: 689b ldr r3, [r3, #8]
- 800299c: 68ba ldr r2, [r7, #8]
- 800299e: 4313 orrs r3, r2
- 80029a0: 60bb str r3, [r7, #8]
-
- /* Update TIMx CR2 */
- htim->Instance->CR2 = tmpcr2;
- 80029a2: 687b ldr r3, [r7, #4]
- 80029a4: 681b ldr r3, [r3, #0]
- 80029a6: 68fa ldr r2, [r7, #12]
- 80029a8: 605a str r2, [r3, #4]
-
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
- 80029aa: 687b ldr r3, [r7, #4]
- 80029ac: 681b ldr r3, [r3, #0]
- 80029ae: 68ba ldr r2, [r7, #8]
- 80029b0: 609a str r2, [r3, #8]
-
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
- 80029b2: 687b ldr r3, [r7, #4]
- 80029b4: 2201 movs r2, #1
- 80029b6: f883 203d strb.w r2, [r3, #61] ; 0x3d
-
- __HAL_UNLOCK(htim);
- 80029ba: 687b ldr r3, [r7, #4]
- 80029bc: 2200 movs r2, #0
- 80029be: f883 203c strb.w r2, [r3, #60] ; 0x3c
-
- return HAL_OK;
- 80029c2: 2300 movs r3, #0
-}
- 80029c4: 4618 mov r0, r3
- 80029c6: 3714 adds r7, #20
- 80029c8: 46bd mov sp, r7
- 80029ca: f85d 7b04 ldr.w r7, [sp], #4
- 80029ce: 4770 bx lr
- 80029d0: 40010000 .word 0x40010000
- 80029d4: 40010400 .word 0x40010400
-
-080029d8 <HAL_TIMEx_CommutCallback>:
- * @brief Hall commutation changed callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- 80029d8: b480 push {r7}
- 80029da: b083 sub sp, #12
- 80029dc: af00 add r7, sp, #0
- 80029de: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutCallback could be implemented in the user file
- */
-}
- 80029e0: bf00 nop
- 80029e2: 370c adds r7, #12
- 80029e4: 46bd mov sp, r7
- 80029e6: f85d 7b04 ldr.w r7, [sp], #4
- 80029ea: 4770 bx lr
-
-080029ec <HAL_TIMEx_BreakCallback>:
- * @brief Hall Break detection callback in non-blocking mode
- * @param htim TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- 80029ec: b480 push {r7}
- 80029ee: b083 sub sp, #12
- 80029f0: af00 add r7, sp, #0
- 80029f2: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_TIMEx_BreakCallback could be implemented in the user file
- */
-}
- 80029f4: bf00 nop
- 80029f6: 370c adds r7, #12
- 80029f8: 46bd mov sp, r7
- 80029fa: f85d 7b04 ldr.w r7, [sp], #4
- 80029fe: 4770 bx lr
-
-08002a00 <HAL_TIMEx_Break2Callback>:
- * @brief Hall Break2 detection callback in non blocking mode
- * @param htim: TIM handle
- * @retval None
- */
-__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- 8002a00: b480 push {r7}
- 8002a02: b083 sub sp, #12
- 8002a04: af00 add r7, sp, #0
- 8002a06: 6078 str r0, [r7, #4]
- UNUSED(htim);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_Break2Callback could be implemented in the user file
- */
-}
- 8002a08: bf00 nop
- 8002a0a: 370c adds r7, #12
- 8002a0c: 46bd mov sp, r7
- 8002a0e: f85d 7b04 ldr.w r7, [sp], #4
- 8002a12: 4770 bx lr
-
-08002a14 <HAL_UART_Init>:
- * parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- 8002a14: b580 push {r7, lr}
- 8002a16: b082 sub sp, #8
- 8002a18: af00 add r7, sp, #0
- 8002a1a: 6078 str r0, [r7, #4]
- /* Check the UART handle allocation */
- if (huart == NULL)
- 8002a1c: 687b ldr r3, [r7, #4]
- 8002a1e: 2b00 cmp r3, #0
- 8002a20: d101 bne.n 8002a26 <HAL_UART_Init+0x12>
- {
- return HAL_ERROR;
- 8002a22: 2301 movs r3, #1
- 8002a24: e040 b.n 8002aa8 <HAL_UART_Init+0x94>
- {
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
- }
-
- if (huart->gState == HAL_UART_STATE_RESET)
- 8002a26: 687b ldr r3, [r7, #4]
- 8002a28: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002a2a: 2b00 cmp r3, #0
- 8002a2c: d106 bne.n 8002a3c <HAL_UART_Init+0x28>
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
- 8002a2e: 687b ldr r3, [r7, #4]
- 8002a30: 2200 movs r2, #0
- 8002a32: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Init the low level hardware */
- huart->MspInitCallback(huart);
-#else
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
- 8002a36: 6878 ldr r0, [r7, #4]
- 8002a38: f7fd ff52 bl 80008e0 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
- 8002a3c: 687b ldr r3, [r7, #4]
- 8002a3e: 2224 movs r2, #36 ; 0x24
- 8002a40: 675a str r2, [r3, #116] ; 0x74
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
- 8002a42: 687b ldr r3, [r7, #4]
- 8002a44: 681b ldr r3, [r3, #0]
- 8002a46: 681a ldr r2, [r3, #0]
- 8002a48: 687b ldr r3, [r7, #4]
- 8002a4a: 681b ldr r3, [r3, #0]
- 8002a4c: f022 0201 bic.w r2, r2, #1
- 8002a50: 601a str r2, [r3, #0]
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- 8002a52: 6878 ldr r0, [r7, #4]
- 8002a54: f000 fa86 bl 8002f64 <UART_SetConfig>
- 8002a58: 4603 mov r3, r0
- 8002a5a: 2b01 cmp r3, #1
- 8002a5c: d101 bne.n 8002a62 <HAL_UART_Init+0x4e>
- {
- return HAL_ERROR;
- 8002a5e: 2301 movs r3, #1
- 8002a60: e022 b.n 8002aa8 <HAL_UART_Init+0x94>
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 8002a62: 687b ldr r3, [r7, #4]
- 8002a64: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002a66: 2b00 cmp r3, #0
- 8002a68: d002 beq.n 8002a70 <HAL_UART_Init+0x5c>
- {
- UART_AdvFeatureConfig(huart);
- 8002a6a: 6878 ldr r0, [r7, #4]
- 8002a6c: f000 fd1e bl 80034ac <UART_AdvFeatureConfig>
- }
-
- /* In asynchronous mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8002a70: 687b ldr r3, [r7, #4]
- 8002a72: 681b ldr r3, [r3, #0]
- 8002a74: 685a ldr r2, [r3, #4]
- 8002a76: 687b ldr r3, [r7, #4]
- 8002a78: 681b ldr r3, [r3, #0]
- 8002a7a: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 8002a7e: 605a str r2, [r3, #4]
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8002a80: 687b ldr r3, [r7, #4]
- 8002a82: 681b ldr r3, [r3, #0]
- 8002a84: 689a ldr r2, [r3, #8]
- 8002a86: 687b ldr r3, [r7, #4]
- 8002a88: 681b ldr r3, [r3, #0]
- 8002a8a: f022 022a bic.w r2, r2, #42 ; 0x2a
- 8002a8e: 609a str r2, [r3, #8]
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
- 8002a90: 687b ldr r3, [r7, #4]
- 8002a92: 681b ldr r3, [r3, #0]
- 8002a94: 681a ldr r2, [r3, #0]
- 8002a96: 687b ldr r3, [r7, #4]
- 8002a98: 681b ldr r3, [r3, #0]
- 8002a9a: f042 0201 orr.w r2, r2, #1
- 8002a9e: 601a str r2, [r3, #0]
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
- 8002aa0: 6878 ldr r0, [r7, #4]
- 8002aa2: f000 fda5 bl 80035f0 <UART_CheckIdleState>
- 8002aa6: 4603 mov r3, r0
-}
- 8002aa8: 4618 mov r0, r3
- 8002aaa: 3708 adds r7, #8
- 8002aac: 46bd mov sp, r7
- 8002aae: bd80 pop {r7, pc}
-
-08002ab0 <HAL_UART_Transmit>:
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- 8002ab0: b580 push {r7, lr}
- 8002ab2: b08a sub sp, #40 ; 0x28
- 8002ab4: af02 add r7, sp, #8
- 8002ab6: 60f8 str r0, [r7, #12]
- 8002ab8: 60b9 str r1, [r7, #8]
- 8002aba: 603b str r3, [r7, #0]
- 8002abc: 4613 mov r3, r2
- 8002abe: 80fb strh r3, [r7, #6]
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
- uint32_t tickstart;
-
- /* Check that a Tx process is not already ongoing */
- if (huart->gState == HAL_UART_STATE_READY)
- 8002ac0: 68fb ldr r3, [r7, #12]
- 8002ac2: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002ac4: 2b20 cmp r3, #32
- 8002ac6: d17f bne.n 8002bc8 <HAL_UART_Transmit+0x118>
- {
- if ((pData == NULL) || (Size == 0U))
- 8002ac8: 68bb ldr r3, [r7, #8]
- 8002aca: 2b00 cmp r3, #0
- 8002acc: d002 beq.n 8002ad4 <HAL_UART_Transmit+0x24>
- 8002ace: 88fb ldrh r3, [r7, #6]
- 8002ad0: 2b00 cmp r3, #0
- 8002ad2: d101 bne.n 8002ad8 <HAL_UART_Transmit+0x28>
- {
- return HAL_ERROR;
- 8002ad4: 2301 movs r3, #1
- 8002ad6: e078 b.n 8002bca <HAL_UART_Transmit+0x11a>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8002ad8: 68fb ldr r3, [r7, #12]
- 8002ada: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 8002ade: 2b01 cmp r3, #1
- 8002ae0: d101 bne.n 8002ae6 <HAL_UART_Transmit+0x36>
- 8002ae2: 2302 movs r3, #2
- 8002ae4: e071 b.n 8002bca <HAL_UART_Transmit+0x11a>
- 8002ae6: 68fb ldr r3, [r7, #12]
- 8002ae8: 2201 movs r2, #1
- 8002aea: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8002aee: 68fb ldr r3, [r7, #12]
- 8002af0: 2200 movs r2, #0
- 8002af2: 67da str r2, [r3, #124] ; 0x7c
- huart->gState = HAL_UART_STATE_BUSY_TX;
- 8002af4: 68fb ldr r3, [r7, #12]
- 8002af6: 2221 movs r2, #33 ; 0x21
- 8002af8: 675a str r2, [r3, #116] ; 0x74
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 8002afa: f7fe f82f bl 8000b5c <HAL_GetTick>
- 8002afe: 6178 str r0, [r7, #20]
-
- huart->TxXferSize = Size;
- 8002b00: 68fb ldr r3, [r7, #12]
- 8002b02: 88fa ldrh r2, [r7, #6]
- 8002b04: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
- huart->TxXferCount = Size;
- 8002b08: 68fb ldr r3, [r7, #12]
- 8002b0a: 88fa ldrh r2, [r7, #6]
- 8002b0c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-
- /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8002b10: 68fb ldr r3, [r7, #12]
- 8002b12: 689b ldr r3, [r3, #8]
- 8002b14: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8002b18: d108 bne.n 8002b2c <HAL_UART_Transmit+0x7c>
- 8002b1a: 68fb ldr r3, [r7, #12]
- 8002b1c: 691b ldr r3, [r3, #16]
- 8002b1e: 2b00 cmp r3, #0
- 8002b20: d104 bne.n 8002b2c <HAL_UART_Transmit+0x7c>
- {
- pdata8bits = NULL;
- 8002b22: 2300 movs r3, #0
- 8002b24: 61fb str r3, [r7, #28]
- pdata16bits = (uint16_t *) pData;
- 8002b26: 68bb ldr r3, [r7, #8]
- 8002b28: 61bb str r3, [r7, #24]
- 8002b2a: e003 b.n 8002b34 <HAL_UART_Transmit+0x84>
- }
- else
- {
- pdata8bits = pData;
- 8002b2c: 68bb ldr r3, [r7, #8]
- 8002b2e: 61fb str r3, [r7, #28]
- pdata16bits = NULL;
- 8002b30: 2300 movs r3, #0
- 8002b32: 61bb str r3, [r7, #24]
- }
-
- while (huart->TxXferCount > 0U)
- 8002b34: e02c b.n 8002b90 <HAL_UART_Transmit+0xe0>
- {
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 8002b36: 683b ldr r3, [r7, #0]
- 8002b38: 9300 str r3, [sp, #0]
- 8002b3a: 697b ldr r3, [r7, #20]
- 8002b3c: 2200 movs r2, #0
- 8002b3e: 2180 movs r1, #128 ; 0x80
- 8002b40: 68f8 ldr r0, [r7, #12]
- 8002b42: f000 fd84 bl 800364e <UART_WaitOnFlagUntilTimeout>
- 8002b46: 4603 mov r3, r0
- 8002b48: 2b00 cmp r3, #0
- 8002b4a: d001 beq.n 8002b50 <HAL_UART_Transmit+0xa0>
- {
- return HAL_TIMEOUT;
- 8002b4c: 2303 movs r3, #3
- 8002b4e: e03c b.n 8002bca <HAL_UART_Transmit+0x11a>
- }
- if (pdata8bits == NULL)
- 8002b50: 69fb ldr r3, [r7, #28]
- 8002b52: 2b00 cmp r3, #0
- 8002b54: d10b bne.n 8002b6e <HAL_UART_Transmit+0xbe>
- {
- huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 8002b56: 69bb ldr r3, [r7, #24]
- 8002b58: 881b ldrh r3, [r3, #0]
- 8002b5a: 461a mov r2, r3
- 8002b5c: 68fb ldr r3, [r7, #12]
- 8002b5e: 681b ldr r3, [r3, #0]
- 8002b60: f3c2 0208 ubfx r2, r2, #0, #9
- 8002b64: 629a str r2, [r3, #40] ; 0x28
- pdata16bits++;
- 8002b66: 69bb ldr r3, [r7, #24]
- 8002b68: 3302 adds r3, #2
- 8002b6a: 61bb str r3, [r7, #24]
- 8002b6c: e007 b.n 8002b7e <HAL_UART_Transmit+0xce>
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 8002b6e: 69fb ldr r3, [r7, #28]
- 8002b70: 781a ldrb r2, [r3, #0]
- 8002b72: 68fb ldr r3, [r7, #12]
- 8002b74: 681b ldr r3, [r3, #0]
- 8002b76: 629a str r2, [r3, #40] ; 0x28
- pdata8bits++;
- 8002b78: 69fb ldr r3, [r7, #28]
- 8002b7a: 3301 adds r3, #1
- 8002b7c: 61fb str r3, [r7, #28]
- }
- huart->TxXferCount--;
- 8002b7e: 68fb ldr r3, [r7, #12]
- 8002b80: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 8002b84: b29b uxth r3, r3
- 8002b86: 3b01 subs r3, #1
- 8002b88: b29a uxth r2, r3
- 8002b8a: 68fb ldr r3, [r7, #12]
- 8002b8c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
- while (huart->TxXferCount > 0U)
- 8002b90: 68fb ldr r3, [r7, #12]
- 8002b92: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 8002b96: b29b uxth r3, r3
- 8002b98: 2b00 cmp r3, #0
- 8002b9a: d1cc bne.n 8002b36 <HAL_UART_Transmit+0x86>
- }
-
- if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 8002b9c: 683b ldr r3, [r7, #0]
- 8002b9e: 9300 str r3, [sp, #0]
- 8002ba0: 697b ldr r3, [r7, #20]
- 8002ba2: 2200 movs r2, #0
- 8002ba4: 2140 movs r1, #64 ; 0x40
- 8002ba6: 68f8 ldr r0, [r7, #12]
- 8002ba8: f000 fd51 bl 800364e <UART_WaitOnFlagUntilTimeout>
- 8002bac: 4603 mov r3, r0
- 8002bae: 2b00 cmp r3, #0
- 8002bb0: d001 beq.n 8002bb6 <HAL_UART_Transmit+0x106>
- {
- return HAL_TIMEOUT;
- 8002bb2: 2303 movs r3, #3
- 8002bb4: e009 b.n 8002bca <HAL_UART_Transmit+0x11a>
- }
-
- /* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 8002bb6: 68fb ldr r3, [r7, #12]
- 8002bb8: 2220 movs r2, #32
- 8002bba: 675a str r2, [r3, #116] ; 0x74
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8002bbc: 68fb ldr r3, [r7, #12]
- 8002bbe: 2200 movs r2, #0
- 8002bc0: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 8002bc4: 2300 movs r3, #0
- 8002bc6: e000 b.n 8002bca <HAL_UART_Transmit+0x11a>
- }
- else
- {
- return HAL_BUSY;
- 8002bc8: 2302 movs r3, #2
- }
-}
- 8002bca: 4618 mov r0, r3
- 8002bcc: 3720 adds r7, #32
- 8002bce: 46bd mov sp, r7
- 8002bd0: bd80 pop {r7, pc}
- ...
-
-08002bd4 <HAL_UART_Receive_IT>:
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- 8002bd4: b480 push {r7}
- 8002bd6: b085 sub sp, #20
- 8002bd8: af00 add r7, sp, #0
- 8002bda: 60f8 str r0, [r7, #12]
- 8002bdc: 60b9 str r1, [r7, #8]
- 8002bde: 4613 mov r3, r2
- 8002be0: 80fb strh r3, [r7, #6]
- /* Check that a Rx process is not already ongoing */
- if (huart->RxState == HAL_UART_STATE_READY)
- 8002be2: 68fb ldr r3, [r7, #12]
- 8002be4: 6f9b ldr r3, [r3, #120] ; 0x78
- 8002be6: 2b20 cmp r3, #32
- 8002be8: f040 808a bne.w 8002d00 <HAL_UART_Receive_IT+0x12c>
- {
- if ((pData == NULL) || (Size == 0U))
- 8002bec: 68bb ldr r3, [r7, #8]
- 8002bee: 2b00 cmp r3, #0
- 8002bf0: d002 beq.n 8002bf8 <HAL_UART_Receive_IT+0x24>
- 8002bf2: 88fb ldrh r3, [r7, #6]
- 8002bf4: 2b00 cmp r3, #0
- 8002bf6: d101 bne.n 8002bfc <HAL_UART_Receive_IT+0x28>
- {
- return HAL_ERROR;
- 8002bf8: 2301 movs r3, #1
- 8002bfa: e082 b.n 8002d02 <HAL_UART_Receive_IT+0x12e>
- }
-
- /* Process Locked */
- __HAL_LOCK(huart);
- 8002bfc: 68fb ldr r3, [r7, #12]
- 8002bfe: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 8002c02: 2b01 cmp r3, #1
- 8002c04: d101 bne.n 8002c0a <HAL_UART_Receive_IT+0x36>
- 8002c06: 2302 movs r3, #2
- 8002c08: e07b b.n 8002d02 <HAL_UART_Receive_IT+0x12e>
- 8002c0a: 68fb ldr r3, [r7, #12]
- 8002c0c: 2201 movs r2, #1
- 8002c0e: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- huart->pRxBuffPtr = pData;
- 8002c12: 68fb ldr r3, [r7, #12]
- 8002c14: 68ba ldr r2, [r7, #8]
- 8002c16: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferSize = Size;
- 8002c18: 68fb ldr r3, [r7, #12]
- 8002c1a: 88fa ldrh r2, [r7, #6]
- 8002c1c: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
- huart->RxXferCount = Size;
- 8002c20: 68fb ldr r3, [r7, #12]
- 8002c22: 88fa ldrh r2, [r7, #6]
- 8002c24: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->RxISR = NULL;
- 8002c28: 68fb ldr r3, [r7, #12]
- 8002c2a: 2200 movs r2, #0
- 8002c2c: 661a str r2, [r3, #96] ; 0x60
-
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
- 8002c2e: 68fb ldr r3, [r7, #12]
- 8002c30: 689b ldr r3, [r3, #8]
- 8002c32: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8002c36: d10e bne.n 8002c56 <HAL_UART_Receive_IT+0x82>
- 8002c38: 68fb ldr r3, [r7, #12]
- 8002c3a: 691b ldr r3, [r3, #16]
- 8002c3c: 2b00 cmp r3, #0
- 8002c3e: d105 bne.n 8002c4c <HAL_UART_Receive_IT+0x78>
- 8002c40: 68fb ldr r3, [r7, #12]
- 8002c42: f240 12ff movw r2, #511 ; 0x1ff
- 8002c46: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8002c4a: e02d b.n 8002ca8 <HAL_UART_Receive_IT+0xd4>
- 8002c4c: 68fb ldr r3, [r7, #12]
- 8002c4e: 22ff movs r2, #255 ; 0xff
- 8002c50: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8002c54: e028 b.n 8002ca8 <HAL_UART_Receive_IT+0xd4>
- 8002c56: 68fb ldr r3, [r7, #12]
- 8002c58: 689b ldr r3, [r3, #8]
- 8002c5a: 2b00 cmp r3, #0
- 8002c5c: d10d bne.n 8002c7a <HAL_UART_Receive_IT+0xa6>
- 8002c5e: 68fb ldr r3, [r7, #12]
- 8002c60: 691b ldr r3, [r3, #16]
- 8002c62: 2b00 cmp r3, #0
- 8002c64: d104 bne.n 8002c70 <HAL_UART_Receive_IT+0x9c>
- 8002c66: 68fb ldr r3, [r7, #12]
- 8002c68: 22ff movs r2, #255 ; 0xff
- 8002c6a: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8002c6e: e01b b.n 8002ca8 <HAL_UART_Receive_IT+0xd4>
- 8002c70: 68fb ldr r3, [r7, #12]
- 8002c72: 227f movs r2, #127 ; 0x7f
- 8002c74: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8002c78: e016 b.n 8002ca8 <HAL_UART_Receive_IT+0xd4>
- 8002c7a: 68fb ldr r3, [r7, #12]
- 8002c7c: 689b ldr r3, [r3, #8]
- 8002c7e: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
- 8002c82: d10d bne.n 8002ca0 <HAL_UART_Receive_IT+0xcc>
- 8002c84: 68fb ldr r3, [r7, #12]
- 8002c86: 691b ldr r3, [r3, #16]
- 8002c88: 2b00 cmp r3, #0
- 8002c8a: d104 bne.n 8002c96 <HAL_UART_Receive_IT+0xc2>
- 8002c8c: 68fb ldr r3, [r7, #12]
- 8002c8e: 227f movs r2, #127 ; 0x7f
- 8002c90: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8002c94: e008 b.n 8002ca8 <HAL_UART_Receive_IT+0xd4>
- 8002c96: 68fb ldr r3, [r7, #12]
- 8002c98: 223f movs r2, #63 ; 0x3f
- 8002c9a: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
- 8002c9e: e003 b.n 8002ca8 <HAL_UART_Receive_IT+0xd4>
- 8002ca0: 68fb ldr r3, [r7, #12]
- 8002ca2: 2200 movs r2, #0
- 8002ca4: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8002ca8: 68fb ldr r3, [r7, #12]
- 8002caa: 2200 movs r2, #0
- 8002cac: 67da str r2, [r3, #124] ; 0x7c
- huart->RxState = HAL_UART_STATE_BUSY_RX;
- 8002cae: 68fb ldr r3, [r7, #12]
- 8002cb0: 2222 movs r2, #34 ; 0x22
- 8002cb2: 679a str r2, [r3, #120] ; 0x78
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8002cb4: 68fb ldr r3, [r7, #12]
- 8002cb6: 681b ldr r3, [r3, #0]
- 8002cb8: 689a ldr r2, [r3, #8]
- 8002cba: 68fb ldr r3, [r7, #12]
- 8002cbc: 681b ldr r3, [r3, #0]
- 8002cbe: f042 0201 orr.w r2, r2, #1
- 8002cc2: 609a str r2, [r3, #8]
-
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8002cc4: 68fb ldr r3, [r7, #12]
- 8002cc6: 689b ldr r3, [r3, #8]
- 8002cc8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8002ccc: d107 bne.n 8002cde <HAL_UART_Receive_IT+0x10a>
- 8002cce: 68fb ldr r3, [r7, #12]
- 8002cd0: 691b ldr r3, [r3, #16]
- 8002cd2: 2b00 cmp r3, #0
- 8002cd4: d103 bne.n 8002cde <HAL_UART_Receive_IT+0x10a>
- {
- huart->RxISR = UART_RxISR_16BIT;
- 8002cd6: 68fb ldr r3, [r7, #12]
- 8002cd8: 4a0d ldr r2, [pc, #52] ; (8002d10 <HAL_UART_Receive_IT+0x13c>)
- 8002cda: 661a str r2, [r3, #96] ; 0x60
- 8002cdc: e002 b.n 8002ce4 <HAL_UART_Receive_IT+0x110>
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- 8002cde: 68fb ldr r3, [r7, #12]
- 8002ce0: 4a0c ldr r2, [pc, #48] ; (8002d14 <HAL_UART_Receive_IT+0x140>)
- 8002ce2: 661a str r2, [r3, #96] ; 0x60
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 8002ce4: 68fb ldr r3, [r7, #12]
- 8002ce6: 2200 movs r2, #0
- 8002ce8: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- 8002cec: 68fb ldr r3, [r7, #12]
- 8002cee: 681b ldr r3, [r3, #0]
- 8002cf0: 681a ldr r2, [r3, #0]
- 8002cf2: 68fb ldr r3, [r7, #12]
- 8002cf4: 681b ldr r3, [r3, #0]
- 8002cf6: f442 7290 orr.w r2, r2, #288 ; 0x120
- 8002cfa: 601a str r2, [r3, #0]
-
- return HAL_OK;
- 8002cfc: 2300 movs r3, #0
- 8002cfe: e000 b.n 8002d02 <HAL_UART_Receive_IT+0x12e>
- }
- else
- {
- return HAL_BUSY;
- 8002d00: 2302 movs r3, #2
- }
-}
- 8002d02: 4618 mov r0, r3
- 8002d04: 3714 adds r7, #20
- 8002d06: 46bd mov sp, r7
- 8002d08: f85d 7b04 ldr.w r7, [sp], #4
- 8002d0c: 4770 bx lr
- 8002d0e: bf00 nop
- 8002d10: 08003823 .word 0x08003823
- 8002d14: 0800377d .word 0x0800377d
-
-08002d18 <HAL_UART_IRQHandler>:
- * @brief Handle UART interrupt request.
- * @param huart UART handle.
- * @retval None
- */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
- 8002d18: b580 push {r7, lr}
- 8002d1a: b088 sub sp, #32
- 8002d1c: af00 add r7, sp, #0
- 8002d1e: 6078 str r0, [r7, #4]
- uint32_t isrflags = READ_REG(huart->Instance->ISR);
- 8002d20: 687b ldr r3, [r7, #4]
- 8002d22: 681b ldr r3, [r3, #0]
- 8002d24: 69db ldr r3, [r3, #28]
- 8002d26: 61fb str r3, [r7, #28]
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- 8002d28: 687b ldr r3, [r7, #4]
- 8002d2a: 681b ldr r3, [r3, #0]
- 8002d2c: 681b ldr r3, [r3, #0]
- 8002d2e: 61bb str r3, [r7, #24]
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- 8002d30: 687b ldr r3, [r7, #4]
- 8002d32: 681b ldr r3, [r3, #0]
- 8002d34: 689b ldr r3, [r3, #8]
- 8002d36: 617b str r3, [r7, #20]
-
- uint32_t errorflags;
- uint32_t errorcode;
-
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- 8002d38: 69fb ldr r3, [r7, #28]
- 8002d3a: f003 030f and.w r3, r3, #15
- 8002d3e: 613b str r3, [r7, #16]
- if (errorflags == 0U)
- 8002d40: 693b ldr r3, [r7, #16]
- 8002d42: 2b00 cmp r3, #0
- 8002d44: d113 bne.n 8002d6e <HAL_UART_IRQHandler+0x56>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 8002d46: 69fb ldr r3, [r7, #28]
- 8002d48: f003 0320 and.w r3, r3, #32
- 8002d4c: 2b00 cmp r3, #0
- 8002d4e: d00e beq.n 8002d6e <HAL_UART_IRQHandler+0x56>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 8002d50: 69bb ldr r3, [r7, #24]
- 8002d52: f003 0320 and.w r3, r3, #32
- 8002d56: 2b00 cmp r3, #0
- 8002d58: d009 beq.n 8002d6e <HAL_UART_IRQHandler+0x56>
- {
- if (huart->RxISR != NULL)
- 8002d5a: 687b ldr r3, [r7, #4]
- 8002d5c: 6e1b ldr r3, [r3, #96] ; 0x60
- 8002d5e: 2b00 cmp r3, #0
- 8002d60: f000 80eb beq.w 8002f3a <HAL_UART_IRQHandler+0x222>
- {
- huart->RxISR(huart);
- 8002d64: 687b ldr r3, [r7, #4]
- 8002d66: 6e1b ldr r3, [r3, #96] ; 0x60
- 8002d68: 6878 ldr r0, [r7, #4]
- 8002d6a: 4798 blx r3
- }
- return;
- 8002d6c: e0e5 b.n 8002f3a <HAL_UART_IRQHandler+0x222>
- }
- }
-
- /* If some errors occur */
- if ((errorflags != 0U)
- 8002d6e: 693b ldr r3, [r7, #16]
- 8002d70: 2b00 cmp r3, #0
- 8002d72: f000 80c0 beq.w 8002ef6 <HAL_UART_IRQHandler+0x1de>
- && (((cr3its & USART_CR3_EIE) != 0U)
- 8002d76: 697b ldr r3, [r7, #20]
- 8002d78: f003 0301 and.w r3, r3, #1
- 8002d7c: 2b00 cmp r3, #0
- 8002d7e: d105 bne.n 8002d8c <HAL_UART_IRQHandler+0x74>
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
- 8002d80: 69bb ldr r3, [r7, #24]
- 8002d82: f403 7390 and.w r3, r3, #288 ; 0x120
- 8002d86: 2b00 cmp r3, #0
- 8002d88: f000 80b5 beq.w 8002ef6 <HAL_UART_IRQHandler+0x1de>
- {
- /* UART parity error interrupt occurred -------------------------------------*/
- if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
- 8002d8c: 69fb ldr r3, [r7, #28]
- 8002d8e: f003 0301 and.w r3, r3, #1
- 8002d92: 2b00 cmp r3, #0
- 8002d94: d00e beq.n 8002db4 <HAL_UART_IRQHandler+0x9c>
- 8002d96: 69bb ldr r3, [r7, #24]
- 8002d98: f403 7380 and.w r3, r3, #256 ; 0x100
- 8002d9c: 2b00 cmp r3, #0
- 8002d9e: d009 beq.n 8002db4 <HAL_UART_IRQHandler+0x9c>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
- 8002da0: 687b ldr r3, [r7, #4]
- 8002da2: 681b ldr r3, [r3, #0]
- 8002da4: 2201 movs r2, #1
- 8002da6: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- 8002da8: 687b ldr r3, [r7, #4]
- 8002daa: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002dac: f043 0201 orr.w r2, r3, #1
- 8002db0: 687b ldr r3, [r7, #4]
- 8002db2: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8002db4: 69fb ldr r3, [r7, #28]
- 8002db6: f003 0302 and.w r3, r3, #2
- 8002dba: 2b00 cmp r3, #0
- 8002dbc: d00e beq.n 8002ddc <HAL_UART_IRQHandler+0xc4>
- 8002dbe: 697b ldr r3, [r7, #20]
- 8002dc0: f003 0301 and.w r3, r3, #1
- 8002dc4: 2b00 cmp r3, #0
- 8002dc6: d009 beq.n 8002ddc <HAL_UART_IRQHandler+0xc4>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
- 8002dc8: 687b ldr r3, [r7, #4]
- 8002dca: 681b ldr r3, [r3, #0]
- 8002dcc: 2202 movs r2, #2
- 8002dce: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- 8002dd0: 687b ldr r3, [r7, #4]
- 8002dd2: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002dd4: f043 0204 orr.w r2, r3, #4
- 8002dd8: 687b ldr r3, [r7, #4]
- 8002dda: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
- 8002ddc: 69fb ldr r3, [r7, #28]
- 8002dde: f003 0304 and.w r3, r3, #4
- 8002de2: 2b00 cmp r3, #0
- 8002de4: d00e beq.n 8002e04 <HAL_UART_IRQHandler+0xec>
- 8002de6: 697b ldr r3, [r7, #20]
- 8002de8: f003 0301 and.w r3, r3, #1
- 8002dec: 2b00 cmp r3, #0
- 8002dee: d009 beq.n 8002e04 <HAL_UART_IRQHandler+0xec>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
- 8002df0: 687b ldr r3, [r7, #4]
- 8002df2: 681b ldr r3, [r3, #0]
- 8002df4: 2204 movs r2, #4
- 8002df6: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- 8002df8: 687b ldr r3, [r7, #4]
- 8002dfa: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002dfc: f043 0202 orr.w r2, r3, #2
- 8002e00: 687b ldr r3, [r7, #4]
- 8002e02: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if (((isrflags & USART_ISR_ORE) != 0U)
- 8002e04: 69fb ldr r3, [r7, #28]
- 8002e06: f003 0308 and.w r3, r3, #8
- 8002e0a: 2b00 cmp r3, #0
- 8002e0c: d013 beq.n 8002e36 <HAL_UART_IRQHandler+0x11e>
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8002e0e: 69bb ldr r3, [r7, #24]
- 8002e10: f003 0320 and.w r3, r3, #32
- 8002e14: 2b00 cmp r3, #0
- 8002e16: d104 bne.n 8002e22 <HAL_UART_IRQHandler+0x10a>
- ((cr3its & USART_CR3_EIE) != 0U)))
- 8002e18: 697b ldr r3, [r7, #20]
- 8002e1a: f003 0301 and.w r3, r3, #1
- && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
- 8002e1e: 2b00 cmp r3, #0
- 8002e20: d009 beq.n 8002e36 <HAL_UART_IRQHandler+0x11e>
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 8002e22: 687b ldr r3, [r7, #4]
- 8002e24: 681b ldr r3, [r3, #0]
- 8002e26: 2208 movs r2, #8
- 8002e28: 621a str r2, [r3, #32]
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- 8002e2a: 687b ldr r3, [r7, #4]
- 8002e2c: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002e2e: f043 0208 orr.w r2, r3, #8
- 8002e32: 687b ldr r3, [r7, #4]
- 8002e34: 67da str r2, [r3, #124] ; 0x7c
- }
-
- /* Call UART Error Call back function if need be --------------------------*/
- if (huart->ErrorCode != HAL_UART_ERROR_NONE)
- 8002e36: 687b ldr r3, [r7, #4]
- 8002e38: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002e3a: 2b00 cmp r3, #0
- 8002e3c: d07f beq.n 8002f3e <HAL_UART_IRQHandler+0x226>
- {
- /* UART in mode Receiver ---------------------------------------------------*/
- if (((isrflags & USART_ISR_RXNE) != 0U)
- 8002e3e: 69fb ldr r3, [r7, #28]
- 8002e40: f003 0320 and.w r3, r3, #32
- 8002e44: 2b00 cmp r3, #0
- 8002e46: d00c beq.n 8002e62 <HAL_UART_IRQHandler+0x14a>
- && ((cr1its & USART_CR1_RXNEIE) != 0U))
- 8002e48: 69bb ldr r3, [r7, #24]
- 8002e4a: f003 0320 and.w r3, r3, #32
- 8002e4e: 2b00 cmp r3, #0
- 8002e50: d007 beq.n 8002e62 <HAL_UART_IRQHandler+0x14a>
- {
- if (huart->RxISR != NULL)
- 8002e52: 687b ldr r3, [r7, #4]
- 8002e54: 6e1b ldr r3, [r3, #96] ; 0x60
- 8002e56: 2b00 cmp r3, #0
- 8002e58: d003 beq.n 8002e62 <HAL_UART_IRQHandler+0x14a>
- {
- huart->RxISR(huart);
- 8002e5a: 687b ldr r3, [r7, #4]
- 8002e5c: 6e1b ldr r3, [r3, #96] ; 0x60
- 8002e5e: 6878 ldr r0, [r7, #4]
- 8002e60: 4798 blx r3
- }
- }
-
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- errorcode = huart->ErrorCode;
- 8002e62: 687b ldr r3, [r7, #4]
- 8002e64: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8002e66: 60fb str r3, [r7, #12]
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8002e68: 687b ldr r3, [r7, #4]
- 8002e6a: 681b ldr r3, [r3, #0]
- 8002e6c: 689b ldr r3, [r3, #8]
- 8002e6e: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002e72: 2b40 cmp r3, #64 ; 0x40
- 8002e74: d004 beq.n 8002e80 <HAL_UART_IRQHandler+0x168>
- ((errorcode & HAL_UART_ERROR_ORE) != 0U))
- 8002e76: 68fb ldr r3, [r7, #12]
- 8002e78: f003 0308 and.w r3, r3, #8
- if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
- 8002e7c: 2b00 cmp r3, #0
- 8002e7e: d031 beq.n 8002ee4 <HAL_UART_IRQHandler+0x1cc>
- {
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- UART_EndRxTransfer(huart);
- 8002e80: 6878 ldr r0, [r7, #4]
- 8002e82: f000 fc2c bl 80036de <UART_EndRxTransfer>
-
- /* Disable the UART DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8002e86: 687b ldr r3, [r7, #4]
- 8002e88: 681b ldr r3, [r3, #0]
- 8002e8a: 689b ldr r3, [r3, #8]
- 8002e8c: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002e90: 2b40 cmp r3, #64 ; 0x40
- 8002e92: d123 bne.n 8002edc <HAL_UART_IRQHandler+0x1c4>
- {
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 8002e94: 687b ldr r3, [r7, #4]
- 8002e96: 681b ldr r3, [r3, #0]
- 8002e98: 689a ldr r2, [r3, #8]
- 8002e9a: 687b ldr r3, [r7, #4]
- 8002e9c: 681b ldr r3, [r3, #0]
- 8002e9e: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8002ea2: 609a str r2, [r3, #8]
-
- /* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL)
- 8002ea4: 687b ldr r3, [r7, #4]
- 8002ea6: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002ea8: 2b00 cmp r3, #0
- 8002eaa: d013 beq.n 8002ed4 <HAL_UART_IRQHandler+0x1bc>
- {
- /* Set the UART DMA Abort callback :
- will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
- huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- 8002eac: 687b ldr r3, [r7, #4]
- 8002eae: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002eb0: 4a26 ldr r2, [pc, #152] ; (8002f4c <HAL_UART_IRQHandler+0x234>)
- 8002eb2: 651a str r2, [r3, #80] ; 0x50
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
- 8002eb4: 687b ldr r3, [r7, #4]
- 8002eb6: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002eb8: 4618 mov r0, r3
- 8002eba: f7fd ff6c bl 8000d96 <HAL_DMA_Abort_IT>
- 8002ebe: 4603 mov r3, r0
- 8002ec0: 2b00 cmp r3, #0
- 8002ec2: d016 beq.n 8002ef2 <HAL_UART_IRQHandler+0x1da>
- {
- /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
- huart->hdmarx->XferAbortCallback(huart->hdmarx);
- 8002ec4: 687b ldr r3, [r7, #4]
- 8002ec6: 6edb ldr r3, [r3, #108] ; 0x6c
- 8002ec8: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002eca: 687a ldr r2, [r7, #4]
- 8002ecc: 6ed2 ldr r2, [r2, #108] ; 0x6c
- 8002ece: 4610 mov r0, r2
- 8002ed0: 4798 blx r3
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8002ed2: e00e b.n 8002ef2 <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8002ed4: 6878 ldr r0, [r7, #4]
- 8002ed6: f7fd fca7 bl 8000828 <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8002eda: e00a b.n 8002ef2 <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8002edc: 6878 ldr r0, [r7, #4]
- 8002ede: f7fd fca3 bl 8000828 <HAL_UART_ErrorCallback>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8002ee2: e006 b.n 8002ef2 <HAL_UART_IRQHandler+0x1da>
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 8002ee4: 6878 ldr r0, [r7, #4]
- 8002ee6: f7fd fc9f bl 8000828 <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8002eea: 687b ldr r3, [r7, #4]
- 8002eec: 2200 movs r2, #0
- 8002eee: 67da str r2, [r3, #124] ; 0x7c
- }
- }
- return;
- 8002ef0: e025 b.n 8002f3e <HAL_UART_IRQHandler+0x226>
- if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
- 8002ef2: bf00 nop
- return;
- 8002ef4: e023 b.n 8002f3e <HAL_UART_IRQHandler+0x226>
-
- } /* End if some error occurs */
-
- /* UART in mode Transmitter ------------------------------------------------*/
- if (((isrflags & USART_ISR_TXE) != 0U)
- 8002ef6: 69fb ldr r3, [r7, #28]
- 8002ef8: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002efc: 2b00 cmp r3, #0
- 8002efe: d00d beq.n 8002f1c <HAL_UART_IRQHandler+0x204>
- && ((cr1its & USART_CR1_TXEIE) != 0U))
- 8002f00: 69bb ldr r3, [r7, #24]
- 8002f02: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002f06: 2b00 cmp r3, #0
- 8002f08: d008 beq.n 8002f1c <HAL_UART_IRQHandler+0x204>
- {
- if (huart->TxISR != NULL)
- 8002f0a: 687b ldr r3, [r7, #4]
- 8002f0c: 6e5b ldr r3, [r3, #100] ; 0x64
- 8002f0e: 2b00 cmp r3, #0
- 8002f10: d017 beq.n 8002f42 <HAL_UART_IRQHandler+0x22a>
- {
- huart->TxISR(huart);
- 8002f12: 687b ldr r3, [r7, #4]
- 8002f14: 6e5b ldr r3, [r3, #100] ; 0x64
- 8002f16: 6878 ldr r0, [r7, #4]
- 8002f18: 4798 blx r3
- }
- return;
- 8002f1a: e012 b.n 8002f42 <HAL_UART_IRQHandler+0x22a>
- }
-
- /* UART in mode Transmitter (transmission end) -----------------------------*/
- if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
- 8002f1c: 69fb ldr r3, [r7, #28]
- 8002f1e: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002f22: 2b00 cmp r3, #0
- 8002f24: d00e beq.n 8002f44 <HAL_UART_IRQHandler+0x22c>
- 8002f26: 69bb ldr r3, [r7, #24]
- 8002f28: f003 0340 and.w r3, r3, #64 ; 0x40
- 8002f2c: 2b00 cmp r3, #0
- 8002f2e: d009 beq.n 8002f44 <HAL_UART_IRQHandler+0x22c>
- {
- UART_EndTransmit_IT(huart);
- 8002f30: 6878 ldr r0, [r7, #4]
- 8002f32: f000 fc0a bl 800374a <UART_EndTransmit_IT>
- return;
- 8002f36: bf00 nop
- 8002f38: e004 b.n 8002f44 <HAL_UART_IRQHandler+0x22c>
- return;
- 8002f3a: bf00 nop
- 8002f3c: e002 b.n 8002f44 <HAL_UART_IRQHandler+0x22c>
- return;
- 8002f3e: bf00 nop
- 8002f40: e000 b.n 8002f44 <HAL_UART_IRQHandler+0x22c>
- return;
- 8002f42: bf00 nop
- }
-
-}
- 8002f44: 3720 adds r7, #32
- 8002f46: 46bd mov sp, r7
- 8002f48: bd80 pop {r7, pc}
- 8002f4a: bf00 nop
- 8002f4c: 0800371f .word 0x0800371f
-
-08002f50 <HAL_UART_TxCpltCallback>:
- * @brief Tx Transfer completed callback.
- * @param huart UART handle.
- * @retval None
- */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
- 8002f50: b480 push {r7}
- 8002f52: b083 sub sp, #12
- 8002f54: af00 add r7, sp, #0
- 8002f56: 6078 str r0, [r7, #4]
- UNUSED(huart);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file.
- */
-}
- 8002f58: bf00 nop
- 8002f5a: 370c adds r7, #12
- 8002f5c: 46bd mov sp, r7
- 8002f5e: f85d 7b04 ldr.w r7, [sp], #4
- 8002f62: 4770 bx lr
-
-08002f64 <UART_SetConfig>:
- * @brief Configure the UART peripheral.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- 8002f64: b580 push {r7, lr}
- 8002f66: b088 sub sp, #32
- 8002f68: af00 add r7, sp, #0
- 8002f6a: 6078 str r0, [r7, #4]
- uint32_t tmpreg;
- uint16_t brrtemp;
- UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv = 0x00000000U;
- 8002f6c: 2300 movs r3, #0
- 8002f6e: 61bb str r3, [r7, #24]
- HAL_StatusTypeDef ret = HAL_OK;
- 8002f70: 2300 movs r3, #0
- 8002f72: 75fb strb r3, [r7, #23]
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 8002f74: 687b ldr r3, [r7, #4]
- 8002f76: 689a ldr r2, [r3, #8]
- 8002f78: 687b ldr r3, [r7, #4]
- 8002f7a: 691b ldr r3, [r3, #16]
- 8002f7c: 431a orrs r2, r3
- 8002f7e: 687b ldr r3, [r7, #4]
- 8002f80: 695b ldr r3, [r3, #20]
- 8002f82: 431a orrs r2, r3
- 8002f84: 687b ldr r3, [r7, #4]
- 8002f86: 69db ldr r3, [r3, #28]
- 8002f88: 4313 orrs r3, r2
- 8002f8a: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 8002f8c: 687b ldr r3, [r7, #4]
- 8002f8e: 681b ldr r3, [r3, #0]
- 8002f90: 681a ldr r2, [r3, #0]
- 8002f92: 4bb1 ldr r3, [pc, #708] ; (8003258 <UART_SetConfig+0x2f4>)
- 8002f94: 4013 ands r3, r2
- 8002f96: 687a ldr r2, [r7, #4]
- 8002f98: 6812 ldr r2, [r2, #0]
- 8002f9a: 6939 ldr r1, [r7, #16]
- 8002f9c: 430b orrs r3, r1
- 8002f9e: 6013 str r3, [r2, #0]
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8002fa0: 687b ldr r3, [r7, #4]
- 8002fa2: 681b ldr r3, [r3, #0]
- 8002fa4: 685b ldr r3, [r3, #4]
- 8002fa6: f423 5140 bic.w r1, r3, #12288 ; 0x3000
- 8002faa: 687b ldr r3, [r7, #4]
- 8002fac: 68da ldr r2, [r3, #12]
- 8002fae: 687b ldr r3, [r7, #4]
- 8002fb0: 681b ldr r3, [r3, #0]
- 8002fb2: 430a orrs r2, r1
- 8002fb4: 605a str r2, [r3, #4]
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling (not applicable to LPUART) */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8002fb6: 687b ldr r3, [r7, #4]
- 8002fb8: 699b ldr r3, [r3, #24]
- 8002fba: 613b str r3, [r7, #16]
-
- tmpreg |= huart->Init.OneBitSampling;
- 8002fbc: 687b ldr r3, [r7, #4]
- 8002fbe: 6a1b ldr r3, [r3, #32]
- 8002fc0: 693a ldr r2, [r7, #16]
- 8002fc2: 4313 orrs r3, r2
- 8002fc4: 613b str r3, [r7, #16]
- MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8002fc6: 687b ldr r3, [r7, #4]
- 8002fc8: 681b ldr r3, [r3, #0]
- 8002fca: 689b ldr r3, [r3, #8]
- 8002fcc: f423 6130 bic.w r1, r3, #2816 ; 0xb00
- 8002fd0: 687b ldr r3, [r7, #4]
- 8002fd2: 681b ldr r3, [r3, #0]
- 8002fd4: 693a ldr r2, [r7, #16]
- 8002fd6: 430a orrs r2, r1
- 8002fd8: 609a str r2, [r3, #8]
-
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- UART_GETCLOCKSOURCE(huart, clocksource);
- 8002fda: 687b ldr r3, [r7, #4]
- 8002fdc: 681b ldr r3, [r3, #0]
- 8002fde: 4a9f ldr r2, [pc, #636] ; (800325c <UART_SetConfig+0x2f8>)
- 8002fe0: 4293 cmp r3, r2
- 8002fe2: d121 bne.n 8003028 <UART_SetConfig+0xc4>
- 8002fe4: 4b9e ldr r3, [pc, #632] ; (8003260 <UART_SetConfig+0x2fc>)
- 8002fe6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002fea: f003 0303 and.w r3, r3, #3
- 8002fee: 2b03 cmp r3, #3
- 8002ff0: d816 bhi.n 8003020 <UART_SetConfig+0xbc>
- 8002ff2: a201 add r2, pc, #4 ; (adr r2, 8002ff8 <UART_SetConfig+0x94>)
- 8002ff4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8002ff8: 08003009 .word 0x08003009
- 8002ffc: 08003015 .word 0x08003015
- 8003000: 0800300f .word 0x0800300f
- 8003004: 0800301b .word 0x0800301b
- 8003008: 2301 movs r3, #1
- 800300a: 77fb strb r3, [r7, #31]
- 800300c: e151 b.n 80032b2 <UART_SetConfig+0x34e>
- 800300e: 2302 movs r3, #2
- 8003010: 77fb strb r3, [r7, #31]
- 8003012: e14e b.n 80032b2 <UART_SetConfig+0x34e>
- 8003014: 2304 movs r3, #4
- 8003016: 77fb strb r3, [r7, #31]
- 8003018: e14b b.n 80032b2 <UART_SetConfig+0x34e>
- 800301a: 2308 movs r3, #8
- 800301c: 77fb strb r3, [r7, #31]
- 800301e: e148 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003020: 2310 movs r3, #16
- 8003022: 77fb strb r3, [r7, #31]
- 8003024: bf00 nop
- 8003026: e144 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003028: 687b ldr r3, [r7, #4]
- 800302a: 681b ldr r3, [r3, #0]
- 800302c: 4a8d ldr r2, [pc, #564] ; (8003264 <UART_SetConfig+0x300>)
- 800302e: 4293 cmp r3, r2
- 8003030: d134 bne.n 800309c <UART_SetConfig+0x138>
- 8003032: 4b8b ldr r3, [pc, #556] ; (8003260 <UART_SetConfig+0x2fc>)
- 8003034: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003038: f003 030c and.w r3, r3, #12
- 800303c: 2b0c cmp r3, #12
- 800303e: d829 bhi.n 8003094 <UART_SetConfig+0x130>
- 8003040: a201 add r2, pc, #4 ; (adr r2, 8003048 <UART_SetConfig+0xe4>)
- 8003042: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8003046: bf00 nop
- 8003048: 0800307d .word 0x0800307d
- 800304c: 08003095 .word 0x08003095
- 8003050: 08003095 .word 0x08003095
- 8003054: 08003095 .word 0x08003095
- 8003058: 08003089 .word 0x08003089
- 800305c: 08003095 .word 0x08003095
- 8003060: 08003095 .word 0x08003095
- 8003064: 08003095 .word 0x08003095
- 8003068: 08003083 .word 0x08003083
- 800306c: 08003095 .word 0x08003095
- 8003070: 08003095 .word 0x08003095
- 8003074: 08003095 .word 0x08003095
- 8003078: 0800308f .word 0x0800308f
- 800307c: 2300 movs r3, #0
- 800307e: 77fb strb r3, [r7, #31]
- 8003080: e117 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003082: 2302 movs r3, #2
- 8003084: 77fb strb r3, [r7, #31]
- 8003086: e114 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003088: 2304 movs r3, #4
- 800308a: 77fb strb r3, [r7, #31]
- 800308c: e111 b.n 80032b2 <UART_SetConfig+0x34e>
- 800308e: 2308 movs r3, #8
- 8003090: 77fb strb r3, [r7, #31]
- 8003092: e10e b.n 80032b2 <UART_SetConfig+0x34e>
- 8003094: 2310 movs r3, #16
- 8003096: 77fb strb r3, [r7, #31]
- 8003098: bf00 nop
- 800309a: e10a b.n 80032b2 <UART_SetConfig+0x34e>
- 800309c: 687b ldr r3, [r7, #4]
- 800309e: 681b ldr r3, [r3, #0]
- 80030a0: 4a71 ldr r2, [pc, #452] ; (8003268 <UART_SetConfig+0x304>)
- 80030a2: 4293 cmp r3, r2
- 80030a4: d120 bne.n 80030e8 <UART_SetConfig+0x184>
- 80030a6: 4b6e ldr r3, [pc, #440] ; (8003260 <UART_SetConfig+0x2fc>)
- 80030a8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80030ac: f003 0330 and.w r3, r3, #48 ; 0x30
- 80030b0: 2b10 cmp r3, #16
- 80030b2: d00f beq.n 80030d4 <UART_SetConfig+0x170>
- 80030b4: 2b10 cmp r3, #16
- 80030b6: d802 bhi.n 80030be <UART_SetConfig+0x15a>
- 80030b8: 2b00 cmp r3, #0
- 80030ba: d005 beq.n 80030c8 <UART_SetConfig+0x164>
- 80030bc: e010 b.n 80030e0 <UART_SetConfig+0x17c>
- 80030be: 2b20 cmp r3, #32
- 80030c0: d005 beq.n 80030ce <UART_SetConfig+0x16a>
- 80030c2: 2b30 cmp r3, #48 ; 0x30
- 80030c4: d009 beq.n 80030da <UART_SetConfig+0x176>
- 80030c6: e00b b.n 80030e0 <UART_SetConfig+0x17c>
- 80030c8: 2300 movs r3, #0
- 80030ca: 77fb strb r3, [r7, #31]
- 80030cc: e0f1 b.n 80032b2 <UART_SetConfig+0x34e>
- 80030ce: 2302 movs r3, #2
- 80030d0: 77fb strb r3, [r7, #31]
- 80030d2: e0ee b.n 80032b2 <UART_SetConfig+0x34e>
- 80030d4: 2304 movs r3, #4
- 80030d6: 77fb strb r3, [r7, #31]
- 80030d8: e0eb b.n 80032b2 <UART_SetConfig+0x34e>
- 80030da: 2308 movs r3, #8
- 80030dc: 77fb strb r3, [r7, #31]
- 80030de: e0e8 b.n 80032b2 <UART_SetConfig+0x34e>
- 80030e0: 2310 movs r3, #16
- 80030e2: 77fb strb r3, [r7, #31]
- 80030e4: bf00 nop
- 80030e6: e0e4 b.n 80032b2 <UART_SetConfig+0x34e>
- 80030e8: 687b ldr r3, [r7, #4]
- 80030ea: 681b ldr r3, [r3, #0]
- 80030ec: 4a5f ldr r2, [pc, #380] ; (800326c <UART_SetConfig+0x308>)
- 80030ee: 4293 cmp r3, r2
- 80030f0: d120 bne.n 8003134 <UART_SetConfig+0x1d0>
- 80030f2: 4b5b ldr r3, [pc, #364] ; (8003260 <UART_SetConfig+0x2fc>)
- 80030f4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80030f8: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 80030fc: 2b40 cmp r3, #64 ; 0x40
- 80030fe: d00f beq.n 8003120 <UART_SetConfig+0x1bc>
- 8003100: 2b40 cmp r3, #64 ; 0x40
- 8003102: d802 bhi.n 800310a <UART_SetConfig+0x1a6>
- 8003104: 2b00 cmp r3, #0
- 8003106: d005 beq.n 8003114 <UART_SetConfig+0x1b0>
- 8003108: e010 b.n 800312c <UART_SetConfig+0x1c8>
- 800310a: 2b80 cmp r3, #128 ; 0x80
- 800310c: d005 beq.n 800311a <UART_SetConfig+0x1b6>
- 800310e: 2bc0 cmp r3, #192 ; 0xc0
- 8003110: d009 beq.n 8003126 <UART_SetConfig+0x1c2>
- 8003112: e00b b.n 800312c <UART_SetConfig+0x1c8>
- 8003114: 2300 movs r3, #0
- 8003116: 77fb strb r3, [r7, #31]
- 8003118: e0cb b.n 80032b2 <UART_SetConfig+0x34e>
- 800311a: 2302 movs r3, #2
- 800311c: 77fb strb r3, [r7, #31]
- 800311e: e0c8 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003120: 2304 movs r3, #4
- 8003122: 77fb strb r3, [r7, #31]
- 8003124: e0c5 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003126: 2308 movs r3, #8
- 8003128: 77fb strb r3, [r7, #31]
- 800312a: e0c2 b.n 80032b2 <UART_SetConfig+0x34e>
- 800312c: 2310 movs r3, #16
- 800312e: 77fb strb r3, [r7, #31]
- 8003130: bf00 nop
- 8003132: e0be b.n 80032b2 <UART_SetConfig+0x34e>
- 8003134: 687b ldr r3, [r7, #4]
- 8003136: 681b ldr r3, [r3, #0]
- 8003138: 4a4d ldr r2, [pc, #308] ; (8003270 <UART_SetConfig+0x30c>)
- 800313a: 4293 cmp r3, r2
- 800313c: d124 bne.n 8003188 <UART_SetConfig+0x224>
- 800313e: 4b48 ldr r3, [pc, #288] ; (8003260 <UART_SetConfig+0x2fc>)
- 8003140: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003144: f403 7340 and.w r3, r3, #768 ; 0x300
- 8003148: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 800314c: d012 beq.n 8003174 <UART_SetConfig+0x210>
- 800314e: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 8003152: d802 bhi.n 800315a <UART_SetConfig+0x1f6>
- 8003154: 2b00 cmp r3, #0
- 8003156: d007 beq.n 8003168 <UART_SetConfig+0x204>
- 8003158: e012 b.n 8003180 <UART_SetConfig+0x21c>
- 800315a: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 800315e: d006 beq.n 800316e <UART_SetConfig+0x20a>
- 8003160: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8003164: d009 beq.n 800317a <UART_SetConfig+0x216>
- 8003166: e00b b.n 8003180 <UART_SetConfig+0x21c>
- 8003168: 2300 movs r3, #0
- 800316a: 77fb strb r3, [r7, #31]
- 800316c: e0a1 b.n 80032b2 <UART_SetConfig+0x34e>
- 800316e: 2302 movs r3, #2
- 8003170: 77fb strb r3, [r7, #31]
- 8003172: e09e b.n 80032b2 <UART_SetConfig+0x34e>
- 8003174: 2304 movs r3, #4
- 8003176: 77fb strb r3, [r7, #31]
- 8003178: e09b b.n 80032b2 <UART_SetConfig+0x34e>
- 800317a: 2308 movs r3, #8
- 800317c: 77fb strb r3, [r7, #31]
- 800317e: e098 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003180: 2310 movs r3, #16
- 8003182: 77fb strb r3, [r7, #31]
- 8003184: bf00 nop
- 8003186: e094 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003188: 687b ldr r3, [r7, #4]
- 800318a: 681b ldr r3, [r3, #0]
- 800318c: 4a39 ldr r2, [pc, #228] ; (8003274 <UART_SetConfig+0x310>)
- 800318e: 4293 cmp r3, r2
- 8003190: d124 bne.n 80031dc <UART_SetConfig+0x278>
- 8003192: 4b33 ldr r3, [pc, #204] ; (8003260 <UART_SetConfig+0x2fc>)
- 8003194: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003198: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 800319c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 80031a0: d012 beq.n 80031c8 <UART_SetConfig+0x264>
- 80031a2: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 80031a6: d802 bhi.n 80031ae <UART_SetConfig+0x24a>
- 80031a8: 2b00 cmp r3, #0
- 80031aa: d007 beq.n 80031bc <UART_SetConfig+0x258>
- 80031ac: e012 b.n 80031d4 <UART_SetConfig+0x270>
- 80031ae: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 80031b2: d006 beq.n 80031c2 <UART_SetConfig+0x25e>
- 80031b4: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 80031b8: d009 beq.n 80031ce <UART_SetConfig+0x26a>
- 80031ba: e00b b.n 80031d4 <UART_SetConfig+0x270>
- 80031bc: 2301 movs r3, #1
- 80031be: 77fb strb r3, [r7, #31]
- 80031c0: e077 b.n 80032b2 <UART_SetConfig+0x34e>
- 80031c2: 2302 movs r3, #2
- 80031c4: 77fb strb r3, [r7, #31]
- 80031c6: e074 b.n 80032b2 <UART_SetConfig+0x34e>
- 80031c8: 2304 movs r3, #4
- 80031ca: 77fb strb r3, [r7, #31]
- 80031cc: e071 b.n 80032b2 <UART_SetConfig+0x34e>
- 80031ce: 2308 movs r3, #8
- 80031d0: 77fb strb r3, [r7, #31]
- 80031d2: e06e b.n 80032b2 <UART_SetConfig+0x34e>
- 80031d4: 2310 movs r3, #16
- 80031d6: 77fb strb r3, [r7, #31]
- 80031d8: bf00 nop
- 80031da: e06a b.n 80032b2 <UART_SetConfig+0x34e>
- 80031dc: 687b ldr r3, [r7, #4]
- 80031de: 681b ldr r3, [r3, #0]
- 80031e0: 4a25 ldr r2, [pc, #148] ; (8003278 <UART_SetConfig+0x314>)
- 80031e2: 4293 cmp r3, r2
- 80031e4: d124 bne.n 8003230 <UART_SetConfig+0x2cc>
- 80031e6: 4b1e ldr r3, [pc, #120] ; (8003260 <UART_SetConfig+0x2fc>)
- 80031e8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80031ec: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 80031f0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80031f4: d012 beq.n 800321c <UART_SetConfig+0x2b8>
- 80031f6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 80031fa: d802 bhi.n 8003202 <UART_SetConfig+0x29e>
- 80031fc: 2b00 cmp r3, #0
- 80031fe: d007 beq.n 8003210 <UART_SetConfig+0x2ac>
- 8003200: e012 b.n 8003228 <UART_SetConfig+0x2c4>
- 8003202: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 8003206: d006 beq.n 8003216 <UART_SetConfig+0x2b2>
- 8003208: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 800320c: d009 beq.n 8003222 <UART_SetConfig+0x2be>
- 800320e: e00b b.n 8003228 <UART_SetConfig+0x2c4>
- 8003210: 2300 movs r3, #0
- 8003212: 77fb strb r3, [r7, #31]
- 8003214: e04d b.n 80032b2 <UART_SetConfig+0x34e>
- 8003216: 2302 movs r3, #2
- 8003218: 77fb strb r3, [r7, #31]
- 800321a: e04a b.n 80032b2 <UART_SetConfig+0x34e>
- 800321c: 2304 movs r3, #4
- 800321e: 77fb strb r3, [r7, #31]
- 8003220: e047 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003222: 2308 movs r3, #8
- 8003224: 77fb strb r3, [r7, #31]
- 8003226: e044 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003228: 2310 movs r3, #16
- 800322a: 77fb strb r3, [r7, #31]
- 800322c: bf00 nop
- 800322e: e040 b.n 80032b2 <UART_SetConfig+0x34e>
- 8003230: 687b ldr r3, [r7, #4]
- 8003232: 681b ldr r3, [r3, #0]
- 8003234: 4a11 ldr r2, [pc, #68] ; (800327c <UART_SetConfig+0x318>)
- 8003236: 4293 cmp r3, r2
- 8003238: d139 bne.n 80032ae <UART_SetConfig+0x34a>
- 800323a: 4b09 ldr r3, [pc, #36] ; (8003260 <UART_SetConfig+0x2fc>)
- 800323c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8003240: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8003244: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 8003248: d027 beq.n 800329a <UART_SetConfig+0x336>
- 800324a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 800324e: d817 bhi.n 8003280 <UART_SetConfig+0x31c>
- 8003250: 2b00 cmp r3, #0
- 8003252: d01c beq.n 800328e <UART_SetConfig+0x32a>
- 8003254: e027 b.n 80032a6 <UART_SetConfig+0x342>
- 8003256: bf00 nop
- 8003258: efff69f3 .word 0xefff69f3
- 800325c: 40011000 .word 0x40011000
- 8003260: 40023800 .word 0x40023800
- 8003264: 40004400 .word 0x40004400
- 8003268: 40004800 .word 0x40004800
- 800326c: 40004c00 .word 0x40004c00
- 8003270: 40005000 .word 0x40005000
- 8003274: 40011400 .word 0x40011400
- 8003278: 40007800 .word 0x40007800
- 800327c: 40007c00 .word 0x40007c00
- 8003280: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8003284: d006 beq.n 8003294 <UART_SetConfig+0x330>
- 8003286: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 800328a: d009 beq.n 80032a0 <UART_SetConfig+0x33c>
- 800328c: e00b b.n 80032a6 <UART_SetConfig+0x342>
- 800328e: 2300 movs r3, #0
- 8003290: 77fb strb r3, [r7, #31]
- 8003292: e00e b.n 80032b2 <UART_SetConfig+0x34e>
- 8003294: 2302 movs r3, #2
- 8003296: 77fb strb r3, [r7, #31]
- 8003298: e00b b.n 80032b2 <UART_SetConfig+0x34e>
- 800329a: 2304 movs r3, #4
- 800329c: 77fb strb r3, [r7, #31]
- 800329e: e008 b.n 80032b2 <UART_SetConfig+0x34e>
- 80032a0: 2308 movs r3, #8
- 80032a2: 77fb strb r3, [r7, #31]
- 80032a4: e005 b.n 80032b2 <UART_SetConfig+0x34e>
- 80032a6: 2310 movs r3, #16
- 80032a8: 77fb strb r3, [r7, #31]
- 80032aa: bf00 nop
- 80032ac: e001 b.n 80032b2 <UART_SetConfig+0x34e>
- 80032ae: 2310 movs r3, #16
- 80032b0: 77fb strb r3, [r7, #31]
-
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 80032b2: 687b ldr r3, [r7, #4]
- 80032b4: 69db ldr r3, [r3, #28]
- 80032b6: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 80032ba: d17c bne.n 80033b6 <UART_SetConfig+0x452>
- {
- switch (clocksource)
- 80032bc: 7ffb ldrb r3, [r7, #31]
- 80032be: 2b08 cmp r3, #8
- 80032c0: d859 bhi.n 8003376 <UART_SetConfig+0x412>
- 80032c2: a201 add r2, pc, #4 ; (adr r2, 80032c8 <UART_SetConfig+0x364>)
- 80032c4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 80032c8: 080032ed .word 0x080032ed
- 80032cc: 0800330b .word 0x0800330b
- 80032d0: 08003329 .word 0x08003329
- 80032d4: 08003377 .word 0x08003377
- 80032d8: 08003341 .word 0x08003341
- 80032dc: 08003377 .word 0x08003377
- 80032e0: 08003377 .word 0x08003377
- 80032e4: 08003377 .word 0x08003377
- 80032e8: 0800335f .word 0x0800335f
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 80032ec: f7fe fb38 bl 8001960 <HAL_RCC_GetPCLK1Freq>
- 80032f0: 4603 mov r3, r0
- 80032f2: 005a lsls r2, r3, #1
- 80032f4: 687b ldr r3, [r7, #4]
- 80032f6: 685b ldr r3, [r3, #4]
- 80032f8: 085b lsrs r3, r3, #1
- 80032fa: 441a add r2, r3
- 80032fc: 687b ldr r3, [r7, #4]
- 80032fe: 685b ldr r3, [r3, #4]
- 8003300: fbb2 f3f3 udiv r3, r2, r3
- 8003304: b29b uxth r3, r3
- 8003306: 61bb str r3, [r7, #24]
- break;
- 8003308: e038 b.n 800337c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 800330a: f7fe fb3d bl 8001988 <HAL_RCC_GetPCLK2Freq>
- 800330e: 4603 mov r3, r0
- 8003310: 005a lsls r2, r3, #1
- 8003312: 687b ldr r3, [r7, #4]
- 8003314: 685b ldr r3, [r3, #4]
- 8003316: 085b lsrs r3, r3, #1
- 8003318: 441a add r2, r3
- 800331a: 687b ldr r3, [r7, #4]
- 800331c: 685b ldr r3, [r3, #4]
- 800331e: fbb2 f3f3 udiv r3, r2, r3
- 8003322: b29b uxth r3, r3
- 8003324: 61bb str r3, [r7, #24]
- break;
- 8003326: e029 b.n 800337c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8003328: 687b ldr r3, [r7, #4]
- 800332a: 685b ldr r3, [r3, #4]
- 800332c: 085a lsrs r2, r3, #1
- 800332e: 4b5d ldr r3, [pc, #372] ; (80034a4 <UART_SetConfig+0x540>)
- 8003330: 4413 add r3, r2
- 8003332: 687a ldr r2, [r7, #4]
- 8003334: 6852 ldr r2, [r2, #4]
- 8003336: fbb3 f3f2 udiv r3, r3, r2
- 800333a: b29b uxth r3, r3
- 800333c: 61bb str r3, [r7, #24]
- break;
- 800333e: e01d b.n 800337c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8003340: f7fe fa50 bl 80017e4 <HAL_RCC_GetSysClockFreq>
- 8003344: 4603 mov r3, r0
- 8003346: 005a lsls r2, r3, #1
- 8003348: 687b ldr r3, [r7, #4]
- 800334a: 685b ldr r3, [r3, #4]
- 800334c: 085b lsrs r3, r3, #1
- 800334e: 441a add r2, r3
- 8003350: 687b ldr r3, [r7, #4]
- 8003352: 685b ldr r3, [r3, #4]
- 8003354: fbb2 f3f3 udiv r3, r2, r3
- 8003358: b29b uxth r3, r3
- 800335a: 61bb str r3, [r7, #24]
- break;
- 800335c: e00e b.n 800337c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 800335e: 687b ldr r3, [r7, #4]
- 8003360: 685b ldr r3, [r3, #4]
- 8003362: 085b lsrs r3, r3, #1
- 8003364: f503 3280 add.w r2, r3, #65536 ; 0x10000
- 8003368: 687b ldr r3, [r7, #4]
- 800336a: 685b ldr r3, [r3, #4]
- 800336c: fbb2 f3f3 udiv r3, r2, r3
- 8003370: b29b uxth r3, r3
- 8003372: 61bb str r3, [r7, #24]
- break;
- 8003374: e002 b.n 800337c <UART_SetConfig+0x418>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 8003376: 2301 movs r3, #1
- 8003378: 75fb strb r3, [r7, #23]
- break;
- 800337a: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 800337c: 69bb ldr r3, [r7, #24]
- 800337e: 2b0f cmp r3, #15
- 8003380: d916 bls.n 80033b0 <UART_SetConfig+0x44c>
- 8003382: 69bb ldr r3, [r7, #24]
- 8003384: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8003388: d212 bcs.n 80033b0 <UART_SetConfig+0x44c>
- {
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 800338a: 69bb ldr r3, [r7, #24]
- 800338c: b29b uxth r3, r3
- 800338e: f023 030f bic.w r3, r3, #15
- 8003392: 81fb strh r3, [r7, #14]
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8003394: 69bb ldr r3, [r7, #24]
- 8003396: 085b lsrs r3, r3, #1
- 8003398: b29b uxth r3, r3
- 800339a: f003 0307 and.w r3, r3, #7
- 800339e: b29a uxth r2, r3
- 80033a0: 89fb ldrh r3, [r7, #14]
- 80033a2: 4313 orrs r3, r2
- 80033a4: 81fb strh r3, [r7, #14]
- huart->Instance->BRR = brrtemp;
- 80033a6: 687b ldr r3, [r7, #4]
- 80033a8: 681b ldr r3, [r3, #0]
- 80033aa: 89fa ldrh r2, [r7, #14]
- 80033ac: 60da str r2, [r3, #12]
- 80033ae: e06e b.n 800348e <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 80033b0: 2301 movs r3, #1
- 80033b2: 75fb strb r3, [r7, #23]
- 80033b4: e06b b.n 800348e <UART_SetConfig+0x52a>
- }
- }
- else
- {
- switch (clocksource)
- 80033b6: 7ffb ldrb r3, [r7, #31]
- 80033b8: 2b08 cmp r3, #8
- 80033ba: d857 bhi.n 800346c <UART_SetConfig+0x508>
- 80033bc: a201 add r2, pc, #4 ; (adr r2, 80033c4 <UART_SetConfig+0x460>)
- 80033be: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 80033c2: bf00 nop
- 80033c4: 080033e9 .word 0x080033e9
- 80033c8: 08003405 .word 0x08003405
- 80033cc: 08003421 .word 0x08003421
- 80033d0: 0800346d .word 0x0800346d
- 80033d4: 08003439 .word 0x08003439
- 80033d8: 0800346d .word 0x0800346d
- 80033dc: 0800346d .word 0x0800346d
- 80033e0: 0800346d .word 0x0800346d
- 80033e4: 08003455 .word 0x08003455
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 80033e8: f7fe faba bl 8001960 <HAL_RCC_GetPCLK1Freq>
- 80033ec: 4602 mov r2, r0
- 80033ee: 687b ldr r3, [r7, #4]
- 80033f0: 685b ldr r3, [r3, #4]
- 80033f2: 085b lsrs r3, r3, #1
- 80033f4: 441a add r2, r3
- 80033f6: 687b ldr r3, [r7, #4]
- 80033f8: 685b ldr r3, [r3, #4]
- 80033fa: fbb2 f3f3 udiv r3, r2, r3
- 80033fe: b29b uxth r3, r3
- 8003400: 61bb str r3, [r7, #24]
- break;
- 8003402: e036 b.n 8003472 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8003404: f7fe fac0 bl 8001988 <HAL_RCC_GetPCLK2Freq>
- 8003408: 4602 mov r2, r0
- 800340a: 687b ldr r3, [r7, #4]
- 800340c: 685b ldr r3, [r3, #4]
- 800340e: 085b lsrs r3, r3, #1
- 8003410: 441a add r2, r3
- 8003412: 687b ldr r3, [r7, #4]
- 8003414: 685b ldr r3, [r3, #4]
- 8003416: fbb2 f3f3 udiv r3, r2, r3
- 800341a: b29b uxth r3, r3
- 800341c: 61bb str r3, [r7, #24]
- break;
- 800341e: e028 b.n 8003472 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 8003420: 687b ldr r3, [r7, #4]
- 8003422: 685b ldr r3, [r3, #4]
- 8003424: 085a lsrs r2, r3, #1
- 8003426: 4b20 ldr r3, [pc, #128] ; (80034a8 <UART_SetConfig+0x544>)
- 8003428: 4413 add r3, r2
- 800342a: 687a ldr r2, [r7, #4]
- 800342c: 6852 ldr r2, [r2, #4]
- 800342e: fbb3 f3f2 udiv r3, r3, r2
- 8003432: b29b uxth r3, r3
- 8003434: 61bb str r3, [r7, #24]
- break;
- 8003436: e01c b.n 8003472 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8003438: f7fe f9d4 bl 80017e4 <HAL_RCC_GetSysClockFreq>
- 800343c: 4602 mov r2, r0
- 800343e: 687b ldr r3, [r7, #4]
- 8003440: 685b ldr r3, [r3, #4]
- 8003442: 085b lsrs r3, r3, #1
- 8003444: 441a add r2, r3
- 8003446: 687b ldr r3, [r7, #4]
- 8003448: 685b ldr r3, [r3, #4]
- 800344a: fbb2 f3f3 udiv r3, r2, r3
- 800344e: b29b uxth r3, r3
- 8003450: 61bb str r3, [r7, #24]
- break;
- 8003452: e00e b.n 8003472 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 8003454: 687b ldr r3, [r7, #4]
- 8003456: 685b ldr r3, [r3, #4]
- 8003458: 085b lsrs r3, r3, #1
- 800345a: f503 4200 add.w r2, r3, #32768 ; 0x8000
- 800345e: 687b ldr r3, [r7, #4]
- 8003460: 685b ldr r3, [r3, #4]
- 8003462: fbb2 f3f3 udiv r3, r2, r3
- 8003466: b29b uxth r3, r3
- 8003468: 61bb str r3, [r7, #24]
- break;
- 800346a: e002 b.n 8003472 <UART_SetConfig+0x50e>
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- 800346c: 2301 movs r3, #1
- 800346e: 75fb strb r3, [r7, #23]
- break;
- 8003470: bf00 nop
- }
-
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8003472: 69bb ldr r3, [r7, #24]
- 8003474: 2b0f cmp r3, #15
- 8003476: d908 bls.n 800348a <UART_SetConfig+0x526>
- 8003478: 69bb ldr r3, [r7, #24]
- 800347a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 800347e: d204 bcs.n 800348a <UART_SetConfig+0x526>
- {
- huart->Instance->BRR = usartdiv;
- 8003480: 687b ldr r3, [r7, #4]
- 8003482: 681b ldr r3, [r3, #0]
- 8003484: 69ba ldr r2, [r7, #24]
- 8003486: 60da str r2, [r3, #12]
- 8003488: e001 b.n 800348e <UART_SetConfig+0x52a>
- }
- else
- {
- ret = HAL_ERROR;
- 800348a: 2301 movs r3, #1
- 800348c: 75fb strb r3, [r7, #23]
- }
- }
-
-
- /* Clear ISR function pointers */
- huart->RxISR = NULL;
- 800348e: 687b ldr r3, [r7, #4]
- 8003490: 2200 movs r2, #0
- 8003492: 661a str r2, [r3, #96] ; 0x60
- huart->TxISR = NULL;
- 8003494: 687b ldr r3, [r7, #4]
- 8003496: 2200 movs r2, #0
- 8003498: 665a str r2, [r3, #100] ; 0x64
-
- return ret;
- 800349a: 7dfb ldrb r3, [r7, #23]
-}
- 800349c: 4618 mov r0, r3
- 800349e: 3720 adds r7, #32
- 80034a0: 46bd mov sp, r7
- 80034a2: bd80 pop {r7, pc}
- 80034a4: 01e84800 .word 0x01e84800
- 80034a8: 00f42400 .word 0x00f42400
-
-080034ac <UART_AdvFeatureConfig>:
- * @brief Configure the UART peripheral advanced features.
- * @param huart UART handle.
- * @retval None
- */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- 80034ac: b480 push {r7}
- 80034ae: b083 sub sp, #12
- 80034b0: af00 add r7, sp, #0
- 80034b2: 6078 str r0, [r7, #4]
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 80034b4: 687b ldr r3, [r7, #4]
- 80034b6: 6a5b ldr r3, [r3, #36] ; 0x24
- 80034b8: f003 0301 and.w r3, r3, #1
- 80034bc: 2b00 cmp r3, #0
- 80034be: d00a beq.n 80034d6 <UART_AdvFeatureConfig+0x2a>
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 80034c0: 687b ldr r3, [r7, #4]
- 80034c2: 681b ldr r3, [r3, #0]
- 80034c4: 685b ldr r3, [r3, #4]
- 80034c6: f423 3100 bic.w r1, r3, #131072 ; 0x20000
- 80034ca: 687b ldr r3, [r7, #4]
- 80034cc: 6a9a ldr r2, [r3, #40] ; 0x28
- 80034ce: 687b ldr r3, [r7, #4]
- 80034d0: 681b ldr r3, [r3, #0]
- 80034d2: 430a orrs r2, r1
- 80034d4: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 80034d6: 687b ldr r3, [r7, #4]
- 80034d8: 6a5b ldr r3, [r3, #36] ; 0x24
- 80034da: f003 0302 and.w r3, r3, #2
- 80034de: 2b00 cmp r3, #0
- 80034e0: d00a beq.n 80034f8 <UART_AdvFeatureConfig+0x4c>
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 80034e2: 687b ldr r3, [r7, #4]
- 80034e4: 681b ldr r3, [r3, #0]
- 80034e6: 685b ldr r3, [r3, #4]
- 80034e8: f423 3180 bic.w r1, r3, #65536 ; 0x10000
- 80034ec: 687b ldr r3, [r7, #4]
- 80034ee: 6ada ldr r2, [r3, #44] ; 0x2c
- 80034f0: 687b ldr r3, [r7, #4]
- 80034f2: 681b ldr r3, [r3, #0]
- 80034f4: 430a orrs r2, r1
- 80034f6: 605a str r2, [r3, #4]
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 80034f8: 687b ldr r3, [r7, #4]
- 80034fa: 6a5b ldr r3, [r3, #36] ; 0x24
- 80034fc: f003 0304 and.w r3, r3, #4
- 8003500: 2b00 cmp r3, #0
- 8003502: d00a beq.n 800351a <UART_AdvFeatureConfig+0x6e>
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 8003504: 687b ldr r3, [r7, #4]
- 8003506: 681b ldr r3, [r3, #0]
- 8003508: 685b ldr r3, [r3, #4]
- 800350a: f423 2180 bic.w r1, r3, #262144 ; 0x40000
- 800350e: 687b ldr r3, [r7, #4]
- 8003510: 6b1a ldr r2, [r3, #48] ; 0x30
- 8003512: 687b ldr r3, [r7, #4]
- 8003514: 681b ldr r3, [r3, #0]
- 8003516: 430a orrs r2, r1
- 8003518: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 800351a: 687b ldr r3, [r7, #4]
- 800351c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800351e: f003 0308 and.w r3, r3, #8
- 8003522: 2b00 cmp r3, #0
- 8003524: d00a beq.n 800353c <UART_AdvFeatureConfig+0x90>
- {
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 8003526: 687b ldr r3, [r7, #4]
- 8003528: 681b ldr r3, [r3, #0]
- 800352a: 685b ldr r3, [r3, #4]
- 800352c: f423 4100 bic.w r1, r3, #32768 ; 0x8000
- 8003530: 687b ldr r3, [r7, #4]
- 8003532: 6b5a ldr r2, [r3, #52] ; 0x34
- 8003534: 687b ldr r3, [r7, #4]
- 8003536: 681b ldr r3, [r3, #0]
- 8003538: 430a orrs r2, r1
- 800353a: 605a str r2, [r3, #4]
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 800353c: 687b ldr r3, [r7, #4]
- 800353e: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003540: f003 0310 and.w r3, r3, #16
- 8003544: 2b00 cmp r3, #0
- 8003546: d00a beq.n 800355e <UART_AdvFeatureConfig+0xb2>
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 8003548: 687b ldr r3, [r7, #4]
- 800354a: 681b ldr r3, [r3, #0]
- 800354c: 689b ldr r3, [r3, #8]
- 800354e: f423 5180 bic.w r1, r3, #4096 ; 0x1000
- 8003552: 687b ldr r3, [r7, #4]
- 8003554: 6b9a ldr r2, [r3, #56] ; 0x38
- 8003556: 687b ldr r3, [r7, #4]
- 8003558: 681b ldr r3, [r3, #0]
- 800355a: 430a orrs r2, r1
- 800355c: 609a str r2, [r3, #8]
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 800355e: 687b ldr r3, [r7, #4]
- 8003560: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003562: f003 0320 and.w r3, r3, #32
- 8003566: 2b00 cmp r3, #0
- 8003568: d00a beq.n 8003580 <UART_AdvFeatureConfig+0xd4>
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 800356a: 687b ldr r3, [r7, #4]
- 800356c: 681b ldr r3, [r3, #0]
- 800356e: 689b ldr r3, [r3, #8]
- 8003570: f423 5100 bic.w r1, r3, #8192 ; 0x2000
- 8003574: 687b ldr r3, [r7, #4]
- 8003576: 6bda ldr r2, [r3, #60] ; 0x3c
- 8003578: 687b ldr r3, [r7, #4]
- 800357a: 681b ldr r3, [r3, #0]
- 800357c: 430a orrs r2, r1
- 800357e: 609a str r2, [r3, #8]
- }
-
- /* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 8003580: 687b ldr r3, [r7, #4]
- 8003582: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003584: f003 0340 and.w r3, r3, #64 ; 0x40
- 8003588: 2b00 cmp r3, #0
- 800358a: d01a beq.n 80035c2 <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 800358c: 687b ldr r3, [r7, #4]
- 800358e: 681b ldr r3, [r3, #0]
- 8003590: 685b ldr r3, [r3, #4]
- 8003592: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
- 8003596: 687b ldr r3, [r7, #4]
- 8003598: 6c1a ldr r2, [r3, #64] ; 0x40
- 800359a: 687b ldr r3, [r7, #4]
- 800359c: 681b ldr r3, [r3, #0]
- 800359e: 430a orrs r2, r1
- 80035a0: 605a str r2, [r3, #4]
- /* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 80035a2: 687b ldr r3, [r7, #4]
- 80035a4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80035a6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 80035aa: d10a bne.n 80035c2 <UART_AdvFeatureConfig+0x116>
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 80035ac: 687b ldr r3, [r7, #4]
- 80035ae: 681b ldr r3, [r3, #0]
- 80035b0: 685b ldr r3, [r3, #4]
- 80035b2: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
- 80035b6: 687b ldr r3, [r7, #4]
- 80035b8: 6c5a ldr r2, [r3, #68] ; 0x44
- 80035ba: 687b ldr r3, [r7, #4]
- 80035bc: 681b ldr r3, [r3, #0]
- 80035be: 430a orrs r2, r1
- 80035c0: 605a str r2, [r3, #4]
- }
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 80035c2: 687b ldr r3, [r7, #4]
- 80035c4: 6a5b ldr r3, [r3, #36] ; 0x24
- 80035c6: f003 0380 and.w r3, r3, #128 ; 0x80
- 80035ca: 2b00 cmp r3, #0
- 80035cc: d00a beq.n 80035e4 <UART_AdvFeatureConfig+0x138>
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 80035ce: 687b ldr r3, [r7, #4]
- 80035d0: 681b ldr r3, [r3, #0]
- 80035d2: 685b ldr r3, [r3, #4]
- 80035d4: f423 2100 bic.w r1, r3, #524288 ; 0x80000
- 80035d8: 687b ldr r3, [r7, #4]
- 80035da: 6c9a ldr r2, [r3, #72] ; 0x48
- 80035dc: 687b ldr r3, [r7, #4]
- 80035de: 681b ldr r3, [r3, #0]
- 80035e0: 430a orrs r2, r1
- 80035e2: 605a str r2, [r3, #4]
- }
-}
- 80035e4: bf00 nop
- 80035e6: 370c adds r7, #12
- 80035e8: 46bd mov sp, r7
- 80035ea: f85d 7b04 ldr.w r7, [sp], #4
- 80035ee: 4770 bx lr
-
-080035f0 <UART_CheckIdleState>:
- * @brief Check the UART Idle State.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- 80035f0: b580 push {r7, lr}
- 80035f2: b086 sub sp, #24
- 80035f4: af02 add r7, sp, #8
- 80035f6: 6078 str r0, [r7, #4]
- uint32_t tickstart;
-
- /* Initialize the UART ErrorCode */
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80035f8: 687b ldr r3, [r7, #4]
- 80035fa: 2200 movs r2, #0
- 80035fc: 67da str r2, [r3, #124] ; 0x7c
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
- 80035fe: f7fd faad bl 8000b5c <HAL_GetTick>
- 8003602: 60f8 str r0, [r7, #12]
-
- /* Check if the Transmitter is enabled */
- if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 8003604: 687b ldr r3, [r7, #4]
- 8003606: 681b ldr r3, [r3, #0]
- 8003608: 681b ldr r3, [r3, #0]
- 800360a: f003 0308 and.w r3, r3, #8
- 800360e: 2b08 cmp r3, #8
- 8003610: d10e bne.n 8003630 <UART_CheckIdleState+0x40>
- {
- /* Wait until TEACK flag is set */
- if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 8003612: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
- 8003616: 9300 str r3, [sp, #0]
- 8003618: 68fb ldr r3, [r7, #12]
- 800361a: 2200 movs r2, #0
- 800361c: f44f 1100 mov.w r1, #2097152 ; 0x200000
- 8003620: 6878 ldr r0, [r7, #4]
- 8003622: f000 f814 bl 800364e <UART_WaitOnFlagUntilTimeout>
- 8003626: 4603 mov r3, r0
- 8003628: 2b00 cmp r3, #0
- 800362a: d001 beq.n 8003630 <UART_CheckIdleState+0x40>
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- 800362c: 2303 movs r3, #3
- 800362e: e00a b.n 8003646 <UART_CheckIdleState+0x56>
- }
- }
-
- /* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
- 8003630: 687b ldr r3, [r7, #4]
- 8003632: 2220 movs r2, #32
- 8003634: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 8003636: 687b ldr r3, [r7, #4]
- 8003638: 2220 movs r2, #32
- 800363a: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 800363c: 687b ldr r3, [r7, #4]
- 800363e: 2200 movs r2, #0
- 8003640: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_OK;
- 8003644: 2300 movs r3, #0
-}
- 8003646: 4618 mov r0, r3
- 8003648: 3710 adds r7, #16
- 800364a: 46bd mov sp, r7
- 800364c: bd80 pop {r7, pc}
-
-0800364e <UART_WaitOnFlagUntilTimeout>:
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- 800364e: b580 push {r7, lr}
- 8003650: b084 sub sp, #16
- 8003652: af00 add r7, sp, #0
- 8003654: 60f8 str r0, [r7, #12]
- 8003656: 60b9 str r1, [r7, #8]
- 8003658: 603b str r3, [r7, #0]
- 800365a: 4613 mov r3, r2
- 800365c: 71fb strb r3, [r7, #7]
- /* Wait until flag is set */
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 800365e: e02a b.n 80036b6 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- 8003660: 69bb ldr r3, [r7, #24]
- 8003662: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 8003666: d026 beq.n 80036b6 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8003668: f7fd fa78 bl 8000b5c <HAL_GetTick>
- 800366c: 4602 mov r2, r0
- 800366e: 683b ldr r3, [r7, #0]
- 8003670: 1ad3 subs r3, r2, r3
- 8003672: 69ba ldr r2, [r7, #24]
- 8003674: 429a cmp r2, r3
- 8003676: d302 bcc.n 800367e <UART_WaitOnFlagUntilTimeout+0x30>
- 8003678: 69bb ldr r3, [r7, #24]
- 800367a: 2b00 cmp r3, #0
- 800367c: d11b bne.n 80036b6 <UART_WaitOnFlagUntilTimeout+0x68>
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 800367e: 68fb ldr r3, [r7, #12]
- 8003680: 681b ldr r3, [r3, #0]
- 8003682: 681a ldr r2, [r3, #0]
- 8003684: 68fb ldr r3, [r7, #12]
- 8003686: 681b ldr r3, [r3, #0]
- 8003688: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 800368c: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800368e: 68fb ldr r3, [r7, #12]
- 8003690: 681b ldr r3, [r3, #0]
- 8003692: 689a ldr r2, [r3, #8]
- 8003694: 68fb ldr r3, [r7, #12]
- 8003696: 681b ldr r3, [r3, #0]
- 8003698: f022 0201 bic.w r2, r2, #1
- 800369c: 609a str r2, [r3, #8]
-
- huart->gState = HAL_UART_STATE_READY;
- 800369e: 68fb ldr r3, [r7, #12]
- 80036a0: 2220 movs r2, #32
- 80036a2: 675a str r2, [r3, #116] ; 0x74
- huart->RxState = HAL_UART_STATE_READY;
- 80036a4: 68fb ldr r3, [r7, #12]
- 80036a6: 2220 movs r2, #32
- 80036a8: 679a str r2, [r3, #120] ; 0x78
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- 80036aa: 68fb ldr r3, [r7, #12]
- 80036ac: 2200 movs r2, #0
- 80036ae: f883 2070 strb.w r2, [r3, #112] ; 0x70
-
- return HAL_TIMEOUT;
- 80036b2: 2303 movs r3, #3
- 80036b4: e00f b.n 80036d6 <UART_WaitOnFlagUntilTimeout+0x88>
- while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 80036b6: 68fb ldr r3, [r7, #12]
- 80036b8: 681b ldr r3, [r3, #0]
- 80036ba: 69da ldr r2, [r3, #28]
- 80036bc: 68bb ldr r3, [r7, #8]
- 80036be: 4013 ands r3, r2
- 80036c0: 68ba ldr r2, [r7, #8]
- 80036c2: 429a cmp r2, r3
- 80036c4: bf0c ite eq
- 80036c6: 2301 moveq r3, #1
- 80036c8: 2300 movne r3, #0
- 80036ca: b2db uxtb r3, r3
- 80036cc: 461a mov r2, r3
- 80036ce: 79fb ldrb r3, [r7, #7]
- 80036d0: 429a cmp r2, r3
- 80036d2: d0c5 beq.n 8003660 <UART_WaitOnFlagUntilTimeout+0x12>
- }
- }
- }
- return HAL_OK;
- 80036d4: 2300 movs r3, #0
-}
- 80036d6: 4618 mov r0, r3
- 80036d8: 3710 adds r7, #16
- 80036da: 46bd mov sp, r7
- 80036dc: bd80 pop {r7, pc}
-
-080036de <UART_EndRxTransfer>:
- * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart UART handle.
- * @retval None
- */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
- 80036de: b480 push {r7}
- 80036e0: b083 sub sp, #12
- 80036e2: af00 add r7, sp, #0
- 80036e4: 6078 str r0, [r7, #4]
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 80036e6: 687b ldr r3, [r7, #4]
- 80036e8: 681b ldr r3, [r3, #0]
- 80036ea: 681a ldr r2, [r3, #0]
- 80036ec: 687b ldr r3, [r7, #4]
- 80036ee: 681b ldr r3, [r3, #0]
- 80036f0: f422 7290 bic.w r2, r2, #288 ; 0x120
- 80036f4: 601a str r2, [r3, #0]
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80036f6: 687b ldr r3, [r7, #4]
- 80036f8: 681b ldr r3, [r3, #0]
- 80036fa: 689a ldr r2, [r3, #8]
- 80036fc: 687b ldr r3, [r7, #4]
- 80036fe: 681b ldr r3, [r3, #0]
- 8003700: f022 0201 bic.w r2, r2, #1
- 8003704: 609a str r2, [r3, #8]
-
- /* At end of Rx process, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 8003706: 687b ldr r3, [r7, #4]
- 8003708: 2220 movs r2, #32
- 800370a: 679a str r2, [r3, #120] ; 0x78
-
- /* Reset RxIsr function pointer */
- huart->RxISR = NULL;
- 800370c: 687b ldr r3, [r7, #4]
- 800370e: 2200 movs r2, #0
- 8003710: 661a str r2, [r3, #96] ; 0x60
-}
- 8003712: bf00 nop
- 8003714: 370c adds r7, #12
- 8003716: 46bd mov sp, r7
- 8003718: f85d 7b04 ldr.w r7, [sp], #4
- 800371c: 4770 bx lr
-
-0800371e <UART_DMAAbortOnError>:
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
- * @retval None
- */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- 800371e: b580 push {r7, lr}
- 8003720: b084 sub sp, #16
- 8003722: af00 add r7, sp, #0
- 8003724: 6078 str r0, [r7, #4]
- UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 8003726: 687b ldr r3, [r7, #4]
- 8003728: 6b9b ldr r3, [r3, #56] ; 0x38
- 800372a: 60fb str r3, [r7, #12]
- huart->RxXferCount = 0U;
- 800372c: 68fb ldr r3, [r7, #12]
- 800372e: 2200 movs r2, #0
- 8003730: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
- huart->TxXferCount = 0U;
- 8003734: 68fb ldr r3, [r7, #12]
- 8003736: 2200 movs r2, #0
- 8003738: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered error callback*/
- huart->ErrorCallback(huart);
-#else
- /*Call legacy weak error callback*/
- HAL_UART_ErrorCallback(huart);
- 800373c: 68f8 ldr r0, [r7, #12]
- 800373e: f7fd f873 bl 8000828 <HAL_UART_ErrorCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 8003742: bf00 nop
- 8003744: 3710 adds r7, #16
- 8003746: 46bd mov sp, r7
- 8003748: bd80 pop {r7, pc}
-
-0800374a <UART_EndTransmit_IT>:
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval None
- */
-static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- 800374a: b580 push {r7, lr}
- 800374c: b082 sub sp, #8
- 800374e: af00 add r7, sp, #0
- 8003750: 6078 str r0, [r7, #4]
- /* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- 8003752: 687b ldr r3, [r7, #4]
- 8003754: 681b ldr r3, [r3, #0]
- 8003756: 681a ldr r2, [r3, #0]
- 8003758: 687b ldr r3, [r7, #4]
- 800375a: 681b ldr r3, [r3, #0]
- 800375c: f022 0240 bic.w r2, r2, #64 ; 0x40
- 8003760: 601a str r2, [r3, #0]
-
- /* Tx process is ended, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
- 8003762: 687b ldr r3, [r7, #4]
- 8003764: 2220 movs r2, #32
- 8003766: 675a str r2, [r3, #116] ; 0x74
-
- /* Cleat TxISR function pointer */
- huart->TxISR = NULL;
- 8003768: 687b ldr r3, [r7, #4]
- 800376a: 2200 movs r2, #0
- 800376c: 665a str r2, [r3, #100] ; 0x64
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Tx complete callback*/
- huart->TxCpltCallback(huart);
-#else
- /*Call legacy weak Tx complete callback*/
- HAL_UART_TxCpltCallback(huart);
- 800376e: 6878 ldr r0, [r7, #4]
- 8003770: f7ff fbee bl 8002f50 <HAL_UART_TxCpltCallback>
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
- 8003774: bf00 nop
- 8003776: 3708 adds r7, #8
- 8003778: 46bd mov sp, r7
- 800377a: bd80 pop {r7, pc}
-
-0800377c <UART_RxISR_8BIT>:
- * @brief RX interrrupt handler for 7 or 8 bits data word length .
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
-{
- 800377c: b580 push {r7, lr}
- 800377e: b084 sub sp, #16
- 8003780: af00 add r7, sp, #0
- 8003782: 6078 str r0, [r7, #4]
- uint16_t uhMask = huart->Mask;
- 8003784: 687b ldr r3, [r7, #4]
- 8003786: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 800378a: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 800378c: 687b ldr r3, [r7, #4]
- 800378e: 6f9b ldr r3, [r3, #120] ; 0x78
- 8003790: 2b22 cmp r3, #34 ; 0x22
- 8003792: d13a bne.n 800380a <UART_RxISR_8BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 8003794: 687b ldr r3, [r7, #4]
- 8003796: 681b ldr r3, [r3, #0]
- 8003798: 6a5b ldr r3, [r3, #36] ; 0x24
- 800379a: 81bb strh r3, [r7, #12]
- *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
- 800379c: 89bb ldrh r3, [r7, #12]
- 800379e: b2d9 uxtb r1, r3
- 80037a0: 89fb ldrh r3, [r7, #14]
- 80037a2: b2da uxtb r2, r3
- 80037a4: 687b ldr r3, [r7, #4]
- 80037a6: 6d5b ldr r3, [r3, #84] ; 0x54
- 80037a8: 400a ands r2, r1
- 80037aa: b2d2 uxtb r2, r2
- 80037ac: 701a strb r2, [r3, #0]
- huart->pRxBuffPtr++;
- 80037ae: 687b ldr r3, [r7, #4]
- 80037b0: 6d5b ldr r3, [r3, #84] ; 0x54
- 80037b2: 1c5a adds r2, r3, #1
- 80037b4: 687b ldr r3, [r7, #4]
- 80037b6: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 80037b8: 687b ldr r3, [r7, #4]
- 80037ba: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 80037be: b29b uxth r3, r3
- 80037c0: 3b01 subs r3, #1
- 80037c2: b29a uxth r2, r3
- 80037c4: 687b ldr r3, [r7, #4]
- 80037c6: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 80037ca: 687b ldr r3, [r7, #4]
- 80037cc: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 80037d0: b29b uxth r3, r3
- 80037d2: 2b00 cmp r3, #0
- 80037d4: d121 bne.n 800381a <UART_RxISR_8BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 80037d6: 687b ldr r3, [r7, #4]
- 80037d8: 681b ldr r3, [r3, #0]
- 80037da: 681a ldr r2, [r3, #0]
- 80037dc: 687b ldr r3, [r7, #4]
- 80037de: 681b ldr r3, [r3, #0]
- 80037e0: f422 7290 bic.w r2, r2, #288 ; 0x120
- 80037e4: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80037e6: 687b ldr r3, [r7, #4]
- 80037e8: 681b ldr r3, [r3, #0]
- 80037ea: 689a ldr r2, [r3, #8]
- 80037ec: 687b ldr r3, [r7, #4]
- 80037ee: 681b ldr r3, [r3, #0]
- 80037f0: f022 0201 bic.w r2, r2, #1
- 80037f4: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 80037f6: 687b ldr r3, [r7, #4]
- 80037f8: 2220 movs r2, #32
- 80037fa: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 80037fc: 687b ldr r3, [r7, #4]
- 80037fe: 2200 movs r2, #0
- 8003800: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 8003802: 6878 ldr r0, [r7, #4]
- 8003804: f7fc fffc bl 8000800 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 8003808: e007 b.n 800381a <UART_RxISR_8BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 800380a: 687b ldr r3, [r7, #4]
- 800380c: 681b ldr r3, [r3, #0]
- 800380e: 699a ldr r2, [r3, #24]
- 8003810: 687b ldr r3, [r7, #4]
- 8003812: 681b ldr r3, [r3, #0]
- 8003814: f042 0208 orr.w r2, r2, #8
- 8003818: 619a str r2, [r3, #24]
-}
- 800381a: bf00 nop
- 800381c: 3710 adds r7, #16
- 800381e: 46bd mov sp, r7
- 8003820: bd80 pop {r7, pc}
-
-08003822 <UART_RxISR_16BIT>:
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval None
- */
-static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
-{
- 8003822: b580 push {r7, lr}
- 8003824: b084 sub sp, #16
- 8003826: af00 add r7, sp, #0
- 8003828: 6078 str r0, [r7, #4]
- uint16_t *tmp;
- uint16_t uhMask = huart->Mask;
- 800382a: 687b ldr r3, [r7, #4]
- 800382c: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
- 8003830: 81fb strh r3, [r7, #14]
- uint16_t uhdata;
-
- /* Check that a Rx process is ongoing */
- if (huart->RxState == HAL_UART_STATE_BUSY_RX)
- 8003832: 687b ldr r3, [r7, #4]
- 8003834: 6f9b ldr r3, [r3, #120] ; 0x78
- 8003836: 2b22 cmp r3, #34 ; 0x22
- 8003838: d13a bne.n 80038b0 <UART_RxISR_16BIT+0x8e>
- {
- uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- 800383a: 687b ldr r3, [r7, #4]
- 800383c: 681b ldr r3, [r3, #0]
- 800383e: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003840: 81bb strh r3, [r7, #12]
- tmp = (uint16_t *) huart->pRxBuffPtr ;
- 8003842: 687b ldr r3, [r7, #4]
- 8003844: 6d5b ldr r3, [r3, #84] ; 0x54
- 8003846: 60bb str r3, [r7, #8]
- *tmp = (uint16_t)(uhdata & uhMask);
- 8003848: 89ba ldrh r2, [r7, #12]
- 800384a: 89fb ldrh r3, [r7, #14]
- 800384c: 4013 ands r3, r2
- 800384e: b29a uxth r2, r3
- 8003850: 68bb ldr r3, [r7, #8]
- 8003852: 801a strh r2, [r3, #0]
- huart->pRxBuffPtr += 2U;
- 8003854: 687b ldr r3, [r7, #4]
- 8003856: 6d5b ldr r3, [r3, #84] ; 0x54
- 8003858: 1c9a adds r2, r3, #2
- 800385a: 687b ldr r3, [r7, #4]
- 800385c: 655a str r2, [r3, #84] ; 0x54
- huart->RxXferCount--;
- 800385e: 687b ldr r3, [r7, #4]
- 8003860: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8003864: b29b uxth r3, r3
- 8003866: 3b01 subs r3, #1
- 8003868: b29a uxth r2, r3
- 800386a: 687b ldr r3, [r7, #4]
- 800386c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
-
- if (huart->RxXferCount == 0U)
- 8003870: 687b ldr r3, [r7, #4]
- 8003872: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
- 8003876: b29b uxth r3, r3
- 8003878: 2b00 cmp r3, #0
- 800387a: d121 bne.n 80038c0 <UART_RxISR_16BIT+0x9e>
- {
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- 800387c: 687b ldr r3, [r7, #4]
- 800387e: 681b ldr r3, [r3, #0]
- 8003880: 681a ldr r2, [r3, #0]
- 8003882: 687b ldr r3, [r7, #4]
- 8003884: 681b ldr r3, [r3, #0]
- 8003886: f422 7290 bic.w r2, r2, #288 ; 0x120
- 800388a: 601a str r2, [r3, #0]
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 800388c: 687b ldr r3, [r7, #4]
- 800388e: 681b ldr r3, [r3, #0]
- 8003890: 689a ldr r2, [r3, #8]
- 8003892: 687b ldr r3, [r7, #4]
- 8003894: 681b ldr r3, [r3, #0]
- 8003896: f022 0201 bic.w r2, r2, #1
- 800389a: 609a str r2, [r3, #8]
-
- /* Rx process is completed, restore huart->RxState to Ready */
- huart->RxState = HAL_UART_STATE_READY;
- 800389c: 687b ldr r3, [r7, #4]
- 800389e: 2220 movs r2, #32
- 80038a0: 679a str r2, [r3, #120] ; 0x78
-
- /* Clear RxISR function pointer */
- huart->RxISR = NULL;
- 80038a2: 687b ldr r3, [r7, #4]
- 80038a4: 2200 movs r2, #0
- 80038a6: 661a str r2, [r3, #96] ; 0x60
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
-#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
- 80038a8: 6878 ldr r0, [r7, #4]
- 80038aa: f7fc ffa9 bl 8000800 <HAL_UART_RxCpltCallback>
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
-}
- 80038ae: e007 b.n 80038c0 <UART_RxISR_16BIT+0x9e>
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- 80038b0: 687b ldr r3, [r7, #4]
- 80038b2: 681b ldr r3, [r3, #0]
- 80038b4: 699a ldr r2, [r3, #24]
- 80038b6: 687b ldr r3, [r7, #4]
- 80038b8: 681b ldr r3, [r3, #0]
- 80038ba: f042 0208 orr.w r2, r2, #8
- 80038be: 619a str r2, [r3, #24]
-}
- 80038c0: bf00 nop
- 80038c2: 3710 adds r7, #16
- 80038c4: 46bd mov sp, r7
- 80038c6: bd80 pop {r7, pc}
-
-080038c8 <__libc_init_array>:
- 80038c8: b570 push {r4, r5, r6, lr}
- 80038ca: 4e0d ldr r6, [pc, #52] ; (8003900 <__libc_init_array+0x38>)
- 80038cc: 4c0d ldr r4, [pc, #52] ; (8003904 <__libc_init_array+0x3c>)
- 80038ce: 1ba4 subs r4, r4, r6
- 80038d0: 10a4 asrs r4, r4, #2
- 80038d2: 2500 movs r5, #0
- 80038d4: 42a5 cmp r5, r4
- 80038d6: d109 bne.n 80038ec <__libc_init_array+0x24>
- 80038d8: 4e0b ldr r6, [pc, #44] ; (8003908 <__libc_init_array+0x40>)
- 80038da: 4c0c ldr r4, [pc, #48] ; (800390c <__libc_init_array+0x44>)
- 80038dc: f000 f820 bl 8003920 <_init>
- 80038e0: 1ba4 subs r4, r4, r6
- 80038e2: 10a4 asrs r4, r4, #2
- 80038e4: 2500 movs r5, #0
- 80038e6: 42a5 cmp r5, r4
- 80038e8: d105 bne.n 80038f6 <__libc_init_array+0x2e>
- 80038ea: bd70 pop {r4, r5, r6, pc}
- 80038ec: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 80038f0: 4798 blx r3
- 80038f2: 3501 adds r5, #1
- 80038f4: e7ee b.n 80038d4 <__libc_init_array+0xc>
- 80038f6: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 80038fa: 4798 blx r3
- 80038fc: 3501 adds r5, #1
- 80038fe: e7f2 b.n 80038e6 <__libc_init_array+0x1e>
- 8003900: 08003958 .word 0x08003958
- 8003904: 08003958 .word 0x08003958
- 8003908: 08003958 .word 0x08003958
- 800390c: 0800395c .word 0x0800395c
-
-08003910 <memset>:
- 8003910: 4402 add r2, r0
- 8003912: 4603 mov r3, r0
- 8003914: 4293 cmp r3, r2
- 8003916: d100 bne.n 800391a <memset+0xa>
- 8003918: 4770 bx lr
- 800391a: f803 1b01 strb.w r1, [r3], #1
- 800391e: e7f9 b.n 8003914 <memset+0x4>
-
-08003920 <_init>:
- 8003920: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8003922: bf00 nop
- 8003924: bcf8 pop {r3, r4, r5, r6, r7}
- 8003926: bc08 pop {r3}
- 8003928: 469e mov lr, r3
- 800392a: 4770 bx lr
-
-0800392c <_fini>:
- 800392c: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800392e: bf00 nop
- 8003930: bcf8 pop {r3, r4, r5, r6, r7}
- 8003932: bc08 pop {r3}
- 8003934: 469e mov lr, r3
- 8003936: 4770 bx lr
-DutyCycle, Velocity
+DutyCycle Velocity
0.000000 0.000000
0.000000 0.000000
1.000000 0.000000
file_name = user_input + "-" + datetime.now().strftime("%Y-%m-%d-%H-%M-%S") + ".csv"
log_file = open("data/" + file_name, 'w')
-log_file.write("DutyCycle, Velocity \n")
+log_file.write("DutyCycle Velocity \n")
while 1:
ser.reset_input_buffer()
while 1:
ser.reset_input_buffer()
- buffer = ser.read(8)
- msg_received = struct.unpack('<ff', buffer)
+ buffer = ser.read(4)
+ msg_received = struct.unpack('<f', buffer)
print(msg_received)
print(buffer)
SourceFiles#2=/home/fdila/Projects/otto/uart_test/Core/Src/main.c\r
SourceFolderListSize=1\r
SourcePath#0=/home/fdila/Projects/otto/uart_test/Core/Src\r
-HeaderFiles=;\r
-SourceFiles=;\r
\r
[PreviousLibFiles]\r
LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm4.h;\r
\r
/* GPIO Ports Clock Enable */\r
__HAL_RCC_GPIOC_CLK_ENABLE();\r
+ __HAL_RCC_GPIOA_CLK_ENABLE();\r
\r
}\r
\r
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {\r
if (htim->Instance == TIM3) {\r
HAL_UART_Transmit(&huart6, tx_buffer, 12, 100);\r
+ test++;\r
}\r
}\r
\r
--- /dev/null
+
+uart_test.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 1 .text 00003768 080001f8 080001f8 000101f8 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 2 .rodata 00000018 08003960 08003960 00013960 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 3 .ARM.extab 00000000 08003978 08003978 0002000c 2**0
+ CONTENTS
+ 4 .ARM 00000008 08003978 08003978 00013978 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 5 .preinit_array 00000000 08003980 08003980 0002000c 2**0
+ CONTENTS, ALLOC, LOAD, DATA
+ 6 .init_array 00000004 08003980 08003980 00013980 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 7 .fini_array 00000004 08003984 08003984 00013984 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 8 .data 0000000c 20000000 08003988 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 9 .bss 00000108 2000000c 08003994 0002000c 2**2
+ ALLOC
+ 10 ._user_heap_stack 00000604 20000114 08003994 00020114 2**0
+ ALLOC
+ 11 .ARM.attributes 0000002e 00000000 00000000 0002000c 2**0
+ CONTENTS, READONLY
+ 12 .debug_info 0000c00e 00000000 00000000 0002003a 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 13 .debug_abbrev 000019c5 00000000 00000000 0002c048 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 14 .debug_aranges 00000c60 00000000 00000000 0002da10 2**3
+ CONTENTS, READONLY, DEBUGGING
+ 15 .debug_ranges 00000b88 00000000 00000000 0002e670 2**3
+ CONTENTS, READONLY, DEBUGGING
+ 16 .debug_macro 00025f5e 00000000 00000000 0002f1f8 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 17 .debug_line 00008efa 00000000 00000000 00055156 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 18 .debug_str 000f0c82 00000000 00000000 0005e050 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 19 .comment 0000007b 00000000 00000000 0014ecd2 2**0
+ CONTENTS, READONLY
+ 20 .debug_frame 00003400 00000000 00000000 0014ed50 2**2
+ CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+080001f8 <__do_global_dtors_aux>:
+ 80001f8: b510 push {r4, lr}
+ 80001fa: 4c05 ldr r4, [pc, #20] ; (8000210 <__do_global_dtors_aux+0x18>)
+ 80001fc: 7823 ldrb r3, [r4, #0]
+ 80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
+ 8000200: 4b04 ldr r3, [pc, #16] ; (8000214 <__do_global_dtors_aux+0x1c>)
+ 8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
+ 8000204: 4804 ldr r0, [pc, #16] ; (8000218 <__do_global_dtors_aux+0x20>)
+ 8000206: f3af 8000 nop.w
+ 800020a: 2301 movs r3, #1
+ 800020c: 7023 strb r3, [r4, #0]
+ 800020e: bd10 pop {r4, pc}
+ 8000210: 2000000c .word 0x2000000c
+ 8000214: 00000000 .word 0x00000000
+ 8000218: 08003948 .word 0x08003948
+
+0800021c <frame_dummy>:
+ 800021c: b508 push {r3, lr}
+ 800021e: 4b03 ldr r3, [pc, #12] ; (800022c <frame_dummy+0x10>)
+ 8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
+ 8000222: 4903 ldr r1, [pc, #12] ; (8000230 <frame_dummy+0x14>)
+ 8000224: 4803 ldr r0, [pc, #12] ; (8000234 <frame_dummy+0x18>)
+ 8000226: f3af 8000 nop.w
+ 800022a: bd08 pop {r3, pc}
+ 800022c: 00000000 .word 0x00000000
+ 8000230: 20000010 .word 0x20000010
+ 8000234: 08003948 .word 0x08003948
+
+08000238 <__aeabi_uldivmod>:
+ 8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
+ 800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
+ 800023c: 2900 cmp r1, #0
+ 800023e: bf08 it eq
+ 8000240: 2800 cmpeq r0, #0
+ 8000242: bf1c itt ne
+ 8000244: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
+ 8000248: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
+ 800024c: f000 b972 b.w 8000534 <__aeabi_idiv0>
+ 8000250: f1ad 0c08 sub.w ip, sp, #8
+ 8000254: e96d ce04 strd ip, lr, [sp, #-16]!
+ 8000258: f000 f806 bl 8000268 <__udivmoddi4>
+ 800025c: f8dd e004 ldr.w lr, [sp, #4]
+ 8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
+ 8000264: b004 add sp, #16
+ 8000266: 4770 bx lr
+
+08000268 <__udivmoddi4>:
+ 8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 800026c: 9e08 ldr r6, [sp, #32]
+ 800026e: 4604 mov r4, r0
+ 8000270: 4688 mov r8, r1
+ 8000272: 2b00 cmp r3, #0
+ 8000274: d14b bne.n 800030e <__udivmoddi4+0xa6>
+ 8000276: 428a cmp r2, r1
+ 8000278: 4615 mov r5, r2
+ 800027a: d967 bls.n 800034c <__udivmoddi4+0xe4>
+ 800027c: fab2 f282 clz r2, r2
+ 8000280: b14a cbz r2, 8000296 <__udivmoddi4+0x2e>
+ 8000282: f1c2 0720 rsb r7, r2, #32
+ 8000286: fa01 f302 lsl.w r3, r1, r2
+ 800028a: fa20 f707 lsr.w r7, r0, r7
+ 800028e: 4095 lsls r5, r2
+ 8000290: ea47 0803 orr.w r8, r7, r3
+ 8000294: 4094 lsls r4, r2
+ 8000296: ea4f 4e15 mov.w lr, r5, lsr #16
+ 800029a: 0c23 lsrs r3, r4, #16
+ 800029c: fbb8 f7fe udiv r7, r8, lr
+ 80002a0: fa1f fc85 uxth.w ip, r5
+ 80002a4: fb0e 8817 mls r8, lr, r7, r8
+ 80002a8: ea43 4308 orr.w r3, r3, r8, lsl #16
+ 80002ac: fb07 f10c mul.w r1, r7, ip
+ 80002b0: 4299 cmp r1, r3
+ 80002b2: d909 bls.n 80002c8 <__udivmoddi4+0x60>
+ 80002b4: 18eb adds r3, r5, r3
+ 80002b6: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
+ 80002ba: f080 811b bcs.w 80004f4 <__udivmoddi4+0x28c>
+ 80002be: 4299 cmp r1, r3
+ 80002c0: f240 8118 bls.w 80004f4 <__udivmoddi4+0x28c>
+ 80002c4: 3f02 subs r7, #2
+ 80002c6: 442b add r3, r5
+ 80002c8: 1a5b subs r3, r3, r1
+ 80002ca: b2a4 uxth r4, r4
+ 80002cc: fbb3 f0fe udiv r0, r3, lr
+ 80002d0: fb0e 3310 mls r3, lr, r0, r3
+ 80002d4: ea44 4403 orr.w r4, r4, r3, lsl #16
+ 80002d8: fb00 fc0c mul.w ip, r0, ip
+ 80002dc: 45a4 cmp ip, r4
+ 80002de: d909 bls.n 80002f4 <__udivmoddi4+0x8c>
+ 80002e0: 192c adds r4, r5, r4
+ 80002e2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
+ 80002e6: f080 8107 bcs.w 80004f8 <__udivmoddi4+0x290>
+ 80002ea: 45a4 cmp ip, r4
+ 80002ec: f240 8104 bls.w 80004f8 <__udivmoddi4+0x290>
+ 80002f0: 3802 subs r0, #2
+ 80002f2: 442c add r4, r5
+ 80002f4: ea40 4007 orr.w r0, r0, r7, lsl #16
+ 80002f8: eba4 040c sub.w r4, r4, ip
+ 80002fc: 2700 movs r7, #0
+ 80002fe: b11e cbz r6, 8000308 <__udivmoddi4+0xa0>
+ 8000300: 40d4 lsrs r4, r2
+ 8000302: 2300 movs r3, #0
+ 8000304: e9c6 4300 strd r4, r3, [r6]
+ 8000308: 4639 mov r1, r7
+ 800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 800030e: 428b cmp r3, r1
+ 8000310: d909 bls.n 8000326 <__udivmoddi4+0xbe>
+ 8000312: 2e00 cmp r6, #0
+ 8000314: f000 80eb beq.w 80004ee <__udivmoddi4+0x286>
+ 8000318: 2700 movs r7, #0
+ 800031a: e9c6 0100 strd r0, r1, [r6]
+ 800031e: 4638 mov r0, r7
+ 8000320: 4639 mov r1, r7
+ 8000322: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 8000326: fab3 f783 clz r7, r3
+ 800032a: 2f00 cmp r7, #0
+ 800032c: d147 bne.n 80003be <__udivmoddi4+0x156>
+ 800032e: 428b cmp r3, r1
+ 8000330: d302 bcc.n 8000338 <__udivmoddi4+0xd0>
+ 8000332: 4282 cmp r2, r0
+ 8000334: f200 80fa bhi.w 800052c <__udivmoddi4+0x2c4>
+ 8000338: 1a84 subs r4, r0, r2
+ 800033a: eb61 0303 sbc.w r3, r1, r3
+ 800033e: 2001 movs r0, #1
+ 8000340: 4698 mov r8, r3
+ 8000342: 2e00 cmp r6, #0
+ 8000344: d0e0 beq.n 8000308 <__udivmoddi4+0xa0>
+ 8000346: e9c6 4800 strd r4, r8, [r6]
+ 800034a: e7dd b.n 8000308 <__udivmoddi4+0xa0>
+ 800034c: b902 cbnz r2, 8000350 <__udivmoddi4+0xe8>
+ 800034e: deff udf #255 ; 0xff
+ 8000350: fab2 f282 clz r2, r2
+ 8000354: 2a00 cmp r2, #0
+ 8000356: f040 808f bne.w 8000478 <__udivmoddi4+0x210>
+ 800035a: 1b49 subs r1, r1, r5
+ 800035c: ea4f 4e15 mov.w lr, r5, lsr #16
+ 8000360: fa1f f885 uxth.w r8, r5
+ 8000364: 2701 movs r7, #1
+ 8000366: fbb1 fcfe udiv ip, r1, lr
+ 800036a: 0c23 lsrs r3, r4, #16
+ 800036c: fb0e 111c mls r1, lr, ip, r1
+ 8000370: ea43 4301 orr.w r3, r3, r1, lsl #16
+ 8000374: fb08 f10c mul.w r1, r8, ip
+ 8000378: 4299 cmp r1, r3
+ 800037a: d907 bls.n 800038c <__udivmoddi4+0x124>
+ 800037c: 18eb adds r3, r5, r3
+ 800037e: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
+ 8000382: d202 bcs.n 800038a <__udivmoddi4+0x122>
+ 8000384: 4299 cmp r1, r3
+ 8000386: f200 80cd bhi.w 8000524 <__udivmoddi4+0x2bc>
+ 800038a: 4684 mov ip, r0
+ 800038c: 1a59 subs r1, r3, r1
+ 800038e: b2a3 uxth r3, r4
+ 8000390: fbb1 f0fe udiv r0, r1, lr
+ 8000394: fb0e 1410 mls r4, lr, r0, r1
+ 8000398: ea43 4404 orr.w r4, r3, r4, lsl #16
+ 800039c: fb08 f800 mul.w r8, r8, r0
+ 80003a0: 45a0 cmp r8, r4
+ 80003a2: d907 bls.n 80003b4 <__udivmoddi4+0x14c>
+ 80003a4: 192c adds r4, r5, r4
+ 80003a6: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
+ 80003aa: d202 bcs.n 80003b2 <__udivmoddi4+0x14a>
+ 80003ac: 45a0 cmp r8, r4
+ 80003ae: f200 80b6 bhi.w 800051e <__udivmoddi4+0x2b6>
+ 80003b2: 4618 mov r0, r3
+ 80003b4: eba4 0408 sub.w r4, r4, r8
+ 80003b8: ea40 400c orr.w r0, r0, ip, lsl #16
+ 80003bc: e79f b.n 80002fe <__udivmoddi4+0x96>
+ 80003be: f1c7 0c20 rsb ip, r7, #32
+ 80003c2: 40bb lsls r3, r7
+ 80003c4: fa22 fe0c lsr.w lr, r2, ip
+ 80003c8: ea4e 0e03 orr.w lr, lr, r3
+ 80003cc: fa01 f407 lsl.w r4, r1, r7
+ 80003d0: fa20 f50c lsr.w r5, r0, ip
+ 80003d4: fa21 f30c lsr.w r3, r1, ip
+ 80003d8: ea4f 481e mov.w r8, lr, lsr #16
+ 80003dc: 4325 orrs r5, r4
+ 80003de: fbb3 f9f8 udiv r9, r3, r8
+ 80003e2: 0c2c lsrs r4, r5, #16
+ 80003e4: fb08 3319 mls r3, r8, r9, r3
+ 80003e8: fa1f fa8e uxth.w sl, lr
+ 80003ec: ea44 4303 orr.w r3, r4, r3, lsl #16
+ 80003f0: fb09 f40a mul.w r4, r9, sl
+ 80003f4: 429c cmp r4, r3
+ 80003f6: fa02 f207 lsl.w r2, r2, r7
+ 80003fa: fa00 f107 lsl.w r1, r0, r7
+ 80003fe: d90b bls.n 8000418 <__udivmoddi4+0x1b0>
+ 8000400: eb1e 0303 adds.w r3, lr, r3
+ 8000404: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
+ 8000408: f080 8087 bcs.w 800051a <__udivmoddi4+0x2b2>
+ 800040c: 429c cmp r4, r3
+ 800040e: f240 8084 bls.w 800051a <__udivmoddi4+0x2b2>
+ 8000412: f1a9 0902 sub.w r9, r9, #2
+ 8000416: 4473 add r3, lr
+ 8000418: 1b1b subs r3, r3, r4
+ 800041a: b2ad uxth r5, r5
+ 800041c: fbb3 f0f8 udiv r0, r3, r8
+ 8000420: fb08 3310 mls r3, r8, r0, r3
+ 8000424: ea45 4403 orr.w r4, r5, r3, lsl #16
+ 8000428: fb00 fa0a mul.w sl, r0, sl
+ 800042c: 45a2 cmp sl, r4
+ 800042e: d908 bls.n 8000442 <__udivmoddi4+0x1da>
+ 8000430: eb1e 0404 adds.w r4, lr, r4
+ 8000434: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
+ 8000438: d26b bcs.n 8000512 <__udivmoddi4+0x2aa>
+ 800043a: 45a2 cmp sl, r4
+ 800043c: d969 bls.n 8000512 <__udivmoddi4+0x2aa>
+ 800043e: 3802 subs r0, #2
+ 8000440: 4474 add r4, lr
+ 8000442: ea40 4009 orr.w r0, r0, r9, lsl #16
+ 8000446: fba0 8902 umull r8, r9, r0, r2
+ 800044a: eba4 040a sub.w r4, r4, sl
+ 800044e: 454c cmp r4, r9
+ 8000450: 46c2 mov sl, r8
+ 8000452: 464b mov r3, r9
+ 8000454: d354 bcc.n 8000500 <__udivmoddi4+0x298>
+ 8000456: d051 beq.n 80004fc <__udivmoddi4+0x294>
+ 8000458: 2e00 cmp r6, #0
+ 800045a: d069 beq.n 8000530 <__udivmoddi4+0x2c8>
+ 800045c: ebb1 050a subs.w r5, r1, sl
+ 8000460: eb64 0403 sbc.w r4, r4, r3
+ 8000464: fa04 fc0c lsl.w ip, r4, ip
+ 8000468: 40fd lsrs r5, r7
+ 800046a: 40fc lsrs r4, r7
+ 800046c: ea4c 0505 orr.w r5, ip, r5
+ 8000470: e9c6 5400 strd r5, r4, [r6]
+ 8000474: 2700 movs r7, #0
+ 8000476: e747 b.n 8000308 <__udivmoddi4+0xa0>
+ 8000478: f1c2 0320 rsb r3, r2, #32
+ 800047c: fa20 f703 lsr.w r7, r0, r3
+ 8000480: 4095 lsls r5, r2
+ 8000482: fa01 f002 lsl.w r0, r1, r2
+ 8000486: fa21 f303 lsr.w r3, r1, r3
+ 800048a: ea4f 4e15 mov.w lr, r5, lsr #16
+ 800048e: 4338 orrs r0, r7
+ 8000490: 0c01 lsrs r1, r0, #16
+ 8000492: fbb3 f7fe udiv r7, r3, lr
+ 8000496: fa1f f885 uxth.w r8, r5
+ 800049a: fb0e 3317 mls r3, lr, r7, r3
+ 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
+ 80004a2: fb07 f308 mul.w r3, r7, r8
+ 80004a6: 428b cmp r3, r1
+ 80004a8: fa04 f402 lsl.w r4, r4, r2
+ 80004ac: d907 bls.n 80004be <__udivmoddi4+0x256>
+ 80004ae: 1869 adds r1, r5, r1
+ 80004b0: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
+ 80004b4: d22f bcs.n 8000516 <__udivmoddi4+0x2ae>
+ 80004b6: 428b cmp r3, r1
+ 80004b8: d92d bls.n 8000516 <__udivmoddi4+0x2ae>
+ 80004ba: 3f02 subs r7, #2
+ 80004bc: 4429 add r1, r5
+ 80004be: 1acb subs r3, r1, r3
+ 80004c0: b281 uxth r1, r0
+ 80004c2: fbb3 f0fe udiv r0, r3, lr
+ 80004c6: fb0e 3310 mls r3, lr, r0, r3
+ 80004ca: ea41 4103 orr.w r1, r1, r3, lsl #16
+ 80004ce: fb00 f308 mul.w r3, r0, r8
+ 80004d2: 428b cmp r3, r1
+ 80004d4: d907 bls.n 80004e6 <__udivmoddi4+0x27e>
+ 80004d6: 1869 adds r1, r5, r1
+ 80004d8: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
+ 80004dc: d217 bcs.n 800050e <__udivmoddi4+0x2a6>
+ 80004de: 428b cmp r3, r1
+ 80004e0: d915 bls.n 800050e <__udivmoddi4+0x2a6>
+ 80004e2: 3802 subs r0, #2
+ 80004e4: 4429 add r1, r5
+ 80004e6: 1ac9 subs r1, r1, r3
+ 80004e8: ea40 4707 orr.w r7, r0, r7, lsl #16
+ 80004ec: e73b b.n 8000366 <__udivmoddi4+0xfe>
+ 80004ee: 4637 mov r7, r6
+ 80004f0: 4630 mov r0, r6
+ 80004f2: e709 b.n 8000308 <__udivmoddi4+0xa0>
+ 80004f4: 4607 mov r7, r0
+ 80004f6: e6e7 b.n 80002c8 <__udivmoddi4+0x60>
+ 80004f8: 4618 mov r0, r3
+ 80004fa: e6fb b.n 80002f4 <__udivmoddi4+0x8c>
+ 80004fc: 4541 cmp r1, r8
+ 80004fe: d2ab bcs.n 8000458 <__udivmoddi4+0x1f0>
+ 8000500: ebb8 0a02 subs.w sl, r8, r2
+ 8000504: eb69 020e sbc.w r2, r9, lr
+ 8000508: 3801 subs r0, #1
+ 800050a: 4613 mov r3, r2
+ 800050c: e7a4 b.n 8000458 <__udivmoddi4+0x1f0>
+ 800050e: 4660 mov r0, ip
+ 8000510: e7e9 b.n 80004e6 <__udivmoddi4+0x27e>
+ 8000512: 4618 mov r0, r3
+ 8000514: e795 b.n 8000442 <__udivmoddi4+0x1da>
+ 8000516: 4667 mov r7, ip
+ 8000518: e7d1 b.n 80004be <__udivmoddi4+0x256>
+ 800051a: 4681 mov r9, r0
+ 800051c: e77c b.n 8000418 <__udivmoddi4+0x1b0>
+ 800051e: 3802 subs r0, #2
+ 8000520: 442c add r4, r5
+ 8000522: e747 b.n 80003b4 <__udivmoddi4+0x14c>
+ 8000524: f1ac 0c02 sub.w ip, ip, #2
+ 8000528: 442b add r3, r5
+ 800052a: e72f b.n 800038c <__udivmoddi4+0x124>
+ 800052c: 4638 mov r0, r7
+ 800052e: e708 b.n 8000342 <__udivmoddi4+0xda>
+ 8000530: 4637 mov r7, r6
+ 8000532: e6e9 b.n 8000308 <__udivmoddi4+0xa0>
+
+08000534 <__aeabi_idiv0>:
+ 8000534: 4770 bx lr
+ 8000536: bf00 nop
+
+08000538 <main>:
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ 8000538: b580 push {r7, lr}
+ 800053a: af00 add r7, sp, #0
+
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ 800053c: f000 fad1 bl 8000ae2 <HAL_Init>
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+ 8000540: f000 f832 bl 80005a8 <SystemClock_Config>
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ 8000544: f000 f92a bl 800079c <MX_GPIO_Init>
+ MX_USART6_UART_Init();
+ 8000548: f000 f8f6 bl 8000738 <MX_USART6_UART_Init>
+ MX_TIM3_Init();
+ 800054c: f000 f8a6 bl 800069c <MX_TIM3_Init>
+ /* USER CODE BEGIN 2 */
+
+ odom_msg.angular_velocity = 0.2;
+ 8000550: 4b0d ldr r3, [pc, #52] ; (8000588 <main+0x50>)
+ 8000552: 4a0e ldr r2, [pc, #56] ; (800058c <main+0x54>)
+ 8000554: 601a str r2, [r3, #0]
+ odom_msg.linear_velocity = 1.5;
+ 8000556: 4b0c ldr r3, [pc, #48] ; (8000588 <main+0x50>)
+ 8000558: f04f 527f mov.w r2, #1069547520 ; 0x3fc00000
+ 800055c: 605a str r2, [r3, #4]
+ odom_msg.delta_time = 2.6;
+ 800055e: 4b0a ldr r3, [pc, #40] ; (8000588 <main+0x50>)
+ 8000560: 4a0b ldr r2, [pc, #44] ; (8000590 <main+0x58>)
+ 8000562: 609a str r2, [r3, #8]
+
+ tx_buffer = (uint8_t *) &odom_msg;
+ 8000564: 4b0b ldr r3, [pc, #44] ; (8000594 <main+0x5c>)
+ 8000566: 4a08 ldr r2, [pc, #32] ; (8000588 <main+0x50>)
+ 8000568: 601a str r2, [r3, #0]
+ rx_buffer = (uint8_t*) &vel_msg;
+ 800056a: 4b0b ldr r3, [pc, #44] ; (8000598 <main+0x60>)
+ 800056c: 4a0b ldr r2, [pc, #44] ; (800059c <main+0x64>)
+ 800056e: 601a str r2, [r3, #0]
+
+ HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
+ 8000570: 4b09 ldr r3, [pc, #36] ; (8000598 <main+0x60>)
+ 8000572: 681b ldr r3, [r3, #0]
+ 8000574: 2208 movs r2, #8
+ 8000576: 4619 mov r1, r3
+ 8000578: 4809 ldr r0, [pc, #36] ; (80005a0 <main+0x68>)
+ 800057a: f002 fb3f bl 8002bfc <HAL_UART_Receive_IT>
+
+ HAL_TIM_Base_Start_IT(&htim3);
+ 800057e: 4809 ldr r0, [pc, #36] ; (80005a4 <main+0x6c>)
+ 8000580: f001 fe7c bl 800227c <HAL_TIM_Base_Start_IT>
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1) {
+ 8000584: e7fe b.n 8000584 <main+0x4c>
+ 8000586: bf00 nop
+ 8000588: 20000034 .word 0x20000034
+ 800058c: 3e4ccccd .word 0x3e4ccccd
+ 8000590: 40266666 .word 0x40266666
+ 8000594: 20000084 .word 0x20000084
+ 8000598: 20000080 .word 0x20000080
+ 800059c: 2000002c .word 0x2000002c
+ 80005a0: 20000088 .word 0x20000088
+ 80005a4: 20000040 .word 0x20000040
+
+080005a8 <SystemClock_Config>:
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ 80005a8: b580 push {r7, lr}
+ 80005aa: b0b8 sub sp, #224 ; 0xe0
+ 80005ac: af00 add r7, sp, #0
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 80005ae: f107 03ac add.w r3, r7, #172 ; 0xac
+ 80005b2: 2234 movs r2, #52 ; 0x34
+ 80005b4: 2100 movs r1, #0
+ 80005b6: 4618 mov r0, r3
+ 80005b8: f003 f9be bl 8003938 <memset>
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 80005bc: f107 0398 add.w r3, r7, #152 ; 0x98
+ 80005c0: 2200 movs r2, #0
+ 80005c2: 601a str r2, [r3, #0]
+ 80005c4: 605a str r2, [r3, #4]
+ 80005c6: 609a str r2, [r3, #8]
+ 80005c8: 60da str r2, [r3, #12]
+ 80005ca: 611a str r2, [r3, #16]
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 80005cc: f107 0308 add.w r3, r7, #8
+ 80005d0: 2290 movs r2, #144 ; 0x90
+ 80005d2: 2100 movs r1, #0
+ 80005d4: 4618 mov r0, r3
+ 80005d6: f003 f9af bl 8003938 <memset>
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 80005da: 4b2e ldr r3, [pc, #184] ; (8000694 <SystemClock_Config+0xec>)
+ 80005dc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80005de: 4a2d ldr r2, [pc, #180] ; (8000694 <SystemClock_Config+0xec>)
+ 80005e0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 80005e4: 6413 str r3, [r2, #64] ; 0x40
+ 80005e6: 4b2b ldr r3, [pc, #172] ; (8000694 <SystemClock_Config+0xec>)
+ 80005e8: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80005ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 80005ee: 607b str r3, [r7, #4]
+ 80005f0: 687b ldr r3, [r7, #4]
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+ 80005f2: 4b29 ldr r3, [pc, #164] ; (8000698 <SystemClock_Config+0xf0>)
+ 80005f4: 681b ldr r3, [r3, #0]
+ 80005f6: f423 4340 bic.w r3, r3, #49152 ; 0xc000
+ 80005fa: 4a27 ldr r2, [pc, #156] ; (8000698 <SystemClock_Config+0xf0>)
+ 80005fc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000600: 6013 str r3, [r2, #0]
+ 8000602: 4b25 ldr r3, [pc, #148] ; (8000698 <SystemClock_Config+0xf0>)
+ 8000604: 681b ldr r3, [r3, #0]
+ 8000606: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 800060a: 603b str r3, [r7, #0]
+ 800060c: 683b ldr r3, [r7, #0]
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ 800060e: 2302 movs r3, #2
+ 8000610: f8c7 30ac str.w r3, [r7, #172] ; 0xac
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ 8000614: 2301 movs r3, #1
+ 8000616: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ 800061a: 2310 movs r3, #16
+ 800061c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ 8000620: 2300 movs r3, #0
+ 8000622: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 8000626: f107 03ac add.w r3, r7, #172 ; 0xac
+ 800062a: 4618 mov r0, r3
+ 800062c: f000 fd94 bl 8001158 <HAL_RCC_OscConfig>
+ 8000630: 4603 mov r3, r0
+ 8000632: 2b00 cmp r3, #0
+ 8000634: d001 beq.n 800063a <SystemClock_Config+0x92>
+ {
+ Error_Handler();
+ 8000636: f000 f915 bl 8000864 <Error_Handler>
+ }
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 800063a: 230f movs r3, #15
+ 800063c: f8c7 3098 str.w r3, [r7, #152] ; 0x98
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ 8000640: 2300 movs r3, #0
+ 8000642: f8c7 309c str.w r3, [r7, #156] ; 0x9c
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 8000646: 2300 movs r3, #0
+ 8000648: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 800064c: 2300 movs r3, #0
+ 800064e: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 8000652: 2300 movs r3, #0
+ 8000654: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ 8000658: f107 0398 add.w r3, r7, #152 ; 0x98
+ 800065c: 2100 movs r1, #0
+ 800065e: 4618 mov r0, r3
+ 8000660: f000 ffec bl 800163c <HAL_RCC_ClockConfig>
+ 8000664: 4603 mov r3, r0
+ 8000666: 2b00 cmp r3, #0
+ 8000668: d001 beq.n 800066e <SystemClock_Config+0xc6>
+ {
+ Error_Handler();
+ 800066a: f000 f8fb bl 8000864 <Error_Handler>
+ }
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
+ 800066e: f44f 6300 mov.w r3, #2048 ; 0x800
+ 8000672: 60bb str r3, [r7, #8]
+ PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
+ 8000674: 2300 movs r3, #0
+ 8000676: 663b str r3, [r7, #96] ; 0x60
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8000678: f107 0308 add.w r3, r7, #8
+ 800067c: 4618 mov r0, r3
+ 800067e: f001 f9ab bl 80019d8 <HAL_RCCEx_PeriphCLKConfig>
+ 8000682: 4603 mov r3, r0
+ 8000684: 2b00 cmp r3, #0
+ 8000686: d001 beq.n 800068c <SystemClock_Config+0xe4>
+ {
+ Error_Handler();
+ 8000688: f000 f8ec bl 8000864 <Error_Handler>
+ }
+}
+ 800068c: bf00 nop
+ 800068e: 37e0 adds r7, #224 ; 0xe0
+ 8000690: 46bd mov sp, r7
+ 8000692: bd80 pop {r7, pc}
+ 8000694: 40023800 .word 0x40023800
+ 8000698: 40007000 .word 0x40007000
+
+0800069c <MX_TIM3_Init>:
+ * @brief TIM3 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM3_Init(void)
+{
+ 800069c: b580 push {r7, lr}
+ 800069e: b088 sub sp, #32
+ 80006a0: af00 add r7, sp, #0
+
+ /* USER CODE BEGIN TIM3_Init 0 */
+
+ /* USER CODE END TIM3_Init 0 */
+
+ TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 80006a2: f107 0310 add.w r3, r7, #16
+ 80006a6: 2200 movs r2, #0
+ 80006a8: 601a str r2, [r3, #0]
+ 80006aa: 605a str r2, [r3, #4]
+ 80006ac: 609a str r2, [r3, #8]
+ 80006ae: 60da str r2, [r3, #12]
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 80006b0: 1d3b adds r3, r7, #4
+ 80006b2: 2200 movs r2, #0
+ 80006b4: 601a str r2, [r3, #0]
+ 80006b6: 605a str r2, [r3, #4]
+ 80006b8: 609a str r2, [r3, #8]
+
+ /* USER CODE BEGIN TIM3_Init 1 */
+
+ /* USER CODE END TIM3_Init 1 */
+ htim3.Instance = TIM3;
+ 80006ba: 4b1d ldr r3, [pc, #116] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006bc: 4a1d ldr r2, [pc, #116] ; (8000734 <MX_TIM3_Init+0x98>)
+ 80006be: 601a str r2, [r3, #0]
+ htim3.Init.Prescaler = 39999;
+ 80006c0: 4b1b ldr r3, [pc, #108] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006c2: f649 423f movw r2, #39999 ; 0x9c3f
+ 80006c6: 605a str r2, [r3, #4]
+ htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 80006c8: 4b19 ldr r3, [pc, #100] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006ca: 2200 movs r2, #0
+ 80006cc: 609a str r2, [r3, #8]
+ htim3.Init.Period = 9;
+ 80006ce: 4b18 ldr r3, [pc, #96] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006d0: 2209 movs r2, #9
+ 80006d2: 60da str r2, [r3, #12]
+ htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 80006d4: 4b16 ldr r3, [pc, #88] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006d6: 2200 movs r2, #0
+ 80006d8: 611a str r2, [r3, #16]
+ htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 80006da: 4b15 ldr r3, [pc, #84] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006dc: 2200 movs r2, #0
+ 80006de: 619a str r2, [r3, #24]
+ if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+ 80006e0: 4813 ldr r0, [pc, #76] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006e2: f001 fd9f bl 8002224 <HAL_TIM_Base_Init>
+ 80006e6: 4603 mov r3, r0
+ 80006e8: 2b00 cmp r3, #0
+ 80006ea: d001 beq.n 80006f0 <MX_TIM3_Init+0x54>
+ {
+ Error_Handler();
+ 80006ec: f000 f8ba bl 8000864 <Error_Handler>
+ }
+ sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 80006f0: f44f 5380 mov.w r3, #4096 ; 0x1000
+ 80006f4: 613b str r3, [r7, #16]
+ if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+ 80006f6: f107 0310 add.w r3, r7, #16
+ 80006fa: 4619 mov r1, r3
+ 80006fc: 480c ldr r0, [pc, #48] ; (8000730 <MX_TIM3_Init+0x94>)
+ 80006fe: f001 ff07 bl 8002510 <HAL_TIM_ConfigClockSource>
+ 8000702: 4603 mov r3, r0
+ 8000704: 2b00 cmp r3, #0
+ 8000706: d001 beq.n 800070c <MX_TIM3_Init+0x70>
+ {
+ Error_Handler();
+ 8000708: f000 f8ac bl 8000864 <Error_Handler>
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 800070c: 2300 movs r3, #0
+ 800070e: 607b str r3, [r7, #4]
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8000710: 2300 movs r3, #0
+ 8000712: 60fb str r3, [r7, #12]
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 8000714: 1d3b adds r3, r7, #4
+ 8000716: 4619 mov r1, r3
+ 8000718: 4805 ldr r0, [pc, #20] ; (8000730 <MX_TIM3_Init+0x94>)
+ 800071a: f002 f915 bl 8002948 <HAL_TIMEx_MasterConfigSynchronization>
+ 800071e: 4603 mov r3, r0
+ 8000720: 2b00 cmp r3, #0
+ 8000722: d001 beq.n 8000728 <MX_TIM3_Init+0x8c>
+ {
+ Error_Handler();
+ 8000724: f000 f89e bl 8000864 <Error_Handler>
+ }
+ /* USER CODE BEGIN TIM3_Init 2 */
+
+ /* USER CODE END TIM3_Init 2 */
+
+}
+ 8000728: bf00 nop
+ 800072a: 3720 adds r7, #32
+ 800072c: 46bd mov sp, r7
+ 800072e: bd80 pop {r7, pc}
+ 8000730: 20000040 .word 0x20000040
+ 8000734: 40000400 .word 0x40000400
+
+08000738 <MX_USART6_UART_Init>:
+ * @brief USART6 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USART6_UART_Init(void)
+{
+ 8000738: b580 push {r7, lr}
+ 800073a: af00 add r7, sp, #0
+ /* USER CODE END USART6_Init 0 */
+
+ /* USER CODE BEGIN USART6_Init 1 */
+
+ /* USER CODE END USART6_Init 1 */
+ huart6.Instance = USART6;
+ 800073c: 4b15 ldr r3, [pc, #84] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 800073e: 4a16 ldr r2, [pc, #88] ; (8000798 <MX_USART6_UART_Init+0x60>)
+ 8000740: 601a str r2, [r3, #0]
+ huart6.Init.BaudRate = 115200;
+ 8000742: 4b14 ldr r3, [pc, #80] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 8000744: f44f 32e1 mov.w r2, #115200 ; 0x1c200
+ 8000748: 605a str r2, [r3, #4]
+ huart6.Init.WordLength = UART_WORDLENGTH_9B;
+ 800074a: 4b12 ldr r3, [pc, #72] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 800074c: f44f 5280 mov.w r2, #4096 ; 0x1000
+ 8000750: 609a str r2, [r3, #8]
+ huart6.Init.StopBits = UART_STOPBITS_1;
+ 8000752: 4b10 ldr r3, [pc, #64] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 8000754: 2200 movs r2, #0
+ 8000756: 60da str r2, [r3, #12]
+ huart6.Init.Parity = UART_PARITY_ODD;
+ 8000758: 4b0e ldr r3, [pc, #56] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 800075a: f44f 62c0 mov.w r2, #1536 ; 0x600
+ 800075e: 611a str r2, [r3, #16]
+ huart6.Init.Mode = UART_MODE_TX_RX;
+ 8000760: 4b0c ldr r3, [pc, #48] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 8000762: 220c movs r2, #12
+ 8000764: 615a str r2, [r3, #20]
+ huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8000766: 4b0b ldr r3, [pc, #44] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 8000768: 2200 movs r2, #0
+ 800076a: 619a str r2, [r3, #24]
+ huart6.Init.OverSampling = UART_OVERSAMPLING_16;
+ 800076c: 4b09 ldr r3, [pc, #36] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 800076e: 2200 movs r2, #0
+ 8000770: 61da str r2, [r3, #28]
+ huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8000772: 4b08 ldr r3, [pc, #32] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 8000774: 2200 movs r2, #0
+ 8000776: 621a str r2, [r3, #32]
+ huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8000778: 4b06 ldr r3, [pc, #24] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 800077a: 2200 movs r2, #0
+ 800077c: 625a str r2, [r3, #36] ; 0x24
+ if (HAL_UART_Init(&huart6) != HAL_OK)
+ 800077e: 4805 ldr r0, [pc, #20] ; (8000794 <MX_USART6_UART_Init+0x5c>)
+ 8000780: f002 f95c bl 8002a3c <HAL_UART_Init>
+ 8000784: 4603 mov r3, r0
+ 8000786: 2b00 cmp r3, #0
+ 8000788: d001 beq.n 800078e <MX_USART6_UART_Init+0x56>
+ {
+ Error_Handler();
+ 800078a: f000 f86b bl 8000864 <Error_Handler>
+ }
+ /* USER CODE BEGIN USART6_Init 2 */
+
+ /* USER CODE END USART6_Init 2 */
+
+}
+ 800078e: bf00 nop
+ 8000790: bd80 pop {r7, pc}
+ 8000792: bf00 nop
+ 8000794: 20000088 .word 0x20000088
+ 8000798: 40011400 .word 0x40011400
+
+0800079c <MX_GPIO_Init>:
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ 800079c: b480 push {r7}
+ 800079e: b083 sub sp, #12
+ 80007a0: af00 add r7, sp, #0
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ 80007a2: 4b0f ldr r3, [pc, #60] ; (80007e0 <MX_GPIO_Init+0x44>)
+ 80007a4: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80007a6: 4a0e ldr r2, [pc, #56] ; (80007e0 <MX_GPIO_Init+0x44>)
+ 80007a8: f043 0304 orr.w r3, r3, #4
+ 80007ac: 6313 str r3, [r2, #48] ; 0x30
+ 80007ae: 4b0c ldr r3, [pc, #48] ; (80007e0 <MX_GPIO_Init+0x44>)
+ 80007b0: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80007b2: f003 0304 and.w r3, r3, #4
+ 80007b6: 607b str r3, [r7, #4]
+ 80007b8: 687b ldr r3, [r7, #4]
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80007ba: 4b09 ldr r3, [pc, #36] ; (80007e0 <MX_GPIO_Init+0x44>)
+ 80007bc: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80007be: 4a08 ldr r2, [pc, #32] ; (80007e0 <MX_GPIO_Init+0x44>)
+ 80007c0: f043 0301 orr.w r3, r3, #1
+ 80007c4: 6313 str r3, [r2, #48] ; 0x30
+ 80007c6: 4b06 ldr r3, [pc, #24] ; (80007e0 <MX_GPIO_Init+0x44>)
+ 80007c8: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80007ca: f003 0301 and.w r3, r3, #1
+ 80007ce: 603b str r3, [r7, #0]
+ 80007d0: 683b ldr r3, [r7, #0]
+
+}
+ 80007d2: bf00 nop
+ 80007d4: 370c adds r7, #12
+ 80007d6: 46bd mov sp, r7
+ 80007d8: f85d 7b04 ldr.w r7, [sp], #4
+ 80007dc: 4770 bx lr
+ 80007de: bf00 nop
+ 80007e0: 40023800 .word 0x40023800
+
+080007e4 <HAL_TIM_PeriodElapsedCallback>:
+
+/* USER CODE BEGIN 4 */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
+ 80007e4: b580 push {r7, lr}
+ 80007e6: b082 sub sp, #8
+ 80007e8: af00 add r7, sp, #0
+ 80007ea: 6078 str r0, [r7, #4]
+ if (htim->Instance == TIM3) {
+ 80007ec: 687b ldr r3, [r7, #4]
+ 80007ee: 681b ldr r3, [r3, #0]
+ 80007f0: 4a09 ldr r2, [pc, #36] ; (8000818 <HAL_TIM_PeriodElapsedCallback+0x34>)
+ 80007f2: 4293 cmp r3, r2
+ 80007f4: d10b bne.n 800080e <HAL_TIM_PeriodElapsedCallback+0x2a>
+ HAL_UART_Transmit(&huart6, tx_buffer, 12, 100);
+ 80007f6: 4b09 ldr r3, [pc, #36] ; (800081c <HAL_TIM_PeriodElapsedCallback+0x38>)
+ 80007f8: 6819 ldr r1, [r3, #0]
+ 80007fa: 2364 movs r3, #100 ; 0x64
+ 80007fc: 220c movs r2, #12
+ 80007fe: 4808 ldr r0, [pc, #32] ; (8000820 <HAL_TIM_PeriodElapsedCallback+0x3c>)
+ 8000800: f002 f96a bl 8002ad8 <HAL_UART_Transmit>
+ test++;
+ 8000804: 4b07 ldr r3, [pc, #28] ; (8000824 <HAL_TIM_PeriodElapsedCallback+0x40>)
+ 8000806: 681b ldr r3, [r3, #0]
+ 8000808: 3301 adds r3, #1
+ 800080a: 4a06 ldr r2, [pc, #24] ; (8000824 <HAL_TIM_PeriodElapsedCallback+0x40>)
+ 800080c: 6013 str r3, [r2, #0]
+ }
+}
+ 800080e: bf00 nop
+ 8000810: 3708 adds r7, #8
+ 8000812: 46bd mov sp, r7
+ 8000814: bd80 pop {r7, pc}
+ 8000816: bf00 nop
+ 8000818: 40000400 .word 0x40000400
+ 800081c: 20000084 .word 0x20000084
+ 8000820: 20000088 .word 0x20000088
+ 8000824: 20000028 .word 0x20000028
+
+08000828 <HAL_UART_RxCpltCallback>:
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle) {
+ 8000828: b580 push {r7, lr}
+ 800082a: b082 sub sp, #8
+ 800082c: af00 add r7, sp, #0
+ 800082e: 6078 str r0, [r7, #4]
+ HAL_UART_Receive_IT(&huart6, rx_buffer, 8);
+ 8000830: 4b05 ldr r3, [pc, #20] ; (8000848 <HAL_UART_RxCpltCallback+0x20>)
+ 8000832: 681b ldr r3, [r3, #0]
+ 8000834: 2208 movs r2, #8
+ 8000836: 4619 mov r1, r3
+ 8000838: 4804 ldr r0, [pc, #16] ; (800084c <HAL_UART_RxCpltCallback+0x24>)
+ 800083a: f002 f9df bl 8002bfc <HAL_UART_Receive_IT>
+}
+ 800083e: bf00 nop
+ 8000840: 3708 adds r7, #8
+ 8000842: 46bd mov sp, r7
+ 8000844: bd80 pop {r7, pc}
+ 8000846: bf00 nop
+ 8000848: 20000080 .word 0x20000080
+ 800084c: 20000088 .word 0x20000088
+
+08000850 <HAL_UART_ErrorCallback>:
+
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle){
+ 8000850: b480 push {r7}
+ 8000852: b083 sub sp, #12
+ 8000854: af00 add r7, sp, #0
+ 8000856: 6078 str r0, [r7, #4]
+ //TODO
+}
+ 8000858: bf00 nop
+ 800085a: 370c adds r7, #12
+ 800085c: 46bd mov sp, r7
+ 800085e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000862: 4770 bx lr
+
+08000864 <Error_Handler>:
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ 8000864: b480 push {r7}
+ 8000866: af00 add r7, sp, #0
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+
+ /* USER CODE END Error_Handler_Debug */
+}
+ 8000868: bf00 nop
+ 800086a: 46bd mov sp, r7
+ 800086c: f85d 7b04 ldr.w r7, [sp], #4
+ 8000870: 4770 bx lr
+ ...
+
+08000874 <HAL_MspInit>:
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ 8000874: b480 push {r7}
+ 8000876: b083 sub sp, #12
+ 8000878: af00 add r7, sp, #0
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 800087a: 4b0f ldr r3, [pc, #60] ; (80008b8 <HAL_MspInit+0x44>)
+ 800087c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800087e: 4a0e ldr r2, [pc, #56] ; (80008b8 <HAL_MspInit+0x44>)
+ 8000880: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000884: 6413 str r3, [r2, #64] ; 0x40
+ 8000886: 4b0c ldr r3, [pc, #48] ; (80008b8 <HAL_MspInit+0x44>)
+ 8000888: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800088a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 800088e: 607b str r3, [r7, #4]
+ 8000890: 687b ldr r3, [r7, #4]
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8000892: 4b09 ldr r3, [pc, #36] ; (80008b8 <HAL_MspInit+0x44>)
+ 8000894: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000896: 4a08 ldr r2, [pc, #32] ; (80008b8 <HAL_MspInit+0x44>)
+ 8000898: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 800089c: 6453 str r3, [r2, #68] ; 0x44
+ 800089e: 4b06 ldr r3, [pc, #24] ; (80008b8 <HAL_MspInit+0x44>)
+ 80008a0: 6c5b ldr r3, [r3, #68] ; 0x44
+ 80008a2: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 80008a6: 603b str r3, [r7, #0]
+ 80008a8: 683b ldr r3, [r7, #0]
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+ 80008aa: bf00 nop
+ 80008ac: 370c adds r7, #12
+ 80008ae: 46bd mov sp, r7
+ 80008b0: f85d 7b04 ldr.w r7, [sp], #4
+ 80008b4: 4770 bx lr
+ 80008b6: bf00 nop
+ 80008b8: 40023800 .word 0x40023800
+
+080008bc <HAL_TIM_Base_MspInit>:
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+ 80008bc: b580 push {r7, lr}
+ 80008be: b084 sub sp, #16
+ 80008c0: af00 add r7, sp, #0
+ 80008c2: 6078 str r0, [r7, #4]
+ if(htim_base->Instance==TIM3)
+ 80008c4: 687b ldr r3, [r7, #4]
+ 80008c6: 681b ldr r3, [r3, #0]
+ 80008c8: 4a0d ldr r2, [pc, #52] ; (8000900 <HAL_TIM_Base_MspInit+0x44>)
+ 80008ca: 4293 cmp r3, r2
+ 80008cc: d113 bne.n 80008f6 <HAL_TIM_Base_MspInit+0x3a>
+ {
+ /* USER CODE BEGIN TIM3_MspInit 0 */
+
+ /* USER CODE END TIM3_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM3_CLK_ENABLE();
+ 80008ce: 4b0d ldr r3, [pc, #52] ; (8000904 <HAL_TIM_Base_MspInit+0x48>)
+ 80008d0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80008d2: 4a0c ldr r2, [pc, #48] ; (8000904 <HAL_TIM_Base_MspInit+0x48>)
+ 80008d4: f043 0302 orr.w r3, r3, #2
+ 80008d8: 6413 str r3, [r2, #64] ; 0x40
+ 80008da: 4b0a ldr r3, [pc, #40] ; (8000904 <HAL_TIM_Base_MspInit+0x48>)
+ 80008dc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80008de: f003 0302 and.w r3, r3, #2
+ 80008e2: 60fb str r3, [r7, #12]
+ 80008e4: 68fb ldr r3, [r7, #12]
+ /* TIM3 interrupt Init */
+ HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
+ 80008e6: 2200 movs r2, #0
+ 80008e8: 2100 movs r1, #0
+ 80008ea: 201d movs r0, #29
+ 80008ec: f000 fa31 bl 8000d52 <HAL_NVIC_SetPriority>
+ HAL_NVIC_EnableIRQ(TIM3_IRQn);
+ 80008f0: 201d movs r0, #29
+ 80008f2: f000 fa4a bl 8000d8a <HAL_NVIC_EnableIRQ>
+ /* USER CODE BEGIN TIM3_MspInit 1 */
+
+ /* USER CODE END TIM3_MspInit 1 */
+ }
+
+}
+ 80008f6: bf00 nop
+ 80008f8: 3710 adds r7, #16
+ 80008fa: 46bd mov sp, r7
+ 80008fc: bd80 pop {r7, pc}
+ 80008fe: bf00 nop
+ 8000900: 40000400 .word 0x40000400
+ 8000904: 40023800 .word 0x40023800
+
+08000908 <HAL_UART_MspInit>:
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ 8000908: b580 push {r7, lr}
+ 800090a: b08a sub sp, #40 ; 0x28
+ 800090c: af00 add r7, sp, #0
+ 800090e: 6078 str r0, [r7, #4]
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000910: f107 0314 add.w r3, r7, #20
+ 8000914: 2200 movs r2, #0
+ 8000916: 601a str r2, [r3, #0]
+ 8000918: 605a str r2, [r3, #4]
+ 800091a: 609a str r2, [r3, #8]
+ 800091c: 60da str r2, [r3, #12]
+ 800091e: 611a str r2, [r3, #16]
+ if(huart->Instance==USART6)
+ 8000920: 687b ldr r3, [r7, #4]
+ 8000922: 681b ldr r3, [r3, #0]
+ 8000924: 4a1b ldr r2, [pc, #108] ; (8000994 <HAL_UART_MspInit+0x8c>)
+ 8000926: 4293 cmp r3, r2
+ 8000928: d12f bne.n 800098a <HAL_UART_MspInit+0x82>
+ {
+ /* USER CODE BEGIN USART6_MspInit 0 */
+
+ /* USER CODE END USART6_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_USART6_CLK_ENABLE();
+ 800092a: 4b1b ldr r3, [pc, #108] ; (8000998 <HAL_UART_MspInit+0x90>)
+ 800092c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800092e: 4a1a ldr r2, [pc, #104] ; (8000998 <HAL_UART_MspInit+0x90>)
+ 8000930: f043 0320 orr.w r3, r3, #32
+ 8000934: 6453 str r3, [r2, #68] ; 0x44
+ 8000936: 4b18 ldr r3, [pc, #96] ; (8000998 <HAL_UART_MspInit+0x90>)
+ 8000938: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800093a: f003 0320 and.w r3, r3, #32
+ 800093e: 613b str r3, [r7, #16]
+ 8000940: 693b ldr r3, [r7, #16]
+
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ 8000942: 4b15 ldr r3, [pc, #84] ; (8000998 <HAL_UART_MspInit+0x90>)
+ 8000944: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000946: 4a14 ldr r2, [pc, #80] ; (8000998 <HAL_UART_MspInit+0x90>)
+ 8000948: f043 0304 orr.w r3, r3, #4
+ 800094c: 6313 str r3, [r2, #48] ; 0x30
+ 800094e: 4b12 ldr r3, [pc, #72] ; (8000998 <HAL_UART_MspInit+0x90>)
+ 8000950: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000952: f003 0304 and.w r3, r3, #4
+ 8000956: 60fb str r3, [r7, #12]
+ 8000958: 68fb ldr r3, [r7, #12]
+ /**USART6 GPIO Configuration
+ PC6 ------> USART6_TX
+ PC7 ------> USART6_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+ 800095a: 23c0 movs r3, #192 ; 0xc0
+ 800095c: 617b str r3, [r7, #20]
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800095e: 2302 movs r3, #2
+ 8000960: 61bb str r3, [r7, #24]
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8000962: 2300 movs r3, #0
+ 8000964: 61fb str r3, [r7, #28]
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000966: 2303 movs r3, #3
+ 8000968: 623b str r3, [r7, #32]
+ GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
+ 800096a: 2308 movs r3, #8
+ 800096c: 627b str r3, [r7, #36] ; 0x24
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 800096e: f107 0314 add.w r3, r7, #20
+ 8000972: 4619 mov r1, r3
+ 8000974: 4809 ldr r0, [pc, #36] ; (800099c <HAL_UART_MspInit+0x94>)
+ 8000976: f000 fa45 bl 8000e04 <HAL_GPIO_Init>
+
+ /* USART6 interrupt Init */
+ HAL_NVIC_SetPriority(USART6_IRQn, 0, 0);
+ 800097a: 2200 movs r2, #0
+ 800097c: 2100 movs r1, #0
+ 800097e: 2047 movs r0, #71 ; 0x47
+ 8000980: f000 f9e7 bl 8000d52 <HAL_NVIC_SetPriority>
+ HAL_NVIC_EnableIRQ(USART6_IRQn);
+ 8000984: 2047 movs r0, #71 ; 0x47
+ 8000986: f000 fa00 bl 8000d8a <HAL_NVIC_EnableIRQ>
+ /* USER CODE BEGIN USART6_MspInit 1 */
+
+ /* USER CODE END USART6_MspInit 1 */
+ }
+
+}
+ 800098a: bf00 nop
+ 800098c: 3728 adds r7, #40 ; 0x28
+ 800098e: 46bd mov sp, r7
+ 8000990: bd80 pop {r7, pc}
+ 8000992: bf00 nop
+ 8000994: 40011400 .word 0x40011400
+ 8000998: 40023800 .word 0x40023800
+ 800099c: 40020800 .word 0x40020800
+
+080009a0 <NMI_Handler>:
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ 80009a0: b480 push {r7}
+ 80009a2: af00 add r7, sp, #0
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+ 80009a4: bf00 nop
+ 80009a6: 46bd mov sp, r7
+ 80009a8: f85d 7b04 ldr.w r7, [sp], #4
+ 80009ac: 4770 bx lr
+
+080009ae <HardFault_Handler>:
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ 80009ae: b480 push {r7}
+ 80009b0: af00 add r7, sp, #0
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ 80009b2: e7fe b.n 80009b2 <HardFault_Handler+0x4>
+
+080009b4 <MemManage_Handler>:
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ 80009b4: b480 push {r7}
+ 80009b6: af00 add r7, sp, #0
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ 80009b8: e7fe b.n 80009b8 <MemManage_Handler+0x4>
+
+080009ba <BusFault_Handler>:
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ 80009ba: b480 push {r7}
+ 80009bc: af00 add r7, sp, #0
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ 80009be: e7fe b.n 80009be <BusFault_Handler+0x4>
+
+080009c0 <UsageFault_Handler>:
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ 80009c0: b480 push {r7}
+ 80009c2: af00 add r7, sp, #0
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ 80009c4: e7fe b.n 80009c4 <UsageFault_Handler+0x4>
+
+080009c6 <SVC_Handler>:
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ 80009c6: b480 push {r7}
+ 80009c8: af00 add r7, sp, #0
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+ 80009ca: bf00 nop
+ 80009cc: 46bd mov sp, r7
+ 80009ce: f85d 7b04 ldr.w r7, [sp], #4
+ 80009d2: 4770 bx lr
+
+080009d4 <DebugMon_Handler>:
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ 80009d4: b480 push {r7}
+ 80009d6: af00 add r7, sp, #0
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+ 80009d8: bf00 nop
+ 80009da: 46bd mov sp, r7
+ 80009dc: f85d 7b04 ldr.w r7, [sp], #4
+ 80009e0: 4770 bx lr
+
+080009e2 <PendSV_Handler>:
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ 80009e2: b480 push {r7}
+ 80009e4: af00 add r7, sp, #0
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+ 80009e6: bf00 nop
+ 80009e8: 46bd mov sp, r7
+ 80009ea: f85d 7b04 ldr.w r7, [sp], #4
+ 80009ee: 4770 bx lr
+
+080009f0 <SysTick_Handler>:
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ 80009f0: b580 push {r7, lr}
+ 80009f2: af00 add r7, sp, #0
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ 80009f4: f000 f8b2 bl 8000b5c <HAL_IncTick>
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+ 80009f8: bf00 nop
+ 80009fa: bd80 pop {r7, pc}
+
+080009fc <TIM3_IRQHandler>:
+
+/**
+ * @brief This function handles TIM3 global interrupt.
+ */
+void TIM3_IRQHandler(void)
+{
+ 80009fc: b580 push {r7, lr}
+ 80009fe: af00 add r7, sp, #0
+ /* USER CODE BEGIN TIM3_IRQn 0 */
+
+ /* USER CODE END TIM3_IRQn 0 */
+ HAL_TIM_IRQHandler(&htim3);
+ 8000a00: 4802 ldr r0, [pc, #8] ; (8000a0c <TIM3_IRQHandler+0x10>)
+ 8000a02: f001 fc65 bl 80022d0 <HAL_TIM_IRQHandler>
+ /* USER CODE BEGIN TIM3_IRQn 1 */
+
+ /* USER CODE END TIM3_IRQn 1 */
+}
+ 8000a06: bf00 nop
+ 8000a08: bd80 pop {r7, pc}
+ 8000a0a: bf00 nop
+ 8000a0c: 20000040 .word 0x20000040
+
+08000a10 <USART6_IRQHandler>:
+
+/**
+ * @brief This function handles USART6 global interrupt.
+ */
+void USART6_IRQHandler(void)
+{
+ 8000a10: b580 push {r7, lr}
+ 8000a12: af00 add r7, sp, #0
+ /* USER CODE BEGIN USART6_IRQn 0 */
+
+ /* USER CODE END USART6_IRQn 0 */
+ HAL_UART_IRQHandler(&huart6);
+ 8000a14: 4802 ldr r0, [pc, #8] ; (8000a20 <USART6_IRQHandler+0x10>)
+ 8000a16: f002 f993 bl 8002d40 <HAL_UART_IRQHandler>
+ /* USER CODE BEGIN USART6_IRQn 1 */
+
+ /* USER CODE END USART6_IRQn 1 */
+}
+ 8000a1a: bf00 nop
+ 8000a1c: bd80 pop {r7, pc}
+ 8000a1e: bf00 nop
+ 8000a20: 20000088 .word 0x20000088
+
+08000a24 <SystemInit>:
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ 8000a24: b480 push {r7}
+ 8000a26: af00 add r7, sp, #0
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ 8000a28: 4b15 ldr r3, [pc, #84] ; (8000a80 <SystemInit+0x5c>)
+ 8000a2a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8000a2e: 4a14 ldr r2, [pc, #80] ; (8000a80 <SystemInit+0x5c>)
+ 8000a30: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
+ 8000a34: f8c2 3088 str.w r3, [r2, #136] ; 0x88
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+ 8000a38: 4b12 ldr r3, [pc, #72] ; (8000a84 <SystemInit+0x60>)
+ 8000a3a: 681b ldr r3, [r3, #0]
+ 8000a3c: 4a11 ldr r2, [pc, #68] ; (8000a84 <SystemInit+0x60>)
+ 8000a3e: f043 0301 orr.w r3, r3, #1
+ 8000a42: 6013 str r3, [r2, #0]
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+ 8000a44: 4b0f ldr r3, [pc, #60] ; (8000a84 <SystemInit+0x60>)
+ 8000a46: 2200 movs r2, #0
+ 8000a48: 609a str r2, [r3, #8]
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+ 8000a4a: 4b0e ldr r3, [pc, #56] ; (8000a84 <SystemInit+0x60>)
+ 8000a4c: 681a ldr r2, [r3, #0]
+ 8000a4e: 490d ldr r1, [pc, #52] ; (8000a84 <SystemInit+0x60>)
+ 8000a50: 4b0d ldr r3, [pc, #52] ; (8000a88 <SystemInit+0x64>)
+ 8000a52: 4013 ands r3, r2
+ 8000a54: 600b str r3, [r1, #0]
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+ 8000a56: 4b0b ldr r3, [pc, #44] ; (8000a84 <SystemInit+0x60>)
+ 8000a58: 4a0c ldr r2, [pc, #48] ; (8000a8c <SystemInit+0x68>)
+ 8000a5a: 605a str r2, [r3, #4]
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+ 8000a5c: 4b09 ldr r3, [pc, #36] ; (8000a84 <SystemInit+0x60>)
+ 8000a5e: 681b ldr r3, [r3, #0]
+ 8000a60: 4a08 ldr r2, [pc, #32] ; (8000a84 <SystemInit+0x60>)
+ 8000a62: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8000a66: 6013 str r3, [r2, #0]
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+ 8000a68: 4b06 ldr r3, [pc, #24] ; (8000a84 <SystemInit+0x60>)
+ 8000a6a: 2200 movs r2, #0
+ 8000a6c: 60da str r2, [r3, #12]
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ 8000a6e: 4b04 ldr r3, [pc, #16] ; (8000a80 <SystemInit+0x5c>)
+ 8000a70: f04f 6200 mov.w r2, #134217728 ; 0x8000000
+ 8000a74: 609a str r2, [r3, #8]
+#endif
+}
+ 8000a76: bf00 nop
+ 8000a78: 46bd mov sp, r7
+ 8000a7a: f85d 7b04 ldr.w r7, [sp], #4
+ 8000a7e: 4770 bx lr
+ 8000a80: e000ed00 .word 0xe000ed00
+ 8000a84: 40023800 .word 0x40023800
+ 8000a88: fef6ffff .word 0xfef6ffff
+ 8000a8c: 24003010 .word 0x24003010
+
+08000a90 <Reset_Handler>:
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+ 8000a90: f8df d034 ldr.w sp, [pc, #52] ; 8000ac8 <LoopFillZerobss+0x14>
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ 8000a94: 2100 movs r1, #0
+ b LoopCopyDataInit
+ 8000a96: e003 b.n 8000aa0 <LoopCopyDataInit>
+
+08000a98 <CopyDataInit>:
+
+CopyDataInit:
+ ldr r3, =_sidata
+ 8000a98: 4b0c ldr r3, [pc, #48] ; (8000acc <LoopFillZerobss+0x18>)
+ ldr r3, [r3, r1]
+ 8000a9a: 585b ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ 8000a9c: 5043 str r3, [r0, r1]
+ adds r1, r1, #4
+ 8000a9e: 3104 adds r1, #4
+
+08000aa0 <LoopCopyDataInit>:
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ 8000aa0: 480b ldr r0, [pc, #44] ; (8000ad0 <LoopFillZerobss+0x1c>)
+ ldr r3, =_edata
+ 8000aa2: 4b0c ldr r3, [pc, #48] ; (8000ad4 <LoopFillZerobss+0x20>)
+ adds r2, r0, r1
+ 8000aa4: 1842 adds r2, r0, r1
+ cmp r2, r3
+ 8000aa6: 429a cmp r2, r3
+ bcc CopyDataInit
+ 8000aa8: d3f6 bcc.n 8000a98 <CopyDataInit>
+ ldr r2, =_sbss
+ 8000aaa: 4a0b ldr r2, [pc, #44] ; (8000ad8 <LoopFillZerobss+0x24>)
+ b LoopFillZerobss
+ 8000aac: e002 b.n 8000ab4 <LoopFillZerobss>
+
+08000aae <FillZerobss>:
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ 8000aae: 2300 movs r3, #0
+ str r3, [r2], #4
+ 8000ab0: f842 3b04 str.w r3, [r2], #4
+
+08000ab4 <LoopFillZerobss>:
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ 8000ab4: 4b09 ldr r3, [pc, #36] ; (8000adc <LoopFillZerobss+0x28>)
+ cmp r2, r3
+ 8000ab6: 429a cmp r2, r3
+ bcc FillZerobss
+ 8000ab8: d3f9 bcc.n 8000aae <FillZerobss>
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+ 8000aba: f7ff ffb3 bl 8000a24 <SystemInit>
+/* Call static constructors */
+ bl __libc_init_array
+ 8000abe: f002 ff17 bl 80038f0 <__libc_init_array>
+/* Call the application's entry point.*/
+ bl main
+ 8000ac2: f7ff fd39 bl 8000538 <main>
+ bx lr
+ 8000ac6: 4770 bx lr
+ ldr sp, =_estack /* set stack pointer */
+ 8000ac8: 20080000 .word 0x20080000
+ ldr r3, =_sidata
+ 8000acc: 08003988 .word 0x08003988
+ ldr r0, =_sdata
+ 8000ad0: 20000000 .word 0x20000000
+ ldr r3, =_edata
+ 8000ad4: 2000000c .word 0x2000000c
+ ldr r2, =_sbss
+ 8000ad8: 2000000c .word 0x2000000c
+ ldr r3, = _ebss
+ 8000adc: 20000114 .word 0x20000114
+
+08000ae0 <ADC_IRQHandler>:
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ 8000ae0: e7fe b.n 8000ae0 <ADC_IRQHandler>
+
+08000ae2 <HAL_Init>:
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct HAL operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 8000ae2: b580 push {r7, lr}
+ 8000ae4: af00 add r7, sp, #0
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 8000ae6: 2003 movs r0, #3
+ 8000ae8: f000 f928 bl 8000d3c <HAL_NVIC_SetPriorityGrouping>
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+ 8000aec: 2000 movs r0, #0
+ 8000aee: f000 f805 bl 8000afc <HAL_InitTick>
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+ 8000af2: f7ff febf bl 8000874 <HAL_MspInit>
+
+ /* Return function status */
+ return HAL_OK;
+ 8000af6: 2300 movs r3, #0
+}
+ 8000af8: 4618 mov r0, r3
+ 8000afa: bd80 pop {r7, pc}
+
+08000afc <HAL_InitTick>:
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 8000afc: b580 push {r7, lr}
+ 8000afe: b082 sub sp, #8
+ 8000b00: af00 add r7, sp, #0
+ 8000b02: 6078 str r0, [r7, #4]
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 8000b04: 4b12 ldr r3, [pc, #72] ; (8000b50 <HAL_InitTick+0x54>)
+ 8000b06: 681a ldr r2, [r3, #0]
+ 8000b08: 4b12 ldr r3, [pc, #72] ; (8000b54 <HAL_InitTick+0x58>)
+ 8000b0a: 781b ldrb r3, [r3, #0]
+ 8000b0c: 4619 mov r1, r3
+ 8000b0e: f44f 737a mov.w r3, #1000 ; 0x3e8
+ 8000b12: fbb3 f3f1 udiv r3, r3, r1
+ 8000b16: fbb2 f3f3 udiv r3, r2, r3
+ 8000b1a: 4618 mov r0, r3
+ 8000b1c: f000 f943 bl 8000da6 <HAL_SYSTICK_Config>
+ 8000b20: 4603 mov r3, r0
+ 8000b22: 2b00 cmp r3, #0
+ 8000b24: d001 beq.n 8000b2a <HAL_InitTick+0x2e>
+ {
+ return HAL_ERROR;
+ 8000b26: 2301 movs r3, #1
+ 8000b28: e00e b.n 8000b48 <HAL_InitTick+0x4c>
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 8000b2a: 687b ldr r3, [r7, #4]
+ 8000b2c: 2b0f cmp r3, #15
+ 8000b2e: d80a bhi.n 8000b46 <HAL_InitTick+0x4a>
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 8000b30: 2200 movs r2, #0
+ 8000b32: 6879 ldr r1, [r7, #4]
+ 8000b34: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8000b38: f000 f90b bl 8000d52 <HAL_NVIC_SetPriority>
+ uwTickPrio = TickPriority;
+ 8000b3c: 4a06 ldr r2, [pc, #24] ; (8000b58 <HAL_InitTick+0x5c>)
+ 8000b3e: 687b ldr r3, [r7, #4]
+ 8000b40: 6013 str r3, [r2, #0]
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ 8000b42: 2300 movs r3, #0
+ 8000b44: e000 b.n 8000b48 <HAL_InitTick+0x4c>
+ return HAL_ERROR;
+ 8000b46: 2301 movs r3, #1
+}
+ 8000b48: 4618 mov r0, r3
+ 8000b4a: 3708 adds r7, #8
+ 8000b4c: 46bd mov sp, r7
+ 8000b4e: bd80 pop {r7, pc}
+ 8000b50: 20000000 .word 0x20000000
+ 8000b54: 20000008 .word 0x20000008
+ 8000b58: 20000004 .word 0x20000004
+
+08000b5c <HAL_IncTick>:
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ 8000b5c: b480 push {r7}
+ 8000b5e: af00 add r7, sp, #0
+ uwTick += uwTickFreq;
+ 8000b60: 4b06 ldr r3, [pc, #24] ; (8000b7c <HAL_IncTick+0x20>)
+ 8000b62: 781b ldrb r3, [r3, #0]
+ 8000b64: 461a mov r2, r3
+ 8000b66: 4b06 ldr r3, [pc, #24] ; (8000b80 <HAL_IncTick+0x24>)
+ 8000b68: 681b ldr r3, [r3, #0]
+ 8000b6a: 4413 add r3, r2
+ 8000b6c: 4a04 ldr r2, [pc, #16] ; (8000b80 <HAL_IncTick+0x24>)
+ 8000b6e: 6013 str r3, [r2, #0]
+}
+ 8000b70: bf00 nop
+ 8000b72: 46bd mov sp, r7
+ 8000b74: f85d 7b04 ldr.w r7, [sp], #4
+ 8000b78: 4770 bx lr
+ 8000b7a: bf00 nop
+ 8000b7c: 20000008 .word 0x20000008
+ 8000b80: 20000110 .word 0x20000110
+
+08000b84 <HAL_GetTick>:
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ 8000b84: b480 push {r7}
+ 8000b86: af00 add r7, sp, #0
+ return uwTick;
+ 8000b88: 4b03 ldr r3, [pc, #12] ; (8000b98 <HAL_GetTick+0x14>)
+ 8000b8a: 681b ldr r3, [r3, #0]
+}
+ 8000b8c: 4618 mov r0, r3
+ 8000b8e: 46bd mov sp, r7
+ 8000b90: f85d 7b04 ldr.w r7, [sp], #4
+ 8000b94: 4770 bx lr
+ 8000b96: bf00 nop
+ 8000b98: 20000110 .word 0x20000110
+
+08000b9c <__NVIC_SetPriorityGrouping>:
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8000b9c: b480 push {r7}
+ 8000b9e: b085 sub sp, #20
+ 8000ba0: af00 add r7, sp, #0
+ 8000ba2: 6078 str r0, [r7, #4]
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 8000ba4: 687b ldr r3, [r7, #4]
+ 8000ba6: f003 0307 and.w r3, r3, #7
+ 8000baa: 60fb str r3, [r7, #12]
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ 8000bac: 4b0b ldr r3, [pc, #44] ; (8000bdc <__NVIC_SetPriorityGrouping+0x40>)
+ 8000bae: 68db ldr r3, [r3, #12]
+ 8000bb0: 60bb str r3, [r7, #8]
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ 8000bb2: 68ba ldr r2, [r7, #8]
+ 8000bb4: f64f 03ff movw r3, #63743 ; 0xf8ff
+ 8000bb8: 4013 ands r3, r2
+ 8000bba: 60bb str r3, [r7, #8]
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ 8000bbc: 68fb ldr r3, [r7, #12]
+ 8000bbe: 021a lsls r2, r3, #8
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 8000bc0: 68bb ldr r3, [r7, #8]
+ 8000bc2: 431a orrs r2, r3
+ reg_value = (reg_value |
+ 8000bc4: 4b06 ldr r3, [pc, #24] ; (8000be0 <__NVIC_SetPriorityGrouping+0x44>)
+ 8000bc6: 4313 orrs r3, r2
+ 8000bc8: 60bb str r3, [r7, #8]
+ SCB->AIRCR = reg_value;
+ 8000bca: 4a04 ldr r2, [pc, #16] ; (8000bdc <__NVIC_SetPriorityGrouping+0x40>)
+ 8000bcc: 68bb ldr r3, [r7, #8]
+ 8000bce: 60d3 str r3, [r2, #12]
+}
+ 8000bd0: bf00 nop
+ 8000bd2: 3714 adds r7, #20
+ 8000bd4: 46bd mov sp, r7
+ 8000bd6: f85d 7b04 ldr.w r7, [sp], #4
+ 8000bda: 4770 bx lr
+ 8000bdc: e000ed00 .word 0xe000ed00
+ 8000be0: 05fa0000 .word 0x05fa0000
+
+08000be4 <__NVIC_GetPriorityGrouping>:
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ 8000be4: b480 push {r7}
+ 8000be6: af00 add r7, sp, #0
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 8000be8: 4b04 ldr r3, [pc, #16] ; (8000bfc <__NVIC_GetPriorityGrouping+0x18>)
+ 8000bea: 68db ldr r3, [r3, #12]
+ 8000bec: 0a1b lsrs r3, r3, #8
+ 8000bee: f003 0307 and.w r3, r3, #7
+}
+ 8000bf2: 4618 mov r0, r3
+ 8000bf4: 46bd mov sp, r7
+ 8000bf6: f85d 7b04 ldr.w r7, [sp], #4
+ 8000bfa: 4770 bx lr
+ 8000bfc: e000ed00 .word 0xe000ed00
+
+08000c00 <__NVIC_EnableIRQ>:
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8000c00: b480 push {r7}
+ 8000c02: b083 sub sp, #12
+ 8000c04: af00 add r7, sp, #0
+ 8000c06: 4603 mov r3, r0
+ 8000c08: 71fb strb r3, [r7, #7]
+ if ((int32_t)(IRQn) >= 0)
+ 8000c0a: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000c0e: 2b00 cmp r3, #0
+ 8000c10: db0b blt.n 8000c2a <__NVIC_EnableIRQ+0x2a>
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8000c12: 79fb ldrb r3, [r7, #7]
+ 8000c14: f003 021f and.w r2, r3, #31
+ 8000c18: 4907 ldr r1, [pc, #28] ; (8000c38 <__NVIC_EnableIRQ+0x38>)
+ 8000c1a: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000c1e: 095b lsrs r3, r3, #5
+ 8000c20: 2001 movs r0, #1
+ 8000c22: fa00 f202 lsl.w r2, r0, r2
+ 8000c26: f841 2023 str.w r2, [r1, r3, lsl #2]
+ }
+}
+ 8000c2a: bf00 nop
+ 8000c2c: 370c adds r7, #12
+ 8000c2e: 46bd mov sp, r7
+ 8000c30: f85d 7b04 ldr.w r7, [sp], #4
+ 8000c34: 4770 bx lr
+ 8000c36: bf00 nop
+ 8000c38: e000e100 .word 0xe000e100
+
+08000c3c <__NVIC_SetPriority>:
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 8000c3c: b480 push {r7}
+ 8000c3e: b083 sub sp, #12
+ 8000c40: af00 add r7, sp, #0
+ 8000c42: 4603 mov r3, r0
+ 8000c44: 6039 str r1, [r7, #0]
+ 8000c46: 71fb strb r3, [r7, #7]
+ if ((int32_t)(IRQn) >= 0)
+ 8000c48: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000c4c: 2b00 cmp r3, #0
+ 8000c4e: db0a blt.n 8000c66 <__NVIC_SetPriority+0x2a>
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 8000c50: 683b ldr r3, [r7, #0]
+ 8000c52: b2da uxtb r2, r3
+ 8000c54: 490c ldr r1, [pc, #48] ; (8000c88 <__NVIC_SetPriority+0x4c>)
+ 8000c56: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000c5a: 0112 lsls r2, r2, #4
+ 8000c5c: b2d2 uxtb r2, r2
+ 8000c5e: 440b add r3, r1
+ 8000c60: f883 2300 strb.w r2, [r3, #768] ; 0x300
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+ 8000c64: e00a b.n 8000c7c <__NVIC_SetPriority+0x40>
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 8000c66: 683b ldr r3, [r7, #0]
+ 8000c68: b2da uxtb r2, r3
+ 8000c6a: 4908 ldr r1, [pc, #32] ; (8000c8c <__NVIC_SetPriority+0x50>)
+ 8000c6c: 79fb ldrb r3, [r7, #7]
+ 8000c6e: f003 030f and.w r3, r3, #15
+ 8000c72: 3b04 subs r3, #4
+ 8000c74: 0112 lsls r2, r2, #4
+ 8000c76: b2d2 uxtb r2, r2
+ 8000c78: 440b add r3, r1
+ 8000c7a: 761a strb r2, [r3, #24]
+}
+ 8000c7c: bf00 nop
+ 8000c7e: 370c adds r7, #12
+ 8000c80: 46bd mov sp, r7
+ 8000c82: f85d 7b04 ldr.w r7, [sp], #4
+ 8000c86: 4770 bx lr
+ 8000c88: e000e100 .word 0xe000e100
+ 8000c8c: e000ed00 .word 0xe000ed00
+
+08000c90 <NVIC_EncodePriority>:
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 8000c90: b480 push {r7}
+ 8000c92: b089 sub sp, #36 ; 0x24
+ 8000c94: af00 add r7, sp, #0
+ 8000c96: 60f8 str r0, [r7, #12]
+ 8000c98: 60b9 str r1, [r7, #8]
+ 8000c9a: 607a str r2, [r7, #4]
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ 8000c9c: 68fb ldr r3, [r7, #12]
+ 8000c9e: f003 0307 and.w r3, r3, #7
+ 8000ca2: 61fb str r3, [r7, #28]
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ 8000ca4: 69fb ldr r3, [r7, #28]
+ 8000ca6: f1c3 0307 rsb r3, r3, #7
+ 8000caa: 2b04 cmp r3, #4
+ 8000cac: bf28 it cs
+ 8000cae: 2304 movcs r3, #4
+ 8000cb0: 61bb str r3, [r7, #24]
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ 8000cb2: 69fb ldr r3, [r7, #28]
+ 8000cb4: 3304 adds r3, #4
+ 8000cb6: 2b06 cmp r3, #6
+ 8000cb8: d902 bls.n 8000cc0 <NVIC_EncodePriority+0x30>
+ 8000cba: 69fb ldr r3, [r7, #28]
+ 8000cbc: 3b03 subs r3, #3
+ 8000cbe: e000 b.n 8000cc2 <NVIC_EncodePriority+0x32>
+ 8000cc0: 2300 movs r3, #0
+ 8000cc2: 617b str r3, [r7, #20]
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8000cc4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 8000cc8: 69bb ldr r3, [r7, #24]
+ 8000cca: fa02 f303 lsl.w r3, r2, r3
+ 8000cce: 43da mvns r2, r3
+ 8000cd0: 68bb ldr r3, [r7, #8]
+ 8000cd2: 401a ands r2, r3
+ 8000cd4: 697b ldr r3, [r7, #20]
+ 8000cd6: 409a lsls r2, r3
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ 8000cd8: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
+ 8000cdc: 697b ldr r3, [r7, #20]
+ 8000cde: fa01 f303 lsl.w r3, r1, r3
+ 8000ce2: 43d9 mvns r1, r3
+ 8000ce4: 687b ldr r3, [r7, #4]
+ 8000ce6: 400b ands r3, r1
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8000ce8: 4313 orrs r3, r2
+ );
+}
+ 8000cea: 4618 mov r0, r3
+ 8000cec: 3724 adds r7, #36 ; 0x24
+ 8000cee: 46bd mov sp, r7
+ 8000cf0: f85d 7b04 ldr.w r7, [sp], #4
+ 8000cf4: 4770 bx lr
+ ...
+
+08000cf8 <SysTick_Config>:
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ 8000cf8: b580 push {r7, lr}
+ 8000cfa: b082 sub sp, #8
+ 8000cfc: af00 add r7, sp, #0
+ 8000cfe: 6078 str r0, [r7, #4]
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8000d00: 687b ldr r3, [r7, #4]
+ 8000d02: 3b01 subs r3, #1
+ 8000d04: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
+ 8000d08: d301 bcc.n 8000d0e <SysTick_Config+0x16>
+ {
+ return (1UL); /* Reload value impossible */
+ 8000d0a: 2301 movs r3, #1
+ 8000d0c: e00f b.n 8000d2e <SysTick_Config+0x36>
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ 8000d0e: 4a0a ldr r2, [pc, #40] ; (8000d38 <SysTick_Config+0x40>)
+ 8000d10: 687b ldr r3, [r7, #4]
+ 8000d12: 3b01 subs r3, #1
+ 8000d14: 6053 str r3, [r2, #4]
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8000d16: 210f movs r1, #15
+ 8000d18: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8000d1c: f7ff ff8e bl 8000c3c <__NVIC_SetPriority>
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 8000d20: 4b05 ldr r3, [pc, #20] ; (8000d38 <SysTick_Config+0x40>)
+ 8000d22: 2200 movs r2, #0
+ 8000d24: 609a str r2, [r3, #8]
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 8000d26: 4b04 ldr r3, [pc, #16] ; (8000d38 <SysTick_Config+0x40>)
+ 8000d28: 2207 movs r2, #7
+ 8000d2a: 601a str r2, [r3, #0]
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+ 8000d2c: 2300 movs r3, #0
+}
+ 8000d2e: 4618 mov r0, r3
+ 8000d30: 3708 adds r7, #8
+ 8000d32: 46bd mov sp, r7
+ 8000d34: bd80 pop {r7, pc}
+ 8000d36: bf00 nop
+ 8000d38: e000e010 .word 0xe000e010
+
+08000d3c <HAL_NVIC_SetPriorityGrouping>:
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8000d3c: b580 push {r7, lr}
+ 8000d3e: b082 sub sp, #8
+ 8000d40: af00 add r7, sp, #0
+ 8000d42: 6078 str r0, [r7, #4]
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+ 8000d44: 6878 ldr r0, [r7, #4]
+ 8000d46: f7ff ff29 bl 8000b9c <__NVIC_SetPriorityGrouping>
+}
+ 8000d4a: bf00 nop
+ 8000d4c: 3708 adds r7, #8
+ 8000d4e: 46bd mov sp, r7
+ 8000d50: bd80 pop {r7, pc}
+
+08000d52 <HAL_NVIC_SetPriority>:
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 8000d52: b580 push {r7, lr}
+ 8000d54: b086 sub sp, #24
+ 8000d56: af00 add r7, sp, #0
+ 8000d58: 4603 mov r3, r0
+ 8000d5a: 60b9 str r1, [r7, #8]
+ 8000d5c: 607a str r2, [r7, #4]
+ 8000d5e: 73fb strb r3, [r7, #15]
+ uint32_t prioritygroup = 0x00;
+ 8000d60: 2300 movs r3, #0
+ 8000d62: 617b str r3, [r7, #20]
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+ 8000d64: f7ff ff3e bl 8000be4 <__NVIC_GetPriorityGrouping>
+ 8000d68: 6178 str r0, [r7, #20]
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 8000d6a: 687a ldr r2, [r7, #4]
+ 8000d6c: 68b9 ldr r1, [r7, #8]
+ 8000d6e: 6978 ldr r0, [r7, #20]
+ 8000d70: f7ff ff8e bl 8000c90 <NVIC_EncodePriority>
+ 8000d74: 4602 mov r2, r0
+ 8000d76: f997 300f ldrsb.w r3, [r7, #15]
+ 8000d7a: 4611 mov r1, r2
+ 8000d7c: 4618 mov r0, r3
+ 8000d7e: f7ff ff5d bl 8000c3c <__NVIC_SetPriority>
+}
+ 8000d82: bf00 nop
+ 8000d84: 3718 adds r7, #24
+ 8000d86: 46bd mov sp, r7
+ 8000d88: bd80 pop {r7, pc}
+
+08000d8a <HAL_NVIC_EnableIRQ>:
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8000d8a: b580 push {r7, lr}
+ 8000d8c: b082 sub sp, #8
+ 8000d8e: af00 add r7, sp, #0
+ 8000d90: 4603 mov r3, r0
+ 8000d92: 71fb strb r3, [r7, #7]
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+ 8000d94: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000d98: 4618 mov r0, r3
+ 8000d9a: f7ff ff31 bl 8000c00 <__NVIC_EnableIRQ>
+}
+ 8000d9e: bf00 nop
+ 8000da0: 3708 adds r7, #8
+ 8000da2: 46bd mov sp, r7
+ 8000da4: bd80 pop {r7, pc}
+
+08000da6 <HAL_SYSTICK_Config>:
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 8000da6: b580 push {r7, lr}
+ 8000da8: b082 sub sp, #8
+ 8000daa: af00 add r7, sp, #0
+ 8000dac: 6078 str r0, [r7, #4]
+ return SysTick_Config(TicksNumb);
+ 8000dae: 6878 ldr r0, [r7, #4]
+ 8000db0: f7ff ffa2 bl 8000cf8 <SysTick_Config>
+ 8000db4: 4603 mov r3, r0
+}
+ 8000db6: 4618 mov r0, r3
+ 8000db8: 3708 adds r7, #8
+ 8000dba: 46bd mov sp, r7
+ 8000dbc: bd80 pop {r7, pc}
+
+08000dbe <HAL_DMA_Abort_IT>:
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ 8000dbe: b480 push {r7}
+ 8000dc0: b083 sub sp, #12
+ 8000dc2: af00 add r7, sp, #0
+ 8000dc4: 6078 str r0, [r7, #4]
+ if(hdma->State != HAL_DMA_STATE_BUSY)
+ 8000dc6: 687b ldr r3, [r7, #4]
+ 8000dc8: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
+ 8000dcc: b2db uxtb r3, r3
+ 8000dce: 2b02 cmp r3, #2
+ 8000dd0: d004 beq.n 8000ddc <HAL_DMA_Abort_IT+0x1e>
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 8000dd2: 687b ldr r3, [r7, #4]
+ 8000dd4: 2280 movs r2, #128 ; 0x80
+ 8000dd6: 655a str r2, [r3, #84] ; 0x54
+ return HAL_ERROR;
+ 8000dd8: 2301 movs r3, #1
+ 8000dda: e00c b.n 8000df6 <HAL_DMA_Abort_IT+0x38>
+ }
+ else
+ {
+ /* Set Abort State */
+ hdma->State = HAL_DMA_STATE_ABORT;
+ 8000ddc: 687b ldr r3, [r7, #4]
+ 8000dde: 2205 movs r2, #5
+ 8000de0: f883 2035 strb.w r2, [r3, #53] ; 0x35
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+ 8000de4: 687b ldr r3, [r7, #4]
+ 8000de6: 681b ldr r3, [r3, #0]
+ 8000de8: 681a ldr r2, [r3, #0]
+ 8000dea: 687b ldr r3, [r7, #4]
+ 8000dec: 681b ldr r3, [r3, #0]
+ 8000dee: f022 0201 bic.w r2, r2, #1
+ 8000df2: 601a str r2, [r3, #0]
+ }
+
+ return HAL_OK;
+ 8000df4: 2300 movs r3, #0
+}
+ 8000df6: 4618 mov r0, r3
+ 8000df8: 370c adds r7, #12
+ 8000dfa: 46bd mov sp, r7
+ 8000dfc: f85d 7b04 ldr.w r7, [sp], #4
+ 8000e00: 4770 bx lr
+ ...
+
+08000e04 <HAL_GPIO_Init>:
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 8000e04: b480 push {r7}
+ 8000e06: b089 sub sp, #36 ; 0x24
+ 8000e08: af00 add r7, sp, #0
+ 8000e0a: 6078 str r0, [r7, #4]
+ 8000e0c: 6039 str r1, [r7, #0]
+ uint32_t position = 0x00;
+ 8000e0e: 2300 movs r3, #0
+ 8000e10: 61fb str r3, [r7, #28]
+ uint32_t ioposition = 0x00;
+ 8000e12: 2300 movs r3, #0
+ 8000e14: 617b str r3, [r7, #20]
+ uint32_t iocurrent = 0x00;
+ 8000e16: 2300 movs r3, #0
+ 8000e18: 613b str r3, [r7, #16]
+ uint32_t temp = 0x00;
+ 8000e1a: 2300 movs r3, #0
+ 8000e1c: 61bb str r3, [r7, #24]
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ for(position = 0; position < GPIO_NUMBER; position++)
+ 8000e1e: 2300 movs r3, #0
+ 8000e20: 61fb str r3, [r7, #28]
+ 8000e22: e175 b.n 8001110 <HAL_GPIO_Init+0x30c>
+ {
+ /* Get the IO position */
+ ioposition = ((uint32_t)0x01) << position;
+ 8000e24: 2201 movs r2, #1
+ 8000e26: 69fb ldr r3, [r7, #28]
+ 8000e28: fa02 f303 lsl.w r3, r2, r3
+ 8000e2c: 617b str r3, [r7, #20]
+ /* Get the current IO position */
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+ 8000e2e: 683b ldr r3, [r7, #0]
+ 8000e30: 681b ldr r3, [r3, #0]
+ 8000e32: 697a ldr r2, [r7, #20]
+ 8000e34: 4013 ands r3, r2
+ 8000e36: 613b str r3, [r7, #16]
+
+ if(iocurrent == ioposition)
+ 8000e38: 693a ldr r2, [r7, #16]
+ 8000e3a: 697b ldr r3, [r7, #20]
+ 8000e3c: 429a cmp r2, r3
+ 8000e3e: f040 8164 bne.w 800110a <HAL_GPIO_Init+0x306>
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 8000e42: 683b ldr r3, [r7, #0]
+ 8000e44: 685b ldr r3, [r3, #4]
+ 8000e46: 2b02 cmp r3, #2
+ 8000e48: d003 beq.n 8000e52 <HAL_GPIO_Init+0x4e>
+ 8000e4a: 683b ldr r3, [r7, #0]
+ 8000e4c: 685b ldr r3, [r3, #4]
+ 8000e4e: 2b12 cmp r3, #18
+ 8000e50: d123 bne.n 8000e9a <HAL_GPIO_Init+0x96>
+ {
+ /* Check the Alternate function parameter */
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3];
+ 8000e52: 69fb ldr r3, [r7, #28]
+ 8000e54: 08da lsrs r2, r3, #3
+ 8000e56: 687b ldr r3, [r7, #4]
+ 8000e58: 3208 adds r2, #8
+ 8000e5a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
+ 8000e5e: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ 8000e60: 69fb ldr r3, [r7, #28]
+ 8000e62: f003 0307 and.w r3, r3, #7
+ 8000e66: 009b lsls r3, r3, #2
+ 8000e68: 220f movs r2, #15
+ 8000e6a: fa02 f303 lsl.w r3, r2, r3
+ 8000e6e: 43db mvns r3, r3
+ 8000e70: 69ba ldr r2, [r7, #24]
+ 8000e72: 4013 ands r3, r2
+ 8000e74: 61bb str r3, [r7, #24]
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ 8000e76: 683b ldr r3, [r7, #0]
+ 8000e78: 691a ldr r2, [r3, #16]
+ 8000e7a: 69fb ldr r3, [r7, #28]
+ 8000e7c: f003 0307 and.w r3, r3, #7
+ 8000e80: 009b lsls r3, r3, #2
+ 8000e82: fa02 f303 lsl.w r3, r2, r3
+ 8000e86: 69ba ldr r2, [r7, #24]
+ 8000e88: 4313 orrs r3, r2
+ 8000e8a: 61bb str r3, [r7, #24]
+ GPIOx->AFR[position >> 3] = temp;
+ 8000e8c: 69fb ldr r3, [r7, #28]
+ 8000e8e: 08da lsrs r2, r3, #3
+ 8000e90: 687b ldr r3, [r7, #4]
+ 8000e92: 3208 adds r2, #8
+ 8000e94: 69b9 ldr r1, [r7, #24]
+ 8000e96: f843 1022 str.w r1, [r3, r2, lsl #2]
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ 8000e9a: 687b ldr r3, [r7, #4]
+ 8000e9c: 681b ldr r3, [r3, #0]
+ 8000e9e: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ 8000ea0: 69fb ldr r3, [r7, #28]
+ 8000ea2: 005b lsls r3, r3, #1
+ 8000ea4: 2203 movs r2, #3
+ 8000ea6: fa02 f303 lsl.w r3, r2, r3
+ 8000eaa: 43db mvns r3, r3
+ 8000eac: 69ba ldr r2, [r7, #24]
+ 8000eae: 4013 ands r3, r2
+ 8000eb0: 61bb str r3, [r7, #24]
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ 8000eb2: 683b ldr r3, [r7, #0]
+ 8000eb4: 685b ldr r3, [r3, #4]
+ 8000eb6: f003 0203 and.w r2, r3, #3
+ 8000eba: 69fb ldr r3, [r7, #28]
+ 8000ebc: 005b lsls r3, r3, #1
+ 8000ebe: fa02 f303 lsl.w r3, r2, r3
+ 8000ec2: 69ba ldr r2, [r7, #24]
+ 8000ec4: 4313 orrs r3, r2
+ 8000ec6: 61bb str r3, [r7, #24]
+ GPIOx->MODER = temp;
+ 8000ec8: 687b ldr r3, [r7, #4]
+ 8000eca: 69ba ldr r2, [r7, #24]
+ 8000ecc: 601a str r2, [r3, #0]
+
+ /* In case of Output or Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 8000ece: 683b ldr r3, [r7, #0]
+ 8000ed0: 685b ldr r3, [r3, #4]
+ 8000ed2: 2b01 cmp r3, #1
+ 8000ed4: d00b beq.n 8000eee <HAL_GPIO_Init+0xea>
+ 8000ed6: 683b ldr r3, [r7, #0]
+ 8000ed8: 685b ldr r3, [r3, #4]
+ 8000eda: 2b02 cmp r3, #2
+ 8000edc: d007 beq.n 8000eee <HAL_GPIO_Init+0xea>
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 8000ede: 683b ldr r3, [r7, #0]
+ 8000ee0: 685b ldr r3, [r3, #4]
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 8000ee2: 2b11 cmp r3, #17
+ 8000ee4: d003 beq.n 8000eee <HAL_GPIO_Init+0xea>
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 8000ee6: 683b ldr r3, [r7, #0]
+ 8000ee8: 685b ldr r3, [r3, #4]
+ 8000eea: 2b12 cmp r3, #18
+ 8000eec: d130 bne.n 8000f50 <HAL_GPIO_Init+0x14c>
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ 8000eee: 687b ldr r3, [r7, #4]
+ 8000ef0: 689b ldr r3, [r3, #8]
+ 8000ef2: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ 8000ef4: 69fb ldr r3, [r7, #28]
+ 8000ef6: 005b lsls r3, r3, #1
+ 8000ef8: 2203 movs r2, #3
+ 8000efa: fa02 f303 lsl.w r3, r2, r3
+ 8000efe: 43db mvns r3, r3
+ 8000f00: 69ba ldr r2, [r7, #24]
+ 8000f02: 4013 ands r3, r2
+ 8000f04: 61bb str r3, [r7, #24]
+ temp |= (GPIO_Init->Speed << (position * 2));
+ 8000f06: 683b ldr r3, [r7, #0]
+ 8000f08: 68da ldr r2, [r3, #12]
+ 8000f0a: 69fb ldr r3, [r7, #28]
+ 8000f0c: 005b lsls r3, r3, #1
+ 8000f0e: fa02 f303 lsl.w r3, r2, r3
+ 8000f12: 69ba ldr r2, [r7, #24]
+ 8000f14: 4313 orrs r3, r2
+ 8000f16: 61bb str r3, [r7, #24]
+ GPIOx->OSPEEDR = temp;
+ 8000f18: 687b ldr r3, [r7, #4]
+ 8000f1a: 69ba ldr r2, [r7, #24]
+ 8000f1c: 609a str r2, [r3, #8]
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ 8000f1e: 687b ldr r3, [r7, #4]
+ 8000f20: 685b ldr r3, [r3, #4]
+ 8000f22: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 8000f24: 2201 movs r2, #1
+ 8000f26: 69fb ldr r3, [r7, #28]
+ 8000f28: fa02 f303 lsl.w r3, r2, r3
+ 8000f2c: 43db mvns r3, r3
+ 8000f2e: 69ba ldr r2, [r7, #24]
+ 8000f30: 4013 ands r3, r2
+ 8000f32: 61bb str r3, [r7, #24]
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ 8000f34: 683b ldr r3, [r7, #0]
+ 8000f36: 685b ldr r3, [r3, #4]
+ 8000f38: 091b lsrs r3, r3, #4
+ 8000f3a: f003 0201 and.w r2, r3, #1
+ 8000f3e: 69fb ldr r3, [r7, #28]
+ 8000f40: fa02 f303 lsl.w r3, r2, r3
+ 8000f44: 69ba ldr r2, [r7, #24]
+ 8000f46: 4313 orrs r3, r2
+ 8000f48: 61bb str r3, [r7, #24]
+ GPIOx->OTYPER = temp;
+ 8000f4a: 687b ldr r3, [r7, #4]
+ 8000f4c: 69ba ldr r2, [r7, #24]
+ 8000f4e: 605a str r2, [r3, #4]
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ 8000f50: 687b ldr r3, [r7, #4]
+ 8000f52: 68db ldr r3, [r3, #12]
+ 8000f54: 61bb str r3, [r7, #24]
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ 8000f56: 69fb ldr r3, [r7, #28]
+ 8000f58: 005b lsls r3, r3, #1
+ 8000f5a: 2203 movs r2, #3
+ 8000f5c: fa02 f303 lsl.w r3, r2, r3
+ 8000f60: 43db mvns r3, r3
+ 8000f62: 69ba ldr r2, [r7, #24]
+ 8000f64: 4013 ands r3, r2
+ 8000f66: 61bb str r3, [r7, #24]
+ temp |= ((GPIO_Init->Pull) << (position * 2));
+ 8000f68: 683b ldr r3, [r7, #0]
+ 8000f6a: 689a ldr r2, [r3, #8]
+ 8000f6c: 69fb ldr r3, [r7, #28]
+ 8000f6e: 005b lsls r3, r3, #1
+ 8000f70: fa02 f303 lsl.w r3, r2, r3
+ 8000f74: 69ba ldr r2, [r7, #24]
+ 8000f76: 4313 orrs r3, r2
+ 8000f78: 61bb str r3, [r7, #24]
+ GPIOx->PUPDR = temp;
+ 8000f7a: 687b ldr r3, [r7, #4]
+ 8000f7c: 69ba ldr r2, [r7, #24]
+ 8000f7e: 60da str r2, [r3, #12]
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ 8000f80: 683b ldr r3, [r7, #0]
+ 8000f82: 685b ldr r3, [r3, #4]
+ 8000f84: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000f88: 2b00 cmp r3, #0
+ 8000f8a: f000 80be beq.w 800110a <HAL_GPIO_Init+0x306>
+ {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8000f8e: 4b65 ldr r3, [pc, #404] ; (8001124 <HAL_GPIO_Init+0x320>)
+ 8000f90: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000f92: 4a64 ldr r2, [pc, #400] ; (8001124 <HAL_GPIO_Init+0x320>)
+ 8000f94: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000f98: 6453 str r3, [r2, #68] ; 0x44
+ 8000f9a: 4b62 ldr r3, [pc, #392] ; (8001124 <HAL_GPIO_Init+0x320>)
+ 8000f9c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000f9e: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8000fa2: 60fb str r3, [r7, #12]
+ 8000fa4: 68fb ldr r3, [r7, #12]
+
+ temp = SYSCFG->EXTICR[position >> 2];
+ 8000fa6: 4a60 ldr r2, [pc, #384] ; (8001128 <HAL_GPIO_Init+0x324>)
+ 8000fa8: 69fb ldr r3, [r7, #28]
+ 8000faa: 089b lsrs r3, r3, #2
+ 8000fac: 3302 adds r3, #2
+ 8000fae: f852 3023 ldr.w r3, [r2, r3, lsl #2]
+ 8000fb2: 61bb str r3, [r7, #24]
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ 8000fb4: 69fb ldr r3, [r7, #28]
+ 8000fb6: f003 0303 and.w r3, r3, #3
+ 8000fba: 009b lsls r3, r3, #2
+ 8000fbc: 220f movs r2, #15
+ 8000fbe: fa02 f303 lsl.w r3, r2, r3
+ 8000fc2: 43db mvns r3, r3
+ 8000fc4: 69ba ldr r2, [r7, #24]
+ 8000fc6: 4013 ands r3, r2
+ 8000fc8: 61bb str r3, [r7, #24]
+ temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
+ 8000fca: 687b ldr r3, [r7, #4]
+ 8000fcc: 4a57 ldr r2, [pc, #348] ; (800112c <HAL_GPIO_Init+0x328>)
+ 8000fce: 4293 cmp r3, r2
+ 8000fd0: d037 beq.n 8001042 <HAL_GPIO_Init+0x23e>
+ 8000fd2: 687b ldr r3, [r7, #4]
+ 8000fd4: 4a56 ldr r2, [pc, #344] ; (8001130 <HAL_GPIO_Init+0x32c>)
+ 8000fd6: 4293 cmp r3, r2
+ 8000fd8: d031 beq.n 800103e <HAL_GPIO_Init+0x23a>
+ 8000fda: 687b ldr r3, [r7, #4]
+ 8000fdc: 4a55 ldr r2, [pc, #340] ; (8001134 <HAL_GPIO_Init+0x330>)
+ 8000fde: 4293 cmp r3, r2
+ 8000fe0: d02b beq.n 800103a <HAL_GPIO_Init+0x236>
+ 8000fe2: 687b ldr r3, [r7, #4]
+ 8000fe4: 4a54 ldr r2, [pc, #336] ; (8001138 <HAL_GPIO_Init+0x334>)
+ 8000fe6: 4293 cmp r3, r2
+ 8000fe8: d025 beq.n 8001036 <HAL_GPIO_Init+0x232>
+ 8000fea: 687b ldr r3, [r7, #4]
+ 8000fec: 4a53 ldr r2, [pc, #332] ; (800113c <HAL_GPIO_Init+0x338>)
+ 8000fee: 4293 cmp r3, r2
+ 8000ff0: d01f beq.n 8001032 <HAL_GPIO_Init+0x22e>
+ 8000ff2: 687b ldr r3, [r7, #4]
+ 8000ff4: 4a52 ldr r2, [pc, #328] ; (8001140 <HAL_GPIO_Init+0x33c>)
+ 8000ff6: 4293 cmp r3, r2
+ 8000ff8: d019 beq.n 800102e <HAL_GPIO_Init+0x22a>
+ 8000ffa: 687b ldr r3, [r7, #4]
+ 8000ffc: 4a51 ldr r2, [pc, #324] ; (8001144 <HAL_GPIO_Init+0x340>)
+ 8000ffe: 4293 cmp r3, r2
+ 8001000: d013 beq.n 800102a <HAL_GPIO_Init+0x226>
+ 8001002: 687b ldr r3, [r7, #4]
+ 8001004: 4a50 ldr r2, [pc, #320] ; (8001148 <HAL_GPIO_Init+0x344>)
+ 8001006: 4293 cmp r3, r2
+ 8001008: d00d beq.n 8001026 <HAL_GPIO_Init+0x222>
+ 800100a: 687b ldr r3, [r7, #4]
+ 800100c: 4a4f ldr r2, [pc, #316] ; (800114c <HAL_GPIO_Init+0x348>)
+ 800100e: 4293 cmp r3, r2
+ 8001010: d007 beq.n 8001022 <HAL_GPIO_Init+0x21e>
+ 8001012: 687b ldr r3, [r7, #4]
+ 8001014: 4a4e ldr r2, [pc, #312] ; (8001150 <HAL_GPIO_Init+0x34c>)
+ 8001016: 4293 cmp r3, r2
+ 8001018: d101 bne.n 800101e <HAL_GPIO_Init+0x21a>
+ 800101a: 2309 movs r3, #9
+ 800101c: e012 b.n 8001044 <HAL_GPIO_Init+0x240>
+ 800101e: 230a movs r3, #10
+ 8001020: e010 b.n 8001044 <HAL_GPIO_Init+0x240>
+ 8001022: 2308 movs r3, #8
+ 8001024: e00e b.n 8001044 <HAL_GPIO_Init+0x240>
+ 8001026: 2307 movs r3, #7
+ 8001028: e00c b.n 8001044 <HAL_GPIO_Init+0x240>
+ 800102a: 2306 movs r3, #6
+ 800102c: e00a b.n 8001044 <HAL_GPIO_Init+0x240>
+ 800102e: 2305 movs r3, #5
+ 8001030: e008 b.n 8001044 <HAL_GPIO_Init+0x240>
+ 8001032: 2304 movs r3, #4
+ 8001034: e006 b.n 8001044 <HAL_GPIO_Init+0x240>
+ 8001036: 2303 movs r3, #3
+ 8001038: e004 b.n 8001044 <HAL_GPIO_Init+0x240>
+ 800103a: 2302 movs r3, #2
+ 800103c: e002 b.n 8001044 <HAL_GPIO_Init+0x240>
+ 800103e: 2301 movs r3, #1
+ 8001040: e000 b.n 8001044 <HAL_GPIO_Init+0x240>
+ 8001042: 2300 movs r3, #0
+ 8001044: 69fa ldr r2, [r7, #28]
+ 8001046: f002 0203 and.w r2, r2, #3
+ 800104a: 0092 lsls r2, r2, #2
+ 800104c: 4093 lsls r3, r2
+ 800104e: 69ba ldr r2, [r7, #24]
+ 8001050: 4313 orrs r3, r2
+ 8001052: 61bb str r3, [r7, #24]
+ SYSCFG->EXTICR[position >> 2] = temp;
+ 8001054: 4934 ldr r1, [pc, #208] ; (8001128 <HAL_GPIO_Init+0x324>)
+ 8001056: 69fb ldr r3, [r7, #28]
+ 8001058: 089b lsrs r3, r3, #2
+ 800105a: 3302 adds r3, #2
+ 800105c: 69ba ldr r2, [r7, #24]
+ 800105e: f841 2023 str.w r2, [r1, r3, lsl #2]
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ 8001062: 4b3c ldr r3, [pc, #240] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 8001064: 681b ldr r3, [r3, #0]
+ 8001066: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8001068: 693b ldr r3, [r7, #16]
+ 800106a: 43db mvns r3, r3
+ 800106c: 69ba ldr r2, [r7, #24]
+ 800106e: 4013 ands r3, r2
+ 8001070: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 8001072: 683b ldr r3, [r7, #0]
+ 8001074: 685b ldr r3, [r3, #4]
+ 8001076: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 800107a: 2b00 cmp r3, #0
+ 800107c: d003 beq.n 8001086 <HAL_GPIO_Init+0x282>
+ {
+ temp |= iocurrent;
+ 800107e: 69ba ldr r2, [r7, #24]
+ 8001080: 693b ldr r3, [r7, #16]
+ 8001082: 4313 orrs r3, r2
+ 8001084: 61bb str r3, [r7, #24]
+ }
+ EXTI->IMR = temp;
+ 8001086: 4a33 ldr r2, [pc, #204] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 8001088: 69bb ldr r3, [r7, #24]
+ 800108a: 6013 str r3, [r2, #0]
+
+ temp = EXTI->EMR;
+ 800108c: 4b31 ldr r3, [pc, #196] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 800108e: 685b ldr r3, [r3, #4]
+ 8001090: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 8001092: 693b ldr r3, [r7, #16]
+ 8001094: 43db mvns r3, r3
+ 8001096: 69ba ldr r2, [r7, #24]
+ 8001098: 4013 ands r3, r2
+ 800109a: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 800109c: 683b ldr r3, [r7, #0]
+ 800109e: 685b ldr r3, [r3, #4]
+ 80010a0: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80010a4: 2b00 cmp r3, #0
+ 80010a6: d003 beq.n 80010b0 <HAL_GPIO_Init+0x2ac>
+ {
+ temp |= iocurrent;
+ 80010a8: 69ba ldr r2, [r7, #24]
+ 80010aa: 693b ldr r3, [r7, #16]
+ 80010ac: 4313 orrs r3, r2
+ 80010ae: 61bb str r3, [r7, #24]
+ }
+ EXTI->EMR = temp;
+ 80010b0: 4a28 ldr r2, [pc, #160] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 80010b2: 69bb ldr r3, [r7, #24]
+ 80010b4: 6053 str r3, [r2, #4]
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ 80010b6: 4b27 ldr r3, [pc, #156] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 80010b8: 689b ldr r3, [r3, #8]
+ 80010ba: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 80010bc: 693b ldr r3, [r7, #16]
+ 80010be: 43db mvns r3, r3
+ 80010c0: 69ba ldr r2, [r7, #24]
+ 80010c2: 4013 ands r3, r2
+ 80010c4: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 80010c6: 683b ldr r3, [r7, #0]
+ 80010c8: 685b ldr r3, [r3, #4]
+ 80010ca: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 80010ce: 2b00 cmp r3, #0
+ 80010d0: d003 beq.n 80010da <HAL_GPIO_Init+0x2d6>
+ {
+ temp |= iocurrent;
+ 80010d2: 69ba ldr r2, [r7, #24]
+ 80010d4: 693b ldr r3, [r7, #16]
+ 80010d6: 4313 orrs r3, r2
+ 80010d8: 61bb str r3, [r7, #24]
+ }
+ EXTI->RTSR = temp;
+ 80010da: 4a1e ldr r2, [pc, #120] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 80010dc: 69bb ldr r3, [r7, #24]
+ 80010de: 6093 str r3, [r2, #8]
+
+ temp = EXTI->FTSR;
+ 80010e0: 4b1c ldr r3, [pc, #112] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 80010e2: 68db ldr r3, [r3, #12]
+ 80010e4: 61bb str r3, [r7, #24]
+ temp &= ~((uint32_t)iocurrent);
+ 80010e6: 693b ldr r3, [r7, #16]
+ 80010e8: 43db mvns r3, r3
+ 80010ea: 69ba ldr r2, [r7, #24]
+ 80010ec: 4013 ands r3, r2
+ 80010ee: 61bb str r3, [r7, #24]
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 80010f0: 683b ldr r3, [r7, #0]
+ 80010f2: 685b ldr r3, [r3, #4]
+ 80010f4: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 80010f8: 2b00 cmp r3, #0
+ 80010fa: d003 beq.n 8001104 <HAL_GPIO_Init+0x300>
+ {
+ temp |= iocurrent;
+ 80010fc: 69ba ldr r2, [r7, #24]
+ 80010fe: 693b ldr r3, [r7, #16]
+ 8001100: 4313 orrs r3, r2
+ 8001102: 61bb str r3, [r7, #24]
+ }
+ EXTI->FTSR = temp;
+ 8001104: 4a13 ldr r2, [pc, #76] ; (8001154 <HAL_GPIO_Init+0x350>)
+ 8001106: 69bb ldr r3, [r7, #24]
+ 8001108: 60d3 str r3, [r2, #12]
+ for(position = 0; position < GPIO_NUMBER; position++)
+ 800110a: 69fb ldr r3, [r7, #28]
+ 800110c: 3301 adds r3, #1
+ 800110e: 61fb str r3, [r7, #28]
+ 8001110: 69fb ldr r3, [r7, #28]
+ 8001112: 2b0f cmp r3, #15
+ 8001114: f67f ae86 bls.w 8000e24 <HAL_GPIO_Init+0x20>
+ }
+ }
+ }
+}
+ 8001118: bf00 nop
+ 800111a: 3724 adds r7, #36 ; 0x24
+ 800111c: 46bd mov sp, r7
+ 800111e: f85d 7b04 ldr.w r7, [sp], #4
+ 8001122: 4770 bx lr
+ 8001124: 40023800 .word 0x40023800
+ 8001128: 40013800 .word 0x40013800
+ 800112c: 40020000 .word 0x40020000
+ 8001130: 40020400 .word 0x40020400
+ 8001134: 40020800 .word 0x40020800
+ 8001138: 40020c00 .word 0x40020c00
+ 800113c: 40021000 .word 0x40021000
+ 8001140: 40021400 .word 0x40021400
+ 8001144: 40021800 .word 0x40021800
+ 8001148: 40021c00 .word 0x40021c00
+ 800114c: 40022000 .word 0x40022000
+ 8001150: 40022400 .word 0x40022400
+ 8001154: 40013c00 .word 0x40013c00
+
+08001158 <HAL_RCC_OscConfig>:
+ * supported by this function. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ 8001158: b580 push {r7, lr}
+ 800115a: b086 sub sp, #24
+ 800115c: af00 add r7, sp, #0
+ 800115e: 6078 str r0, [r7, #4]
+ uint32_t tickstart;
+ FlagStatus pwrclkchanged = RESET;
+ 8001160: 2300 movs r3, #0
+ 8001162: 75fb strb r3, [r7, #23]
+
+ /* Check Null pointer */
+ if(RCC_OscInitStruct == NULL)
+ 8001164: 687b ldr r3, [r7, #4]
+ 8001166: 2b00 cmp r3, #0
+ 8001168: d101 bne.n 800116e <HAL_RCC_OscConfig+0x16>
+ {
+ return HAL_ERROR;
+ 800116a: 2301 movs r3, #1
+ 800116c: e25e b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 800116e: 687b ldr r3, [r7, #4]
+ 8001170: 681b ldr r3, [r3, #0]
+ 8001172: f003 0301 and.w r3, r3, #1
+ 8001176: 2b00 cmp r3, #0
+ 8001178: f000 8087 beq.w 800128a <HAL_RCC_OscConfig+0x132>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ 800117c: 4b96 ldr r3, [pc, #600] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800117e: 689b ldr r3, [r3, #8]
+ 8001180: f003 030c and.w r3, r3, #12
+ 8001184: 2b04 cmp r3, #4
+ 8001186: d00c beq.n 80011a2 <HAL_RCC_OscConfig+0x4a>
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+ 8001188: 4b93 ldr r3, [pc, #588] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800118a: 689b ldr r3, [r3, #8]
+ 800118c: f003 030c and.w r3, r3, #12
+ 8001190: 2b08 cmp r3, #8
+ 8001192: d112 bne.n 80011ba <HAL_RCC_OscConfig+0x62>
+ 8001194: 4b90 ldr r3, [pc, #576] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001196: 685b ldr r3, [r3, #4]
+ 8001198: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 800119c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 80011a0: d10b bne.n 80011ba <HAL_RCC_OscConfig+0x62>
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 80011a2: 4b8d ldr r3, [pc, #564] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80011a4: 681b ldr r3, [r3, #0]
+ 80011a6: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80011aa: 2b00 cmp r3, #0
+ 80011ac: d06c beq.n 8001288 <HAL_RCC_OscConfig+0x130>
+ 80011ae: 687b ldr r3, [r7, #4]
+ 80011b0: 685b ldr r3, [r3, #4]
+ 80011b2: 2b00 cmp r3, #0
+ 80011b4: d168 bne.n 8001288 <HAL_RCC_OscConfig+0x130>
+ {
+ return HAL_ERROR;
+ 80011b6: 2301 movs r3, #1
+ 80011b8: e238 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ }
+ }
+ else
+ {
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 80011ba: 687b ldr r3, [r7, #4]
+ 80011bc: 685b ldr r3, [r3, #4]
+ 80011be: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 80011c2: d106 bne.n 80011d2 <HAL_RCC_OscConfig+0x7a>
+ 80011c4: 4b84 ldr r3, [pc, #528] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80011c6: 681b ldr r3, [r3, #0]
+ 80011c8: 4a83 ldr r2, [pc, #524] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80011ca: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 80011ce: 6013 str r3, [r2, #0]
+ 80011d0: e02e b.n 8001230 <HAL_RCC_OscConfig+0xd8>
+ 80011d2: 687b ldr r3, [r7, #4]
+ 80011d4: 685b ldr r3, [r3, #4]
+ 80011d6: 2b00 cmp r3, #0
+ 80011d8: d10c bne.n 80011f4 <HAL_RCC_OscConfig+0x9c>
+ 80011da: 4b7f ldr r3, [pc, #508] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80011dc: 681b ldr r3, [r3, #0]
+ 80011de: 4a7e ldr r2, [pc, #504] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80011e0: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 80011e4: 6013 str r3, [r2, #0]
+ 80011e6: 4b7c ldr r3, [pc, #496] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80011e8: 681b ldr r3, [r3, #0]
+ 80011ea: 4a7b ldr r2, [pc, #492] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80011ec: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 80011f0: 6013 str r3, [r2, #0]
+ 80011f2: e01d b.n 8001230 <HAL_RCC_OscConfig+0xd8>
+ 80011f4: 687b ldr r3, [r7, #4]
+ 80011f6: 685b ldr r3, [r3, #4]
+ 80011f8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
+ 80011fc: d10c bne.n 8001218 <HAL_RCC_OscConfig+0xc0>
+ 80011fe: 4b76 ldr r3, [pc, #472] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001200: 681b ldr r3, [r3, #0]
+ 8001202: 4a75 ldr r2, [pc, #468] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001204: f443 2380 orr.w r3, r3, #262144 ; 0x40000
+ 8001208: 6013 str r3, [r2, #0]
+ 800120a: 4b73 ldr r3, [pc, #460] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800120c: 681b ldr r3, [r3, #0]
+ 800120e: 4a72 ldr r2, [pc, #456] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001210: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8001214: 6013 str r3, [r2, #0]
+ 8001216: e00b b.n 8001230 <HAL_RCC_OscConfig+0xd8>
+ 8001218: 4b6f ldr r3, [pc, #444] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800121a: 681b ldr r3, [r3, #0]
+ 800121c: 4a6e ldr r2, [pc, #440] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800121e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8001222: 6013 str r3, [r2, #0]
+ 8001224: 4b6c ldr r3, [pc, #432] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001226: 681b ldr r3, [r3, #0]
+ 8001228: 4a6b ldr r2, [pc, #428] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800122a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 800122e: 6013 str r3, [r2, #0]
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 8001230: 687b ldr r3, [r7, #4]
+ 8001232: 685b ldr r3, [r3, #4]
+ 8001234: 2b00 cmp r3, #0
+ 8001236: d013 beq.n 8001260 <HAL_RCC_OscConfig+0x108>
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001238: f7ff fca4 bl 8000b84 <HAL_GetTick>
+ 800123c: 6138 str r0, [r7, #16]
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 800123e: e008 b.n 8001252 <HAL_RCC_OscConfig+0xfa>
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 8001240: f7ff fca0 bl 8000b84 <HAL_GetTick>
+ 8001244: 4602 mov r2, r0
+ 8001246: 693b ldr r3, [r7, #16]
+ 8001248: 1ad3 subs r3, r2, r3
+ 800124a: 2b64 cmp r3, #100 ; 0x64
+ 800124c: d901 bls.n 8001252 <HAL_RCC_OscConfig+0xfa>
+ {
+ return HAL_TIMEOUT;
+ 800124e: 2303 movs r3, #3
+ 8001250: e1ec b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 8001252: 4b61 ldr r3, [pc, #388] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001254: 681b ldr r3, [r3, #0]
+ 8001256: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 800125a: 2b00 cmp r3, #0
+ 800125c: d0f0 beq.n 8001240 <HAL_RCC_OscConfig+0xe8>
+ 800125e: e014 b.n 800128a <HAL_RCC_OscConfig+0x132>
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001260: f7ff fc90 bl 8000b84 <HAL_GetTick>
+ 8001264: 6138 str r0, [r7, #16]
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 8001266: e008 b.n 800127a <HAL_RCC_OscConfig+0x122>
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 8001268: f7ff fc8c bl 8000b84 <HAL_GetTick>
+ 800126c: 4602 mov r2, r0
+ 800126e: 693b ldr r3, [r7, #16]
+ 8001270: 1ad3 subs r3, r2, r3
+ 8001272: 2b64 cmp r3, #100 ; 0x64
+ 8001274: d901 bls.n 800127a <HAL_RCC_OscConfig+0x122>
+ {
+ return HAL_TIMEOUT;
+ 8001276: 2303 movs r3, #3
+ 8001278: e1d8 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 800127a: 4b57 ldr r3, [pc, #348] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800127c: 681b ldr r3, [r3, #0]
+ 800127e: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8001282: 2b00 cmp r3, #0
+ 8001284: d1f0 bne.n 8001268 <HAL_RCC_OscConfig+0x110>
+ 8001286: e000 b.n 800128a <HAL_RCC_OscConfig+0x132>
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8001288: bf00 nop
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 800128a: 687b ldr r3, [r7, #4]
+ 800128c: 681b ldr r3, [r3, #0]
+ 800128e: f003 0302 and.w r3, r3, #2
+ 8001292: 2b00 cmp r3, #0
+ 8001294: d069 beq.n 800136a <HAL_RCC_OscConfig+0x212>
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ 8001296: 4b50 ldr r3, [pc, #320] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001298: 689b ldr r3, [r3, #8]
+ 800129a: f003 030c and.w r3, r3, #12
+ 800129e: 2b00 cmp r3, #0
+ 80012a0: d00b beq.n 80012ba <HAL_RCC_OscConfig+0x162>
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+ 80012a2: 4b4d ldr r3, [pc, #308] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80012a4: 689b ldr r3, [r3, #8]
+ 80012a6: f003 030c and.w r3, r3, #12
+ 80012aa: 2b08 cmp r3, #8
+ 80012ac: d11c bne.n 80012e8 <HAL_RCC_OscConfig+0x190>
+ 80012ae: 4b4a ldr r3, [pc, #296] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80012b0: 685b ldr r3, [r3, #4]
+ 80012b2: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 80012b6: 2b00 cmp r3, #0
+ 80012b8: d116 bne.n 80012e8 <HAL_RCC_OscConfig+0x190>
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 80012ba: 4b47 ldr r3, [pc, #284] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80012bc: 681b ldr r3, [r3, #0]
+ 80012be: f003 0302 and.w r3, r3, #2
+ 80012c2: 2b00 cmp r3, #0
+ 80012c4: d005 beq.n 80012d2 <HAL_RCC_OscConfig+0x17a>
+ 80012c6: 687b ldr r3, [r7, #4]
+ 80012c8: 68db ldr r3, [r3, #12]
+ 80012ca: 2b01 cmp r3, #1
+ 80012cc: d001 beq.n 80012d2 <HAL_RCC_OscConfig+0x17a>
+ {
+ return HAL_ERROR;
+ 80012ce: 2301 movs r3, #1
+ 80012d0: e1ac b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 80012d2: 4b41 ldr r3, [pc, #260] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80012d4: 681b ldr r3, [r3, #0]
+ 80012d6: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 80012da: 687b ldr r3, [r7, #4]
+ 80012dc: 691b ldr r3, [r3, #16]
+ 80012de: 00db lsls r3, r3, #3
+ 80012e0: 493d ldr r1, [pc, #244] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80012e2: 4313 orrs r3, r2
+ 80012e4: 600b str r3, [r1, #0]
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ 80012e6: e040 b.n 800136a <HAL_RCC_OscConfig+0x212>
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+ 80012e8: 687b ldr r3, [r7, #4]
+ 80012ea: 68db ldr r3, [r3, #12]
+ 80012ec: 2b00 cmp r3, #0
+ 80012ee: d023 beq.n 8001338 <HAL_RCC_OscConfig+0x1e0>
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+ 80012f0: 4b39 ldr r3, [pc, #228] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80012f2: 681b ldr r3, [r3, #0]
+ 80012f4: 4a38 ldr r2, [pc, #224] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80012f6: f043 0301 orr.w r3, r3, #1
+ 80012fa: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 80012fc: f7ff fc42 bl 8000b84 <HAL_GetTick>
+ 8001300: 6138 str r0, [r7, #16]
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8001302: e008 b.n 8001316 <HAL_RCC_OscConfig+0x1be>
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 8001304: f7ff fc3e bl 8000b84 <HAL_GetTick>
+ 8001308: 4602 mov r2, r0
+ 800130a: 693b ldr r3, [r7, #16]
+ 800130c: 1ad3 subs r3, r2, r3
+ 800130e: 2b02 cmp r3, #2
+ 8001310: d901 bls.n 8001316 <HAL_RCC_OscConfig+0x1be>
+ {
+ return HAL_TIMEOUT;
+ 8001312: 2303 movs r3, #3
+ 8001314: e18a b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 8001316: 4b30 ldr r3, [pc, #192] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001318: 681b ldr r3, [r3, #0]
+ 800131a: f003 0302 and.w r3, r3, #2
+ 800131e: 2b00 cmp r3, #0
+ 8001320: d0f0 beq.n 8001304 <HAL_RCC_OscConfig+0x1ac>
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8001322: 4b2d ldr r3, [pc, #180] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001324: 681b ldr r3, [r3, #0]
+ 8001326: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 800132a: 687b ldr r3, [r7, #4]
+ 800132c: 691b ldr r3, [r3, #16]
+ 800132e: 00db lsls r3, r3, #3
+ 8001330: 4929 ldr r1, [pc, #164] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001332: 4313 orrs r3, r2
+ 8001334: 600b str r3, [r1, #0]
+ 8001336: e018 b.n 800136a <HAL_RCC_OscConfig+0x212>
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+ 8001338: 4b27 ldr r3, [pc, #156] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800133a: 681b ldr r3, [r3, #0]
+ 800133c: 4a26 ldr r2, [pc, #152] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 800133e: f023 0301 bic.w r3, r3, #1
+ 8001342: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001344: f7ff fc1e bl 8000b84 <HAL_GetTick>
+ 8001348: 6138 str r0, [r7, #16]
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 800134a: e008 b.n 800135e <HAL_RCC_OscConfig+0x206>
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 800134c: f7ff fc1a bl 8000b84 <HAL_GetTick>
+ 8001350: 4602 mov r2, r0
+ 8001352: 693b ldr r3, [r7, #16]
+ 8001354: 1ad3 subs r3, r2, r3
+ 8001356: 2b02 cmp r3, #2
+ 8001358: d901 bls.n 800135e <HAL_RCC_OscConfig+0x206>
+ {
+ return HAL_TIMEOUT;
+ 800135a: 2303 movs r3, #3
+ 800135c: e166 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 800135e: 4b1e ldr r3, [pc, #120] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001360: 681b ldr r3, [r3, #0]
+ 8001362: f003 0302 and.w r3, r3, #2
+ 8001366: 2b00 cmp r3, #0
+ 8001368: d1f0 bne.n 800134c <HAL_RCC_OscConfig+0x1f4>
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 800136a: 687b ldr r3, [r7, #4]
+ 800136c: 681b ldr r3, [r3, #0]
+ 800136e: f003 0308 and.w r3, r3, #8
+ 8001372: 2b00 cmp r3, #0
+ 8001374: d038 beq.n 80013e8 <HAL_RCC_OscConfig+0x290>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+ 8001376: 687b ldr r3, [r7, #4]
+ 8001378: 695b ldr r3, [r3, #20]
+ 800137a: 2b00 cmp r3, #0
+ 800137c: d019 beq.n 80013b2 <HAL_RCC_OscConfig+0x25a>
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+ 800137e: 4b16 ldr r3, [pc, #88] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001380: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8001382: 4a15 ldr r2, [pc, #84] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 8001384: f043 0301 orr.w r3, r3, #1
+ 8001388: 6753 str r3, [r2, #116] ; 0x74
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 800138a: f7ff fbfb bl 8000b84 <HAL_GetTick>
+ 800138e: 6138 str r0, [r7, #16]
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 8001390: e008 b.n 80013a4 <HAL_RCC_OscConfig+0x24c>
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 8001392: f7ff fbf7 bl 8000b84 <HAL_GetTick>
+ 8001396: 4602 mov r2, r0
+ 8001398: 693b ldr r3, [r7, #16]
+ 800139a: 1ad3 subs r3, r2, r3
+ 800139c: 2b02 cmp r3, #2
+ 800139e: d901 bls.n 80013a4 <HAL_RCC_OscConfig+0x24c>
+ {
+ return HAL_TIMEOUT;
+ 80013a0: 2303 movs r3, #3
+ 80013a2: e143 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 80013a4: 4b0c ldr r3, [pc, #48] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80013a6: 6f5b ldr r3, [r3, #116] ; 0x74
+ 80013a8: f003 0302 and.w r3, r3, #2
+ 80013ac: 2b00 cmp r3, #0
+ 80013ae: d0f0 beq.n 8001392 <HAL_RCC_OscConfig+0x23a>
+ 80013b0: e01a b.n 80013e8 <HAL_RCC_OscConfig+0x290>
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+ 80013b2: 4b09 ldr r3, [pc, #36] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80013b4: 6f5b ldr r3, [r3, #116] ; 0x74
+ 80013b6: 4a08 ldr r2, [pc, #32] ; (80013d8 <HAL_RCC_OscConfig+0x280>)
+ 80013b8: f023 0301 bic.w r3, r3, #1
+ 80013bc: 6753 str r3, [r2, #116] ; 0x74
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 80013be: f7ff fbe1 bl 8000b84 <HAL_GetTick>
+ 80013c2: 6138 str r0, [r7, #16]
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 80013c4: e00a b.n 80013dc <HAL_RCC_OscConfig+0x284>
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 80013c6: f7ff fbdd bl 8000b84 <HAL_GetTick>
+ 80013ca: 4602 mov r2, r0
+ 80013cc: 693b ldr r3, [r7, #16]
+ 80013ce: 1ad3 subs r3, r2, r3
+ 80013d0: 2b02 cmp r3, #2
+ 80013d2: d903 bls.n 80013dc <HAL_RCC_OscConfig+0x284>
+ {
+ return HAL_TIMEOUT;
+ 80013d4: 2303 movs r3, #3
+ 80013d6: e129 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ 80013d8: 40023800 .word 0x40023800
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 80013dc: 4b95 ldr r3, [pc, #596] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80013de: 6f5b ldr r3, [r3, #116] ; 0x74
+ 80013e0: f003 0302 and.w r3, r3, #2
+ 80013e4: 2b00 cmp r3, #0
+ 80013e6: d1ee bne.n 80013c6 <HAL_RCC_OscConfig+0x26e>
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 80013e8: 687b ldr r3, [r7, #4]
+ 80013ea: 681b ldr r3, [r3, #0]
+ 80013ec: f003 0304 and.w r3, r3, #4
+ 80013f0: 2b00 cmp r3, #0
+ 80013f2: f000 80a4 beq.w 800153e <HAL_RCC_OscConfig+0x3e6>
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 80013f6: 4b8f ldr r3, [pc, #572] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80013f8: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80013fa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 80013fe: 2b00 cmp r3, #0
+ 8001400: d10d bne.n 800141e <HAL_RCC_OscConfig+0x2c6>
+ {
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8001402: 4b8c ldr r3, [pc, #560] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001404: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001406: 4a8b ldr r2, [pc, #556] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001408: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 800140c: 6413 str r3, [r2, #64] ; 0x40
+ 800140e: 4b89 ldr r3, [pc, #548] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001410: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001412: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001416: 60fb str r3, [r7, #12]
+ 8001418: 68fb ldr r3, [r7, #12]
+ pwrclkchanged = SET;
+ 800141a: 2301 movs r3, #1
+ 800141c: 75fb strb r3, [r7, #23]
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 800141e: 4b86 ldr r3, [pc, #536] ; (8001638 <HAL_RCC_OscConfig+0x4e0>)
+ 8001420: 681b ldr r3, [r3, #0]
+ 8001422: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8001426: 2b00 cmp r3, #0
+ 8001428: d118 bne.n 800145c <HAL_RCC_OscConfig+0x304>
+ {
+ /* Enable write access to Backup domain */
+ PWR->CR1 |= PWR_CR1_DBP;
+ 800142a: 4b83 ldr r3, [pc, #524] ; (8001638 <HAL_RCC_OscConfig+0x4e0>)
+ 800142c: 681b ldr r3, [r3, #0]
+ 800142e: 4a82 ldr r2, [pc, #520] ; (8001638 <HAL_RCC_OscConfig+0x4e0>)
+ 8001430: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 8001434: 6013 str r3, [r2, #0]
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+ 8001436: f7ff fba5 bl 8000b84 <HAL_GetTick>
+ 800143a: 6138 str r0, [r7, #16]
+
+ while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 800143c: e008 b.n 8001450 <HAL_RCC_OscConfig+0x2f8>
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ 800143e: f7ff fba1 bl 8000b84 <HAL_GetTick>
+ 8001442: 4602 mov r2, r0
+ 8001444: 693b ldr r3, [r7, #16]
+ 8001446: 1ad3 subs r3, r2, r3
+ 8001448: 2b64 cmp r3, #100 ; 0x64
+ 800144a: d901 bls.n 8001450 <HAL_RCC_OscConfig+0x2f8>
+ {
+ return HAL_TIMEOUT;
+ 800144c: 2303 movs r3, #3
+ 800144e: e0ed b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ 8001450: 4b79 ldr r3, [pc, #484] ; (8001638 <HAL_RCC_OscConfig+0x4e0>)
+ 8001452: 681b ldr r3, [r3, #0]
+ 8001454: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8001458: 2b00 cmp r3, #0
+ 800145a: d0f0 beq.n 800143e <HAL_RCC_OscConfig+0x2e6>
+ }
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 800145c: 687b ldr r3, [r7, #4]
+ 800145e: 689b ldr r3, [r3, #8]
+ 8001460: 2b01 cmp r3, #1
+ 8001462: d106 bne.n 8001472 <HAL_RCC_OscConfig+0x31a>
+ 8001464: 4b73 ldr r3, [pc, #460] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001466: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001468: 4a72 ldr r2, [pc, #456] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 800146a: f043 0301 orr.w r3, r3, #1
+ 800146e: 6713 str r3, [r2, #112] ; 0x70
+ 8001470: e02d b.n 80014ce <HAL_RCC_OscConfig+0x376>
+ 8001472: 687b ldr r3, [r7, #4]
+ 8001474: 689b ldr r3, [r3, #8]
+ 8001476: 2b00 cmp r3, #0
+ 8001478: d10c bne.n 8001494 <HAL_RCC_OscConfig+0x33c>
+ 800147a: 4b6e ldr r3, [pc, #440] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 800147c: 6f1b ldr r3, [r3, #112] ; 0x70
+ 800147e: 4a6d ldr r2, [pc, #436] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001480: f023 0301 bic.w r3, r3, #1
+ 8001484: 6713 str r3, [r2, #112] ; 0x70
+ 8001486: 4b6b ldr r3, [pc, #428] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001488: 6f1b ldr r3, [r3, #112] ; 0x70
+ 800148a: 4a6a ldr r2, [pc, #424] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 800148c: f023 0304 bic.w r3, r3, #4
+ 8001490: 6713 str r3, [r2, #112] ; 0x70
+ 8001492: e01c b.n 80014ce <HAL_RCC_OscConfig+0x376>
+ 8001494: 687b ldr r3, [r7, #4]
+ 8001496: 689b ldr r3, [r3, #8]
+ 8001498: 2b05 cmp r3, #5
+ 800149a: d10c bne.n 80014b6 <HAL_RCC_OscConfig+0x35e>
+ 800149c: 4b65 ldr r3, [pc, #404] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 800149e: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80014a0: 4a64 ldr r2, [pc, #400] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014a2: f043 0304 orr.w r3, r3, #4
+ 80014a6: 6713 str r3, [r2, #112] ; 0x70
+ 80014a8: 4b62 ldr r3, [pc, #392] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014aa: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80014ac: 4a61 ldr r2, [pc, #388] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014ae: f043 0301 orr.w r3, r3, #1
+ 80014b2: 6713 str r3, [r2, #112] ; 0x70
+ 80014b4: e00b b.n 80014ce <HAL_RCC_OscConfig+0x376>
+ 80014b6: 4b5f ldr r3, [pc, #380] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014b8: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80014ba: 4a5e ldr r2, [pc, #376] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014bc: f023 0301 bic.w r3, r3, #1
+ 80014c0: 6713 str r3, [r2, #112] ; 0x70
+ 80014c2: 4b5c ldr r3, [pc, #368] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014c4: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80014c6: 4a5b ldr r2, [pc, #364] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014c8: f023 0304 bic.w r3, r3, #4
+ 80014cc: 6713 str r3, [r2, #112] ; 0x70
+ /* Check the LSE State */
+ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ 80014ce: 687b ldr r3, [r7, #4]
+ 80014d0: 689b ldr r3, [r3, #8]
+ 80014d2: 2b00 cmp r3, #0
+ 80014d4: d015 beq.n 8001502 <HAL_RCC_OscConfig+0x3aa>
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 80014d6: f7ff fb55 bl 8000b84 <HAL_GetTick>
+ 80014da: 6138 str r0, [r7, #16]
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 80014dc: e00a b.n 80014f4 <HAL_RCC_OscConfig+0x39c>
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 80014de: f7ff fb51 bl 8000b84 <HAL_GetTick>
+ 80014e2: 4602 mov r2, r0
+ 80014e4: 693b ldr r3, [r7, #16]
+ 80014e6: 1ad3 subs r3, r2, r3
+ 80014e8: f241 3288 movw r2, #5000 ; 0x1388
+ 80014ec: 4293 cmp r3, r2
+ 80014ee: d901 bls.n 80014f4 <HAL_RCC_OscConfig+0x39c>
+ {
+ return HAL_TIMEOUT;
+ 80014f0: 2303 movs r3, #3
+ 80014f2: e09b b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 80014f4: 4b4f ldr r3, [pc, #316] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80014f6: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80014f8: f003 0302 and.w r3, r3, #2
+ 80014fc: 2b00 cmp r3, #0
+ 80014fe: d0ee beq.n 80014de <HAL_RCC_OscConfig+0x386>
+ 8001500: e014 b.n 800152c <HAL_RCC_OscConfig+0x3d4>
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001502: f7ff fb3f bl 8000b84 <HAL_GetTick>
+ 8001506: 6138 str r0, [r7, #16]
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 8001508: e00a b.n 8001520 <HAL_RCC_OscConfig+0x3c8>
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 800150a: f7ff fb3b bl 8000b84 <HAL_GetTick>
+ 800150e: 4602 mov r2, r0
+ 8001510: 693b ldr r3, [r7, #16]
+ 8001512: 1ad3 subs r3, r2, r3
+ 8001514: f241 3288 movw r2, #5000 ; 0x1388
+ 8001518: 4293 cmp r3, r2
+ 800151a: d901 bls.n 8001520 <HAL_RCC_OscConfig+0x3c8>
+ {
+ return HAL_TIMEOUT;
+ 800151c: 2303 movs r3, #3
+ 800151e: e085 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 8001520: 4b44 ldr r3, [pc, #272] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001522: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001524: f003 0302 and.w r3, r3, #2
+ 8001528: 2b00 cmp r3, #0
+ 800152a: d1ee bne.n 800150a <HAL_RCC_OscConfig+0x3b2>
+ }
+ }
+ }
+
+ /* Restore clock configuration if changed */
+ if(pwrclkchanged == SET)
+ 800152c: 7dfb ldrb r3, [r7, #23]
+ 800152e: 2b01 cmp r3, #1
+ 8001530: d105 bne.n 800153e <HAL_RCC_OscConfig+0x3e6>
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ 8001532: 4b40 ldr r3, [pc, #256] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001534: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001536: 4a3f ldr r2, [pc, #252] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001538: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 800153c: 6413 str r3, [r2, #64] ; 0x40
+ }
+ }
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 800153e: 687b ldr r3, [r7, #4]
+ 8001540: 699b ldr r3, [r3, #24]
+ 8001542: 2b00 cmp r3, #0
+ 8001544: d071 beq.n 800162a <HAL_RCC_OscConfig+0x4d2>
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 8001546: 4b3b ldr r3, [pc, #236] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001548: 689b ldr r3, [r3, #8]
+ 800154a: f003 030c and.w r3, r3, #12
+ 800154e: 2b08 cmp r3, #8
+ 8001550: d069 beq.n 8001626 <HAL_RCC_OscConfig+0x4ce>
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 8001552: 687b ldr r3, [r7, #4]
+ 8001554: 699b ldr r3, [r3, #24]
+ 8001556: 2b02 cmp r3, #2
+ 8001558: d14b bne.n 80015f2 <HAL_RCC_OscConfig+0x49a>
+#if defined (RCC_PLLCFGR_PLLR)
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+#endif
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+ 800155a: 4b36 ldr r3, [pc, #216] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 800155c: 681b ldr r3, [r3, #0]
+ 800155e: 4a35 ldr r2, [pc, #212] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001560: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8001564: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001566: f7ff fb0d bl 8000b84 <HAL_GetTick>
+ 800156a: 6138 str r0, [r7, #16]
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 800156c: e008 b.n 8001580 <HAL_RCC_OscConfig+0x428>
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 800156e: f7ff fb09 bl 8000b84 <HAL_GetTick>
+ 8001572: 4602 mov r2, r0
+ 8001574: 693b ldr r3, [r7, #16]
+ 8001576: 1ad3 subs r3, r2, r3
+ 8001578: 2b02 cmp r3, #2
+ 800157a: d901 bls.n 8001580 <HAL_RCC_OscConfig+0x428>
+ {
+ return HAL_TIMEOUT;
+ 800157c: 2303 movs r3, #3
+ 800157e: e055 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 8001580: 4b2c ldr r3, [pc, #176] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 8001582: 681b ldr r3, [r3, #0]
+ 8001584: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8001588: 2b00 cmp r3, #0
+ 800158a: d1f0 bne.n 800156e <HAL_RCC_OscConfig+0x416>
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division factors. */
+#if defined (RCC_PLLCFGR_PLLR)
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 800158c: 687b ldr r3, [r7, #4]
+ 800158e: 69da ldr r2, [r3, #28]
+ 8001590: 687b ldr r3, [r7, #4]
+ 8001592: 6a1b ldr r3, [r3, #32]
+ 8001594: 431a orrs r2, r3
+ 8001596: 687b ldr r3, [r7, #4]
+ 8001598: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800159a: 019b lsls r3, r3, #6
+ 800159c: 431a orrs r2, r3
+ 800159e: 687b ldr r3, [r7, #4]
+ 80015a0: 6a9b ldr r3, [r3, #40] ; 0x28
+ 80015a2: 085b lsrs r3, r3, #1
+ 80015a4: 3b01 subs r3, #1
+ 80015a6: 041b lsls r3, r3, #16
+ 80015a8: 431a orrs r2, r3
+ 80015aa: 687b ldr r3, [r7, #4]
+ 80015ac: 6adb ldr r3, [r3, #44] ; 0x2c
+ 80015ae: 061b lsls r3, r3, #24
+ 80015b0: 431a orrs r2, r3
+ 80015b2: 687b ldr r3, [r7, #4]
+ 80015b4: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80015b6: 071b lsls r3, r3, #28
+ 80015b8: 491e ldr r1, [pc, #120] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80015ba: 4313 orrs r3, r2
+ 80015bc: 604b str r3, [r1, #4]
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ);
+#endif
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+ 80015be: 4b1d ldr r3, [pc, #116] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80015c0: 681b ldr r3, [r3, #0]
+ 80015c2: 4a1c ldr r2, [pc, #112] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80015c4: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
+ 80015c8: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 80015ca: f7ff fadb bl 8000b84 <HAL_GetTick>
+ 80015ce: 6138 str r0, [r7, #16]
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 80015d0: e008 b.n 80015e4 <HAL_RCC_OscConfig+0x48c>
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 80015d2: f7ff fad7 bl 8000b84 <HAL_GetTick>
+ 80015d6: 4602 mov r2, r0
+ 80015d8: 693b ldr r3, [r7, #16]
+ 80015da: 1ad3 subs r3, r2, r3
+ 80015dc: 2b02 cmp r3, #2
+ 80015de: d901 bls.n 80015e4 <HAL_RCC_OscConfig+0x48c>
+ {
+ return HAL_TIMEOUT;
+ 80015e0: 2303 movs r3, #3
+ 80015e2: e023 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 80015e4: 4b13 ldr r3, [pc, #76] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80015e6: 681b ldr r3, [r3, #0]
+ 80015e8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 80015ec: 2b00 cmp r3, #0
+ 80015ee: d0f0 beq.n 80015d2 <HAL_RCC_OscConfig+0x47a>
+ 80015f0: e01b b.n 800162a <HAL_RCC_OscConfig+0x4d2>
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+ 80015f2: 4b10 ldr r3, [pc, #64] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80015f4: 681b ldr r3, [r3, #0]
+ 80015f6: 4a0f ldr r2, [pc, #60] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 80015f8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 80015fc: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 80015fe: f7ff fac1 bl 8000b84 <HAL_GetTick>
+ 8001602: 6138 str r0, [r7, #16]
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 8001604: e008 b.n 8001618 <HAL_RCC_OscConfig+0x4c0>
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 8001606: f7ff fabd bl 8000b84 <HAL_GetTick>
+ 800160a: 4602 mov r2, r0
+ 800160c: 693b ldr r3, [r7, #16]
+ 800160e: 1ad3 subs r3, r2, r3
+ 8001610: 2b02 cmp r3, #2
+ 8001612: d901 bls.n 8001618 <HAL_RCC_OscConfig+0x4c0>
+ {
+ return HAL_TIMEOUT;
+ 8001614: 2303 movs r3, #3
+ 8001616: e009 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ 8001618: 4b06 ldr r3, [pc, #24] ; (8001634 <HAL_RCC_OscConfig+0x4dc>)
+ 800161a: 681b ldr r3, [r3, #0]
+ 800161c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8001620: 2b00 cmp r3, #0
+ 8001622: d1f0 bne.n 8001606 <HAL_RCC_OscConfig+0x4ae>
+ 8001624: e001 b.n 800162a <HAL_RCC_OscConfig+0x4d2>
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ 8001626: 2301 movs r3, #1
+ 8001628: e000 b.n 800162c <HAL_RCC_OscConfig+0x4d4>
+ }
+ }
+ return HAL_OK;
+ 800162a: 2300 movs r3, #0
+}
+ 800162c: 4618 mov r0, r3
+ 800162e: 3718 adds r7, #24
+ 8001630: 46bd mov sp, r7
+ 8001632: bd80 pop {r7, pc}
+ 8001634: 40023800 .word 0x40023800
+ 8001638: 40007000 .word 0x40007000
+
+0800163c <HAL_RCC_ClockConfig>:
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above "Initialization/de-initialization functions")
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ 800163c: b580 push {r7, lr}
+ 800163e: b084 sub sp, #16
+ 8001640: af00 add r7, sp, #0
+ 8001642: 6078 str r0, [r7, #4]
+ 8001644: 6039 str r1, [r7, #0]
+ uint32_t tickstart = 0;
+ 8001646: 2300 movs r3, #0
+ 8001648: 60fb str r3, [r7, #12]
+
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ 800164a: 687b ldr r3, [r7, #4]
+ 800164c: 2b00 cmp r3, #0
+ 800164e: d101 bne.n 8001654 <HAL_RCC_ClockConfig+0x18>
+ {
+ return HAL_ERROR;
+ 8001650: 2301 movs r3, #1
+ 8001652: e0ce b.n 80017f2 <HAL_RCC_ClockConfig+0x1b6>
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device. */
+
+ /* Increasing the CPU frequency */
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
+ 8001654: 4b69 ldr r3, [pc, #420] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 8001656: 681b ldr r3, [r3, #0]
+ 8001658: f003 030f and.w r3, r3, #15
+ 800165c: 683a ldr r2, [r7, #0]
+ 800165e: 429a cmp r2, r3
+ 8001660: d910 bls.n 8001684 <HAL_RCC_ClockConfig+0x48>
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+ 8001662: 4b66 ldr r3, [pc, #408] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 8001664: 681b ldr r3, [r3, #0]
+ 8001666: f023 020f bic.w r2, r3, #15
+ 800166a: 4964 ldr r1, [pc, #400] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 800166c: 683b ldr r3, [r7, #0]
+ 800166e: 4313 orrs r3, r2
+ 8001670: 600b str r3, [r1, #0]
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8001672: 4b62 ldr r3, [pc, #392] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 8001674: 681b ldr r3, [r3, #0]
+ 8001676: f003 030f and.w r3, r3, #15
+ 800167a: 683a ldr r2, [r7, #0]
+ 800167c: 429a cmp r2, r3
+ 800167e: d001 beq.n 8001684 <HAL_RCC_ClockConfig+0x48>
+ {
+ return HAL_ERROR;
+ 8001680: 2301 movs r3, #1
+ 8001682: e0b6 b.n 80017f2 <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 8001684: 687b ldr r3, [r7, #4]
+ 8001686: 681b ldr r3, [r3, #0]
+ 8001688: f003 0302 and.w r3, r3, #2
+ 800168c: 2b00 cmp r3, #0
+ 800168e: d020 beq.n 80016d2 <HAL_RCC_ClockConfig+0x96>
+ {
+ /* Set the highest APBx dividers in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8001690: 687b ldr r3, [r7, #4]
+ 8001692: 681b ldr r3, [r3, #0]
+ 8001694: f003 0304 and.w r3, r3, #4
+ 8001698: 2b00 cmp r3, #0
+ 800169a: d005 beq.n 80016a8 <HAL_RCC_ClockConfig+0x6c>
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ 800169c: 4b58 ldr r3, [pc, #352] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 800169e: 689b ldr r3, [r3, #8]
+ 80016a0: 4a57 ldr r2, [pc, #348] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80016a2: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
+ 80016a6: 6093 str r3, [r2, #8]
+ }
+
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 80016a8: 687b ldr r3, [r7, #4]
+ 80016aa: 681b ldr r3, [r3, #0]
+ 80016ac: f003 0308 and.w r3, r3, #8
+ 80016b0: 2b00 cmp r3, #0
+ 80016b2: d005 beq.n 80016c0 <HAL_RCC_ClockConfig+0x84>
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ 80016b4: 4b52 ldr r3, [pc, #328] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80016b6: 689b ldr r3, [r3, #8]
+ 80016b8: 4a51 ldr r2, [pc, #324] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80016ba: f443 4360 orr.w r3, r3, #57344 ; 0xe000
+ 80016be: 6093 str r3, [r2, #8]
+ }
+
+ /* Set the new HCLK clock divider */
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 80016c0: 4b4f ldr r3, [pc, #316] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80016c2: 689b ldr r3, [r3, #8]
+ 80016c4: f023 02f0 bic.w r2, r3, #240 ; 0xf0
+ 80016c8: 687b ldr r3, [r7, #4]
+ 80016ca: 689b ldr r3, [r3, #8]
+ 80016cc: 494c ldr r1, [pc, #304] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80016ce: 4313 orrs r3, r2
+ 80016d0: 608b str r3, [r1, #8]
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 80016d2: 687b ldr r3, [r7, #4]
+ 80016d4: 681b ldr r3, [r3, #0]
+ 80016d6: f003 0301 and.w r3, r3, #1
+ 80016da: 2b00 cmp r3, #0
+ 80016dc: d040 beq.n 8001760 <HAL_RCC_ClockConfig+0x124>
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 80016de: 687b ldr r3, [r7, #4]
+ 80016e0: 685b ldr r3, [r3, #4]
+ 80016e2: 2b01 cmp r3, #1
+ 80016e4: d107 bne.n 80016f6 <HAL_RCC_ClockConfig+0xba>
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 80016e6: 4b46 ldr r3, [pc, #280] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80016e8: 681b ldr r3, [r3, #0]
+ 80016ea: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80016ee: 2b00 cmp r3, #0
+ 80016f0: d115 bne.n 800171e <HAL_RCC_ClockConfig+0xe2>
+ {
+ return HAL_ERROR;
+ 80016f2: 2301 movs r3, #1
+ 80016f4: e07d b.n 80017f2 <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 80016f6: 687b ldr r3, [r7, #4]
+ 80016f8: 685b ldr r3, [r3, #4]
+ 80016fa: 2b02 cmp r3, #2
+ 80016fc: d107 bne.n 800170e <HAL_RCC_ClockConfig+0xd2>
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 80016fe: 4b40 ldr r3, [pc, #256] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 8001700: 681b ldr r3, [r3, #0]
+ 8001702: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8001706: 2b00 cmp r3, #0
+ 8001708: d109 bne.n 800171e <HAL_RCC_ClockConfig+0xe2>
+ {
+ return HAL_ERROR;
+ 800170a: 2301 movs r3, #1
+ 800170c: e071 b.n 80017f2 <HAL_RCC_ClockConfig+0x1b6>
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 800170e: 4b3c ldr r3, [pc, #240] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 8001710: 681b ldr r3, [r3, #0]
+ 8001712: f003 0302 and.w r3, r3, #2
+ 8001716: 2b00 cmp r3, #0
+ 8001718: d101 bne.n 800171e <HAL_RCC_ClockConfig+0xe2>
+ {
+ return HAL_ERROR;
+ 800171a: 2301 movs r3, #1
+ 800171c: e069 b.n 80017f2 <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 800171e: 4b38 ldr r3, [pc, #224] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 8001720: 689b ldr r3, [r3, #8]
+ 8001722: f023 0203 bic.w r2, r3, #3
+ 8001726: 687b ldr r3, [r7, #4]
+ 8001728: 685b ldr r3, [r3, #4]
+ 800172a: 4935 ldr r1, [pc, #212] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 800172c: 4313 orrs r3, r2
+ 800172e: 608b str r3, [r1, #8]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001730: f7ff fa28 bl 8000b84 <HAL_GetTick>
+ 8001734: 60f8 str r0, [r7, #12]
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8001736: e00a b.n 800174e <HAL_RCC_ClockConfig+0x112>
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8001738: f7ff fa24 bl 8000b84 <HAL_GetTick>
+ 800173c: 4602 mov r2, r0
+ 800173e: 68fb ldr r3, [r7, #12]
+ 8001740: 1ad3 subs r3, r2, r3
+ 8001742: f241 3288 movw r2, #5000 ; 0x1388
+ 8001746: 4293 cmp r3, r2
+ 8001748: d901 bls.n 800174e <HAL_RCC_ClockConfig+0x112>
+ {
+ return HAL_TIMEOUT;
+ 800174a: 2303 movs r3, #3
+ 800174c: e051 b.n 80017f2 <HAL_RCC_ClockConfig+0x1b6>
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 800174e: 4b2c ldr r3, [pc, #176] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 8001750: 689b ldr r3, [r3, #8]
+ 8001752: f003 020c and.w r2, r3, #12
+ 8001756: 687b ldr r3, [r7, #4]
+ 8001758: 685b ldr r3, [r3, #4]
+ 800175a: 009b lsls r3, r3, #2
+ 800175c: 429a cmp r2, r3
+ 800175e: d1eb bne.n 8001738 <HAL_RCC_ClockConfig+0xfc>
+ }
+ }
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
+ 8001760: 4b26 ldr r3, [pc, #152] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 8001762: 681b ldr r3, [r3, #0]
+ 8001764: f003 030f and.w r3, r3, #15
+ 8001768: 683a ldr r2, [r7, #0]
+ 800176a: 429a cmp r2, r3
+ 800176c: d210 bcs.n 8001790 <HAL_RCC_ClockConfig+0x154>
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+ 800176e: 4b23 ldr r3, [pc, #140] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 8001770: 681b ldr r3, [r3, #0]
+ 8001772: f023 020f bic.w r2, r3, #15
+ 8001776: 4921 ldr r1, [pc, #132] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 8001778: 683b ldr r3, [r7, #0]
+ 800177a: 4313 orrs r3, r2
+ 800177c: 600b str r3, [r1, #0]
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
+ 800177e: 4b1f ldr r3, [pc, #124] ; (80017fc <HAL_RCC_ClockConfig+0x1c0>)
+ 8001780: 681b ldr r3, [r3, #0]
+ 8001782: f003 030f and.w r3, r3, #15
+ 8001786: 683a ldr r2, [r7, #0]
+ 8001788: 429a cmp r2, r3
+ 800178a: d001 beq.n 8001790 <HAL_RCC_ClockConfig+0x154>
+ {
+ return HAL_ERROR;
+ 800178c: 2301 movs r3, #1
+ 800178e: e030 b.n 80017f2 <HAL_RCC_ClockConfig+0x1b6>
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8001790: 687b ldr r3, [r7, #4]
+ 8001792: 681b ldr r3, [r3, #0]
+ 8001794: f003 0304 and.w r3, r3, #4
+ 8001798: 2b00 cmp r3, #0
+ 800179a: d008 beq.n 80017ae <HAL_RCC_ClockConfig+0x172>
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 800179c: 4b18 ldr r3, [pc, #96] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 800179e: 689b ldr r3, [r3, #8]
+ 80017a0: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
+ 80017a4: 687b ldr r3, [r7, #4]
+ 80017a6: 68db ldr r3, [r3, #12]
+ 80017a8: 4915 ldr r1, [pc, #84] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80017aa: 4313 orrs r3, r2
+ 80017ac: 608b str r3, [r1, #8]
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 80017ae: 687b ldr r3, [r7, #4]
+ 80017b0: 681b ldr r3, [r3, #0]
+ 80017b2: f003 0308 and.w r3, r3, #8
+ 80017b6: 2b00 cmp r3, #0
+ 80017b8: d009 beq.n 80017ce <HAL_RCC_ClockConfig+0x192>
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ 80017ba: 4b11 ldr r3, [pc, #68] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80017bc: 689b ldr r3, [r3, #8]
+ 80017be: f423 4260 bic.w r2, r3, #57344 ; 0xe000
+ 80017c2: 687b ldr r3, [r7, #4]
+ 80017c4: 691b ldr r3, [r3, #16]
+ 80017c6: 00db lsls r3, r3, #3
+ 80017c8: 490d ldr r1, [pc, #52] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80017ca: 4313 orrs r3, r2
+ 80017cc: 608b str r3, [r1, #8]
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+ 80017ce: f000 f81d bl 800180c <HAL_RCC_GetSysClockFreq>
+ 80017d2: 4601 mov r1, r0
+ 80017d4: 4b0a ldr r3, [pc, #40] ; (8001800 <HAL_RCC_ClockConfig+0x1c4>)
+ 80017d6: 689b ldr r3, [r3, #8]
+ 80017d8: 091b lsrs r3, r3, #4
+ 80017da: f003 030f and.w r3, r3, #15
+ 80017de: 4a09 ldr r2, [pc, #36] ; (8001804 <HAL_RCC_ClockConfig+0x1c8>)
+ 80017e0: 5cd3 ldrb r3, [r2, r3]
+ 80017e2: fa21 f303 lsr.w r3, r1, r3
+ 80017e6: 4a08 ldr r2, [pc, #32] ; (8001808 <HAL_RCC_ClockConfig+0x1cc>)
+ 80017e8: 6013 str r3, [r2, #0]
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+ 80017ea: 2000 movs r0, #0
+ 80017ec: f7ff f986 bl 8000afc <HAL_InitTick>
+
+ return HAL_OK;
+ 80017f0: 2300 movs r3, #0
+}
+ 80017f2: 4618 mov r0, r3
+ 80017f4: 3710 adds r7, #16
+ 80017f6: 46bd mov sp, r7
+ 80017f8: bd80 pop {r7, pc}
+ 80017fa: bf00 nop
+ 80017fc: 40023c00 .word 0x40023c00
+ 8001800: 40023800 .word 0x40023800
+ 8001804: 08003960 .word 0x08003960
+ 8001808: 20000000 .word 0x20000000
+
+0800180c <HAL_RCC_GetSysClockFreq>:
+ *
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ 800180c: b5f0 push {r4, r5, r6, r7, lr}
+ 800180e: b085 sub sp, #20
+ 8001810: af00 add r7, sp, #0
+ uint32_t pllm = 0, pllvco = 0, pllp = 0;
+ 8001812: 2300 movs r3, #0
+ 8001814: 607b str r3, [r7, #4]
+ 8001816: 2300 movs r3, #0
+ 8001818: 60fb str r3, [r7, #12]
+ 800181a: 2300 movs r3, #0
+ 800181c: 603b str r3, [r7, #0]
+ uint32_t sysclockfreq = 0;
+ 800181e: 2300 movs r3, #0
+ 8001820: 60bb str r3, [r7, #8]
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ 8001822: 4b50 ldr r3, [pc, #320] ; (8001964 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001824: 689b ldr r3, [r3, #8]
+ 8001826: f003 030c and.w r3, r3, #12
+ 800182a: 2b04 cmp r3, #4
+ 800182c: d007 beq.n 800183e <HAL_RCC_GetSysClockFreq+0x32>
+ 800182e: 2b08 cmp r3, #8
+ 8001830: d008 beq.n 8001844 <HAL_RCC_GetSysClockFreq+0x38>
+ 8001832: 2b00 cmp r3, #0
+ 8001834: f040 808d bne.w 8001952 <HAL_RCC_GetSysClockFreq+0x146>
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ {
+ sysclockfreq = HSI_VALUE;
+ 8001838: 4b4b ldr r3, [pc, #300] ; (8001968 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 800183a: 60bb str r3, [r7, #8]
+ break;
+ 800183c: e08c b.n 8001958 <HAL_RCC_GetSysClockFreq+0x14c>
+ }
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ {
+ sysclockfreq = HSE_VALUE;
+ 800183e: 4b4b ldr r3, [pc, #300] ; (800196c <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001840: 60bb str r3, [r7, #8]
+ break;
+ 8001842: e089 b.n 8001958 <HAL_RCC_GetSysClockFreq+0x14c>
+ }
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
+ {
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP */
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ 8001844: 4b47 ldr r3, [pc, #284] ; (8001964 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001846: 685b ldr r3, [r3, #4]
+ 8001848: f003 033f and.w r3, r3, #63 ; 0x3f
+ 800184c: 607b str r3, [r7, #4]
+ if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
+ 800184e: 4b45 ldr r3, [pc, #276] ; (8001964 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001850: 685b ldr r3, [r3, #4]
+ 8001852: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8001856: 2b00 cmp r3, #0
+ 8001858: d023 beq.n 80018a2 <HAL_RCC_GetSysClockFreq+0x96>
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ 800185a: 4b42 ldr r3, [pc, #264] ; (8001964 <HAL_RCC_GetSysClockFreq+0x158>)
+ 800185c: 685b ldr r3, [r3, #4]
+ 800185e: 099b lsrs r3, r3, #6
+ 8001860: f04f 0400 mov.w r4, #0
+ 8001864: f240 11ff movw r1, #511 ; 0x1ff
+ 8001868: f04f 0200 mov.w r2, #0
+ 800186c: ea03 0501 and.w r5, r3, r1
+ 8001870: ea04 0602 and.w r6, r4, r2
+ 8001874: 4a3d ldr r2, [pc, #244] ; (800196c <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001876: fb02 f106 mul.w r1, r2, r6
+ 800187a: 2200 movs r2, #0
+ 800187c: fb02 f205 mul.w r2, r2, r5
+ 8001880: 440a add r2, r1
+ 8001882: 493a ldr r1, [pc, #232] ; (800196c <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001884: fba5 0101 umull r0, r1, r5, r1
+ 8001888: 1853 adds r3, r2, r1
+ 800188a: 4619 mov r1, r3
+ 800188c: 687b ldr r3, [r7, #4]
+ 800188e: f04f 0400 mov.w r4, #0
+ 8001892: 461a mov r2, r3
+ 8001894: 4623 mov r3, r4
+ 8001896: f7fe fccf bl 8000238 <__aeabi_uldivmod>
+ 800189a: 4603 mov r3, r0
+ 800189c: 460c mov r4, r1
+ 800189e: 60fb str r3, [r7, #12]
+ 80018a0: e049 b.n 8001936 <HAL_RCC_GetSysClockFreq+0x12a>
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+ 80018a2: 4b30 ldr r3, [pc, #192] ; (8001964 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80018a4: 685b ldr r3, [r3, #4]
+ 80018a6: 099b lsrs r3, r3, #6
+ 80018a8: f04f 0400 mov.w r4, #0
+ 80018ac: f240 11ff movw r1, #511 ; 0x1ff
+ 80018b0: f04f 0200 mov.w r2, #0
+ 80018b4: ea03 0501 and.w r5, r3, r1
+ 80018b8: ea04 0602 and.w r6, r4, r2
+ 80018bc: 4629 mov r1, r5
+ 80018be: 4632 mov r2, r6
+ 80018c0: f04f 0300 mov.w r3, #0
+ 80018c4: f04f 0400 mov.w r4, #0
+ 80018c8: 0154 lsls r4, r2, #5
+ 80018ca: ea44 64d1 orr.w r4, r4, r1, lsr #27
+ 80018ce: 014b lsls r3, r1, #5
+ 80018d0: 4619 mov r1, r3
+ 80018d2: 4622 mov r2, r4
+ 80018d4: 1b49 subs r1, r1, r5
+ 80018d6: eb62 0206 sbc.w r2, r2, r6
+ 80018da: f04f 0300 mov.w r3, #0
+ 80018de: f04f 0400 mov.w r4, #0
+ 80018e2: 0194 lsls r4, r2, #6
+ 80018e4: ea44 6491 orr.w r4, r4, r1, lsr #26
+ 80018e8: 018b lsls r3, r1, #6
+ 80018ea: 1a5b subs r3, r3, r1
+ 80018ec: eb64 0402 sbc.w r4, r4, r2
+ 80018f0: f04f 0100 mov.w r1, #0
+ 80018f4: f04f 0200 mov.w r2, #0
+ 80018f8: 00e2 lsls r2, r4, #3
+ 80018fa: ea42 7253 orr.w r2, r2, r3, lsr #29
+ 80018fe: 00d9 lsls r1, r3, #3
+ 8001900: 460b mov r3, r1
+ 8001902: 4614 mov r4, r2
+ 8001904: 195b adds r3, r3, r5
+ 8001906: eb44 0406 adc.w r4, r4, r6
+ 800190a: f04f 0100 mov.w r1, #0
+ 800190e: f04f 0200 mov.w r2, #0
+ 8001912: 02a2 lsls r2, r4, #10
+ 8001914: ea42 5293 orr.w r2, r2, r3, lsr #22
+ 8001918: 0299 lsls r1, r3, #10
+ 800191a: 460b mov r3, r1
+ 800191c: 4614 mov r4, r2
+ 800191e: 4618 mov r0, r3
+ 8001920: 4621 mov r1, r4
+ 8001922: 687b ldr r3, [r7, #4]
+ 8001924: f04f 0400 mov.w r4, #0
+ 8001928: 461a mov r2, r3
+ 800192a: 4623 mov r3, r4
+ 800192c: f7fe fc84 bl 8000238 <__aeabi_uldivmod>
+ 8001930: 4603 mov r3, r0
+ 8001932: 460c mov r4, r1
+ 8001934: 60fb str r3, [r7, #12]
+ }
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
+ 8001936: 4b0b ldr r3, [pc, #44] ; (8001964 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001938: 685b ldr r3, [r3, #4]
+ 800193a: 0c1b lsrs r3, r3, #16
+ 800193c: f003 0303 and.w r3, r3, #3
+ 8001940: 3301 adds r3, #1
+ 8001942: 005b lsls r3, r3, #1
+ 8001944: 603b str r3, [r7, #0]
+
+ sysclockfreq = pllvco/pllp;
+ 8001946: 68fa ldr r2, [r7, #12]
+ 8001948: 683b ldr r3, [r7, #0]
+ 800194a: fbb2 f3f3 udiv r3, r2, r3
+ 800194e: 60bb str r3, [r7, #8]
+ break;
+ 8001950: e002 b.n 8001958 <HAL_RCC_GetSysClockFreq+0x14c>
+ }
+ default:
+ {
+ sysclockfreq = HSI_VALUE;
+ 8001952: 4b05 ldr r3, [pc, #20] ; (8001968 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 8001954: 60bb str r3, [r7, #8]
+ break;
+ 8001956: bf00 nop
+ }
+ }
+ return sysclockfreq;
+ 8001958: 68bb ldr r3, [r7, #8]
+}
+ 800195a: 4618 mov r0, r3
+ 800195c: 3714 adds r7, #20
+ 800195e: 46bd mov sp, r7
+ 8001960: bdf0 pop {r4, r5, r6, r7, pc}
+ 8001962: bf00 nop
+ 8001964: 40023800 .word 0x40023800
+ 8001968: 00f42400 .word 0x00f42400
+ 800196c: 017d7840 .word 0x017d7840
+
+08001970 <HAL_RCC_GetHCLKFreq>:
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
+ * @retval HCLK frequency
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ 8001970: b480 push {r7}
+ 8001972: af00 add r7, sp, #0
+ return SystemCoreClock;
+ 8001974: 4b03 ldr r3, [pc, #12] ; (8001984 <HAL_RCC_GetHCLKFreq+0x14>)
+ 8001976: 681b ldr r3, [r3, #0]
+}
+ 8001978: 4618 mov r0, r3
+ 800197a: 46bd mov sp, r7
+ 800197c: f85d 7b04 ldr.w r7, [sp], #4
+ 8001980: 4770 bx lr
+ 8001982: bf00 nop
+ 8001984: 20000000 .word 0x20000000
+
+08001988 <HAL_RCC_GetPCLK1Freq>:
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ 8001988: b580 push {r7, lr}
+ 800198a: af00 add r7, sp, #0
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
+ 800198c: f7ff fff0 bl 8001970 <HAL_RCC_GetHCLKFreq>
+ 8001990: 4601 mov r1, r0
+ 8001992: 4b05 ldr r3, [pc, #20] ; (80019a8 <HAL_RCC_GetPCLK1Freq+0x20>)
+ 8001994: 689b ldr r3, [r3, #8]
+ 8001996: 0a9b lsrs r3, r3, #10
+ 8001998: f003 0307 and.w r3, r3, #7
+ 800199c: 4a03 ldr r2, [pc, #12] ; (80019ac <HAL_RCC_GetPCLK1Freq+0x24>)
+ 800199e: 5cd3 ldrb r3, [r2, r3]
+ 80019a0: fa21 f303 lsr.w r3, r1, r3
+}
+ 80019a4: 4618 mov r0, r3
+ 80019a6: bd80 pop {r7, pc}
+ 80019a8: 40023800 .word 0x40023800
+ 80019ac: 08003970 .word 0x08003970
+
+080019b0 <HAL_RCC_GetPCLK2Freq>:
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ 80019b0: b580 push {r7, lr}
+ 80019b2: af00 add r7, sp, #0
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
+ 80019b4: f7ff ffdc bl 8001970 <HAL_RCC_GetHCLKFreq>
+ 80019b8: 4601 mov r1, r0
+ 80019ba: 4b05 ldr r3, [pc, #20] ; (80019d0 <HAL_RCC_GetPCLK2Freq+0x20>)
+ 80019bc: 689b ldr r3, [r3, #8]
+ 80019be: 0b5b lsrs r3, r3, #13
+ 80019c0: f003 0307 and.w r3, r3, #7
+ 80019c4: 4a03 ldr r2, [pc, #12] ; (80019d4 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 80019c6: 5cd3 ldrb r3, [r2, r3]
+ 80019c8: fa21 f303 lsr.w r3, r1, r3
+}
+ 80019cc: 4618 mov r0, r3
+ 80019ce: bd80 pop {r7, pc}
+ 80019d0: 40023800 .word 0x40023800
+ 80019d4: 08003970 .word 0x08003970
+
+080019d8 <HAL_RCCEx_PeriphCLKConfig>:
+ * the backup registers) are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ 80019d8: b580 push {r7, lr}
+ 80019da: b088 sub sp, #32
+ 80019dc: af00 add r7, sp, #0
+ 80019de: 6078 str r0, [r7, #4]
+ uint32_t tickstart = 0;
+ 80019e0: 2300 movs r3, #0
+ 80019e2: 617b str r3, [r7, #20]
+ uint32_t tmpreg0 = 0;
+ 80019e4: 2300 movs r3, #0
+ 80019e6: 613b str r3, [r7, #16]
+ uint32_t tmpreg1 = 0;
+ 80019e8: 2300 movs r3, #0
+ 80019ea: 60fb str r3, [r7, #12]
+ uint32_t plli2sused = 0;
+ 80019ec: 2300 movs r3, #0
+ 80019ee: 61fb str r3, [r7, #28]
+ uint32_t pllsaiused = 0;
+ 80019f0: 2300 movs r3, #0
+ 80019f2: 61bb str r3, [r7, #24]
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*----------------------------------- I2S configuration ----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ 80019f4: 687b ldr r3, [r7, #4]
+ 80019f6: 681b ldr r3, [r3, #0]
+ 80019f8: f003 0301 and.w r3, r3, #1
+ 80019fc: 2b00 cmp r3, #0
+ 80019fe: d012 beq.n 8001a26 <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+ /* Configure I2S Clock source */
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+ 8001a00: 4b69 ldr r3, [pc, #420] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a02: 689b ldr r3, [r3, #8]
+ 8001a04: 4a68 ldr r2, [pc, #416] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a06: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
+ 8001a0a: 6093 str r3, [r2, #8]
+ 8001a0c: 4b66 ldr r3, [pc, #408] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a0e: 689a ldr r2, [r3, #8]
+ 8001a10: 687b ldr r3, [r7, #4]
+ 8001a12: 6b5b ldr r3, [r3, #52] ; 0x34
+ 8001a14: 4964 ldr r1, [pc, #400] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a16: 4313 orrs r3, r2
+ 8001a18: 608b str r3, [r1, #8]
+
+ /* Enable the PLLI2S when it's used as clock source for I2S */
+ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
+ 8001a1a: 687b ldr r3, [r7, #4]
+ 8001a1c: 6b5b ldr r3, [r3, #52] ; 0x34
+ 8001a1e: 2b00 cmp r3, #0
+ 8001a20: d101 bne.n 8001a26 <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ {
+ plli2sused = 1;
+ 8001a22: 2301 movs r3, #1
+ 8001a24: 61fb str r3, [r7, #28]
+ }
+ }
+
+ /*------------------------------------ SAI1 configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+ 8001a26: 687b ldr r3, [r7, #4]
+ 8001a28: 681b ldr r3, [r3, #0]
+ 8001a2a: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 8001a2e: 2b00 cmp r3, #0
+ 8001a30: d017 beq.n 8001a62 <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+ /* Configure SAI1 Clock source */
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ 8001a32: 4b5d ldr r3, [pc, #372] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a34: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001a38: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
+ 8001a3c: 687b ldr r3, [r7, #4]
+ 8001a3e: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 8001a40: 4959 ldr r1, [pc, #356] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a42: 4313 orrs r3, r2
+ 8001a44: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+ 8001a48: 687b ldr r3, [r7, #4]
+ 8001a4a: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 8001a4c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 8001a50: d101 bne.n 8001a56 <HAL_RCCEx_PeriphCLKConfig+0x7e>
+ {
+ plli2sused = 1;
+ 8001a52: 2301 movs r3, #1
+ 8001a54: 61fb str r3, [r7, #28]
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+ 8001a56: 687b ldr r3, [r7, #4]
+ 8001a58: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 8001a5a: 2b00 cmp r3, #0
+ 8001a5c: d101 bne.n 8001a62 <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ {
+ pllsaiused = 1;
+ 8001a5e: 2301 movs r3, #1
+ 8001a60: 61bb str r3, [r7, #24]
+ }
+ }
+
+ /*------------------------------------ SAI2 configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+ 8001a62: 687b ldr r3, [r7, #4]
+ 8001a64: 681b ldr r3, [r3, #0]
+ 8001a66: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8001a6a: 2b00 cmp r3, #0
+ 8001a6c: d017 beq.n 8001a9e <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+ /* Configure SAI2 Clock source */
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+ 8001a6e: 4b4e ldr r3, [pc, #312] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a70: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001a74: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
+ 8001a78: 687b ldr r3, [r7, #4]
+ 8001a7a: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001a7c: 494a ldr r1, [pc, #296] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a7e: 4313 orrs r3, r2
+ 8001a80: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+
+ /* Enable the PLLI2S when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+ 8001a84: 687b ldr r3, [r7, #4]
+ 8001a86: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001a88: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8001a8c: d101 bne.n 8001a92 <HAL_RCCEx_PeriphCLKConfig+0xba>
+ {
+ plli2sused = 1;
+ 8001a8e: 2301 movs r3, #1
+ 8001a90: 61fb str r3, [r7, #28]
+ }
+ /* Enable the PLLSAI when it's used as clock source for SAI */
+ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+ 8001a92: 687b ldr r3, [r7, #4]
+ 8001a94: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001a96: 2b00 cmp r3, #0
+ 8001a98: d101 bne.n 8001a9e <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ {
+ pllsaiused = 1;
+ 8001a9a: 2301 movs r3, #1
+ 8001a9c: 61bb str r3, [r7, #24]
+ }
+ }
+
+ /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ 8001a9e: 687b ldr r3, [r7, #4]
+ 8001aa0: 681b ldr r3, [r3, #0]
+ 8001aa2: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
+ 8001aa6: 2b00 cmp r3, #0
+ 8001aa8: d001 beq.n 8001aae <HAL_RCCEx_PeriphCLKConfig+0xd6>
+ {
+ plli2sused = 1;
+ 8001aaa: 2301 movs r3, #1
+ 8001aac: 61fb str r3, [r7, #28]
+ }
+
+ /*------------------------------------ RTC configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ 8001aae: 687b ldr r3, [r7, #4]
+ 8001ab0: 681b ldr r3, [r3, #0]
+ 8001ab2: f003 0320 and.w r3, r3, #32
+ 8001ab6: 2b00 cmp r3, #0
+ 8001ab8: f000 808b beq.w 8001bd2 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ {
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8001abc: 4b3a ldr r3, [pc, #232] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001abe: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001ac0: 4a39 ldr r2, [pc, #228] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001ac2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8001ac6: 6413 str r3, [r2, #64] ; 0x40
+ 8001ac8: 4b37 ldr r3, [pc, #220] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001aca: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001acc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001ad0: 60bb str r3, [r7, #8]
+ 8001ad2: 68bb ldr r3, [r7, #8]
+
+ /* Enable write access to Backup domain */
+ PWR->CR1 |= PWR_CR1_DBP;
+ 8001ad4: 4b35 ldr r3, [pc, #212] ; (8001bac <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001ad6: 681b ldr r3, [r3, #0]
+ 8001ad8: 4a34 ldr r2, [pc, #208] ; (8001bac <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001ada: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 8001ade: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001ae0: f7ff f850 bl 8000b84 <HAL_GetTick>
+ 8001ae4: 6178 str r0, [r7, #20]
+
+ /* Wait for Backup domain Write protection disable */
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ 8001ae6: e008 b.n 8001afa <HAL_RCCEx_PeriphCLKConfig+0x122>
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 8001ae8: f7ff f84c bl 8000b84 <HAL_GetTick>
+ 8001aec: 4602 mov r2, r0
+ 8001aee: 697b ldr r3, [r7, #20]
+ 8001af0: 1ad3 subs r3, r2, r3
+ 8001af2: 2b64 cmp r3, #100 ; 0x64
+ 8001af4: d901 bls.n 8001afa <HAL_RCCEx_PeriphCLKConfig+0x122>
+ {
+ return HAL_TIMEOUT;
+ 8001af6: 2303 movs r3, #3
+ 8001af8: e38d b.n 8002216 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ 8001afa: 4b2c ldr r3, [pc, #176] ; (8001bac <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001afc: 681b ldr r3, [r3, #0]
+ 8001afe: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8001b02: 2b00 cmp r3, #0
+ 8001b04: d0f0 beq.n 8001ae8 <HAL_RCCEx_PeriphCLKConfig+0x110>
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ 8001b06: 4b28 ldr r3, [pc, #160] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b08: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001b0a: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8001b0e: 613b str r3, [r7, #16]
+
+ if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ 8001b10: 693b ldr r3, [r7, #16]
+ 8001b12: 2b00 cmp r3, #0
+ 8001b14: d035 beq.n 8001b82 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8001b16: 687b ldr r3, [r7, #4]
+ 8001b18: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001b1a: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8001b1e: 693a ldr r2, [r7, #16]
+ 8001b20: 429a cmp r2, r3
+ 8001b22: d02e beq.n 8001b82 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ 8001b24: 4b20 ldr r3, [pc, #128] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b26: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001b28: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8001b2c: 613b str r3, [r7, #16]
+
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ 8001b2e: 4b1e ldr r3, [pc, #120] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b30: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001b32: 4a1d ldr r2, [pc, #116] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b34: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8001b38: 6713 str r3, [r2, #112] ; 0x70
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ 8001b3a: 4b1b ldr r3, [pc, #108] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b3c: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001b3e: 4a1a ldr r2, [pc, #104] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b40: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8001b44: 6713 str r3, [r2, #112] ; 0x70
+
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = tmpreg0;
+ 8001b46: 4a18 ldr r2, [pc, #96] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b48: 693b ldr r3, [r7, #16]
+ 8001b4a: 6713 str r3, [r2, #112] ; 0x70
+
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+ 8001b4c: 4b16 ldr r3, [pc, #88] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b4e: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001b50: f003 0301 and.w r3, r3, #1
+ 8001b54: 2b01 cmp r3, #1
+ 8001b56: d114 bne.n 8001b82 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001b58: f7ff f814 bl 8000b84 <HAL_GetTick>
+ 8001b5c: 6178 str r0, [r7, #20]
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 8001b5e: e00a b.n 8001b76 <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 8001b60: f7ff f810 bl 8000b84 <HAL_GetTick>
+ 8001b64: 4602 mov r2, r0
+ 8001b66: 697b ldr r3, [r7, #20]
+ 8001b68: 1ad3 subs r3, r2, r3
+ 8001b6a: f241 3288 movw r2, #5000 ; 0x1388
+ 8001b6e: 4293 cmp r3, r2
+ 8001b70: d901 bls.n 8001b76 <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ {
+ return HAL_TIMEOUT;
+ 8001b72: 2303 movs r3, #3
+ 8001b74: e34f b.n 8002216 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 8001b76: 4b0c ldr r3, [pc, #48] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b78: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001b7a: f003 0302 and.w r3, r3, #2
+ 8001b7e: 2b00 cmp r3, #0
+ 8001b80: d0ee beq.n 8001b60 <HAL_RCCEx_PeriphCLKConfig+0x188>
+ }
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ 8001b82: 687b ldr r3, [r7, #4]
+ 8001b84: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001b86: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8001b8a: f5b3 7f40 cmp.w r3, #768 ; 0x300
+ 8001b8e: d111 bne.n 8001bb4 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
+ 8001b90: 4b05 ldr r3, [pc, #20] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001b92: 689b ldr r3, [r3, #8]
+ 8001b94: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
+ 8001b98: 687b ldr r3, [r7, #4]
+ 8001b9a: 6b19 ldr r1, [r3, #48] ; 0x30
+ 8001b9c: 4b04 ldr r3, [pc, #16] ; (8001bb0 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
+ 8001b9e: 400b ands r3, r1
+ 8001ba0: 4901 ldr r1, [pc, #4] ; (8001ba8 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001ba2: 4313 orrs r3, r2
+ 8001ba4: 608b str r3, [r1, #8]
+ 8001ba6: e00b b.n 8001bc0 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
+ 8001ba8: 40023800 .word 0x40023800
+ 8001bac: 40007000 .word 0x40007000
+ 8001bb0: 0ffffcff .word 0x0ffffcff
+ 8001bb4: 4bb3 ldr r3, [pc, #716] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bb6: 689b ldr r3, [r3, #8]
+ 8001bb8: 4ab2 ldr r2, [pc, #712] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bba: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
+ 8001bbe: 6093 str r3, [r2, #8]
+ 8001bc0: 4bb0 ldr r3, [pc, #704] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bc2: 6f1a ldr r2, [r3, #112] ; 0x70
+ 8001bc4: 687b ldr r3, [r7, #4]
+ 8001bc6: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001bc8: f3c3 030b ubfx r3, r3, #0, #12
+ 8001bcc: 49ad ldr r1, [pc, #692] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bce: 4313 orrs r3, r2
+ 8001bd0: 670b str r3, [r1, #112] ; 0x70
+ }
+
+ /*------------------------------------ TIM configuration --------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+ 8001bd2: 687b ldr r3, [r7, #4]
+ 8001bd4: 681b ldr r3, [r3, #0]
+ 8001bd6: f003 0310 and.w r3, r3, #16
+ 8001bda: 2b00 cmp r3, #0
+ 8001bdc: d010 beq.n 8001c00 <HAL_RCCEx_PeriphCLKConfig+0x228>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+ /* Configure Timer Prescaler */
+ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ 8001bde: 4ba9 ldr r3, [pc, #676] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001be0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001be4: 4aa7 ldr r2, [pc, #668] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001be6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8001bea: f8c2 308c str.w r3, [r2, #140] ; 0x8c
+ 8001bee: 4ba5 ldr r3, [pc, #660] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bf0: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
+ 8001bf4: 687b ldr r3, [r7, #4]
+ 8001bf6: 6b9b ldr r3, [r3, #56] ; 0x38
+ 8001bf8: 49a2 ldr r1, [pc, #648] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bfa: 4313 orrs r3, r2
+ 8001bfc: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ }
+
+ /*-------------------------------------- I2C1 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ 8001c00: 687b ldr r3, [r7, #4]
+ 8001c02: 681b ldr r3, [r3, #0]
+ 8001c04: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8001c08: 2b00 cmp r3, #0
+ 8001c0a: d00a beq.n 8001c22 <HAL_RCCEx_PeriphCLKConfig+0x24a>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+ /* Configure the I2C1 clock source */
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ 8001c0c: 4b9d ldr r3, [pc, #628] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c0e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c12: f423 3240 bic.w r2, r3, #196608 ; 0x30000
+ 8001c16: 687b ldr r3, [r7, #4]
+ 8001c18: 6e5b ldr r3, [r3, #100] ; 0x64
+ 8001c1a: 499a ldr r1, [pc, #616] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c1c: 4313 orrs r3, r2
+ 8001c1e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- I2C2 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+ 8001c22: 687b ldr r3, [r7, #4]
+ 8001c24: 681b ldr r3, [r3, #0]
+ 8001c26: f403 4300 and.w r3, r3, #32768 ; 0x8000
+ 8001c2a: 2b00 cmp r3, #0
+ 8001c2c: d00a beq.n 8001c44 <HAL_RCCEx_PeriphCLKConfig+0x26c>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+ /* Configure the I2C2 clock source */
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+ 8001c2e: 4b95 ldr r3, [pc, #596] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c30: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c34: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
+ 8001c38: 687b ldr r3, [r7, #4]
+ 8001c3a: 6e9b ldr r3, [r3, #104] ; 0x68
+ 8001c3c: 4991 ldr r1, [pc, #580] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c3e: 4313 orrs r3, r2
+ 8001c40: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- I2C3 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+ 8001c44: 687b ldr r3, [r7, #4]
+ 8001c46: 681b ldr r3, [r3, #0]
+ 8001c48: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8001c4c: 2b00 cmp r3, #0
+ 8001c4e: d00a beq.n 8001c66 <HAL_RCCEx_PeriphCLKConfig+0x28e>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+ /* Configure the I2C3 clock source */
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+ 8001c50: 4b8c ldr r3, [pc, #560] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c52: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c56: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
+ 8001c5a: 687b ldr r3, [r7, #4]
+ 8001c5c: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8001c5e: 4989 ldr r1, [pc, #548] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c60: 4313 orrs r3, r2
+ 8001c62: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- I2C4 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+ 8001c66: 687b ldr r3, [r7, #4]
+ 8001c68: 681b ldr r3, [r3, #0]
+ 8001c6a: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8001c6e: 2b00 cmp r3, #0
+ 8001c70: d00a beq.n 8001c88 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+ /* Configure the I2C4 clock source */
+ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+ 8001c72: 4b84 ldr r3, [pc, #528] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c74: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c78: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
+ 8001c7c: 687b ldr r3, [r7, #4]
+ 8001c7e: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001c80: 4980 ldr r1, [pc, #512] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c82: 4313 orrs r3, r2
+ 8001c84: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- USART1 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ 8001c88: 687b ldr r3, [r7, #4]
+ 8001c8a: 681b ldr r3, [r3, #0]
+ 8001c8c: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8001c90: 2b00 cmp r3, #0
+ 8001c92: d00a beq.n 8001caa <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+ /* Configure the USART1 clock source */
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ 8001c94: 4b7b ldr r3, [pc, #492] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c96: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c9a: f023 0203 bic.w r2, r3, #3
+ 8001c9e: 687b ldr r3, [r7, #4]
+ 8001ca0: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001ca2: 4978 ldr r1, [pc, #480] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001ca4: 4313 orrs r3, r2
+ 8001ca6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- USART2 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ 8001caa: 687b ldr r3, [r7, #4]
+ 8001cac: 681b ldr r3, [r3, #0]
+ 8001cae: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8001cb2: 2b00 cmp r3, #0
+ 8001cb4: d00a beq.n 8001ccc <HAL_RCCEx_PeriphCLKConfig+0x2f4>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+ /* Configure the USART2 clock source */
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ 8001cb6: 4b73 ldr r3, [pc, #460] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cb8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001cbc: f023 020c bic.w r2, r3, #12
+ 8001cc0: 687b ldr r3, [r7, #4]
+ 8001cc2: 6c9b ldr r3, [r3, #72] ; 0x48
+ 8001cc4: 496f ldr r1, [pc, #444] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cc6: 4313 orrs r3, r2
+ 8001cc8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- USART3 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+ 8001ccc: 687b ldr r3, [r7, #4]
+ 8001cce: 681b ldr r3, [r3, #0]
+ 8001cd0: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8001cd4: 2b00 cmp r3, #0
+ 8001cd6: d00a beq.n 8001cee <HAL_RCCEx_PeriphCLKConfig+0x316>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+ /* Configure the USART3 clock source */
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+ 8001cd8: 4b6a ldr r3, [pc, #424] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cda: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001cde: f023 0230 bic.w r2, r3, #48 ; 0x30
+ 8001ce2: 687b ldr r3, [r7, #4]
+ 8001ce4: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 8001ce6: 4967 ldr r1, [pc, #412] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001ce8: 4313 orrs r3, r2
+ 8001cea: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- UART4 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+ 8001cee: 687b ldr r3, [r7, #4]
+ 8001cf0: 681b ldr r3, [r3, #0]
+ 8001cf2: f403 7300 and.w r3, r3, #512 ; 0x200
+ 8001cf6: 2b00 cmp r3, #0
+ 8001cf8: d00a beq.n 8001d10 <HAL_RCCEx_PeriphCLKConfig+0x338>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+ /* Configure the UART4 clock source */
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+ 8001cfa: 4b62 ldr r3, [pc, #392] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cfc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001d00: f023 02c0 bic.w r2, r3, #192 ; 0xc0
+ 8001d04: 687b ldr r3, [r7, #4]
+ 8001d06: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8001d08: 495e ldr r1, [pc, #376] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d0a: 4313 orrs r3, r2
+ 8001d0c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- UART5 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+ 8001d10: 687b ldr r3, [r7, #4]
+ 8001d12: 681b ldr r3, [r3, #0]
+ 8001d14: f403 6380 and.w r3, r3, #1024 ; 0x400
+ 8001d18: 2b00 cmp r3, #0
+ 8001d1a: d00a beq.n 8001d32 <HAL_RCCEx_PeriphCLKConfig+0x35a>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+ /* Configure the UART5 clock source */
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+ 8001d1c: 4b59 ldr r3, [pc, #356] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d1e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001d22: f423 7240 bic.w r2, r3, #768 ; 0x300
+ 8001d26: 687b ldr r3, [r7, #4]
+ 8001d28: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8001d2a: 4956 ldr r1, [pc, #344] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d2c: 4313 orrs r3, r2
+ 8001d2e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- USART6 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
+ 8001d32: 687b ldr r3, [r7, #4]
+ 8001d34: 681b ldr r3, [r3, #0]
+ 8001d36: f403 6300 and.w r3, r3, #2048 ; 0x800
+ 8001d3a: 2b00 cmp r3, #0
+ 8001d3c: d00a beq.n 8001d54 <HAL_RCCEx_PeriphCLKConfig+0x37c>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
+
+ /* Configure the USART6 clock source */
+ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
+ 8001d3e: 4b51 ldr r3, [pc, #324] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d40: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001d44: f423 6240 bic.w r2, r3, #3072 ; 0xc00
+ 8001d48: 687b ldr r3, [r7, #4]
+ 8001d4a: 6d9b ldr r3, [r3, #88] ; 0x58
+ 8001d4c: 494d ldr r1, [pc, #308] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d4e: 4313 orrs r3, r2
+ 8001d50: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- UART7 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
+ 8001d54: 687b ldr r3, [r7, #4]
+ 8001d56: 681b ldr r3, [r3, #0]
+ 8001d58: f403 5380 and.w r3, r3, #4096 ; 0x1000
+ 8001d5c: 2b00 cmp r3, #0
+ 8001d5e: d00a beq.n 8001d76 <HAL_RCCEx_PeriphCLKConfig+0x39e>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
+
+ /* Configure the UART7 clock source */
+ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
+ 8001d60: 4b48 ldr r3, [pc, #288] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d62: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001d66: f423 5240 bic.w r2, r3, #12288 ; 0x3000
+ 8001d6a: 687b ldr r3, [r7, #4]
+ 8001d6c: 6ddb ldr r3, [r3, #92] ; 0x5c
+ 8001d6e: 4945 ldr r1, [pc, #276] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d70: 4313 orrs r3, r2
+ 8001d72: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- UART8 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
+ 8001d76: 687b ldr r3, [r7, #4]
+ 8001d78: 681b ldr r3, [r3, #0]
+ 8001d7a: f403 5300 and.w r3, r3, #8192 ; 0x2000
+ 8001d7e: 2b00 cmp r3, #0
+ 8001d80: d00a beq.n 8001d98 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
+
+ /* Configure the UART8 clock source */
+ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
+ 8001d82: 4b40 ldr r3, [pc, #256] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001d88: f423 4240 bic.w r2, r3, #49152 ; 0xc000
+ 8001d8c: 687b ldr r3, [r7, #4]
+ 8001d8e: 6e1b ldr r3, [r3, #96] ; 0x60
+ 8001d90: 493c ldr r1, [pc, #240] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001d92: 4313 orrs r3, r2
+ 8001d94: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*--------------------------------------- CEC Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ 8001d98: 687b ldr r3, [r7, #4]
+ 8001d9a: 681b ldr r3, [r3, #0]
+ 8001d9c: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8001da0: 2b00 cmp r3, #0
+ 8001da2: d00a beq.n 8001dba <HAL_RCCEx_PeriphCLKConfig+0x3e2>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ 8001da4: 4b37 ldr r3, [pc, #220] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001da6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001daa: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
+ 8001dae: 687b ldr r3, [r7, #4]
+ 8001db0: 6f9b ldr r3, [r3, #120] ; 0x78
+ 8001db2: 4934 ldr r1, [pc, #208] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001db4: 4313 orrs r3, r2
+ 8001db6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*-------------------------------------- CK48 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+ 8001dba: 687b ldr r3, [r7, #4]
+ 8001dbc: 681b ldr r3, [r3, #0]
+ 8001dbe: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8001dc2: 2b00 cmp r3, #0
+ 8001dc4: d011 beq.n 8001dea <HAL_RCCEx_PeriphCLKConfig+0x412>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
+
+ /* Configure the CLK48 source */
+ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+ 8001dc6: 4b2f ldr r3, [pc, #188] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001dc8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001dcc: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
+ 8001dd0: 687b ldr r3, [r7, #4]
+ 8001dd2: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8001dd4: 492b ldr r1, [pc, #172] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001dd6: 4313 orrs r3, r2
+ 8001dd8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+
+ /* Enable the PLLSAI when it's used as clock source for CK48 */
+ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
+ 8001ddc: 687b ldr r3, [r7, #4]
+ 8001dde: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8001de0: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
+ 8001de4: d101 bne.n 8001dea <HAL_RCCEx_PeriphCLKConfig+0x412>
+ {
+ pllsaiused = 1;
+ 8001de6: 2301 movs r3, #1
+ 8001de8: 61bb str r3, [r7, #24]
+ }
+ }
+
+ /*-------------------------------------- LTDC Configuration -----------------------------------*/
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+ 8001dea: 687b ldr r3, [r7, #4]
+ 8001dec: 681b ldr r3, [r3, #0]
+ 8001dee: f003 0308 and.w r3, r3, #8
+ 8001df2: 2b00 cmp r3, #0
+ 8001df4: d001 beq.n 8001dfa <HAL_RCCEx_PeriphCLKConfig+0x422>
+ {
+ pllsaiused = 1;
+ 8001df6: 2301 movs r3, #1
+ 8001df8: 61bb str r3, [r7, #24]
+ }
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ 8001dfa: 687b ldr r3, [r7, #4]
+ 8001dfc: 681b ldr r3, [r3, #0]
+ 8001dfe: f403 2380 and.w r3, r3, #262144 ; 0x40000
+ 8001e02: 2b00 cmp r3, #0
+ 8001e04: d00a beq.n 8001e1c <HAL_RCCEx_PeriphCLKConfig+0x444>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
+
+ /* Configure the LTPIM1 clock source */
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ 8001e06: 4b1f ldr r3, [pc, #124] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e08: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001e0c: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
+ 8001e10: 687b ldr r3, [r7, #4]
+ 8001e12: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8001e14: 491b ldr r1, [pc, #108] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e16: 4313 orrs r3, r2
+ 8001e18: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
+ 8001e1c: 687b ldr r3, [r7, #4]
+ 8001e1e: 681b ldr r3, [r3, #0]
+ 8001e20: f403 0300 and.w r3, r3, #8388608 ; 0x800000
+ 8001e24: 2b00 cmp r3, #0
+ 8001e26: d00b beq.n 8001e40 <HAL_RCCEx_PeriphCLKConfig+0x468>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
+
+ /* Configure the SDMMC1 clock source */
+ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
+ 8001e28: 4b16 ldr r3, [pc, #88] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e2a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001e2e: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
+ 8001e32: 687b ldr r3, [r7, #4]
+ 8001e34: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
+ 8001e38: 4912 ldr r1, [pc, #72] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e3a: 4313 orrs r3, r2
+ 8001e3c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+ /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
+ 8001e40: 687b ldr r3, [r7, #4]
+ 8001e42: 681b ldr r3, [r3, #0]
+ 8001e44: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
+ 8001e48: 2b00 cmp r3, #0
+ 8001e4a: d00b beq.n 8001e64 <HAL_RCCEx_PeriphCLKConfig+0x48c>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
+
+ /* Configure the SDMMC2 clock source */
+ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
+ 8001e4c: 4b0d ldr r3, [pc, #52] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e4e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001e52: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
+ 8001e56: 687b ldr r3, [r7, #4]
+ 8001e58: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001e5c: 4909 ldr r1, [pc, #36] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e5e: 4313 orrs r3, r2
+ 8001e60: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ }
+
+ /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+ 8001e64: 687b ldr r3, [r7, #4]
+ 8001e66: 681b ldr r3, [r3, #0]
+ 8001e68: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8001e6c: 2b00 cmp r3, #0
+ 8001e6e: d00f beq.n 8001e90 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+ /* Configure the DFSDM1 interface clock source */
+ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+ 8001e70: 4b04 ldr r3, [pc, #16] ; (8001e84 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001e72: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001e76: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
+ 8001e7a: 687b ldr r3, [r7, #4]
+ 8001e7c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001e80: e002 b.n 8001e88 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
+ 8001e82: bf00 nop
+ 8001e84: 40023800 .word 0x40023800
+ 8001e88: 4985 ldr r1, [pc, #532] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e8a: 4313 orrs r3, r2
+ 8001e8c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ }
+
+ /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
+ 8001e90: 687b ldr r3, [r7, #4]
+ 8001e92: 681b ldr r3, [r3, #0]
+ 8001e94: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001e98: 2b00 cmp r3, #0
+ 8001e9a: d00b beq.n 8001eb4 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+
+ /* Configure the DFSDM interface clock source */
+ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+ 8001e9c: 4b80 ldr r3, [pc, #512] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e9e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001ea2: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
+ 8001ea6: 687b ldr r3, [r7, #4]
+ 8001ea8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001eac: 497c ldr r1, [pc, #496] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001eae: 4313 orrs r3, r2
+ 8001eb0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ }
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
+ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
+ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
+ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+ 8001eb4: 69fb ldr r3, [r7, #28]
+ 8001eb6: 2b01 cmp r3, #1
+ 8001eb8: d005 beq.n 8001ec6 <HAL_RCCEx_PeriphCLKConfig+0x4ee>
+ 8001eba: 687b ldr r3, [r7, #4]
+ 8001ebc: 681b ldr r3, [r3, #0]
+ 8001ebe: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
+ 8001ec2: f040 80d6 bne.w 8002072 <HAL_RCCEx_PeriphCLKConfig+0x69a>
+ {
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+ 8001ec6: 4b76 ldr r3, [pc, #472] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001ec8: 681b ldr r3, [r3, #0]
+ 8001eca: 4a75 ldr r2, [pc, #468] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001ecc: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
+ 8001ed0: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8001ed2: f7fe fe57 bl 8000b84 <HAL_GetTick>
+ 8001ed6: 6178 str r0, [r7, #20]
+
+ /* Wait till PLLI2S is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ 8001ed8: e008 b.n 8001eec <HAL_RCCEx_PeriphCLKConfig+0x514>
+ {
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ 8001eda: f7fe fe53 bl 8000b84 <HAL_GetTick>
+ 8001ede: 4602 mov r2, r0
+ 8001ee0: 697b ldr r3, [r7, #20]
+ 8001ee2: 1ad3 subs r3, r2, r3
+ 8001ee4: 2b64 cmp r3, #100 ; 0x64
+ 8001ee6: d901 bls.n 8001eec <HAL_RCCEx_PeriphCLKConfig+0x514>
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ 8001ee8: 2303 movs r3, #3
+ 8001eea: e194 b.n 8002216 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ 8001eec: 4b6c ldr r3, [pc, #432] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001eee: 681b ldr r3, [r3, #0]
+ 8001ef0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8001ef4: 2b00 cmp r3, #0
+ 8001ef6: d1f0 bne.n 8001eda <HAL_RCCEx_PeriphCLKConfig+0x502>
+
+ /* check for common PLLI2S Parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+ /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
+ 8001ef8: 687b ldr r3, [r7, #4]
+ 8001efa: 681b ldr r3, [r3, #0]
+ 8001efc: f003 0301 and.w r3, r3, #1
+ 8001f00: 2b00 cmp r3, #0
+ 8001f02: d021 beq.n 8001f48 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ 8001f04: 687b ldr r3, [r7, #4]
+ 8001f06: 6b5b ldr r3, [r3, #52] ; 0x34
+ 8001f08: 2b00 cmp r3, #0
+ 8001f0a: d11d bne.n 8001f48 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+ /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+ 8001f0c: 4b64 ldr r3, [pc, #400] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f0e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001f12: 0c1b lsrs r3, r3, #16
+ 8001f14: f003 0303 and.w r3, r3, #3
+ 8001f18: 613b str r3, [r7, #16]
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ 8001f1a: 4b61 ldr r3, [pc, #388] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f1c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001f20: 0e1b lsrs r3, r3, #24
+ 8001f22: f003 030f and.w r3, r3, #15
+ 8001f26: 60fb str r3, [r7, #12]
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
+ 8001f28: 687b ldr r3, [r7, #4]
+ 8001f2a: 685b ldr r3, [r3, #4]
+ 8001f2c: 019a lsls r2, r3, #6
+ 8001f2e: 693b ldr r3, [r7, #16]
+ 8001f30: 041b lsls r3, r3, #16
+ 8001f32: 431a orrs r2, r3
+ 8001f34: 68fb ldr r3, [r7, #12]
+ 8001f36: 061b lsls r3, r3, #24
+ 8001f38: 431a orrs r2, r3
+ 8001f3a: 687b ldr r3, [r7, #4]
+ 8001f3c: 689b ldr r3, [r3, #8]
+ 8001f3e: 071b lsls r3, r3, #28
+ 8001f40: 4957 ldr r1, [pc, #348] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f42: 4313 orrs r3, r2
+ 8001f44: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ }
+
+ /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+ 8001f48: 687b ldr r3, [r7, #4]
+ 8001f4a: 681b ldr r3, [r3, #0]
+ 8001f4c: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 8001f50: 2b00 cmp r3, #0
+ 8001f52: d004 beq.n 8001f5e <HAL_RCCEx_PeriphCLKConfig+0x586>
+ 8001f54: 687b ldr r3, [r7, #4]
+ 8001f56: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 8001f58: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 8001f5c: d00a beq.n 8001f74 <HAL_RCCEx_PeriphCLKConfig+0x59c>
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+ 8001f5e: 687b ldr r3, [r7, #4]
+ 8001f60: 681b ldr r3, [r3, #0]
+ 8001f62: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+ 8001f66: 2b00 cmp r3, #0
+ 8001f68: d02e beq.n 8001fc8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+ 8001f6a: 687b ldr r3, [r7, #4]
+ 8001f6c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001f6e: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8001f72: d129 bne.n 8001fc8 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ /* Check for PLLI2S/DIVQ parameters */
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+ /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+ 8001f74: 4b4a ldr r3, [pc, #296] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f76: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001f7a: 0c1b lsrs r3, r3, #16
+ 8001f7c: f003 0303 and.w r3, r3, #3
+ 8001f80: 613b str r3, [r7, #16]
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ 8001f82: 4b47 ldr r3, [pc, #284] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001f84: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001f88: 0f1b lsrs r3, r3, #28
+ 8001f8a: f003 0307 and.w r3, r3, #7
+ 8001f8e: 60fb str r3, [r7, #12]
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
+ 8001f90: 687b ldr r3, [r7, #4]
+ 8001f92: 685b ldr r3, [r3, #4]
+ 8001f94: 019a lsls r2, r3, #6
+ 8001f96: 693b ldr r3, [r7, #16]
+ 8001f98: 041b lsls r3, r3, #16
+ 8001f9a: 431a orrs r2, r3
+ 8001f9c: 687b ldr r3, [r7, #4]
+ 8001f9e: 68db ldr r3, [r3, #12]
+ 8001fa0: 061b lsls r3, r3, #24
+ 8001fa2: 431a orrs r2, r3
+ 8001fa4: 68fb ldr r3, [r7, #12]
+ 8001fa6: 071b lsls r3, r3, #28
+ 8001fa8: 493d ldr r1, [pc, #244] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001faa: 4313 orrs r3, r2
+ 8001fac: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ 8001fb0: 4b3b ldr r3, [pc, #236] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001fb2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001fb6: f023 021f bic.w r2, r3, #31
+ 8001fba: 687b ldr r3, [r7, #4]
+ 8001fbc: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001fbe: 3b01 subs r3, #1
+ 8001fc0: 4937 ldr r1, [pc, #220] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001fc2: 4313 orrs r3, r2
+ 8001fc4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ }
+
+ /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ 8001fc8: 687b ldr r3, [r7, #4]
+ 8001fca: 681b ldr r3, [r3, #0]
+ 8001fcc: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
+ 8001fd0: 2b00 cmp r3, #0
+ 8001fd2: d01d beq.n 8002010 <HAL_RCCEx_PeriphCLKConfig+0x638>
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+
+ /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ 8001fd4: 4b32 ldr r3, [pc, #200] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001fd6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001fda: 0e1b lsrs r3, r3, #24
+ 8001fdc: f003 030f and.w r3, r3, #15
+ 8001fe0: 613b str r3, [r7, #16]
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ 8001fe2: 4b2f ldr r3, [pc, #188] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001fe4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001fe8: 0f1b lsrs r3, r3, #28
+ 8001fea: f003 0307 and.w r3, r3, #7
+ 8001fee: 60fb str r3, [r7, #12]
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
+ 8001ff0: 687b ldr r3, [r7, #4]
+ 8001ff2: 685b ldr r3, [r3, #4]
+ 8001ff4: 019a lsls r2, r3, #6
+ 8001ff6: 687b ldr r3, [r7, #4]
+ 8001ff8: 691b ldr r3, [r3, #16]
+ 8001ffa: 041b lsls r3, r3, #16
+ 8001ffc: 431a orrs r2, r3
+ 8001ffe: 693b ldr r3, [r7, #16]
+ 8002000: 061b lsls r3, r3, #24
+ 8002002: 431a orrs r2, r3
+ 8002004: 68fb ldr r3, [r7, #12]
+ 8002006: 071b lsls r3, r3, #28
+ 8002008: 4925 ldr r1, [pc, #148] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 800200a: 4313 orrs r3, r2
+ 800200c: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ }
+
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ 8002010: 687b ldr r3, [r7, #4]
+ 8002012: 681b ldr r3, [r3, #0]
+ 8002014: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8002018: 2b00 cmp r3, #0
+ 800201a: d011 beq.n 8002040 <HAL_RCCEx_PeriphCLKConfig+0x668>
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+ /* Configure the PLLI2S division factors */
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
+ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ 800201c: 687b ldr r3, [r7, #4]
+ 800201e: 685b ldr r3, [r3, #4]
+ 8002020: 019a lsls r2, r3, #6
+ 8002022: 687b ldr r3, [r7, #4]
+ 8002024: 691b ldr r3, [r3, #16]
+ 8002026: 041b lsls r3, r3, #16
+ 8002028: 431a orrs r2, r3
+ 800202a: 687b ldr r3, [r7, #4]
+ 800202c: 68db ldr r3, [r3, #12]
+ 800202e: 061b lsls r3, r3, #24
+ 8002030: 431a orrs r2, r3
+ 8002032: 687b ldr r3, [r7, #4]
+ 8002034: 689b ldr r3, [r3, #8]
+ 8002036: 071b lsls r3, r3, #28
+ 8002038: 4919 ldr r1, [pc, #100] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 800203a: 4313 orrs r3, r2
+ 800203c: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ }
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+ 8002040: 4b17 ldr r3, [pc, #92] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002042: 681b ldr r3, [r3, #0]
+ 8002044: 4a16 ldr r2, [pc, #88] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002046: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
+ 800204a: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 800204c: f7fe fd9a bl 8000b84 <HAL_GetTick>
+ 8002050: 6178 str r0, [r7, #20]
+
+ /* Wait till PLLI2S is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ 8002052: e008 b.n 8002066 <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ {
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ 8002054: f7fe fd96 bl 8000b84 <HAL_GetTick>
+ 8002058: 4602 mov r2, r0
+ 800205a: 697b ldr r3, [r7, #20]
+ 800205c: 1ad3 subs r3, r2, r3
+ 800205e: 2b64 cmp r3, #100 ; 0x64
+ 8002060: d901 bls.n 8002066 <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ 8002062: 2303 movs r3, #3
+ 8002064: e0d7 b.n 8002216 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ 8002066: 4b0e ldr r3, [pc, #56] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002068: 681b ldr r3, [r3, #0]
+ 800206a: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 800206e: 2b00 cmp r3, #0
+ 8002070: d0f0 beq.n 8002054 <HAL_RCCEx_PeriphCLKConfig+0x67c>
+ }
+ }
+
+ /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
+ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
+ if(pllsaiused == 1)
+ 8002072: 69bb ldr r3, [r7, #24]
+ 8002074: 2b01 cmp r3, #1
+ 8002076: f040 80cd bne.w 8002214 <HAL_RCCEx_PeriphCLKConfig+0x83c>
+ {
+ /* Disable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_DISABLE();
+ 800207a: 4b09 ldr r3, [pc, #36] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 800207c: 681b ldr r3, [r3, #0]
+ 800207e: 4a08 ldr r2, [pc, #32] ; (80020a0 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8002080: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 8002084: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 8002086: f7fe fd7d bl 8000b84 <HAL_GetTick>
+ 800208a: 6178 str r0, [r7, #20]
+
+ /* Wait till PLLSAI is disabled */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ 800208c: e00a b.n 80020a4 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ {
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ 800208e: f7fe fd79 bl 8000b84 <HAL_GetTick>
+ 8002092: 4602 mov r2, r0
+ 8002094: 697b ldr r3, [r7, #20]
+ 8002096: 1ad3 subs r3, r2, r3
+ 8002098: 2b64 cmp r3, #100 ; 0x64
+ 800209a: d903 bls.n 80020a4 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ 800209c: 2303 movs r3, #3
+ 800209e: e0ba b.n 8002216 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 80020a0: 40023800 .word 0x40023800
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ 80020a4: 4b5e ldr r3, [pc, #376] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80020a6: 681b ldr r3, [r3, #0]
+ 80020a8: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
+ 80020ac: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
+ 80020b0: d0ed beq.n 800208e <HAL_RCCEx_PeriphCLKConfig+0x6b6>
+
+ /* Check the PLLSAI division factors */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+ /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
+ 80020b2: 687b ldr r3, [r7, #4]
+ 80020b4: 681b ldr r3, [r3, #0]
+ 80020b6: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 80020ba: 2b00 cmp r3, #0
+ 80020bc: d003 beq.n 80020c6 <HAL_RCCEx_PeriphCLKConfig+0x6ee>
+ 80020be: 687b ldr r3, [r7, #4]
+ 80020c0: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 80020c2: 2b00 cmp r3, #0
+ 80020c4: d009 beq.n 80020da <HAL_RCCEx_PeriphCLKConfig+0x702>
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+ 80020c6: 687b ldr r3, [r7, #4]
+ 80020c8: 681b ldr r3, [r3, #0]
+ 80020ca: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
+ 80020ce: 2b00 cmp r3, #0
+ 80020d0: d02e beq.n 8002130 <HAL_RCCEx_PeriphCLKConfig+0x758>
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+ 80020d2: 687b ldr r3, [r7, #4]
+ 80020d4: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80020d6: 2b00 cmp r3, #0
+ 80020d8: d12a bne.n 8002130 <HAL_RCCEx_PeriphCLKConfig+0x758>
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+ /* check for PLLSAI/DIVQ Parameter */
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+ /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ 80020da: 4b51 ldr r3, [pc, #324] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80020dc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 80020e0: 0c1b lsrs r3, r3, #16
+ 80020e2: f003 0303 and.w r3, r3, #3
+ 80020e6: 613b str r3, [r7, #16]
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 80020e8: 4b4d ldr r3, [pc, #308] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80020ea: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 80020ee: 0f1b lsrs r3, r3, #28
+ 80020f0: f003 0307 and.w r3, r3, #7
+ 80020f4: 60fb str r3, [r7, #12]
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
+ 80020f6: 687b ldr r3, [r7, #4]
+ 80020f8: 695b ldr r3, [r3, #20]
+ 80020fa: 019a lsls r2, r3, #6
+ 80020fc: 693b ldr r3, [r7, #16]
+ 80020fe: 041b lsls r3, r3, #16
+ 8002100: 431a orrs r2, r3
+ 8002102: 687b ldr r3, [r7, #4]
+ 8002104: 699b ldr r3, [r3, #24]
+ 8002106: 061b lsls r3, r3, #24
+ 8002108: 431a orrs r2, r3
+ 800210a: 68fb ldr r3, [r7, #12]
+ 800210c: 071b lsls r3, r3, #28
+ 800210e: 4944 ldr r1, [pc, #272] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002110: 4313 orrs r3, r2
+ 8002112: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+ 8002116: 4b42 ldr r3, [pc, #264] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002118: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 800211c: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
+ 8002120: 687b ldr r3, [r7, #4]
+ 8002122: 6a9b ldr r3, [r3, #40] ; 0x28
+ 8002124: 3b01 subs r3, #1
+ 8002126: 021b lsls r3, r3, #8
+ 8002128: 493d ldr r1, [pc, #244] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800212a: 4313 orrs r3, r2
+ 800212c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ }
+
+ /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
+ /* In Case of PLLI2S is selected as source clock for CK48 */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
+ 8002130: 687b ldr r3, [r7, #4]
+ 8002132: 681b ldr r3, [r3, #0]
+ 8002134: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8002138: 2b00 cmp r3, #0
+ 800213a: d022 beq.n 8002182 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ 800213c: 687b ldr r3, [r7, #4]
+ 800213e: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002140: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
+ 8002144: d11d bne.n 8002182 <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ {
+ /* check for Parameters */
+ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+ /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ 8002146: 4b36 ldr r3, [pc, #216] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002148: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 800214c: 0e1b lsrs r3, r3, #24
+ 800214e: f003 030f and.w r3, r3, #15
+ 8002152: 613b str r3, [r7, #16]
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ 8002154: 4b32 ldr r3, [pc, #200] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002156: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 800215a: 0f1b lsrs r3, r3, #28
+ 800215c: f003 0307 and.w r3, r3, #7
+ 8002160: 60fb str r3, [r7, #12]
+
+ /* Configure the PLLSAI division factors */
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
+ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
+ 8002162: 687b ldr r3, [r7, #4]
+ 8002164: 695b ldr r3, [r3, #20]
+ 8002166: 019a lsls r2, r3, #6
+ 8002168: 687b ldr r3, [r7, #4]
+ 800216a: 6a1b ldr r3, [r3, #32]
+ 800216c: 041b lsls r3, r3, #16
+ 800216e: 431a orrs r2, r3
+ 8002170: 693b ldr r3, [r7, #16]
+ 8002172: 061b lsls r3, r3, #24
+ 8002174: 431a orrs r2, r3
+ 8002176: 68fb ldr r3, [r7, #12]
+ 8002178: 071b lsls r3, r3, #28
+ 800217a: 4929 ldr r1, [pc, #164] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800217c: 4313 orrs r3, r2
+ 800217e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+ }
+
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
+ /*---------------------------- LTDC configuration -------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+ 8002182: 687b ldr r3, [r7, #4]
+ 8002184: 681b ldr r3, [r3, #0]
+ 8002186: f003 0308 and.w r3, r3, #8
+ 800218a: 2b00 cmp r3, #0
+ 800218c: d028 beq.n 80021e0 <HAL_RCCEx_PeriphCLKConfig+0x808>
+ {
+ assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+ /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ 800218e: 4b24 ldr r3, [pc, #144] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002190: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8002194: 0e1b lsrs r3, r3, #24
+ 8002196: f003 030f and.w r3, r3, #15
+ 800219a: 613b str r3, [r7, #16]
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ 800219c: 4b20 ldr r3, [pc, #128] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800219e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 80021a2: 0c1b lsrs r3, r3, #16
+ 80021a4: f003 0303 and.w r3, r3, #3
+ 80021a8: 60fb str r3, [r7, #12]
+
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
+ 80021aa: 687b ldr r3, [r7, #4]
+ 80021ac: 695b ldr r3, [r3, #20]
+ 80021ae: 019a lsls r2, r3, #6
+ 80021b0: 68fb ldr r3, [r7, #12]
+ 80021b2: 041b lsls r3, r3, #16
+ 80021b4: 431a orrs r2, r3
+ 80021b6: 693b ldr r3, [r7, #16]
+ 80021b8: 061b lsls r3, r3, #24
+ 80021ba: 431a orrs r2, r3
+ 80021bc: 687b ldr r3, [r7, #4]
+ 80021be: 69db ldr r3, [r3, #28]
+ 80021c0: 071b lsls r3, r3, #28
+ 80021c2: 4917 ldr r1, [pc, #92] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021c4: 4313 orrs r3, r2
+ 80021c6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+ 80021ca: 4b15 ldr r3, [pc, #84] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021cc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 80021d0: f423 3240 bic.w r2, r3, #196608 ; 0x30000
+ 80021d4: 687b ldr r3, [r7, #4]
+ 80021d6: 6adb ldr r3, [r3, #44] ; 0x2c
+ 80021d8: 4911 ldr r1, [pc, #68] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021da: 4313 orrs r3, r2
+ 80021dc: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ }
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
+
+ /* Enable PLLSAI Clock */
+ __HAL_RCC_PLLSAI_ENABLE();
+ 80021e0: 4b0f ldr r3, [pc, #60] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021e2: 681b ldr r3, [r3, #0]
+ 80021e4: 4a0e ldr r2, [pc, #56] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 80021e6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 80021ea: 6013 str r3, [r2, #0]
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+ 80021ec: f7fe fcca bl 8000b84 <HAL_GetTick>
+ 80021f0: 6178 str r0, [r7, #20]
+
+ /* Wait till PLLSAI is ready */
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ 80021f2: e008 b.n 8002206 <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ {
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ 80021f4: f7fe fcc6 bl 8000b84 <HAL_GetTick>
+ 80021f8: 4602 mov r2, r0
+ 80021fa: 697b ldr r3, [r7, #20]
+ 80021fc: 1ad3 subs r3, r2, r3
+ 80021fe: 2b64 cmp r3, #100 ; 0x64
+ 8002200: d901 bls.n 8002206 <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ 8002202: 2303 movs r3, #3
+ 8002204: e007 b.n 8002216 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ 8002206: 4b06 ldr r3, [pc, #24] ; (8002220 <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002208: 681b ldr r3, [r3, #0]
+ 800220a: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
+ 800220e: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
+ 8002212: d1ef bne.n 80021f4 <HAL_RCCEx_PeriphCLKConfig+0x81c>
+ }
+ }
+ }
+ return HAL_OK;
+ 8002214: 2300 movs r3, #0
+}
+ 8002216: 4618 mov r0, r3
+ 8002218: 3720 adds r7, #32
+ 800221a: 46bd mov sp, r7
+ 800221c: bd80 pop {r7, pc}
+ 800221e: bf00 nop
+ 8002220: 40023800 .word 0x40023800
+
+08002224 <HAL_TIM_Base_Init>:
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ 8002224: b580 push {r7, lr}
+ 8002226: b082 sub sp, #8
+ 8002228: af00 add r7, sp, #0
+ 800222a: 6078 str r0, [r7, #4]
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ 800222c: 687b ldr r3, [r7, #4]
+ 800222e: 2b00 cmp r3, #0
+ 8002230: d101 bne.n 8002236 <HAL_TIM_Base_Init+0x12>
+ {
+ return HAL_ERROR;
+ 8002232: 2301 movs r3, #1
+ 8002234: e01d b.n 8002272 <HAL_TIM_Base_Init+0x4e>
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ 8002236: 687b ldr r3, [r7, #4]
+ 8002238: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
+ 800223c: b2db uxtb r3, r3
+ 800223e: 2b00 cmp r3, #0
+ 8002240: d106 bne.n 8002250 <HAL_TIM_Base_Init+0x2c>
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+ 8002242: 687b ldr r3, [r7, #4]
+ 8002244: 2200 movs r2, #0
+ 8002246: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+ 800224a: 6878 ldr r0, [r7, #4]
+ 800224c: f7fe fb36 bl 80008bc <HAL_TIM_Base_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+ 8002250: 687b ldr r3, [r7, #4]
+ 8002252: 2202 movs r2, #2
+ 8002254: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8002258: 687b ldr r3, [r7, #4]
+ 800225a: 681a ldr r2, [r3, #0]
+ 800225c: 687b ldr r3, [r7, #4]
+ 800225e: 3304 adds r3, #4
+ 8002260: 4619 mov r1, r3
+ 8002262: 4610 mov r0, r2
+ 8002264: f000 fa36 bl 80026d4 <TIM_Base_SetConfig>
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+ 8002268: 687b ldr r3, [r7, #4]
+ 800226a: 2201 movs r2, #1
+ 800226c: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ return HAL_OK;
+ 8002270: 2300 movs r3, #0
+}
+ 8002272: 4618 mov r0, r3
+ 8002274: 3708 adds r7, #8
+ 8002276: 46bd mov sp, r7
+ 8002278: bd80 pop {r7, pc}
+ ...
+
+0800227c <HAL_TIM_Base_Start_IT>:
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ 800227c: b480 push {r7}
+ 800227e: b085 sub sp, #20
+ 8002280: af00 add r7, sp, #0
+ 8002282: 6078 str r0, [r7, #4]
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+ 8002284: 687b ldr r3, [r7, #4]
+ 8002286: 681b ldr r3, [r3, #0]
+ 8002288: 68da ldr r2, [r3, #12]
+ 800228a: 687b ldr r3, [r7, #4]
+ 800228c: 681b ldr r3, [r3, #0]
+ 800228e: f042 0201 orr.w r2, r2, #1
+ 8002292: 60da str r2, [r3, #12]
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 8002294: 687b ldr r3, [r7, #4]
+ 8002296: 681b ldr r3, [r3, #0]
+ 8002298: 689a ldr r2, [r3, #8]
+ 800229a: 4b0c ldr r3, [pc, #48] ; (80022cc <HAL_TIM_Base_Start_IT+0x50>)
+ 800229c: 4013 ands r3, r2
+ 800229e: 60fb str r3, [r7, #12]
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 80022a0: 68fb ldr r3, [r7, #12]
+ 80022a2: 2b06 cmp r3, #6
+ 80022a4: d00b beq.n 80022be <HAL_TIM_Base_Start_IT+0x42>
+ 80022a6: 68fb ldr r3, [r7, #12]
+ 80022a8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 80022ac: d007 beq.n 80022be <HAL_TIM_Base_Start_IT+0x42>
+ {
+ __HAL_TIM_ENABLE(htim);
+ 80022ae: 687b ldr r3, [r7, #4]
+ 80022b0: 681b ldr r3, [r3, #0]
+ 80022b2: 681a ldr r2, [r3, #0]
+ 80022b4: 687b ldr r3, [r7, #4]
+ 80022b6: 681b ldr r3, [r3, #0]
+ 80022b8: f042 0201 orr.w r2, r2, #1
+ 80022bc: 601a str r2, [r3, #0]
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ 80022be: 2300 movs r3, #0
+}
+ 80022c0: 4618 mov r0, r3
+ 80022c2: 3714 adds r7, #20
+ 80022c4: 46bd mov sp, r7
+ 80022c6: f85d 7b04 ldr.w r7, [sp], #4
+ 80022ca: 4770 bx lr
+ 80022cc: 00010007 .word 0x00010007
+
+080022d0 <HAL_TIM_IRQHandler>:
+ * @brief This function handles TIM interrupts requests.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ 80022d0: b580 push {r7, lr}
+ 80022d2: b082 sub sp, #8
+ 80022d4: af00 add r7, sp, #0
+ 80022d6: 6078 str r0, [r7, #4]
+ /* Capture compare 1 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ 80022d8: 687b ldr r3, [r7, #4]
+ 80022da: 681b ldr r3, [r3, #0]
+ 80022dc: 691b ldr r3, [r3, #16]
+ 80022de: f003 0302 and.w r3, r3, #2
+ 80022e2: 2b02 cmp r3, #2
+ 80022e4: d122 bne.n 800232c <HAL_TIM_IRQHandler+0x5c>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ 80022e6: 687b ldr r3, [r7, #4]
+ 80022e8: 681b ldr r3, [r3, #0]
+ 80022ea: 68db ldr r3, [r3, #12]
+ 80022ec: f003 0302 and.w r3, r3, #2
+ 80022f0: 2b02 cmp r3, #2
+ 80022f2: d11b bne.n 800232c <HAL_TIM_IRQHandler+0x5c>
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ 80022f4: 687b ldr r3, [r7, #4]
+ 80022f6: 681b ldr r3, [r3, #0]
+ 80022f8: f06f 0202 mvn.w r2, #2
+ 80022fc: 611a str r2, [r3, #16]
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ 80022fe: 687b ldr r3, [r7, #4]
+ 8002300: 2201 movs r2, #1
+ 8002302: 771a strb r2, [r3, #28]
+
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ 8002304: 687b ldr r3, [r7, #4]
+ 8002306: 681b ldr r3, [r3, #0]
+ 8002308: 699b ldr r3, [r3, #24]
+ 800230a: f003 0303 and.w r3, r3, #3
+ 800230e: 2b00 cmp r3, #0
+ 8002310: d003 beq.n 800231a <HAL_TIM_IRQHandler+0x4a>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+ 8002312: 6878 ldr r0, [r7, #4]
+ 8002314: f000 f9c0 bl 8002698 <HAL_TIM_IC_CaptureCallback>
+ 8002318: e005 b.n 8002326 <HAL_TIM_IRQHandler+0x56>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ 800231a: 6878 ldr r0, [r7, #4]
+ 800231c: f000 f9b2 bl 8002684 <HAL_TIM_OC_DelayElapsedCallback>
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8002320: 6878 ldr r0, [r7, #4]
+ 8002322: f000 f9c3 bl 80026ac <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8002326: 687b ldr r3, [r7, #4]
+ 8002328: 2200 movs r2, #0
+ 800232a: 771a strb r2, [r3, #28]
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ 800232c: 687b ldr r3, [r7, #4]
+ 800232e: 681b ldr r3, [r3, #0]
+ 8002330: 691b ldr r3, [r3, #16]
+ 8002332: f003 0304 and.w r3, r3, #4
+ 8002336: 2b04 cmp r3, #4
+ 8002338: d122 bne.n 8002380 <HAL_TIM_IRQHandler+0xb0>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ 800233a: 687b ldr r3, [r7, #4]
+ 800233c: 681b ldr r3, [r3, #0]
+ 800233e: 68db ldr r3, [r3, #12]
+ 8002340: f003 0304 and.w r3, r3, #4
+ 8002344: 2b04 cmp r3, #4
+ 8002346: d11b bne.n 8002380 <HAL_TIM_IRQHandler+0xb0>
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ 8002348: 687b ldr r3, [r7, #4]
+ 800234a: 681b ldr r3, [r3, #0]
+ 800234c: f06f 0204 mvn.w r2, #4
+ 8002350: 611a str r2, [r3, #16]
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ 8002352: 687b ldr r3, [r7, #4]
+ 8002354: 2202 movs r2, #2
+ 8002356: 771a strb r2, [r3, #28]
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ 8002358: 687b ldr r3, [r7, #4]
+ 800235a: 681b ldr r3, [r3, #0]
+ 800235c: 699b ldr r3, [r3, #24]
+ 800235e: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8002362: 2b00 cmp r3, #0
+ 8002364: d003 beq.n 800236e <HAL_TIM_IRQHandler+0x9e>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+ 8002366: 6878 ldr r0, [r7, #4]
+ 8002368: f000 f996 bl 8002698 <HAL_TIM_IC_CaptureCallback>
+ 800236c: e005 b.n 800237a <HAL_TIM_IRQHandler+0xaa>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ 800236e: 6878 ldr r0, [r7, #4]
+ 8002370: f000 f988 bl 8002684 <HAL_TIM_OC_DelayElapsedCallback>
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8002374: 6878 ldr r0, [r7, #4]
+ 8002376: f000 f999 bl 80026ac <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 800237a: 687b ldr r3, [r7, #4]
+ 800237c: 2200 movs r2, #0
+ 800237e: 771a strb r2, [r3, #28]
+ }
+ }
+ /* Capture compare 3 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ 8002380: 687b ldr r3, [r7, #4]
+ 8002382: 681b ldr r3, [r3, #0]
+ 8002384: 691b ldr r3, [r3, #16]
+ 8002386: f003 0308 and.w r3, r3, #8
+ 800238a: 2b08 cmp r3, #8
+ 800238c: d122 bne.n 80023d4 <HAL_TIM_IRQHandler+0x104>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ 800238e: 687b ldr r3, [r7, #4]
+ 8002390: 681b ldr r3, [r3, #0]
+ 8002392: 68db ldr r3, [r3, #12]
+ 8002394: f003 0308 and.w r3, r3, #8
+ 8002398: 2b08 cmp r3, #8
+ 800239a: d11b bne.n 80023d4 <HAL_TIM_IRQHandler+0x104>
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ 800239c: 687b ldr r3, [r7, #4]
+ 800239e: 681b ldr r3, [r3, #0]
+ 80023a0: f06f 0208 mvn.w r2, #8
+ 80023a4: 611a str r2, [r3, #16]
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ 80023a6: 687b ldr r3, [r7, #4]
+ 80023a8: 2204 movs r2, #4
+ 80023aa: 771a strb r2, [r3, #28]
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ 80023ac: 687b ldr r3, [r7, #4]
+ 80023ae: 681b ldr r3, [r3, #0]
+ 80023b0: 69db ldr r3, [r3, #28]
+ 80023b2: f003 0303 and.w r3, r3, #3
+ 80023b6: 2b00 cmp r3, #0
+ 80023b8: d003 beq.n 80023c2 <HAL_TIM_IRQHandler+0xf2>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+ 80023ba: 6878 ldr r0, [r7, #4]
+ 80023bc: f000 f96c bl 8002698 <HAL_TIM_IC_CaptureCallback>
+ 80023c0: e005 b.n 80023ce <HAL_TIM_IRQHandler+0xfe>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ 80023c2: 6878 ldr r0, [r7, #4]
+ 80023c4: f000 f95e bl 8002684 <HAL_TIM_OC_DelayElapsedCallback>
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 80023c8: 6878 ldr r0, [r7, #4]
+ 80023ca: f000 f96f bl 80026ac <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 80023ce: 687b ldr r3, [r7, #4]
+ 80023d0: 2200 movs r2, #0
+ 80023d2: 771a strb r2, [r3, #28]
+ }
+ }
+ /* Capture compare 4 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ 80023d4: 687b ldr r3, [r7, #4]
+ 80023d6: 681b ldr r3, [r3, #0]
+ 80023d8: 691b ldr r3, [r3, #16]
+ 80023da: f003 0310 and.w r3, r3, #16
+ 80023de: 2b10 cmp r3, #16
+ 80023e0: d122 bne.n 8002428 <HAL_TIM_IRQHandler+0x158>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ 80023e2: 687b ldr r3, [r7, #4]
+ 80023e4: 681b ldr r3, [r3, #0]
+ 80023e6: 68db ldr r3, [r3, #12]
+ 80023e8: f003 0310 and.w r3, r3, #16
+ 80023ec: 2b10 cmp r3, #16
+ 80023ee: d11b bne.n 8002428 <HAL_TIM_IRQHandler+0x158>
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ 80023f0: 687b ldr r3, [r7, #4]
+ 80023f2: 681b ldr r3, [r3, #0]
+ 80023f4: f06f 0210 mvn.w r2, #16
+ 80023f8: 611a str r2, [r3, #16]
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ 80023fa: 687b ldr r3, [r7, #4]
+ 80023fc: 2208 movs r2, #8
+ 80023fe: 771a strb r2, [r3, #28]
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ 8002400: 687b ldr r3, [r7, #4]
+ 8002402: 681b ldr r3, [r3, #0]
+ 8002404: 69db ldr r3, [r3, #28]
+ 8002406: f403 7340 and.w r3, r3, #768 ; 0x300
+ 800240a: 2b00 cmp r3, #0
+ 800240c: d003 beq.n 8002416 <HAL_TIM_IRQHandler+0x146>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+ 800240e: 6878 ldr r0, [r7, #4]
+ 8002410: f000 f942 bl 8002698 <HAL_TIM_IC_CaptureCallback>
+ 8002414: e005 b.n 8002422 <HAL_TIM_IRQHandler+0x152>
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8002416: 6878 ldr r0, [r7, #4]
+ 8002418: f000 f934 bl 8002684 <HAL_TIM_OC_DelayElapsedCallback>
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 800241c: 6878 ldr r0, [r7, #4]
+ 800241e: f000 f945 bl 80026ac <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8002422: 687b ldr r3, [r7, #4]
+ 8002424: 2200 movs r2, #0
+ 8002426: 771a strb r2, [r3, #28]
+ }
+ }
+ /* TIM Update event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ 8002428: 687b ldr r3, [r7, #4]
+ 800242a: 681b ldr r3, [r3, #0]
+ 800242c: 691b ldr r3, [r3, #16]
+ 800242e: f003 0301 and.w r3, r3, #1
+ 8002432: 2b01 cmp r3, #1
+ 8002434: d10e bne.n 8002454 <HAL_TIM_IRQHandler+0x184>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ 8002436: 687b ldr r3, [r7, #4]
+ 8002438: 681b ldr r3, [r3, #0]
+ 800243a: 68db ldr r3, [r3, #12]
+ 800243c: f003 0301 and.w r3, r3, #1
+ 8002440: 2b01 cmp r3, #1
+ 8002442: d107 bne.n 8002454 <HAL_TIM_IRQHandler+0x184>
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ 8002444: 687b ldr r3, [r7, #4]
+ 8002446: 681b ldr r3, [r3, #0]
+ 8002448: f06f 0201 mvn.w r2, #1
+ 800244c: 611a str r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+ 800244e: 6878 ldr r0, [r7, #4]
+ 8002450: f7fe f9c8 bl 80007e4 <HAL_TIM_PeriodElapsedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ 8002454: 687b ldr r3, [r7, #4]
+ 8002456: 681b ldr r3, [r3, #0]
+ 8002458: 691b ldr r3, [r3, #16]
+ 800245a: f003 0380 and.w r3, r3, #128 ; 0x80
+ 800245e: 2b80 cmp r3, #128 ; 0x80
+ 8002460: d10e bne.n 8002480 <HAL_TIM_IRQHandler+0x1b0>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ 8002462: 687b ldr r3, [r7, #4]
+ 8002464: 681b ldr r3, [r3, #0]
+ 8002466: 68db ldr r3, [r3, #12]
+ 8002468: f003 0380 and.w r3, r3, #128 ; 0x80
+ 800246c: 2b80 cmp r3, #128 ; 0x80
+ 800246e: d107 bne.n 8002480 <HAL_TIM_IRQHandler+0x1b0>
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ 8002470: 687b ldr r3, [r7, #4]
+ 8002472: 681b ldr r3, [r3, #0]
+ 8002474: f06f 0280 mvn.w r2, #128 ; 0x80
+ 8002478: 611a str r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
+ HAL_TIMEx_BreakCallback(htim);
+ 800247a: 6878 ldr r0, [r7, #4]
+ 800247c: f000 faca bl 8002a14 <HAL_TIMEx_BreakCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break2 input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ 8002480: 687b ldr r3, [r7, #4]
+ 8002482: 681b ldr r3, [r3, #0]
+ 8002484: 691b ldr r3, [r3, #16]
+ 8002486: f403 7380 and.w r3, r3, #256 ; 0x100
+ 800248a: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 800248e: d10e bne.n 80024ae <HAL_TIM_IRQHandler+0x1de>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ 8002490: 687b ldr r3, [r7, #4]
+ 8002492: 681b ldr r3, [r3, #0]
+ 8002494: 68db ldr r3, [r3, #12]
+ 8002496: f003 0380 and.w r3, r3, #128 ; 0x80
+ 800249a: 2b80 cmp r3, #128 ; 0x80
+ 800249c: d107 bne.n 80024ae <HAL_TIM_IRQHandler+0x1de>
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+ 800249e: 687b ldr r3, [r7, #4]
+ 80024a0: 681b ldr r3, [r3, #0]
+ 80024a2: f46f 7280 mvn.w r2, #256 ; 0x100
+ 80024a6: 611a str r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->Break2Callback(htim);
+#else
+ HAL_TIMEx_Break2Callback(htim);
+ 80024a8: 6878 ldr r0, [r7, #4]
+ 80024aa: f000 fabd bl 8002a28 <HAL_TIMEx_Break2Callback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Trigger detection event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ 80024ae: 687b ldr r3, [r7, #4]
+ 80024b0: 681b ldr r3, [r3, #0]
+ 80024b2: 691b ldr r3, [r3, #16]
+ 80024b4: f003 0340 and.w r3, r3, #64 ; 0x40
+ 80024b8: 2b40 cmp r3, #64 ; 0x40
+ 80024ba: d10e bne.n 80024da <HAL_TIM_IRQHandler+0x20a>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ 80024bc: 687b ldr r3, [r7, #4]
+ 80024be: 681b ldr r3, [r3, #0]
+ 80024c0: 68db ldr r3, [r3, #12]
+ 80024c2: f003 0340 and.w r3, r3, #64 ; 0x40
+ 80024c6: 2b40 cmp r3, #64 ; 0x40
+ 80024c8: d107 bne.n 80024da <HAL_TIM_IRQHandler+0x20a>
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ 80024ca: 687b ldr r3, [r7, #4]
+ 80024cc: 681b ldr r3, [r3, #0]
+ 80024ce: f06f 0240 mvn.w r2, #64 ; 0x40
+ 80024d2: 611a str r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+ 80024d4: 6878 ldr r0, [r7, #4]
+ 80024d6: f000 f8f3 bl 80026c0 <HAL_TIM_TriggerCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM commutation event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ 80024da: 687b ldr r3, [r7, #4]
+ 80024dc: 681b ldr r3, [r3, #0]
+ 80024de: 691b ldr r3, [r3, #16]
+ 80024e0: f003 0320 and.w r3, r3, #32
+ 80024e4: 2b20 cmp r3, #32
+ 80024e6: d10e bne.n 8002506 <HAL_TIM_IRQHandler+0x236>
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ 80024e8: 687b ldr r3, [r7, #4]
+ 80024ea: 681b ldr r3, [r3, #0]
+ 80024ec: 68db ldr r3, [r3, #12]
+ 80024ee: f003 0320 and.w r3, r3, #32
+ 80024f2: 2b20 cmp r3, #32
+ 80024f4: d107 bne.n 8002506 <HAL_TIM_IRQHandler+0x236>
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ 80024f6: 687b ldr r3, [r7, #4]
+ 80024f8: 681b ldr r3, [r3, #0]
+ 80024fa: f06f 0220 mvn.w r2, #32
+ 80024fe: 611a str r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+ 8002500: 6878 ldr r0, [r7, #4]
+ 8002502: f000 fa7d bl 8002a00 <HAL_TIMEx_CommutCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+}
+ 8002506: bf00 nop
+ 8002508: 3708 adds r7, #8
+ 800250a: 46bd mov sp, r7
+ 800250c: bd80 pop {r7, pc}
+ ...
+
+08002510 <HAL_TIM_ConfigClockSource>:
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ 8002510: b580 push {r7, lr}
+ 8002512: b084 sub sp, #16
+ 8002514: af00 add r7, sp, #0
+ 8002516: 6078 str r0, [r7, #4]
+ 8002518: 6039 str r1, [r7, #0]
+ uint32_t tmpsmcr;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+ 800251a: 687b ldr r3, [r7, #4]
+ 800251c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 8002520: 2b01 cmp r3, #1
+ 8002522: d101 bne.n 8002528 <HAL_TIM_ConfigClockSource+0x18>
+ 8002524: 2302 movs r3, #2
+ 8002526: e0a6 b.n 8002676 <HAL_TIM_ConfigClockSource+0x166>
+ 8002528: 687b ldr r3, [r7, #4]
+ 800252a: 2201 movs r2, #1
+ 800252c: f883 203c strb.w r2, [r3, #60] ; 0x3c
+
+ htim->State = HAL_TIM_STATE_BUSY;
+ 8002530: 687b ldr r3, [r7, #4]
+ 8002532: 2202 movs r2, #2
+ 8002534: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ 8002538: 687b ldr r3, [r7, #4]
+ 800253a: 681b ldr r3, [r3, #0]
+ 800253c: 689b ldr r3, [r3, #8]
+ 800253e: 60fb str r3, [r7, #12]
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 8002540: 68fa ldr r2, [r7, #12]
+ 8002542: 4b4f ldr r3, [pc, #316] ; (8002680 <HAL_TIM_ConfigClockSource+0x170>)
+ 8002544: 4013 ands r3, r2
+ 8002546: 60fb str r3, [r7, #12]
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8002548: 68fb ldr r3, [r7, #12]
+ 800254a: f423 437f bic.w r3, r3, #65280 ; 0xff00
+ 800254e: 60fb str r3, [r7, #12]
+ htim->Instance->SMCR = tmpsmcr;
+ 8002550: 687b ldr r3, [r7, #4]
+ 8002552: 681b ldr r3, [r3, #0]
+ 8002554: 68fa ldr r2, [r7, #12]
+ 8002556: 609a str r2, [r3, #8]
+
+ switch (sClockSourceConfig->ClockSource)
+ 8002558: 683b ldr r3, [r7, #0]
+ 800255a: 681b ldr r3, [r3, #0]
+ 800255c: 2b40 cmp r3, #64 ; 0x40
+ 800255e: d067 beq.n 8002630 <HAL_TIM_ConfigClockSource+0x120>
+ 8002560: 2b40 cmp r3, #64 ; 0x40
+ 8002562: d80b bhi.n 800257c <HAL_TIM_ConfigClockSource+0x6c>
+ 8002564: 2b10 cmp r3, #16
+ 8002566: d073 beq.n 8002650 <HAL_TIM_ConfigClockSource+0x140>
+ 8002568: 2b10 cmp r3, #16
+ 800256a: d802 bhi.n 8002572 <HAL_TIM_ConfigClockSource+0x62>
+ 800256c: 2b00 cmp r3, #0
+ 800256e: d06f beq.n 8002650 <HAL_TIM_ConfigClockSource+0x140>
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
+
+ default:
+ break;
+ 8002570: e078 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ switch (sClockSourceConfig->ClockSource)
+ 8002572: 2b20 cmp r3, #32
+ 8002574: d06c beq.n 8002650 <HAL_TIM_ConfigClockSource+0x140>
+ 8002576: 2b30 cmp r3, #48 ; 0x30
+ 8002578: d06a beq.n 8002650 <HAL_TIM_ConfigClockSource+0x140>
+ break;
+ 800257a: e073 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ switch (sClockSourceConfig->ClockSource)
+ 800257c: 2b70 cmp r3, #112 ; 0x70
+ 800257e: d00d beq.n 800259c <HAL_TIM_ConfigClockSource+0x8c>
+ 8002580: 2b70 cmp r3, #112 ; 0x70
+ 8002582: d804 bhi.n 800258e <HAL_TIM_ConfigClockSource+0x7e>
+ 8002584: 2b50 cmp r3, #80 ; 0x50
+ 8002586: d033 beq.n 80025f0 <HAL_TIM_ConfigClockSource+0xe0>
+ 8002588: 2b60 cmp r3, #96 ; 0x60
+ 800258a: d041 beq.n 8002610 <HAL_TIM_ConfigClockSource+0x100>
+ break;
+ 800258c: e06a b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ switch (sClockSourceConfig->ClockSource)
+ 800258e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8002592: d066 beq.n 8002662 <HAL_TIM_ConfigClockSource+0x152>
+ 8002594: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
+ 8002598: d017 beq.n 80025ca <HAL_TIM_ConfigClockSource+0xba>
+ break;
+ 800259a: e063 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ TIM_ETR_SetConfig(htim->Instance,
+ 800259c: 687b ldr r3, [r7, #4]
+ 800259e: 6818 ldr r0, [r3, #0]
+ 80025a0: 683b ldr r3, [r7, #0]
+ 80025a2: 6899 ldr r1, [r3, #8]
+ 80025a4: 683b ldr r3, [r7, #0]
+ 80025a6: 685a ldr r2, [r3, #4]
+ 80025a8: 683b ldr r3, [r7, #0]
+ 80025aa: 68db ldr r3, [r3, #12]
+ 80025ac: f000 f9ac bl 8002908 <TIM_ETR_SetConfig>
+ tmpsmcr = htim->Instance->SMCR;
+ 80025b0: 687b ldr r3, [r7, #4]
+ 80025b2: 681b ldr r3, [r3, #0]
+ 80025b4: 689b ldr r3, [r3, #8]
+ 80025b6: 60fb str r3, [r7, #12]
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 80025b8: 68fb ldr r3, [r7, #12]
+ 80025ba: f043 0377 orr.w r3, r3, #119 ; 0x77
+ 80025be: 60fb str r3, [r7, #12]
+ htim->Instance->SMCR = tmpsmcr;
+ 80025c0: 687b ldr r3, [r7, #4]
+ 80025c2: 681b ldr r3, [r3, #0]
+ 80025c4: 68fa ldr r2, [r7, #12]
+ 80025c6: 609a str r2, [r3, #8]
+ break;
+ 80025c8: e04c b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ TIM_ETR_SetConfig(htim->Instance,
+ 80025ca: 687b ldr r3, [r7, #4]
+ 80025cc: 6818 ldr r0, [r3, #0]
+ 80025ce: 683b ldr r3, [r7, #0]
+ 80025d0: 6899 ldr r1, [r3, #8]
+ 80025d2: 683b ldr r3, [r7, #0]
+ 80025d4: 685a ldr r2, [r3, #4]
+ 80025d6: 683b ldr r3, [r7, #0]
+ 80025d8: 68db ldr r3, [r3, #12]
+ 80025da: f000 f995 bl 8002908 <TIM_ETR_SetConfig>
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ 80025de: 687b ldr r3, [r7, #4]
+ 80025e0: 681b ldr r3, [r3, #0]
+ 80025e2: 689a ldr r2, [r3, #8]
+ 80025e4: 687b ldr r3, [r7, #4]
+ 80025e6: 681b ldr r3, [r3, #0]
+ 80025e8: f442 4280 orr.w r2, r2, #16384 ; 0x4000
+ 80025ec: 609a str r2, [r3, #8]
+ break;
+ 80025ee: e039 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ 80025f0: 687b ldr r3, [r7, #4]
+ 80025f2: 6818 ldr r0, [r3, #0]
+ 80025f4: 683b ldr r3, [r7, #0]
+ 80025f6: 6859 ldr r1, [r3, #4]
+ 80025f8: 683b ldr r3, [r7, #0]
+ 80025fa: 68db ldr r3, [r3, #12]
+ 80025fc: 461a mov r2, r3
+ 80025fe: f000 f909 bl 8002814 <TIM_TI1_ConfigInputStage>
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ 8002602: 687b ldr r3, [r7, #4]
+ 8002604: 681b ldr r3, [r3, #0]
+ 8002606: 2150 movs r1, #80 ; 0x50
+ 8002608: 4618 mov r0, r3
+ 800260a: f000 f962 bl 80028d2 <TIM_ITRx_SetConfig>
+ break;
+ 800260e: e029 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ 8002610: 687b ldr r3, [r7, #4]
+ 8002612: 6818 ldr r0, [r3, #0]
+ 8002614: 683b ldr r3, [r7, #0]
+ 8002616: 6859 ldr r1, [r3, #4]
+ 8002618: 683b ldr r3, [r7, #0]
+ 800261a: 68db ldr r3, [r3, #12]
+ 800261c: 461a mov r2, r3
+ 800261e: f000 f928 bl 8002872 <TIM_TI2_ConfigInputStage>
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ 8002622: 687b ldr r3, [r7, #4]
+ 8002624: 681b ldr r3, [r3, #0]
+ 8002626: 2160 movs r1, #96 ; 0x60
+ 8002628: 4618 mov r0, r3
+ 800262a: f000 f952 bl 80028d2 <TIM_ITRx_SetConfig>
+ break;
+ 800262e: e019 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ 8002630: 687b ldr r3, [r7, #4]
+ 8002632: 6818 ldr r0, [r3, #0]
+ 8002634: 683b ldr r3, [r7, #0]
+ 8002636: 6859 ldr r1, [r3, #4]
+ 8002638: 683b ldr r3, [r7, #0]
+ 800263a: 68db ldr r3, [r3, #12]
+ 800263c: 461a mov r2, r3
+ 800263e: f000 f8e9 bl 8002814 <TIM_TI1_ConfigInputStage>
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ 8002642: 687b ldr r3, [r7, #4]
+ 8002644: 681b ldr r3, [r3, #0]
+ 8002646: 2140 movs r1, #64 ; 0x40
+ 8002648: 4618 mov r0, r3
+ 800264a: f000 f942 bl 80028d2 <TIM_ITRx_SetConfig>
+ break;
+ 800264e: e009 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ 8002650: 687b ldr r3, [r7, #4]
+ 8002652: 681a ldr r2, [r3, #0]
+ 8002654: 683b ldr r3, [r7, #0]
+ 8002656: 681b ldr r3, [r3, #0]
+ 8002658: 4619 mov r1, r3
+ 800265a: 4610 mov r0, r2
+ 800265c: f000 f939 bl 80028d2 <TIM_ITRx_SetConfig>
+ break;
+ 8002660: e000 b.n 8002664 <HAL_TIM_ConfigClockSource+0x154>
+ break;
+ 8002662: bf00 nop
+ }
+ htim->State = HAL_TIM_STATE_READY;
+ 8002664: 687b ldr r3, [r7, #4]
+ 8002666: 2201 movs r2, #1
+ 8002668: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ __HAL_UNLOCK(htim);
+ 800266c: 687b ldr r3, [r7, #4]
+ 800266e: 2200 movs r2, #0
+ 8002670: f883 203c strb.w r2, [r3, #60] ; 0x3c
+
+ return HAL_OK;
+ 8002674: 2300 movs r3, #0
+}
+ 8002676: 4618 mov r0, r3
+ 8002678: 3710 adds r7, #16
+ 800267a: 46bd mov sp, r7
+ 800267c: bd80 pop {r7, pc}
+ 800267e: bf00 nop
+ 8002680: fffeff88 .word 0xfffeff88
+
+08002684 <HAL_TIM_OC_DelayElapsedCallback>:
+ * @brief Output Compare callback in non-blocking mode
+ * @param htim TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ 8002684: b480 push {r7}
+ 8002686: b083 sub sp, #12
+ 8002688: af00 add r7, sp, #0
+ 800268a: 6078 str r0, [r7, #4]
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+ 800268c: bf00 nop
+ 800268e: 370c adds r7, #12
+ 8002690: 46bd mov sp, r7
+ 8002692: f85d 7b04 ldr.w r7, [sp], #4
+ 8002696: 4770 bx lr
+
+08002698 <HAL_TIM_IC_CaptureCallback>:
+ * @brief Input Capture callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ 8002698: b480 push {r7}
+ 800269a: b083 sub sp, #12
+ 800269c: af00 add r7, sp, #0
+ 800269e: 6078 str r0, [r7, #4]
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+ 80026a0: bf00 nop
+ 80026a2: 370c adds r7, #12
+ 80026a4: 46bd mov sp, r7
+ 80026a6: f85d 7b04 ldr.w r7, [sp], #4
+ 80026aa: 4770 bx lr
+
+080026ac <HAL_TIM_PWM_PulseFinishedCallback>:
+ * @brief PWM Pulse finished callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ 80026ac: b480 push {r7}
+ 80026ae: b083 sub sp, #12
+ 80026b0: af00 add r7, sp, #0
+ 80026b2: 6078 str r0, [r7, #4]
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+ 80026b4: bf00 nop
+ 80026b6: 370c adds r7, #12
+ 80026b8: 46bd mov sp, r7
+ 80026ba: f85d 7b04 ldr.w r7, [sp], #4
+ 80026be: 4770 bx lr
+
+080026c0 <HAL_TIM_TriggerCallback>:
+ * @brief Hall Trigger detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ 80026c0: b480 push {r7}
+ 80026c2: b083 sub sp, #12
+ 80026c4: af00 add r7, sp, #0
+ 80026c6: 6078 str r0, [r7, #4]
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+ 80026c8: bf00 nop
+ 80026ca: 370c adds r7, #12
+ 80026cc: 46bd mov sp, r7
+ 80026ce: f85d 7b04 ldr.w r7, [sp], #4
+ 80026d2: 4770 bx lr
+
+080026d4 <TIM_Base_SetConfig>:
+ * @param TIMx TIM peripheral
+ * @param Structure TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ 80026d4: b480 push {r7}
+ 80026d6: b085 sub sp, #20
+ 80026d8: af00 add r7, sp, #0
+ 80026da: 6078 str r0, [r7, #4]
+ 80026dc: 6039 str r1, [r7, #0]
+ uint32_t tmpcr1;
+ tmpcr1 = TIMx->CR1;
+ 80026de: 687b ldr r3, [r7, #4]
+ 80026e0: 681b ldr r3, [r3, #0]
+ 80026e2: 60fb str r3, [r7, #12]
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 80026e4: 687b ldr r3, [r7, #4]
+ 80026e6: 4a40 ldr r2, [pc, #256] ; (80027e8 <TIM_Base_SetConfig+0x114>)
+ 80026e8: 4293 cmp r3, r2
+ 80026ea: d013 beq.n 8002714 <TIM_Base_SetConfig+0x40>
+ 80026ec: 687b ldr r3, [r7, #4]
+ 80026ee: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 80026f2: d00f beq.n 8002714 <TIM_Base_SetConfig+0x40>
+ 80026f4: 687b ldr r3, [r7, #4]
+ 80026f6: 4a3d ldr r2, [pc, #244] ; (80027ec <TIM_Base_SetConfig+0x118>)
+ 80026f8: 4293 cmp r3, r2
+ 80026fa: d00b beq.n 8002714 <TIM_Base_SetConfig+0x40>
+ 80026fc: 687b ldr r3, [r7, #4]
+ 80026fe: 4a3c ldr r2, [pc, #240] ; (80027f0 <TIM_Base_SetConfig+0x11c>)
+ 8002700: 4293 cmp r3, r2
+ 8002702: d007 beq.n 8002714 <TIM_Base_SetConfig+0x40>
+ 8002704: 687b ldr r3, [r7, #4]
+ 8002706: 4a3b ldr r2, [pc, #236] ; (80027f4 <TIM_Base_SetConfig+0x120>)
+ 8002708: 4293 cmp r3, r2
+ 800270a: d003 beq.n 8002714 <TIM_Base_SetConfig+0x40>
+ 800270c: 687b ldr r3, [r7, #4]
+ 800270e: 4a3a ldr r2, [pc, #232] ; (80027f8 <TIM_Base_SetConfig+0x124>)
+ 8002710: 4293 cmp r3, r2
+ 8002712: d108 bne.n 8002726 <TIM_Base_SetConfig+0x52>
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 8002714: 68fb ldr r3, [r7, #12]
+ 8002716: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 800271a: 60fb str r3, [r7, #12]
+ tmpcr1 |= Structure->CounterMode;
+ 800271c: 683b ldr r3, [r7, #0]
+ 800271e: 685b ldr r3, [r3, #4]
+ 8002720: 68fa ldr r2, [r7, #12]
+ 8002722: 4313 orrs r3, r2
+ 8002724: 60fb str r3, [r7, #12]
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 8002726: 687b ldr r3, [r7, #4]
+ 8002728: 4a2f ldr r2, [pc, #188] ; (80027e8 <TIM_Base_SetConfig+0x114>)
+ 800272a: 4293 cmp r3, r2
+ 800272c: d02b beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 800272e: 687b ldr r3, [r7, #4]
+ 8002730: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 8002734: d027 beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 8002736: 687b ldr r3, [r7, #4]
+ 8002738: 4a2c ldr r2, [pc, #176] ; (80027ec <TIM_Base_SetConfig+0x118>)
+ 800273a: 4293 cmp r3, r2
+ 800273c: d023 beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 800273e: 687b ldr r3, [r7, #4]
+ 8002740: 4a2b ldr r2, [pc, #172] ; (80027f0 <TIM_Base_SetConfig+0x11c>)
+ 8002742: 4293 cmp r3, r2
+ 8002744: d01f beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 8002746: 687b ldr r3, [r7, #4]
+ 8002748: 4a2a ldr r2, [pc, #168] ; (80027f4 <TIM_Base_SetConfig+0x120>)
+ 800274a: 4293 cmp r3, r2
+ 800274c: d01b beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 800274e: 687b ldr r3, [r7, #4]
+ 8002750: 4a29 ldr r2, [pc, #164] ; (80027f8 <TIM_Base_SetConfig+0x124>)
+ 8002752: 4293 cmp r3, r2
+ 8002754: d017 beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 8002756: 687b ldr r3, [r7, #4]
+ 8002758: 4a28 ldr r2, [pc, #160] ; (80027fc <TIM_Base_SetConfig+0x128>)
+ 800275a: 4293 cmp r3, r2
+ 800275c: d013 beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 800275e: 687b ldr r3, [r7, #4]
+ 8002760: 4a27 ldr r2, [pc, #156] ; (8002800 <TIM_Base_SetConfig+0x12c>)
+ 8002762: 4293 cmp r3, r2
+ 8002764: d00f beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 8002766: 687b ldr r3, [r7, #4]
+ 8002768: 4a26 ldr r2, [pc, #152] ; (8002804 <TIM_Base_SetConfig+0x130>)
+ 800276a: 4293 cmp r3, r2
+ 800276c: d00b beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 800276e: 687b ldr r3, [r7, #4]
+ 8002770: 4a25 ldr r2, [pc, #148] ; (8002808 <TIM_Base_SetConfig+0x134>)
+ 8002772: 4293 cmp r3, r2
+ 8002774: d007 beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 8002776: 687b ldr r3, [r7, #4]
+ 8002778: 4a24 ldr r2, [pc, #144] ; (800280c <TIM_Base_SetConfig+0x138>)
+ 800277a: 4293 cmp r3, r2
+ 800277c: d003 beq.n 8002786 <TIM_Base_SetConfig+0xb2>
+ 800277e: 687b ldr r3, [r7, #4]
+ 8002780: 4a23 ldr r2, [pc, #140] ; (8002810 <TIM_Base_SetConfig+0x13c>)
+ 8002782: 4293 cmp r3, r2
+ 8002784: d108 bne.n 8002798 <TIM_Base_SetConfig+0xc4>
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ 8002786: 68fb ldr r3, [r7, #12]
+ 8002788: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 800278c: 60fb str r3, [r7, #12]
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 800278e: 683b ldr r3, [r7, #0]
+ 8002790: 68db ldr r3, [r3, #12]
+ 8002792: 68fa ldr r2, [r7, #12]
+ 8002794: 4313 orrs r3, r2
+ 8002796: 60fb str r3, [r7, #12]
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 8002798: 68fb ldr r3, [r7, #12]
+ 800279a: f023 0280 bic.w r2, r3, #128 ; 0x80
+ 800279e: 683b ldr r3, [r7, #0]
+ 80027a0: 695b ldr r3, [r3, #20]
+ 80027a2: 4313 orrs r3, r2
+ 80027a4: 60fb str r3, [r7, #12]
+
+ TIMx->CR1 = tmpcr1;
+ 80027a6: 687b ldr r3, [r7, #4]
+ 80027a8: 68fa ldr r2, [r7, #12]
+ 80027aa: 601a str r2, [r3, #0]
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+ 80027ac: 683b ldr r3, [r7, #0]
+ 80027ae: 689a ldr r2, [r3, #8]
+ 80027b0: 687b ldr r3, [r7, #4]
+ 80027b2: 62da str r2, [r3, #44] ; 0x2c
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Structure->Prescaler;
+ 80027b4: 683b ldr r3, [r7, #0]
+ 80027b6: 681a ldr r2, [r3, #0]
+ 80027b8: 687b ldr r3, [r7, #4]
+ 80027ba: 629a str r2, [r3, #40] ; 0x28
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ 80027bc: 687b ldr r3, [r7, #4]
+ 80027be: 4a0a ldr r2, [pc, #40] ; (80027e8 <TIM_Base_SetConfig+0x114>)
+ 80027c0: 4293 cmp r3, r2
+ 80027c2: d003 beq.n 80027cc <TIM_Base_SetConfig+0xf8>
+ 80027c4: 687b ldr r3, [r7, #4]
+ 80027c6: 4a0c ldr r2, [pc, #48] ; (80027f8 <TIM_Base_SetConfig+0x124>)
+ 80027c8: 4293 cmp r3, r2
+ 80027ca: d103 bne.n 80027d4 <TIM_Base_SetConfig+0x100>
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ 80027cc: 683b ldr r3, [r7, #0]
+ 80027ce: 691a ldr r2, [r3, #16]
+ 80027d0: 687b ldr r3, [r7, #4]
+ 80027d2: 631a str r2, [r3, #48] ; 0x30
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+ 80027d4: 687b ldr r3, [r7, #4]
+ 80027d6: 2201 movs r2, #1
+ 80027d8: 615a str r2, [r3, #20]
+}
+ 80027da: bf00 nop
+ 80027dc: 3714 adds r7, #20
+ 80027de: 46bd mov sp, r7
+ 80027e0: f85d 7b04 ldr.w r7, [sp], #4
+ 80027e4: 4770 bx lr
+ 80027e6: bf00 nop
+ 80027e8: 40010000 .word 0x40010000
+ 80027ec: 40000400 .word 0x40000400
+ 80027f0: 40000800 .word 0x40000800
+ 80027f4: 40000c00 .word 0x40000c00
+ 80027f8: 40010400 .word 0x40010400
+ 80027fc: 40014000 .word 0x40014000
+ 8002800: 40014400 .word 0x40014400
+ 8002804: 40014800 .word 0x40014800
+ 8002808: 40001800 .word 0x40001800
+ 800280c: 40001c00 .word 0x40001c00
+ 8002810: 40002000 .word 0x40002000
+
+08002814 <TIM_TI1_ConfigInputStage>:
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 8002814: b480 push {r7}
+ 8002816: b087 sub sp, #28
+ 8002818: af00 add r7, sp, #0
+ 800281a: 60f8 str r0, [r7, #12]
+ 800281c: 60b9 str r1, [r7, #8]
+ 800281e: 607a str r2, [r7, #4]
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ 8002820: 68fb ldr r3, [r7, #12]
+ 8002822: 6a1b ldr r3, [r3, #32]
+ 8002824: 617b str r3, [r7, #20]
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ 8002826: 68fb ldr r3, [r7, #12]
+ 8002828: 6a1b ldr r3, [r3, #32]
+ 800282a: f023 0201 bic.w r2, r3, #1
+ 800282e: 68fb ldr r3, [r7, #12]
+ 8002830: 621a str r2, [r3, #32]
+ tmpccmr1 = TIMx->CCMR1;
+ 8002832: 68fb ldr r3, [r7, #12]
+ 8002834: 699b ldr r3, [r3, #24]
+ 8002836: 613b str r3, [r7, #16]
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 8002838: 693b ldr r3, [r7, #16]
+ 800283a: f023 03f0 bic.w r3, r3, #240 ; 0xf0
+ 800283e: 613b str r3, [r7, #16]
+ tmpccmr1 |= (TIM_ICFilter << 4U);
+ 8002840: 687b ldr r3, [r7, #4]
+ 8002842: 011b lsls r3, r3, #4
+ 8002844: 693a ldr r2, [r7, #16]
+ 8002846: 4313 orrs r3, r2
+ 8002848: 613b str r3, [r7, #16]
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 800284a: 697b ldr r3, [r7, #20]
+ 800284c: f023 030a bic.w r3, r3, #10
+ 8002850: 617b str r3, [r7, #20]
+ tmpccer |= TIM_ICPolarity;
+ 8002852: 697a ldr r2, [r7, #20]
+ 8002854: 68bb ldr r3, [r7, #8]
+ 8002856: 4313 orrs r3, r2
+ 8002858: 617b str r3, [r7, #20]
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ 800285a: 68fb ldr r3, [r7, #12]
+ 800285c: 693a ldr r2, [r7, #16]
+ 800285e: 619a str r2, [r3, #24]
+ TIMx->CCER = tmpccer;
+ 8002860: 68fb ldr r3, [r7, #12]
+ 8002862: 697a ldr r2, [r7, #20]
+ 8002864: 621a str r2, [r3, #32]
+}
+ 8002866: bf00 nop
+ 8002868: 371c adds r7, #28
+ 800286a: 46bd mov sp, r7
+ 800286c: f85d 7b04 ldr.w r7, [sp], #4
+ 8002870: 4770 bx lr
+
+08002872 <TIM_TI2_ConfigInputStage>:
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 8002872: b480 push {r7}
+ 8002874: b087 sub sp, #28
+ 8002876: af00 add r7, sp, #0
+ 8002878: 60f8 str r0, [r7, #12]
+ 800287a: 60b9 str r1, [r7, #8]
+ 800287c: 607a str r2, [r7, #4]
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ 800287e: 68fb ldr r3, [r7, #12]
+ 8002880: 6a1b ldr r3, [r3, #32]
+ 8002882: f023 0210 bic.w r2, r3, #16
+ 8002886: 68fb ldr r3, [r7, #12]
+ 8002888: 621a str r2, [r3, #32]
+ tmpccmr1 = TIMx->CCMR1;
+ 800288a: 68fb ldr r3, [r7, #12]
+ 800288c: 699b ldr r3, [r3, #24]
+ 800288e: 617b str r3, [r7, #20]
+ tmpccer = TIMx->CCER;
+ 8002890: 68fb ldr r3, [r7, #12]
+ 8002892: 6a1b ldr r3, [r3, #32]
+ 8002894: 613b str r3, [r7, #16]
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 8002896: 697b ldr r3, [r7, #20]
+ 8002898: f423 4370 bic.w r3, r3, #61440 ; 0xf000
+ 800289c: 617b str r3, [r7, #20]
+ tmpccmr1 |= (TIM_ICFilter << 12U);
+ 800289e: 687b ldr r3, [r7, #4]
+ 80028a0: 031b lsls r3, r3, #12
+ 80028a2: 697a ldr r2, [r7, #20]
+ 80028a4: 4313 orrs r3, r2
+ 80028a6: 617b str r3, [r7, #20]
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 80028a8: 693b ldr r3, [r7, #16]
+ 80028aa: f023 03a0 bic.w r3, r3, #160 ; 0xa0
+ 80028ae: 613b str r3, [r7, #16]
+ tmpccer |= (TIM_ICPolarity << 4U);
+ 80028b0: 68bb ldr r3, [r7, #8]
+ 80028b2: 011b lsls r3, r3, #4
+ 80028b4: 693a ldr r2, [r7, #16]
+ 80028b6: 4313 orrs r3, r2
+ 80028b8: 613b str r3, [r7, #16]
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ 80028ba: 68fb ldr r3, [r7, #12]
+ 80028bc: 697a ldr r2, [r7, #20]
+ 80028be: 619a str r2, [r3, #24]
+ TIMx->CCER = tmpccer;
+ 80028c0: 68fb ldr r3, [r7, #12]
+ 80028c2: 693a ldr r2, [r7, #16]
+ 80028c4: 621a str r2, [r3, #32]
+}
+ 80028c6: bf00 nop
+ 80028c8: 371c adds r7, #28
+ 80028ca: 46bd mov sp, r7
+ 80028cc: f85d 7b04 ldr.w r7, [sp], #4
+ 80028d0: 4770 bx lr
+
+080028d2 <TIM_ITRx_SetConfig>:
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ 80028d2: b480 push {r7}
+ 80028d4: b085 sub sp, #20
+ 80028d6: af00 add r7, sp, #0
+ 80028d8: 6078 str r0, [r7, #4]
+ 80028da: 6039 str r1, [r7, #0]
+ uint32_t tmpsmcr;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ 80028dc: 687b ldr r3, [r7, #4]
+ 80028de: 689b ldr r3, [r3, #8]
+ 80028e0: 60fb str r3, [r7, #12]
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ 80028e2: 68fb ldr r3, [r7, #12]
+ 80028e4: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 80028e8: 60fb str r3, [r7, #12]
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 80028ea: 683a ldr r2, [r7, #0]
+ 80028ec: 68fb ldr r3, [r7, #12]
+ 80028ee: 4313 orrs r3, r2
+ 80028f0: f043 0307 orr.w r3, r3, #7
+ 80028f4: 60fb str r3, [r7, #12]
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+ 80028f6: 687b ldr r3, [r7, #4]
+ 80028f8: 68fa ldr r2, [r7, #12]
+ 80028fa: 609a str r2, [r3, #8]
+}
+ 80028fc: bf00 nop
+ 80028fe: 3714 adds r7, #20
+ 8002900: 46bd mov sp, r7
+ 8002902: f85d 7b04 ldr.w r7, [sp], #4
+ 8002906: 4770 bx lr
+
+08002908 <TIM_ETR_SetConfig>:
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ 8002908: b480 push {r7}
+ 800290a: b087 sub sp, #28
+ 800290c: af00 add r7, sp, #0
+ 800290e: 60f8 str r0, [r7, #12]
+ 8002910: 60b9 str r1, [r7, #8]
+ 8002912: 607a str r2, [r7, #4]
+ 8002914: 603b str r3, [r7, #0]
+ uint32_t tmpsmcr;
+
+ tmpsmcr = TIMx->SMCR;
+ 8002916: 68fb ldr r3, [r7, #12]
+ 8002918: 689b ldr r3, [r3, #8]
+ 800291a: 617b str r3, [r7, #20]
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 800291c: 697b ldr r3, [r7, #20]
+ 800291e: f423 437f bic.w r3, r3, #65280 ; 0xff00
+ 8002922: 617b str r3, [r7, #20]
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 8002924: 683b ldr r3, [r7, #0]
+ 8002926: 021a lsls r2, r3, #8
+ 8002928: 687b ldr r3, [r7, #4]
+ 800292a: 431a orrs r2, r3
+ 800292c: 68bb ldr r3, [r7, #8]
+ 800292e: 4313 orrs r3, r2
+ 8002930: 697a ldr r2, [r7, #20]
+ 8002932: 4313 orrs r3, r2
+ 8002934: 617b str r3, [r7, #20]
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+ 8002936: 68fb ldr r3, [r7, #12]
+ 8002938: 697a ldr r2, [r7, #20]
+ 800293a: 609a str r2, [r3, #8]
+}
+ 800293c: bf00 nop
+ 800293e: 371c adds r7, #28
+ 8002940: 46bd mov sp, r7
+ 8002942: f85d 7b04 ldr.w r7, [sp], #4
+ 8002946: 4770 bx lr
+
+08002948 <HAL_TIMEx_MasterConfigSynchronization>:
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ 8002948: b480 push {r7}
+ 800294a: b085 sub sp, #20
+ 800294c: af00 add r7, sp, #0
+ 800294e: 6078 str r0, [r7, #4]
+ 8002950: 6039 str r1, [r7, #0]
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+ 8002952: 687b ldr r3, [r7, #4]
+ 8002954: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 8002958: 2b01 cmp r3, #1
+ 800295a: d101 bne.n 8002960 <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 800295c: 2302 movs r3, #2
+ 800295e: e045 b.n 80029ec <HAL_TIMEx_MasterConfigSynchronization+0xa4>
+ 8002960: 687b ldr r3, [r7, #4]
+ 8002962: 2201 movs r2, #1
+ 8002964: f883 203c strb.w r2, [r3, #60] ; 0x3c
+
+ /* Change the handler state */
+ htim->State = HAL_TIM_STATE_BUSY;
+ 8002968: 687b ldr r3, [r7, #4]
+ 800296a: 2202 movs r2, #2
+ 800296c: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+ 8002970: 687b ldr r3, [r7, #4]
+ 8002972: 681b ldr r3, [r3, #0]
+ 8002974: 685b ldr r3, [r3, #4]
+ 8002976: 60fb str r3, [r7, #12]
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ 8002978: 687b ldr r3, [r7, #4]
+ 800297a: 681b ldr r3, [r3, #0]
+ 800297c: 689b ldr r3, [r3, #8]
+ 800297e: 60bb str r3, [r7, #8]
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ 8002980: 687b ldr r3, [r7, #4]
+ 8002982: 681b ldr r3, [r3, #0]
+ 8002984: 4a1c ldr r2, [pc, #112] ; (80029f8 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
+ 8002986: 4293 cmp r3, r2
+ 8002988: d004 beq.n 8002994 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
+ 800298a: 687b ldr r3, [r7, #4]
+ 800298c: 681b ldr r3, [r3, #0]
+ 800298e: 4a1b ldr r2, [pc, #108] ; (80029fc <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
+ 8002990: 4293 cmp r3, r2
+ 8002992: d108 bne.n 80029a6 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ 8002994: 68fb ldr r3, [r7, #12]
+ 8002996: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
+ 800299a: 60fb str r3, [r7, #12]
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ 800299c: 683b ldr r3, [r7, #0]
+ 800299e: 685b ldr r3, [r3, #4]
+ 80029a0: 68fa ldr r2, [r7, #12]
+ 80029a2: 4313 orrs r3, r2
+ 80029a4: 60fb str r3, [r7, #12]
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ 80029a6: 68fb ldr r3, [r7, #12]
+ 80029a8: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 80029ac: 60fb str r3, [r7, #12]
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+ 80029ae: 683b ldr r3, [r7, #0]
+ 80029b0: 681b ldr r3, [r3, #0]
+ 80029b2: 68fa ldr r2, [r7, #12]
+ 80029b4: 4313 orrs r3, r2
+ 80029b6: 60fb str r3, [r7, #12]
+
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ 80029b8: 68bb ldr r3, [r7, #8]
+ 80029ba: f023 0380 bic.w r3, r3, #128 ; 0x80
+ 80029be: 60bb str r3, [r7, #8]
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+ 80029c0: 683b ldr r3, [r7, #0]
+ 80029c2: 689b ldr r3, [r3, #8]
+ 80029c4: 68ba ldr r2, [r7, #8]
+ 80029c6: 4313 orrs r3, r2
+ 80029c8: 60bb str r3, [r7, #8]
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+ 80029ca: 687b ldr r3, [r7, #4]
+ 80029cc: 681b ldr r3, [r3, #0]
+ 80029ce: 68fa ldr r2, [r7, #12]
+ 80029d0: 605a str r2, [r3, #4]
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ 80029d2: 687b ldr r3, [r7, #4]
+ 80029d4: 681b ldr r3, [r3, #0]
+ 80029d6: 68ba ldr r2, [r7, #8]
+ 80029d8: 609a str r2, [r3, #8]
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+ 80029da: 687b ldr r3, [r7, #4]
+ 80029dc: 2201 movs r2, #1
+ 80029de: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
+ __HAL_UNLOCK(htim);
+ 80029e2: 687b ldr r3, [r7, #4]
+ 80029e4: 2200 movs r2, #0
+ 80029e6: f883 203c strb.w r2, [r3, #60] ; 0x3c
+
+ return HAL_OK;
+ 80029ea: 2300 movs r3, #0
+}
+ 80029ec: 4618 mov r0, r3
+ 80029ee: 3714 adds r7, #20
+ 80029f0: 46bd mov sp, r7
+ 80029f2: f85d 7b04 ldr.w r7, [sp], #4
+ 80029f6: 4770 bx lr
+ 80029f8: 40010000 .word 0x40010000
+ 80029fc: 40010400 .word 0x40010400
+
+08002a00 <HAL_TIMEx_CommutCallback>:
+ * @brief Hall commutation changed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+ 8002a00: b480 push {r7}
+ 8002a02: b083 sub sp, #12
+ 8002a04: af00 add r7, sp, #0
+ 8002a06: 6078 str r0, [r7, #4]
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+ 8002a08: bf00 nop
+ 8002a0a: 370c adds r7, #12
+ 8002a0c: 46bd mov sp, r7
+ 8002a0e: f85d 7b04 ldr.w r7, [sp], #4
+ 8002a12: 4770 bx lr
+
+08002a14 <HAL_TIMEx_BreakCallback>:
+ * @brief Hall Break detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ 8002a14: b480 push {r7}
+ 8002a16: b083 sub sp, #12
+ 8002a18: af00 add r7, sp, #0
+ 8002a1a: 6078 str r0, [r7, #4]
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+ 8002a1c: bf00 nop
+ 8002a1e: 370c adds r7, #12
+ 8002a20: 46bd mov sp, r7
+ 8002a22: f85d 7b04 ldr.w r7, [sp], #4
+ 8002a26: 4770 bx lr
+
+08002a28 <HAL_TIMEx_Break2Callback>:
+ * @brief Hall Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ 8002a28: b480 push {r7}
+ 8002a2a: b083 sub sp, #12
+ 8002a2c: af00 add r7, sp, #0
+ 8002a2e: 6078 str r0, [r7, #4]
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
+ 8002a30: bf00 nop
+ 8002a32: 370c adds r7, #12
+ 8002a34: 46bd mov sp, r7
+ 8002a36: f85d 7b04 ldr.w r7, [sp], #4
+ 8002a3a: 4770 bx lr
+
+08002a3c <HAL_UART_Init>:
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ 8002a3c: b580 push {r7, lr}
+ 8002a3e: b082 sub sp, #8
+ 8002a40: af00 add r7, sp, #0
+ 8002a42: 6078 str r0, [r7, #4]
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ 8002a44: 687b ldr r3, [r7, #4]
+ 8002a46: 2b00 cmp r3, #0
+ 8002a48: d101 bne.n 8002a4e <HAL_UART_Init+0x12>
+ {
+ return HAL_ERROR;
+ 8002a4a: 2301 movs r3, #1
+ 8002a4c: e040 b.n 8002ad0 <HAL_UART_Init+0x94>
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ 8002a4e: 687b ldr r3, [r7, #4]
+ 8002a50: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8002a52: 2b00 cmp r3, #0
+ 8002a54: d106 bne.n 8002a64 <HAL_UART_Init+0x28>
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+ 8002a56: 687b ldr r3, [r7, #4]
+ 8002a58: 2200 movs r2, #0
+ 8002a5a: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ 8002a5e: 6878 ldr r0, [r7, #4]
+ 8002a60: f7fd ff52 bl 8000908 <HAL_UART_MspInit>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+ 8002a64: 687b ldr r3, [r7, #4]
+ 8002a66: 2224 movs r2, #36 ; 0x24
+ 8002a68: 675a str r2, [r3, #116] ; 0x74
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+ 8002a6a: 687b ldr r3, [r7, #4]
+ 8002a6c: 681b ldr r3, [r3, #0]
+ 8002a6e: 681a ldr r2, [r3, #0]
+ 8002a70: 687b ldr r3, [r7, #4]
+ 8002a72: 681b ldr r3, [r3, #0]
+ 8002a74: f022 0201 bic.w r2, r2, #1
+ 8002a78: 601a str r2, [r3, #0]
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ 8002a7a: 6878 ldr r0, [r7, #4]
+ 8002a7c: f000 fa86 bl 8002f8c <UART_SetConfig>
+ 8002a80: 4603 mov r3, r0
+ 8002a82: 2b01 cmp r3, #1
+ 8002a84: d101 bne.n 8002a8a <HAL_UART_Init+0x4e>
+ {
+ return HAL_ERROR;
+ 8002a86: 2301 movs r3, #1
+ 8002a88: e022 b.n 8002ad0 <HAL_UART_Init+0x94>
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 8002a8a: 687b ldr r3, [r7, #4]
+ 8002a8c: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8002a8e: 2b00 cmp r3, #0
+ 8002a90: d002 beq.n 8002a98 <HAL_UART_Init+0x5c>
+ {
+ UART_AdvFeatureConfig(huart);
+ 8002a92: 6878 ldr r0, [r7, #4]
+ 8002a94: f000 fd1e bl 80034d4 <UART_AdvFeatureConfig>
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 8002a98: 687b ldr r3, [r7, #4]
+ 8002a9a: 681b ldr r3, [r3, #0]
+ 8002a9c: 685a ldr r2, [r3, #4]
+ 8002a9e: 687b ldr r3, [r7, #4]
+ 8002aa0: 681b ldr r3, [r3, #0]
+ 8002aa2: f422 4290 bic.w r2, r2, #18432 ; 0x4800
+ 8002aa6: 605a str r2, [r3, #4]
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 8002aa8: 687b ldr r3, [r7, #4]
+ 8002aaa: 681b ldr r3, [r3, #0]
+ 8002aac: 689a ldr r2, [r3, #8]
+ 8002aae: 687b ldr r3, [r7, #4]
+ 8002ab0: 681b ldr r3, [r3, #0]
+ 8002ab2: f022 022a bic.w r2, r2, #42 ; 0x2a
+ 8002ab6: 609a str r2, [r3, #8]
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+ 8002ab8: 687b ldr r3, [r7, #4]
+ 8002aba: 681b ldr r3, [r3, #0]
+ 8002abc: 681a ldr r2, [r3, #0]
+ 8002abe: 687b ldr r3, [r7, #4]
+ 8002ac0: 681b ldr r3, [r3, #0]
+ 8002ac2: f042 0201 orr.w r2, r2, #1
+ 8002ac6: 601a str r2, [r3, #0]
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+ 8002ac8: 6878 ldr r0, [r7, #4]
+ 8002aca: f000 fda5 bl 8003618 <UART_CheckIdleState>
+ 8002ace: 4603 mov r3, r0
+}
+ 8002ad0: 4618 mov r0, r3
+ 8002ad2: 3708 adds r7, #8
+ 8002ad4: 46bd mov sp, r7
+ 8002ad6: bd80 pop {r7, pc}
+
+08002ad8 <HAL_UART_Transmit>:
+ * @param Size Amount of data to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ 8002ad8: b580 push {r7, lr}
+ 8002ada: b08a sub sp, #40 ; 0x28
+ 8002adc: af02 add r7, sp, #8
+ 8002ade: 60f8 str r0, [r7, #12]
+ 8002ae0: 60b9 str r1, [r7, #8]
+ 8002ae2: 603b str r3, [r7, #0]
+ 8002ae4: 4613 mov r3, r2
+ 8002ae6: 80fb strh r3, [r7, #6]
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
+
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ 8002ae8: 68fb ldr r3, [r7, #12]
+ 8002aea: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8002aec: 2b20 cmp r3, #32
+ 8002aee: d17f bne.n 8002bf0 <HAL_UART_Transmit+0x118>
+ {
+ if ((pData == NULL) || (Size == 0U))
+ 8002af0: 68bb ldr r3, [r7, #8]
+ 8002af2: 2b00 cmp r3, #0
+ 8002af4: d002 beq.n 8002afc <HAL_UART_Transmit+0x24>
+ 8002af6: 88fb ldrh r3, [r7, #6]
+ 8002af8: 2b00 cmp r3, #0
+ 8002afa: d101 bne.n 8002b00 <HAL_UART_Transmit+0x28>
+ {
+ return HAL_ERROR;
+ 8002afc: 2301 movs r3, #1
+ 8002afe: e078 b.n 8002bf2 <HAL_UART_Transmit+0x11a>
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ 8002b00: 68fb ldr r3, [r7, #12]
+ 8002b02: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
+ 8002b06: 2b01 cmp r3, #1
+ 8002b08: d101 bne.n 8002b0e <HAL_UART_Transmit+0x36>
+ 8002b0a: 2302 movs r3, #2
+ 8002b0c: e071 b.n 8002bf2 <HAL_UART_Transmit+0x11a>
+ 8002b0e: 68fb ldr r3, [r7, #12]
+ 8002b10: 2201 movs r2, #1
+ 8002b12: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8002b16: 68fb ldr r3, [r7, #12]
+ 8002b18: 2200 movs r2, #0
+ 8002b1a: 67da str r2, [r3, #124] ; 0x7c
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+ 8002b1c: 68fb ldr r3, [r7, #12]
+ 8002b1e: 2221 movs r2, #33 ; 0x21
+ 8002b20: 675a str r2, [r3, #116] ; 0x74
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+ 8002b22: f7fe f82f bl 8000b84 <HAL_GetTick>
+ 8002b26: 6178 str r0, [r7, #20]
+
+ huart->TxXferSize = Size;
+ 8002b28: 68fb ldr r3, [r7, #12]
+ 8002b2a: 88fa ldrh r2, [r7, #6]
+ 8002b2c: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
+ huart->TxXferCount = Size;
+ 8002b30: 68fb ldr r3, [r7, #12]
+ 8002b32: 88fa ldrh r2, [r7, #6]
+ 8002b34: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 8002b38: 68fb ldr r3, [r7, #12]
+ 8002b3a: 689b ldr r3, [r3, #8]
+ 8002b3c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8002b40: d108 bne.n 8002b54 <HAL_UART_Transmit+0x7c>
+ 8002b42: 68fb ldr r3, [r7, #12]
+ 8002b44: 691b ldr r3, [r3, #16]
+ 8002b46: 2b00 cmp r3, #0
+ 8002b48: d104 bne.n 8002b54 <HAL_UART_Transmit+0x7c>
+ {
+ pdata8bits = NULL;
+ 8002b4a: 2300 movs r3, #0
+ 8002b4c: 61fb str r3, [r7, #28]
+ pdata16bits = (uint16_t *) pData;
+ 8002b4e: 68bb ldr r3, [r7, #8]
+ 8002b50: 61bb str r3, [r7, #24]
+ 8002b52: e003 b.n 8002b5c <HAL_UART_Transmit+0x84>
+ }
+ else
+ {
+ pdata8bits = pData;
+ 8002b54: 68bb ldr r3, [r7, #8]
+ 8002b56: 61fb str r3, [r7, #28]
+ pdata16bits = NULL;
+ 8002b58: 2300 movs r3, #0
+ 8002b5a: 61bb str r3, [r7, #24]
+ }
+
+ while (huart->TxXferCount > 0U)
+ 8002b5c: e02c b.n 8002bb8 <HAL_UART_Transmit+0xe0>
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 8002b5e: 683b ldr r3, [r7, #0]
+ 8002b60: 9300 str r3, [sp, #0]
+ 8002b62: 697b ldr r3, [r7, #20]
+ 8002b64: 2200 movs r2, #0
+ 8002b66: 2180 movs r1, #128 ; 0x80
+ 8002b68: 68f8 ldr r0, [r7, #12]
+ 8002b6a: f000 fd84 bl 8003676 <UART_WaitOnFlagUntilTimeout>
+ 8002b6e: 4603 mov r3, r0
+ 8002b70: 2b00 cmp r3, #0
+ 8002b72: d001 beq.n 8002b78 <HAL_UART_Transmit+0xa0>
+ {
+ return HAL_TIMEOUT;
+ 8002b74: 2303 movs r3, #3
+ 8002b76: e03c b.n 8002bf2 <HAL_UART_Transmit+0x11a>
+ }
+ if (pdata8bits == NULL)
+ 8002b78: 69fb ldr r3, [r7, #28]
+ 8002b7a: 2b00 cmp r3, #0
+ 8002b7c: d10b bne.n 8002b96 <HAL_UART_Transmit+0xbe>
+ {
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ 8002b7e: 69bb ldr r3, [r7, #24]
+ 8002b80: 881b ldrh r3, [r3, #0]
+ 8002b82: 461a mov r2, r3
+ 8002b84: 68fb ldr r3, [r7, #12]
+ 8002b86: 681b ldr r3, [r3, #0]
+ 8002b88: f3c2 0208 ubfx r2, r2, #0, #9
+ 8002b8c: 629a str r2, [r3, #40] ; 0x28
+ pdata16bits++;
+ 8002b8e: 69bb ldr r3, [r7, #24]
+ 8002b90: 3302 adds r3, #2
+ 8002b92: 61bb str r3, [r7, #24]
+ 8002b94: e007 b.n 8002ba6 <HAL_UART_Transmit+0xce>
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ 8002b96: 69fb ldr r3, [r7, #28]
+ 8002b98: 781a ldrb r2, [r3, #0]
+ 8002b9a: 68fb ldr r3, [r7, #12]
+ 8002b9c: 681b ldr r3, [r3, #0]
+ 8002b9e: 629a str r2, [r3, #40] ; 0x28
+ pdata8bits++;
+ 8002ba0: 69fb ldr r3, [r7, #28]
+ 8002ba2: 3301 adds r3, #1
+ 8002ba4: 61fb str r3, [r7, #28]
+ }
+ huart->TxXferCount--;
+ 8002ba6: 68fb ldr r3, [r7, #12]
+ 8002ba8: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
+ 8002bac: b29b uxth r3, r3
+ 8002bae: 3b01 subs r3, #1
+ 8002bb0: b29a uxth r2, r3
+ 8002bb2: 68fb ldr r3, [r7, #12]
+ 8002bb4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+ while (huart->TxXferCount > 0U)
+ 8002bb8: 68fb ldr r3, [r7, #12]
+ 8002bba: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
+ 8002bbe: b29b uxth r3, r3
+ 8002bc0: 2b00 cmp r3, #0
+ 8002bc2: d1cc bne.n 8002b5e <HAL_UART_Transmit+0x86>
+ }
+
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ 8002bc4: 683b ldr r3, [r7, #0]
+ 8002bc6: 9300 str r3, [sp, #0]
+ 8002bc8: 697b ldr r3, [r7, #20]
+ 8002bca: 2200 movs r2, #0
+ 8002bcc: 2140 movs r1, #64 ; 0x40
+ 8002bce: 68f8 ldr r0, [r7, #12]
+ 8002bd0: f000 fd51 bl 8003676 <UART_WaitOnFlagUntilTimeout>
+ 8002bd4: 4603 mov r3, r0
+ 8002bd6: 2b00 cmp r3, #0
+ 8002bd8: d001 beq.n 8002bde <HAL_UART_Transmit+0x106>
+ {
+ return HAL_TIMEOUT;
+ 8002bda: 2303 movs r3, #3
+ 8002bdc: e009 b.n 8002bf2 <HAL_UART_Transmit+0x11a>
+ }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ 8002bde: 68fb ldr r3, [r7, #12]
+ 8002be0: 2220 movs r2, #32
+ 8002be2: 675a str r2, [r3, #116] ; 0x74
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ 8002be4: 68fb ldr r3, [r7, #12]
+ 8002be6: 2200 movs r2, #0
+ 8002be8: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ return HAL_OK;
+ 8002bec: 2300 movs r3, #0
+ 8002bee: e000 b.n 8002bf2 <HAL_UART_Transmit+0x11a>
+ }
+ else
+ {
+ return HAL_BUSY;
+ 8002bf0: 2302 movs r3, #2
+ }
+}
+ 8002bf2: 4618 mov r0, r3
+ 8002bf4: 3720 adds r7, #32
+ 8002bf6: 46bd mov sp, r7
+ 8002bf8: bd80 pop {r7, pc}
+ ...
+
+08002bfc <HAL_UART_Receive_IT>:
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ 8002bfc: b480 push {r7}
+ 8002bfe: b085 sub sp, #20
+ 8002c00: af00 add r7, sp, #0
+ 8002c02: 60f8 str r0, [r7, #12]
+ 8002c04: 60b9 str r1, [r7, #8]
+ 8002c06: 4613 mov r3, r2
+ 8002c08: 80fb strh r3, [r7, #6]
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ 8002c0a: 68fb ldr r3, [r7, #12]
+ 8002c0c: 6f9b ldr r3, [r3, #120] ; 0x78
+ 8002c0e: 2b20 cmp r3, #32
+ 8002c10: f040 808a bne.w 8002d28 <HAL_UART_Receive_IT+0x12c>
+ {
+ if ((pData == NULL) || (Size == 0U))
+ 8002c14: 68bb ldr r3, [r7, #8]
+ 8002c16: 2b00 cmp r3, #0
+ 8002c18: d002 beq.n 8002c20 <HAL_UART_Receive_IT+0x24>
+ 8002c1a: 88fb ldrh r3, [r7, #6]
+ 8002c1c: 2b00 cmp r3, #0
+ 8002c1e: d101 bne.n 8002c24 <HAL_UART_Receive_IT+0x28>
+ {
+ return HAL_ERROR;
+ 8002c20: 2301 movs r3, #1
+ 8002c22: e082 b.n 8002d2a <HAL_UART_Receive_IT+0x12e>
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ 8002c24: 68fb ldr r3, [r7, #12]
+ 8002c26: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
+ 8002c2a: 2b01 cmp r3, #1
+ 8002c2c: d101 bne.n 8002c32 <HAL_UART_Receive_IT+0x36>
+ 8002c2e: 2302 movs r3, #2
+ 8002c30: e07b b.n 8002d2a <HAL_UART_Receive_IT+0x12e>
+ 8002c32: 68fb ldr r3, [r7, #12]
+ 8002c34: 2201 movs r2, #1
+ 8002c36: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ huart->pRxBuffPtr = pData;
+ 8002c3a: 68fb ldr r3, [r7, #12]
+ 8002c3c: 68ba ldr r2, [r7, #8]
+ 8002c3e: 655a str r2, [r3, #84] ; 0x54
+ huart->RxXferSize = Size;
+ 8002c40: 68fb ldr r3, [r7, #12]
+ 8002c42: 88fa ldrh r2, [r7, #6]
+ 8002c44: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
+ huart->RxXferCount = Size;
+ 8002c48: 68fb ldr r3, [r7, #12]
+ 8002c4a: 88fa ldrh r2, [r7, #6]
+ 8002c4c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+ huart->RxISR = NULL;
+ 8002c50: 68fb ldr r3, [r7, #12]
+ 8002c52: 2200 movs r2, #0
+ 8002c54: 661a str r2, [r3, #96] ; 0x60
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ 8002c56: 68fb ldr r3, [r7, #12]
+ 8002c58: 689b ldr r3, [r3, #8]
+ 8002c5a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8002c5e: d10e bne.n 8002c7e <HAL_UART_Receive_IT+0x82>
+ 8002c60: 68fb ldr r3, [r7, #12]
+ 8002c62: 691b ldr r3, [r3, #16]
+ 8002c64: 2b00 cmp r3, #0
+ 8002c66: d105 bne.n 8002c74 <HAL_UART_Receive_IT+0x78>
+ 8002c68: 68fb ldr r3, [r7, #12]
+ 8002c6a: f240 12ff movw r2, #511 ; 0x1ff
+ 8002c6e: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 8002c72: e02d b.n 8002cd0 <HAL_UART_Receive_IT+0xd4>
+ 8002c74: 68fb ldr r3, [r7, #12]
+ 8002c76: 22ff movs r2, #255 ; 0xff
+ 8002c78: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 8002c7c: e028 b.n 8002cd0 <HAL_UART_Receive_IT+0xd4>
+ 8002c7e: 68fb ldr r3, [r7, #12]
+ 8002c80: 689b ldr r3, [r3, #8]
+ 8002c82: 2b00 cmp r3, #0
+ 8002c84: d10d bne.n 8002ca2 <HAL_UART_Receive_IT+0xa6>
+ 8002c86: 68fb ldr r3, [r7, #12]
+ 8002c88: 691b ldr r3, [r3, #16]
+ 8002c8a: 2b00 cmp r3, #0
+ 8002c8c: d104 bne.n 8002c98 <HAL_UART_Receive_IT+0x9c>
+ 8002c8e: 68fb ldr r3, [r7, #12]
+ 8002c90: 22ff movs r2, #255 ; 0xff
+ 8002c92: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 8002c96: e01b b.n 8002cd0 <HAL_UART_Receive_IT+0xd4>
+ 8002c98: 68fb ldr r3, [r7, #12]
+ 8002c9a: 227f movs r2, #127 ; 0x7f
+ 8002c9c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 8002ca0: e016 b.n 8002cd0 <HAL_UART_Receive_IT+0xd4>
+ 8002ca2: 68fb ldr r3, [r7, #12]
+ 8002ca4: 689b ldr r3, [r3, #8]
+ 8002ca6: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
+ 8002caa: d10d bne.n 8002cc8 <HAL_UART_Receive_IT+0xcc>
+ 8002cac: 68fb ldr r3, [r7, #12]
+ 8002cae: 691b ldr r3, [r3, #16]
+ 8002cb0: 2b00 cmp r3, #0
+ 8002cb2: d104 bne.n 8002cbe <HAL_UART_Receive_IT+0xc2>
+ 8002cb4: 68fb ldr r3, [r7, #12]
+ 8002cb6: 227f movs r2, #127 ; 0x7f
+ 8002cb8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 8002cbc: e008 b.n 8002cd0 <HAL_UART_Receive_IT+0xd4>
+ 8002cbe: 68fb ldr r3, [r7, #12]
+ 8002cc0: 223f movs r2, #63 ; 0x3f
+ 8002cc2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+ 8002cc6: e003 b.n 8002cd0 <HAL_UART_Receive_IT+0xd4>
+ 8002cc8: 68fb ldr r3, [r7, #12]
+ 8002cca: 2200 movs r2, #0
+ 8002ccc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8002cd0: 68fb ldr r3, [r7, #12]
+ 8002cd2: 2200 movs r2, #0
+ 8002cd4: 67da str r2, [r3, #124] ; 0x7c
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 8002cd6: 68fb ldr r3, [r7, #12]
+ 8002cd8: 2222 movs r2, #34 ; 0x22
+ 8002cda: 679a str r2, [r3, #120] ; 0x78
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8002cdc: 68fb ldr r3, [r7, #12]
+ 8002cde: 681b ldr r3, [r3, #0]
+ 8002ce0: 689a ldr r2, [r3, #8]
+ 8002ce2: 68fb ldr r3, [r7, #12]
+ 8002ce4: 681b ldr r3, [r3, #0]
+ 8002ce6: f042 0201 orr.w r2, r2, #1
+ 8002cea: 609a str r2, [r3, #8]
+
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 8002cec: 68fb ldr r3, [r7, #12]
+ 8002cee: 689b ldr r3, [r3, #8]
+ 8002cf0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8002cf4: d107 bne.n 8002d06 <HAL_UART_Receive_IT+0x10a>
+ 8002cf6: 68fb ldr r3, [r7, #12]
+ 8002cf8: 691b ldr r3, [r3, #16]
+ 8002cfa: 2b00 cmp r3, #0
+ 8002cfc: d103 bne.n 8002d06 <HAL_UART_Receive_IT+0x10a>
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ 8002cfe: 68fb ldr r3, [r7, #12]
+ 8002d00: 4a0d ldr r2, [pc, #52] ; (8002d38 <HAL_UART_Receive_IT+0x13c>)
+ 8002d02: 661a str r2, [r3, #96] ; 0x60
+ 8002d04: e002 b.n 8002d0c <HAL_UART_Receive_IT+0x110>
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ 8002d06: 68fb ldr r3, [r7, #12]
+ 8002d08: 4a0c ldr r2, [pc, #48] ; (8002d3c <HAL_UART_Receive_IT+0x140>)
+ 8002d0a: 661a str r2, [r3, #96] ; 0x60
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ 8002d0c: 68fb ldr r3, [r7, #12]
+ 8002d0e: 2200 movs r2, #0
+ 8002d10: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ 8002d14: 68fb ldr r3, [r7, #12]
+ 8002d16: 681b ldr r3, [r3, #0]
+ 8002d18: 681a ldr r2, [r3, #0]
+ 8002d1a: 68fb ldr r3, [r7, #12]
+ 8002d1c: 681b ldr r3, [r3, #0]
+ 8002d1e: f442 7290 orr.w r2, r2, #288 ; 0x120
+ 8002d22: 601a str r2, [r3, #0]
+
+ return HAL_OK;
+ 8002d24: 2300 movs r3, #0
+ 8002d26: e000 b.n 8002d2a <HAL_UART_Receive_IT+0x12e>
+ }
+ else
+ {
+ return HAL_BUSY;
+ 8002d28: 2302 movs r3, #2
+ }
+}
+ 8002d2a: 4618 mov r0, r3
+ 8002d2c: 3714 adds r7, #20
+ 8002d2e: 46bd mov sp, r7
+ 8002d30: f85d 7b04 ldr.w r7, [sp], #4
+ 8002d34: 4770 bx lr
+ 8002d36: bf00 nop
+ 8002d38: 0800384b .word 0x0800384b
+ 8002d3c: 080037a5 .word 0x080037a5
+
+08002d40 <HAL_UART_IRQHandler>:
+ * @brief Handle UART interrupt request.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ 8002d40: b580 push {r7, lr}
+ 8002d42: b088 sub sp, #32
+ 8002d44: af00 add r7, sp, #0
+ 8002d46: 6078 str r0, [r7, #4]
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ 8002d48: 687b ldr r3, [r7, #4]
+ 8002d4a: 681b ldr r3, [r3, #0]
+ 8002d4c: 69db ldr r3, [r3, #28]
+ 8002d4e: 61fb str r3, [r7, #28]
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ 8002d50: 687b ldr r3, [r7, #4]
+ 8002d52: 681b ldr r3, [r3, #0]
+ 8002d54: 681b ldr r3, [r3, #0]
+ 8002d56: 61bb str r3, [r7, #24]
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+ 8002d58: 687b ldr r3, [r7, #4]
+ 8002d5a: 681b ldr r3, [r3, #0]
+ 8002d5c: 689b ldr r3, [r3, #8]
+ 8002d5e: 617b str r3, [r7, #20]
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ 8002d60: 69fb ldr r3, [r7, #28]
+ 8002d62: f003 030f and.w r3, r3, #15
+ 8002d66: 613b str r3, [r7, #16]
+ if (errorflags == 0U)
+ 8002d68: 693b ldr r3, [r7, #16]
+ 8002d6a: 2b00 cmp r3, #0
+ 8002d6c: d113 bne.n 8002d96 <HAL_UART_IRQHandler+0x56>
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ 8002d6e: 69fb ldr r3, [r7, #28]
+ 8002d70: f003 0320 and.w r3, r3, #32
+ 8002d74: 2b00 cmp r3, #0
+ 8002d76: d00e beq.n 8002d96 <HAL_UART_IRQHandler+0x56>
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ 8002d78: 69bb ldr r3, [r7, #24]
+ 8002d7a: f003 0320 and.w r3, r3, #32
+ 8002d7e: 2b00 cmp r3, #0
+ 8002d80: d009 beq.n 8002d96 <HAL_UART_IRQHandler+0x56>
+ {
+ if (huart->RxISR != NULL)
+ 8002d82: 687b ldr r3, [r7, #4]
+ 8002d84: 6e1b ldr r3, [r3, #96] ; 0x60
+ 8002d86: 2b00 cmp r3, #0
+ 8002d88: f000 80eb beq.w 8002f62 <HAL_UART_IRQHandler+0x222>
+ {
+ huart->RxISR(huart);
+ 8002d8c: 687b ldr r3, [r7, #4]
+ 8002d8e: 6e1b ldr r3, [r3, #96] ; 0x60
+ 8002d90: 6878 ldr r0, [r7, #4]
+ 8002d92: 4798 blx r3
+ }
+ return;
+ 8002d94: e0e5 b.n 8002f62 <HAL_UART_IRQHandler+0x222>
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ 8002d96: 693b ldr r3, [r7, #16]
+ 8002d98: 2b00 cmp r3, #0
+ 8002d9a: f000 80c0 beq.w 8002f1e <HAL_UART_IRQHandler+0x1de>
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ 8002d9e: 697b ldr r3, [r7, #20]
+ 8002da0: f003 0301 and.w r3, r3, #1
+ 8002da4: 2b00 cmp r3, #0
+ 8002da6: d105 bne.n 8002db4 <HAL_UART_IRQHandler+0x74>
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
+ 8002da8: 69bb ldr r3, [r7, #24]
+ 8002daa: f403 7390 and.w r3, r3, #288 ; 0x120
+ 8002dae: 2b00 cmp r3, #0
+ 8002db0: f000 80b5 beq.w 8002f1e <HAL_UART_IRQHandler+0x1de>
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ 8002db4: 69fb ldr r3, [r7, #28]
+ 8002db6: f003 0301 and.w r3, r3, #1
+ 8002dba: 2b00 cmp r3, #0
+ 8002dbc: d00e beq.n 8002ddc <HAL_UART_IRQHandler+0x9c>
+ 8002dbe: 69bb ldr r3, [r7, #24]
+ 8002dc0: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8002dc4: 2b00 cmp r3, #0
+ 8002dc6: d009 beq.n 8002ddc <HAL_UART_IRQHandler+0x9c>
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+ 8002dc8: 687b ldr r3, [r7, #4]
+ 8002dca: 681b ldr r3, [r3, #0]
+ 8002dcc: 2201 movs r2, #1
+ 8002dce: 621a str r2, [r3, #32]
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ 8002dd0: 687b ldr r3, [r7, #4]
+ 8002dd2: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002dd4: f043 0201 orr.w r2, r3, #1
+ 8002dd8: 687b ldr r3, [r7, #4]
+ 8002dda: 67da str r2, [r3, #124] ; 0x7c
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 8002ddc: 69fb ldr r3, [r7, #28]
+ 8002dde: f003 0302 and.w r3, r3, #2
+ 8002de2: 2b00 cmp r3, #0
+ 8002de4: d00e beq.n 8002e04 <HAL_UART_IRQHandler+0xc4>
+ 8002de6: 697b ldr r3, [r7, #20]
+ 8002de8: f003 0301 and.w r3, r3, #1
+ 8002dec: 2b00 cmp r3, #0
+ 8002dee: d009 beq.n 8002e04 <HAL_UART_IRQHandler+0xc4>
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+ 8002df0: 687b ldr r3, [r7, #4]
+ 8002df2: 681b ldr r3, [r3, #0]
+ 8002df4: 2202 movs r2, #2
+ 8002df6: 621a str r2, [r3, #32]
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ 8002df8: 687b ldr r3, [r7, #4]
+ 8002dfa: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002dfc: f043 0204 orr.w r2, r3, #4
+ 8002e00: 687b ldr r3, [r7, #4]
+ 8002e02: 67da str r2, [r3, #124] ; 0x7c
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 8002e04: 69fb ldr r3, [r7, #28]
+ 8002e06: f003 0304 and.w r3, r3, #4
+ 8002e0a: 2b00 cmp r3, #0
+ 8002e0c: d00e beq.n 8002e2c <HAL_UART_IRQHandler+0xec>
+ 8002e0e: 697b ldr r3, [r7, #20]
+ 8002e10: f003 0301 and.w r3, r3, #1
+ 8002e14: 2b00 cmp r3, #0
+ 8002e16: d009 beq.n 8002e2c <HAL_UART_IRQHandler+0xec>
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+ 8002e18: 687b ldr r3, [r7, #4]
+ 8002e1a: 681b ldr r3, [r3, #0]
+ 8002e1c: 2204 movs r2, #4
+ 8002e1e: 621a str r2, [r3, #32]
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ 8002e20: 687b ldr r3, [r7, #4]
+ 8002e22: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002e24: f043 0202 orr.w r2, r3, #2
+ 8002e28: 687b ldr r3, [r7, #4]
+ 8002e2a: 67da str r2, [r3, #124] ; 0x7c
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ 8002e2c: 69fb ldr r3, [r7, #28]
+ 8002e2e: f003 0308 and.w r3, r3, #8
+ 8002e32: 2b00 cmp r3, #0
+ 8002e34: d013 beq.n 8002e5e <HAL_UART_IRQHandler+0x11e>
+ && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ 8002e36: 69bb ldr r3, [r7, #24]
+ 8002e38: f003 0320 and.w r3, r3, #32
+ 8002e3c: 2b00 cmp r3, #0
+ 8002e3e: d104 bne.n 8002e4a <HAL_UART_IRQHandler+0x10a>
+ ((cr3its & USART_CR3_EIE) != 0U)))
+ 8002e40: 697b ldr r3, [r7, #20]
+ 8002e42: f003 0301 and.w r3, r3, #1
+ && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ 8002e46: 2b00 cmp r3, #0
+ 8002e48: d009 beq.n 8002e5e <HAL_UART_IRQHandler+0x11e>
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ 8002e4a: 687b ldr r3, [r7, #4]
+ 8002e4c: 681b ldr r3, [r3, #0]
+ 8002e4e: 2208 movs r2, #8
+ 8002e50: 621a str r2, [r3, #32]
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ 8002e52: 687b ldr r3, [r7, #4]
+ 8002e54: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002e56: f043 0208 orr.w r2, r3, #8
+ 8002e5a: 687b ldr r3, [r7, #4]
+ 8002e5c: 67da str r2, [r3, #124] ; 0x7c
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ 8002e5e: 687b ldr r3, [r7, #4]
+ 8002e60: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002e62: 2b00 cmp r3, #0
+ 8002e64: d07f beq.n 8002f66 <HAL_UART_IRQHandler+0x226>
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ 8002e66: 69fb ldr r3, [r7, #28]
+ 8002e68: f003 0320 and.w r3, r3, #32
+ 8002e6c: 2b00 cmp r3, #0
+ 8002e6e: d00c beq.n 8002e8a <HAL_UART_IRQHandler+0x14a>
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
+ 8002e70: 69bb ldr r3, [r7, #24]
+ 8002e72: f003 0320 and.w r3, r3, #32
+ 8002e76: 2b00 cmp r3, #0
+ 8002e78: d007 beq.n 8002e8a <HAL_UART_IRQHandler+0x14a>
+ {
+ if (huart->RxISR != NULL)
+ 8002e7a: 687b ldr r3, [r7, #4]
+ 8002e7c: 6e1b ldr r3, [r3, #96] ; 0x60
+ 8002e7e: 2b00 cmp r3, #0
+ 8002e80: d003 beq.n 8002e8a <HAL_UART_IRQHandler+0x14a>
+ {
+ huart->RxISR(huart);
+ 8002e82: 687b ldr r3, [r7, #4]
+ 8002e84: 6e1b ldr r3, [r3, #96] ; 0x60
+ 8002e86: 6878 ldr r0, [r7, #4]
+ 8002e88: 4798 blx r3
+ }
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ errorcode = huart->ErrorCode;
+ 8002e8a: 687b ldr r3, [r7, #4]
+ 8002e8c: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8002e8e: 60fb str r3, [r7, #12]
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 8002e90: 687b ldr r3, [r7, #4]
+ 8002e92: 681b ldr r3, [r3, #0]
+ 8002e94: 689b ldr r3, [r3, #8]
+ 8002e96: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8002e9a: 2b40 cmp r3, #64 ; 0x40
+ 8002e9c: d004 beq.n 8002ea8 <HAL_UART_IRQHandler+0x168>
+ ((errorcode & HAL_UART_ERROR_ORE) != 0U))
+ 8002e9e: 68fb ldr r3, [r7, #12]
+ 8002ea0: f003 0308 and.w r3, r3, #8
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 8002ea4: 2b00 cmp r3, #0
+ 8002ea6: d031 beq.n 8002f0c <HAL_UART_IRQHandler+0x1cc>
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+ 8002ea8: 6878 ldr r0, [r7, #4]
+ 8002eaa: f000 fc2c bl 8003706 <UART_EndRxTransfer>
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8002eae: 687b ldr r3, [r7, #4]
+ 8002eb0: 681b ldr r3, [r3, #0]
+ 8002eb2: 689b ldr r3, [r3, #8]
+ 8002eb4: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8002eb8: 2b40 cmp r3, #64 ; 0x40
+ 8002eba: d123 bne.n 8002f04 <HAL_UART_IRQHandler+0x1c4>
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 8002ebc: 687b ldr r3, [r7, #4]
+ 8002ebe: 681b ldr r3, [r3, #0]
+ 8002ec0: 689a ldr r2, [r3, #8]
+ 8002ec2: 687b ldr r3, [r7, #4]
+ 8002ec4: 681b ldr r3, [r3, #0]
+ 8002ec6: f022 0240 bic.w r2, r2, #64 ; 0x40
+ 8002eca: 609a str r2, [r3, #8]
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ 8002ecc: 687b ldr r3, [r7, #4]
+ 8002ece: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8002ed0: 2b00 cmp r3, #0
+ 8002ed2: d013 beq.n 8002efc <HAL_UART_IRQHandler+0x1bc>
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+ 8002ed4: 687b ldr r3, [r7, #4]
+ 8002ed6: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8002ed8: 4a26 ldr r2, [pc, #152] ; (8002f74 <HAL_UART_IRQHandler+0x234>)
+ 8002eda: 651a str r2, [r3, #80] ; 0x50
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ 8002edc: 687b ldr r3, [r7, #4]
+ 8002ede: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8002ee0: 4618 mov r0, r3
+ 8002ee2: f7fd ff6c bl 8000dbe <HAL_DMA_Abort_IT>
+ 8002ee6: 4603 mov r3, r0
+ 8002ee8: 2b00 cmp r3, #0
+ 8002eea: d016 beq.n 8002f1a <HAL_UART_IRQHandler+0x1da>
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ 8002eec: 687b ldr r3, [r7, #4]
+ 8002eee: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8002ef0: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8002ef2: 687a ldr r2, [r7, #4]
+ 8002ef4: 6ed2 ldr r2, [r2, #108] ; 0x6c
+ 8002ef6: 4610 mov r0, r2
+ 8002ef8: 4798 blx r3
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8002efa: e00e b.n 8002f1a <HAL_UART_IRQHandler+0x1da>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+ 8002efc: 6878 ldr r0, [r7, #4]
+ 8002efe: f7fd fca7 bl 8000850 <HAL_UART_ErrorCallback>
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8002f02: e00a b.n 8002f1a <HAL_UART_IRQHandler+0x1da>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+ 8002f04: 6878 ldr r0, [r7, #4]
+ 8002f06: f7fd fca3 bl 8000850 <HAL_UART_ErrorCallback>
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8002f0a: e006 b.n 8002f1a <HAL_UART_IRQHandler+0x1da>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+ 8002f0c: 6878 ldr r0, [r7, #4]
+ 8002f0e: f7fd fc9f bl 8000850 <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8002f12: 687b ldr r3, [r7, #4]
+ 8002f14: 2200 movs r2, #0
+ 8002f16: 67da str r2, [r3, #124] ; 0x7c
+ }
+ }
+ return;
+ 8002f18: e025 b.n 8002f66 <HAL_UART_IRQHandler+0x226>
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8002f1a: bf00 nop
+ return;
+ 8002f1c: e023 b.n 8002f66 <HAL_UART_IRQHandler+0x226>
+
+ } /* End if some error occurs */
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE) != 0U)
+ 8002f1e: 69fb ldr r3, [r7, #28]
+ 8002f20: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8002f24: 2b00 cmp r3, #0
+ 8002f26: d00d beq.n 8002f44 <HAL_UART_IRQHandler+0x204>
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
+ 8002f28: 69bb ldr r3, [r7, #24]
+ 8002f2a: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8002f2e: 2b00 cmp r3, #0
+ 8002f30: d008 beq.n 8002f44 <HAL_UART_IRQHandler+0x204>
+ {
+ if (huart->TxISR != NULL)
+ 8002f32: 687b ldr r3, [r7, #4]
+ 8002f34: 6e5b ldr r3, [r3, #100] ; 0x64
+ 8002f36: 2b00 cmp r3, #0
+ 8002f38: d017 beq.n 8002f6a <HAL_UART_IRQHandler+0x22a>
+ {
+ huart->TxISR(huart);
+ 8002f3a: 687b ldr r3, [r7, #4]
+ 8002f3c: 6e5b ldr r3, [r3, #100] ; 0x64
+ 8002f3e: 6878 ldr r0, [r7, #4]
+ 8002f40: 4798 blx r3
+ }
+ return;
+ 8002f42: e012 b.n 8002f6a <HAL_UART_IRQHandler+0x22a>
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ 8002f44: 69fb ldr r3, [r7, #28]
+ 8002f46: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8002f4a: 2b00 cmp r3, #0
+ 8002f4c: d00e beq.n 8002f6c <HAL_UART_IRQHandler+0x22c>
+ 8002f4e: 69bb ldr r3, [r7, #24]
+ 8002f50: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8002f54: 2b00 cmp r3, #0
+ 8002f56: d009 beq.n 8002f6c <HAL_UART_IRQHandler+0x22c>
+ {
+ UART_EndTransmit_IT(huart);
+ 8002f58: 6878 ldr r0, [r7, #4]
+ 8002f5a: f000 fc0a bl 8003772 <UART_EndTransmit_IT>
+ return;
+ 8002f5e: bf00 nop
+ 8002f60: e004 b.n 8002f6c <HAL_UART_IRQHandler+0x22c>
+ return;
+ 8002f62: bf00 nop
+ 8002f64: e002 b.n 8002f6c <HAL_UART_IRQHandler+0x22c>
+ return;
+ 8002f66: bf00 nop
+ 8002f68: e000 b.n 8002f6c <HAL_UART_IRQHandler+0x22c>
+ return;
+ 8002f6a: bf00 nop
+ }
+
+}
+ 8002f6c: 3720 adds r7, #32
+ 8002f6e: 46bd mov sp, r7
+ 8002f70: bd80 pop {r7, pc}
+ 8002f72: bf00 nop
+ 8002f74: 08003747 .word 0x08003747
+
+08002f78 <HAL_UART_TxCpltCallback>:
+ * @brief Tx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ 8002f78: b480 push {r7}
+ 8002f7a: b083 sub sp, #12
+ 8002f7c: af00 add r7, sp, #0
+ 8002f7e: 6078 str r0, [r7, #4]
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
+}
+ 8002f80: bf00 nop
+ 8002f82: 370c adds r7, #12
+ 8002f84: 46bd mov sp, r7
+ 8002f86: f85d 7b04 ldr.w r7, [sp], #4
+ 8002f8a: 4770 bx lr
+
+08002f8c <UART_SetConfig>:
+ * @brief Configure the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ 8002f8c: b580 push {r7, lr}
+ 8002f8e: b088 sub sp, #32
+ 8002f90: af00 add r7, sp, #0
+ 8002f92: 6078 str r0, [r7, #4]
+ uint32_t tmpreg;
+ uint16_t brrtemp;
+ UART_ClockSourceTypeDef clocksource;
+ uint32_t usartdiv = 0x00000000U;
+ 8002f94: 2300 movs r3, #0
+ 8002f96: 61bb str r3, [r7, #24]
+ HAL_StatusTypeDef ret = HAL_OK;
+ 8002f98: 2300 movs r3, #0
+ 8002f9a: 75fb strb r3, [r7, #23]
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ 8002f9c: 687b ldr r3, [r7, #4]
+ 8002f9e: 689a ldr r2, [r3, #8]
+ 8002fa0: 687b ldr r3, [r7, #4]
+ 8002fa2: 691b ldr r3, [r3, #16]
+ 8002fa4: 431a orrs r2, r3
+ 8002fa6: 687b ldr r3, [r7, #4]
+ 8002fa8: 695b ldr r3, [r3, #20]
+ 8002faa: 431a orrs r2, r3
+ 8002fac: 687b ldr r3, [r7, #4]
+ 8002fae: 69db ldr r3, [r3, #28]
+ 8002fb0: 4313 orrs r3, r2
+ 8002fb2: 613b str r3, [r7, #16]
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 8002fb4: 687b ldr r3, [r7, #4]
+ 8002fb6: 681b ldr r3, [r3, #0]
+ 8002fb8: 681a ldr r2, [r3, #0]
+ 8002fba: 4bb1 ldr r3, [pc, #708] ; (8003280 <UART_SetConfig+0x2f4>)
+ 8002fbc: 4013 ands r3, r2
+ 8002fbe: 687a ldr r2, [r7, #4]
+ 8002fc0: 6812 ldr r2, [r2, #0]
+ 8002fc2: 6939 ldr r1, [r7, #16]
+ 8002fc4: 430b orrs r3, r1
+ 8002fc6: 6013 str r3, [r2, #0]
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 8002fc8: 687b ldr r3, [r7, #4]
+ 8002fca: 681b ldr r3, [r3, #0]
+ 8002fcc: 685b ldr r3, [r3, #4]
+ 8002fce: f423 5140 bic.w r1, r3, #12288 ; 0x3000
+ 8002fd2: 687b ldr r3, [r7, #4]
+ 8002fd4: 68da ldr r2, [r3, #12]
+ 8002fd6: 687b ldr r3, [r7, #4]
+ 8002fd8: 681b ldr r3, [r3, #0]
+ 8002fda: 430a orrs r2, r1
+ 8002fdc: 605a str r2, [r3, #4]
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+ 8002fde: 687b ldr r3, [r7, #4]
+ 8002fe0: 699b ldr r3, [r3, #24]
+ 8002fe2: 613b str r3, [r7, #16]
+
+ tmpreg |= huart->Init.OneBitSampling;
+ 8002fe4: 687b ldr r3, [r7, #4]
+ 8002fe6: 6a1b ldr r3, [r3, #32]
+ 8002fe8: 693a ldr r2, [r7, #16]
+ 8002fea: 4313 orrs r3, r2
+ 8002fec: 613b str r3, [r7, #16]
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+ 8002fee: 687b ldr r3, [r7, #4]
+ 8002ff0: 681b ldr r3, [r3, #0]
+ 8002ff2: 689b ldr r3, [r3, #8]
+ 8002ff4: f423 6130 bic.w r1, r3, #2816 ; 0xb00
+ 8002ff8: 687b ldr r3, [r7, #4]
+ 8002ffa: 681b ldr r3, [r3, #0]
+ 8002ffc: 693a ldr r2, [r7, #16]
+ 8002ffe: 430a orrs r2, r1
+ 8003000: 609a str r2, [r3, #8]
+
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+ 8003002: 687b ldr r3, [r7, #4]
+ 8003004: 681b ldr r3, [r3, #0]
+ 8003006: 4a9f ldr r2, [pc, #636] ; (8003284 <UART_SetConfig+0x2f8>)
+ 8003008: 4293 cmp r3, r2
+ 800300a: d121 bne.n 8003050 <UART_SetConfig+0xc4>
+ 800300c: 4b9e ldr r3, [pc, #632] ; (8003288 <UART_SetConfig+0x2fc>)
+ 800300e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8003012: f003 0303 and.w r3, r3, #3
+ 8003016: 2b03 cmp r3, #3
+ 8003018: d816 bhi.n 8003048 <UART_SetConfig+0xbc>
+ 800301a: a201 add r2, pc, #4 ; (adr r2, 8003020 <UART_SetConfig+0x94>)
+ 800301c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 8003020: 08003031 .word 0x08003031
+ 8003024: 0800303d .word 0x0800303d
+ 8003028: 08003037 .word 0x08003037
+ 800302c: 08003043 .word 0x08003043
+ 8003030: 2301 movs r3, #1
+ 8003032: 77fb strb r3, [r7, #31]
+ 8003034: e151 b.n 80032da <UART_SetConfig+0x34e>
+ 8003036: 2302 movs r3, #2
+ 8003038: 77fb strb r3, [r7, #31]
+ 800303a: e14e b.n 80032da <UART_SetConfig+0x34e>
+ 800303c: 2304 movs r3, #4
+ 800303e: 77fb strb r3, [r7, #31]
+ 8003040: e14b b.n 80032da <UART_SetConfig+0x34e>
+ 8003042: 2308 movs r3, #8
+ 8003044: 77fb strb r3, [r7, #31]
+ 8003046: e148 b.n 80032da <UART_SetConfig+0x34e>
+ 8003048: 2310 movs r3, #16
+ 800304a: 77fb strb r3, [r7, #31]
+ 800304c: bf00 nop
+ 800304e: e144 b.n 80032da <UART_SetConfig+0x34e>
+ 8003050: 687b ldr r3, [r7, #4]
+ 8003052: 681b ldr r3, [r3, #0]
+ 8003054: 4a8d ldr r2, [pc, #564] ; (800328c <UART_SetConfig+0x300>)
+ 8003056: 4293 cmp r3, r2
+ 8003058: d134 bne.n 80030c4 <UART_SetConfig+0x138>
+ 800305a: 4b8b ldr r3, [pc, #556] ; (8003288 <UART_SetConfig+0x2fc>)
+ 800305c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8003060: f003 030c and.w r3, r3, #12
+ 8003064: 2b0c cmp r3, #12
+ 8003066: d829 bhi.n 80030bc <UART_SetConfig+0x130>
+ 8003068: a201 add r2, pc, #4 ; (adr r2, 8003070 <UART_SetConfig+0xe4>)
+ 800306a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 800306e: bf00 nop
+ 8003070: 080030a5 .word 0x080030a5
+ 8003074: 080030bd .word 0x080030bd
+ 8003078: 080030bd .word 0x080030bd
+ 800307c: 080030bd .word 0x080030bd
+ 8003080: 080030b1 .word 0x080030b1
+ 8003084: 080030bd .word 0x080030bd
+ 8003088: 080030bd .word 0x080030bd
+ 800308c: 080030bd .word 0x080030bd
+ 8003090: 080030ab .word 0x080030ab
+ 8003094: 080030bd .word 0x080030bd
+ 8003098: 080030bd .word 0x080030bd
+ 800309c: 080030bd .word 0x080030bd
+ 80030a0: 080030b7 .word 0x080030b7
+ 80030a4: 2300 movs r3, #0
+ 80030a6: 77fb strb r3, [r7, #31]
+ 80030a8: e117 b.n 80032da <UART_SetConfig+0x34e>
+ 80030aa: 2302 movs r3, #2
+ 80030ac: 77fb strb r3, [r7, #31]
+ 80030ae: e114 b.n 80032da <UART_SetConfig+0x34e>
+ 80030b0: 2304 movs r3, #4
+ 80030b2: 77fb strb r3, [r7, #31]
+ 80030b4: e111 b.n 80032da <UART_SetConfig+0x34e>
+ 80030b6: 2308 movs r3, #8
+ 80030b8: 77fb strb r3, [r7, #31]
+ 80030ba: e10e b.n 80032da <UART_SetConfig+0x34e>
+ 80030bc: 2310 movs r3, #16
+ 80030be: 77fb strb r3, [r7, #31]
+ 80030c0: bf00 nop
+ 80030c2: e10a b.n 80032da <UART_SetConfig+0x34e>
+ 80030c4: 687b ldr r3, [r7, #4]
+ 80030c6: 681b ldr r3, [r3, #0]
+ 80030c8: 4a71 ldr r2, [pc, #452] ; (8003290 <UART_SetConfig+0x304>)
+ 80030ca: 4293 cmp r3, r2
+ 80030cc: d120 bne.n 8003110 <UART_SetConfig+0x184>
+ 80030ce: 4b6e ldr r3, [pc, #440] ; (8003288 <UART_SetConfig+0x2fc>)
+ 80030d0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 80030d4: f003 0330 and.w r3, r3, #48 ; 0x30
+ 80030d8: 2b10 cmp r3, #16
+ 80030da: d00f beq.n 80030fc <UART_SetConfig+0x170>
+ 80030dc: 2b10 cmp r3, #16
+ 80030de: d802 bhi.n 80030e6 <UART_SetConfig+0x15a>
+ 80030e0: 2b00 cmp r3, #0
+ 80030e2: d005 beq.n 80030f0 <UART_SetConfig+0x164>
+ 80030e4: e010 b.n 8003108 <UART_SetConfig+0x17c>
+ 80030e6: 2b20 cmp r3, #32
+ 80030e8: d005 beq.n 80030f6 <UART_SetConfig+0x16a>
+ 80030ea: 2b30 cmp r3, #48 ; 0x30
+ 80030ec: d009 beq.n 8003102 <UART_SetConfig+0x176>
+ 80030ee: e00b b.n 8003108 <UART_SetConfig+0x17c>
+ 80030f0: 2300 movs r3, #0
+ 80030f2: 77fb strb r3, [r7, #31]
+ 80030f4: e0f1 b.n 80032da <UART_SetConfig+0x34e>
+ 80030f6: 2302 movs r3, #2
+ 80030f8: 77fb strb r3, [r7, #31]
+ 80030fa: e0ee b.n 80032da <UART_SetConfig+0x34e>
+ 80030fc: 2304 movs r3, #4
+ 80030fe: 77fb strb r3, [r7, #31]
+ 8003100: e0eb b.n 80032da <UART_SetConfig+0x34e>
+ 8003102: 2308 movs r3, #8
+ 8003104: 77fb strb r3, [r7, #31]
+ 8003106: e0e8 b.n 80032da <UART_SetConfig+0x34e>
+ 8003108: 2310 movs r3, #16
+ 800310a: 77fb strb r3, [r7, #31]
+ 800310c: bf00 nop
+ 800310e: e0e4 b.n 80032da <UART_SetConfig+0x34e>
+ 8003110: 687b ldr r3, [r7, #4]
+ 8003112: 681b ldr r3, [r3, #0]
+ 8003114: 4a5f ldr r2, [pc, #380] ; (8003294 <UART_SetConfig+0x308>)
+ 8003116: 4293 cmp r3, r2
+ 8003118: d120 bne.n 800315c <UART_SetConfig+0x1d0>
+ 800311a: 4b5b ldr r3, [pc, #364] ; (8003288 <UART_SetConfig+0x2fc>)
+ 800311c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8003120: f003 03c0 and.w r3, r3, #192 ; 0xc0
+ 8003124: 2b40 cmp r3, #64 ; 0x40
+ 8003126: d00f beq.n 8003148 <UART_SetConfig+0x1bc>
+ 8003128: 2b40 cmp r3, #64 ; 0x40
+ 800312a: d802 bhi.n 8003132 <UART_SetConfig+0x1a6>
+ 800312c: 2b00 cmp r3, #0
+ 800312e: d005 beq.n 800313c <UART_SetConfig+0x1b0>
+ 8003130: e010 b.n 8003154 <UART_SetConfig+0x1c8>
+ 8003132: 2b80 cmp r3, #128 ; 0x80
+ 8003134: d005 beq.n 8003142 <UART_SetConfig+0x1b6>
+ 8003136: 2bc0 cmp r3, #192 ; 0xc0
+ 8003138: d009 beq.n 800314e <UART_SetConfig+0x1c2>
+ 800313a: e00b b.n 8003154 <UART_SetConfig+0x1c8>
+ 800313c: 2300 movs r3, #0
+ 800313e: 77fb strb r3, [r7, #31]
+ 8003140: e0cb b.n 80032da <UART_SetConfig+0x34e>
+ 8003142: 2302 movs r3, #2
+ 8003144: 77fb strb r3, [r7, #31]
+ 8003146: e0c8 b.n 80032da <UART_SetConfig+0x34e>
+ 8003148: 2304 movs r3, #4
+ 800314a: 77fb strb r3, [r7, #31]
+ 800314c: e0c5 b.n 80032da <UART_SetConfig+0x34e>
+ 800314e: 2308 movs r3, #8
+ 8003150: 77fb strb r3, [r7, #31]
+ 8003152: e0c2 b.n 80032da <UART_SetConfig+0x34e>
+ 8003154: 2310 movs r3, #16
+ 8003156: 77fb strb r3, [r7, #31]
+ 8003158: bf00 nop
+ 800315a: e0be b.n 80032da <UART_SetConfig+0x34e>
+ 800315c: 687b ldr r3, [r7, #4]
+ 800315e: 681b ldr r3, [r3, #0]
+ 8003160: 4a4d ldr r2, [pc, #308] ; (8003298 <UART_SetConfig+0x30c>)
+ 8003162: 4293 cmp r3, r2
+ 8003164: d124 bne.n 80031b0 <UART_SetConfig+0x224>
+ 8003166: 4b48 ldr r3, [pc, #288] ; (8003288 <UART_SetConfig+0x2fc>)
+ 8003168: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 800316c: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8003170: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 8003174: d012 beq.n 800319c <UART_SetConfig+0x210>
+ 8003176: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 800317a: d802 bhi.n 8003182 <UART_SetConfig+0x1f6>
+ 800317c: 2b00 cmp r3, #0
+ 800317e: d007 beq.n 8003190 <UART_SetConfig+0x204>
+ 8003180: e012 b.n 80031a8 <UART_SetConfig+0x21c>
+ 8003182: f5b3 7f00 cmp.w r3, #512 ; 0x200
+ 8003186: d006 beq.n 8003196 <UART_SetConfig+0x20a>
+ 8003188: f5b3 7f40 cmp.w r3, #768 ; 0x300
+ 800318c: d009 beq.n 80031a2 <UART_SetConfig+0x216>
+ 800318e: e00b b.n 80031a8 <UART_SetConfig+0x21c>
+ 8003190: 2300 movs r3, #0
+ 8003192: 77fb strb r3, [r7, #31]
+ 8003194: e0a1 b.n 80032da <UART_SetConfig+0x34e>
+ 8003196: 2302 movs r3, #2
+ 8003198: 77fb strb r3, [r7, #31]
+ 800319a: e09e b.n 80032da <UART_SetConfig+0x34e>
+ 800319c: 2304 movs r3, #4
+ 800319e: 77fb strb r3, [r7, #31]
+ 80031a0: e09b b.n 80032da <UART_SetConfig+0x34e>
+ 80031a2: 2308 movs r3, #8
+ 80031a4: 77fb strb r3, [r7, #31]
+ 80031a6: e098 b.n 80032da <UART_SetConfig+0x34e>
+ 80031a8: 2310 movs r3, #16
+ 80031aa: 77fb strb r3, [r7, #31]
+ 80031ac: bf00 nop
+ 80031ae: e094 b.n 80032da <UART_SetConfig+0x34e>
+ 80031b0: 687b ldr r3, [r7, #4]
+ 80031b2: 681b ldr r3, [r3, #0]
+ 80031b4: 4a39 ldr r2, [pc, #228] ; (800329c <UART_SetConfig+0x310>)
+ 80031b6: 4293 cmp r3, r2
+ 80031b8: d124 bne.n 8003204 <UART_SetConfig+0x278>
+ 80031ba: 4b33 ldr r3, [pc, #204] ; (8003288 <UART_SetConfig+0x2fc>)
+ 80031bc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 80031c0: f403 6340 and.w r3, r3, #3072 ; 0xc00
+ 80031c4: f5b3 6f80 cmp.w r3, #1024 ; 0x400
+ 80031c8: d012 beq.n 80031f0 <UART_SetConfig+0x264>
+ 80031ca: f5b3 6f80 cmp.w r3, #1024 ; 0x400
+ 80031ce: d802 bhi.n 80031d6 <UART_SetConfig+0x24a>
+ 80031d0: 2b00 cmp r3, #0
+ 80031d2: d007 beq.n 80031e4 <UART_SetConfig+0x258>
+ 80031d4: e012 b.n 80031fc <UART_SetConfig+0x270>
+ 80031d6: f5b3 6f00 cmp.w r3, #2048 ; 0x800
+ 80031da: d006 beq.n 80031ea <UART_SetConfig+0x25e>
+ 80031dc: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
+ 80031e0: d009 beq.n 80031f6 <UART_SetConfig+0x26a>
+ 80031e2: e00b b.n 80031fc <UART_SetConfig+0x270>
+ 80031e4: 2301 movs r3, #1
+ 80031e6: 77fb strb r3, [r7, #31]
+ 80031e8: e077 b.n 80032da <UART_SetConfig+0x34e>
+ 80031ea: 2302 movs r3, #2
+ 80031ec: 77fb strb r3, [r7, #31]
+ 80031ee: e074 b.n 80032da <UART_SetConfig+0x34e>
+ 80031f0: 2304 movs r3, #4
+ 80031f2: 77fb strb r3, [r7, #31]
+ 80031f4: e071 b.n 80032da <UART_SetConfig+0x34e>
+ 80031f6: 2308 movs r3, #8
+ 80031f8: 77fb strb r3, [r7, #31]
+ 80031fa: e06e b.n 80032da <UART_SetConfig+0x34e>
+ 80031fc: 2310 movs r3, #16
+ 80031fe: 77fb strb r3, [r7, #31]
+ 8003200: bf00 nop
+ 8003202: e06a b.n 80032da <UART_SetConfig+0x34e>
+ 8003204: 687b ldr r3, [r7, #4]
+ 8003206: 681b ldr r3, [r3, #0]
+ 8003208: 4a25 ldr r2, [pc, #148] ; (80032a0 <UART_SetConfig+0x314>)
+ 800320a: 4293 cmp r3, r2
+ 800320c: d124 bne.n 8003258 <UART_SetConfig+0x2cc>
+ 800320e: 4b1e ldr r3, [pc, #120] ; (8003288 <UART_SetConfig+0x2fc>)
+ 8003210: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8003214: f403 5340 and.w r3, r3, #12288 ; 0x3000
+ 8003218: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 800321c: d012 beq.n 8003244 <UART_SetConfig+0x2b8>
+ 800321e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 8003222: d802 bhi.n 800322a <UART_SetConfig+0x29e>
+ 8003224: 2b00 cmp r3, #0
+ 8003226: d007 beq.n 8003238 <UART_SetConfig+0x2ac>
+ 8003228: e012 b.n 8003250 <UART_SetConfig+0x2c4>
+ 800322a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
+ 800322e: d006 beq.n 800323e <UART_SetConfig+0x2b2>
+ 8003230: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
+ 8003234: d009 beq.n 800324a <UART_SetConfig+0x2be>
+ 8003236: e00b b.n 8003250 <UART_SetConfig+0x2c4>
+ 8003238: 2300 movs r3, #0
+ 800323a: 77fb strb r3, [r7, #31]
+ 800323c: e04d b.n 80032da <UART_SetConfig+0x34e>
+ 800323e: 2302 movs r3, #2
+ 8003240: 77fb strb r3, [r7, #31]
+ 8003242: e04a b.n 80032da <UART_SetConfig+0x34e>
+ 8003244: 2304 movs r3, #4
+ 8003246: 77fb strb r3, [r7, #31]
+ 8003248: e047 b.n 80032da <UART_SetConfig+0x34e>
+ 800324a: 2308 movs r3, #8
+ 800324c: 77fb strb r3, [r7, #31]
+ 800324e: e044 b.n 80032da <UART_SetConfig+0x34e>
+ 8003250: 2310 movs r3, #16
+ 8003252: 77fb strb r3, [r7, #31]
+ 8003254: bf00 nop
+ 8003256: e040 b.n 80032da <UART_SetConfig+0x34e>
+ 8003258: 687b ldr r3, [r7, #4]
+ 800325a: 681b ldr r3, [r3, #0]
+ 800325c: 4a11 ldr r2, [pc, #68] ; (80032a4 <UART_SetConfig+0x318>)
+ 800325e: 4293 cmp r3, r2
+ 8003260: d139 bne.n 80032d6 <UART_SetConfig+0x34a>
+ 8003262: 4b09 ldr r3, [pc, #36] ; (8003288 <UART_SetConfig+0x2fc>)
+ 8003264: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8003268: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 800326c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
+ 8003270: d027 beq.n 80032c2 <UART_SetConfig+0x336>
+ 8003272: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
+ 8003276: d817 bhi.n 80032a8 <UART_SetConfig+0x31c>
+ 8003278: 2b00 cmp r3, #0
+ 800327a: d01c beq.n 80032b6 <UART_SetConfig+0x32a>
+ 800327c: e027 b.n 80032ce <UART_SetConfig+0x342>
+ 800327e: bf00 nop
+ 8003280: efff69f3 .word 0xefff69f3
+ 8003284: 40011000 .word 0x40011000
+ 8003288: 40023800 .word 0x40023800
+ 800328c: 40004400 .word 0x40004400
+ 8003290: 40004800 .word 0x40004800
+ 8003294: 40004c00 .word 0x40004c00
+ 8003298: 40005000 .word 0x40005000
+ 800329c: 40011400 .word 0x40011400
+ 80032a0: 40007800 .word 0x40007800
+ 80032a4: 40007c00 .word 0x40007c00
+ 80032a8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
+ 80032ac: d006 beq.n 80032bc <UART_SetConfig+0x330>
+ 80032ae: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
+ 80032b2: d009 beq.n 80032c8 <UART_SetConfig+0x33c>
+ 80032b4: e00b b.n 80032ce <UART_SetConfig+0x342>
+ 80032b6: 2300 movs r3, #0
+ 80032b8: 77fb strb r3, [r7, #31]
+ 80032ba: e00e b.n 80032da <UART_SetConfig+0x34e>
+ 80032bc: 2302 movs r3, #2
+ 80032be: 77fb strb r3, [r7, #31]
+ 80032c0: e00b b.n 80032da <UART_SetConfig+0x34e>
+ 80032c2: 2304 movs r3, #4
+ 80032c4: 77fb strb r3, [r7, #31]
+ 80032c6: e008 b.n 80032da <UART_SetConfig+0x34e>
+ 80032c8: 2308 movs r3, #8
+ 80032ca: 77fb strb r3, [r7, #31]
+ 80032cc: e005 b.n 80032da <UART_SetConfig+0x34e>
+ 80032ce: 2310 movs r3, #16
+ 80032d0: 77fb strb r3, [r7, #31]
+ 80032d2: bf00 nop
+ 80032d4: e001 b.n 80032da <UART_SetConfig+0x34e>
+ 80032d6: 2310 movs r3, #16
+ 80032d8: 77fb strb r3, [r7, #31]
+
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 80032da: 687b ldr r3, [r7, #4]
+ 80032dc: 69db ldr r3, [r3, #28]
+ 80032de: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
+ 80032e2: d17c bne.n 80033de <UART_SetConfig+0x452>
+ {
+ switch (clocksource)
+ 80032e4: 7ffb ldrb r3, [r7, #31]
+ 80032e6: 2b08 cmp r3, #8
+ 80032e8: d859 bhi.n 800339e <UART_SetConfig+0x412>
+ 80032ea: a201 add r2, pc, #4 ; (adr r2, 80032f0 <UART_SetConfig+0x364>)
+ 80032ec: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80032f0: 08003315 .word 0x08003315
+ 80032f4: 08003333 .word 0x08003333
+ 80032f8: 08003351 .word 0x08003351
+ 80032fc: 0800339f .word 0x0800339f
+ 8003300: 08003369 .word 0x08003369
+ 8003304: 0800339f .word 0x0800339f
+ 8003308: 0800339f .word 0x0800339f
+ 800330c: 0800339f .word 0x0800339f
+ 8003310: 08003387 .word 0x08003387
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ 8003314: f7fe fb38 bl 8001988 <HAL_RCC_GetPCLK1Freq>
+ 8003318: 4603 mov r3, r0
+ 800331a: 005a lsls r2, r3, #1
+ 800331c: 687b ldr r3, [r7, #4]
+ 800331e: 685b ldr r3, [r3, #4]
+ 8003320: 085b lsrs r3, r3, #1
+ 8003322: 441a add r2, r3
+ 8003324: 687b ldr r3, [r7, #4]
+ 8003326: 685b ldr r3, [r3, #4]
+ 8003328: fbb2 f3f3 udiv r3, r2, r3
+ 800332c: b29b uxth r3, r3
+ 800332e: 61bb str r3, [r7, #24]
+ break;
+ 8003330: e038 b.n 80033a4 <UART_SetConfig+0x418>
+ case UART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ 8003332: f7fe fb3d bl 80019b0 <HAL_RCC_GetPCLK2Freq>
+ 8003336: 4603 mov r3, r0
+ 8003338: 005a lsls r2, r3, #1
+ 800333a: 687b ldr r3, [r7, #4]
+ 800333c: 685b ldr r3, [r3, #4]
+ 800333e: 085b lsrs r3, r3, #1
+ 8003340: 441a add r2, r3
+ 8003342: 687b ldr r3, [r7, #4]
+ 8003344: 685b ldr r3, [r3, #4]
+ 8003346: fbb2 f3f3 udiv r3, r2, r3
+ 800334a: b29b uxth r3, r3
+ 800334c: 61bb str r3, [r7, #24]
+ break;
+ 800334e: e029 b.n 80033a4 <UART_SetConfig+0x418>
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ 8003350: 687b ldr r3, [r7, #4]
+ 8003352: 685b ldr r3, [r3, #4]
+ 8003354: 085a lsrs r2, r3, #1
+ 8003356: 4b5d ldr r3, [pc, #372] ; (80034cc <UART_SetConfig+0x540>)
+ 8003358: 4413 add r3, r2
+ 800335a: 687a ldr r2, [r7, #4]
+ 800335c: 6852 ldr r2, [r2, #4]
+ 800335e: fbb3 f3f2 udiv r3, r3, r2
+ 8003362: b29b uxth r3, r3
+ 8003364: 61bb str r3, [r7, #24]
+ break;
+ 8003366: e01d b.n 80033a4 <UART_SetConfig+0x418>
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ 8003368: f7fe fa50 bl 800180c <HAL_RCC_GetSysClockFreq>
+ 800336c: 4603 mov r3, r0
+ 800336e: 005a lsls r2, r3, #1
+ 8003370: 687b ldr r3, [r7, #4]
+ 8003372: 685b ldr r3, [r3, #4]
+ 8003374: 085b lsrs r3, r3, #1
+ 8003376: 441a add r2, r3
+ 8003378: 687b ldr r3, [r7, #4]
+ 800337a: 685b ldr r3, [r3, #4]
+ 800337c: fbb2 f3f3 udiv r3, r2, r3
+ 8003380: b29b uxth r3, r3
+ 8003382: 61bb str r3, [r7, #24]
+ break;
+ 8003384: e00e b.n 80033a4 <UART_SetConfig+0x418>
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ 8003386: 687b ldr r3, [r7, #4]
+ 8003388: 685b ldr r3, [r3, #4]
+ 800338a: 085b lsrs r3, r3, #1
+ 800338c: f503 3280 add.w r2, r3, #65536 ; 0x10000
+ 8003390: 687b ldr r3, [r7, #4]
+ 8003392: 685b ldr r3, [r3, #4]
+ 8003394: fbb2 f3f3 udiv r3, r2, r3
+ 8003398: b29b uxth r3, r3
+ 800339a: 61bb str r3, [r7, #24]
+ break;
+ 800339c: e002 b.n 80033a4 <UART_SetConfig+0x418>
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ 800339e: 2301 movs r3, #1
+ 80033a0: 75fb strb r3, [r7, #23]
+ break;
+ 80033a2: bf00 nop
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 80033a4: 69bb ldr r3, [r7, #24]
+ 80033a6: 2b0f cmp r3, #15
+ 80033a8: d916 bls.n 80033d8 <UART_SetConfig+0x44c>
+ 80033aa: 69bb ldr r3, [r7, #24]
+ 80033ac: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 80033b0: d212 bcs.n 80033d8 <UART_SetConfig+0x44c>
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ 80033b2: 69bb ldr r3, [r7, #24]
+ 80033b4: b29b uxth r3, r3
+ 80033b6: f023 030f bic.w r3, r3, #15
+ 80033ba: 81fb strh r3, [r7, #14]
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 80033bc: 69bb ldr r3, [r7, #24]
+ 80033be: 085b lsrs r3, r3, #1
+ 80033c0: b29b uxth r3, r3
+ 80033c2: f003 0307 and.w r3, r3, #7
+ 80033c6: b29a uxth r2, r3
+ 80033c8: 89fb ldrh r3, [r7, #14]
+ 80033ca: 4313 orrs r3, r2
+ 80033cc: 81fb strh r3, [r7, #14]
+ huart->Instance->BRR = brrtemp;
+ 80033ce: 687b ldr r3, [r7, #4]
+ 80033d0: 681b ldr r3, [r3, #0]
+ 80033d2: 89fa ldrh r2, [r7, #14]
+ 80033d4: 60da str r2, [r3, #12]
+ 80033d6: e06e b.n 80034b6 <UART_SetConfig+0x52a>
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ 80033d8: 2301 movs r3, #1
+ 80033da: 75fb strb r3, [r7, #23]
+ 80033dc: e06b b.n 80034b6 <UART_SetConfig+0x52a>
+ }
+ }
+ else
+ {
+ switch (clocksource)
+ 80033de: 7ffb ldrb r3, [r7, #31]
+ 80033e0: 2b08 cmp r3, #8
+ 80033e2: d857 bhi.n 8003494 <UART_SetConfig+0x508>
+ 80033e4: a201 add r2, pc, #4 ; (adr r2, 80033ec <UART_SetConfig+0x460>)
+ 80033e6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80033ea: bf00 nop
+ 80033ec: 08003411 .word 0x08003411
+ 80033f0: 0800342d .word 0x0800342d
+ 80033f4: 08003449 .word 0x08003449
+ 80033f8: 08003495 .word 0x08003495
+ 80033fc: 08003461 .word 0x08003461
+ 8003400: 08003495 .word 0x08003495
+ 8003404: 08003495 .word 0x08003495
+ 8003408: 08003495 .word 0x08003495
+ 800340c: 0800347d .word 0x0800347d
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ 8003410: f7fe faba bl 8001988 <HAL_RCC_GetPCLK1Freq>
+ 8003414: 4602 mov r2, r0
+ 8003416: 687b ldr r3, [r7, #4]
+ 8003418: 685b ldr r3, [r3, #4]
+ 800341a: 085b lsrs r3, r3, #1
+ 800341c: 441a add r2, r3
+ 800341e: 687b ldr r3, [r7, #4]
+ 8003420: 685b ldr r3, [r3, #4]
+ 8003422: fbb2 f3f3 udiv r3, r2, r3
+ 8003426: b29b uxth r3, r3
+ 8003428: 61bb str r3, [r7, #24]
+ break;
+ 800342a: e036 b.n 800349a <UART_SetConfig+0x50e>
+ case UART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ 800342c: f7fe fac0 bl 80019b0 <HAL_RCC_GetPCLK2Freq>
+ 8003430: 4602 mov r2, r0
+ 8003432: 687b ldr r3, [r7, #4]
+ 8003434: 685b ldr r3, [r3, #4]
+ 8003436: 085b lsrs r3, r3, #1
+ 8003438: 441a add r2, r3
+ 800343a: 687b ldr r3, [r7, #4]
+ 800343c: 685b ldr r3, [r3, #4]
+ 800343e: fbb2 f3f3 udiv r3, r2, r3
+ 8003442: b29b uxth r3, r3
+ 8003444: 61bb str r3, [r7, #24]
+ break;
+ 8003446: e028 b.n 800349a <UART_SetConfig+0x50e>
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ 8003448: 687b ldr r3, [r7, #4]
+ 800344a: 685b ldr r3, [r3, #4]
+ 800344c: 085a lsrs r2, r3, #1
+ 800344e: 4b20 ldr r3, [pc, #128] ; (80034d0 <UART_SetConfig+0x544>)
+ 8003450: 4413 add r3, r2
+ 8003452: 687a ldr r2, [r7, #4]
+ 8003454: 6852 ldr r2, [r2, #4]
+ 8003456: fbb3 f3f2 udiv r3, r3, r2
+ 800345a: b29b uxth r3, r3
+ 800345c: 61bb str r3, [r7, #24]
+ break;
+ 800345e: e01c b.n 800349a <UART_SetConfig+0x50e>
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ 8003460: f7fe f9d4 bl 800180c <HAL_RCC_GetSysClockFreq>
+ 8003464: 4602 mov r2, r0
+ 8003466: 687b ldr r3, [r7, #4]
+ 8003468: 685b ldr r3, [r3, #4]
+ 800346a: 085b lsrs r3, r3, #1
+ 800346c: 441a add r2, r3
+ 800346e: 687b ldr r3, [r7, #4]
+ 8003470: 685b ldr r3, [r3, #4]
+ 8003472: fbb2 f3f3 udiv r3, r2, r3
+ 8003476: b29b uxth r3, r3
+ 8003478: 61bb str r3, [r7, #24]
+ break;
+ 800347a: e00e b.n 800349a <UART_SetConfig+0x50e>
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ 800347c: 687b ldr r3, [r7, #4]
+ 800347e: 685b ldr r3, [r3, #4]
+ 8003480: 085b lsrs r3, r3, #1
+ 8003482: f503 4200 add.w r2, r3, #32768 ; 0x8000
+ 8003486: 687b ldr r3, [r7, #4]
+ 8003488: 685b ldr r3, [r3, #4]
+ 800348a: fbb2 f3f3 udiv r3, r2, r3
+ 800348e: b29b uxth r3, r3
+ 8003490: 61bb str r3, [r7, #24]
+ break;
+ 8003492: e002 b.n 800349a <UART_SetConfig+0x50e>
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ 8003494: 2301 movs r3, #1
+ 8003496: 75fb strb r3, [r7, #23]
+ break;
+ 8003498: bf00 nop
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 800349a: 69bb ldr r3, [r7, #24]
+ 800349c: 2b0f cmp r3, #15
+ 800349e: d908 bls.n 80034b2 <UART_SetConfig+0x526>
+ 80034a0: 69bb ldr r3, [r7, #24]
+ 80034a2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 80034a6: d204 bcs.n 80034b2 <UART_SetConfig+0x526>
+ {
+ huart->Instance->BRR = usartdiv;
+ 80034a8: 687b ldr r3, [r7, #4]
+ 80034aa: 681b ldr r3, [r3, #0]
+ 80034ac: 69ba ldr r2, [r7, #24]
+ 80034ae: 60da str r2, [r3, #12]
+ 80034b0: e001 b.n 80034b6 <UART_SetConfig+0x52a>
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ 80034b2: 2301 movs r3, #1
+ 80034b4: 75fb strb r3, [r7, #23]
+ }
+ }
+
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ 80034b6: 687b ldr r3, [r7, #4]
+ 80034b8: 2200 movs r2, #0
+ 80034ba: 661a str r2, [r3, #96] ; 0x60
+ huart->TxISR = NULL;
+ 80034bc: 687b ldr r3, [r7, #4]
+ 80034be: 2200 movs r2, #0
+ 80034c0: 665a str r2, [r3, #100] ; 0x64
+
+ return ret;
+ 80034c2: 7dfb ldrb r3, [r7, #23]
+}
+ 80034c4: 4618 mov r0, r3
+ 80034c6: 3720 adds r7, #32
+ 80034c8: 46bd mov sp, r7
+ 80034ca: bd80 pop {r7, pc}
+ 80034cc: 01e84800 .word 0x01e84800
+ 80034d0: 00f42400 .word 0x00f42400
+
+080034d4 <UART_AdvFeatureConfig>:
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ 80034d4: b480 push {r7}
+ 80034d6: b083 sub sp, #12
+ 80034d8: af00 add r7, sp, #0
+ 80034da: 6078 str r0, [r7, #4]
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ 80034dc: 687b ldr r3, [r7, #4]
+ 80034de: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80034e0: f003 0301 and.w r3, r3, #1
+ 80034e4: 2b00 cmp r3, #0
+ 80034e6: d00a beq.n 80034fe <UART_AdvFeatureConfig+0x2a>
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ 80034e8: 687b ldr r3, [r7, #4]
+ 80034ea: 681b ldr r3, [r3, #0]
+ 80034ec: 685b ldr r3, [r3, #4]
+ 80034ee: f423 3100 bic.w r1, r3, #131072 ; 0x20000
+ 80034f2: 687b ldr r3, [r7, #4]
+ 80034f4: 6a9a ldr r2, [r3, #40] ; 0x28
+ 80034f6: 687b ldr r3, [r7, #4]
+ 80034f8: 681b ldr r3, [r3, #0]
+ 80034fa: 430a orrs r2, r1
+ 80034fc: 605a str r2, [r3, #4]
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ 80034fe: 687b ldr r3, [r7, #4]
+ 8003500: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003502: f003 0302 and.w r3, r3, #2
+ 8003506: 2b00 cmp r3, #0
+ 8003508: d00a beq.n 8003520 <UART_AdvFeatureConfig+0x4c>
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ 800350a: 687b ldr r3, [r7, #4]
+ 800350c: 681b ldr r3, [r3, #0]
+ 800350e: 685b ldr r3, [r3, #4]
+ 8003510: f423 3180 bic.w r1, r3, #65536 ; 0x10000
+ 8003514: 687b ldr r3, [r7, #4]
+ 8003516: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8003518: 687b ldr r3, [r7, #4]
+ 800351a: 681b ldr r3, [r3, #0]
+ 800351c: 430a orrs r2, r1
+ 800351e: 605a str r2, [r3, #4]
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ 8003520: 687b ldr r3, [r7, #4]
+ 8003522: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003524: f003 0304 and.w r3, r3, #4
+ 8003528: 2b00 cmp r3, #0
+ 800352a: d00a beq.n 8003542 <UART_AdvFeatureConfig+0x6e>
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ 800352c: 687b ldr r3, [r7, #4]
+ 800352e: 681b ldr r3, [r3, #0]
+ 8003530: 685b ldr r3, [r3, #4]
+ 8003532: f423 2180 bic.w r1, r3, #262144 ; 0x40000
+ 8003536: 687b ldr r3, [r7, #4]
+ 8003538: 6b1a ldr r2, [r3, #48] ; 0x30
+ 800353a: 687b ldr r3, [r7, #4]
+ 800353c: 681b ldr r3, [r3, #0]
+ 800353e: 430a orrs r2, r1
+ 8003540: 605a str r2, [r3, #4]
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ 8003542: 687b ldr r3, [r7, #4]
+ 8003544: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003546: f003 0308 and.w r3, r3, #8
+ 800354a: 2b00 cmp r3, #0
+ 800354c: d00a beq.n 8003564 <UART_AdvFeatureConfig+0x90>
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ 800354e: 687b ldr r3, [r7, #4]
+ 8003550: 681b ldr r3, [r3, #0]
+ 8003552: 685b ldr r3, [r3, #4]
+ 8003554: f423 4100 bic.w r1, r3, #32768 ; 0x8000
+ 8003558: 687b ldr r3, [r7, #4]
+ 800355a: 6b5a ldr r2, [r3, #52] ; 0x34
+ 800355c: 687b ldr r3, [r7, #4]
+ 800355e: 681b ldr r3, [r3, #0]
+ 8003560: 430a orrs r2, r1
+ 8003562: 605a str r2, [r3, #4]
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ 8003564: 687b ldr r3, [r7, #4]
+ 8003566: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003568: f003 0310 and.w r3, r3, #16
+ 800356c: 2b00 cmp r3, #0
+ 800356e: d00a beq.n 8003586 <UART_AdvFeatureConfig+0xb2>
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ 8003570: 687b ldr r3, [r7, #4]
+ 8003572: 681b ldr r3, [r3, #0]
+ 8003574: 689b ldr r3, [r3, #8]
+ 8003576: f423 5180 bic.w r1, r3, #4096 ; 0x1000
+ 800357a: 687b ldr r3, [r7, #4]
+ 800357c: 6b9a ldr r2, [r3, #56] ; 0x38
+ 800357e: 687b ldr r3, [r7, #4]
+ 8003580: 681b ldr r3, [r3, #0]
+ 8003582: 430a orrs r2, r1
+ 8003584: 609a str r2, [r3, #8]
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ 8003586: 687b ldr r3, [r7, #4]
+ 8003588: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800358a: f003 0320 and.w r3, r3, #32
+ 800358e: 2b00 cmp r3, #0
+ 8003590: d00a beq.n 80035a8 <UART_AdvFeatureConfig+0xd4>
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ 8003592: 687b ldr r3, [r7, #4]
+ 8003594: 681b ldr r3, [r3, #0]
+ 8003596: 689b ldr r3, [r3, #8]
+ 8003598: f423 5100 bic.w r1, r3, #8192 ; 0x2000
+ 800359c: 687b ldr r3, [r7, #4]
+ 800359e: 6bda ldr r2, [r3, #60] ; 0x3c
+ 80035a0: 687b ldr r3, [r7, #4]
+ 80035a2: 681b ldr r3, [r3, #0]
+ 80035a4: 430a orrs r2, r1
+ 80035a6: 609a str r2, [r3, #8]
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ 80035a8: 687b ldr r3, [r7, #4]
+ 80035aa: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80035ac: f003 0340 and.w r3, r3, #64 ; 0x40
+ 80035b0: 2b00 cmp r3, #0
+ 80035b2: d01a beq.n 80035ea <UART_AdvFeatureConfig+0x116>
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ 80035b4: 687b ldr r3, [r7, #4]
+ 80035b6: 681b ldr r3, [r3, #0]
+ 80035b8: 685b ldr r3, [r3, #4]
+ 80035ba: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
+ 80035be: 687b ldr r3, [r7, #4]
+ 80035c0: 6c1a ldr r2, [r3, #64] ; 0x40
+ 80035c2: 687b ldr r3, [r7, #4]
+ 80035c4: 681b ldr r3, [r3, #0]
+ 80035c6: 430a orrs r2, r1
+ 80035c8: 605a str r2, [r3, #4]
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ 80035ca: 687b ldr r3, [r7, #4]
+ 80035cc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80035ce: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 80035d2: d10a bne.n 80035ea <UART_AdvFeatureConfig+0x116>
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ 80035d4: 687b ldr r3, [r7, #4]
+ 80035d6: 681b ldr r3, [r3, #0]
+ 80035d8: 685b ldr r3, [r3, #4]
+ 80035da: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
+ 80035de: 687b ldr r3, [r7, #4]
+ 80035e0: 6c5a ldr r2, [r3, #68] ; 0x44
+ 80035e2: 687b ldr r3, [r7, #4]
+ 80035e4: 681b ldr r3, [r3, #0]
+ 80035e6: 430a orrs r2, r1
+ 80035e8: 605a str r2, [r3, #4]
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ 80035ea: 687b ldr r3, [r7, #4]
+ 80035ec: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80035ee: f003 0380 and.w r3, r3, #128 ; 0x80
+ 80035f2: 2b00 cmp r3, #0
+ 80035f4: d00a beq.n 800360c <UART_AdvFeatureConfig+0x138>
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ 80035f6: 687b ldr r3, [r7, #4]
+ 80035f8: 681b ldr r3, [r3, #0]
+ 80035fa: 685b ldr r3, [r3, #4]
+ 80035fc: f423 2100 bic.w r1, r3, #524288 ; 0x80000
+ 8003600: 687b ldr r3, [r7, #4]
+ 8003602: 6c9a ldr r2, [r3, #72] ; 0x48
+ 8003604: 687b ldr r3, [r7, #4]
+ 8003606: 681b ldr r3, [r3, #0]
+ 8003608: 430a orrs r2, r1
+ 800360a: 605a str r2, [r3, #4]
+ }
+}
+ 800360c: bf00 nop
+ 800360e: 370c adds r7, #12
+ 8003610: 46bd mov sp, r7
+ 8003612: f85d 7b04 ldr.w r7, [sp], #4
+ 8003616: 4770 bx lr
+
+08003618 <UART_CheckIdleState>:
+ * @brief Check the UART Idle State.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ 8003618: b580 push {r7, lr}
+ 800361a: b086 sub sp, #24
+ 800361c: af02 add r7, sp, #8
+ 800361e: 6078 str r0, [r7, #4]
+ uint32_t tickstart;
+
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8003620: 687b ldr r3, [r7, #4]
+ 8003622: 2200 movs r2, #0
+ 8003624: 67da str r2, [r3, #124] ; 0x7c
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+ 8003626: f7fd faad bl 8000b84 <HAL_GetTick>
+ 800362a: 60f8 str r0, [r7, #12]
+
+ /* Check if the Transmitter is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 800362c: 687b ldr r3, [r7, #4]
+ 800362e: 681b ldr r3, [r3, #0]
+ 8003630: 681b ldr r3, [r3, #0]
+ 8003632: f003 0308 and.w r3, r3, #8
+ 8003636: 2b08 cmp r3, #8
+ 8003638: d10e bne.n 8003658 <UART_CheckIdleState+0x40>
+ {
+ /* Wait until TEACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 800363a: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
+ 800363e: 9300 str r3, [sp, #0]
+ 8003640: 68fb ldr r3, [r7, #12]
+ 8003642: 2200 movs r2, #0
+ 8003644: f44f 1100 mov.w r1, #2097152 ; 0x200000
+ 8003648: 6878 ldr r0, [r7, #4]
+ 800364a: f000 f814 bl 8003676 <UART_WaitOnFlagUntilTimeout>
+ 800364e: 4603 mov r3, r0
+ 8003650: 2b00 cmp r3, #0
+ 8003652: d001 beq.n 8003658 <UART_CheckIdleState+0x40>
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ 8003654: 2303 movs r3, #3
+ 8003656: e00a b.n 800366e <UART_CheckIdleState+0x56>
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ 8003658: 687b ldr r3, [r7, #4]
+ 800365a: 2220 movs r2, #32
+ 800365c: 675a str r2, [r3, #116] ; 0x74
+ huart->RxState = HAL_UART_STATE_READY;
+ 800365e: 687b ldr r3, [r7, #4]
+ 8003660: 2220 movs r2, #32
+ 8003662: 679a str r2, [r3, #120] ; 0x78
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ 8003664: 687b ldr r3, [r7, #4]
+ 8003666: 2200 movs r2, #0
+ 8003668: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ return HAL_OK;
+ 800366c: 2300 movs r3, #0
+}
+ 800366e: 4618 mov r0, r3
+ 8003670: 3710 adds r7, #16
+ 8003672: 46bd mov sp, r7
+ 8003674: bd80 pop {r7, pc}
+
+08003676 <UART_WaitOnFlagUntilTimeout>:
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ 8003676: b580 push {r7, lr}
+ 8003678: b084 sub sp, #16
+ 800367a: af00 add r7, sp, #0
+ 800367c: 60f8 str r0, [r7, #12]
+ 800367e: 60b9 str r1, [r7, #8]
+ 8003680: 603b str r3, [r7, #0]
+ 8003682: 4613 mov r3, r2
+ 8003684: 71fb strb r3, [r7, #7]
+ /* Wait until flag is set */
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 8003686: e02a b.n 80036de <UART_WaitOnFlagUntilTimeout+0x68>
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ 8003688: 69bb ldr r3, [r7, #24]
+ 800368a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
+ 800368e: d026 beq.n 80036de <UART_WaitOnFlagUntilTimeout+0x68>
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ 8003690: f7fd fa78 bl 8000b84 <HAL_GetTick>
+ 8003694: 4602 mov r2, r0
+ 8003696: 683b ldr r3, [r7, #0]
+ 8003698: 1ad3 subs r3, r2, r3
+ 800369a: 69ba ldr r2, [r7, #24]
+ 800369c: 429a cmp r2, r3
+ 800369e: d302 bcc.n 80036a6 <UART_WaitOnFlagUntilTimeout+0x30>
+ 80036a0: 69bb ldr r3, [r7, #24]
+ 80036a2: 2b00 cmp r3, #0
+ 80036a4: d11b bne.n 80036de <UART_WaitOnFlagUntilTimeout+0x68>
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ 80036a6: 68fb ldr r3, [r7, #12]
+ 80036a8: 681b ldr r3, [r3, #0]
+ 80036aa: 681a ldr r2, [r3, #0]
+ 80036ac: 68fb ldr r3, [r7, #12]
+ 80036ae: 681b ldr r3, [r3, #0]
+ 80036b0: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
+ 80036b4: 601a str r2, [r3, #0]
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 80036b6: 68fb ldr r3, [r7, #12]
+ 80036b8: 681b ldr r3, [r3, #0]
+ 80036ba: 689a ldr r2, [r3, #8]
+ 80036bc: 68fb ldr r3, [r7, #12]
+ 80036be: 681b ldr r3, [r3, #0]
+ 80036c0: f022 0201 bic.w r2, r2, #1
+ 80036c4: 609a str r2, [r3, #8]
+
+ huart->gState = HAL_UART_STATE_READY;
+ 80036c6: 68fb ldr r3, [r7, #12]
+ 80036c8: 2220 movs r2, #32
+ 80036ca: 675a str r2, [r3, #116] ; 0x74
+ huart->RxState = HAL_UART_STATE_READY;
+ 80036cc: 68fb ldr r3, [r7, #12]
+ 80036ce: 2220 movs r2, #32
+ 80036d0: 679a str r2, [r3, #120] ; 0x78
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ 80036d2: 68fb ldr r3, [r7, #12]
+ 80036d4: 2200 movs r2, #0
+ 80036d6: f883 2070 strb.w r2, [r3, #112] ; 0x70
+
+ return HAL_TIMEOUT;
+ 80036da: 2303 movs r3, #3
+ 80036dc: e00f b.n 80036fe <UART_WaitOnFlagUntilTimeout+0x88>
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 80036de: 68fb ldr r3, [r7, #12]
+ 80036e0: 681b ldr r3, [r3, #0]
+ 80036e2: 69da ldr r2, [r3, #28]
+ 80036e4: 68bb ldr r3, [r7, #8]
+ 80036e6: 4013 ands r3, r2
+ 80036e8: 68ba ldr r2, [r7, #8]
+ 80036ea: 429a cmp r2, r3
+ 80036ec: bf0c ite eq
+ 80036ee: 2301 moveq r3, #1
+ 80036f0: 2300 movne r3, #0
+ 80036f2: b2db uxtb r3, r3
+ 80036f4: 461a mov r2, r3
+ 80036f6: 79fb ldrb r3, [r7, #7]
+ 80036f8: 429a cmp r2, r3
+ 80036fa: d0c5 beq.n 8003688 <UART_WaitOnFlagUntilTimeout+0x12>
+ }
+ }
+ }
+ return HAL_OK;
+ 80036fc: 2300 movs r3, #0
+}
+ 80036fe: 4618 mov r0, r3
+ 8003700: 3710 adds r7, #16
+ 8003702: 46bd mov sp, r7
+ 8003704: bd80 pop {r7, pc}
+
+08003706 <UART_EndRxTransfer>:
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ 8003706: b480 push {r7}
+ 8003708: b083 sub sp, #12
+ 800370a: af00 add r7, sp, #0
+ 800370c: 6078 str r0, [r7, #4]
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ 800370e: 687b ldr r3, [r7, #4]
+ 8003710: 681b ldr r3, [r3, #0]
+ 8003712: 681a ldr r2, [r3, #0]
+ 8003714: 687b ldr r3, [r7, #4]
+ 8003716: 681b ldr r3, [r3, #0]
+ 8003718: f422 7290 bic.w r2, r2, #288 ; 0x120
+ 800371c: 601a str r2, [r3, #0]
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 800371e: 687b ldr r3, [r7, #4]
+ 8003720: 681b ldr r3, [r3, #0]
+ 8003722: 689a ldr r2, [r3, #8]
+ 8003724: 687b ldr r3, [r7, #4]
+ 8003726: 681b ldr r3, [r3, #0]
+ 8003728: f022 0201 bic.w r2, r2, #1
+ 800372c: 609a str r2, [r3, #8]
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ 800372e: 687b ldr r3, [r7, #4]
+ 8003730: 2220 movs r2, #32
+ 8003732: 679a str r2, [r3, #120] ; 0x78
+
+ /* Reset RxIsr function pointer */
+ huart->RxISR = NULL;
+ 8003734: 687b ldr r3, [r7, #4]
+ 8003736: 2200 movs r2, #0
+ 8003738: 661a str r2, [r3, #96] ; 0x60
+}
+ 800373a: bf00 nop
+ 800373c: 370c adds r7, #12
+ 800373e: 46bd mov sp, r7
+ 8003740: f85d 7b04 ldr.w r7, [sp], #4
+ 8003744: 4770 bx lr
+
+08003746 <UART_DMAAbortOnError>:
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ 8003746: b580 push {r7, lr}
+ 8003748: b084 sub sp, #16
+ 800374a: af00 add r7, sp, #0
+ 800374c: 6078 str r0, [r7, #4]
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 800374e: 687b ldr r3, [r7, #4]
+ 8003750: 6b9b ldr r3, [r3, #56] ; 0x38
+ 8003752: 60fb str r3, [r7, #12]
+ huart->RxXferCount = 0U;
+ 8003754: 68fb ldr r3, [r7, #12]
+ 8003756: 2200 movs r2, #0
+ 8003758: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+ huart->TxXferCount = 0U;
+ 800375c: 68fb ldr r3, [r7, #12]
+ 800375e: 2200 movs r2, #0
+ 8003760: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+ 8003764: 68f8 ldr r0, [r7, #12]
+ 8003766: f7fd f873 bl 8000850 <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 800376a: bf00 nop
+ 800376c: 3710 adds r7, #16
+ 800376e: 46bd mov sp, r7
+ 8003770: bd80 pop {r7, pc}
+
+08003772 <UART_EndTransmit_IT>:
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ 8003772: b580 push {r7, lr}
+ 8003774: b082 sub sp, #8
+ 8003776: af00 add r7, sp, #0
+ 8003778: 6078 str r0, [r7, #4]
+ /* Disable the UART Transmit Complete Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ 800377a: 687b ldr r3, [r7, #4]
+ 800377c: 681b ldr r3, [r3, #0]
+ 800377e: 681a ldr r2, [r3, #0]
+ 8003780: 687b ldr r3, [r7, #4]
+ 8003782: 681b ldr r3, [r3, #0]
+ 8003784: f022 0240 bic.w r2, r2, #64 ; 0x40
+ 8003788: 601a str r2, [r3, #0]
+
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ 800378a: 687b ldr r3, [r7, #4]
+ 800378c: 2220 movs r2, #32
+ 800378e: 675a str r2, [r3, #116] ; 0x74
+
+ /* Cleat TxISR function pointer */
+ huart->TxISR = NULL;
+ 8003790: 687b ldr r3, [r7, #4]
+ 8003792: 2200 movs r2, #0
+ 8003794: 665a str r2, [r3, #100] ; 0x64
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+ 8003796: 6878 ldr r0, [r7, #4]
+ 8003798: f7ff fbee bl 8002f78 <HAL_UART_TxCpltCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 800379c: bf00 nop
+ 800379e: 3708 adds r7, #8
+ 80037a0: 46bd mov sp, r7
+ 80037a2: bd80 pop {r7, pc}
+
+080037a4 <UART_RxISR_8BIT>:
+ * @brief RX interrrupt handler for 7 or 8 bits data word length .
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ 80037a4: b580 push {r7, lr}
+ 80037a6: b084 sub sp, #16
+ 80037a8: af00 add r7, sp, #0
+ 80037aa: 6078 str r0, [r7, #4]
+ uint16_t uhMask = huart->Mask;
+ 80037ac: 687b ldr r3, [r7, #4]
+ 80037ae: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
+ 80037b2: 81fb strh r3, [r7, #14]
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 80037b4: 687b ldr r3, [r7, #4]
+ 80037b6: 6f9b ldr r3, [r3, #120] ; 0x78
+ 80037b8: 2b22 cmp r3, #34 ; 0x22
+ 80037ba: d13a bne.n 8003832 <UART_RxISR_8BIT+0x8e>
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 80037bc: 687b ldr r3, [r7, #4]
+ 80037be: 681b ldr r3, [r3, #0]
+ 80037c0: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80037c2: 81bb strh r3, [r7, #12]
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 80037c4: 89bb ldrh r3, [r7, #12]
+ 80037c6: b2d9 uxtb r1, r3
+ 80037c8: 89fb ldrh r3, [r7, #14]
+ 80037ca: b2da uxtb r2, r3
+ 80037cc: 687b ldr r3, [r7, #4]
+ 80037ce: 6d5b ldr r3, [r3, #84] ; 0x54
+ 80037d0: 400a ands r2, r1
+ 80037d2: b2d2 uxtb r2, r2
+ 80037d4: 701a strb r2, [r3, #0]
+ huart->pRxBuffPtr++;
+ 80037d6: 687b ldr r3, [r7, #4]
+ 80037d8: 6d5b ldr r3, [r3, #84] ; 0x54
+ 80037da: 1c5a adds r2, r3, #1
+ 80037dc: 687b ldr r3, [r7, #4]
+ 80037de: 655a str r2, [r3, #84] ; 0x54
+ huart->RxXferCount--;
+ 80037e0: 687b ldr r3, [r7, #4]
+ 80037e2: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 80037e6: b29b uxth r3, r3
+ 80037e8: 3b01 subs r3, #1
+ 80037ea: b29a uxth r2, r3
+ 80037ec: 687b ldr r3, [r7, #4]
+ 80037ee: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+
+ if (huart->RxXferCount == 0U)
+ 80037f2: 687b ldr r3, [r7, #4]
+ 80037f4: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 80037f8: b29b uxth r3, r3
+ 80037fa: 2b00 cmp r3, #0
+ 80037fc: d121 bne.n 8003842 <UART_RxISR_8BIT+0x9e>
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ 80037fe: 687b ldr r3, [r7, #4]
+ 8003800: 681b ldr r3, [r3, #0]
+ 8003802: 681a ldr r2, [r3, #0]
+ 8003804: 687b ldr r3, [r7, #4]
+ 8003806: 681b ldr r3, [r3, #0]
+ 8003808: f422 7290 bic.w r2, r2, #288 ; 0x120
+ 800380c: 601a str r2, [r3, #0]
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 800380e: 687b ldr r3, [r7, #4]
+ 8003810: 681b ldr r3, [r3, #0]
+ 8003812: 689a ldr r2, [r3, #8]
+ 8003814: 687b ldr r3, [r7, #4]
+ 8003816: 681b ldr r3, [r3, #0]
+ 8003818: f022 0201 bic.w r2, r2, #1
+ 800381c: 609a str r2, [r3, #8]
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ 800381e: 687b ldr r3, [r7, #4]
+ 8003820: 2220 movs r2, #32
+ 8003822: 679a str r2, [r3, #120] ; 0x78
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+ 8003824: 687b ldr r3, [r7, #4]
+ 8003826: 2200 movs r2, #0
+ 8003828: 661a str r2, [r3, #96] ; 0x60
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+ 800382a: 6878 ldr r0, [r7, #4]
+ 800382c: f7fc fffc bl 8000828 <HAL_UART_RxCpltCallback>
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+ 8003830: e007 b.n 8003842 <UART_RxISR_8BIT+0x9e>
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 8003832: 687b ldr r3, [r7, #4]
+ 8003834: 681b ldr r3, [r3, #0]
+ 8003836: 699a ldr r2, [r3, #24]
+ 8003838: 687b ldr r3, [r7, #4]
+ 800383a: 681b ldr r3, [r3, #0]
+ 800383c: f042 0208 orr.w r2, r2, #8
+ 8003840: 619a str r2, [r3, #24]
+}
+ 8003842: bf00 nop
+ 8003844: 3710 adds r7, #16
+ 8003846: 46bd mov sp, r7
+ 8003848: bd80 pop {r7, pc}
+
+0800384a <UART_RxISR_16BIT>:
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ 800384a: b580 push {r7, lr}
+ 800384c: b084 sub sp, #16
+ 800384e: af00 add r7, sp, #0
+ 8003850: 6078 str r0, [r7, #4]
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ 8003852: 687b ldr r3, [r7, #4]
+ 8003854: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
+ 8003858: 81fb strh r3, [r7, #14]
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 800385a: 687b ldr r3, [r7, #4]
+ 800385c: 6f9b ldr r3, [r3, #120] ; 0x78
+ 800385e: 2b22 cmp r3, #34 ; 0x22
+ 8003860: d13a bne.n 80038d8 <UART_RxISR_16BIT+0x8e>
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 8003862: 687b ldr r3, [r7, #4]
+ 8003864: 681b ldr r3, [r3, #0]
+ 8003866: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003868: 81bb strh r3, [r7, #12]
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 800386a: 687b ldr r3, [r7, #4]
+ 800386c: 6d5b ldr r3, [r3, #84] ; 0x54
+ 800386e: 60bb str r3, [r7, #8]
+ *tmp = (uint16_t)(uhdata & uhMask);
+ 8003870: 89ba ldrh r2, [r7, #12]
+ 8003872: 89fb ldrh r3, [r7, #14]
+ 8003874: 4013 ands r3, r2
+ 8003876: b29a uxth r2, r3
+ 8003878: 68bb ldr r3, [r7, #8]
+ 800387a: 801a strh r2, [r3, #0]
+ huart->pRxBuffPtr += 2U;
+ 800387c: 687b ldr r3, [r7, #4]
+ 800387e: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8003880: 1c9a adds r2, r3, #2
+ 8003882: 687b ldr r3, [r7, #4]
+ 8003884: 655a str r2, [r3, #84] ; 0x54
+ huart->RxXferCount--;
+ 8003886: 687b ldr r3, [r7, #4]
+ 8003888: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 800388c: b29b uxth r3, r3
+ 800388e: 3b01 subs r3, #1
+ 8003890: b29a uxth r2, r3
+ 8003892: 687b ldr r3, [r7, #4]
+ 8003894: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
+
+ if (huart->RxXferCount == 0U)
+ 8003898: 687b ldr r3, [r7, #4]
+ 800389a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
+ 800389e: b29b uxth r3, r3
+ 80038a0: 2b00 cmp r3, #0
+ 80038a2: d121 bne.n 80038e8 <UART_RxISR_16BIT+0x9e>
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ 80038a4: 687b ldr r3, [r7, #4]
+ 80038a6: 681b ldr r3, [r3, #0]
+ 80038a8: 681a ldr r2, [r3, #0]
+ 80038aa: 687b ldr r3, [r7, #4]
+ 80038ac: 681b ldr r3, [r3, #0]
+ 80038ae: f422 7290 bic.w r2, r2, #288 ; 0x120
+ 80038b2: 601a str r2, [r3, #0]
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 80038b4: 687b ldr r3, [r7, #4]
+ 80038b6: 681b ldr r3, [r3, #0]
+ 80038b8: 689a ldr r2, [r3, #8]
+ 80038ba: 687b ldr r3, [r7, #4]
+ 80038bc: 681b ldr r3, [r3, #0]
+ 80038be: f022 0201 bic.w r2, r2, #1
+ 80038c2: 609a str r2, [r3, #8]
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ 80038c4: 687b ldr r3, [r7, #4]
+ 80038c6: 2220 movs r2, #32
+ 80038c8: 679a str r2, [r3, #120] ; 0x78
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+ 80038ca: 687b ldr r3, [r7, #4]
+ 80038cc: 2200 movs r2, #0
+ 80038ce: 661a str r2, [r3, #96] ; 0x60
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+ 80038d0: 6878 ldr r0, [r7, #4]
+ 80038d2: f7fc ffa9 bl 8000828 <HAL_UART_RxCpltCallback>
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+ 80038d6: e007 b.n 80038e8 <UART_RxISR_16BIT+0x9e>
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 80038d8: 687b ldr r3, [r7, #4]
+ 80038da: 681b ldr r3, [r3, #0]
+ 80038dc: 699a ldr r2, [r3, #24]
+ 80038de: 687b ldr r3, [r7, #4]
+ 80038e0: 681b ldr r3, [r3, #0]
+ 80038e2: f042 0208 orr.w r2, r2, #8
+ 80038e6: 619a str r2, [r3, #24]
+}
+ 80038e8: bf00 nop
+ 80038ea: 3710 adds r7, #16
+ 80038ec: 46bd mov sp, r7
+ 80038ee: bd80 pop {r7, pc}
+
+080038f0 <__libc_init_array>:
+ 80038f0: b570 push {r4, r5, r6, lr}
+ 80038f2: 4e0d ldr r6, [pc, #52] ; (8003928 <__libc_init_array+0x38>)
+ 80038f4: 4c0d ldr r4, [pc, #52] ; (800392c <__libc_init_array+0x3c>)
+ 80038f6: 1ba4 subs r4, r4, r6
+ 80038f8: 10a4 asrs r4, r4, #2
+ 80038fa: 2500 movs r5, #0
+ 80038fc: 42a5 cmp r5, r4
+ 80038fe: d109 bne.n 8003914 <__libc_init_array+0x24>
+ 8003900: 4e0b ldr r6, [pc, #44] ; (8003930 <__libc_init_array+0x40>)
+ 8003902: 4c0c ldr r4, [pc, #48] ; (8003934 <__libc_init_array+0x44>)
+ 8003904: f000 f820 bl 8003948 <_init>
+ 8003908: 1ba4 subs r4, r4, r6
+ 800390a: 10a4 asrs r4, r4, #2
+ 800390c: 2500 movs r5, #0
+ 800390e: 42a5 cmp r5, r4
+ 8003910: d105 bne.n 800391e <__libc_init_array+0x2e>
+ 8003912: bd70 pop {r4, r5, r6, pc}
+ 8003914: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8003918: 4798 blx r3
+ 800391a: 3501 adds r5, #1
+ 800391c: e7ee b.n 80038fc <__libc_init_array+0xc>
+ 800391e: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8003922: 4798 blx r3
+ 8003924: 3501 adds r5, #1
+ 8003926: e7f2 b.n 800390e <__libc_init_array+0x1e>
+ 8003928: 08003980 .word 0x08003980
+ 800392c: 08003980 .word 0x08003980
+ 8003930: 08003980 .word 0x08003980
+ 8003934: 08003984 .word 0x08003984
+
+08003938 <memset>:
+ 8003938: 4402 add r2, r0
+ 800393a: 4603 mov r3, r0
+ 800393c: 4293 cmp r3, r2
+ 800393e: d100 bne.n 8003942 <memset+0xa>
+ 8003940: 4770 bx lr
+ 8003942: f803 1b01 strb.w r1, [r3], #1
+ 8003946: e7f9 b.n 800393c <memset+0x4>
+
+08003948 <_init>:
+ 8003948: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 800394a: bf00 nop
+ 800394c: bcf8 pop {r3, r4, r5, r6, r7}
+ 800394e: bc08 pop {r3}
+ 8003950: 469e mov lr, r3
+ 8003952: 4770 bx lr
+
+08003954 <_fini>:
+ 8003954: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8003956: bf00 nop
+ 8003958: bcf8 pop {r3, r4, r5, r6, r7}
+ 800395a: bc08 pop {r3}
+ 800395c: 469e mov lr, r3
+ 800395e: 4770 bx lr
<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.access_port_id" value="0"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
-<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
+<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="true"/>
<intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{"fItems":[{"fIsFromMainTab":true,"fPath":"Debug/uart_test.elf","fProjectName":"uart_test","fPerformBuild":true,"fDownload":true,"fLoadSymbols":true}]}"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="system_reset"/>
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_0" value="Enabled=true:Address=test:Access=Read/Write:Size=Word:Function=Data Value"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_1" value="Enabled=false:Address=0x0:Access=Read/Write:Size=Word:Function=Data Value"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_2" value="Enabled=false:Address=0x0:Access=Read/Write:Size=Word:Function=Data Value"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.datatrace_3" value="Enabled=false:Address=0x0:Access=Read/Write:Size=Word:Function=Data Value"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.itmports" value="0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.itmports_priv" value="0:0:0:0"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.pc_sample" value="1:16384"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.timestamps" value="1:1"/>
+<stringAttribute key="com.st.stm32cube.ide.mcu.debug.swv.trace_events" value="Cpi=0:Exc=0:Sleep=0:Lsu=0:Fold=0:Exetrc=0"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
Mcu.Package=LQFP144
Mcu.Pin0=PC6
Mcu.Pin1=PC7
-Mcu.Pin2=VP_SYS_VS_Systick
-Mcu.Pin3=VP_TIM3_VS_ClockSourceINT
-Mcu.PinsNb=4
+Mcu.Pin2=PA13
+Mcu.Pin3=PA14
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.Pin5=VP_TIM3_VS_ClockSourceINT
+Mcu.PinsNb=6
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F767ZITx
NVIC.TIM3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.USART6_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
PC6.Mode=Asynchronous
PC6.Signal=USART6_TX
PC7.Mode=Asynchronous
projects / pioneer-stm32 / commitdiff
