Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 000027b0 080001f8 080001f8 000101f8 2**2
+ 1 .text 00002854 080001f8 080001f8 000101f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000028 080029a8 080029a8 000129a8 2**2
+ 2 .rodata 00000028 08002a4c 08002a4c 00012a4c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 080029d0 080029d0 0002000c 2**0
+ 3 .ARM.extab 00000000 08002a74 08002a74 0002000c 2**0
CONTENTS
- 4 .ARM 00000008 080029d0 080029d0 000129d0 2**2
+ 4 .ARM 00000008 08002a74 08002a74 00012a74 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 080029d8 080029d8 0002000c 2**0
+ 5 .preinit_array 00000000 08002a7c 08002a7c 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000004 080029d8 080029d8 000129d8 2**2
+ 6 .init_array 00000004 08002a7c 08002a7c 00012a7c 2**2
CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 080029dc 080029dc 000129dc 2**2
+ 7 .fini_array 00000004 08002a80 08002a80 00012a80 2**2
CONTENTS, ALLOC, LOAD, DATA
- 8 .data 0000000c 20000000 080029e0 00020000 2**2
+ 8 .data 0000000c 20000000 08002a84 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 000000a0 2000000c 080029ec 0002000c 2**2
+ 9 .bss 000000a0 2000000c 08002a90 0002000c 2**2
ALLOC
- 10 ._user_heap_stack 00000604 200000ac 080029ec 000200ac 2**0
+ 10 ._user_heap_stack 00000604 200000ac 08002a90 000200ac 2**0
ALLOC
11 .ARM.attributes 0000002e 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
- 12 .debug_info 00006b3d 00000000 00000000 0002003a 2**0
+ 12 .debug_info 00006bb7 00000000 00000000 0002003a 2**0
CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 00001227 00000000 00000000 00026b77 2**0
+ 13 .debug_abbrev 0000122e 00000000 00000000 00026bf1 2**0
CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000670 00000000 00000000 00027da0 2**3
+ 14 .debug_aranges 00000670 00000000 00000000 00027e20 2**3
CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 000005c8 00000000 00000000 00028410 2**3
+ 15 .debug_ranges 000005c8 00000000 00000000 00028490 2**3
CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 00024e43 00000000 00000000 000289d8 2**0
+ 16 .debug_macro 00024e43 00000000 00000000 00028a58 2**0
CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 00005b21 00000000 00000000 0004d81b 2**0
+ 17 .debug_line 00005b3e 00000000 00000000 0004d89b 2**0
CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000e7afa 00000000 00000000 0005333c 2**0
+ 18 .debug_str 000e7b3b 00000000 00000000 000533d9 2**0
CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 0013ae36 2**0
+ 19 .comment 0000007b 00000000 00000000 0013af14 2**0
CONTENTS, READONLY
- 20 .debug_frame 00001924 00000000 00000000 0013aeb4 2**2
+ 20 .debug_frame 00001924 00000000 00000000 0013af90 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
800020e: bd10 pop {r4, pc}
8000210: 2000000c .word 0x2000000c
8000214: 00000000 .word 0x00000000
- 8000218: 08002990 .word 0x08002990
+ 8000218: 08002a34 .word 0x08002a34
0800021c <frame_dummy>:
800021c: b508 push {r3, lr}
800022a: bd08 pop {r3, pc}
800022c: 00000000 .word 0x00000000
8000230: 20000010 .word 0x20000010
- 8000234: 08002990 .word 0x08002990
+ 8000234: 08002a34 .word 0x08002a34
08000238 <__aeabi_uldivmod>:
8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
int main(void)
{
8000538: b590 push {r4, r7, lr}
- 800053a: b089 sub sp, #36 ; 0x24
+ 800053a: b08d sub sp, #52 ; 0x34
800053c: af00 add r7, sp, #0
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
- 800053e: f000 f9e8 bl 8000912 <HAL_Init>
+ 800053e: f000 fa3a bl 80009b6 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
- 8000542: f000 f827 bl 8000594 <SystemClock_Config>
+ 8000542: f000 f84b bl 80005dc <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
- 8000546: f000 f8cf bl 80006e8 <MX_GPIO_Init>
+ 8000546: f000 f8f7 bl 8000738 <MX_GPIO_Init>
MX_USART6_UART_Init();
- 800054a: f000 f89d bl 8000688 <MX_USART6_UART_Init>
+ 800054a: f000 f8c1 bl 80006d0 <MX_USART6_UART_Init>
/* USER CODE BEGIN 2 */
char hello[] = "Hello world! \n";
- 800054e: 4b0e ldr r3, [pc, #56] ; (8000588 <main+0x50>)
- 8000550: f107 040c add.w r4, r7, #12
+ 800054e: 4b1e ldr r3, [pc, #120] ; (80005c8 <main+0x90>)
+ 8000550: f107 041c add.w r4, r7, #28
8000554: cb0f ldmia r3, {r0, r1, r2, r3}
8000556: c407 stmia r4!, {r0, r1, r2}
8000558: 8023 strh r3, [r4, #0]
800055a: 3402 adds r4, #2
800055c: 0c1b lsrs r3, r3, #16
800055e: 7023 strb r3, [r4, #0]
+ float delta_time;
+ } odometry_msg;
float odometry_values[3];
odometry_values[0] = 0.5;
8000560: f04f 537c mov.w r3, #1056964608 ; 0x3f000000
- 8000564: 603b str r3, [r7, #0]
+ 8000564: 613b str r3, [r7, #16]
odometry_values[1] = 1.5;
8000566: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000
- 800056a: 607b str r3, [r7, #4]
+ 800056a: 617b str r3, [r7, #20]
odometry_values[2] = 9.5;
- 800056c: 4b07 ldr r3, [pc, #28] ; (800058c <main+0x54>)
- 800056e: 60bb str r3, [r7, #8]
- uint8_t* buffer = &odometry_values;
- 8000570: 463b mov r3, r7
- 8000572: 61fb str r3, [r7, #28]
+ 800056c: 4b17 ldr r3, [pc, #92] ; (80005cc <main+0x94>)
+ 800056e: 61bb str r3, [r7, #24]
+
+ odometry_msg out_msg;
+ out_msg.angular_velocity = 0.2;
+ 8000570: 4b17 ldr r3, [pc, #92] ; (80005d0 <main+0x98>)
+ 8000572: 607b str r3, [r7, #4]
+ out_msg.linear_velocity = 1.5;
+ 8000574: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000
+ 8000578: 60bb str r3, [r7, #8]
+ out_msg.delta_time = 2.6;
+ 800057a: 4b16 ldr r3, [pc, #88] ; (80005d4 <main+0x9c>)
+ 800057c: 60fb str r3, [r7, #12]
+ uint8_t *buffer = &out_msg;
+ 800057e: 1d3b adds r3, r7, #4
+ 8000580: 62fb str r3, [r7, #44] ; 0x2c
+ /* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
- while (1)
- {
- HAL_UART_Transmit(&huart6, buffer, 12, 100);
- 8000574: 2364 movs r3, #100 ; 0x64
- 8000576: 220c movs r2, #12
- 8000578: 69f9 ldr r1, [r7, #28]
- 800057a: 4805 ldr r0, [pc, #20] ; (8000590 <main+0x58>)
- 800057c: f001 fd8c bl 8002098 <HAL_UART_Transmit>
-
- //HAL_UART_Transmit(&huart6, (uint8_t)* hello, 15, 100);
-
-
- HAL_Delay(100);
- 8000580: 2064 movs r0, #100 ; 0x64
- 8000582: f000 fa23 bl 80009cc <HAL_Delay>
- HAL_UART_Transmit(&huart6, buffer, 12, 100);
- 8000586: e7f5 b.n 8000574 <main+0x3c>
- 8000588: 080029a8 .word 0x080029a8
- 800058c: 41180000 .word 0x41180000
- 8000590: 20000028 .word 0x20000028
-
-08000594 <SystemClock_Config>:
+ while (1) {
+ HAL_UART_Transmit(&huart6, buffer, 12, 100);
+ 8000582: 2364 movs r3, #100 ; 0x64
+ 8000584: 220c movs r2, #12
+ 8000586: 6af9 ldr r1, [r7, #44] ; 0x2c
+ 8000588: 4813 ldr r0, [pc, #76] ; (80005d8 <main+0xa0>)
+ 800058a: f001 fdd7 bl 800213c <HAL_UART_Transmit>
+ out_msg.angular_velocity++;
+ 800058e: edd7 7a01 vldr s15, [r7, #4]
+ 8000592: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0
+ 8000596: ee77 7a87 vadd.f32 s15, s15, s14
+ 800059a: edc7 7a01 vstr s15, [r7, #4]
+ out_msg.linear_velocity++;
+ 800059e: edd7 7a02 vldr s15, [r7, #8]
+ 80005a2: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0
+ 80005a6: ee77 7a87 vadd.f32 s15, s15, s14
+ 80005aa: edc7 7a02 vstr s15, [r7, #8]
+ out_msg.delta_time++;
+ 80005ae: edd7 7a03 vldr s15, [r7, #12]
+ 80005b2: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0
+ 80005b6: ee77 7a87 vadd.f32 s15, s15, s14
+ 80005ba: edc7 7a03 vstr s15, [r7, #12]
+
+ //HAL_UART_Transmit(&huart6, (uint8_t)* hello, 15, 100);
+
+ HAL_Delay(100);
+ 80005be: 2064 movs r0, #100 ; 0x64
+ 80005c0: f000 fa56 bl 8000a70 <HAL_Delay>
+ HAL_UART_Transmit(&huart6, buffer, 12, 100);
+ 80005c4: e7dd b.n 8000582 <main+0x4a>
+ 80005c6: bf00 nop
+ 80005c8: 08002a4c .word 0x08002a4c
+ 80005cc: 41180000 .word 0x41180000
+ 80005d0: 3e4ccccd .word 0x3e4ccccd
+ 80005d4: 40266666 .word 0x40266666
+ 80005d8: 20000028 .word 0x20000028
+
+080005dc <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
- 8000594: b580 push {r7, lr}
- 8000596: b0b8 sub sp, #224 ; 0xe0
- 8000598: af00 add r7, sp, #0
+ 80005dc: b580 push {r7, lr}
+ 80005de: b0b8 sub sp, #224 ; 0xe0
+ 80005e0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 800059a: f107 03ac add.w r3, r7, #172 ; 0xac
- 800059e: 2234 movs r2, #52 ; 0x34
- 80005a0: 2100 movs r1, #0
- 80005a2: 4618 mov r0, r3
- 80005a4: f002 f9ec bl 8002980 <memset>
+ 80005e2: f107 03ac add.w r3, r7, #172 ; 0xac
+ 80005e6: 2234 movs r2, #52 ; 0x34
+ 80005e8: 2100 movs r1, #0
+ 80005ea: 4618 mov r0, r3
+ 80005ec: f002 fa1a bl 8002a24 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 80005a8: f107 0398 add.w r3, r7, #152 ; 0x98
- 80005ac: 2200 movs r2, #0
- 80005ae: 601a str r2, [r3, #0]
- 80005b0: 605a str r2, [r3, #4]
- 80005b2: 609a str r2, [r3, #8]
- 80005b4: 60da str r2, [r3, #12]
- 80005b6: 611a str r2, [r3, #16]
+ 80005f0: f107 0398 add.w r3, r7, #152 ; 0x98
+ 80005f4: 2200 movs r2, #0
+ 80005f6: 601a str r2, [r3, #0]
+ 80005f8: 605a str r2, [r3, #4]
+ 80005fa: 609a str r2, [r3, #8]
+ 80005fc: 60da str r2, [r3, #12]
+ 80005fe: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
- 80005b8: f107 0308 add.w r3, r7, #8
- 80005bc: 2290 movs r2, #144 ; 0x90
- 80005be: 2100 movs r1, #0
- 80005c0: 4618 mov r0, r3
- 80005c2: f002 f9dd bl 8002980 <memset>
+ 8000600: f107 0308 add.w r3, r7, #8
+ 8000604: 2290 movs r2, #144 ; 0x90
+ 8000606: 2100 movs r1, #0
+ 8000608: 4618 mov r0, r3
+ 800060a: f002 fa0b bl 8002a24 <memset>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
- 80005c6: 4b2e ldr r3, [pc, #184] ; (8000680 <SystemClock_Config+0xec>)
- 80005c8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80005ca: 4a2d ldr r2, [pc, #180] ; (8000680 <SystemClock_Config+0xec>)
- 80005cc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80005d0: 6413 str r3, [r2, #64] ; 0x40
- 80005d2: 4b2b ldr r3, [pc, #172] ; (8000680 <SystemClock_Config+0xec>)
- 80005d4: 6c1b ldr r3, [r3, #64] ; 0x40
- 80005d6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80005da: 607b str r3, [r7, #4]
- 80005dc: 687b ldr r3, [r7, #4]
+ 800060e: 4b2e ldr r3, [pc, #184] ; (80006c8 <SystemClock_Config+0xec>)
+ 8000610: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000612: 4a2d ldr r2, [pc, #180] ; (80006c8 <SystemClock_Config+0xec>)
+ 8000614: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000618: 6413 str r3, [r2, #64] ; 0x40
+ 800061a: 4b2b ldr r3, [pc, #172] ; (80006c8 <SystemClock_Config+0xec>)
+ 800061c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800061e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000622: 607b str r3, [r7, #4]
+ 8000624: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 80005de: 4b29 ldr r3, [pc, #164] ; (8000684 <SystemClock_Config+0xf0>)
- 80005e0: 681b ldr r3, [r3, #0]
- 80005e2: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 80005e6: 4a27 ldr r2, [pc, #156] ; (8000684 <SystemClock_Config+0xf0>)
- 80005e8: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 80005ec: 6013 str r3, [r2, #0]
- 80005ee: 4b25 ldr r3, [pc, #148] ; (8000684 <SystemClock_Config+0xf0>)
- 80005f0: 681b ldr r3, [r3, #0]
- 80005f2: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 80005f6: 603b str r3, [r7, #0]
- 80005f8: 683b ldr r3, [r7, #0]
+ 8000626: 4b29 ldr r3, [pc, #164] ; (80006cc <SystemClock_Config+0xf0>)
+ 8000628: 681b ldr r3, [r3, #0]
+ 800062a: f423 4340 bic.w r3, r3, #49152 ; 0xc000
+ 800062e: 4a27 ldr r2, [pc, #156] ; (80006cc <SystemClock_Config+0xf0>)
+ 8000630: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000634: 6013 str r3, [r2, #0]
+ 8000636: 4b25 ldr r3, [pc, #148] ; (80006cc <SystemClock_Config+0xf0>)
+ 8000638: 681b ldr r3, [r3, #0]
+ 800063a: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 800063e: 603b str r3, [r7, #0]
+ 8000640: 683b ldr r3, [r7, #0]
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 80005fa: 2302 movs r3, #2
- 80005fc: f8c7 30ac str.w r3, [r7, #172] ; 0xac
+ 8000642: 2302 movs r3, #2
+ 8000644: f8c7 30ac str.w r3, [r7, #172] ; 0xac
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8000600: 2301 movs r3, #1
- 8000602: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
+ 8000648: 2301 movs r3, #1
+ 800064a: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000606: 2310 movs r3, #16
- 8000608: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
+ 800064e: 2310 movs r3, #16
+ 8000650: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 800060c: 2300 movs r3, #0
- 800060e: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
+ 8000654: 2300 movs r3, #0
+ 8000656: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 8000612: f107 03ac add.w r3, r7, #172 ; 0xac
- 8000616: 4618 mov r0, r3
- 8000618: f000 fc8a bl 8000f30 <HAL_RCC_OscConfig>
- 800061c: 4603 mov r3, r0
- 800061e: 2b00 cmp r3, #0
- 8000620: d001 beq.n 8000626 <SystemClock_Config+0x92>
+ 800065a: f107 03ac add.w r3, r7, #172 ; 0xac
+ 800065e: 4618 mov r0, r3
+ 8000660: f000 fcb8 bl 8000fd4 <HAL_RCC_OscConfig>
+ 8000664: 4603 mov r3, r0
+ 8000666: 2b00 cmp r3, #0
+ 8000668: d001 beq.n 800066e <SystemClock_Config+0x92>
{
Error_Handler();
- 8000622: f000 f879 bl 8000718 <Error_Handler>
+ 800066a: f000 f889 bl 8000780 <Error_Handler>
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 8000626: 230f movs r3, #15
- 8000628: f8c7 3098 str.w r3, [r7, #152] ; 0x98
+ 800066e: 230f movs r3, #15
+ 8000670: f8c7 3098 str.w r3, [r7, #152] ; 0x98
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 800062c: 2300 movs r3, #0
- 800062e: f8c7 309c str.w r3, [r7, #156] ; 0x9c
+ 8000674: 2300 movs r3, #0
+ 8000676: f8c7 309c str.w r3, [r7, #156] ; 0x9c
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000632: 2300 movs r3, #0
- 8000634: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
+ 800067a: 2300 movs r3, #0
+ 800067c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8000638: 2300 movs r3, #0
- 800063a: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
+ 8000680: 2300 movs r3, #0
+ 8000682: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 800063e: 2300 movs r3, #0
- 8000640: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
+ 8000686: 2300 movs r3, #0
+ 8000688: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 8000644: f107 0398 add.w r3, r7, #152 ; 0x98
- 8000648: 2100 movs r1, #0
- 800064a: 4618 mov r0, r3
- 800064c: f000 fee2 bl 8001414 <HAL_RCC_ClockConfig>
- 8000650: 4603 mov r3, r0
- 8000652: 2b00 cmp r3, #0
- 8000654: d001 beq.n 800065a <SystemClock_Config+0xc6>
+ 800068c: f107 0398 add.w r3, r7, #152 ; 0x98
+ 8000690: 2100 movs r1, #0
+ 8000692: 4618 mov r0, r3
+ 8000694: f000 ff10 bl 80014b8 <HAL_RCC_ClockConfig>
+ 8000698: 4603 mov r3, r0
+ 800069a: 2b00 cmp r3, #0
+ 800069c: d001 beq.n 80006a2 <SystemClock_Config+0xc6>
{
Error_Handler();
- 8000656: f000 f85f bl 8000718 <Error_Handler>
+ 800069e: f000 f86f bl 8000780 <Error_Handler>
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
- 800065a: f44f 6300 mov.w r3, #2048 ; 0x800
- 800065e: 60bb str r3, [r7, #8]
+ 80006a2: f44f 6300 mov.w r3, #2048 ; 0x800
+ 80006a6: 60bb str r3, [r7, #8]
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
- 8000660: 2300 movs r3, #0
- 8000662: 663b str r3, [r7, #96] ; 0x60
+ 80006a8: 2300 movs r3, #0
+ 80006aa: 663b str r3, [r7, #96] ; 0x60
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
- 8000664: f107 0308 add.w r3, r7, #8
- 8000668: 4618 mov r0, r3
- 800066a: f001 f8a1 bl 80017b0 <HAL_RCCEx_PeriphCLKConfig>
- 800066e: 4603 mov r3, r0
- 8000670: 2b00 cmp r3, #0
- 8000672: d001 beq.n 8000678 <SystemClock_Config+0xe4>
+ 80006ac: f107 0308 add.w r3, r7, #8
+ 80006b0: 4618 mov r0, r3
+ 80006b2: f001 f8cf bl 8001854 <HAL_RCCEx_PeriphCLKConfig>
+ 80006b6: 4603 mov r3, r0
+ 80006b8: 2b00 cmp r3, #0
+ 80006ba: d001 beq.n 80006c0 <SystemClock_Config+0xe4>
{
Error_Handler();
- 8000674: f000 f850 bl 8000718 <Error_Handler>
+ 80006bc: f000 f860 bl 8000780 <Error_Handler>
}
}
- 8000678: bf00 nop
- 800067a: 37e0 adds r7, #224 ; 0xe0
- 800067c: 46bd mov sp, r7
- 800067e: bd80 pop {r7, pc}
- 8000680: 40023800 .word 0x40023800
- 8000684: 40007000 .word 0x40007000
-
-08000688 <MX_USART6_UART_Init>:
+ 80006c0: bf00 nop
+ 80006c2: 37e0 adds r7, #224 ; 0xe0
+ 80006c4: 46bd mov sp, r7
+ 80006c6: bd80 pop {r7, pc}
+ 80006c8: 40023800 .word 0x40023800
+ 80006cc: 40007000 .word 0x40007000
+
+080006d0 <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
- 8000688: b580 push {r7, lr}
- 800068a: af00 add r7, sp, #0
+ 80006d0: b580 push {r7, lr}
+ 80006d2: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
- 800068c: 4b14 ldr r3, [pc, #80] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 800068e: 4a15 ldr r2, [pc, #84] ; (80006e4 <MX_USART6_UART_Init+0x5c>)
- 8000690: 601a str r2, [r3, #0]
- huart6.Init.BaudRate = 9600;
- 8000692: 4b13 ldr r3, [pc, #76] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 8000694: f44f 5216 mov.w r2, #9600 ; 0x2580
- 8000698: 605a str r2, [r3, #4]
- huart6.Init.WordLength = UART_WORDLENGTH_8B;
- 800069a: 4b11 ldr r3, [pc, #68] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 800069c: 2200 movs r2, #0
- 800069e: 609a str r2, [r3, #8]
- huart6.Init.StopBits = UART_STOPBITS_1;
- 80006a0: 4b0f ldr r3, [pc, #60] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006a2: 2200 movs r2, #0
- 80006a4: 60da str r2, [r3, #12]
- huart6.Init.Parity = UART_PARITY_NONE;
- 80006a6: 4b0e ldr r3, [pc, #56] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006a8: 2200 movs r2, #0
- 80006aa: 611a str r2, [r3, #16]
+ 80006d4: 4b16 ldr r3, [pc, #88] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 80006d6: 4a17 ldr r2, [pc, #92] ; (8000734 <MX_USART6_UART_Init+0x64>)
+ 80006d8: 601a str r2, [r3, #0]
+ huart6.Init.BaudRate = 115200;
+ 80006da: 4b15 ldr r3, [pc, #84] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 80006dc: f44f 32e1 mov.w r2, #115200 ; 0x1c200
+ 80006e0: 605a str r2, [r3, #4]
+ huart6.Init.WordLength = UART_WORDLENGTH_9B;
+ 80006e2: 4b13 ldr r3, [pc, #76] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 80006e4: f44f 5280 mov.w r2, #4096 ; 0x1000
+ 80006e8: 609a str r2, [r3, #8]
+ huart6.Init.StopBits = UART_STOPBITS_2;
+ 80006ea: 4b11 ldr r3, [pc, #68] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 80006ec: f44f 5200 mov.w r2, #8192 ; 0x2000
+ 80006f0: 60da str r2, [r3, #12]
+ huart6.Init.Parity = UART_PARITY_ODD;
+ 80006f2: 4b0f ldr r3, [pc, #60] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 80006f4: f44f 62c0 mov.w r2, #1536 ; 0x600
+ 80006f8: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
- 80006ac: 4b0c ldr r3, [pc, #48] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006ae: 220c movs r2, #12
- 80006b0: 615a str r2, [r3, #20]
- huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 80006b2: 4b0b ldr r3, [pc, #44] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006b4: 2200 movs r2, #0
- 80006b6: 619a str r2, [r3, #24]
+ 80006fa: 4b0d ldr r3, [pc, #52] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 80006fc: 220c movs r2, #12
+ 80006fe: 615a str r2, [r3, #20]
+ huart6.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
+ 8000700: 4b0b ldr r3, [pc, #44] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 8000702: f44f 7240 mov.w r2, #768 ; 0x300
+ 8000706: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
- 80006b8: 4b09 ldr r3, [pc, #36] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006ba: 2200 movs r2, #0
- 80006bc: 61da str r2, [r3, #28]
+ 8000708: 4b09 ldr r3, [pc, #36] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 800070a: 2200 movs r2, #0
+ 800070c: 61da str r2, [r3, #28]
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 80006be: 4b08 ldr r3, [pc, #32] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006c0: 2200 movs r2, #0
- 80006c2: 621a str r2, [r3, #32]
+ 800070e: 4b08 ldr r3, [pc, #32] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 8000710: 2200 movs r2, #0
+ 8000712: 621a str r2, [r3, #32]
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 80006c4: 4b06 ldr r3, [pc, #24] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006c6: 2200 movs r2, #0
- 80006c8: 625a str r2, [r3, #36] ; 0x24
+ 8000714: 4b06 ldr r3, [pc, #24] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 8000716: 2200 movs r2, #0
+ 8000718: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart6) != HAL_OK)
- 80006ca: 4805 ldr r0, [pc, #20] ; (80006e0 <MX_USART6_UART_Init+0x58>)
- 80006cc: f001 fc96 bl 8001ffc <HAL_UART_Init>
- 80006d0: 4603 mov r3, r0
- 80006d2: 2b00 cmp r3, #0
- 80006d4: d001 beq.n 80006da <MX_USART6_UART_Init+0x52>
+ 800071a: 4805 ldr r0, [pc, #20] ; (8000730 <MX_USART6_UART_Init+0x60>)
+ 800071c: f001 fcc0 bl 80020a0 <HAL_UART_Init>
+ 8000720: 4603 mov r3, r0
+ 8000722: 2b00 cmp r3, #0
+ 8000724: d001 beq.n 800072a <MX_USART6_UART_Init+0x5a>
{
Error_Handler();
- 80006d6: f000 f81f bl 8000718 <Error_Handler>
+ 8000726: f000 f82b bl 8000780 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
- 80006da: bf00 nop
- 80006dc: bd80 pop {r7, pc}
- 80006de: bf00 nop
- 80006e0: 20000028 .word 0x20000028
- 80006e4: 40011400 .word 0x40011400
+ 800072a: bf00 nop
+ 800072c: bd80 pop {r7, pc}
+ 800072e: bf00 nop
+ 8000730: 20000028 .word 0x20000028
+ 8000734: 40011400 .word 0x40011400
-080006e8 <MX_GPIO_Init>:
+08000738 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
- 80006e8: b480 push {r7}
- 80006ea: b083 sub sp, #12
- 80006ec: af00 add r7, sp, #0
+ 8000738: b480 push {r7}
+ 800073a: b083 sub sp, #12
+ 800073c: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ 800073e: 4b0f ldr r3, [pc, #60] ; (800077c <MX_GPIO_Init+0x44>)
+ 8000740: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000742: 4a0e ldr r2, [pc, #56] ; (800077c <MX_GPIO_Init+0x44>)
+ 8000744: f043 0340 orr.w r3, r3, #64 ; 0x40
+ 8000748: 6313 str r3, [r2, #48] ; 0x30
+ 800074a: 4b0c ldr r3, [pc, #48] ; (800077c <MX_GPIO_Init+0x44>)
+ 800074c: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800074e: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8000752: 607b str r3, [r7, #4]
+ 8000754: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOC_CLK_ENABLE();
- 80006ee: 4b09 ldr r3, [pc, #36] ; (8000714 <MX_GPIO_Init+0x2c>)
- 80006f0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80006f2: 4a08 ldr r2, [pc, #32] ; (8000714 <MX_GPIO_Init+0x2c>)
- 80006f4: f043 0304 orr.w r3, r3, #4
- 80006f8: 6313 str r3, [r2, #48] ; 0x30
- 80006fa: 4b06 ldr r3, [pc, #24] ; (8000714 <MX_GPIO_Init+0x2c>)
- 80006fc: 6b1b ldr r3, [r3, #48] ; 0x30
- 80006fe: f003 0304 and.w r3, r3, #4
- 8000702: 607b str r3, [r7, #4]
- 8000704: 687b ldr r3, [r7, #4]
+ 8000756: 4b09 ldr r3, [pc, #36] ; (800077c <MX_GPIO_Init+0x44>)
+ 8000758: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800075a: 4a08 ldr r2, [pc, #32] ; (800077c <MX_GPIO_Init+0x44>)
+ 800075c: f043 0304 orr.w r3, r3, #4
+ 8000760: 6313 str r3, [r2, #48] ; 0x30
+ 8000762: 4b06 ldr r3, [pc, #24] ; (800077c <MX_GPIO_Init+0x44>)
+ 8000764: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000766: f003 0304 and.w r3, r3, #4
+ 800076a: 603b str r3, [r7, #0]
+ 800076c: 683b ldr r3, [r7, #0]
}
- 8000706: bf00 nop
- 8000708: 370c adds r7, #12
- 800070a: 46bd mov sp, r7
- 800070c: f85d 7b04 ldr.w r7, [sp], #4
- 8000710: 4770 bx lr
- 8000712: bf00 nop
- 8000714: 40023800 .word 0x40023800
-
-08000718 <Error_Handler>:
+ 800076e: bf00 nop
+ 8000770: 370c adds r7, #12
+ 8000772: 46bd mov sp, r7
+ 8000774: f85d 7b04 ldr.w r7, [sp], #4
+ 8000778: 4770 bx lr
+ 800077a: bf00 nop
+ 800077c: 40023800 .word 0x40023800
+
+08000780 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
- 8000718: b480 push {r7}
- 800071a: af00 add r7, sp, #0
+ 8000780: b480 push {r7}
+ 8000782: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
- 800071c: bf00 nop
- 800071e: 46bd mov sp, r7
- 8000720: f85d 7b04 ldr.w r7, [sp], #4
- 8000724: 4770 bx lr
+ 8000784: bf00 nop
+ 8000786: 46bd mov sp, r7
+ 8000788: f85d 7b04 ldr.w r7, [sp], #4
+ 800078c: 4770 bx lr
...
-08000728 <HAL_MspInit>:
+08000790 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
- 8000728: b480 push {r7}
- 800072a: b083 sub sp, #12
- 800072c: af00 add r7, sp, #0
+ 8000790: b480 push {r7}
+ 8000792: b083 sub sp, #12
+ 8000794: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
- 800072e: 4b0f ldr r3, [pc, #60] ; (800076c <HAL_MspInit+0x44>)
- 8000730: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000732: 4a0e ldr r2, [pc, #56] ; (800076c <HAL_MspInit+0x44>)
- 8000734: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8000738: 6413 str r3, [r2, #64] ; 0x40
- 800073a: 4b0c ldr r3, [pc, #48] ; (800076c <HAL_MspInit+0x44>)
- 800073c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800073e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000742: 607b str r3, [r7, #4]
- 8000744: 687b ldr r3, [r7, #4]
+ 8000796: 4b0f ldr r3, [pc, #60] ; (80007d4 <HAL_MspInit+0x44>)
+ 8000798: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800079a: 4a0e ldr r2, [pc, #56] ; (80007d4 <HAL_MspInit+0x44>)
+ 800079c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 80007a0: 6413 str r3, [r2, #64] ; 0x40
+ 80007a2: 4b0c ldr r3, [pc, #48] ; (80007d4 <HAL_MspInit+0x44>)
+ 80007a4: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80007a6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 80007aa: 607b str r3, [r7, #4]
+ 80007ac: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 8000746: 4b09 ldr r3, [pc, #36] ; (800076c <HAL_MspInit+0x44>)
- 8000748: 6c5b ldr r3, [r3, #68] ; 0x44
- 800074a: 4a08 ldr r2, [pc, #32] ; (800076c <HAL_MspInit+0x44>)
- 800074c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000750: 6453 str r3, [r2, #68] ; 0x44
- 8000752: 4b06 ldr r3, [pc, #24] ; (800076c <HAL_MspInit+0x44>)
- 8000754: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000756: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 800075a: 603b str r3, [r7, #0]
- 800075c: 683b ldr r3, [r7, #0]
+ 80007ae: 4b09 ldr r3, [pc, #36] ; (80007d4 <HAL_MspInit+0x44>)
+ 80007b0: 6c5b ldr r3, [r3, #68] ; 0x44
+ 80007b2: 4a08 ldr r2, [pc, #32] ; (80007d4 <HAL_MspInit+0x44>)
+ 80007b4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 80007b8: 6453 str r3, [r2, #68] ; 0x44
+ 80007ba: 4b06 ldr r3, [pc, #24] ; (80007d4 <HAL_MspInit+0x44>)
+ 80007bc: 6c5b ldr r3, [r3, #68] ; 0x44
+ 80007be: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 80007c2: 603b str r3, [r7, #0]
+ 80007c4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
- 800075e: bf00 nop
- 8000760: 370c adds r7, #12
- 8000762: 46bd mov sp, r7
- 8000764: f85d 7b04 ldr.w r7, [sp], #4
- 8000768: 4770 bx lr
- 800076a: bf00 nop
- 800076c: 40023800 .word 0x40023800
-
-08000770 <HAL_UART_MspInit>:
+ 80007c6: bf00 nop
+ 80007c8: 370c adds r7, #12
+ 80007ca: 46bd mov sp, r7
+ 80007cc: f85d 7b04 ldr.w r7, [sp], #4
+ 80007d0: 4770 bx lr
+ 80007d2: bf00 nop
+ 80007d4: 40023800 .word 0x40023800
+
+080007d8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
- 8000770: b580 push {r7, lr}
- 8000772: b08a sub sp, #40 ; 0x28
- 8000774: af00 add r7, sp, #0
- 8000776: 6078 str r0, [r7, #4]
+ 80007d8: b580 push {r7, lr}
+ 80007da: b08a sub sp, #40 ; 0x28
+ 80007dc: af00 add r7, sp, #0
+ 80007de: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8000778: f107 0314 add.w r3, r7, #20
- 800077c: 2200 movs r2, #0
- 800077e: 601a str r2, [r3, #0]
- 8000780: 605a str r2, [r3, #4]
- 8000782: 609a str r2, [r3, #8]
- 8000784: 60da str r2, [r3, #12]
- 8000786: 611a str r2, [r3, #16]
+ 80007e0: f107 0314 add.w r3, r7, #20
+ 80007e4: 2200 movs r2, #0
+ 80007e6: 601a str r2, [r3, #0]
+ 80007e8: 605a str r2, [r3, #4]
+ 80007ea: 609a str r2, [r3, #8]
+ 80007ec: 60da str r2, [r3, #12]
+ 80007ee: 611a str r2, [r3, #16]
if(huart->Instance==USART6)
- 8000788: 687b ldr r3, [r7, #4]
- 800078a: 681b ldr r3, [r3, #0]
- 800078c: 4a17 ldr r2, [pc, #92] ; (80007ec <HAL_UART_MspInit+0x7c>)
- 800078e: 4293 cmp r3, r2
- 8000790: d127 bne.n 80007e2 <HAL_UART_MspInit+0x72>
+ 80007f0: 687b ldr r3, [r7, #4]
+ 80007f2: 681b ldr r3, [r3, #0]
+ 80007f4: 4a25 ldr r2, [pc, #148] ; (800088c <HAL_UART_MspInit+0xb4>)
+ 80007f6: 4293 cmp r3, r2
+ 80007f8: d144 bne.n 8000884 <HAL_UART_MspInit+0xac>
{
/* USER CODE BEGIN USART6_MspInit 0 */
/* USER CODE END USART6_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART6_CLK_ENABLE();
- 8000792: 4b17 ldr r3, [pc, #92] ; (80007f0 <HAL_UART_MspInit+0x80>)
- 8000794: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000796: 4a16 ldr r2, [pc, #88] ; (80007f0 <HAL_UART_MspInit+0x80>)
- 8000798: f043 0320 orr.w r3, r3, #32
- 800079c: 6453 str r3, [r2, #68] ; 0x44
- 800079e: 4b14 ldr r3, [pc, #80] ; (80007f0 <HAL_UART_MspInit+0x80>)
- 80007a0: 6c5b ldr r3, [r3, #68] ; 0x44
- 80007a2: f003 0320 and.w r3, r3, #32
- 80007a6: 613b str r3, [r7, #16]
- 80007a8: 693b ldr r3, [r7, #16]
+ 80007fa: 4b25 ldr r3, [pc, #148] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 80007fc: 6c5b ldr r3, [r3, #68] ; 0x44
+ 80007fe: 4a24 ldr r2, [pc, #144] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 8000800: f043 0320 orr.w r3, r3, #32
+ 8000804: 6453 str r3, [r2, #68] ; 0x44
+ 8000806: 4b22 ldr r3, [pc, #136] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 8000808: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800080a: f003 0320 and.w r3, r3, #32
+ 800080e: 613b str r3, [r7, #16]
+ 8000810: 693b ldr r3, [r7, #16]
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ 8000812: 4b1f ldr r3, [pc, #124] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 8000814: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000816: 4a1e ldr r2, [pc, #120] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 8000818: f043 0340 orr.w r3, r3, #64 ; 0x40
+ 800081c: 6313 str r3, [r2, #48] ; 0x30
+ 800081e: 4b1c ldr r3, [pc, #112] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 8000820: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000822: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8000826: 60fb str r3, [r7, #12]
+ 8000828: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOC_CLK_ENABLE();
- 80007aa: 4b11 ldr r3, [pc, #68] ; (80007f0 <HAL_UART_MspInit+0x80>)
- 80007ac: 6b1b ldr r3, [r3, #48] ; 0x30
- 80007ae: 4a10 ldr r2, [pc, #64] ; (80007f0 <HAL_UART_MspInit+0x80>)
- 80007b0: f043 0304 orr.w r3, r3, #4
- 80007b4: 6313 str r3, [r2, #48] ; 0x30
- 80007b6: 4b0e ldr r3, [pc, #56] ; (80007f0 <HAL_UART_MspInit+0x80>)
- 80007b8: 6b1b ldr r3, [r3, #48] ; 0x30
- 80007ba: f003 0304 and.w r3, r3, #4
- 80007be: 60fb str r3, [r7, #12]
- 80007c0: 68fb ldr r3, [r7, #12]
- /**USART6 GPIO Configuration
+ 800082a: 4b19 ldr r3, [pc, #100] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 800082c: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800082e: 4a18 ldr r2, [pc, #96] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 8000830: f043 0304 orr.w r3, r3, #4
+ 8000834: 6313 str r3, [r2, #48] ; 0x30
+ 8000836: 4b16 ldr r3, [pc, #88] ; (8000890 <HAL_UART_MspInit+0xb8>)
+ 8000838: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800083a: f003 0304 and.w r3, r3, #4
+ 800083e: 60bb str r3, [r7, #8]
+ 8000840: 68bb ldr r3, [r7, #8]
+ PG8 ------> USART6_RTS
PC6 ------> USART6_TX
- PC7 ------> USART6_RX
+ PC7 ------> USART6_RX
+ PG13 ------> USART6_CTS
*/
+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_13;
+ 8000842: f44f 5304 mov.w r3, #8448 ; 0x2100
+ 8000846: 617b str r3, [r7, #20]
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8000848: 2302 movs r3, #2
+ 800084a: 61bb str r3, [r7, #24]
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800084c: 2300 movs r3, #0
+ 800084e: 61fb str r3, [r7, #28]
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000850: 2303 movs r3, #3
+ 8000852: 623b str r3, [r7, #32]
+ GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
+ 8000854: 2308 movs r3, #8
+ 8000856: 627b str r3, [r7, #36] ; 0x24
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+ 8000858: f107 0314 add.w r3, r7, #20
+ 800085c: 4619 mov r1, r3
+ 800085e: 480d ldr r0, [pc, #52] ; (8000894 <HAL_UART_MspInit+0xbc>)
+ 8000860: f000 fa0e bl 8000c80 <HAL_GPIO_Init>
+
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 80007c2: 23c0 movs r3, #192 ; 0xc0
- 80007c4: 617b str r3, [r7, #20]
+ 8000864: 23c0 movs r3, #192 ; 0xc0
+ 8000866: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 80007c6: 2302 movs r3, #2
- 80007c8: 61bb str r3, [r7, #24]
+ 8000868: 2302 movs r3, #2
+ 800086a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80007ca: 2300 movs r3, #0
- 80007cc: 61fb str r3, [r7, #28]
+ 800086c: 2300 movs r3, #0
+ 800086e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 80007ce: 2303 movs r3, #3
- 80007d0: 623b str r3, [r7, #32]
+ 8000870: 2303 movs r3, #3
+ 8000872: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
- 80007d2: 2308 movs r3, #8
- 80007d4: 627b str r3, [r7, #36] ; 0x24
+ 8000874: 2308 movs r3, #8
+ 8000876: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 80007d6: f107 0314 add.w r3, r7, #20
- 80007da: 4619 mov r1, r3
- 80007dc: 4805 ldr r0, [pc, #20] ; (80007f4 <HAL_UART_MspInit+0x84>)
- 80007de: f000 f9fd bl 8000bdc <HAL_GPIO_Init>
+ 8000878: f107 0314 add.w r3, r7, #20
+ 800087c: 4619 mov r1, r3
+ 800087e: 4806 ldr r0, [pc, #24] ; (8000898 <HAL_UART_MspInit+0xc0>)
+ 8000880: f000 f9fe bl 8000c80 <HAL_GPIO_Init>
/* USER CODE BEGIN USART6_MspInit 1 */
/* USER CODE END USART6_MspInit 1 */
}
}
- 80007e2: bf00 nop
- 80007e4: 3728 adds r7, #40 ; 0x28
- 80007e6: 46bd mov sp, r7
- 80007e8: bd80 pop {r7, pc}
- 80007ea: bf00 nop
- 80007ec: 40011400 .word 0x40011400
- 80007f0: 40023800 .word 0x40023800
- 80007f4: 40020800 .word 0x40020800
-
-080007f8 <NMI_Handler>:
+ 8000884: bf00 nop
+ 8000886: 3728 adds r7, #40 ; 0x28
+ 8000888: 46bd mov sp, r7
+ 800088a: bd80 pop {r7, pc}
+ 800088c: 40011400 .word 0x40011400
+ 8000890: 40023800 .word 0x40023800
+ 8000894: 40021800 .word 0x40021800
+ 8000898: 40020800 .word 0x40020800
+
+0800089c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
- 80007f8: b480 push {r7}
- 80007fa: af00 add r7, sp, #0
+ 800089c: b480 push {r7}
+ 800089e: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
- 80007fc: bf00 nop
- 80007fe: 46bd mov sp, r7
- 8000800: f85d 7b04 ldr.w r7, [sp], #4
- 8000804: 4770 bx lr
+ 80008a0: bf00 nop
+ 80008a2: 46bd mov sp, r7
+ 80008a4: f85d 7b04 ldr.w r7, [sp], #4
+ 80008a8: 4770 bx lr
-08000806 <HardFault_Handler>:
+080008aa <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
- 8000806: b480 push {r7}
- 8000808: af00 add r7, sp, #0
+ 80008aa: b480 push {r7}
+ 80008ac: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
- 800080a: e7fe b.n 800080a <HardFault_Handler+0x4>
+ 80008ae: e7fe b.n 80008ae <HardFault_Handler+0x4>
-0800080c <MemManage_Handler>:
+080008b0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
- 800080c: b480 push {r7}
- 800080e: af00 add r7, sp, #0
+ 80008b0: b480 push {r7}
+ 80008b2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
- 8000810: e7fe b.n 8000810 <MemManage_Handler+0x4>
+ 80008b4: e7fe b.n 80008b4 <MemManage_Handler+0x4>
-08000812 <BusFault_Handler>:
+080008b6 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
- 8000812: b480 push {r7}
- 8000814: af00 add r7, sp, #0
+ 80008b6: b480 push {r7}
+ 80008b8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
- 8000816: e7fe b.n 8000816 <BusFault_Handler+0x4>
+ 80008ba: e7fe b.n 80008ba <BusFault_Handler+0x4>
-08000818 <UsageFault_Handler>:
+080008bc <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
- 8000818: b480 push {r7}
- 800081a: af00 add r7, sp, #0
+ 80008bc: b480 push {r7}
+ 80008be: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
- 800081c: e7fe b.n 800081c <UsageFault_Handler+0x4>
+ 80008c0: e7fe b.n 80008c0 <UsageFault_Handler+0x4>
-0800081e <SVC_Handler>:
+080008c2 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
- 800081e: b480 push {r7}
- 8000820: af00 add r7, sp, #0
+ 80008c2: b480 push {r7}
+ 80008c4: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
- 8000822: bf00 nop
- 8000824: 46bd mov sp, r7
- 8000826: f85d 7b04 ldr.w r7, [sp], #4
- 800082a: 4770 bx lr
+ 80008c6: bf00 nop
+ 80008c8: 46bd mov sp, r7
+ 80008ca: f85d 7b04 ldr.w r7, [sp], #4
+ 80008ce: 4770 bx lr
-0800082c <DebugMon_Handler>:
+080008d0 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
- 800082c: b480 push {r7}
- 800082e: af00 add r7, sp, #0
+ 80008d0: b480 push {r7}
+ 80008d2: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
- 8000830: bf00 nop
- 8000832: 46bd mov sp, r7
- 8000834: f85d 7b04 ldr.w r7, [sp], #4
- 8000838: 4770 bx lr
+ 80008d4: bf00 nop
+ 80008d6: 46bd mov sp, r7
+ 80008d8: f85d 7b04 ldr.w r7, [sp], #4
+ 80008dc: 4770 bx lr
-080008
3a <PendSV_Handler>:
+080008
de <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
- 800083a: b480 push {r7}
- 800083c: af00 add r7, sp, #0
+ 80008de: b480 push {r7}
+ 80008e0: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
- 800083e: bf00 nop
- 8000840: 46bd mov sp, r7
- 8000842: f85d 7b04 ldr.w r7, [sp], #4
- 8000846: 4770 bx lr
+ 80008e2: bf00 nop
+ 80008e4: 46bd mov sp, r7
+ 80008e6: f85d 7b04 ldr.w r7, [sp], #4
+ 80008ea: 4770 bx lr
-08000848 <SysTick_Handler>:
+080008ec <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
- 8000848: b580 push {r7, lr}
- 800084a: af00 add r7, sp, #0
+ 80008ec: b580 push {r7, lr}
+ 80008ee: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
- 800084c: f000 f89e bl 800098c <HAL_IncTick>
+ 80008f0: f000 f89e bl 8000a30 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
- 8000850: bf00 nop
- 8000852: bd80 pop {r7, pc}
+ 80008f4: bf00 nop
+ 80008f6: bd80 pop {r7, pc}
-08000854 <SystemInit>:
+080008f8 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
- 8000854: b480 push {r7}
- 8000856: af00 add r7, sp, #0
+ 80008f8: b480 push {r7}
+ 80008fa: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 8000858: 4b15 ldr r3, [pc, #84] ; (80008b0 <SystemInit+0x5c>)
- 800085a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 800085e: 4a14 ldr r2, [pc, #80] ; (80008b0 <SystemInit+0x5c>)
- 8000860: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 8000864: f8c2 3088 str.w r3, [r2, #136] ; 0x88
+ 80008fc: 4b15 ldr r3, [pc, #84] ; (8000954 <SystemInit+0x5c>)
+ 80008fe: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8000902: 4a14 ldr r2, [pc, #80] ; (8000954 <SystemInit+0x5c>)
+ 8000904: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
+ 8000908: f8c2 3088 str.w r3, [r2, #136] ; 0x88
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
- 8000868: 4b12 ldr r3, [pc, #72] ; (80008b4 <SystemInit+0x60>)
- 800086a: 681b ldr r3, [r3, #0]
- 800086c: 4a11 ldr r2, [pc, #68] ; (80008b4 <SystemInit+0x60>)
- 800086e: f043 0301 orr.w r3, r3, #1
- 8000872: 6013 str r3, [r2, #0]
+ 800090c: 4b12 ldr r3, [pc, #72] ; (8000958 <SystemInit+0x60>)
+ 800090e: 681b ldr r3, [r3, #0]
+ 8000910: 4a11 ldr r2, [pc, #68] ; (8000958 <SystemInit+0x60>)
+ 8000912: f043 0301 orr.w r3, r3, #1
+ 8000916: 6013 str r3, [r2, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
- 8000874: 4b0f ldr r3, [pc, #60] ; (80008b4 <SystemInit+0x60>)
- 8000876: 2200 movs r2, #0
- 8000878: 609a str r2, [r3, #8]
+ 8000918: 4b0f ldr r3, [pc, #60] ; (8000958 <SystemInit+0x60>)
+ 800091a: 2200 movs r2, #0
+ 800091c: 609a str r2, [r3, #8]
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
- 800087a: 4b0e ldr r3, [pc, #56] ; (80008b4 <SystemInit+0x60>)
- 800087c: 681a ldr r2, [r3, #0]
- 800087e: 490d ldr r1, [pc, #52] ; (80008b4 <SystemInit+0x60>)
- 8000880: 4b0d ldr r3, [pc, #52] ; (80008b8 <SystemInit+0x64>)
- 8000882: 4013 ands r3, r2
- 8000884: 600b str r3, [r1, #0]
+ 800091e: 4b0e ldr r3, [pc, #56] ; (8000958 <SystemInit+0x60>)
+ 8000920: 681a ldr r2, [r3, #0]
+ 8000922: 490d ldr r1, [pc, #52] ; (8000958 <SystemInit+0x60>)
+ 8000924: 4b0d ldr r3, [pc, #52] ; (800095c <SystemInit+0x64>)
+ 8000926: 4013 ands r3, r2
+ 8000928: 600b str r3, [r1, #0]
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
- 8000886: 4b0b ldr r3, [pc, #44] ; (80008b4 <SystemInit+0x60>)
- 8000888: 4a0c ldr r2, [pc, #48] ; (80008bc <SystemInit+0x68>)
- 800088a: 605a str r2, [r3, #4]
+ 800092a: 4b0b ldr r3, [pc, #44] ; (8000958 <SystemInit+0x60>)
+ 800092c: 4a0c ldr r2, [pc, #48] ; (8000960 <SystemInit+0x68>)
+ 800092e: 605a str r2, [r3, #4]
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
- 800088c: 4b09 ldr r3, [pc, #36] ; (80008b4 <SystemInit+0x60>)
- 800088e: 681b ldr r3, [r3, #0]
- 8000890: 4a08 ldr r2, [pc, #32] ; (80008b4 <SystemInit+0x60>)
- 8000892: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8000896: 6013 str r3, [r2, #0]
+ 8000930: 4b09 ldr r3, [pc, #36] ; (8000958 <SystemInit+0x60>)
+ 8000932: 681b ldr r3, [r3, #0]
+ 8000934: 4a08 ldr r2, [pc, #32] ; (8000958 <SystemInit+0x60>)
+ 8000936: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 800093a: 6013 str r3, [r2, #0]
/* Disable all interrupts */
RCC->CIR = 0x00000000;
- 8000898: 4b06 ldr r3, [pc, #24] ; (80008b4 <SystemInit+0x60>)
- 800089a: 2200 movs r2, #0
- 800089c: 60da str r2, [r3, #12]
+ 800093c: 4b06 ldr r3, [pc, #24] ; (8000958 <SystemInit+0x60>)
+ 800093e: 2200 movs r2, #0
+ 8000940: 60da str r2, [r3, #12]
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 800089e: 4b04 ldr r3, [pc, #16] ; (80008b0 <SystemInit+0x5c>)
- 80008a0: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 80008a4: 609a str r2, [r3, #8]
+ 8000942: 4b04 ldr r3, [pc, #16] ; (8000954 <SystemInit+0x5c>)
+ 8000944: f04f 6200 mov.w r2, #134217728 ; 0x8000000
+ 8000948: 609a str r2, [r3, #8]
#endif
}
- 80008a6: bf00 nop
- 80008a8: 46bd mov sp, r7
- 80008aa: f85d 7b04 ldr.w r7, [sp], #4
- 80008ae: 4770 bx lr
- 80008b0: e000ed00 .word 0xe000ed00
- 80008b4: 40023800 .word 0x40023800
- 80008b8: fef6ffff .word 0xfef6ffff
- 80008bc: 24003010 .word 0x24003010
+ 800094a: bf00 nop
+ 800094c: 46bd mov sp, r7
+ 800094e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000952: 4770 bx lr
+ 8000954: e000ed00 .word 0xe000ed00
+ 8000958: 40023800 .word 0x40023800
+ 800095c: fef6ffff .word 0xfef6ffff
+ 8000960: 24003010 .word 0x24003010
-080008c0 <Reset_Handler>:
+08000964 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
- 80008c0: f8df d034 ldr.w sp, [pc, #52] ; 80008f8 <LoopFillZerobss+0x14>
+ 8000964: f8df d034 ldr.w sp, [pc, #52] ; 800099c <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
- 80008c4: 2100 movs r1, #0
+ 8000968: 2100 movs r1, #0
b LoopCopyDataInit
- 80008c6: e003 b.n 80008d0 <LoopCopyDataInit>
+ 800096a: e003 b.n 8000974 <LoopCopyDataInit>
-080008c8 <CopyDataInit>:
+0800096c <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
- 80008c8: 4b0c ldr r3, [pc, #48] ; (80008fc <LoopFillZerobss+0x18>)
+ 800096c: 4b0c ldr r3, [pc, #48] ; (80009a0 <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
- 80008ca: 585b ldr r3, [r3, r1]
+ 800096e: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
- 80008cc: 5043 str r3, [r0, r1]
+ 8000970: 5043 str r3, [r0, r1]
adds r1, r1, #4
- 80008ce: 3104 adds r1, #4
+ 8000972: 3104 adds r1, #4
-080008d0 <LoopCopyDataInit>:
+08000974 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
- 80008d0: 480b ldr r0, [pc, #44] ; (8000900 <LoopFillZerobss+0x1c>)
+ 8000974: 480b ldr r0, [pc, #44] ; (80009a4 <LoopFillZerobss+0x1c>)
ldr r3, =_edata
- 80008d2: 4b0c ldr r3, [pc, #48] ; (8000904 <LoopFillZerobss+0x20>)
+ 8000976: 4b0c ldr r3, [pc, #48] ; (80009a8 <LoopFillZerobss+0x20>)
adds r2, r0, r1
- 80008d4: 1842 adds r2, r0, r1
+ 8000978: 1842 adds r2, r0, r1
cmp r2, r3
- 80008d6: 429a cmp r2, r3
+ 800097a: 429a cmp r2, r3
bcc CopyDataInit
- 80008d8: d3f6 bcc.n 80008c8 <CopyDataInit>
+ 800097c: d3f6 bcc.n 800096c <CopyDataInit>
ldr r2, =_sbss
- 80008da: 4a0b ldr r2, [pc, #44] ; (8000908 <LoopFillZerobss+0x24>)
+ 800097e: 4a0b ldr r2, [pc, #44] ; (80009ac <LoopFillZerobss+0x24>)
b LoopFillZerobss
- 80008dc: e002 b.n 80008e4 <LoopFillZerobss>
+ 8000980: e002 b.n 8000988 <LoopFillZerobss>
-080008de <FillZerobss>:
+08000982 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
- 80008de: 2300 movs r3, #0
+ 8000982: 2300 movs r3, #0
str r3, [r2], #4
- 80008e0: f842 3b04 str.w r3, [r2], #4
+ 8000984: f842 3b04 str.w r3, [r2], #4
-080008e4 <LoopFillZerobss>:
+08000988 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
- 80008e4: 4b09 ldr r3, [pc, #36] ; (800090c <LoopFillZerobss+0x28>)
+ 8000988: 4b09 ldr r3, [pc, #36] ; (80009b0 <LoopFillZerobss+0x28>)
cmp r2, r3
- 80008e6: 429a cmp r2, r3
+ 800098a: 429a cmp r2, r3
bcc FillZerobss
- 80008e8: d3f9 bcc.n 80008de <FillZerobss>
+ 800098c: d3f9 bcc.n 8000982 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
- 80008ea: f7ff ffb3 bl 8000854 <SystemInit>
+ 800098e: f7ff ffb3 bl 80008f8 <SystemInit>
/* Call static constructors */
bl __libc_init_array
- 80008ee: f002 f823 bl 8002938 <__libc_init_array>
+ 8000992: f002 f823 bl 80029dc <__libc_init_array>
/* Call the application's entry point.*/
bl main
- 80008f2: f7ff fe21 bl 8000538 <main>
+ 8000996: f7ff fdcf bl 8000538 <main>
bx lr
- 80008f6: 4770 bx lr
+ 800099a: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
- 80008f8: 20080000 .word 0x20080000
+ 800099c: 20080000 .word 0x20080000
ldr r3, =_sidata
- 80008fc: 080029e0 .word 0x080029e0
+ 80009a0: 08002a84 .word 0x08002a84
ldr r0, =_sdata
- 8000900: 20000000 .word 0x20000000
+ 80009a4: 20000000 .word 0x20000000
ldr r3, =_edata
- 8000904: 2000000c .word 0x2000000c
+ 80009a8: 2000000c .word 0x2000000c
ldr r2, =_sbss
- 8000908: 2000000c .word 0x2000000c
+ 80009ac: 2000000c .word 0x2000000c
ldr r3, = _ebss
- 800090c: 200000ac .word 0x200000ac
+ 80009b0: 200000ac .word 0x200000ac
-080009
10 <ADC_IRQHandler>:
+080009
b4 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 80009
10: e7fe b.n 8000910 <ADC_IRQHandler>
+ 80009
b4: e7fe b.n 80009b4 <ADC_IRQHandler>
-08000912 <HAL_Init>:
+080009b6 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
- 8000912: b580 push {r7, lr}
- 8000914: af00 add r7, sp, #0
+ 80009b6: b580 push {r7, lr}
+ 80009b8: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8000916: 2003 movs r0, #3
- 8000918: f000 f92c bl 8000b74 <HAL_NVIC_SetPriorityGrouping>
+ 80009ba: 2003 movs r0, #3
+ 80009bc: f000 f92c bl 8000c18 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
- 800091c: 2000 movs r0, #0
- 800091e: f000 f805 bl 800092c <HAL_InitTick>
+ 80009c0: 2000 movs r0, #0
+ 80009c2: f000 f805 bl 80009d0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
- 8000922: f7ff ff01 bl 8000728 <HAL_MspInit>
+ 80009c6: f7ff fee3 bl 8000790 <HAL_MspInit>
/* Return function status */
return HAL_OK;
- 8000926: 2300 movs r3, #0
+ 80009ca: 2300 movs r3, #0
}
- 8000928: 4618 mov r0, r3
- 800092a: bd80 pop {r7, pc}
+ 80009cc: 4618 mov r0, r3
+ 80009ce: bd80 pop {r7, pc}
-0800092c <HAL_InitTick>:
+080009d0 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
- 800092c: b580 push {r7, lr}
- 800092e: b082 sub sp, #8
- 8000930: af00 add r7, sp, #0
- 8000932: 6078 str r0, [r7, #4]
+ 80009d0: b580 push {r7, lr}
+ 80009d2: b082 sub sp, #8
+ 80009d4: af00 add r7, sp, #0
+ 80009d6: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8000934: 4b12 ldr r3, [pc, #72] ; (8000980 <HAL_InitTick+0x54>)
- 8000936: 681a ldr r2, [r3, #0]
- 8000938: 4b12 ldr r3, [pc, #72] ; (8000984 <HAL_InitTick+0x58>)
- 800093a: 781b ldrb r3, [r3, #0]
- 800093c: 4619 mov r1, r3
- 800093e: f44f 737a mov.w r3, #1000 ; 0x3e8
- 8000942: fbb3 f3f1 udiv r3, r3, r1
- 8000946: fbb2 f3f3 udiv r3, r2, r3
- 800094a: 4618 mov r0, r3
- 800094c: f000 f939 bl 8000bc2 <HAL_SYSTICK_Config>
- 8000950: 4603 mov r3, r0
- 8000952: 2b00 cmp r3, #0
- 8000954: d001 beq.n 800095a <HAL_InitTick+0x2e>
+ 80009d8: 4b12 ldr r3, [pc, #72] ; (8000a24 <HAL_InitTick+0x54>)
+ 80009da: 681a ldr r2, [r3, #0]
+ 80009dc: 4b12 ldr r3, [pc, #72] ; (8000a28 <HAL_InitTick+0x58>)
+ 80009de: 781b ldrb r3, [r3, #0]
+ 80009e0: 4619 mov r1, r3
+ 80009e2: f44f 737a mov.w r3, #1000 ; 0x3e8
+ 80009e6: fbb3 f3f1 udiv r3, r3, r1
+ 80009ea: fbb2 f3f3 udiv r3, r2, r3
+ 80009ee: 4618 mov r0, r3
+ 80009f0: f000 f939 bl 8000c66 <HAL_SYSTICK_Config>
+ 80009f4: 4603 mov r3, r0
+ 80009f6: 2b00 cmp r3, #0
+ 80009f8: d001 beq.n 80009fe <HAL_InitTick+0x2e>
{
return HAL_ERROR;
- 8000956: 2301 movs r3, #1
- 8000958: e00e b.n 8000978 <HAL_InitTick+0x4c>
+ 80009fa: 2301 movs r3, #1
+ 80009fc: e00e b.n 8000a1c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 800095a: 687b ldr r3, [r7, #4]
- 800095c: 2b0f cmp r3, #15
- 800095e: d80a bhi.n 8000976 <HAL_InitTick+0x4a>
+ 80009fe: 687b ldr r3, [r7, #4]
+ 8000a00: 2b0f cmp r3, #15
+ 8000a02: d80a bhi.n 8000a1a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8000960: 2200 movs r2, #0
- 8000962: 6879 ldr r1, [r7, #4]
- 8000964: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8000968: f000 f90f bl 8000b8a <HAL_NVIC_SetPriority>
+ 8000a04: 2200 movs r2, #0
+ 8000a06: 6879 ldr r1, [r7, #4]
+ 8000a08: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8000a0c: f000 f90f bl 8000c2e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
- 800096c: 4a06 ldr r2, [pc, #24] ; (8000988 <HAL_InitTick+0x5c>)
- 800096e: 687b ldr r3, [r7, #4]
- 8000970: 6013 str r3, [r2, #0]
+ 8000a10: 4a06 ldr r2, [pc, #24] ; (8000a2c <HAL_InitTick+0x5c>)
+ 8000a12: 687b ldr r3, [r7, #4]
+ 8000a14: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
- 8000972: 2300 movs r3, #0
- 8000974: e000 b.n 8000978 <HAL_InitTick+0x4c>
+ 8000a16: 2300 movs r3, #0
+ 8000a18: e000 b.n 8000a1c <HAL_InitTick+0x4c>
return HAL_ERROR;
- 8000976: 2301 movs r3, #1
+ 8000a1a: 2301 movs r3, #1
}
- 8000978: 4618 mov r0, r3
- 800097a: 3708 adds r7, #8
- 800097c: 46bd mov sp, r7
- 800097e: bd80 pop {r7, pc}
- 8000980: 20000000 .word 0x20000000
- 8000984: 20000008 .word 0x20000008
- 8000988: 20000004 .word 0x20000004
-
-0800098c <HAL_IncTick>:
+ 8000a1c: 4618 mov r0, r3
+ 8000a1e: 3708 adds r7, #8
+ 8000a20: 46bd mov sp, r7
+ 8000a22: bd80 pop {r7, pc}
+ 8000a24: 20000000 .word 0x20000000
+ 8000a28: 20000008 .word 0x20000008
+ 8000a2c: 20000004 .word 0x20000004
+
+08000a30 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
- 800098c: b480 push {r7}
- 800098e: af00 add r7, sp, #0
+ 8000a30: b480 push {r7}
+ 8000a32: af00 add r7, sp, #0
uwTick += uwTickFreq;
- 8000990: 4b06 ldr r3, [pc, #24] ; (80009ac <HAL_IncTick+0x20>)
- 8000992: 781b ldrb r3, [r3, #0]
- 8000994: 461a mov r2, r3
- 8000996: 4b06 ldr r3, [pc, #24] ; (80009b0 <HAL_IncTick+0x24>)
- 8000998: 681b ldr r3, [r3, #0]
- 800099a: 4413 add r3, r2
- 800099c: 4a04 ldr r2, [pc, #16] ; (80009b0 <HAL_IncTick+0x24>)
- 800099e: 6013 str r3, [r2, #0]
+ 8000a34: 4b06 ldr r3, [pc, #24] ; (8000a50 <HAL_IncTick+0x20>)
+ 8000a36: 781b ldrb r3, [r3, #0]
+ 8000a38: 461a mov r2, r3
+ 8000a3a: 4b06 ldr r3, [pc, #24] ; (8000a54 <HAL_IncTick+0x24>)
+ 8000a3c: 681b ldr r3, [r3, #0]
+ 8000a3e: 4413 add r3, r2
+ 8000a40: 4a04 ldr r2, [pc, #16] ; (8000a54 <HAL_IncTick+0x24>)
+ 8000a42: 6013 str r3, [r2, #0]
}
- 80009a0: bf00 nop
- 80009a2: 46bd mov sp, r7
- 80009a4: f85d 7b04 ldr.w r7, [sp], #4
- 80009a8: 4770 bx lr
- 80009aa: bf00 nop
- 80009ac: 20000008 .word 0x20000008
- 80009b0: 200000a8 .word 0x200000a8
-
-080009b4 <HAL_GetTick>:
+ 8000a44: bf00 nop
+ 8000a46: 46bd mov sp, r7
+ 8000a48: f85d 7b04 ldr.w r7, [sp], #4
+ 8000a4c: 4770 bx lr
+ 8000a4e: bf00 nop
+ 8000a50: 20000008 .word 0x20000008
+ 8000a54: 200000a8 .word 0x200000a8
+
+08000a58 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
- 80009b4: b480 push {r7}
- 80009b6: af00 add r7, sp, #0
+ 8000a58: b480 push {r7}
+ 8000a5a: af00 add r7, sp, #0
return uwTick;
- 80009b8: 4b03 ldr r3, [pc, #12] ; (80009c8 <HAL_GetTick+0x14>)
- 80009ba: 681b ldr r3, [r3, #0]
+ 8000a5c: 4b03 ldr r3, [pc, #12] ; (8000a6c <HAL_GetTick+0x14>)
+ 8000a5e: 681b ldr r3, [r3, #0]
}
- 80009bc: 4618 mov r0, r3
- 80009be: 46bd mov sp, r7
- 80009c0: f85d 7b04 ldr.w r7, [sp], #4
- 80009c4: 4770 bx lr
- 80009c6: bf00 nop
- 80009c8: 200000a8 .word 0x200000a8
-
-080009cc <HAL_Delay>:
+ 8000a60: 4618 mov r0, r3
+ 8000a62: 46bd mov sp, r7
+ 8000a64: f85d 7b04 ldr.w r7, [sp], #4
+ 8000a68: 4770 bx lr
+ 8000a6a: bf00 nop
+ 8000a6c: 200000a8 .word 0x200000a8
+
+08000a70 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
- 80009cc: b580 push {r7, lr}
- 80009ce: b084 sub sp, #16
- 80009d0: af00 add r7, sp, #0
- 80009d2: 6078 str r0, [r7, #4]
+ 8000a70: b580 push {r7, lr}
+ 8000a72: b084 sub sp, #16
+ 8000a74: af00 add r7, sp, #0
+ 8000a76: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
- 80009d4: f7ff ffee bl 80009b4 <HAL_GetTick>
- 80009d8: 60b8 str r0, [r7, #8]
+ 8000a78: f7ff ffee bl 8000a58 <HAL_GetTick>
+ 8000a7c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
- 80009da: 687b ldr r3, [r7, #4]
- 80009dc: 60fb str r3, [r7, #12]
+ 8000a7e: 687b ldr r3, [r7, #4]
+ 8000a80: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
- 80009de: 68fb ldr r3, [r7, #12]
- 80009e0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 80009e4: d005 beq.n 80009f2 <HAL_Delay+0x26>
+ 8000a82: 68fb ldr r3, [r7, #12]
+ 8000a84: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
+ 8000a88: d005 beq.n 8000a96 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
- 80009e6: 4b09 ldr r3, [pc, #36] ; (8000a0c <HAL_Delay+0x40>)
- 80009e8: 781b ldrb r3, [r3, #0]
- 80009ea: 461a mov r2, r3
- 80009ec: 68fb ldr r3, [r7, #12]
- 80009ee: 4413 add r3, r2
- 80009f0: 60fb str r3, [r7, #12]
+ 8000a8a: 4b09 ldr r3, [pc, #36] ; (8000ab0 <HAL_Delay+0x40>)
+ 8000a8c: 781b ldrb r3, [r3, #0]
+ 8000a8e: 461a mov r2, r3
+ 8000a90: 68fb ldr r3, [r7, #12]
+ 8000a92: 4413 add r3, r2
+ 8000a94: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
- 80009f2: bf00 nop
- 80009f4: f7ff ffde bl 80009b4 <HAL_GetTick>
- 80009f8: 4602 mov r2, r0
- 80009fa: 68bb ldr r3, [r7, #8]
- 80009fc: 1ad3 subs r3, r2, r3
- 80009fe: 68fa ldr r2, [r7, #12]
- 8000a00: 429a cmp r2, r3
- 8000a02: d8f7 bhi.n 80009f4 <HAL_Delay+0x28>
+ 8000a96: bf00 nop
+ 8000a98: f7ff ffde bl 8000a58 <HAL_GetTick>
+ 8000a9c: 4602 mov r2, r0
+ 8000a9e: 68bb ldr r3, [r7, #8]
+ 8000aa0: 1ad3 subs r3, r2, r3
+ 8000aa2: 68fa ldr r2, [r7, #12]
+ 8000aa4: 429a cmp r2, r3
+ 8000aa6: d8f7 bhi.n 8000a98 <HAL_Delay+0x28>
{
}
}
- 8000a04: bf00 nop
- 8000a06: 3710 adds r7, #16
- 8000a08: 46bd mov sp, r7
- 8000a0a: bd80 pop {r7, pc}
- 8000a0c: 20000008 .word 0x20000008
+ 8000aa8: bf00 nop
+ 8000aaa: 3710 adds r7, #16
+ 8000aac: 46bd mov sp, r7
+ 8000aae: bd80 pop {r7, pc}
+ 8000ab0: 20000008 .word 0x20000008
-08000a10 <__NVIC_SetPriorityGrouping>:
+08000ab4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
- 8000a10: b480 push {r7}
- 8000a12: b085 sub sp, #20
- 8000a14: af00 add r7, sp, #0
- 8000a16: 6078 str r0, [r7, #4]
+ 8000ab4: b480 push {r7}
+ 8000ab6: b085 sub sp, #20
+ 8000ab8: af00 add r7, sp, #0
+ 8000aba: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8000a18: 687b ldr r3, [r7, #4]
- 8000a1a: f003 0307 and.w r3, r3, #7
- 8000a1e: 60fb str r3, [r7, #12]
+ 8000abc: 687b ldr r3, [r7, #4]
+ 8000abe: f003 0307 and.w r3, r3, #7
+ 8000ac2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
- 8000a20: 4b0b ldr r3, [pc, #44] ; (8000a50 <__NVIC_SetPriorityGrouping+0x40>)
- 8000a22: 68db ldr r3, [r3, #12]
- 8000a24: 60bb str r3, [r7, #8]
+ 8000ac4: 4b0b ldr r3, [pc, #44] ; (8000af4 <__NVIC_SetPriorityGrouping+0x40>)
+ 8000ac6: 68db ldr r3, [r3, #12]
+ 8000ac8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 8000a26: 68ba ldr r2, [r7, #8]
- 8000a28: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8000a2c: 4013 ands r3, r2
- 8000a2e: 60bb str r3, [r7, #8]
+ 8000aca: 68ba ldr r2, [r7, #8]
+ 8000acc: f64f 03ff movw r3, #63743 ; 0xf8ff
+ 8000ad0: 4013 ands r3, r2
+ 8000ad2: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8000a30: 68fb ldr r3, [r7, #12]
- 8000a32: 021a lsls r2, r3, #8
+ 8000ad4: 68fb ldr r3, [r7, #12]
+ 8000ad6: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8000a34: 68bb ldr r3, [r7, #8]
- 8000a36: 431a orrs r2, r3
+ 8000ad8: 68bb ldr r3, [r7, #8]
+ 8000ada: 431a orrs r2, r3
reg_value = (reg_value |
- 8000a38: 4b06 ldr r3, [pc, #24] ; (8000a54 <__NVIC_SetPriorityGrouping+0x44>)
- 8000a3a: 4313 orrs r3, r2
- 8000a3c: 60bb str r3, [r7, #8]
+ 8000adc: 4b06 ldr r3, [pc, #24] ; (8000af8 <__NVIC_SetPriorityGrouping+0x44>)
+ 8000ade: 4313 orrs r3, r2
+ 8000ae0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
- 8000a3e: 4a04 ldr r2, [pc, #16] ; (8000a50 <__NVIC_SetPriorityGrouping+0x40>)
- 8000a40: 68bb ldr r3, [r7, #8]
- 8000a42: 60d3 str r3, [r2, #12]
+ 8000ae2: 4a04 ldr r2, [pc, #16] ; (8000af4 <__NVIC_SetPriorityGrouping+0x40>)
+ 8000ae4: 68bb ldr r3, [r7, #8]
+ 8000ae6: 60d3 str r3, [r2, #12]
}
- 8000a44: bf00 nop
- 8000a46: 3714 adds r7, #20
- 8000a48: 46bd mov sp, r7
- 8000a4a: f85d 7b04 ldr.w r7, [sp], #4
- 8000a4e: 4770 bx lr
- 8000a50: e000ed00 .word 0xe000ed00
- 8000a54: 05fa0000 .word 0x05fa0000
-
-08000a58 <__NVIC_GetPriorityGrouping>:
+ 8000ae8: bf00 nop
+ 8000aea: 3714 adds r7, #20
+ 8000aec: 46bd mov sp, r7
+ 8000aee: f85d 7b04 ldr.w r7, [sp], #4
+ 8000af2: 4770 bx lr
+ 8000af4: e000ed00 .word 0xe000ed00
+ 8000af8: 05fa0000 .word 0x05fa0000
+
+08000afc <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
- 8000a58: b480 push {r7}
- 8000a5a: af00 add r7, sp, #0
+ 8000afc: b480 push {r7}
+ 8000afe: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8000a5c: 4b04 ldr r3, [pc, #16] ; (8000a70 <__NVIC_GetPriorityGrouping+0x18>)
- 8000a5e: 68db ldr r3, [r3, #12]
- 8000a60: 0a1b lsrs r3, r3, #8
- 8000a62: f003 0307 and.w r3, r3, #7
+ 8000b00: 4b04 ldr r3, [pc, #16] ; (8000b14 <__NVIC_GetPriorityGrouping+0x18>)
+ 8000b02: 68db ldr r3, [r3, #12]
+ 8000b04: 0a1b lsrs r3, r3, #8
+ 8000b06: f003 0307 and.w r3, r3, #7
}
- 8000a66: 4618 mov r0, r3
- 8000a68: 46bd mov sp, r7
- 8000a6a: f85d 7b04 ldr.w r7, [sp], #4
- 8000a6e: 4770 bx lr
- 8000a70: e000ed00 .word 0xe000ed00
+ 8000b0a: 4618 mov r0, r3
+ 8000b0c: 46bd mov sp, r7
+ 8000b0e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000b12: 4770 bx lr
+ 8000b14: e000ed00 .word 0xe000ed00
-08000a74 <__NVIC_SetPriority>:
+08000b18 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- 8000a74: b480 push {r7}
- 8000a76: b083 sub sp, #12
- 8000a78: af00 add r7, sp, #0
- 8000a7a: 4603 mov r3, r0
- 8000a7c: 6039 str r1, [r7, #0]
- 8000a7e: 71fb strb r3, [r7, #7]
+ 8000b18: b480 push {r7}
+ 8000b1a: b083 sub sp, #12
+ 8000b1c: af00 add r7, sp, #0
+ 8000b1e: 4603 mov r3, r0
+ 8000b20: 6039 str r1, [r7, #0]
+ 8000b22: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
- 8000a80: f997 3007 ldrsb.w r3, [r7, #7]
- 8000a84: 2b00 cmp r3, #0
- 8000a86: db0a blt.n 8000a9e <__NVIC_SetPriority+0x2a>
+ 8000b24: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000b28: 2b00 cmp r3, #0
+ 8000b2a: db0a blt.n 8000b42 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8000a88: 683b ldr r3, [r7, #0]
- 8000a8a: b2da uxtb r2, r3
- 8000a8c: 490c ldr r1, [pc, #48] ; (8000ac0 <__NVIC_SetPriority+0x4c>)
- 8000a8e: f997 3007 ldrsb.w r3, [r7, #7]
- 8000a92: 0112 lsls r2, r2, #4
- 8000a94: b2d2 uxtb r2, r2
- 8000a96: 440b add r3, r1
- 8000a98: f883 2300 strb.w r2, [r3, #768] ; 0x300
+ 8000b2c: 683b ldr r3, [r7, #0]
+ 8000b2e: b2da uxtb r2, r3
+ 8000b30: 490c ldr r1, [pc, #48] ; (8000b64 <__NVIC_SetPriority+0x4c>)
+ 8000b32: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000b36: 0112 lsls r2, r2, #4
+ 8000b38: b2d2 uxtb r2, r2
+ 8000b3a: 440b add r3, r1
+ 8000b3c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
- 8000a9c: e00a b.n 8000ab4 <__NVIC_SetPriority+0x40>
+ 8000b40: e00a b.n 8000b58 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8000a9e: 683b ldr r3, [r7, #0]
- 8000aa0: b2da uxtb r2, r3
- 8000aa2: 4908 ldr r1, [pc, #32] ; (8000ac4 <__NVIC_SetPriority+0x50>)
- 8000aa4: 79fb ldrb r3, [r7, #7]
- 8000aa6: f003 030f and.w r3, r3, #15
- 8000aaa: 3b04 subs r3, #4
- 8000aac: 0112 lsls r2, r2, #4
- 8000aae: b2d2 uxtb r2, r2
- 8000ab0: 440b add r3, r1
- 8000ab2: 761a strb r2, [r3, #24]
+ 8000b42: 683b ldr r3, [r7, #0]
+ 8000b44: b2da uxtb r2, r3
+ 8000b46: 4908 ldr r1, [pc, #32] ; (8000b68 <__NVIC_SetPriority+0x50>)
+ 8000b48: 79fb ldrb r3, [r7, #7]
+ 8000b4a: f003 030f and.w r3, r3, #15
+ 8000b4e: 3b04 subs r3, #4
+ 8000b50: 0112 lsls r2, r2, #4
+ 8000b52: b2d2 uxtb r2, r2
+ 8000b54: 440b add r3, r1
+ 8000b56: 761a strb r2, [r3, #24]
}
- 8000ab4: bf00 nop
- 8000ab6: 370c adds r7, #12
- 8000ab8: 46bd mov sp, r7
- 8000aba: f85d 7b04 ldr.w r7, [sp], #4
- 8000abe: 4770 bx lr
- 8000ac0: e000e100 .word 0xe000e100
- 8000ac4: e000ed00 .word 0xe000ed00
-
-08000ac8 <NVIC_EncodePriority>:
+ 8000b58: bf00 nop
+ 8000b5a: 370c adds r7, #12
+ 8000b5c: 46bd mov sp, r7
+ 8000b5e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000b62: 4770 bx lr
+ 8000b64: e000e100 .word 0xe000e100
+ 8000b68: e000ed00 .word 0xe000ed00
+
+08000b6c <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- 8000ac8: b480 push {r7}
- 8000aca: b089 sub sp, #36 ; 0x24
- 8000acc: af00 add r7, sp, #0
- 8000ace: 60f8 str r0, [r7, #12]
- 8000ad0: 60b9 str r1, [r7, #8]
- 8000ad2: 607a str r2, [r7, #4]
+ 8000b6c: b480 push {r7}
+ 8000b6e: b089 sub sp, #36 ; 0x24
+ 8000b70: af00 add r7, sp, #0
+ 8000b72: 60f8 str r0, [r7, #12]
+ 8000b74: 60b9 str r1, [r7, #8]
+ 8000b76: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8000ad4: 68fb ldr r3, [r7, #12]
- 8000ad6: f003 0307 and.w r3, r3, #7
- 8000ada: 61fb str r3, [r7, #28]
+ 8000b78: 68fb ldr r3, [r7, #12]
+ 8000b7a: f003 0307 and.w r3, r3, #7
+ 8000b7e: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8000adc: 69fb ldr r3, [r7, #28]
- 8000ade: f1c3 0307 rsb r3, r3, #7
- 8000ae2: 2b04 cmp r3, #4
- 8000ae4: bf28 it cs
- 8000ae6: 2304 movcs r3, #4
- 8000ae8: 61bb str r3, [r7, #24]
+ 8000b80: 69fb ldr r3, [r7, #28]
+ 8000b82: f1c3 0307 rsb r3, r3, #7
+ 8000b86: 2b04 cmp r3, #4
+ 8000b88: bf28 it cs
+ 8000b8a: 2304 movcs r3, #4
+ 8000b8c: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8000aea: 69fb ldr r3, [r7, #28]
- 8000aec: 3304 adds r3, #4
- 8000aee: 2b06 cmp r3, #6
- 8000af0: d902 bls.n 8000af8 <NVIC_EncodePriority+0x30>
- 8000af2: 69fb ldr r3, [r7, #28]
- 8000af4: 3b03 subs r3, #3
- 8000af6: e000 b.n 8000afa <NVIC_EncodePriority+0x32>
- 8000af8: 2300 movs r3, #0
- 8000afa: 617b str r3, [r7, #20]
+ 8000b8e: 69fb ldr r3, [r7, #28]
+ 8000b90: 3304 adds r3, #4
+ 8000b92: 2b06 cmp r3, #6
+ 8000b94: d902 bls.n 8000b9c <NVIC_EncodePriority+0x30>
+ 8000b96: 69fb ldr r3, [r7, #28]
+ 8000b98: 3b03 subs r3, #3
+ 8000b9a: e000 b.n 8000b9e <NVIC_EncodePriority+0x32>
+ 8000b9c: 2300 movs r3, #0
+ 8000b9e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000afc: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000b00: 69bb ldr r3, [r7, #24]
- 8000b02: fa02 f303 lsl.w r3, r2, r3
- 8000b06: 43da mvns r2, r3
- 8000b08: 68bb ldr r3, [r7, #8]
- 8000b0a: 401a ands r2, r3
- 8000b0c: 697b ldr r3, [r7, #20]
- 8000b0e: 409a lsls r2, r3
+ 8000ba0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 8000ba4: 69bb ldr r3, [r7, #24]
+ 8000ba6: fa02 f303 lsl.w r3, r2, r3
+ 8000baa: 43da mvns r2, r3
+ 8000bac: 68bb ldr r3, [r7, #8]
+ 8000bae: 401a ands r2, r3
+ 8000bb0: 697b ldr r3, [r7, #20]
+ 8000bb2: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8000b10: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 8000b14: 697b ldr r3, [r7, #20]
- 8000b16: fa01 f303 lsl.w r3, r1, r3
- 8000b1a: 43d9 mvns r1, r3
- 8000b1c: 687b ldr r3, [r7, #4]
- 8000b1e: 400b ands r3, r1
+ 8000bb4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
+ 8000bb8: 697b ldr r3, [r7, #20]
+ 8000bba: fa01 f303 lsl.w r3, r1, r3
+ 8000bbe: 43d9 mvns r1, r3
+ 8000bc0: 687b ldr r3, [r7, #4]
+ 8000bc2: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000b20: 4313 orrs r3, r2
+ 8000bc4: 4313 orrs r3, r2
);
}
- 8000b22: 4618 mov r0, r3
- 8000b24: 3724 adds r7, #36 ; 0x24
- 8000b26: 46bd mov sp, r7
- 8000b28: f85d 7b04 ldr.w r7, [sp], #4
- 8000b2c: 4770 bx lr
+ 8000bc6: 4618 mov r0, r3
+ 8000bc8: 3724 adds r7, #36 ; 0x24
+ 8000bca: 46bd mov sp, r7
+ 8000bcc: f85d 7b04 ldr.w r7, [sp], #4
+ 8000bd0: 4770 bx lr
...
-08000b30 <SysTick_Config>:
+08000bd4 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- 8000b30: b580 push {r7, lr}
- 8000b32: b082 sub sp, #8
- 8000b34: af00 add r7, sp, #0
- 8000b36: 6078 str r0, [r7, #4]
+ 8000bd4: b580 push {r7, lr}
+ 8000bd6: b082 sub sp, #8
+ 8000bd8: af00 add r7, sp, #0
+ 8000bda: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8000b38: 687b ldr r3, [r7, #4]
- 8000b3a: 3b01 subs r3, #1
- 8000b3c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8000b40: d301 bcc.n 8000b46 <SysTick_Config+0x16>
+ 8000bdc: 687b ldr r3, [r7, #4]
+ 8000bde: 3b01 subs r3, #1
+ 8000be0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
+ 8000be4: d301 bcc.n 8000bea <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
- 8000b42: 2301 movs r3, #1
- 8000b44: e00f b.n 8000b66 <SysTick_Config+0x36>
+ 8000be6: 2301 movs r3, #1
+ 8000be8: e00f b.n 8000c0a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8000b46: 4a0a ldr r2, [pc, #40] ; (8000b70 <SysTick_Config+0x40>)
- 8000b48: 687b ldr r3, [r7, #4]
- 8000b4a: 3b01 subs r3, #1
- 8000b4c: 6053 str r3, [r2, #4]
+ 8000bea: 4a0a ldr r2, [pc, #40] ; (8000c14 <SysTick_Config+0x40>)
+ 8000bec: 687b ldr r3, [r7, #4]
+ 8000bee: 3b01 subs r3, #1
+ 8000bf0: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8000b4e: 210f movs r1, #15
- 8000b50: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8000b54: f7ff ff8e bl 8000a74 <__NVIC_SetPriority>
+ 8000bf2: 210f movs r1, #15
+ 8000bf4: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8000bf8: f7ff ff8e bl 8000b18 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8000b58: 4b05 ldr r3, [pc, #20] ; (8000b70 <SysTick_Config+0x40>)
- 8000b5a: 2200 movs r2, #0
- 8000b5c: 609a str r2, [r3, #8]
+ 8000bfc: 4b05 ldr r3, [pc, #20] ; (8000c14 <SysTick_Config+0x40>)
+ 8000bfe: 2200 movs r2, #0
+ 8000c00: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8000b5e: 4b04 ldr r3, [pc, #16] ; (8000b70 <SysTick_Config+0x40>)
- 8000b60: 2207 movs r2, #7
- 8000b62: 601a str r2, [r3, #0]
+ 8000c02: 4b04 ldr r3, [pc, #16] ; (8000c14 <SysTick_Config+0x40>)
+ 8000c04: 2207 movs r2, #7
+ 8000c06: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
- 8000b64: 2300 movs r3, #0
+ 8000c08: 2300 movs r3, #0
}
- 8000b66: 4618 mov r0, r3
- 8000b68: 3708 adds r7, #8
- 8000b6a: 46bd mov sp, r7
- 8000b6c: bd80 pop {r7, pc}
- 8000b6e: bf00 nop
- 8000b70: e000e010 .word 0xe000e010
-
-08000b74 <HAL_NVIC_SetPriorityGrouping>:
+ 8000c0a: 4618 mov r0, r3
+ 8000c0c: 3708 adds r7, #8
+ 8000c0e: 46bd mov sp, r7
+ 8000c10: bd80 pop {r7, pc}
+ 8000c12: bf00 nop
+ 8000c14: e000e010 .word 0xe000e010
+
+08000c18 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
- 8000b74: b580 push {r7, lr}
- 8000b76: b082 sub sp, #8
- 8000b78: af00 add r7, sp, #0
- 8000b7a: 6078 str r0, [r7, #4]
+ 8000c18: b580 push {r7, lr}
+ 8000c1a: b082 sub sp, #8
+ 8000c1c: af00 add r7, sp, #0
+ 8000c1e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
- 8000b7c: 6878 ldr r0, [r7, #4]
- 8000b7e: f7ff ff47 bl 8000a10 <__NVIC_SetPriorityGrouping>
+ 8000c20: 6878 ldr r0, [r7, #4]
+ 8000c22: f7ff ff47 bl 8000ab4 <__NVIC_SetPriorityGrouping>
}
- 8000b82: bf00 nop
- 8000b84: 3708 adds r7, #8
- 8000b86: 46bd mov sp, r7
- 8000b88: bd80 pop {r7, pc}
+ 8000c26: bf00 nop
+ 8000c28: 3708 adds r7, #8
+ 8000c2a: 46bd mov sp, r7
+ 8000c2c: bd80 pop {r7, pc}
-08000b8a <HAL_NVIC_SetPriority>:
+08000c2e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
- 8000b8a: b580 push {r7, lr}
- 8000b8c: b086 sub sp, #24
- 8000b8e: af00 add r7, sp, #0
- 8000b90: 4603 mov r3, r0
- 8000b92: 60b9 str r1, [r7, #8]
- 8000b94: 607a str r2, [r7, #4]
- 8000b96: 73fb strb r3, [r7, #15]
+ 8000c2e: b580 push {r7, lr}
+ 8000c30: b086 sub sp, #24
+ 8000c32: af00 add r7, sp, #0
+ 8000c34: 4603 mov r3, r0
+ 8000c36: 60b9 str r1, [r7, #8]
+ 8000c38: 607a str r2, [r7, #4]
+ 8000c3a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
- 8000b98: 2300 movs r3, #0
- 8000b9a: 617b str r3, [r7, #20]
+ 8000c3c: 2300 movs r3, #0
+ 8000c3e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
- 8000b9c: f7ff ff5c bl 8000a58 <__NVIC_GetPriorityGrouping>
- 8000ba0: 6178 str r0, [r7, #20]
+ 8000c40: f7ff ff5c bl 8000afc <__NVIC_GetPriorityGrouping>
+ 8000c44: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8000ba2: 687a ldr r2, [r7, #4]
- 8000ba4: 68b9 ldr r1, [r7, #8]
- 8000ba6: 6978 ldr r0, [r7, #20]
- 8000ba8: f7ff ff8e bl 8000ac8 <NVIC_EncodePriority>
- 8000bac: 4602 mov r2, r0
- 8000bae: f997 300f ldrsb.w r3, [r7, #15]
- 8000bb2: 4611 mov r1, r2
- 8000bb4: 4618 mov r0, r3
- 8000bb6: f7ff ff5d bl 8000a74 <__NVIC_SetPriority>
+ 8000c46: 687a ldr r2, [r7, #4]
+ 8000c48: 68b9 ldr r1, [r7, #8]
+ 8000c4a: 6978 ldr r0, [r7, #20]
+ 8000c4c: f7ff ff8e bl 8000b6c <NVIC_EncodePriority>
+ 8000c50: 4602 mov r2, r0
+ 8000c52: f997 300f ldrsb.w r3, [r7, #15]
+ 8000c56: 4611 mov r1, r2
+ 8000c58: 4618 mov r0, r3
+ 8000c5a: f7ff ff5d bl 8000b18 <__NVIC_SetPriority>
}
- 8000bba: bf00 nop
- 8000bbc: 3718 adds r7, #24
- 8000bbe: 46bd mov sp, r7
- 8000bc0: bd80 pop {r7, pc}
+ 8000c5e: bf00 nop
+ 8000c60: 3718 adds r7, #24
+ 8000c62: 46bd mov sp, r7
+ 8000c64: bd80 pop {r7, pc}
-08000bc2 <HAL_SYSTICK_Config>:
+08000c66 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
- 8000bc2: b580 push {r7, lr}
- 8000bc4: b082 sub sp, #8
- 8000bc6: af00 add r7, sp, #0
- 8000bc8: 6078 str r0, [r7, #4]
+ 8000c66: b580 push {r7, lr}
+ 8000c68: b082 sub sp, #8
+ 8000c6a: af00 add r7, sp, #0
+ 8000c6c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
- 8000bca: 6878 ldr r0, [r7, #4]
- 8000bcc: f7ff ffb0 bl 8000b30 <SysTick_Config>
- 8000bd0: 4603 mov r3, r0
+ 8000c6e: 6878 ldr r0, [r7, #4]
+ 8000c70: f7ff ffb0 bl 8000bd4 <SysTick_Config>
+ 8000c74: 4603 mov r3, r0
}
- 8000bd2: 4618 mov r0, r3
- 8000bd4: 3708 adds r7, #8
- 8000bd6: 46bd mov sp, r7
- 8000bd8: bd80 pop {r7, pc}
+ 8000c76: 4618 mov r0, r3
+ 8000c78: 3708 adds r7, #8
+ 8000c7a: 46bd mov sp, r7
+ 8000c7c: bd80 pop {r7, pc}
...
-08000bdc <HAL_GPIO_Init>:
+08000c80 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
- 8000bdc: b480 push {r7}
- 8000bde: b089 sub sp, #36 ; 0x24
- 8000be0: af00 add r7, sp, #0
- 8000be2: 6078 str r0, [r7, #4]
- 8000be4: 6039 str r1, [r7, #0]
+ 8000c80: b480 push {r7}
+ 8000c82: b089 sub sp, #36 ; 0x24
+ 8000c84: af00 add r7, sp, #0
+ 8000c86: 6078 str r0, [r7, #4]
+ 8000c88: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
- 8000be6: 2300 movs r3, #0
- 8000be8: 61fb str r3, [r7, #28]
+ 8000c8a: 2300 movs r3, #0
+ 8000c8c: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
- 8000bea: 2300 movs r3, #0
- 8000bec: 617b str r3, [r7, #20]
+ 8000c8e: 2300 movs r3, #0
+ 8000c90: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
- 8000bee: 2300 movs r3, #0
- 8000bf0: 613b str r3, [r7, #16]
+ 8000c92: 2300 movs r3, #0
+ 8000c94: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
- 8000bf2: 2300 movs r3, #0
- 8000bf4: 61bb str r3, [r7, #24]
+ 8000c96: 2300 movs r3, #0
+ 8000c98: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
- 8000bf6: 2300 movs r3, #0
- 8000bf8: 61fb str r3, [r7, #28]
- 8000bfa: e175 b.n 8000ee8 <HAL_GPIO_Init+0x30c>
+ 8000c9a: 2300 movs r3, #0
+ 8000c9c: 61fb str r3, [r7, #28]
+ 8000c9e: e175 b.n 8000f8c <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
- 8000bfc: 2201 movs r2, #1
- 8000bfe: 69fb ldr r3, [r7, #28]
- 8000c00: fa02 f303 lsl.w r3, r2, r3
- 8000c04: 617b str r3, [r7, #20]
+ 8000ca0: 2201 movs r2, #1
+ 8000ca2: 69fb ldr r3, [r7, #28]
+ 8000ca4: fa02 f303 lsl.w r3, r2, r3
+ 8000ca8: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8000c06: 683b ldr r3, [r7, #0]
- 8000c08: 681b ldr r3, [r3, #0]
- 8000c0a: 697a ldr r2, [r7, #20]
- 8000c0c: 4013 ands r3, r2
- 8000c0e: 613b str r3, [r7, #16]
+ 8000caa: 683b ldr r3, [r7, #0]
+ 8000cac: 681b ldr r3, [r3, #0]
+ 8000cae: 697a ldr r2, [r7, #20]
+ 8000cb0: 4013 ands r3, r2
+ 8000cb2: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
- 8000c10: 693a ldr r2, [r7, #16]
- 8000c12: 697b ldr r3, [r7, #20]
- 8000c14: 429a cmp r2, r3
- 8000c16: f040 8164 bne.w 8000ee2 <HAL_GPIO_Init+0x306>
+ 8000cb4: 693a ldr r2, [r7, #16]
+ 8000cb6: 697b ldr r3, [r7, #20]
+ 8000cb8: 429a cmp r2, r3
+ 8000cba: f040 8164 bne.w 8000f86 <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8000c1a: 683b ldr r3, [r7, #0]
- 8000c1c: 685b ldr r3, [r3, #4]
- 8000c1e: 2b02 cmp r3, #2
- 8000c20: d003 beq.n 8000c2a <HAL_GPIO_Init+0x4e>
- 8000c22: 683b ldr r3, [r7, #0]
- 8000c24: 685b ldr r3, [r3, #4]
- 8000c26: 2b12 cmp r3, #18
- 8000c28: d123 bne.n 8000c72 <HAL_GPIO_Init+0x96>
+ 8000cbe: 683b ldr r3, [r7, #0]
+ 8000cc0: 685b ldr r3, [r3, #4]
+ 8000cc2: 2b02 cmp r3, #2
+ 8000cc4: d003 beq.n 8000cce <HAL_GPIO_Init+0x4e>
+ 8000cc6: 683b ldr r3, [r7, #0]
+ 8000cc8: 685b ldr r3, [r3, #4]
+ 8000cca: 2b12 cmp r3, #18
+ 8000ccc: d123 bne.n 8000d16 <HAL_GPIO_Init+0x96>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
- 8000c2a: 69fb ldr r3, [r7, #28]
- 8000c2c: 08da lsrs r2, r3, #3
- 8000c2e: 687b ldr r3, [r7, #4]
- 8000c30: 3208 adds r2, #8
- 8000c32: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 8000c36: 61bb str r3, [r7, #24]
+ 8000cce: 69fb ldr r3, [r7, #28]
+ 8000cd0: 08da lsrs r2, r3, #3
+ 8000cd2: 687b ldr r3, [r7, #4]
+ 8000cd4: 3208 adds r2, #8
+ 8000cd6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
+ 8000cda: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 8000c38: 69fb ldr r3, [r7, #28]
- 8000c3a: f003 0307 and.w r3, r3, #7
- 8000c3e: 009b lsls r3, r3, #2
- 8000c40: 220f movs r2, #15
- 8000c42: fa02 f303 lsl.w r3, r2, r3
- 8000c46: 43db mvns r3, r3
- 8000c48: 69ba ldr r2, [r7, #24]
- 8000c4a: 4013 ands r3, r2
- 8000c4c: 61bb str r3, [r7, #24]
+ 8000cdc: 69fb ldr r3, [r7, #28]
+ 8000cde: f003 0307 and.w r3, r3, #7
+ 8000ce2: 009b lsls r3, r3, #2
+ 8000ce4: 220f movs r2, #15
+ 8000ce6: fa02 f303 lsl.w r3, r2, r3
+ 8000cea: 43db mvns r3, r3
+ 8000cec: 69ba ldr r2, [r7, #24]
+ 8000cee: 4013 ands r3, r2
+ 8000cf0: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 8000c4e: 683b ldr r3, [r7, #0]
- 8000c50: 691a ldr r2, [r3, #16]
- 8000c52: 69fb ldr r3, [r7, #28]
- 8000c54: f003 0307 and.w r3, r3, #7
- 8000c58: 009b lsls r3, r3, #2
- 8000c5a: fa02 f303 lsl.w r3, r2, r3
- 8000c5e: 69ba ldr r2, [r7, #24]
- 8000c60: 4313 orrs r3, r2
- 8000c62: 61bb str r3, [r7, #24]
+ 8000cf2: 683b ldr r3, [r7, #0]
+ 8000cf4: 691a ldr r2, [r3, #16]
+ 8000cf6: 69fb ldr r3, [r7, #28]
+ 8000cf8: f003 0307 and.w r3, r3, #7
+ 8000cfc: 009b lsls r3, r3, #2
+ 8000cfe: fa02 f303 lsl.w r3, r2, r3
+ 8000d02: 69ba ldr r2, [r7, #24]
+ 8000d04: 4313 orrs r3, r2
+ 8000d06: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
- 8000c64: 69fb ldr r3, [r7, #28]
- 8000c66: 08da lsrs r2, r3, #3
- 8000c68: 687b ldr r3, [r7, #4]
- 8000c6a: 3208 adds r2, #8
- 8000c6c: 69b9 ldr r1, [r7, #24]
- 8000c6e: f843 1022 str.w r1, [r3, r2, lsl #2]
+ 8000d08: 69fb ldr r3, [r7, #28]
+ 8000d0a: 08da lsrs r2, r3, #3
+ 8000d0c: 687b ldr r3, [r7, #4]
+ 8000d0e: 3208 adds r2, #8
+ 8000d10: 69b9 ldr r1, [r7, #24]
+ 8000d12: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
- 8000c72: 687b ldr r3, [r7, #4]
- 8000c74: 681b ldr r3, [r3, #0]
- 8000c76: 61bb str r3, [r7, #24]
+ 8000d16: 687b ldr r3, [r7, #4]
+ 8000d18: 681b ldr r3, [r3, #0]
+ 8000d1a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 8000c78: 69fb ldr r3, [r7, #28]
- 8000c7a: 005b lsls r3, r3, #1
- 8000c7c: 2203 movs r2, #3
- 8000c7e: fa02 f303 lsl.w r3, r2, r3
- 8000c82: 43db mvns r3, r3
- 8000c84: 69ba ldr r2, [r7, #24]
- 8000c86: 4013 ands r3, r2
- 8000c88: 61bb str r3, [r7, #24]
+ 8000d1c: 69fb ldr r3, [r7, #28]
+ 8000d1e: 005b lsls r3, r3, #1
+ 8000d20: 2203 movs r2, #3
+ 8000d22: fa02 f303 lsl.w r3, r2, r3
+ 8000d26: 43db mvns r3, r3
+ 8000d28: 69ba ldr r2, [r7, #24]
+ 8000d2a: 4013 ands r3, r2
+ 8000d2c: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 8000c8a: 683b ldr r3, [r7, #0]
- 8000c8c: 685b ldr r3, [r3, #4]
- 8000c8e: f003 0203 and.w r2, r3, #3
- 8000c92: 69fb ldr r3, [r7, #28]
- 8000c94: 005b lsls r3, r3, #1
- 8000c96: fa02 f303 lsl.w r3, r2, r3
- 8000c9a: 69ba ldr r2, [r7, #24]
- 8000c9c: 4313 orrs r3, r2
- 8000c9e: 61bb str r3, [r7, #24]
+ 8000d2e: 683b ldr r3, [r7, #0]
+ 8000d30: 685b ldr r3, [r3, #4]
+ 8000d32: f003 0203 and.w r2, r3, #3
+ 8000d36: 69fb ldr r3, [r7, #28]
+ 8000d38: 005b lsls r3, r3, #1
+ 8000d3a: fa02 f303 lsl.w r3, r2, r3
+ 8000d3e: 69ba ldr r2, [r7, #24]
+ 8000d40: 4313 orrs r3, r2
+ 8000d42: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
- 8000ca0: 687b ldr r3, [r7, #4]
- 8000ca2: 69ba ldr r2, [r7, #24]
- 8000ca4: 601a str r2, [r3, #0]
+ 8000d44: 687b ldr r3, [r7, #4]
+ 8000d46: 69ba ldr r2, [r7, #24]
+ 8000d48: 601a str r2, [r3, #0]
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8000ca6: 683b ldr r3, [r7, #0]
- 8000ca8: 685b ldr r3, [r3, #4]
- 8000caa: 2b01 cmp r3, #1
- 8000cac: d00b beq.n 8000cc6 <HAL_GPIO_Init+0xea>
- 8000cae: 683b ldr r3, [r7, #0]
- 8000cb0: 685b ldr r3, [r3, #4]
- 8000cb2: 2b02 cmp r3, #2
- 8000cb4: d007 beq.n 8000cc6 <HAL_GPIO_Init+0xea>
+ 8000d4a: 683b ldr r3, [r7, #0]
+ 8000d4c: 685b ldr r3, [r3, #4]
+ 8000d4e: 2b01 cmp r3, #1
+ 8000d50: d00b beq.n 8000d6a <HAL_GPIO_Init+0xea>
+ 8000d52: 683b ldr r3, [r7, #0]
+ 8000d54: 685b ldr r3, [r3, #4]
+ 8000d56: 2b02 cmp r3, #2
+ 8000d58: d007 beq.n 8000d6a <HAL_GPIO_Init+0xea>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8000cb6: 683b ldr r3, [r7, #0]
- 8000cb8: 685b ldr r3, [r3, #4]
+ 8000d5a: 683b ldr r3, [r7, #0]
+ 8000d5c: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 8000cba: 2b11 cmp r3, #17
- 8000cbc: d003 beq.n 8000cc6 <HAL_GPIO_Init+0xea>
+ 8000d5e: 2b11 cmp r3, #17
+ 8000d60: d003 beq.n 8000d6a <HAL_GPIO_Init+0xea>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8000cbe: 683b ldr r3, [r7, #0]
- 8000cc0: 685b ldr r3, [r3, #4]
- 8000cc2: 2b12 cmp r3, #18
- 8000cc4: d130 bne.n 8000d28 <HAL_GPIO_Init+0x14c>
+ 8000d62: 683b ldr r3, [r7, #0]
+ 8000d64: 685b ldr r3, [r3, #4]
+ 8000d66: 2b12 cmp r3, #18
+ 8000d68: d130 bne.n 8000dcc <HAL_GPIO_Init+0x14c>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
- 8000cc6: 687b ldr r3, [r7, #4]
- 8000cc8: 689b ldr r3, [r3, #8]
- 8000cca: 61bb str r3, [r7, #24]
+ 8000d6a: 687b ldr r3, [r7, #4]
+ 8000d6c: 689b ldr r3, [r3, #8]
+ 8000d6e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8000ccc: 69fb ldr r3, [r7, #28]
- 8000cce: 005b lsls r3, r3, #1
- 8000cd0: 2203 movs r2, #3
- 8000cd2: fa02 f303 lsl.w r3, r2, r3
- 8000cd6: 43db mvns r3, r3
- 8000cd8: 69ba ldr r2, [r7, #24]
- 8000cda: 4013 ands r3, r2
- 8000cdc: 61bb str r3, [r7, #24]
+ 8000d70: 69fb ldr r3, [r7, #28]
+ 8000d72: 005b lsls r3, r3, #1
+ 8000d74: 2203 movs r2, #3
+ 8000d76: fa02 f303 lsl.w r3, r2, r3
+ 8000d7a: 43db mvns r3, r3
+ 8000d7c: 69ba ldr r2, [r7, #24]
+ 8000d7e: 4013 ands r3, r2
+ 8000d80: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
- 8000cde: 683b ldr r3, [r7, #0]
- 8000ce0: 68da ldr r2, [r3, #12]
- 8000ce2: 69fb ldr r3, [r7, #28]
- 8000ce4: 005b lsls r3, r3, #1
- 8000ce6: fa02 f303 lsl.w r3, r2, r3
- 8000cea: 69ba ldr r2, [r7, #24]
- 8000cec: 4313 orrs r3, r2
- 8000cee: 61bb str r3, [r7, #24]
+ 8000d82: 683b ldr r3, [r7, #0]
+ 8000d84: 68da ldr r2, [r3, #12]
+ 8000d86: 69fb ldr r3, [r7, #28]
+ 8000d88: 005b lsls r3, r3, #1
+ 8000d8a: fa02 f303 lsl.w r3, r2, r3
+ 8000d8e: 69ba ldr r2, [r7, #24]
+ 8000d90: 4313 orrs r3, r2
+ 8000d92: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
- 8000cf0: 687b ldr r3, [r7, #4]
- 8000cf2: 69ba ldr r2, [r7, #24]
- 8000cf4: 609a str r2, [r3, #8]
+ 8000d94: 687b ldr r3, [r7, #4]
+ 8000d96: 69ba ldr r2, [r7, #24]
+ 8000d98: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
- 8000cf6: 687b ldr r3, [r7, #4]
- 8000cf8: 685b ldr r3, [r3, #4]
- 8000cfa: 61bb str r3, [r7, #24]
+ 8000d9a: 687b ldr r3, [r7, #4]
+ 8000d9c: 685b ldr r3, [r3, #4]
+ 8000d9e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8000cfc: 2201 movs r2, #1
- 8000cfe: 69fb ldr r3, [r7, #28]
- 8000d00: fa02 f303 lsl.w r3, r2, r3
- 8000d04: 43db mvns r3, r3
- 8000d06: 69ba ldr r2, [r7, #24]
- 8000d08: 4013 ands r3, r2
- 8000d0a: 61bb str r3, [r7, #24]
+ 8000da0: 2201 movs r2, #1
+ 8000da2: 69fb ldr r3, [r7, #28]
+ 8000da4: fa02 f303 lsl.w r3, r2, r3
+ 8000da8: 43db mvns r3, r3
+ 8000daa: 69ba ldr r2, [r7, #24]
+ 8000dac: 4013 ands r3, r2
+ 8000dae: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 8000d0c: 683b ldr r3, [r7, #0]
- 8000d0e: 685b ldr r3, [r3, #4]
- 8000d10: 091b lsrs r3, r3, #4
- 8000d12: f003 0201 and.w r2, r3, #1
- 8000d16: 69fb ldr r3, [r7, #28]
- 8000d18: fa02 f303 lsl.w r3, r2, r3
- 8000d1c: 69ba ldr r2, [r7, #24]
- 8000d1e: 4313 orrs r3, r2
- 8000d20: 61bb str r3, [r7, #24]
+ 8000db0: 683b ldr r3, [r7, #0]
+ 8000db2: 685b ldr r3, [r3, #4]
+ 8000db4: 091b lsrs r3, r3, #4
+ 8000db6: f003 0201 and.w r2, r3, #1
+ 8000dba: 69fb ldr r3, [r7, #28]
+ 8000dbc: fa02 f303 lsl.w r3, r2, r3
+ 8000dc0: 69ba ldr r2, [r7, #24]
+ 8000dc2: 4313 orrs r3, r2
+ 8000dc4: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
- 8000d22: 687b ldr r3, [r7, #4]
- 8000d24: 69ba ldr r2, [r7, #24]
- 8000d26: 605a str r2, [r3, #4]
+ 8000dc6: 687b ldr r3, [r7, #4]
+ 8000dc8: 69ba ldr r2, [r7, #24]
+ 8000dca: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
- 8000d28: 687b ldr r3, [r7, #4]
- 8000d2a: 68db ldr r3, [r3, #12]
- 8000d2c: 61bb str r3, [r7, #24]
+ 8000dcc: 687b ldr r3, [r7, #4]
+ 8000dce: 68db ldr r3, [r3, #12]
+ 8000dd0: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 8000d2e: 69fb ldr r3, [r7, #28]
- 8000d30: 005b lsls r3, r3, #1
- 8000d32: 2203 movs r2, #3
- 8000d34: fa02 f303 lsl.w r3, r2, r3
- 8000d38: 43db mvns r3, r3
- 8000d3a: 69ba ldr r2, [r7, #24]
- 8000d3c: 4013 ands r3, r2
- 8000d3e: 61bb str r3, [r7, #24]
+ 8000dd2: 69fb ldr r3, [r7, #28]
+ 8000dd4: 005b lsls r3, r3, #1
+ 8000dd6: 2203 movs r2, #3
+ 8000dd8: fa02 f303 lsl.w r3, r2, r3
+ 8000ddc: 43db mvns r3, r3
+ 8000dde: 69ba ldr r2, [r7, #24]
+ 8000de0: 4013 ands r3, r2
+ 8000de2: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
- 8000d40: 683b ldr r3, [r7, #0]
- 8000d42: 689a ldr r2, [r3, #8]
- 8000d44: 69fb ldr r3, [r7, #28]
- 8000d46: 005b lsls r3, r3, #1
- 8000d48: fa02 f303 lsl.w r3, r2, r3
- 8000d4c: 69ba ldr r2, [r7, #24]
- 8000d4e: 4313 orrs r3, r2
- 8000d50: 61bb str r3, [r7, #24]
+ 8000de4: 683b ldr r3, [r7, #0]
+ 8000de6: 689a ldr r2, [r3, #8]
+ 8000de8: 69fb ldr r3, [r7, #28]
+ 8000dea: 005b lsls r3, r3, #1
+ 8000dec: fa02 f303 lsl.w r3, r2, r3
+ 8000df0: 69ba ldr r2, [r7, #24]
+ 8000df2: 4313 orrs r3, r2
+ 8000df4: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
- 8000d52: 687b ldr r3, [r7, #4]
- 8000d54: 69ba ldr r2, [r7, #24]
- 8000d56: 60da str r2, [r3, #12]
+ 8000df6: 687b ldr r3, [r7, #4]
+ 8000df8: 69ba ldr r2, [r7, #24]
+ 8000dfa: 60da str r2, [r3, #12]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 8000d58: 683b ldr r3, [r7, #0]
- 8000d5a: 685b ldr r3, [r3, #4]
- 8000d5c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000d60: 2b00 cmp r3, #0
- 8000d62: f000 80be beq.w 8000ee2 <HAL_GPIO_Init+0x306>
+ 8000dfc: 683b ldr r3, [r7, #0]
+ 8000dfe: 685b ldr r3, [r3, #4]
+ 8000e00: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000e04: 2b00 cmp r3, #0
+ 8000e06: f000 80be beq.w 8000f86 <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 8000d66: 4b65 ldr r3, [pc, #404] ; (8000efc <HAL_GPIO_Init+0x320>)
- 8000d68: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000d6a: 4a64 ldr r2, [pc, #400] ; (8000efc <HAL_GPIO_Init+0x320>)
- 8000d6c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000d70: 6453 str r3, [r2, #68] ; 0x44
- 8000d72: 4b62 ldr r3, [pc, #392] ; (8000efc <HAL_GPIO_Init+0x320>)
- 8000d74: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000d76: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8000d7a: 60fb str r3, [r7, #12]
- 8000d7c: 68fb ldr r3, [r7, #12]
+ 8000e0a: 4b65 ldr r3, [pc, #404] ; (8000fa0 <HAL_GPIO_Init+0x320>)
+ 8000e0c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000e0e: 4a64 ldr r2, [pc, #400] ; (8000fa0 <HAL_GPIO_Init+0x320>)
+ 8000e10: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000e14: 6453 str r3, [r2, #68] ; 0x44
+ 8000e16: 4b62 ldr r3, [pc, #392] ; (8000fa0 <HAL_GPIO_Init+0x320>)
+ 8000e18: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8000e1a: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8000e1e: 60fb str r3, [r7, #12]
+ 8000e20: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
- 8000d7e: 4a60 ldr r2, [pc, #384] ; (8000f00 <HAL_GPIO_Init+0x324>)
- 8000d80: 69fb ldr r3, [r7, #28]
- 8000d82: 089b lsrs r3, r3, #2
- 8000d84: 3302 adds r3, #2
- 8000d86: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 8000d8a: 61bb str r3, [r7, #24]
+ 8000e22: 4a60 ldr r2, [pc, #384] ; (8000fa4 <HAL_GPIO_Init+0x324>)
+ 8000e24: 69fb ldr r3, [r7, #28]
+ 8000e26: 089b lsrs r3, r3, #2
+ 8000e28: 3302 adds r3, #2
+ 8000e2a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
+ 8000e2e: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 8000d8c: 69fb ldr r3, [r7, #28]
- 8000d8e: f003 0303 and.w r3, r3, #3
- 8000d92: 009b lsls r3, r3, #2
- 8000d94: 220f movs r2, #15
- 8000d96: fa02 f303 lsl.w r3, r2, r3
- 8000d9a: 43db mvns r3, r3
- 8000d9c: 69ba ldr r2, [r7, #24]
- 8000d9e: 4013 ands r3, r2
- 8000da0: 61bb str r3, [r7, #24]
+ 8000e30: 69fb ldr r3, [r7, #28]
+ 8000e32: f003 0303 and.w r3, r3, #3
+ 8000e36: 009b lsls r3, r3, #2
+ 8000e38: 220f movs r2, #15
+ 8000e3a: fa02 f303 lsl.w r3, r2, r3
+ 8000e3e: 43db mvns r3, r3
+ 8000e40: 69ba ldr r2, [r7, #24]
+ 8000e42: 4013 ands r3, r2
+ 8000e44: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 8000da2: 687b ldr r3, [r7, #4]
- 8000da4: 4a57 ldr r2, [pc, #348] ; (8000f04 <HAL_GPIO_Init+0x328>)
- 8000da6: 4293 cmp r3, r2
- 8000da8: d037 beq.n 8000e1a <HAL_GPIO_Init+0x23e>
- 8000daa: 687b ldr r3, [r7, #4]
- 8000dac: 4a56 ldr r2, [pc, #344] ; (8000f08 <HAL_GPIO_Init+0x32c>)
- 8000dae: 4293 cmp r3, r2
- 8000db0: d031 beq.n 8000e16 <HAL_GPIO_Init+0x23a>
- 8000db2: 687b ldr r3, [r7, #4]
- 8000db4: 4a55 ldr r2, [pc, #340] ; (8000f0c <HAL_GPIO_Init+0x330>)
- 8000db6: 4293 cmp r3, r2
- 8000db8: d02b beq.n 8000e12 <HAL_GPIO_Init+0x236>
- 8000dba: 687b ldr r3, [r7, #4]
- 8000dbc: 4a54 ldr r2, [pc, #336] ; (8000f10 <HAL_GPIO_Init+0x334>)
- 8000dbe: 4293 cmp r3, r2
- 8000dc0: d025 beq.n 8000e0e <HAL_GPIO_Init+0x232>
- 8000dc2: 687b ldr r3, [r7, #4]
- 8000dc4: 4a53 ldr r2, [pc, #332] ; (8000f14 <HAL_GPIO_Init+0x338>)
- 8000dc6: 4293 cmp r3, r2
- 8000dc8: d01f beq.n 8000e0a <HAL_GPIO_Init+0x22e>
- 8000dca: 687b ldr r3, [r7, #4]
- 8000dcc: 4a52 ldr r2, [pc, #328] ; (8000f18 <HAL_GPIO_Init+0x33c>)
- 8000dce: 4293 cmp r3, r2
- 8000dd0: d019 beq.n 8000e06 <HAL_GPIO_Init+0x22a>
- 8000dd2: 687b ldr r3, [r7, #4]
- 8000dd4: 4a51 ldr r2, [pc, #324] ; (8000f1c <HAL_GPIO_Init+0x340>)
- 8000dd6: 4293 cmp r3, r2
- 8000dd8: d013 beq.n 8000e02 <HAL_GPIO_Init+0x226>
- 8000dda: 687b ldr r3, [r7, #4]
- 8000ddc: 4a50 ldr r2, [pc, #320] ; (8000f20 <HAL_GPIO_Init+0x344>)
- 8000dde: 4293 cmp r3, r2
- 8000de0: d00d beq.n 8000dfe <HAL_GPIO_Init+0x222>
- 8000de2: 687b ldr r3, [r7, #4]
- 8000de4: 4a4f ldr r2, [pc, #316] ; (8000f24 <HAL_GPIO_Init+0x348>)
- 8000de6: 4293 cmp r3, r2
- 8000de8: d007 beq.n 8000dfa <HAL_GPIO_Init+0x21e>
- 8000dea: 687b ldr r3, [r7, #4]
- 8000dec: 4a4e ldr r2, [pc, #312] ; (8000f28 <HAL_GPIO_Init+0x34c>)
- 8000dee: 4293 cmp r3, r2
- 8000df0: d101 bne.n 8000df6 <HAL_GPIO_Init+0x21a>
- 8000df2: 2309 movs r3, #9
- 8000df4: e012 b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000df6: 230a movs r3, #10
- 8000df8: e010 b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000dfa: 2308 movs r3, #8
- 8000dfc: e00e b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000dfe: 2307 movs r3, #7
- 8000e00: e00c b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000e02: 2306 movs r3, #6
- 8000e04: e00a b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000e06: 2305 movs r3, #5
- 8000e08: e008 b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000e0a: 2304 movs r3, #4
- 8000e0c: e006 b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000e0e: 2303 movs r3, #3
- 8000e10: e004 b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000e12: 2302 movs r3, #2
- 8000e14: e002 b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000e16: 2301 movs r3, #1
- 8000e18: e000 b.n 8000e1c <HAL_GPIO_Init+0x240>
- 8000e1a: 2300 movs r3, #0
- 8000e1c: 69fa ldr r2, [r7, #28]
- 8000e1e: f002 0203 and.w r2, r2, #3
- 8000e22: 0092 lsls r2, r2, #2
- 8000e24: 4093 lsls r3, r2
- 8000e26: 69ba ldr r2, [r7, #24]
- 8000e28: 4313 orrs r3, r2
- 8000e2a: 61bb str r3, [r7, #24]
+ 8000e46: 687b ldr r3, [r7, #4]
+ 8000e48: 4a57 ldr r2, [pc, #348] ; (8000fa8 <HAL_GPIO_Init+0x328>)
+ 8000e4a: 4293 cmp r3, r2
+ 8000e4c: d037 beq.n 8000ebe <HAL_GPIO_Init+0x23e>
+ 8000e4e: 687b ldr r3, [r7, #4]
+ 8000e50: 4a56 ldr r2, [pc, #344] ; (8000fac <HAL_GPIO_Init+0x32c>)
+ 8000e52: 4293 cmp r3, r2
+ 8000e54: d031 beq.n 8000eba <HAL_GPIO_Init+0x23a>
+ 8000e56: 687b ldr r3, [r7, #4]
+ 8000e58: 4a55 ldr r2, [pc, #340] ; (8000fb0 <HAL_GPIO_Init+0x330>)
+ 8000e5a: 4293 cmp r3, r2
+ 8000e5c: d02b beq.n 8000eb6 <HAL_GPIO_Init+0x236>
+ 8000e5e: 687b ldr r3, [r7, #4]
+ 8000e60: 4a54 ldr r2, [pc, #336] ; (8000fb4 <HAL_GPIO_Init+0x334>)
+ 8000e62: 4293 cmp r3, r2
+ 8000e64: d025 beq.n 8000eb2 <HAL_GPIO_Init+0x232>
+ 8000e66: 687b ldr r3, [r7, #4]
+ 8000e68: 4a53 ldr r2, [pc, #332] ; (8000fb8 <HAL_GPIO_Init+0x338>)
+ 8000e6a: 4293 cmp r3, r2
+ 8000e6c: d01f beq.n 8000eae <HAL_GPIO_Init+0x22e>
+ 8000e6e: 687b ldr r3, [r7, #4]
+ 8000e70: 4a52 ldr r2, [pc, #328] ; (8000fbc <HAL_GPIO_Init+0x33c>)
+ 8000e72: 4293 cmp r3, r2
+ 8000e74: d019 beq.n 8000eaa <HAL_GPIO_Init+0x22a>
+ 8000e76: 687b ldr r3, [r7, #4]
+ 8000e78: 4a51 ldr r2, [pc, #324] ; (8000fc0 <HAL_GPIO_Init+0x340>)
+ 8000e7a: 4293 cmp r3, r2
+ 8000e7c: d013 beq.n 8000ea6 <HAL_GPIO_Init+0x226>
+ 8000e7e: 687b ldr r3, [r7, #4]
+ 8000e80: 4a50 ldr r2, [pc, #320] ; (8000fc4 <HAL_GPIO_Init+0x344>)
+ 8000e82: 4293 cmp r3, r2
+ 8000e84: d00d beq.n 8000ea2 <HAL_GPIO_Init+0x222>
+ 8000e86: 687b ldr r3, [r7, #4]
+ 8000e88: 4a4f ldr r2, [pc, #316] ; (8000fc8 <HAL_GPIO_Init+0x348>)
+ 8000e8a: 4293 cmp r3, r2
+ 8000e8c: d007 beq.n 8000e9e <HAL_GPIO_Init+0x21e>
+ 8000e8e: 687b ldr r3, [r7, #4]
+ 8000e90: 4a4e ldr r2, [pc, #312] ; (8000fcc <HAL_GPIO_Init+0x34c>)
+ 8000e92: 4293 cmp r3, r2
+ 8000e94: d101 bne.n 8000e9a <HAL_GPIO_Init+0x21a>
+ 8000e96: 2309 movs r3, #9
+ 8000e98: e012 b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000e9a: 230a movs r3, #10
+ 8000e9c: e010 b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000e9e: 2308 movs r3, #8
+ 8000ea0: e00e b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000ea2: 2307 movs r3, #7
+ 8000ea4: e00c b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000ea6: 2306 movs r3, #6
+ 8000ea8: e00a b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000eaa: 2305 movs r3, #5
+ 8000eac: e008 b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000eae: 2304 movs r3, #4
+ 8000eb0: e006 b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000eb2: 2303 movs r3, #3
+ 8000eb4: e004 b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000eb6: 2302 movs r3, #2
+ 8000eb8: e002 b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000eba: 2301 movs r3, #1
+ 8000ebc: e000 b.n 8000ec0 <HAL_GPIO_Init+0x240>
+ 8000ebe: 2300 movs r3, #0
+ 8000ec0: 69fa ldr r2, [r7, #28]
+ 8000ec2: f002 0203 and.w r2, r2, #3
+ 8000ec6: 0092 lsls r2, r2, #2
+ 8000ec8: 4093 lsls r3, r2
+ 8000eca: 69ba ldr r2, [r7, #24]
+ 8000ecc: 4313 orrs r3, r2
+ 8000ece: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
- 8000e2c: 4934 ldr r1, [pc, #208] ; (8000f00 <HAL_GPIO_Init+0x324>)
- 8000e2e: 69fb ldr r3, [r7, #28]
- 8000e30: 089b lsrs r3, r3, #2
- 8000e32: 3302 adds r3, #2
- 8000e34: 69ba ldr r2, [r7, #24]
- 8000e36: f841 2023 str.w r2, [r1, r3, lsl #2]
+ 8000ed0: 4934 ldr r1, [pc, #208] ; (8000fa4 <HAL_GPIO_Init+0x324>)
+ 8000ed2: 69fb ldr r3, [r7, #28]
+ 8000ed4: 089b lsrs r3, r3, #2
+ 8000ed6: 3302 adds r3, #2
+ 8000ed8: 69ba ldr r2, [r7, #24]
+ 8000eda: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
- 8000e3a: 4b3c ldr r3, [pc, #240] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000e3c: 681b ldr r3, [r3, #0]
- 8000e3e: 61bb str r3, [r7, #24]
+ 8000ede: 4b3c ldr r3, [pc, #240] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000ee0: 681b ldr r3, [r3, #0]
+ 8000ee2: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000e40: 693b ldr r3, [r7, #16]
- 8000e42: 43db mvns r3, r3
- 8000e44: 69ba ldr r2, [r7, #24]
- 8000e46: 4013 ands r3, r2
- 8000e48: 61bb str r3, [r7, #24]
+ 8000ee4: 693b ldr r3, [r7, #16]
+ 8000ee6: 43db mvns r3, r3
+ 8000ee8: 69ba ldr r2, [r7, #24]
+ 8000eea: 4013 ands r3, r2
+ 8000eec: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 8000e4a: 683b ldr r3, [r7, #0]
- 8000e4c: 685b ldr r3, [r3, #4]
- 8000e4e: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8000e52: 2b00 cmp r3, #0
- 8000e54: d003 beq.n 8000e5e <HAL_GPIO_Init+0x282>
+ 8000eee: 683b ldr r3, [r7, #0]
+ 8000ef0: 685b ldr r3, [r3, #4]
+ 8000ef2: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8000ef6: 2b00 cmp r3, #0
+ 8000ef8: d003 beq.n 8000f02 <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
- 8000e56: 69ba ldr r2, [r7, #24]
- 8000e58: 693b ldr r3, [r7, #16]
- 8000e5a: 4313 orrs r3, r2
- 8000e5c: 61bb str r3, [r7, #24]
+ 8000efa: 69ba ldr r2, [r7, #24]
+ 8000efc: 693b ldr r3, [r7, #16]
+ 8000efe: 4313 orrs r3, r2
+ 8000f00: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
- 8000e5e: 4a33 ldr r2, [pc, #204] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000e60: 69bb ldr r3, [r7, #24]
- 8000e62: 6013 str r3, [r2, #0]
+ 8000f02: 4a33 ldr r2, [pc, #204] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000f04: 69bb ldr r3, [r7, #24]
+ 8000f06: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
- 8000e64: 4b31 ldr r3, [pc, #196] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000e66: 685b ldr r3, [r3, #4]
- 8000e68: 61bb str r3, [r7, #24]
+ 8000f08: 4b31 ldr r3, [pc, #196] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000f0a: 685b ldr r3, [r3, #4]
+ 8000f0c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000e6a: 693b ldr r3, [r7, #16]
- 8000e6c: 43db mvns r3, r3
- 8000e6e: 69ba ldr r2, [r7, #24]
- 8000e70: 4013 ands r3, r2
- 8000e72: 61bb str r3, [r7, #24]
+ 8000f0e: 693b ldr r3, [r7, #16]
+ 8000f10: 43db mvns r3, r3
+ 8000f12: 69ba ldr r2, [r7, #24]
+ 8000f14: 4013 ands r3, r2
+ 8000f16: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 8000e74: 683b ldr r3, [r7, #0]
- 8000e76: 685b ldr r3, [r3, #4]
- 8000e78: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8000e7c: 2b00 cmp r3, #0
- 8000e7e: d003 beq.n 8000e88 <HAL_GPIO_Init+0x2ac>
+ 8000f18: 683b ldr r3, [r7, #0]
+ 8000f1a: 685b ldr r3, [r3, #4]
+ 8000f1c: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000f20: 2b00 cmp r3, #0
+ 8000f22: d003 beq.n 8000f2c <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
- 8000e80: 69ba ldr r2, [r7, #24]
- 8000e82: 693b ldr r3, [r7, #16]
- 8000e84: 4313 orrs r3, r2
- 8000e86: 61bb str r3, [r7, #24]
+ 8000f24: 69ba ldr r2, [r7, #24]
+ 8000f26: 693b ldr r3, [r7, #16]
+ 8000f28: 4313 orrs r3, r2
+ 8000f2a: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
- 8000e88: 4a28 ldr r2, [pc, #160] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000e8a: 69bb ldr r3, [r7, #24]
- 8000e8c: 6053 str r3, [r2, #4]
+ 8000f2c: 4a28 ldr r2, [pc, #160] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000f2e: 69bb ldr r3, [r7, #24]
+ 8000f30: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
- 8000e8e: 4b27 ldr r3, [pc, #156] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000e90: 689b ldr r3, [r3, #8]
- 8000e92: 61bb str r3, [r7, #24]
+ 8000f32: 4b27 ldr r3, [pc, #156] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000f34: 689b ldr r3, [r3, #8]
+ 8000f36: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000e94: 693b ldr r3, [r7, #16]
- 8000e96: 43db mvns r3, r3
- 8000e98: 69ba ldr r2, [r7, #24]
- 8000e9a: 4013 ands r3, r2
- 8000e9c: 61bb str r3, [r7, #24]
+ 8000f38: 693b ldr r3, [r7, #16]
+ 8000f3a: 43db mvns r3, r3
+ 8000f3c: 69ba ldr r2, [r7, #24]
+ 8000f3e: 4013 ands r3, r2
+ 8000f40: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 8000e9e: 683b ldr r3, [r7, #0]
- 8000ea0: 685b ldr r3, [r3, #4]
- 8000ea2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8000ea6: 2b00 cmp r3, #0
- 8000ea8: d003 beq.n 8000eb2 <HAL_GPIO_Init+0x2d6>
+ 8000f42: 683b ldr r3, [r7, #0]
+ 8000f44: 685b ldr r3, [r3, #4]
+ 8000f46: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8000f4a: 2b00 cmp r3, #0
+ 8000f4c: d003 beq.n 8000f56 <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
- 8000eaa: 69ba ldr r2, [r7, #24]
- 8000eac: 693b ldr r3, [r7, #16]
- 8000eae: 4313 orrs r3, r2
- 8000eb0: 61bb str r3, [r7, #24]
+ 8000f4e: 69ba ldr r2, [r7, #24]
+ 8000f50: 693b ldr r3, [r7, #16]
+ 8000f52: 4313 orrs r3, r2
+ 8000f54: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
- 8000eb2: 4a1e ldr r2, [pc, #120] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000eb4: 69bb ldr r3, [r7, #24]
- 8000eb6: 6093 str r3, [r2, #8]
+ 8000f56: 4a1e ldr r2, [pc, #120] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000f58: 69bb ldr r3, [r7, #24]
+ 8000f5a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
- 8000eb8: 4b1c ldr r3, [pc, #112] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000eba: 68db ldr r3, [r3, #12]
- 8000ebc: 61bb str r3, [r7, #24]
+ 8000f5c: 4b1c ldr r3, [pc, #112] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000f5e: 68db ldr r3, [r3, #12]
+ 8000f60: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000ebe: 693b ldr r3, [r7, #16]
- 8000ec0: 43db mvns r3, r3
- 8000ec2: 69ba ldr r2, [r7, #24]
- 8000ec4: 4013 ands r3, r2
- 8000ec6: 61bb str r3, [r7, #24]
+ 8000f62: 693b ldr r3, [r7, #16]
+ 8000f64: 43db mvns r3, r3
+ 8000f66: 69ba ldr r2, [r7, #24]
+ 8000f68: 4013 ands r3, r2
+ 8000f6a: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 8000ec8: 683b ldr r3, [r7, #0]
- 8000eca: 685b ldr r3, [r3, #4]
- 8000ecc: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8000ed0: 2b00 cmp r3, #0
- 8000ed2: d003 beq.n 8000edc <HAL_GPIO_Init+0x300>
+ 8000f6c: 683b ldr r3, [r7, #0]
+ 8000f6e: 685b ldr r3, [r3, #4]
+ 8000f70: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8000f74: 2b00 cmp r3, #0
+ 8000f76: d003 beq.n 8000f80 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
- 8000ed4: 69ba ldr r2, [r7, #24]
- 8000ed6: 693b ldr r3, [r7, #16]
- 8000ed8: 4313 orrs r3, r2
- 8000eda: 61bb str r3, [r7, #24]
+ 8000f78: 69ba ldr r2, [r7, #24]
+ 8000f7a: 693b ldr r3, [r7, #16]
+ 8000f7c: 4313 orrs r3, r2
+ 8000f7e: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
- 8000edc: 4a13 ldr r2, [pc, #76] ; (8000f2c <HAL_GPIO_Init+0x350>)
- 8000ede: 69bb ldr r3, [r7, #24]
- 8000ee0: 60d3 str r3, [r2, #12]
+ 8000f80: 4a13 ldr r2, [pc, #76] ; (8000fd0 <HAL_GPIO_Init+0x350>)
+ 8000f82: 69bb ldr r3, [r7, #24]
+ 8000f84: 60d3 str r3, [r2, #12]
for(position = 0; position < GPIO_NUMBER; position++)
- 8000ee2: 69fb ldr r3, [r7, #28]
- 8000ee4: 3301 adds r3, #1
- 8000ee6: 61fb str r3, [r7, #28]
- 8000ee8: 69fb ldr r3, [r7, #28]
- 8000eea: 2b0f cmp r3, #15
- 8000eec: f67f ae86 bls.w 8000bfc <HAL_GPIO_Init+0x20>
+ 8000f86: 69fb ldr r3, [r7, #28]
+ 8000f88: 3301 adds r3, #1
+ 8000f8a: 61fb str r3, [r7, #28]
+ 8000f8c: 69fb ldr r3, [r7, #28]
+ 8000f8e: 2b0f cmp r3, #15
+ 8000f90: f67f ae86 bls.w 8000ca0 <HAL_GPIO_Init+0x20>
}
}
}
}
- 8000ef0: bf00 nop
- 8000ef2: 3724 adds r7, #36 ; 0x24
- 8000ef4: 46bd mov sp, r7
- 8000ef6: f85d 7b04 ldr.w r7, [sp], #4
- 8000efa: 4770 bx lr
- 8000efc: 40023800 .word 0x40023800
- 8000f00: 40013800 .word 0x40013800
- 8000f04: 40020000 .word 0x40020000
- 8000f08: 40020400 .word 0x40020400
- 8000f0c: 40020800 .word 0x40020800
- 8000f10: 40020c00 .word 0x40020c00
- 8000f14: 40021000 .word 0x40021000
- 8000f18: 40021400 .word 0x40021400
- 8000f1c: 40021800 .word 0x40021800
- 8000f20: 40021c00 .word 0x40021c00
- 8000f24: 40022000 .word 0x40022000
- 8000f28: 40022400 .word 0x40022400
- 8000f2c: 40013c00 .word 0x40013c00
-
-08000f30 <HAL_RCC_OscConfig>:
+ 8000f94: bf00 nop
+ 8000f96: 3724 adds r7, #36 ; 0x24
+ 8000f98: 46bd mov sp, r7
+ 8000f9a: f85d 7b04 ldr.w r7, [sp], #4
+ 8000f9e: 4770 bx lr
+ 8000fa0: 40023800 .word 0x40023800
+ 8000fa4: 40013800 .word 0x40013800
+ 8000fa8: 40020000 .word 0x40020000
+ 8000fac: 40020400 .word 0x40020400
+ 8000fb0: 40020800 .word 0x40020800
+ 8000fb4: 40020c00 .word 0x40020c00
+ 8000fb8: 40021000 .word 0x40021000
+ 8000fbc: 40021400 .word 0x40021400
+ 8000fc0: 40021800 .word 0x40021800
+ 8000fc4: 40021c00 .word 0x40021c00
+ 8000fc8: 40022000 .word 0x40022000
+ 8000fcc: 40022400 .word 0x40022400
+ 8000fd0: 40013c00 .word 0x40013c00
+
+08000fd4 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- 8000f30: b580 push {r7, lr}
- 8000f32: b086 sub sp, #24
- 8000f34: af00 add r7, sp, #0
- 8000f36: 6078 str r0, [r7, #4]
+ 8000fd4: b580 push {r7, lr}
+ 8000fd6: b086 sub sp, #24
+ 8000fd8: af00 add r7, sp, #0
+ 8000fda: 6078 str r0, [r7, #4]
uint32_t tickstart;
FlagStatus pwrclkchanged = RESET;
- 8000f38: 2300 movs r3, #0
- 8000f3a: 75fb strb r3, [r7, #23]
+ 8000fdc: 2300 movs r3, #0
+ 8000fde: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
- 8000f3c: 687b ldr r3, [r7, #4]
- 8000f3e: 2b00 cmp r3, #0
- 8000f40: d101 bne.n 8000f46 <HAL_RCC_OscConfig+0x16>
+ 8000fe0: 687b ldr r3, [r7, #4]
+ 8000fe2: 2b00 cmp r3, #0
+ 8000fe4: d101 bne.n 8000fea <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
- 8000f42: 2301 movs r3, #1
- 8000f44: e25e b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 8000fe6: 2301 movs r3, #1
+ 8000fe8: e25e b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8000f46: 687b ldr r3, [r7, #4]
- 8000f48: 681b ldr r3, [r3, #0]
- 8000f4a: f003 0301 and.w r3, r3, #1
- 8000f4e: 2b00 cmp r3, #0
- 8000f50: f000 8087 beq.w 8001062 <HAL_RCC_OscConfig+0x132>
+ 8000fea: 687b ldr r3, [r7, #4]
+ 8000fec: 681b ldr r3, [r3, #0]
+ 8000fee: f003 0301 and.w r3, r3, #1
+ 8000ff2: 2b00 cmp r3, #0
+ 8000ff4: f000 8087 beq.w 8001106 <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8000f54: 4b96 ldr r3, [pc, #600] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000f56: 689b ldr r3, [r3, #8]
- 8000f58: f003 030c and.w r3, r3, #12
- 8000f5c: 2b04 cmp r3, #4
- 8000f5e: d00c beq.n 8000f7a <HAL_RCC_OscConfig+0x4a>
+ 8000ff8: 4b96 ldr r3, [pc, #600] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8000ffa: 689b ldr r3, [r3, #8]
+ 8000ffc: f003 030c and.w r3, r3, #12
+ 8001000: 2b04 cmp r3, #4
+ 8001002: d00c beq.n 800101e <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 8000f60: 4b93 ldr r3, [pc, #588] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000f62: 689b ldr r3, [r3, #8]
- 8000f64: f003 030c and.w r3, r3, #12
- 8000f68: 2b08 cmp r3, #8
- 8000f6a: d112 bne.n 8000f92 <HAL_RCC_OscConfig+0x62>
- 8000f6c: 4b90 ldr r3, [pc, #576] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000f6e: 685b ldr r3, [r3, #4]
- 8000f70: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8000f74: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8000f78: d10b bne.n 8000f92 <HAL_RCC_OscConfig+0x62>
+ 8001004: 4b93 ldr r3, [pc, #588] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001006: 689b ldr r3, [r3, #8]
+ 8001008: f003 030c and.w r3, r3, #12
+ 800100c: 2b08 cmp r3, #8
+ 800100e: d112 bne.n 8001036 <HAL_RCC_OscConfig+0x62>
+ 8001010: 4b90 ldr r3, [pc, #576] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001012: 685b ldr r3, [r3, #4]
+ 8001014: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8001018: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 800101c: d10b bne.n 8001036 <HAL_RCC_OscConfig+0x62>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8000f7a: 4b8d ldr r3, [pc, #564] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000f7c: 681b ldr r3, [r3, #0]
- 8000f7e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8000f82: 2b00 cmp r3, #0
- 8000f84: d06c beq.n 8001060 <HAL_RCC_OscConfig+0x130>
- 8000f86: 687b ldr r3, [r7, #4]
- 8000f88: 685b ldr r3, [r3, #4]
- 8000f8a: 2b00 cmp r3, #0
- 8000f8c: d168 bne.n 8001060 <HAL_RCC_OscConfig+0x130>
+ 800101e: 4b8d ldr r3, [pc, #564] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001020: 681b ldr r3, [r3, #0]
+ 8001022: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8001026: 2b00 cmp r3, #0
+ 8001028: d06c beq.n 8001104 <HAL_RCC_OscConfig+0x130>
+ 800102a: 687b ldr r3, [r7, #4]
+ 800102c: 685b ldr r3, [r3, #4]
+ 800102e: 2b00 cmp r3, #0
+ 8001030: d168 bne.n 8001104 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
- 8000f8e: 2301 movs r3, #1
- 8000f90: e238 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 8001032: 2301 movs r3, #1
+ 8001034: e238 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 8000f92: 687b ldr r3, [r7, #4]
- 8000f94: 685b ldr r3, [r3, #4]
- 8000f96: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8000f9a: d106 bne.n 8000faa <HAL_RCC_OscConfig+0x7a>
- 8000f9c: 4b84 ldr r3, [pc, #528] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000f9e: 681b ldr r3, [r3, #0]
- 8000fa0: 4a83 ldr r2, [pc, #524] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fa2: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8000fa6: 6013 str r3, [r2, #0]
- 8000fa8: e02e b.n 8001008 <HAL_RCC_OscConfig+0xd8>
- 8000faa: 687b ldr r3, [r7, #4]
- 8000fac: 685b ldr r3, [r3, #4]
- 8000fae: 2b00 cmp r3, #0
- 8000fb0: d10c bne.n 8000fcc <HAL_RCC_OscConfig+0x9c>
- 8000fb2: 4b7f ldr r3, [pc, #508] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fb4: 681b ldr r3, [r3, #0]
- 8000fb6: 4a7e ldr r2, [pc, #504] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fb8: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8000fbc: 6013 str r3, [r2, #0]
- 8000fbe: 4b7c ldr r3, [pc, #496] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fc0: 681b ldr r3, [r3, #0]
- 8000fc2: 4a7b ldr r2, [pc, #492] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fc4: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8000fc8: 6013 str r3, [r2, #0]
- 8000fca: e01d b.n 8001008 <HAL_RCC_OscConfig+0xd8>
- 8000fcc: 687b ldr r3, [r7, #4]
- 8000fce: 685b ldr r3, [r3, #4]
- 8000fd0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 8000fd4: d10c bne.n 8000ff0 <HAL_RCC_OscConfig+0xc0>
- 8000fd6: 4b76 ldr r3, [pc, #472] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fd8: 681b ldr r3, [r3, #0]
- 8000fda: 4a75 ldr r2, [pc, #468] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fdc: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 8000fe0: 6013 str r3, [r2, #0]
- 8000fe2: 4b73 ldr r3, [pc, #460] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fe4: 681b ldr r3, [r3, #0]
- 8000fe6: 4a72 ldr r2, [pc, #456] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000fe8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8000fec: 6013 str r3, [r2, #0]
- 8000fee: e00b b.n 8001008 <HAL_RCC_OscConfig+0xd8>
- 8000ff0: 4b6f ldr r3, [pc, #444] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000ff2: 681b ldr r3, [r3, #0]
- 8000ff4: 4a6e ldr r2, [pc, #440] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000ff6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8000ffa: 6013 str r3, [r2, #0]
- 8000ffc: 4b6c ldr r3, [pc, #432] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8000ffe: 681b ldr r3, [r3, #0]
- 8001000: 4a6b ldr r2, [pc, #428] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001002: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8001006: 6013 str r3, [r2, #0]
+ 8001036: 687b ldr r3, [r7, #4]
+ 8001038: 685b ldr r3, [r3, #4]
+ 800103a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 800103e: d106 bne.n 800104e <HAL_RCC_OscConfig+0x7a>
+ 8001040: 4b84 ldr r3, [pc, #528] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001042: 681b ldr r3, [r3, #0]
+ 8001044: 4a83 ldr r2, [pc, #524] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001046: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 800104a: 6013 str r3, [r2, #0]
+ 800104c: e02e b.n 80010ac <HAL_RCC_OscConfig+0xd8>
+ 800104e: 687b ldr r3, [r7, #4]
+ 8001050: 685b ldr r3, [r3, #4]
+ 8001052: 2b00 cmp r3, #0
+ 8001054: d10c bne.n 8001070 <HAL_RCC_OscConfig+0x9c>
+ 8001056: 4b7f ldr r3, [pc, #508] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001058: 681b ldr r3, [r3, #0]
+ 800105a: 4a7e ldr r2, [pc, #504] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 800105c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8001060: 6013 str r3, [r2, #0]
+ 8001062: 4b7c ldr r3, [pc, #496] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001064: 681b ldr r3, [r3, #0]
+ 8001066: 4a7b ldr r2, [pc, #492] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001068: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 800106c: 6013 str r3, [r2, #0]
+ 800106e: e01d b.n 80010ac <HAL_RCC_OscConfig+0xd8>
+ 8001070: 687b ldr r3, [r7, #4]
+ 8001072: 685b ldr r3, [r3, #4]
+ 8001074: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
+ 8001078: d10c bne.n 8001094 <HAL_RCC_OscConfig+0xc0>
+ 800107a: 4b76 ldr r3, [pc, #472] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 800107c: 681b ldr r3, [r3, #0]
+ 800107e: 4a75 ldr r2, [pc, #468] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001080: f443 2380 orr.w r3, r3, #262144 ; 0x40000
+ 8001084: 6013 str r3, [r2, #0]
+ 8001086: 4b73 ldr r3, [pc, #460] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001088: 681b ldr r3, [r3, #0]
+ 800108a: 4a72 ldr r2, [pc, #456] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 800108c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8001090: 6013 str r3, [r2, #0]
+ 8001092: e00b b.n 80010ac <HAL_RCC_OscConfig+0xd8>
+ 8001094: 4b6f ldr r3, [pc, #444] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001096: 681b ldr r3, [r3, #0]
+ 8001098: 4a6e ldr r2, [pc, #440] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 800109a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 800109e: 6013 str r3, [r2, #0]
+ 80010a0: 4b6c ldr r3, [pc, #432] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80010a2: 681b ldr r3, [r3, #0]
+ 80010a4: 4a6b ldr r2, [pc, #428] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80010a6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 80010aa: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8001008: 687b ldr r3, [r7, #4]
- 800100a: 685b ldr r3, [r3, #4]
- 800100c: 2b00 cmp r3, #0
- 800100e: d013 beq.n 8001038 <HAL_RCC_OscConfig+0x108>
+ 80010ac: 687b ldr r3, [r7, #4]
+ 80010ae: 685b ldr r3, [r3, #4]
+ 80010b0: 2b00 cmp r3, #0
+ 80010b2: d013 beq.n 80010dc <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001010: f7ff fcd0 bl 80009b4 <HAL_GetTick>
- 8001014: 6138 str r0, [r7, #16]
+ 80010b4: f7ff fcd0 bl 8000a58 <HAL_GetTick>
+ 80010b8: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8001016: e008 b.n 800102a <HAL_RCC_OscConfig+0xfa>
+ 80010ba: e008 b.n 80010ce <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8001018: f7ff fccc bl 80009b4 <HAL_GetTick>
- 800101c: 4602 mov r2, r0
- 800101e: 693b ldr r3, [r7, #16]
- 8001020: 1ad3 subs r3, r2, r3
- 8001022: 2b64 cmp r3, #100 ; 0x64
- 8001024: d901 bls.n 800102a <HAL_RCC_OscConfig+0xfa>
+ 80010bc: f7ff fccc bl 8000a58 <HAL_GetTick>
+ 80010c0: 4602 mov r2, r0
+ 80010c2: 693b ldr r3, [r7, #16]
+ 80010c4: 1ad3 subs r3, r2, r3
+ 80010c6: 2b64 cmp r3, #100 ; 0x64
+ 80010c8: d901 bls.n 80010ce <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
- 8001026: 2303 movs r3, #3
- 8001028: e1ec b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 80010ca: 2303 movs r3, #3
+ 80010cc: e1ec b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800102a: 4b61 ldr r3, [pc, #388] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 800102c: 681b ldr r3, [r3, #0]
- 800102e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8001032: 2b00 cmp r3, #0
- 8001034: d0f0 beq.n 8001018 <HAL_RCC_OscConfig+0xe8>
- 8001036: e014 b.n 8001062 <HAL_RCC_OscConfig+0x132>
+ 80010ce: 4b61 ldr r3, [pc, #388] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80010d0: 681b ldr r3, [r3, #0]
+ 80010d2: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80010d6: 2b00 cmp r3, #0
+ 80010d8: d0f0 beq.n 80010bc <HAL_RCC_OscConfig+0xe8>
+ 80010da: e014 b.n 8001106 <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001038: f7ff fcbc bl 80009b4 <HAL_GetTick>
- 800103c: 6138 str r0, [r7, #16]
+ 80010dc: f7ff fcbc bl 8000a58 <HAL_GetTick>
+ 80010e0: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 800103e: e008 b.n 8001052 <HAL_RCC_OscConfig+0x122>
+ 80010e2: e008 b.n 80010f6 <HAL_RCC_OscConfig+0x122>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8001040: f7ff fcb8 bl 80009b4 <HAL_GetTick>
- 8001044: 4602 mov r2, r0
- 8001046: 693b ldr r3, [r7, #16]
- 8001048: 1ad3 subs r3, r2, r3
- 800104a: 2b64 cmp r3, #100 ; 0x64
- 800104c: d901 bls.n 8001052 <HAL_RCC_OscConfig+0x122>
+ 80010e4: f7ff fcb8 bl 8000a58 <HAL_GetTick>
+ 80010e8: 4602 mov r2, r0
+ 80010ea: 693b ldr r3, [r7, #16]
+ 80010ec: 1ad3 subs r3, r2, r3
+ 80010ee: 2b64 cmp r3, #100 ; 0x64
+ 80010f0: d901 bls.n 80010f6 <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
- 800104e: 2303 movs r3, #3
- 8001050: e1d8 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 80010f2: 2303 movs r3, #3
+ 80010f4: e1d8 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8001052: 4b57 ldr r3, [pc, #348] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001054: 681b ldr r3, [r3, #0]
- 8001056: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 800105a: 2b00 cmp r3, #0
- 800105c: d1f0 bne.n 8001040 <HAL_RCC_OscConfig+0x110>
- 800105e: e000 b.n 8001062 <HAL_RCC_OscConfig+0x132>
+ 80010f6: 4b57 ldr r3, [pc, #348] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80010f8: 681b ldr r3, [r3, #0]
+ 80010fa: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80010fe: 2b00 cmp r3, #0
+ 8001100: d1f0 bne.n 80010e4 <HAL_RCC_OscConfig+0x110>
+ 8001102: e000 b.n 8001106 <HAL_RCC_OscConfig+0x132>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8001060: bf00 nop
+ 8001104: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8001062: 687b ldr r3, [r7, #4]
- 8001064: 681b ldr r3, [r3, #0]
- 8001066: f003 0302 and.w r3, r3, #2
- 800106a: 2b00 cmp r3, #0
- 800106c: d069 beq.n 8001142 <HAL_RCC_OscConfig+0x212>
+ 8001106: 687b ldr r3, [r7, #4]
+ 8001108: 681b ldr r3, [r3, #0]
+ 800110a: f003 0302 and.w r3, r3, #2
+ 800110e: 2b00 cmp r3, #0
+ 8001110: d069 beq.n 80011e6 <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 800106e: 4b50 ldr r3, [pc, #320] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001070: 689b ldr r3, [r3, #8]
- 8001072: f003 030c and.w r3, r3, #12
- 8001076: 2b00 cmp r3, #0
- 8001078: d00b beq.n 8001092 <HAL_RCC_OscConfig+0x162>
+ 8001112: 4b50 ldr r3, [pc, #320] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001114: 689b ldr r3, [r3, #8]
+ 8001116: f003 030c and.w r3, r3, #12
+ 800111a: 2b00 cmp r3, #0
+ 800111c: d00b beq.n 8001136 <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 800107a: 4b4d ldr r3, [pc, #308] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 800107c: 689b ldr r3, [r3, #8]
- 800107e: f003 030c and.w r3, r3, #12
- 8001082: 2b08 cmp r3, #8
- 8001084: d11c bne.n 80010c0 <HAL_RCC_OscConfig+0x190>
- 8001086: 4b4a ldr r3, [pc, #296] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001088: 685b ldr r3, [r3, #4]
- 800108a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800108e: 2b00 cmp r3, #0
- 8001090: d116 bne.n 80010c0 <HAL_RCC_OscConfig+0x190>
+ 800111e: 4b4d ldr r3, [pc, #308] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001120: 689b ldr r3, [r3, #8]
+ 8001122: f003 030c and.w r3, r3, #12
+ 8001126: 2b08 cmp r3, #8
+ 8001128: d11c bne.n 8001164 <HAL_RCC_OscConfig+0x190>
+ 800112a: 4b4a ldr r3, [pc, #296] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 800112c: 685b ldr r3, [r3, #4]
+ 800112e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8001132: 2b00 cmp r3, #0
+ 8001134: d116 bne.n 8001164 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8001092: 4b47 ldr r3, [pc, #284] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001094: 681b ldr r3, [r3, #0]
- 8001096: f003 0302 and.w r3, r3, #2
- 800109a: 2b00 cmp r3, #0
- 800109c: d005 beq.n 80010aa <HAL_RCC_OscConfig+0x17a>
- 800109e: 687b ldr r3, [r7, #4]
- 80010a0: 68db ldr r3, [r3, #12]
- 80010a2: 2b01 cmp r3, #1
- 80010a4: d001 beq.n 80010aa <HAL_RCC_OscConfig+0x17a>
+ 8001136: 4b47 ldr r3, [pc, #284] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001138: 681b ldr r3, [r3, #0]
+ 800113a: f003 0302 and.w r3, r3, #2
+ 800113e: 2b00 cmp r3, #0
+ 8001140: d005 beq.n 800114e <HAL_RCC_OscConfig+0x17a>
+ 8001142: 687b ldr r3, [r7, #4]
+ 8001144: 68db ldr r3, [r3, #12]
+ 8001146: 2b01 cmp r3, #1
+ 8001148: d001 beq.n 800114e <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
- 80010a6: 2301 movs r3, #1
- 80010a8: e1ac b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 800114a: 2301 movs r3, #1
+ 800114c: e1ac b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80010aa: 4b41 ldr r3, [pc, #260] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 80010ac: 681b ldr r3, [r3, #0]
- 80010ae: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 80010b2: 687b ldr r3, [r7, #4]
- 80010b4: 691b ldr r3, [r3, #16]
- 80010b6: 00db lsls r3, r3, #3
- 80010b8: 493d ldr r1, [pc, #244] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 80010ba: 4313 orrs r3, r2
- 80010bc: 600b str r3, [r1, #0]
+ 800114e: 4b41 ldr r3, [pc, #260] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001150: 681b ldr r3, [r3, #0]
+ 8001152: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 8001156: 687b ldr r3, [r7, #4]
+ 8001158: 691b ldr r3, [r3, #16]
+ 800115a: 00db lsls r3, r3, #3
+ 800115c: 493d ldr r1, [pc, #244] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 800115e: 4313 orrs r3, r2
+ 8001160: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80010be: e040 b.n 8001142 <HAL_RCC_OscConfig+0x212>
+ 8001162: e040 b.n 80011e6 <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 80010c0: 687b ldr r3, [r7, #4]
- 80010c2: 68db ldr r3, [r3, #12]
- 80010c4: 2b00 cmp r3, #0
- 80010c6: d023 beq.n 8001110 <HAL_RCC_OscConfig+0x1e0>
+ 8001164: 687b ldr r3, [r7, #4]
+ 8001166: 68db ldr r3, [r3, #12]
+ 8001168: 2b00 cmp r3, #0
+ 800116a: d023 beq.n 80011b4 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
- 80010c8: 4b39 ldr r3, [pc, #228] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 80010ca: 681b ldr r3, [r3, #0]
- 80010cc: 4a38 ldr r2, [pc, #224] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 80010ce: f043 0301 orr.w r3, r3, #1
- 80010d2: 6013 str r3, [r2, #0]
+ 800116c: 4b39 ldr r3, [pc, #228] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 800116e: 681b ldr r3, [r3, #0]
+ 8001170: 4a38 ldr r2, [pc, #224] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001172: f043 0301 orr.w r3, r3, #1
+ 8001176: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80010d4: f7ff fc6e bl 80009b4 <HAL_GetTick>
- 80010d8: 6138 str r0, [r7, #16]
+ 8001178: f7ff fc6e bl 8000a58 <HAL_GetTick>
+ 800117c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80010da: e008 b.n 80010ee <HAL_RCC_OscConfig+0x1be>
+ 800117e: e008 b.n 8001192 <HAL_RCC_OscConfig+0x1be>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80010dc: f7ff fc6a bl 80009b4 <HAL_GetTick>
- 80010e0: 4602 mov r2, r0
- 80010e2: 693b ldr r3, [r7, #16]
- 80010e4: 1ad3 subs r3, r2, r3
- 80010e6: 2b02 cmp r3, #2
- 80010e8: d901 bls.n 80010ee <HAL_RCC_OscConfig+0x1be>
+ 8001180: f7ff fc6a bl 8000a58 <HAL_GetTick>
+ 8001184: 4602 mov r2, r0
+ 8001186: 693b ldr r3, [r7, #16]
+ 8001188: 1ad3 subs r3, r2, r3
+ 800118a: 2b02 cmp r3, #2
+ 800118c: d901 bls.n 8001192 <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
- 80010ea: 2303 movs r3, #3
- 80010ec: e18a b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 800118e: 2303 movs r3, #3
+ 8001190: e18a b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80010ee: 4b30 ldr r3, [pc, #192] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 80010f0: 681b ldr r3, [r3, #0]
- 80010f2: f003 0302 and.w r3, r3, #2
- 80010f6: 2b00 cmp r3, #0
- 80010f8: d0f0 beq.n 80010dc <HAL_RCC_OscConfig+0x1ac>
+ 8001192: 4b30 ldr r3, [pc, #192] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001194: 681b ldr r3, [r3, #0]
+ 8001196: f003 0302 and.w r3, r3, #2
+ 800119a: 2b00 cmp r3, #0
+ 800119c: d0f0 beq.n 8001180 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80010fa: 4b2d ldr r3, [pc, #180] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 80010fc: 681b ldr r3, [r3, #0]
- 80010fe: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 8001102: 687b ldr r3, [r7, #4]
- 8001104: 691b ldr r3, [r3, #16]
- 8001106: 00db lsls r3, r3, #3
- 8001108: 4929 ldr r1, [pc, #164] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 800110a: 4313 orrs r3, r2
- 800110c: 600b str r3, [r1, #0]
- 800110e: e018 b.n 8001142 <HAL_RCC_OscConfig+0x212>
+ 800119e: 4b2d ldr r3, [pc, #180] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80011a0: 681b ldr r3, [r3, #0]
+ 80011a2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 80011a6: 687b ldr r3, [r7, #4]
+ 80011a8: 691b ldr r3, [r3, #16]
+ 80011aa: 00db lsls r3, r3, #3
+ 80011ac: 4929 ldr r1, [pc, #164] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80011ae: 4313 orrs r3, r2
+ 80011b0: 600b str r3, [r1, #0]
+ 80011b2: e018 b.n 80011e6 <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
- 8001110: 4b27 ldr r3, [pc, #156] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001112: 681b ldr r3, [r3, #0]
- 8001114: 4a26 ldr r2, [pc, #152] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001116: f023 0301 bic.w r3, r3, #1
- 800111a: 6013 str r3, [r2, #0]
+ 80011b4: 4b27 ldr r3, [pc, #156] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80011b6: 681b ldr r3, [r3, #0]
+ 80011b8: 4a26 ldr r2, [pc, #152] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80011ba: f023 0301 bic.w r3, r3, #1
+ 80011be: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 800111c: f7ff fc4a bl 80009b4 <HAL_GetTick>
- 8001120: 6138 str r0, [r7, #16]
+ 80011c0: f7ff fc4a bl 8000a58 <HAL_GetTick>
+ 80011c4: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001122: e008 b.n 8001136 <HAL_RCC_OscConfig+0x206>
+ 80011c6: e008 b.n 80011da <HAL_RCC_OscConfig+0x206>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8001124: f7ff fc46 bl 80009b4 <HAL_GetTick>
- 8001128: 4602 mov r2, r0
- 800112a: 693b ldr r3, [r7, #16]
- 800112c: 1ad3 subs r3, r2, r3
- 800112e: 2b02 cmp r3, #2
- 8001130: d901 bls.n 8001136 <HAL_RCC_OscConfig+0x206>
+ 80011c8: f7ff fc46 bl 8000a58 <HAL_GetTick>
+ 80011cc: 4602 mov r2, r0
+ 80011ce: 693b ldr r3, [r7, #16]
+ 80011d0: 1ad3 subs r3, r2, r3
+ 80011d2: 2b02 cmp r3, #2
+ 80011d4: d901 bls.n 80011da <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
- 8001132: 2303 movs r3, #3
- 8001134: e166 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 80011d6: 2303 movs r3, #3
+ 80011d8: e166 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001136: 4b1e ldr r3, [pc, #120] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001138: 681b ldr r3, [r3, #0]
- 800113a: f003 0302 and.w r3, r3, #2
- 800113e: 2b00 cmp r3, #0
- 8001140: d1f0 bne.n 8001124 <HAL_RCC_OscConfig+0x1f4>
+ 80011da: 4b1e ldr r3, [pc, #120] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80011dc: 681b ldr r3, [r3, #0]
+ 80011de: f003 0302 and.w r3, r3, #2
+ 80011e2: 2b00 cmp r3, #0
+ 80011e4: d1f0 bne.n 80011c8 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8001142: 687b ldr r3, [r7, #4]
- 8001144: 681b ldr r3, [r3, #0]
- 8001146: f003 0308 and.w r3, r3, #8
- 800114a: 2b00 cmp r3, #0
- 800114c: d038 beq.n 80011c0 <HAL_RCC_OscConfig+0x290>
+ 80011e6: 687b ldr r3, [r7, #4]
+ 80011e8: 681b ldr r3, [r3, #0]
+ 80011ea: f003 0308 and.w r3, r3, #8
+ 80011ee: 2b00 cmp r3, #0
+ 80011f0: d038 beq.n 8001264 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 800114e: 687b ldr r3, [r7, #4]
- 8001150: 695b ldr r3, [r3, #20]
- 8001152: 2b00 cmp r3, #0
- 8001154: d019 beq.n 800118a <HAL_RCC_OscConfig+0x25a>
+ 80011f2: 687b ldr r3, [r7, #4]
+ 80011f4: 695b ldr r3, [r3, #20]
+ 80011f6: 2b00 cmp r3, #0
+ 80011f8: d019 beq.n 800122e <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
- 8001156: 4b16 ldr r3, [pc, #88] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001158: 6f5b ldr r3, [r3, #116] ; 0x74
- 800115a: 4a15 ldr r2, [pc, #84] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 800115c: f043 0301 orr.w r3, r3, #1
- 8001160: 6753 str r3, [r2, #116] ; 0x74
+ 80011fa: 4b16 ldr r3, [pc, #88] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 80011fc: 6f5b ldr r3, [r3, #116] ; 0x74
+ 80011fe: 4a15 ldr r2, [pc, #84] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001200: f043 0301 orr.w r3, r3, #1
+ 8001204: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001162: f7ff fc27 bl 80009b4 <HAL_GetTick>
- 8001166: 6138 str r0, [r7, #16]
+ 8001206: f7ff fc27 bl 8000a58 <HAL_GetTick>
+ 800120a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8001168: e008 b.n 800117c <HAL_RCC_OscConfig+0x24c>
+ 800120c: e008 b.n 8001220 <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800116a: f7ff fc23 bl 80009b4 <HAL_GetTick>
- 800116e: 4602 mov r2, r0
- 8001170: 693b ldr r3, [r7, #16]
- 8001172: 1ad3 subs r3, r2, r3
- 8001174: 2b02 cmp r3, #2
- 8001176: d901 bls.n 800117c <HAL_RCC_OscConfig+0x24c>
+ 800120e: f7ff fc23 bl 8000a58 <HAL_GetTick>
+ 8001212: 4602 mov r2, r0
+ 8001214: 693b ldr r3, [r7, #16]
+ 8001216: 1ad3 subs r3, r2, r3
+ 8001218: 2b02 cmp r3, #2
+ 800121a: d901 bls.n 8001220 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
- 8001178: 2303 movs r3, #3
- 800117a: e143 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 800121c: 2303 movs r3, #3
+ 800121e: e143 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 800117c: 4b0c ldr r3, [pc, #48] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 800117e: 6f5b ldr r3, [r3, #116] ; 0x74
- 8001180: f003 0302 and.w r3, r3, #2
- 8001184: 2b00 cmp r3, #0
- 8001186: d0f0 beq.n 800116a <HAL_RCC_OscConfig+0x23a>
- 8001188: e01a b.n 80011c0 <HAL_RCC_OscConfig+0x290>
+ 8001220: 4b0c ldr r3, [pc, #48] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001222: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8001224: f003 0302 and.w r3, r3, #2
+ 8001228: 2b00 cmp r3, #0
+ 800122a: d0f0 beq.n 800120e <HAL_RCC_OscConfig+0x23a>
+ 800122c: e01a b.n 8001264 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
- 800118a: 4b09 ldr r3, [pc, #36] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 800118c: 6f5b ldr r3, [r3, #116] ; 0x74
- 800118e: 4a08 ldr r2, [pc, #32] ; (80011b0 <HAL_RCC_OscConfig+0x280>)
- 8001190: f023 0301 bic.w r3, r3, #1
- 8001194: 6753 str r3, [r2, #116] ; 0x74
+ 800122e: 4b09 ldr r3, [pc, #36] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001230: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8001232: 4a08 ldr r2, [pc, #32] ; (8001254 <HAL_RCC_OscConfig+0x280>)
+ 8001234: f023 0301 bic.w r3, r3, #1
+ 8001238: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001196: f7ff fc0d bl 80009b4 <HAL_GetTick>
- 800119a: 6138 str r0, [r7, #16]
+ 800123a: f7ff fc0d bl 8000a58 <HAL_GetTick>
+ 800123e: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 800119c: e00a b.n 80011b4 <HAL_RCC_OscConfig+0x284>
+ 8001240: e00a b.n 8001258 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800119e: f7ff fc09 bl 80009b4 <HAL_GetTick>
- 80011a2: 4602 mov r2, r0
- 80011a4: 693b ldr r3, [r7, #16]
- 80011a6: 1ad3 subs r3, r2, r3
- 80011a8: 2b02 cmp r3, #2
- 80011aa: d903 bls.n 80011b4 <HAL_RCC_OscConfig+0x284>
+ 8001242: f7ff fc09 bl 8000a58 <HAL_GetTick>
+ 8001246: 4602 mov r2, r0
+ 8001248: 693b ldr r3, [r7, #16]
+ 800124a: 1ad3 subs r3, r2, r3
+ 800124c: 2b02 cmp r3, #2
+ 800124e: d903 bls.n 8001258 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
- 80011ac: 2303 movs r3, #3
- 80011ae: e129 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
- 80011b0: 40023800 .word 0x40023800
+ 8001250: 2303 movs r3, #3
+ 8001252: e129 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
+ 8001254: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 80011b4: 4b95 ldr r3, [pc, #596] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80011b6: 6f5b ldr r3, [r3, #116] ; 0x74
- 80011b8: f003 0302 and.w r3, r3, #2
- 80011bc: 2b00 cmp r3, #0
- 80011be: d1ee bne.n 800119e <HAL_RCC_OscConfig+0x26e>
+ 8001258: 4b95 ldr r3, [pc, #596] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 800125a: 6f5b ldr r3, [r3, #116] ; 0x74
+ 800125c: f003 0302 and.w r3, r3, #2
+ 8001260: 2b00 cmp r3, #0
+ 8001262: d1ee bne.n 8001242 <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 80011c0: 687b ldr r3, [r7, #4]
- 80011c2: 681b ldr r3, [r3, #0]
- 80011c4: f003 0304 and.w r3, r3, #4
- 80011c8: 2b00 cmp r3, #0
- 80011ca: f000 80a4 beq.w 8001316 <HAL_RCC_OscConfig+0x3e6>
+ 8001264: 687b ldr r3, [r7, #4]
+ 8001266: 681b ldr r3, [r3, #0]
+ 8001268: f003 0304 and.w r3, r3, #4
+ 800126c: 2b00 cmp r3, #0
+ 800126e: f000 80a4 beq.w 80013ba <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80011ce: 4b8f ldr r3, [pc, #572] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80011d0: 6c1b ldr r3, [r3, #64] ; 0x40
- 80011d2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80011d6: 2b00 cmp r3, #0
- 80011d8: d10d bne.n 80011f6 <HAL_RCC_OscConfig+0x2c6>
+ 8001272: 4b8f ldr r3, [pc, #572] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001274: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001276: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 800127a: 2b00 cmp r3, #0
+ 800127c: d10d bne.n 800129a <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
- 80011da: 4b8c ldr r3, [pc, #560] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80011dc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80011de: 4a8b ldr r2, [pc, #556] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80011e0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 80011e4: 6413 str r3, [r2, #64] ; 0x40
- 80011e6: 4b89 ldr r3, [pc, #548] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80011e8: 6c1b ldr r3, [r3, #64] ; 0x40
- 80011ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80011ee: 60fb str r3, [r7, #12]
- 80011f0: 68fb ldr r3, [r7, #12]
+ 800127e: 4b8c ldr r3, [pc, #560] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001280: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001282: 4a8b ldr r2, [pc, #556] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001284: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8001288: 6413 str r3, [r2, #64] ; 0x40
+ 800128a: 4b89 ldr r3, [pc, #548] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 800128c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800128e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001292: 60fb str r3, [r7, #12]
+ 8001294: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
- 80011f2: 2301 movs r3, #1
- 80011f4: 75fb strb r3, [r7, #23]
+ 8001296: 2301 movs r3, #1
+ 8001298: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 80011f6: 4b86 ldr r3, [pc, #536] ; (8001410 <HAL_RCC_OscConfig+0x4e0>)
- 80011f8: 681b ldr r3, [r3, #0]
- 80011fa: f403 7380 and.w r3, r3, #256 ; 0x100
- 80011fe: 2b00 cmp r3, #0
- 8001200: d118 bne.n 8001234 <HAL_RCC_OscConfig+0x304>
+ 800129a: 4b86 ldr r3, [pc, #536] ; (80014b4 <HAL_RCC_OscConfig+0x4e0>)
+ 800129c: 681b ldr r3, [r3, #0]
+ 800129e: f403 7380 and.w r3, r3, #256 ; 0x100
+ 80012a2: 2b00 cmp r3, #0
+ 80012a4: d118 bne.n 80012d8 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
- 8001202: 4b83 ldr r3, [pc, #524] ; (8001410 <HAL_RCC_OscConfig+0x4e0>)
- 8001204: 681b ldr r3, [r3, #0]
- 8001206: 4a82 ldr r2, [pc, #520] ; (8001410 <HAL_RCC_OscConfig+0x4e0>)
- 8001208: f443 7380 orr.w r3, r3, #256 ; 0x100
- 800120c: 6013 str r3, [r2, #0]
+ 80012a6: 4b83 ldr r3, [pc, #524] ; (80014b4 <HAL_RCC_OscConfig+0x4e0>)
+ 80012a8: 681b ldr r3, [r3, #0]
+ 80012aa: 4a82 ldr r2, [pc, #520] ; (80014b4 <HAL_RCC_OscConfig+0x4e0>)
+ 80012ac: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 80012b0: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
- 800120e: f7ff fbd1 bl 80009b4 <HAL_GetTick>
- 8001212: 6138 str r0, [r7, #16]
+ 80012b2: f7ff fbd1 bl 8000a58 <HAL_GetTick>
+ 80012b6: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8001214: e008 b.n 8001228 <HAL_RCC_OscConfig+0x2f8>
+ 80012b8: e008 b.n 80012cc <HAL_RCC_OscConfig+0x2f8>
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 8001216: f7ff fbcd bl 80009b4 <HAL_GetTick>
- 800121a: 4602 mov r2, r0
- 800121c: 693b ldr r3, [r7, #16]
- 800121e: 1ad3 subs r3, r2, r3
- 8001220: 2b64 cmp r3, #100 ; 0x64
- 8001222: d901 bls.n 8001228 <HAL_RCC_OscConfig+0x2f8>
+ 80012ba: f7ff fbcd bl 8000a58 <HAL_GetTick>
+ 80012be: 4602 mov r2, r0
+ 80012c0: 693b ldr r3, [r7, #16]
+ 80012c2: 1ad3 subs r3, r2, r3
+ 80012c4: 2b64 cmp r3, #100 ; 0x64
+ 80012c6: d901 bls.n 80012cc <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
- 8001224: 2303 movs r3, #3
- 8001226: e0ed b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 80012c8: 2303 movs r3, #3
+ 80012ca: e0ed b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8001228: 4b79 ldr r3, [pc, #484] ; (8001410 <HAL_RCC_OscConfig+0x4e0>)
- 800122a: 681b ldr r3, [r3, #0]
- 800122c: f403 7380 and.w r3, r3, #256 ; 0x100
- 8001230: 2b00 cmp r3, #0
- 8001232: d0f0 beq.n 8001216 <HAL_RCC_OscConfig+0x2e6>
+ 80012cc: 4b79 ldr r3, [pc, #484] ; (80014b4 <HAL_RCC_OscConfig+0x4e0>)
+ 80012ce: 681b ldr r3, [r3, #0]
+ 80012d0: f403 7380 and.w r3, r3, #256 ; 0x100
+ 80012d4: 2b00 cmp r3, #0
+ 80012d6: d0f0 beq.n 80012ba <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8001234: 687b ldr r3, [r7, #4]
- 8001236: 689b ldr r3, [r3, #8]
- 8001238: 2b01 cmp r3, #1
- 800123a: d106 bne.n 800124a <HAL_RCC_OscConfig+0x31a>
- 800123c: 4b73 ldr r3, [pc, #460] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 800123e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001240: 4a72 ldr r2, [pc, #456] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001242: f043 0301 orr.w r3, r3, #1
- 8001246: 6713 str r3, [r2, #112] ; 0x70
- 8001248: e02d b.n 80012a6 <HAL_RCC_OscConfig+0x376>
- 800124a: 687b ldr r3, [r7, #4]
- 800124c: 689b ldr r3, [r3, #8]
- 800124e: 2b00 cmp r3, #0
- 8001250: d10c bne.n 800126c <HAL_RCC_OscConfig+0x33c>
- 8001252: 4b6e ldr r3, [pc, #440] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001254: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001256: 4a6d ldr r2, [pc, #436] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001258: f023 0301 bic.w r3, r3, #1
- 800125c: 6713 str r3, [r2, #112] ; 0x70
- 800125e: 4b6b ldr r3, [pc, #428] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001260: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001262: 4a6a ldr r2, [pc, #424] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001264: f023 0304 bic.w r3, r3, #4
- 8001268: 6713 str r3, [r2, #112] ; 0x70
- 800126a: e01c b.n 80012a6 <HAL_RCC_OscConfig+0x376>
- 800126c: 687b ldr r3, [r7, #4]
- 800126e: 689b ldr r3, [r3, #8]
- 8001270: 2b05 cmp r3, #5
- 8001272: d10c bne.n 800128e <HAL_RCC_OscConfig+0x35e>
- 8001274: 4b65 ldr r3, [pc, #404] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001276: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001278: 4a64 ldr r2, [pc, #400] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 800127a: f043 0304 orr.w r3, r3, #4
- 800127e: 6713 str r3, [r2, #112] ; 0x70
- 8001280: 4b62 ldr r3, [pc, #392] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001282: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001284: 4a61 ldr r2, [pc, #388] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001286: f043 0301 orr.w r3, r3, #1
- 800128a: 6713 str r3, [r2, #112] ; 0x70
- 800128c: e00b b.n 80012a6 <HAL_RCC_OscConfig+0x376>
- 800128e: 4b5f ldr r3, [pc, #380] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001290: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001292: 4a5e ldr r2, [pc, #376] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001294: f023 0301 bic.w r3, r3, #1
- 8001298: 6713 str r3, [r2, #112] ; 0x70
- 800129a: 4b5c ldr r3, [pc, #368] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 800129c: 6f1b ldr r3, [r3, #112] ; 0x70
- 800129e: 4a5b ldr r2, [pc, #364] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80012a0: f023 0304 bic.w r3, r3, #4
- 80012a4: 6713 str r3, [r2, #112] ; 0x70
+ 80012d8: 687b ldr r3, [r7, #4]
+ 80012da: 689b ldr r3, [r3, #8]
+ 80012dc: 2b01 cmp r3, #1
+ 80012de: d106 bne.n 80012ee <HAL_RCC_OscConfig+0x31a>
+ 80012e0: 4b73 ldr r3, [pc, #460] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80012e2: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80012e4: 4a72 ldr r2, [pc, #456] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80012e6: f043 0301 orr.w r3, r3, #1
+ 80012ea: 6713 str r3, [r2, #112] ; 0x70
+ 80012ec: e02d b.n 800134a <HAL_RCC_OscConfig+0x376>
+ 80012ee: 687b ldr r3, [r7, #4]
+ 80012f0: 689b ldr r3, [r3, #8]
+ 80012f2: 2b00 cmp r3, #0
+ 80012f4: d10c bne.n 8001310 <HAL_RCC_OscConfig+0x33c>
+ 80012f6: 4b6e ldr r3, [pc, #440] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80012f8: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80012fa: 4a6d ldr r2, [pc, #436] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80012fc: f023 0301 bic.w r3, r3, #1
+ 8001300: 6713 str r3, [r2, #112] ; 0x70
+ 8001302: 4b6b ldr r3, [pc, #428] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001304: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001306: 4a6a ldr r2, [pc, #424] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001308: f023 0304 bic.w r3, r3, #4
+ 800130c: 6713 str r3, [r2, #112] ; 0x70
+ 800130e: e01c b.n 800134a <HAL_RCC_OscConfig+0x376>
+ 8001310: 687b ldr r3, [r7, #4]
+ 8001312: 689b ldr r3, [r3, #8]
+ 8001314: 2b05 cmp r3, #5
+ 8001316: d10c bne.n 8001332 <HAL_RCC_OscConfig+0x35e>
+ 8001318: 4b65 ldr r3, [pc, #404] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 800131a: 6f1b ldr r3, [r3, #112] ; 0x70
+ 800131c: 4a64 ldr r2, [pc, #400] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 800131e: f043 0304 orr.w r3, r3, #4
+ 8001322: 6713 str r3, [r2, #112] ; 0x70
+ 8001324: 4b62 ldr r3, [pc, #392] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001326: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001328: 4a61 ldr r2, [pc, #388] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 800132a: f043 0301 orr.w r3, r3, #1
+ 800132e: 6713 str r3, [r2, #112] ; 0x70
+ 8001330: e00b b.n 800134a <HAL_RCC_OscConfig+0x376>
+ 8001332: 4b5f ldr r3, [pc, #380] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001334: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001336: 4a5e ldr r2, [pc, #376] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001338: f023 0301 bic.w r3, r3, #1
+ 800133c: 6713 str r3, [r2, #112] ; 0x70
+ 800133e: 4b5c ldr r3, [pc, #368] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001340: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001342: 4a5b ldr r2, [pc, #364] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001344: f023 0304 bic.w r3, r3, #4
+ 8001348: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 80012a6: 687b ldr r3, [r7, #4]
- 80012a8: 689b ldr r3, [r3, #8]
- 80012aa: 2b00 cmp r3, #0
- 80012ac: d015 beq.n 80012da <HAL_RCC_OscConfig+0x3aa>
+ 800134a: 687b ldr r3, [r7, #4]
+ 800134c: 689b ldr r3, [r3, #8]
+ 800134e: 2b00 cmp r3, #0
+ 8001350: d015 beq.n 800137e <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80012ae: f7ff fb81 bl 80009b4 <HAL_GetTick>
- 80012b2: 6138 str r0, [r7, #16]
+ 8001352: f7ff fb81 bl 8000a58 <HAL_GetTick>
+ 8001356: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80012b4: e00a b.n 80012cc <HAL_RCC_OscConfig+0x39c>
+ 8001358: e00a b.n 8001370 <HAL_RCC_OscConfig+0x39c>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80012b6: f7ff fb7d bl 80009b4 <HAL_GetTick>
- 80012ba: 4602 mov r2, r0
- 80012bc: 693b ldr r3, [r7, #16]
- 80012be: 1ad3 subs r3, r2, r3
- 80012c0: f241 3288 movw r2, #5000 ; 0x1388
- 80012c4: 4293 cmp r3, r2
- 80012c6: d901 bls.n 80012cc <HAL_RCC_OscConfig+0x39c>
+ 800135a: f7ff fb7d bl 8000a58 <HAL_GetTick>
+ 800135e: 4602 mov r2, r0
+ 8001360: 693b ldr r3, [r7, #16]
+ 8001362: 1ad3 subs r3, r2, r3
+ 8001364: f241 3288 movw r2, #5000 ; 0x1388
+ 8001368: 4293 cmp r3, r2
+ 800136a: d901 bls.n 8001370 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
- 80012c8: 2303 movs r3, #3
- 80012ca: e09b b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 800136c: 2303 movs r3, #3
+ 800136e: e09b b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 80012cc: 4b4f ldr r3, [pc, #316] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80012ce: 6f1b ldr r3, [r3, #112] ; 0x70
- 80012d0: f003 0302 and.w r3, r3, #2
- 80012d4: 2b00 cmp r3, #0
- 80012d6: d0ee beq.n 80012b6 <HAL_RCC_OscConfig+0x386>
- 80012d8: e014 b.n 8001304 <HAL_RCC_OscConfig+0x3d4>
+ 8001370: 4b4f ldr r3, [pc, #316] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001372: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001374: f003 0302 and.w r3, r3, #2
+ 8001378: 2b00 cmp r3, #0
+ 800137a: d0ee beq.n 800135a <HAL_RCC_OscConfig+0x386>
+ 800137c: e014 b.n 80013a8 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80012da: f7ff fb6b bl 80009b4 <HAL_GetTick>
- 80012de: 6138 str r0, [r7, #16]
+ 800137e: f7ff fb6b bl 8000a58 <HAL_GetTick>
+ 8001382: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80012e0: e00a b.n 80012f8 <HAL_RCC_OscConfig+0x3c8>
+ 8001384: e00a b.n 800139c <HAL_RCC_OscConfig+0x3c8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80012e2: f7ff fb67 bl 80009b4 <HAL_GetTick>
- 80012e6: 4602 mov r2, r0
- 80012e8: 693b ldr r3, [r7, #16]
- 80012ea: 1ad3 subs r3, r2, r3
- 80012ec: f241 3288 movw r2, #5000 ; 0x1388
- 80012f0: 4293 cmp r3, r2
- 80012f2: d901 bls.n 80012f8 <HAL_RCC_OscConfig+0x3c8>
+ 8001386: f7ff fb67 bl 8000a58 <HAL_GetTick>
+ 800138a: 4602 mov r2, r0
+ 800138c: 693b ldr r3, [r7, #16]
+ 800138e: 1ad3 subs r3, r2, r3
+ 8001390: f241 3288 movw r2, #5000 ; 0x1388
+ 8001394: 4293 cmp r3, r2
+ 8001396: d901 bls.n 800139c <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
- 80012f4: 2303 movs r3, #3
- 80012f6: e085 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 8001398: 2303 movs r3, #3
+ 800139a: e085 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 80012f8: 4b44 ldr r3, [pc, #272] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80012fa: 6f1b ldr r3, [r3, #112] ; 0x70
- 80012fc: f003 0302 and.w r3, r3, #2
- 8001300: 2b00 cmp r3, #0
- 8001302: d1ee bne.n 80012e2 <HAL_RCC_OscConfig+0x3b2>
+ 800139c: 4b44 ldr r3, [pc, #272] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 800139e: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80013a0: f003 0302 and.w r3, r3, #2
+ 80013a4: 2b00 cmp r3, #0
+ 80013a6: d1ee bne.n 8001386 <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
- 8001304: 7dfb ldrb r3, [r7, #23]
- 8001306: 2b01 cmp r3, #1
- 8001308: d105 bne.n 8001316 <HAL_RCC_OscConfig+0x3e6>
+ 80013a8: 7dfb ldrb r3, [r7, #23]
+ 80013aa: 2b01 cmp r3, #1
+ 80013ac: d105 bne.n 80013ba <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
- 800130a: 4b40 ldr r3, [pc, #256] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 800130c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800130e: 4a3f ldr r2, [pc, #252] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001310: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8001314: 6413 str r3, [r2, #64] ; 0x40
+ 80013ae: 4b40 ldr r3, [pc, #256] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80013b0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80013b2: 4a3f ldr r2, [pc, #252] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80013b4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 80013b8: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8001316: 687b ldr r3, [r7, #4]
- 8001318: 699b ldr r3, [r3, #24]
- 800131a: 2b00 cmp r3, #0
- 800131c: d071 beq.n 8001402 <HAL_RCC_OscConfig+0x4d2>
+ 80013ba: 687b ldr r3, [r7, #4]
+ 80013bc: 699b ldr r3, [r3, #24]
+ 80013be: 2b00 cmp r3, #0
+ 80013c0: d071 beq.n 80014a6 <HAL_RCC_OscConfig+0x4d2>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 800131e: 4b3b ldr r3, [pc, #236] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001320: 689b ldr r3, [r3, #8]
- 8001322: f003 030c and.w r3, r3, #12
- 8001326: 2b08 cmp r3, #8
- 8001328: d069 beq.n 80013fe <HAL_RCC_OscConfig+0x4ce>
+ 80013c2: 4b3b ldr r3, [pc, #236] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80013c4: 689b ldr r3, [r3, #8]
+ 80013c6: f003 030c and.w r3, r3, #12
+ 80013ca: 2b08 cmp r3, #8
+ 80013cc: d069 beq.n 80014a2 <HAL_RCC_OscConfig+0x4ce>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 800132a: 687b ldr r3, [r7, #4]
- 800132c: 699b ldr r3, [r3, #24]
- 800132e: 2b02 cmp r3, #2
- 8001330: d14b bne.n 80013ca <HAL_RCC_OscConfig+0x49a>
+ 80013ce: 687b ldr r3, [r7, #4]
+ 80013d0: 699b ldr r3, [r3, #24]
+ 80013d2: 2b02 cmp r3, #2
+ 80013d4: d14b bne.n 800146e <HAL_RCC_OscConfig+0x49a>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 8001332: 4b36 ldr r3, [pc, #216] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001334: 681b ldr r3, [r3, #0]
- 8001336: 4a35 ldr r2, [pc, #212] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001338: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 800133c: 6013 str r3, [r2, #0]
+ 80013d6: 4b36 ldr r3, [pc, #216] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80013d8: 681b ldr r3, [r3, #0]
+ 80013da: 4a35 ldr r2, [pc, #212] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80013dc: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 80013e0: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 800133e: f7ff fb39 bl 80009b4 <HAL_GetTick>
- 8001342: 6138 str r0, [r7, #16]
+ 80013e2: f7ff fb39 bl 8000a58 <HAL_GetTick>
+ 80013e6: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001344: e008 b.n 8001358 <HAL_RCC_OscConfig+0x428>
+ 80013e8: e008 b.n 80013fc <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001346: f7ff fb35 bl 80009b4 <HAL_GetTick>
- 800134a: 4602 mov r2, r0
- 800134c: 693b ldr r3, [r7, #16]
- 800134e: 1ad3 subs r3, r2, r3
- 8001350: 2b02 cmp r3, #2
- 8001352: d901 bls.n 8001358 <HAL_RCC_OscConfig+0x428>
+ 80013ea: f7ff fb35 bl 8000a58 <HAL_GetTick>
+ 80013ee: 4602 mov r2, r0
+ 80013f0: 693b ldr r3, [r7, #16]
+ 80013f2: 1ad3 subs r3, r2, r3
+ 80013f4: 2b02 cmp r3, #2
+ 80013f6: d901 bls.n 80013fc <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
- 8001354: 2303 movs r3, #3
- 8001356: e055 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 80013f8: 2303 movs r3, #3
+ 80013fa: e055 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001358: 4b2c ldr r3, [pc, #176] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 800135a: 681b ldr r3, [r3, #0]
- 800135c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8001360: 2b00 cmp r3, #0
- 8001362: d1f0 bne.n 8001346 <HAL_RCC_OscConfig+0x416>
+ 80013fc: 4b2c ldr r3, [pc, #176] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 80013fe: 681b ldr r3, [r3, #0]
+ 8001400: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8001404: 2b00 cmp r3, #0
+ 8001406: d1f0 bne.n 80013ea <HAL_RCC_OscConfig+0x416>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined (RCC_PLLCFGR_PLLR)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8001364: 687b ldr r3, [r7, #4]
- 8001366: 69da ldr r2, [r3, #28]
- 8001368: 687b ldr r3, [r7, #4]
- 800136a: 6a1b ldr r3, [r3, #32]
- 800136c: 431a orrs r2, r3
- 800136e: 687b ldr r3, [r7, #4]
- 8001370: 6a5b ldr r3, [r3, #36] ; 0x24
- 8001372: 019b lsls r3, r3, #6
- 8001374: 431a orrs r2, r3
- 8001376: 687b ldr r3, [r7, #4]
- 8001378: 6a9b ldr r3, [r3, #40] ; 0x28
- 800137a: 085b lsrs r3, r3, #1
- 800137c: 3b01 subs r3, #1
- 800137e: 041b lsls r3, r3, #16
- 8001380: 431a orrs r2, r3
- 8001382: 687b ldr r3, [r7, #4]
- 8001384: 6adb ldr r3, [r3, #44] ; 0x2c
- 8001386: 061b lsls r3, r3, #24
- 8001388: 431a orrs r2, r3
- 800138a: 687b ldr r3, [r7, #4]
- 800138c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800138e: 071b lsls r3, r3, #28
- 8001390: 491e ldr r1, [pc, #120] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001392: 4313 orrs r3, r2
- 8001394: 604b str r3, [r1, #4]
+ 8001408: 687b ldr r3, [r7, #4]
+ 800140a: 69da ldr r2, [r3, #28]
+ 800140c: 687b ldr r3, [r7, #4]
+ 800140e: 6a1b ldr r3, [r3, #32]
+ 8001410: 431a orrs r2, r3
+ 8001412: 687b ldr r3, [r7, #4]
+ 8001414: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001416: 019b lsls r3, r3, #6
+ 8001418: 431a orrs r2, r3
+ 800141a: 687b ldr r3, [r7, #4]
+ 800141c: 6a9b ldr r3, [r3, #40] ; 0x28
+ 800141e: 085b lsrs r3, r3, #1
+ 8001420: 3b01 subs r3, #1
+ 8001422: 041b lsls r3, r3, #16
+ 8001424: 431a orrs r2, r3
+ 8001426: 687b ldr r3, [r7, #4]
+ 8001428: 6adb ldr r3, [r3, #44] ; 0x2c
+ 800142a: 061b lsls r3, r3, #24
+ 800142c: 431a orrs r2, r3
+ 800142e: 687b ldr r3, [r7, #4]
+ 8001430: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001432: 071b lsls r3, r3, #28
+ 8001434: 491e ldr r1, [pc, #120] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001436: 4313 orrs r3, r2
+ 8001438: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- 8001396: 4b1d ldr r3, [pc, #116] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 8001398: 681b ldr r3, [r3, #0]
- 800139a: 4a1c ldr r2, [pc, #112] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 800139c: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 80013a0: 6013 str r3, [r2, #0]
+ 800143a: 4b1d ldr r3, [pc, #116] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 800143c: 681b ldr r3, [r3, #0]
+ 800143e: 4a1c ldr r2, [pc, #112] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001440: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
+ 8001444: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80013a2: f7ff fb07 bl 80009b4 <HAL_GetTick>
- 80013a6: 6138 str r0, [r7, #16]
+ 8001446: f7ff fb07 bl 8000a58 <HAL_GetTick>
+ 800144a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80013a8: e008 b.n 80013bc <HAL_RCC_OscConfig+0x48c>
+ 800144c: e008 b.n 8001460 <HAL_RCC_OscConfig+0x48c>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80013aa: f7ff fb03 bl 80009b4 <HAL_GetTick>
- 80013ae: 4602 mov r2, r0
- 80013b0: 693b ldr r3, [r7, #16]
- 80013b2: 1ad3 subs r3, r2, r3
- 80013b4: 2b02 cmp r3, #2
- 80013b6: d901 bls.n 80013bc <HAL_RCC_OscConfig+0x48c>
+ 800144e: f7ff fb03 bl 8000a58 <HAL_GetTick>
+ 8001452: 4602 mov r2, r0
+ 8001454: 693b ldr r3, [r7, #16]
+ 8001456: 1ad3 subs r3, r2, r3
+ 8001458: 2b02 cmp r3, #2
+ 800145a: d901 bls.n 8001460 <HAL_RCC_OscConfig+0x48c>
{
return HAL_TIMEOUT;
- 80013b8: 2303 movs r3, #3
- 80013ba: e023 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 800145c: 2303 movs r3, #3
+ 800145e: e023 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80013bc: 4b13 ldr r3, [pc, #76] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80013be: 681b ldr r3, [r3, #0]
- 80013c0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80013c4: 2b00 cmp r3, #0
- 80013c6: d0f0 beq.n 80013aa <HAL_RCC_OscConfig+0x47a>
- 80013c8: e01b b.n 8001402 <HAL_RCC_OscConfig+0x4d2>
+ 8001460: 4b13 ldr r3, [pc, #76] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001462: 681b ldr r3, [r3, #0]
+ 8001464: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8001468: 2b00 cmp r3, #0
+ 800146a: d0f0 beq.n 800144e <HAL_RCC_OscConfig+0x47a>
+ 800146c: e01b b.n 80014a6 <HAL_RCC_OscConfig+0x4d2>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 80013ca: 4b10 ldr r3, [pc, #64] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80013cc: 681b ldr r3, [r3, #0]
- 80013ce: 4a0f ldr r2, [pc, #60] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80013d0: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80013d4: 6013 str r3, [r2, #0]
+ 800146e: 4b10 ldr r3, [pc, #64] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001470: 681b ldr r3, [r3, #0]
+ 8001472: 4a0f ldr r2, [pc, #60] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001474: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8001478: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80013d6: f7ff faed bl 80009b4 <HAL_GetTick>
- 80013da: 6138 str r0, [r7, #16]
+ 800147a: f7ff faed bl 8000a58 <HAL_GetTick>
+ 800147e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80013dc: e008 b.n 80013f0 <HAL_RCC_OscConfig+0x4c0>
+ 8001480: e008 b.n 8001494 <HAL_RCC_OscConfig+0x4c0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80013de: f7ff fae9 bl 80009b4 <HAL_GetTick>
- 80013e2: 4602 mov r2, r0
- 80013e4: 693b ldr r3, [r7, #16]
- 80013e6: 1ad3 subs r3, r2, r3
- 80013e8: 2b02 cmp r3, #2
- 80013ea: d901 bls.n 80013f0 <HAL_RCC_OscConfig+0x4c0>
+ 8001482: f7ff fae9 bl 8000a58 <HAL_GetTick>
+ 8001486: 4602 mov r2, r0
+ 8001488: 693b ldr r3, [r7, #16]
+ 800148a: 1ad3 subs r3, r2, r3
+ 800148c: 2b02 cmp r3, #2
+ 800148e: d901 bls.n 8001494 <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
- 80013ec: 2303 movs r3, #3
- 80013ee: e009 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 8001490: 2303 movs r3, #3
+ 8001492: e009 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 80013f0: 4b06 ldr r3, [pc, #24] ; (800140c <HAL_RCC_OscConfig+0x4dc>)
- 80013f2: 681b ldr r3, [r3, #0]
- 80013f4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80013f8: 2b00 cmp r3, #0
- 80013fa: d1f0 bne.n 80013de <HAL_RCC_OscConfig+0x4ae>
- 80013fc: e001 b.n 8001402 <HAL_RCC_OscConfig+0x4d2>
+ 8001494: 4b06 ldr r3, [pc, #24] ; (80014b0 <HAL_RCC_OscConfig+0x4dc>)
+ 8001496: 681b ldr r3, [r3, #0]
+ 8001498: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 800149c: 2b00 cmp r3, #0
+ 800149e: d1f0 bne.n 8001482 <HAL_RCC_OscConfig+0x4ae>
+ 80014a0: e001 b.n 80014a6 <HAL_RCC_OscConfig+0x4d2>
}
}
}
else
{
return HAL_ERROR;
- 80013fe: 2301 movs r3, #1
- 8001400: e000 b.n 8001404 <HAL_RCC_OscConfig+0x4d4>
+ 80014a2: 2301 movs r3, #1
+ 80014a4: e000 b.n 80014a8 <HAL_RCC_OscConfig+0x4d4>
}
}
return HAL_OK;
- 8001402: 2300 movs r3, #0
+ 80014a6: 2300 movs r3, #0
}
- 8001404: 4618 mov r0, r3
- 8001406: 3718 adds r7, #24
- 8001408: 46bd mov sp, r7
- 800140a: bd80 pop {r7, pc}
- 800140c: 40023800 .word 0x40023800
- 8001410: 40007000 .word 0x40007000
-
-08001414 <HAL_RCC_ClockConfig>:
+ 80014a8: 4618 mov r0, r3
+ 80014aa: 3718 adds r7, #24
+ 80014ac: 46bd mov sp, r7
+ 80014ae: bd80 pop {r7, pc}
+ 80014b0: 40023800 .word 0x40023800
+ 80014b4: 40007000 .word 0x40007000
+
+080014b8 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- 8001414: b580 push {r7, lr}
- 8001416: b084 sub sp, #16
- 8001418: af00 add r7, sp, #0
- 800141a: 6078 str r0, [r7, #4]
- 800141c: 6039 str r1, [r7, #0]
+ 80014b8: b580 push {r7, lr}
+ 80014ba: b084 sub sp, #16
+ 80014bc: af00 add r7, sp, #0
+ 80014be: 6078 str r0, [r7, #4]
+ 80014c0: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
- 800141e: 2300 movs r3, #0
- 8001420: 60fb str r3, [r7, #12]
+ 80014c2: 2300 movs r3, #0
+ 80014c4: 60fb str r3, [r7, #12]
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
- 8001422: 687b ldr r3, [r7, #4]
- 8001424: 2b00 cmp r3, #0
- 8001426: d101 bne.n 800142c <HAL_RCC_ClockConfig+0x18>
+ 80014c6: 687b ldr r3, [r7, #4]
+ 80014c8: 2b00 cmp r3, #0
+ 80014ca: d101 bne.n 80014d0 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
- 8001428: 2301 movs r3, #1
- 800142a: e0ce b.n 80015ca <HAL_RCC_ClockConfig+0x1b6>
+ 80014cc: 2301 movs r3, #1
+ 80014ce: e0ce b.n 800166e <HAL_RCC_ClockConfig+0x1b6>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
- 800142c: 4b69 ldr r3, [pc, #420] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800142e: 681b ldr r3, [r3, #0]
- 8001430: f003 030f and.w r3, r3, #15
- 8001434: 683a ldr r2, [r7, #0]
- 8001436: 429a cmp r2, r3
- 8001438: d910 bls.n 800145c <HAL_RCC_ClockConfig+0x48>
+ 80014d0: 4b69 ldr r3, [pc, #420] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80014d2: 681b ldr r3, [r3, #0]
+ 80014d4: f003 030f and.w r3, r3, #15
+ 80014d8: 683a ldr r2, [r7, #0]
+ 80014da: 429a cmp r2, r3
+ 80014dc: d910 bls.n 8001500 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 800143a: 4b66 ldr r3, [pc, #408] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800143c: 681b ldr r3, [r3, #0]
- 800143e: f023 020f bic.w r2, r3, #15
- 8001442: 4964 ldr r1, [pc, #400] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001444: 683b ldr r3, [r7, #0]
- 8001446: 4313 orrs r3, r2
- 8001448: 600b str r3, [r1, #0]
+ 80014de: 4b66 ldr r3, [pc, #408] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80014e0: 681b ldr r3, [r3, #0]
+ 80014e2: f023 020f bic.w r2, r3, #15
+ 80014e6: 4964 ldr r1, [pc, #400] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80014e8: 683b ldr r3, [r7, #0]
+ 80014ea: 4313 orrs r3, r2
+ 80014ec: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800144a: 4b62 ldr r3, [pc, #392] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800144c: 681b ldr r3, [r3, #0]
- 800144e: f003 030f and.w r3, r3, #15
- 8001452: 683a ldr r2, [r7, #0]
- 8001454: 429a cmp r2, r3
- 8001456: d001 beq.n 800145c <HAL_RCC_ClockConfig+0x48>
+ 80014ee: 4b62 ldr r3, [pc, #392] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80014f0: 681b ldr r3, [r3, #0]
+ 80014f2: f003 030f and.w r3, r3, #15
+ 80014f6: 683a ldr r2, [r7, #0]
+ 80014f8: 429a cmp r2, r3
+ 80014fa: d001 beq.n 8001500 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
- 8001458: 2301 movs r3, #1
- 800145a: e0b6 b.n 80015ca <HAL_RCC_ClockConfig+0x1b6>
+ 80014fc: 2301 movs r3, #1
+ 80014fe: e0b6 b.n 800166e <HAL_RCC_ClockConfig+0x1b6>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 800145c: 687b ldr r3, [r7, #4]
- 800145e: 681b ldr r3, [r3, #0]
- 8001460: f003 0302 and.w r3, r3, #2
- 8001464: 2b00 cmp r3, #0
- 8001466: d020 beq.n 80014aa <HAL_RCC_ClockConfig+0x96>
+ 8001500: 687b ldr r3, [r7, #4]
+ 8001502: 681b ldr r3, [r3, #0]
+ 8001504: f003 0302 and.w r3, r3, #2
+ 8001508: 2b00 cmp r3, #0
+ 800150a: d020 beq.n 800154e <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001468: 687b ldr r3, [r7, #4]
- 800146a: 681b ldr r3, [r3, #0]
- 800146c: f003 0304 and.w r3, r3, #4
- 8001470: 2b00 cmp r3, #0
- 8001472: d005 beq.n 8001480 <HAL_RCC_ClockConfig+0x6c>
+ 800150c: 687b ldr r3, [r7, #4]
+ 800150e: 681b ldr r3, [r3, #0]
+ 8001510: f003 0304 and.w r3, r3, #4
+ 8001514: 2b00 cmp r3, #0
+ 8001516: d005 beq.n 8001524 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 8001474: 4b58 ldr r3, [pc, #352] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001476: 689b ldr r3, [r3, #8]
- 8001478: 4a57 ldr r2, [pc, #348] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 800147a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 800147e: 6093 str r3, [r2, #8]
+ 8001518: 4b58 ldr r3, [pc, #352] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800151a: 689b ldr r3, [r3, #8]
+ 800151c: 4a57 ldr r2, [pc, #348] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800151e: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
+ 8001522: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8001480: 687b ldr r3, [r7, #4]
- 8001482: 681b ldr r3, [r3, #0]
- 8001484: f003 0308 and.w r3, r3, #8
- 8001488: 2b00 cmp r3, #0
- 800148a: d005 beq.n 8001498 <HAL_RCC_ClockConfig+0x84>
+ 8001524: 687b ldr r3, [r7, #4]
+ 8001526: 681b ldr r3, [r3, #0]
+ 8001528: f003 0308 and.w r3, r3, #8
+ 800152c: 2b00 cmp r3, #0
+ 800152e: d005 beq.n 800153c <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 800148c: 4b52 ldr r3, [pc, #328] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 800148e: 689b ldr r3, [r3, #8]
- 8001490: 4a51 ldr r2, [pc, #324] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001492: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 8001496: 6093 str r3, [r2, #8]
+ 8001530: 4b52 ldr r3, [pc, #328] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001532: 689b ldr r3, [r3, #8]
+ 8001534: 4a51 ldr r2, [pc, #324] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001536: f443 4360 orr.w r3, r3, #57344 ; 0xe000
+ 800153a: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8001498: 4b4f ldr r3, [pc, #316] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 800149a: 689b ldr r3, [r3, #8]
- 800149c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 80014a0: 687b ldr r3, [r7, #4]
- 80014a2: 689b ldr r3, [r3, #8]
- 80014a4: 494c ldr r1, [pc, #304] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80014a6: 4313 orrs r3, r2
- 80014a8: 608b str r3, [r1, #8]
+ 800153c: 4b4f ldr r3, [pc, #316] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800153e: 689b ldr r3, [r3, #8]
+ 8001540: f023 02f0 bic.w r2, r3, #240 ; 0xf0
+ 8001544: 687b ldr r3, [r7, #4]
+ 8001546: 689b ldr r3, [r3, #8]
+ 8001548: 494c ldr r1, [pc, #304] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800154a: 4313 orrs r3, r2
+ 800154c: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 80014aa: 687b ldr r3, [r7, #4]
- 80014ac: 681b ldr r3, [r3, #0]
- 80014ae: f003 0301 and.w r3, r3, #1
- 80014b2: 2b00 cmp r3, #0
- 80014b4: d040 beq.n 8001538 <HAL_RCC_ClockConfig+0x124>
+ 800154e: 687b ldr r3, [r7, #4]
+ 8001550: 681b ldr r3, [r3, #0]
+ 8001552: f003 0301 and.w r3, r3, #1
+ 8001556: 2b00 cmp r3, #0
+ 8001558: d040 beq.n 80015dc <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 80014b6: 687b ldr r3, [r7, #4]
- 80014b8: 685b ldr r3, [r3, #4]
- 80014ba: 2b01 cmp r3, #1
- 80014bc: d107 bne.n 80014ce <HAL_RCC_ClockConfig+0xba>
+ 800155a: 687b ldr r3, [r7, #4]
+ 800155c: 685b ldr r3, [r3, #4]
+ 800155e: 2b01 cmp r3, #1
+ 8001560: d107 bne.n 8001572 <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80014be: 4b46 ldr r3, [pc, #280] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80014c0: 681b ldr r3, [r3, #0]
- 80014c2: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80014c6: 2b00 cmp r3, #0
- 80014c8: d115 bne.n 80014f6 <HAL_RCC_ClockConfig+0xe2>
+ 8001562: 4b46 ldr r3, [pc, #280] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001564: 681b ldr r3, [r3, #0]
+ 8001566: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 800156a: 2b00 cmp r3, #0
+ 800156c: d115 bne.n 800159a <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 80014ca: 2301 movs r3, #1
- 80014cc: e07d b.n 80015ca <HAL_RCC_ClockConfig+0x1b6>
+ 800156e: 2301 movs r3, #1
+ 8001570: e07d b.n 800166e <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 80014ce: 687b ldr r3, [r7, #4]
- 80014d0: 685b ldr r3, [r3, #4]
- 80014d2: 2b02 cmp r3, #2
- 80014d4: d107 bne.n 80014e6 <HAL_RCC_ClockConfig+0xd2>
+ 8001572: 687b ldr r3, [r7, #4]
+ 8001574: 685b ldr r3, [r3, #4]
+ 8001576: 2b02 cmp r3, #2
+ 8001578: d107 bne.n 800158a <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80014d6: 4b40 ldr r3, [pc, #256] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80014d8: 681b ldr r3, [r3, #0]
- 80014da: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 80014de: 2b00 cmp r3, #0
- 80014e0: d109 bne.n 80014f6 <HAL_RCC_ClockConfig+0xe2>
+ 800157a: 4b40 ldr r3, [pc, #256] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800157c: 681b ldr r3, [r3, #0]
+ 800157e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8001582: 2b00 cmp r3, #0
+ 8001584: d109 bne.n 800159a <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 80014e2: 2301 movs r3, #1
- 80014e4: e071 b.n 80015ca <HAL_RCC_ClockConfig+0x1b6>
+ 8001586: 2301 movs r3, #1
+ 8001588: e071 b.n 800166e <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 80014e6: 4b3c ldr r3, [pc, #240] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80014e8: 681b ldr r3, [r3, #0]
- 80014ea: f003 0302 and.w r3, r3, #2
- 80014ee: 2b00 cmp r3, #0
- 80014f0: d101 bne.n 80014f6 <HAL_RCC_ClockConfig+0xe2>
+ 800158a: 4b3c ldr r3, [pc, #240] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800158c: 681b ldr r3, [r3, #0]
+ 800158e: f003 0302 and.w r3, r3, #2
+ 8001592: 2b00 cmp r3, #0
+ 8001594: d101 bne.n 800159a <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 80014f2: 2301 movs r3, #1
- 80014f4: e069 b.n 80015ca <HAL_RCC_ClockConfig+0x1b6>
+ 8001596: 2301 movs r3, #1
+ 8001598: e069 b.n 800166e <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 80014f6: 4b38 ldr r3, [pc, #224] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80014f8: 689b ldr r3, [r3, #8]
- 80014fa: f023 0203 bic.w r2, r3, #3
- 80014fe: 687b ldr r3, [r7, #4]
- 8001500: 685b ldr r3, [r3, #4]
- 8001502: 4935 ldr r1, [pc, #212] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001504: 4313 orrs r3, r2
- 8001506: 608b str r3, [r1, #8]
+ 800159a: 4b38 ldr r3, [pc, #224] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800159c: 689b ldr r3, [r3, #8]
+ 800159e: f023 0203 bic.w r2, r3, #3
+ 80015a2: 687b ldr r3, [r7, #4]
+ 80015a4: 685b ldr r3, [r3, #4]
+ 80015a6: 4935 ldr r1, [pc, #212] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 80015a8: 4313 orrs r3, r2
+ 80015aa: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001508: f7ff fa54 bl 80009b4 <HAL_GetTick>
- 800150c: 60f8 str r0, [r7, #12]
+ 80015ac: f7ff fa54 bl 8000a58 <HAL_GetTick>
+ 80015b0: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 800150e: e00a b.n 8001526 <HAL_RCC_ClockConfig+0x112>
+ 80015b2: e00a b.n 80015ca <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8001510: f7ff fa50 bl 80009b4 <HAL_GetTick>
- 8001514: 4602 mov r2, r0
- 8001516: 68fb ldr r3, [r7, #12]
- 8001518: 1ad3 subs r3, r2, r3
- 800151a: f241 3288 movw r2, #5000 ; 0x1388
- 800151e: 4293 cmp r3, r2
- 8001520: d901 bls.n 8001526 <HAL_RCC_ClockConfig+0x112>
+ 80015b4: f7ff fa50 bl 8000a58 <HAL_GetTick>
+ 80015b8: 4602 mov r2, r0
+ 80015ba: 68fb ldr r3, [r7, #12]
+ 80015bc: 1ad3 subs r3, r2, r3
+ 80015be: f241 3288 movw r2, #5000 ; 0x1388
+ 80015c2: 4293 cmp r3, r2
+ 80015c4: d901 bls.n 80015ca <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
- 8001522: 2303 movs r3, #3
- 8001524: e051 b.n 80015ca <HAL_RCC_ClockConfig+0x1b6>
+ 80015c6: 2303 movs r3, #3
+ 80015c8: e051 b.n 800166e <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8001526: 4b2c ldr r3, [pc, #176] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001528: 689b ldr r3, [r3, #8]
- 800152a: f003 020c and.w r2, r3, #12
- 800152e: 687b ldr r3, [r7, #4]
- 8001530: 685b ldr r3, [r3, #4]
- 8001532: 009b lsls r3, r3, #2
- 8001534: 429a cmp r2, r3
- 8001536: d1eb bne.n 8001510 <HAL_RCC_ClockConfig+0xfc>
+ 80015ca: 4b2c ldr r3, [pc, #176] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 80015cc: 689b ldr r3, [r3, #8]
+ 80015ce: f003 020c and.w r2, r3, #12
+ 80015d2: 687b ldr r3, [r7, #4]
+ 80015d4: 685b ldr r3, [r3, #4]
+ 80015d6: 009b lsls r3, r3, #2
+ 80015d8: 429a cmp r2, r3
+ 80015da: d1eb bne.n 80015b4 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8001538: 4b26 ldr r3, [pc, #152] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 800153a: 681b ldr r3, [r3, #0]
- 800153c: f003 030f and.w r3, r3, #15
- 8001540: 683a ldr r2, [r7, #0]
- 8001542: 429a cmp r2, r3
- 8001544: d210 bcs.n 8001568 <HAL_RCC_ClockConfig+0x154>
+ 80015dc: 4b26 ldr r3, [pc, #152] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80015de: 681b ldr r3, [r3, #0]
+ 80015e0: f003 030f and.w r3, r3, #15
+ 80015e4: 683a ldr r2, [r7, #0]
+ 80015e6: 429a cmp r2, r3
+ 80015e8: d210 bcs.n 800160c <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 8001546: 4b23 ldr r3, [pc, #140] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001548: 681b ldr r3, [r3, #0]
- 800154a: f023 020f bic.w r2, r3, #15
- 800154e: 4921 ldr r1, [pc, #132] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001550: 683b ldr r3, [r7, #0]
- 8001552: 4313 orrs r3, r2
- 8001554: 600b str r3, [r1, #0]
+ 80015ea: 4b23 ldr r3, [pc, #140] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80015ec: 681b ldr r3, [r3, #0]
+ 80015ee: f023 020f bic.w r2, r3, #15
+ 80015f2: 4921 ldr r1, [pc, #132] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80015f4: 683b ldr r3, [r7, #0]
+ 80015f6: 4313 orrs r3, r2
+ 80015f8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8001556: 4b1f ldr r3, [pc, #124] ; (80015d4 <HAL_RCC_ClockConfig+0x1c0>)
- 8001558: 681b ldr r3, [r3, #0]
- 800155a: f003 030f and.w r3, r3, #15
- 800155e: 683a ldr r2, [r7, #0]
- 8001560: 429a cmp r2, r3
- 8001562: d001 beq.n 8001568 <HAL_RCC_ClockConfig+0x154>
+ 80015fa: 4b1f ldr r3, [pc, #124] ; (8001678 <HAL_RCC_ClockConfig+0x1c0>)
+ 80015fc: 681b ldr r3, [r3, #0]
+ 80015fe: f003 030f and.w r3, r3, #15
+ 8001602: 683a ldr r2, [r7, #0]
+ 8001604: 429a cmp r2, r3
+ 8001606: d001 beq.n 800160c <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
- 8001564: 2301 movs r3, #1
- 8001566: e030 b.n 80015ca <HAL_RCC_ClockConfig+0x1b6>
+ 8001608: 2301 movs r3, #1
+ 800160a: e030 b.n 800166e <HAL_RCC_ClockConfig+0x1b6>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001568: 687b ldr r3, [r7, #4]
- 800156a: 681b ldr r3, [r3, #0]
- 800156c: f003 0304 and.w r3, r3, #4
- 8001570: 2b00 cmp r3, #0
- 8001572: d008 beq.n 8001586 <HAL_RCC_ClockConfig+0x172>
+ 800160c: 687b ldr r3, [r7, #4]
+ 800160e: 681b ldr r3, [r3, #0]
+ 8001610: f003 0304 and.w r3, r3, #4
+ 8001614: 2b00 cmp r3, #0
+ 8001616: d008 beq.n 800162a <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8001574: 4b18 ldr r3, [pc, #96] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001576: 689b ldr r3, [r3, #8]
- 8001578: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 800157c: 687b ldr r3, [r7, #4]
- 800157e: 68db ldr r3, [r3, #12]
- 8001580: 4915 ldr r1, [pc, #84] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001582: 4313 orrs r3, r2
- 8001584: 608b str r3, [r1, #8]
+ 8001618: 4b18 ldr r3, [pc, #96] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 800161a: 689b ldr r3, [r3, #8]
+ 800161c: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
+ 8001620: 687b ldr r3, [r7, #4]
+ 8001622: 68db ldr r3, [r3, #12]
+ 8001624: 4915 ldr r1, [pc, #84] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001626: 4313 orrs r3, r2
+ 8001628: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8001586: 687b ldr r3, [r7, #4]
- 8001588: 681b ldr r3, [r3, #0]
- 800158a: f003 0308 and.w r3, r3, #8
- 800158e: 2b00 cmp r3, #0
- 8001590: d009 beq.n 80015a6 <HAL_RCC_ClockConfig+0x192>
+ 800162a: 687b ldr r3, [r7, #4]
+ 800162c: 681b ldr r3, [r3, #0]
+ 800162e: f003 0308 and.w r3, r3, #8
+ 8001632: 2b00 cmp r3, #0
+ 8001634: d009 beq.n 800164a <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 8001592: 4b11 ldr r3, [pc, #68] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 8001594: 689b ldr r3, [r3, #8]
- 8001596: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 800159a: 687b ldr r3, [r7, #4]
- 800159c: 691b ldr r3, [r3, #16]
- 800159e: 00db lsls r3, r3, #3
- 80015a0: 490d ldr r1, [pc, #52] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80015a2: 4313 orrs r3, r2
- 80015a4: 608b str r3, [r1, #8]
+ 8001636: 4b11 ldr r3, [pc, #68] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001638: 689b ldr r3, [r3, #8]
+ 800163a: f423 4260 bic.w r2, r3, #57344 ; 0xe000
+ 800163e: 687b ldr r3, [r7, #4]
+ 8001640: 691b ldr r3, [r3, #16]
+ 8001642: 00db lsls r3, r3, #3
+ 8001644: 490d ldr r1, [pc, #52] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001646: 4313 orrs r3, r2
+ 8001648: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 80015a6: f000 f81d bl 80015e4 <HAL_RCC_GetSysClockFreq>
- 80015aa: 4601 mov r1, r0
- 80015ac: 4b0a ldr r3, [pc, #40] ; (80015d8 <HAL_RCC_ClockConfig+0x1c4>)
- 80015ae: 689b ldr r3, [r3, #8]
- 80015b0: 091b lsrs r3, r3, #4
- 80015b2: f003 030f and.w r3, r3, #15
- 80015b6: 4a09 ldr r2, [pc, #36] ; (80015dc <HAL_RCC_ClockConfig+0x1c8>)
- 80015b8: 5cd3 ldrb r3, [r2, r3]
- 80015ba: fa21 f303 lsr.w r3, r1, r3
- 80015be: 4a08 ldr r2, [pc, #32] ; (80015e0 <HAL_RCC_ClockConfig+0x1cc>)
- 80015c0: 6013 str r3, [r2, #0]
+ 800164a: f000 f81d bl 8001688 <HAL_RCC_GetSysClockFreq>
+ 800164e: 4601 mov r1, r0
+ 8001650: 4b0a ldr r3, [pc, #40] ; (800167c <HAL_RCC_ClockConfig+0x1c4>)
+ 8001652: 689b ldr r3, [r3, #8]
+ 8001654: 091b lsrs r3, r3, #4
+ 8001656: f003 030f and.w r3, r3, #15
+ 800165a: 4a09 ldr r2, [pc, #36] ; (8001680 <HAL_RCC_ClockConfig+0x1c8>)
+ 800165c: 5cd3 ldrb r3, [r2, r3]
+ 800165e: fa21 f303 lsr.w r3, r1, r3
+ 8001662: 4a08 ldr r2, [pc, #32] ; (8001684 <HAL_RCC_ClockConfig+0x1cc>)
+ 8001664: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
- 80015c2: 2000 movs r0, #0
- 80015c4: f7ff f9b2 bl 800092c <HAL_InitTick>
+ 8001666: 2000 movs r0, #0
+ 8001668: f7ff f9b2 bl 80009d0 <HAL_InitTick>
return HAL_OK;
- 80015c8: 2300 movs r3, #0
+ 800166c: 2300 movs r3, #0
}
- 80015ca: 4618 mov r0, r3
- 80015cc: 3710 adds r7, #16
- 80015ce: 46bd mov sp, r7
- 80015d0: bd80 pop {r7, pc}
- 80015d2: bf00 nop
- 80015d4: 40023c00 .word 0x40023c00
- 80015d8: 40023800 .word 0x40023800
- 80015dc: 080029b8 .word 0x080029b8
- 80015e0: 20000000 .word 0x20000000
-
-080015e4 <HAL_RCC_GetSysClockFreq>:
+ 800166e: 4618 mov r0, r3
+ 8001670: 3710 adds r7, #16
+ 8001672: 46bd mov sp, r7
+ 8001674: bd80 pop {r7, pc}
+ 8001676: bf00 nop
+ 8001678: 40023c00 .word 0x40023c00
+ 800167c: 40023800 .word 0x40023800
+ 8001680: 08002a5c .word 0x08002a5c
+ 8001684: 20000000 .word 0x20000000
+
+08001688 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
- 80015e4: b5f0 push {r4, r5, r6, r7, lr}
- 80015e6: b085 sub sp, #20
- 80015e8: af00 add r7, sp, #0
+ 8001688: b5f0 push {r4, r5, r6, r7, lr}
+ 800168a: b085 sub sp, #20
+ 800168c: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 80015ea: 2300 movs r3, #0
- 80015ec: 607b str r3, [r7, #4]
- 80015ee: 2300 movs r3, #0
- 80015f0: 60fb str r3, [r7, #12]
- 80015f2: 2300 movs r3, #0
- 80015f4: 603b str r3, [r7, #0]
+ 800168e: 2300 movs r3, #0
+ 8001690: 607b str r3, [r7, #4]
+ 8001692: 2300 movs r3, #0
+ 8001694: 60fb str r3, [r7, #12]
+ 8001696: 2300 movs r3, #0
+ 8001698: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0;
- 80015f6: 2300 movs r3, #0
- 80015f8: 60bb str r3, [r7, #8]
+ 800169a: 2300 movs r3, #0
+ 800169c: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
- 80015fa: 4b50 ldr r3, [pc, #320] ; (800173c <HAL_RCC_GetSysClockFreq+0x158>)
- 80015fc: 689b ldr r3, [r3, #8]
- 80015fe: f003 030c and.w r3, r3, #12
- 8001602: 2b04 cmp r3, #4
- 8001604: d007 beq.n 8001616 <HAL_RCC_GetSysClockFreq+0x32>
- 8001606: 2b08 cmp r3, #8
- 8001608: d008 beq.n 800161c <HAL_RCC_GetSysClockFreq+0x38>
- 800160a: 2b00 cmp r3, #0
- 800160c: f040 808d bne.w 800172a <HAL_RCC_GetSysClockFreq+0x146>
+ 800169e: 4b50 ldr r3, [pc, #320] ; (80017e0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80016a0: 689b ldr r3, [r3, #8]
+ 80016a2: f003 030c and.w r3, r3, #12
+ 80016a6: 2b04 cmp r3, #4
+ 80016a8: d007 beq.n 80016ba <HAL_RCC_GetSysClockFreq+0x32>
+ 80016aa: 2b08 cmp r3, #8
+ 80016ac: d008 beq.n 80016c0 <HAL_RCC_GetSysClockFreq+0x38>
+ 80016ae: 2b00 cmp r3, #0
+ 80016b0: f040 808d bne.w 80017ce <HAL_RCC_GetSysClockFreq+0x146>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
- 8001610: 4b4b ldr r3, [pc, #300] ; (8001740 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8001612: 60bb str r3, [r7, #8]
+ 80016b4: 4b4b ldr r3, [pc, #300] ; (80017e4 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 80016b6: 60bb str r3, [r7, #8]
break;
- 8001614: e08c b.n 8001730 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80016b8: e08c b.n 80017d4 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
- 8001616: 4b4b ldr r3, [pc, #300] ; (8001744 <HAL_RCC_GetSysClockFreq+0x160>)
- 8001618: 60bb str r3, [r7, #8]
+ 80016ba: 4b4b ldr r3, [pc, #300] ; (80017e8 <HAL_RCC_GetSysClockFreq+0x160>)
+ 80016bc: 60bb str r3, [r7, #8]
break;
- 800161a: e089 b.n 8001730 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80016be: e089 b.n 80017d4 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 800161c: 4b47 ldr r3, [pc, #284] ; (800173c <HAL_RCC_GetSysClockFreq+0x158>)
- 800161e: 685b ldr r3, [r3, #4]
- 8001620: f003 033f and.w r3, r3, #63 ; 0x3f
- 8001624: 607b str r3, [r7, #4]
+ 80016c0: 4b47 ldr r3, [pc, #284] ; (80017e0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80016c2: 685b ldr r3, [r3, #4]
+ 80016c4: f003 033f and.w r3, r3, #63 ; 0x3f
+ 80016c8: 607b str r3, [r7, #4]
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 8001626: 4b45 ldr r3, [pc, #276] ; (800173c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001628: 685b ldr r3, [r3, #4]
- 800162a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 800162e: 2b00 cmp r3, #0
- 8001630: d023 beq.n 800167a <HAL_RCC_GetSysClockFreq+0x96>
+ 80016ca: 4b45 ldr r3, [pc, #276] ; (80017e0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80016cc: 685b ldr r3, [r3, #4]
+ 80016ce: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 80016d2: 2b00 cmp r3, #0
+ 80016d4: d023 beq.n 800171e <HAL_RCC_GetSysClockFreq+0x96>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8001632: 4b42 ldr r3, [pc, #264] ; (800173c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001634: 685b ldr r3, [r3, #4]
- 8001636: 099b lsrs r3, r3, #6
- 8001638: f04f 0400 mov.w r4, #0
- 800163c: f240 11ff movw r1, #511 ; 0x1ff
- 8001640: f04f 0200 mov.w r2, #0
- 8001644: ea03 0501 and.w r5, r3, r1
- 8001648: ea04 0602 and.w r6, r4, r2
- 800164c: 4a3d ldr r2, [pc, #244] ; (8001744 <HAL_RCC_GetSysClockFreq+0x160>)
- 800164e: fb02 f106 mul.w r1, r2, r6
- 8001652: 2200 movs r2, #0
- 8001654: fb02 f205 mul.w r2, r2, r5
- 8001658: 440a add r2, r1
- 800165a: 493a ldr r1, [pc, #232] ; (8001744 <HAL_RCC_GetSysClockFreq+0x160>)
- 800165c: fba5 0101 umull r0, r1, r5, r1
- 8001660: 1853 adds r3, r2, r1
- 8001662: 4619 mov r1, r3
- 8001664: 687b ldr r3, [r7, #4]
- 8001666: f04f 0400 mov.w r4, #0
- 800166a: 461a mov r2, r3
- 800166c: 4623 mov r3, r4
- 800166e: f7fe fde3 bl 8000238 <__aeabi_uldivmod>
- 8001672: 4603 mov r3, r0
- 8001674: 460c mov r4, r1
- 8001676: 60fb str r3, [r7, #12]
- 8001678: e049 b.n 800170e <HAL_RCC_GetSysClockFreq+0x12a>
+ 80016d6: 4b42 ldr r3, [pc, #264] ; (80017e0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80016d8: 685b ldr r3, [r3, #4]
+ 80016da: 099b lsrs r3, r3, #6
+ 80016dc: f04f 0400 mov.w r4, #0
+ 80016e0: f240 11ff movw r1, #511 ; 0x1ff
+ 80016e4: f04f 0200 mov.w r2, #0
+ 80016e8: ea03 0501 and.w r5, r3, r1
+ 80016ec: ea04 0602 and.w r6, r4, r2
+ 80016f0: 4a3d ldr r2, [pc, #244] ; (80017e8 <HAL_RCC_GetSysClockFreq+0x160>)
+ 80016f2: fb02 f106 mul.w r1, r2, r6
+ 80016f6: 2200 movs r2, #0
+ 80016f8: fb02 f205 mul.w r2, r2, r5
+ 80016fc: 440a add r2, r1
+ 80016fe: 493a ldr r1, [pc, #232] ; (80017e8 <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001700: fba5 0101 umull r0, r1, r5, r1
+ 8001704: 1853 adds r3, r2, r1
+ 8001706: 4619 mov r1, r3
+ 8001708: 687b ldr r3, [r7, #4]
+ 800170a: f04f 0400 mov.w r4, #0
+ 800170e: 461a mov r2, r3
+ 8001710: 4623 mov r3, r4
+ 8001712: f7fe fd91 bl 8000238 <__aeabi_uldivmod>
+ 8001716: 4603 mov r3, r0
+ 8001718: 460c mov r4, r1
+ 800171a: 60fb str r3, [r7, #12]
+ 800171c: e049 b.n 80017b2 <HAL_RCC_GetSysClockFreq+0x12a>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 800167a: 4b30 ldr r3, [pc, #192] ; (800173c <HAL_RCC_GetSysClockFreq+0x158>)
- 800167c: 685b ldr r3, [r3, #4]
- 800167e: 099b lsrs r3, r3, #6
- 8001680: f04f 0400 mov.w r4, #0
- 8001684: f240 11ff movw r1, #511 ; 0x1ff
- 8001688: f04f 0200 mov.w r2, #0
- 800168c: ea03 0501 and.w r5, r3, r1
- 8001690: ea04 0602 and.w r6, r4, r2
- 8001694: 4629 mov r1, r5
- 8001696: 4632 mov r2, r6
- 8001698: f04f 0300 mov.w r3, #0
- 800169c: f04f 0400 mov.w r4, #0
- 80016a0: 0154 lsls r4, r2, #5
- 80016a2: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 80016a6: 014b lsls r3, r1, #5
- 80016a8: 4619 mov r1, r3
- 80016aa: 4622 mov r2, r4
- 80016ac: 1b49 subs r1, r1, r5
- 80016ae: eb62 0206 sbc.w r2, r2, r6
- 80016b2: f04f 0300 mov.w r3, #0
- 80016b6: f04f 0400 mov.w r4, #0
- 80016ba: 0194 lsls r4, r2, #6
- 80016bc: ea44 6491 orr.w r4, r4, r1, lsr #26
- 80016c0: 018b lsls r3, r1, #6
- 80016c2: 1a5b subs r3, r3, r1
- 80016c4: eb64 0402 sbc.w r4, r4, r2
- 80016c8: f04f 0100 mov.w r1, #0
- 80016cc: f04f 0200 mov.w r2, #0
- 80016d0: 00e2 lsls r2, r4, #3
- 80016d2: ea42 7253 orr.w r2, r2, r3, lsr #29
- 80016d6: 00d9 lsls r1, r3, #3
- 80016d8: 460b mov r3, r1
- 80016da: 4614 mov r4, r2
- 80016dc: 195b adds r3, r3, r5
- 80016de: eb44 0406 adc.w r4, r4, r6
- 80016e2: f04f 0100 mov.w r1, #0
- 80016e6: f04f 0200 mov.w r2, #0
- 80016ea: 02a2 lsls r2, r4, #10
- 80016ec: ea42 5293 orr.w r2, r2, r3, lsr #22
- 80016f0: 0299 lsls r1, r3, #10
- 80016f2: 460b mov r3, r1
- 80016f4: 4614 mov r4, r2
- 80016f6: 4618 mov r0, r3
- 80016f8: 4621 mov r1, r4
- 80016fa: 687b ldr r3, [r7, #4]
- 80016fc: f04f 0400 mov.w r4, #0
- 8001700: 461a mov r2, r3
- 8001702: 4623 mov r3, r4
- 8001704: f7fe fd98 bl 8000238 <__aeabi_uldivmod>
- 8001708: 4603 mov r3, r0
- 800170a: 460c mov r4, r1
- 800170c: 60fb str r3, [r7, #12]
+ 800171e: 4b30 ldr r3, [pc, #192] ; (80017e0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001720: 685b ldr r3, [r3, #4]
+ 8001722: 099b lsrs r3, r3, #6
+ 8001724: f04f 0400 mov.w r4, #0
+ 8001728: f240 11ff movw r1, #511 ; 0x1ff
+ 800172c: f04f 0200 mov.w r2, #0
+ 8001730: ea03 0501 and.w r5, r3, r1
+ 8001734: ea04 0602 and.w r6, r4, r2
+ 8001738: 4629 mov r1, r5
+ 800173a: 4632 mov r2, r6
+ 800173c: f04f 0300 mov.w r3, #0
+ 8001740: f04f 0400 mov.w r4, #0
+ 8001744: 0154 lsls r4, r2, #5
+ 8001746: ea44 64d1 orr.w r4, r4, r1, lsr #27
+ 800174a: 014b lsls r3, r1, #5
+ 800174c: 4619 mov r1, r3
+ 800174e: 4622 mov r2, r4
+ 8001750: 1b49 subs r1, r1, r5
+ 8001752: eb62 0206 sbc.w r2, r2, r6
+ 8001756: f04f 0300 mov.w r3, #0
+ 800175a: f04f 0400 mov.w r4, #0
+ 800175e: 0194 lsls r4, r2, #6
+ 8001760: ea44 6491 orr.w r4, r4, r1, lsr #26
+ 8001764: 018b lsls r3, r1, #6
+ 8001766: 1a5b subs r3, r3, r1
+ 8001768: eb64 0402 sbc.w r4, r4, r2
+ 800176c: f04f 0100 mov.w r1, #0
+ 8001770: f04f 0200 mov.w r2, #0
+ 8001774: 00e2 lsls r2, r4, #3
+ 8001776: ea42 7253 orr.w r2, r2, r3, lsr #29
+ 800177a: 00d9 lsls r1, r3, #3
+ 800177c: 460b mov r3, r1
+ 800177e: 4614 mov r4, r2
+ 8001780: 195b adds r3, r3, r5
+ 8001782: eb44 0406 adc.w r4, r4, r6
+ 8001786: f04f 0100 mov.w r1, #0
+ 800178a: f04f 0200 mov.w r2, #0
+ 800178e: 02a2 lsls r2, r4, #10
+ 8001790: ea42 5293 orr.w r2, r2, r3, lsr #22
+ 8001794: 0299 lsls r1, r3, #10
+ 8001796: 460b mov r3, r1
+ 8001798: 4614 mov r4, r2
+ 800179a: 4618 mov r0, r3
+ 800179c: 4621 mov r1, r4
+ 800179e: 687b ldr r3, [r7, #4]
+ 80017a0: f04f 0400 mov.w r4, #0
+ 80017a4: 461a mov r2, r3
+ 80017a6: 4623 mov r3, r4
+ 80017a8: f7fe fd46 bl 8000238 <__aeabi_uldivmod>
+ 80017ac: 4603 mov r3, r0
+ 80017ae: 460c mov r4, r1
+ 80017b0: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 800170e: 4b0b ldr r3, [pc, #44] ; (800173c <HAL_RCC_GetSysClockFreq+0x158>)
- 8001710: 685b ldr r3, [r3, #4]
- 8001712: 0c1b lsrs r3, r3, #16
- 8001714: f003 0303 and.w r3, r3, #3
- 8001718: 3301 adds r3, #1
- 800171a: 005b lsls r3, r3, #1
- 800171c: 603b str r3, [r7, #0]
+ 80017b2: 4b0b ldr r3, [pc, #44] ; (80017e0 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80017b4: 685b ldr r3, [r3, #4]
+ 80017b6: 0c1b lsrs r3, r3, #16
+ 80017b8: f003 0303 and.w r3, r3, #3
+ 80017bc: 3301 adds r3, #1
+ 80017be: 005b lsls r3, r3, #1
+ 80017c0: 603b str r3, [r7, #0]
sysclockfreq = pllvco/pllp;
- 800171e: 68fa ldr r2, [r7, #12]
- 8001720: 683b ldr r3, [r7, #0]
- 8001722: fbb2 f3f3 udiv r3, r2, r3
- 8001726: 60bb str r3, [r7, #8]
+ 80017c2: 68fa ldr r2, [r7, #12]
+ 80017c4: 683b ldr r3, [r7, #0]
+ 80017c6: fbb2 f3f3 udiv r3, r2, r3
+ 80017ca: 60bb str r3, [r7, #8]
break;
- 8001728: e002 b.n 8001730 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80017cc: e002 b.n 80017d4 <HAL_RCC_GetSysClockFreq+0x14c>
}
default:
{
sysclockfreq = HSI_VALUE;
- 800172a: 4b05 ldr r3, [pc, #20] ; (8001740 <HAL_RCC_GetSysClockFreq+0x15c>)
- 800172c: 60bb str r3, [r7, #8]
+ 80017ce: 4b05 ldr r3, [pc, #20] ; (80017e4 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 80017d0: 60bb str r3, [r7, #8]
break;
- 800172e: bf00 nop
+ 80017d2: bf00 nop
}
}
return sysclockfreq;
- 8001730: 68bb ldr r3, [r7, #8]
+ 80017d4: 68bb ldr r3, [r7, #8]
}
- 8001732: 4618 mov r0, r3
- 8001734: 3714 adds r7, #20
- 8001736: 46bd mov sp, r7
- 8001738: bdf0 pop {r4, r5, r6, r7, pc}
- 800173a: bf00 nop
- 800173c: 40023800 .word 0x40023800
- 8001740: 00f42400 .word 0x00f42400
- 8001744: 017d7840 .word 0x017d7840
-
-08001748 <HAL_RCC_GetHCLKFreq>:
+ 80017d6: 4618 mov r0, r3
+ 80017d8: 3714 adds r7, #20
+ 80017da: 46bd mov sp, r7
+ 80017dc: bdf0 pop {r4, r5, r6, r7, pc}
+ 80017de: bf00 nop
+ 80017e0: 40023800 .word 0x40023800
+ 80017e4: 00f42400 .word 0x00f42400
+ 80017e8: 017d7840 .word 0x017d7840
+
+080017ec <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
- 8001748: b480 push {r7}
- 800174a: af00 add r7, sp, #0
+ 80017ec: b480 push {r7}
+ 80017ee: af00 add r7, sp, #0
return SystemCoreClock;
- 800174c: 4b03 ldr r3, [pc, #12] ; (800175c <HAL_RCC_GetHCLKFreq+0x14>)
- 800174e: 681b ldr r3, [r3, #0]
+ 80017f0: 4b03 ldr r3, [pc, #12] ; (8001800 <HAL_RCC_GetHCLKFreq+0x14>)
+ 80017f2: 681b ldr r3, [r3, #0]
}
- 8001750: 4618 mov r0, r3
- 8001752: 46bd mov sp, r7
- 8001754: f85d 7b04 ldr.w r7, [sp], #4
- 8001758: 4770 bx lr
- 800175a: bf00 nop
- 800175c: 20000000 .word 0x20000000
-
-08001760 <HAL_RCC_GetPCLK1Freq>:
+ 80017f4: 4618 mov r0, r3
+ 80017f6: 46bd mov sp, r7
+ 80017f8: f85d 7b04 ldr.w r7, [sp], #4
+ 80017fc: 4770 bx lr
+ 80017fe: bf00 nop
+ 8001800: 20000000 .word 0x20000000
+
+08001804 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
- 8001760: b580 push {r7, lr}
- 8001762: af00 add r7, sp, #0
+ 8001804: b580 push {r7, lr}
+ 8001806: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 8001764: f7ff fff0 bl 8001748 <HAL_RCC_GetHCLKFreq>
- 8001768: 4601 mov r1, r0
- 800176a: 4b05 ldr r3, [pc, #20] ; (8001780 <HAL_RCC_GetPCLK1Freq+0x20>)
- 800176c: 689b ldr r3, [r3, #8]
- 800176e: 0a9b lsrs r3, r3, #10
- 8001770: f003 0307 and.w r3, r3, #7
- 8001774: 4a03 ldr r2, [pc, #12] ; (8001784 <HAL_RCC_GetPCLK1Freq+0x24>)
- 8001776: 5cd3 ldrb r3, [r2, r3]
- 8001778: fa21 f303 lsr.w r3, r1, r3
+ 8001808: f7ff fff0 bl 80017ec <HAL_RCC_GetHCLKFreq>
+ 800180c: 4601 mov r1, r0
+ 800180e: 4b05 ldr r3, [pc, #20] ; (8001824 <HAL_RCC_GetPCLK1Freq+0x20>)
+ 8001810: 689b ldr r3, [r3, #8]
+ 8001812: 0a9b lsrs r3, r3, #10
+ 8001814: f003 0307 and.w r3, r3, #7
+ 8001818: 4a03 ldr r2, [pc, #12] ; (8001828 <HAL_RCC_GetPCLK1Freq+0x24>)
+ 800181a: 5cd3 ldrb r3, [r2, r3]
+ 800181c: fa21 f303 lsr.w r3, r1, r3
}
- 800177c: 4618 mov r0, r3
- 800177e: bd80 pop {r7, pc}
- 8001780: 40023800 .word 0x40023800
- 8001784: 080029c8 .word 0x080029c8
+ 8001820: 4618 mov r0, r3
+ 8001822: bd80 pop {r7, pc}
+ 8001824: 40023800 .word 0x40023800
+ 8001828: 08002a6c .word 0x08002a6c
-08001788 <HAL_RCC_GetPCLK2Freq>:
+0800182c <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
- 8001788: b580 push {r7, lr}
- 800178a: af00 add r7, sp, #0
+ 800182c: b580 push {r7, lr}
+ 800182e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 800178c: f7ff ffdc bl 8001748 <HAL_RCC_GetHCLKFreq>
- 8001790: 4601 mov r1, r0
- 8001792: 4b05 ldr r3, [pc, #20] ; (80017a8 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8001794: 689b ldr r3, [r3, #8]
- 8001796: 0b5b lsrs r3, r3, #13
- 8001798: f003 0307 and.w r3, r3, #7
- 800179c: 4a03 ldr r2, [pc, #12] ; (80017ac <HAL_RCC_GetPCLK2Freq+0x24>)
- 800179e: 5cd3 ldrb r3, [r2, r3]
- 80017a0: fa21 f303 lsr.w r3, r1, r3
+ 8001830: f7ff ffdc bl 80017ec <HAL_RCC_GetHCLKFreq>
+ 8001834: 4601 mov r1, r0
+ 8001836: 4b05 ldr r3, [pc, #20] ; (800184c <HAL_RCC_GetPCLK2Freq+0x20>)
+ 8001838: 689b ldr r3, [r3, #8]
+ 800183a: 0b5b lsrs r3, r3, #13
+ 800183c: f003 0307 and.w r3, r3, #7
+ 8001840: 4a03 ldr r2, [pc, #12] ; (8001850 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 8001842: 5cd3 ldrb r3, [r2, r3]
+ 8001844: fa21 f303 lsr.w r3, r1, r3
}
- 80017a4: 4618 mov r0, r3
- 80017a6: bd80 pop {r7, pc}
- 80017a8: 40023800 .word 0x40023800
- 80017ac: 080029c8 .word 0x080029c8
+ 8001848: 4618 mov r0, r3
+ 800184a: bd80 pop {r7, pc}
+ 800184c: 40023800 .word 0x40023800
+ 8001850: 08002a6c .word 0x08002a6c
-080017b0 <HAL_RCCEx_PeriphCLKConfig>:
+08001854 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- 80017b0: b580 push {r7, lr}
- 80017b2: b088 sub sp, #32
- 80017b4: af00 add r7, sp, #0
- 80017b6: 6078 str r0, [r7, #4]
+ 8001854: b580 push {r7, lr}
+ 8001856: b088 sub sp, #32
+ 8001858: af00 add r7, sp, #0
+ 800185a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
- 80017b8: 2300 movs r3, #0
- 80017ba: 617b str r3, [r7, #20]
+ 800185c: 2300 movs r3, #0
+ 800185e: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
- 80017bc: 2300 movs r3, #0
- 80017be: 613b str r3, [r7, #16]
+ 8001860: 2300 movs r3, #0
+ 8001862: 613b str r3, [r7, #16]
uint32_t tmpreg1 = 0;
- 80017c0: 2300 movs r3, #0
- 80017c2: 60fb str r3, [r7, #12]
+ 8001864: 2300 movs r3, #0
+ 8001866: 60fb str r3, [r7, #12]
uint32_t plli2sused = 0;
- 80017c4: 2300 movs r3, #0
- 80017c6: 61fb str r3, [r7, #28]
+ 8001868: 2300 movs r3, #0
+ 800186a: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
- 80017c8: 2300 movs r3, #0
- 80017ca: 61bb str r3, [r7, #24]
+ 800186c: 2300 movs r3, #0
+ 800186e: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- 80017cc: 687b ldr r3, [r7, #4]
- 80017ce: 681b ldr r3, [r3, #0]
- 80017d0: f003 0301 and.w r3, r3, #1
- 80017d4: 2b00 cmp r3, #0
- 80017d6: d012 beq.n 80017fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ 8001870: 687b ldr r3, [r7, #4]
+ 8001872: 681b ldr r3, [r3, #0]
+ 8001874: f003 0301 and.w r3, r3, #1
+ 8001878: 2b00 cmp r3, #0
+ 800187a: d012 beq.n 80018a2 <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
- 80017d8: 4b69 ldr r3, [pc, #420] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80017da: 689b ldr r3, [r3, #8]
- 80017dc: 4a68 ldr r2, [pc, #416] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80017de: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
- 80017e2: 6093 str r3, [r2, #8]
- 80017e4: 4b66 ldr r3, [pc, #408] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80017e6: 689a ldr r2, [r3, #8]
- 80017e8: 687b ldr r3, [r7, #4]
- 80017ea: 6b5b ldr r3, [r3, #52] ; 0x34
- 80017ec: 4964 ldr r1, [pc, #400] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80017ee: 4313 orrs r3, r2
- 80017f0: 608b str r3, [r1, #8]
+ 800187c: 4b69 ldr r3, [pc, #420] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 800187e: 689b ldr r3, [r3, #8]
+ 8001880: 4a68 ldr r2, [pc, #416] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001882: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
+ 8001886: 6093 str r3, [r2, #8]
+ 8001888: 4b66 ldr r3, [pc, #408] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 800188a: 689a ldr r2, [r3, #8]
+ 800188c: 687b ldr r3, [r7, #4]
+ 800188e: 6b5b ldr r3, [r3, #52] ; 0x34
+ 8001890: 4964 ldr r1, [pc, #400] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001892: 4313 orrs r3, r2
+ 8001894: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
- 80017f2: 687b ldr r3, [r7, #4]
- 80017f4: 6b5b ldr r3, [r3, #52] ; 0x34
- 80017f6: 2b00 cmp r3, #0
- 80017f8: d101 bne.n 80017fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
+ 8001896: 687b ldr r3, [r7, #4]
+ 8001898: 6b5b ldr r3, [r3, #52] ; 0x34
+ 800189a: 2b00 cmp r3, #0
+ 800189c: d101 bne.n 80018a2 <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
plli2sused = 1;
- 80017fa: 2301 movs r3, #1
- 80017fc: 61fb str r3, [r7, #28]
+ 800189e: 2301 movs r3, #1
+ 80018a0: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
- 80017fe: 687b ldr r3, [r7, #4]
- 8001800: 681b ldr r3, [r3, #0]
- 8001802: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8001806: 2b00 cmp r3, #0
- 8001808: d017 beq.n 800183a <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ 80018a2: 687b ldr r3, [r7, #4]
+ 80018a4: 681b ldr r3, [r3, #0]
+ 80018a6: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 80018aa: 2b00 cmp r3, #0
+ 80018ac: d017 beq.n 80018de <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
- 800180a: 4b5d ldr r3, [pc, #372] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800180c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001810: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8001814: 687b ldr r3, [r7, #4]
- 8001816: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001818: 4959 ldr r1, [pc, #356] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800181a: 4313 orrs r3, r2
- 800181c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 80018ae: 4b5d ldr r3, [pc, #372] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80018b0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 80018b4: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
+ 80018b8: 687b ldr r3, [r7, #4]
+ 80018ba: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 80018bc: 4959 ldr r1, [pc, #356] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80018be: 4313 orrs r3, r2
+ 80018c0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
- 8001820: 687b ldr r3, [r7, #4]
- 8001822: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001824: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8001828: d101 bne.n 800182e <HAL_RCCEx_PeriphCLKConfig+0x7e>
+ 80018c4: 687b ldr r3, [r7, #4]
+ 80018c6: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 80018c8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 80018cc: d101 bne.n 80018d2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
plli2sused = 1;
- 800182a: 2301 movs r3, #1
- 800182c: 61fb str r3, [r7, #28]
+ 80018ce: 2301 movs r3, #1
+ 80018d0: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
- 800182e: 687b ldr r3, [r7, #4]
- 8001830: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001832: 2b00 cmp r3, #0
- 8001834: d101 bne.n 800183a <HAL_RCCEx_PeriphCLKConfig+0x8a>
+ 80018d2: 687b ldr r3, [r7, #4]
+ 80018d4: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 80018d6: 2b00 cmp r3, #0
+ 80018d8: d101 bne.n 80018de <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
pllsaiused = 1;
- 8001836: 2301 movs r3, #1
- 8001838: 61bb str r3, [r7, #24]
+ 80018da: 2301 movs r3, #1
+ 80018dc: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
- 800183a: 687b ldr r3, [r7, #4]
- 800183c: 681b ldr r3, [r3, #0]
- 800183e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8001842: 2b00 cmp r3, #0
- 8001844: d017 beq.n 8001876 <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ 80018de: 687b ldr r3, [r7, #4]
+ 80018e0: 681b ldr r3, [r3, #0]
+ 80018e2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 80018e6: 2b00 cmp r3, #0
+ 80018e8: d017 beq.n 800191a <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
- 8001846: 4b4e ldr r3, [pc, #312] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001848: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 800184c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8001850: 687b ldr r3, [r7, #4]
- 8001852: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001854: 494a ldr r1, [pc, #296] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001856: 4313 orrs r3, r2
- 8001858: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 80018ea: 4b4e ldr r3, [pc, #312] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80018ec: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 80018f0: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
+ 80018f4: 687b ldr r3, [r7, #4]
+ 80018f6: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80018f8: 494a ldr r1, [pc, #296] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80018fa: 4313 orrs r3, r2
+ 80018fc: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
- 800185c: 687b ldr r3, [r7, #4]
- 800185e: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001860: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8001864: d101 bne.n 800186a <HAL_RCCEx_PeriphCLKConfig+0xba>
+ 8001900: 687b ldr r3, [r7, #4]
+ 8001902: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001904: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8001908: d101 bne.n 800190e <HAL_RCCEx_PeriphCLKConfig+0xba>
{
plli2sused = 1;
- 8001866: 2301 movs r3, #1
- 8001868: 61fb str r3, [r7, #28]
+ 800190a: 2301 movs r3, #1
+ 800190c: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
- 800186a: 687b ldr r3, [r7, #4]
- 800186c: 6c1b ldr r3, [r3, #64] ; 0x40
- 800186e: 2b00 cmp r3, #0
- 8001870: d101 bne.n 8001876 <HAL_RCCEx_PeriphCLKConfig+0xc6>
+ 800190e: 687b ldr r3, [r7, #4]
+ 8001910: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001912: 2b00 cmp r3, #0
+ 8001914: d101 bne.n 800191a <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
pllsaiused = 1;
- 8001872: 2301 movs r3, #1
- 8001874: 61bb str r3, [r7, #24]
+ 8001916: 2301 movs r3, #1
+ 8001918: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8001876: 687b ldr r3, [r7, #4]
- 8001878: 681b ldr r3, [r3, #0]
- 800187a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 800187e: 2b00 cmp r3, #0
- 8001880: d001 beq.n 8001886 <HAL_RCCEx_PeriphCLKConfig+0xd6>
+ 800191a: 687b ldr r3, [r7, #4]
+ 800191c: 681b ldr r3, [r3, #0]
+ 800191e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
+ 8001922: 2b00 cmp r3, #0
+ 8001924: d001 beq.n 800192a <HAL_RCCEx_PeriphCLKConfig+0xd6>
{
plli2sused = 1;
- 8001882: 2301 movs r3, #1
- 8001884: 61fb str r3, [r7, #28]
+ 8001926: 2301 movs r3, #1
+ 8001928: 61fb str r3, [r7, #28]
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
- 8001886: 687b ldr r3, [r7, #4]
- 8001888: 681b ldr r3, [r3, #0]
- 800188a: f003 0320 and.w r3, r3, #32
- 800188e: 2b00 cmp r3, #0
- 8001890: f000 808b beq.w 80019aa <HAL_RCCEx_PeriphCLKConfig+0x1fa>
+ 800192a: 687b ldr r3, [r7, #4]
+ 800192c: 681b ldr r3, [r3, #0]
+ 800192e: f003 0320 and.w r3, r3, #32
+ 8001932: 2b00 cmp r3, #0
+ 8001934: f000 808b beq.w 8001a4e <HAL_RCCEx_PeriphCLKConfig+0x1fa>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
- 8001894: 4b3a ldr r3, [pc, #232] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001896: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001898: 4a39 ldr r2, [pc, #228] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800189a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 800189e: 6413 str r3, [r2, #64] ; 0x40
- 80018a0: 4b37 ldr r3, [pc, #220] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80018a2: 6c1b ldr r3, [r3, #64] ; 0x40
- 80018a4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 80018a8: 60bb str r3, [r7, #8]
- 80018aa: 68bb ldr r3, [r7, #8]
+ 8001938: 4b3a ldr r3, [pc, #232] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 800193a: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800193c: 4a39 ldr r2, [pc, #228] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 800193e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8001942: 6413 str r3, [r2, #64] ; 0x40
+ 8001944: 4b37 ldr r3, [pc, #220] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001946: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001948: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 800194c: 60bb str r3, [r7, #8]
+ 800194e: 68bb ldr r3, [r7, #8]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
- 80018ac: 4b35 ldr r3, [pc, #212] ; (8001984 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 80018ae: 681b ldr r3, [r3, #0]
- 80018b0: 4a34 ldr r2, [pc, #208] ; (8001984 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 80018b2: f443 7380 orr.w r3, r3, #256 ; 0x100
- 80018b6: 6013 str r3, [r2, #0]
+ 8001950: 4b35 ldr r3, [pc, #212] ; (8001a28 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001952: 681b ldr r3, [r3, #0]
+ 8001954: 4a34 ldr r2, [pc, #208] ; (8001a28 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001956: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 800195a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 80018b8: f7ff f87c bl 80009b4 <HAL_GetTick>
- 80018bc: 6178 str r0, [r7, #20]
+ 800195c: f7ff f87c bl 8000a58 <HAL_GetTick>
+ 8001960: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 80018be: e008 b.n 80018d2 <HAL_RCCEx_PeriphCLKConfig+0x122>
+ 8001962: e008 b.n 8001976 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 80018c0: f7ff f878 bl 80009b4 <HAL_GetTick>
- 80018c4: 4602 mov r2, r0
- 80018c6: 697b ldr r3, [r7, #20]
- 80018c8: 1ad3 subs r3, r2, r3
- 80018ca: 2b64 cmp r3, #100 ; 0x64
- 80018cc: d901 bls.n 80018d2 <HAL_RCCEx_PeriphCLKConfig+0x122>
+ 8001964: f7ff f878 bl 8000a58 <HAL_GetTick>
+ 8001968: 4602 mov r2, r0
+ 800196a: 697b ldr r3, [r7, #20]
+ 800196c: 1ad3 subs r3, r2, r3
+ 800196e: 2b64 cmp r3, #100 ; 0x64
+ 8001970: d901 bls.n 8001976 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
return HAL_TIMEOUT;
- 80018ce: 2303 movs r3, #3
- 80018d0: e38d b.n 8001fee <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8001972: 2303 movs r3, #3
+ 8001974: e38d b.n 8002092 <HAL_RCCEx_PeriphCLKConfig+0x83e>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- 80018d2: 4b2c ldr r3, [pc, #176] ; (8001984 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 80018d4: 681b ldr r3, [r3, #0]
- 80018d6: f403 7380 and.w r3, r3, #256 ; 0x100
- 80018da: 2b00 cmp r3, #0
- 80018dc: d0f0 beq.n 80018c0 <HAL_RCCEx_PeriphCLKConfig+0x110>
+ 8001976: 4b2c ldr r3, [pc, #176] ; (8001a28 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
+ 8001978: 681b ldr r3, [r3, #0]
+ 800197a: f403 7380 and.w r3, r3, #256 ; 0x100
+ 800197e: 2b00 cmp r3, #0
+ 8001980: d0f0 beq.n 8001964 <HAL_RCCEx_PeriphCLKConfig+0x110>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
- 80018de: 4b28 ldr r3, [pc, #160] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80018e0: 6f1b ldr r3, [r3, #112] ; 0x70
- 80018e2: f403 7340 and.w r3, r3, #768 ; 0x300
- 80018e6: 613b str r3, [r7, #16]
+ 8001982: 4b28 ldr r3, [pc, #160] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001984: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001986: f403 7340 and.w r3, r3, #768 ; 0x300
+ 800198a: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
- 80018e8: 693b ldr r3, [r7, #16]
- 80018ea: 2b00 cmp r3, #0
- 80018ec: d035 beq.n 800195a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
- 80018ee: 687b ldr r3, [r7, #4]
- 80018f0: 6b1b ldr r3, [r3, #48] ; 0x30
- 80018f2: f403 7340 and.w r3, r3, #768 ; 0x300
- 80018f6: 693a ldr r2, [r7, #16]
- 80018f8: 429a cmp r2, r3
- 80018fa: d02e beq.n 800195a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 800198c: 693b ldr r3, [r7, #16]
+ 800198e: 2b00 cmp r3, #0
+ 8001990: d035 beq.n 80019fe <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 8001992: 687b ldr r3, [r7, #4]
+ 8001994: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001996: f403 7340 and.w r3, r3, #768 ; 0x300
+ 800199a: 693a ldr r2, [r7, #16]
+ 800199c: 429a cmp r2, r3
+ 800199e: d02e beq.n 80019fe <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
- 80018fc: 4b20 ldr r3, [pc, #128] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80018fe: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001900: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8001904: 613b str r3, [r7, #16]
+ 80019a0: 4b20 ldr r3, [pc, #128] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019a2: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80019a4: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 80019a8: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
- 8001906: 4b1e ldr r3, [pc, #120] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001908: 6f1b ldr r3, [r3, #112] ; 0x70
- 800190a: 4a1d ldr r2, [pc, #116] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800190c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8001910: 6713 str r3, [r2, #112] ; 0x70
+ 80019aa: 4b1e ldr r3, [pc, #120] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019ac: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80019ae: 4a1d ldr r2, [pc, #116] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019b0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 80019b4: 6713 str r3, [r2, #112] ; 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
- 8001912: 4b1b ldr r3, [pc, #108] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001914: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001916: 4a1a ldr r2, [pc, #104] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001918: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 800191c: 6713 str r3, [r2, #112] ; 0x70
+ 80019b6: 4b1b ldr r3, [pc, #108] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019b8: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80019ba: 4a1a ldr r2, [pc, #104] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019bc: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 80019c0: 6713 str r3, [r2, #112] ; 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
- 800191e: 4a18 ldr r2, [pc, #96] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001920: 693b ldr r3, [r7, #16]
- 8001922: 6713 str r3, [r2, #112] ; 0x70
+ 80019c2: 4a18 ldr r2, [pc, #96] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019c4: 693b ldr r3, [r7, #16]
+ 80019c6: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
- 8001924: 4b16 ldr r3, [pc, #88] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001926: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001928: f003 0301 and.w r3, r3, #1
- 800192c: 2b01 cmp r3, #1
- 800192e: d114 bne.n 800195a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
+ 80019c8: 4b16 ldr r3, [pc, #88] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019ca: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80019cc: f003 0301 and.w r3, r3, #1
+ 80019d0: 2b01 cmp r3, #1
+ 80019d2: d114 bne.n 80019fe <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001930: f7ff f840 bl 80009b4 <HAL_GetTick>
- 8001934: 6178 str r0, [r7, #20]
+ 80019d4: f7ff f840 bl 8000a58 <HAL_GetTick>
+ 80019d8: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001936: e00a b.n 800194e <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ 80019da: e00a b.n 80019f2 <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001938: f7ff f83c bl 80009b4 <HAL_GetTick>
- 800193c: 4602 mov r2, r0
- 800193e: 697b ldr r3, [r7, #20]
- 8001940: 1ad3 subs r3, r2, r3
- 8001942: f241 3288 movw r2, #5000 ; 0x1388
- 8001946: 4293 cmp r3, r2
- 8001948: d901 bls.n 800194e <HAL_RCCEx_PeriphCLKConfig+0x19e>
+ 80019dc: f7ff f83c bl 8000a58 <HAL_GetTick>
+ 80019e0: 4602 mov r2, r0
+ 80019e2: 697b ldr r3, [r7, #20]
+ 80019e4: 1ad3 subs r3, r2, r3
+ 80019e6: f241 3288 movw r2, #5000 ; 0x1388
+ 80019ea: 4293 cmp r3, r2
+ 80019ec: d901 bls.n 80019f2 <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
return HAL_TIMEOUT;
- 800194a: 2303 movs r3, #3
- 800194c: e34f b.n 8001fee <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 80019ee: 2303 movs r3, #3
+ 80019f0: e34f b.n 8002092 <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 800194e: 4b0c ldr r3, [pc, #48] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 8001950: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001952: f003 0302 and.w r3, r3, #2
- 8001956: 2b00 cmp r3, #0
- 8001958: d0ee beq.n 8001938 <HAL_RCCEx_PeriphCLKConfig+0x188>
+ 80019f2: 4b0c ldr r3, [pc, #48] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 80019f4: 6f1b ldr r3, [r3, #112] ; 0x70
+ 80019f6: f003 0302 and.w r3, r3, #2
+ 80019fa: 2b00 cmp r3, #0
+ 80019fc: d0ee beq.n 80019dc <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 800195a: 687b ldr r3, [r7, #4]
- 800195c: 6b1b ldr r3, [r3, #48] ; 0x30
- 800195e: f403 7340 and.w r3, r3, #768 ; 0x300
- 8001962: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 8001966: d111 bne.n 800198c <HAL_RCCEx_PeriphCLKConfig+0x1dc>
- 8001968: 4b05 ldr r3, [pc, #20] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800196a: 689b ldr r3, [r3, #8]
- 800196c: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
- 8001970: 687b ldr r3, [r7, #4]
- 8001972: 6b19 ldr r1, [r3, #48] ; 0x30
- 8001974: 4b04 ldr r3, [pc, #16] ; (8001988 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
- 8001976: 400b ands r3, r1
- 8001978: 4901 ldr r1, [pc, #4] ; (8001980 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 800197a: 4313 orrs r3, r2
- 800197c: 608b str r3, [r1, #8]
- 800197e: e00b b.n 8001998 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
- 8001980: 40023800 .word 0x40023800
- 8001984: 40007000 .word 0x40007000
- 8001988: 0ffffcff .word 0x0ffffcff
- 800198c: 4bb3 ldr r3, [pc, #716] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800198e: 689b ldr r3, [r3, #8]
- 8001990: 4ab2 ldr r2, [pc, #712] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001992: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
- 8001996: 6093 str r3, [r2, #8]
- 8001998: 4bb0 ldr r3, [pc, #704] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 800199a: 6f1a ldr r2, [r3, #112] ; 0x70
- 800199c: 687b ldr r3, [r7, #4]
- 800199e: 6b1b ldr r3, [r3, #48] ; 0x30
- 80019a0: f3c3 030b ubfx r3, r3, #0, #12
- 80019a4: 49ad ldr r1, [pc, #692] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80019a6: 4313 orrs r3, r2
- 80019a8: 670b str r3, [r1, #112] ; 0x70
+ 80019fe: 687b ldr r3, [r7, #4]
+ 8001a00: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001a02: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8001a06: f5b3 7f40 cmp.w r3, #768 ; 0x300
+ 8001a0a: d111 bne.n 8001a30 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
+ 8001a0c: 4b05 ldr r3, [pc, #20] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a0e: 689b ldr r3, [r3, #8]
+ 8001a10: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
+ 8001a14: 687b ldr r3, [r7, #4]
+ 8001a16: 6b19 ldr r1, [r3, #48] ; 0x30
+ 8001a18: 4b04 ldr r3, [pc, #16] ; (8001a2c <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
+ 8001a1a: 400b ands r3, r1
+ 8001a1c: 4901 ldr r1, [pc, #4] ; (8001a24 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
+ 8001a1e: 4313 orrs r3, r2
+ 8001a20: 608b str r3, [r1, #8]
+ 8001a22: e00b b.n 8001a3c <HAL_RCCEx_PeriphCLKConfig+0x1e8>
+ 8001a24: 40023800 .word 0x40023800
+ 8001a28: 40007000 .word 0x40007000
+ 8001a2c: 0ffffcff .word 0x0ffffcff
+ 8001a30: 4bb3 ldr r3, [pc, #716] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a32: 689b ldr r3, [r3, #8]
+ 8001a34: 4ab2 ldr r2, [pc, #712] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a36: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
+ 8001a3a: 6093 str r3, [r2, #8]
+ 8001a3c: 4bb0 ldr r3, [pc, #704] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a3e: 6f1a ldr r2, [r3, #112] ; 0x70
+ 8001a40: 687b ldr r3, [r7, #4]
+ 8001a42: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001a44: f3c3 030b ubfx r3, r3, #0, #12
+ 8001a48: 49ad ldr r1, [pc, #692] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a4a: 4313 orrs r3, r2
+ 8001a4c: 670b str r3, [r1, #112] ; 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
- 80019aa: 687b ldr r3, [r7, #4]
- 80019ac: 681b ldr r3, [r3, #0]
- 80019ae: f003 0310 and.w r3, r3, #16
- 80019b2: 2b00 cmp r3, #0
- 80019b4: d010 beq.n 80019d8 <HAL_RCCEx_PeriphCLKConfig+0x228>
+ 8001a4e: 687b ldr r3, [r7, #4]
+ 8001a50: 681b ldr r3, [r3, #0]
+ 8001a52: f003 0310 and.w r3, r3, #16
+ 8001a56: 2b00 cmp r3, #0
+ 8001a58: d010 beq.n 8001a7c <HAL_RCCEx_PeriphCLKConfig+0x228>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
- 80019b6: 4ba9 ldr r3, [pc, #676] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80019b8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 80019bc: 4aa7 ldr r2, [pc, #668] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80019be: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 80019c2: f8c2 308c str.w r3, [r2, #140] ; 0x8c
- 80019c6: 4ba5 ldr r3, [pc, #660] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80019c8: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
- 80019cc: 687b ldr r3, [r7, #4]
- 80019ce: 6b9b ldr r3, [r3, #56] ; 0x38
- 80019d0: 49a2 ldr r1, [pc, #648] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80019d2: 4313 orrs r3, r2
- 80019d4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8001a5a: 4ba9 ldr r3, [pc, #676] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a5c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001a60: 4aa7 ldr r2, [pc, #668] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a62: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8001a66: f8c2 308c str.w r3, [r2, #140] ; 0x8c
+ 8001a6a: 4ba5 ldr r3, [pc, #660] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a6c: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
+ 8001a70: 687b ldr r3, [r7, #4]
+ 8001a72: 6b9b ldr r3, [r3, #56] ; 0x38
+ 8001a74: 49a2 ldr r1, [pc, #648] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a76: 4313 orrs r3, r2
+ 8001a78: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 80019d8: 687b ldr r3, [r7, #4]
- 80019da: 681b ldr r3, [r3, #0]
- 80019dc: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 80019e0: 2b00 cmp r3, #0
- 80019e2: d00a beq.n 80019fa <HAL_RCCEx_PeriphCLKConfig+0x24a>
+ 8001a7c: 687b ldr r3, [r7, #4]
+ 8001a7e: 681b ldr r3, [r3, #0]
+ 8001a80: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 8001a84: 2b00 cmp r3, #0
+ 8001a86: d00a beq.n 8001a9e <HAL_RCCEx_PeriphCLKConfig+0x24a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 80019e4: 4b9d ldr r3, [pc, #628] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80019e6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80019ea: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 80019ee: 687b ldr r3, [r7, #4]
- 80019f0: 6e5b ldr r3, [r3, #100] ; 0x64
- 80019f2: 499a ldr r1, [pc, #616] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 80019f4: 4313 orrs r3, r2
- 80019f6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001a88: 4b9d ldr r3, [pc, #628] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a8a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001a8e: f423 3240 bic.w r2, r3, #196608 ; 0x30000
+ 8001a92: 687b ldr r3, [r7, #4]
+ 8001a94: 6e5b ldr r3, [r3, #100] ; 0x64
+ 8001a96: 499a ldr r1, [pc, #616] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001a98: 4313 orrs r3, r2
+ 8001a9a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
- 80019fa: 687b ldr r3, [r7, #4]
- 80019fc: 681b ldr r3, [r3, #0]
- 80019fe: f403 4300 and.w r3, r3, #32768 ; 0x8000
- 8001a02: 2b00 cmp r3, #0
- 8001a04: d00a beq.n 8001a1c <HAL_RCCEx_PeriphCLKConfig+0x26c>
+ 8001a9e: 687b ldr r3, [r7, #4]
+ 8001aa0: 681b ldr r3, [r3, #0]
+ 8001aa2: f403 4300 and.w r3, r3, #32768 ; 0x8000
+ 8001aa6: 2b00 cmp r3, #0
+ 8001aa8: d00a beq.n 8001ac0 <HAL_RCCEx_PeriphCLKConfig+0x26c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
- 8001a06: 4b95 ldr r3, [pc, #596] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a08: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001a0c: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
- 8001a10: 687b ldr r3, [r7, #4]
- 8001a12: 6e9b ldr r3, [r3, #104] ; 0x68
- 8001a14: 4991 ldr r1, [pc, #580] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a16: 4313 orrs r3, r2
- 8001a18: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001aaa: 4b95 ldr r3, [pc, #596] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001aac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001ab0: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
+ 8001ab4: 687b ldr r3, [r7, #4]
+ 8001ab6: 6e9b ldr r3, [r3, #104] ; 0x68
+ 8001ab8: 4991 ldr r1, [pc, #580] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001aba: 4313 orrs r3, r2
+ 8001abc: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
- 8001a1c: 687b ldr r3, [r7, #4]
- 8001a1e: 681b ldr r3, [r3, #0]
- 8001a20: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8001a24: 2b00 cmp r3, #0
- 8001a26: d00a beq.n 8001a3e <HAL_RCCEx_PeriphCLKConfig+0x28e>
+ 8001ac0: 687b ldr r3, [r7, #4]
+ 8001ac2: 681b ldr r3, [r3, #0]
+ 8001ac4: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8001ac8: 2b00 cmp r3, #0
+ 8001aca: d00a beq.n 8001ae2 <HAL_RCCEx_PeriphCLKConfig+0x28e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
- 8001a28: 4b8c ldr r3, [pc, #560] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a2a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001a2e: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
- 8001a32: 687b ldr r3, [r7, #4]
- 8001a34: 6edb ldr r3, [r3, #108] ; 0x6c
- 8001a36: 4989 ldr r1, [pc, #548] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a38: 4313 orrs r3, r2
- 8001a3a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001acc: 4b8c ldr r3, [pc, #560] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001ace: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001ad2: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
+ 8001ad6: 687b ldr r3, [r7, #4]
+ 8001ad8: 6edb ldr r3, [r3, #108] ; 0x6c
+ 8001ada: 4989 ldr r1, [pc, #548] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001adc: 4313 orrs r3, r2
+ 8001ade: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
- 8001a3e: 687b ldr r3, [r7, #4]
- 8001a40: 681b ldr r3, [r3, #0]
- 8001a42: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8001a46: 2b00 cmp r3, #0
- 8001a48: d00a beq.n 8001a60 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
+ 8001ae2: 687b ldr r3, [r7, #4]
+ 8001ae4: 681b ldr r3, [r3, #0]
+ 8001ae6: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8001aea: 2b00 cmp r3, #0
+ 8001aec: d00a beq.n 8001b04 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
- 8001a4a: 4b84 ldr r3, [pc, #528] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a4c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001a50: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
- 8001a54: 687b ldr r3, [r7, #4]
- 8001a56: 6f1b ldr r3, [r3, #112] ; 0x70
- 8001a58: 4980 ldr r1, [pc, #512] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a5a: 4313 orrs r3, r2
- 8001a5c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001aee: 4b84 ldr r3, [pc, #528] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001af0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001af4: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
+ 8001af8: 687b ldr r3, [r7, #4]
+ 8001afa: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8001afc: 4980 ldr r1, [pc, #512] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001afe: 4313 orrs r3, r2
+ 8001b00: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8001a60: 687b ldr r3, [r7, #4]
- 8001a62: 681b ldr r3, [r3, #0]
- 8001a64: f003 0340 and.w r3, r3, #64 ; 0x40
- 8001a68: 2b00 cmp r3, #0
- 8001a6a: d00a beq.n 8001a82 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
+ 8001b04: 687b ldr r3, [r7, #4]
+ 8001b06: 681b ldr r3, [r3, #0]
+ 8001b08: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8001b0c: 2b00 cmp r3, #0
+ 8001b0e: d00a beq.n 8001b26 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 8001a6c: 4b7b ldr r3, [pc, #492] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a6e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001a72: f023 0203 bic.w r2, r3, #3
- 8001a76: 687b ldr r3, [r7, #4]
- 8001a78: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001a7a: 4978 ldr r1, [pc, #480] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a7c: 4313 orrs r3, r2
- 8001a7e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001b10: 4b7b ldr r3, [pc, #492] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b12: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001b16: f023 0203 bic.w r2, r3, #3
+ 8001b1a: 687b ldr r3, [r7, #4]
+ 8001b1c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001b1e: 4978 ldr r1, [pc, #480] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b20: 4313 orrs r3, r2
+ 8001b22: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8001a82: 687b ldr r3, [r7, #4]
- 8001a84: 681b ldr r3, [r3, #0]
- 8001a86: f003 0380 and.w r3, r3, #128 ; 0x80
- 8001a8a: 2b00 cmp r3, #0
- 8001a8c: d00a beq.n 8001aa4 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
+ 8001b26: 687b ldr r3, [r7, #4]
+ 8001b28: 681b ldr r3, [r3, #0]
+ 8001b2a: f003 0380 and.w r3, r3, #128 ; 0x80
+ 8001b2e: 2b00 cmp r3, #0
+ 8001b30: d00a beq.n 8001b48 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 8001a8e: 4b73 ldr r3, [pc, #460] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a90: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001a94: f023 020c bic.w r2, r3, #12
- 8001a98: 687b ldr r3, [r7, #4]
- 8001a9a: 6c9b ldr r3, [r3, #72] ; 0x48
- 8001a9c: 496f ldr r1, [pc, #444] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001a9e: 4313 orrs r3, r2
- 8001aa0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001b32: 4b73 ldr r3, [pc, #460] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b34: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001b38: f023 020c bic.w r2, r3, #12
+ 8001b3c: 687b ldr r3, [r7, #4]
+ 8001b3e: 6c9b ldr r3, [r3, #72] ; 0x48
+ 8001b40: 496f ldr r1, [pc, #444] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b42: 4313 orrs r3, r2
+ 8001b44: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
- 8001aa4: 687b ldr r3, [r7, #4]
- 8001aa6: 681b ldr r3, [r3, #0]
- 8001aa8: f403 7380 and.w r3, r3, #256 ; 0x100
- 8001aac: 2b00 cmp r3, #0
- 8001aae: d00a beq.n 8001ac6 <HAL_RCCEx_PeriphCLKConfig+0x316>
+ 8001b48: 687b ldr r3, [r7, #4]
+ 8001b4a: 681b ldr r3, [r3, #0]
+ 8001b4c: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8001b50: 2b00 cmp r3, #0
+ 8001b52: d00a beq.n 8001b6a <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
- 8001ab0: 4b6a ldr r3, [pc, #424] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ab2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001ab6: f023 0230 bic.w r2, r3, #48 ; 0x30
- 8001aba: 687b ldr r3, [r7, #4]
- 8001abc: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8001abe: 4967 ldr r1, [pc, #412] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ac0: 4313 orrs r3, r2
- 8001ac2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001b54: 4b6a ldr r3, [pc, #424] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b56: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001b5a: f023 0230 bic.w r2, r3, #48 ; 0x30
+ 8001b5e: 687b ldr r3, [r7, #4]
+ 8001b60: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 8001b62: 4967 ldr r1, [pc, #412] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b64: 4313 orrs r3, r2
+ 8001b66: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
- 8001ac6: 687b ldr r3, [r7, #4]
- 8001ac8: 681b ldr r3, [r3, #0]
- 8001aca: f403 7300 and.w r3, r3, #512 ; 0x200
- 8001ace: 2b00 cmp r3, #0
- 8001ad0: d00a beq.n 8001ae8 <HAL_RCCEx_PeriphCLKConfig+0x338>
+ 8001b6a: 687b ldr r3, [r7, #4]
+ 8001b6c: 681b ldr r3, [r3, #0]
+ 8001b6e: f403 7300 and.w r3, r3, #512 ; 0x200
+ 8001b72: 2b00 cmp r3, #0
+ 8001b74: d00a beq.n 8001b8c <HAL_RCCEx_PeriphCLKConfig+0x338>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
- 8001ad2: 4b62 ldr r3, [pc, #392] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ad4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001ad8: f023 02c0 bic.w r2, r3, #192 ; 0xc0
- 8001adc: 687b ldr r3, [r7, #4]
- 8001ade: 6d1b ldr r3, [r3, #80] ; 0x50
- 8001ae0: 495e ldr r1, [pc, #376] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ae2: 4313 orrs r3, r2
- 8001ae4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001b76: 4b62 ldr r3, [pc, #392] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b78: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001b7c: f023 02c0 bic.w r2, r3, #192 ; 0xc0
+ 8001b80: 687b ldr r3, [r7, #4]
+ 8001b82: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8001b84: 495e ldr r1, [pc, #376] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b86: 4313 orrs r3, r2
+ 8001b88: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
- 8001ae8: 687b ldr r3, [r7, #4]
- 8001aea: 681b ldr r3, [r3, #0]
- 8001aec: f403 6380 and.w r3, r3, #1024 ; 0x400
- 8001af0: 2b00 cmp r3, #0
- 8001af2: d00a beq.n 8001b0a <HAL_RCCEx_PeriphCLKConfig+0x35a>
+ 8001b8c: 687b ldr r3, [r7, #4]
+ 8001b8e: 681b ldr r3, [r3, #0]
+ 8001b90: f403 6380 and.w r3, r3, #1024 ; 0x400
+ 8001b94: 2b00 cmp r3, #0
+ 8001b96: d00a beq.n 8001bae <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
- 8001af4: 4b59 ldr r3, [pc, #356] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001af6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001afa: f423 7240 bic.w r2, r3, #768 ; 0x300
- 8001afe: 687b ldr r3, [r7, #4]
- 8001b00: 6d5b ldr r3, [r3, #84] ; 0x54
- 8001b02: 4956 ldr r1, [pc, #344] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b04: 4313 orrs r3, r2
- 8001b06: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001b98: 4b59 ldr r3, [pc, #356] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001b9a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001b9e: f423 7240 bic.w r2, r3, #768 ; 0x300
+ 8001ba2: 687b ldr r3, [r7, #4]
+ 8001ba4: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8001ba6: 4956 ldr r1, [pc, #344] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001ba8: 4313 orrs r3, r2
+ 8001baa: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
- 8001b0a: 687b ldr r3, [r7, #4]
- 8001b0c: 681b ldr r3, [r3, #0]
- 8001b0e: f403 6300 and.w r3, r3, #2048 ; 0x800
- 8001b12: 2b00 cmp r3, #0
- 8001b14: d00a beq.n 8001b2c <HAL_RCCEx_PeriphCLKConfig+0x37c>
+ 8001bae: 687b ldr r3, [r7, #4]
+ 8001bb0: 681b ldr r3, [r3, #0]
+ 8001bb2: f403 6300 and.w r3, r3, #2048 ; 0x800
+ 8001bb6: 2b00 cmp r3, #0
+ 8001bb8: d00a beq.n 8001bd0 <HAL_RCCEx_PeriphCLKConfig+0x37c>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
- 8001b16: 4b51 ldr r3, [pc, #324] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b18: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001b1c: f423 6240 bic.w r2, r3, #3072 ; 0xc00
- 8001b20: 687b ldr r3, [r7, #4]
- 8001b22: 6d9b ldr r3, [r3, #88] ; 0x58
- 8001b24: 494d ldr r1, [pc, #308] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b26: 4313 orrs r3, r2
- 8001b28: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001bba: 4b51 ldr r3, [pc, #324] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bbc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001bc0: f423 6240 bic.w r2, r3, #3072 ; 0xc00
+ 8001bc4: 687b ldr r3, [r7, #4]
+ 8001bc6: 6d9b ldr r3, [r3, #88] ; 0x58
+ 8001bc8: 494d ldr r1, [pc, #308] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bca: 4313 orrs r3, r2
+ 8001bcc: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
- 8001b2c: 687b ldr r3, [r7, #4]
- 8001b2e: 681b ldr r3, [r3, #0]
- 8001b30: f403 5380 and.w r3, r3, #4096 ; 0x1000
- 8001b34: 2b00 cmp r3, #0
- 8001b36: d00a beq.n 8001b4e <HAL_RCCEx_PeriphCLKConfig+0x39e>
+ 8001bd0: 687b ldr r3, [r7, #4]
+ 8001bd2: 681b ldr r3, [r3, #0]
+ 8001bd4: f403 5380 and.w r3, r3, #4096 ; 0x1000
+ 8001bd8: 2b00 cmp r3, #0
+ 8001bda: d00a beq.n 8001bf2 <HAL_RCCEx_PeriphCLKConfig+0x39e>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
- 8001b38: 4b48 ldr r3, [pc, #288] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b3a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001b3e: f423 5240 bic.w r2, r3, #12288 ; 0x3000
- 8001b42: 687b ldr r3, [r7, #4]
- 8001b44: 6ddb ldr r3, [r3, #92] ; 0x5c
- 8001b46: 4945 ldr r1, [pc, #276] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b48: 4313 orrs r3, r2
- 8001b4a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001bdc: 4b48 ldr r3, [pc, #288] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bde: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001be2: f423 5240 bic.w r2, r3, #12288 ; 0x3000
+ 8001be6: 687b ldr r3, [r7, #4]
+ 8001be8: 6ddb ldr r3, [r3, #92] ; 0x5c
+ 8001bea: 4945 ldr r1, [pc, #276] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001bec: 4313 orrs r3, r2
+ 8001bee: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
- 8001b4e: 687b ldr r3, [r7, #4]
- 8001b50: 681b ldr r3, [r3, #0]
- 8001b52: f403 5300 and.w r3, r3, #8192 ; 0x2000
- 8001b56: 2b00 cmp r3, #0
- 8001b58: d00a beq.n 8001b70 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
+ 8001bf2: 687b ldr r3, [r7, #4]
+ 8001bf4: 681b ldr r3, [r3, #0]
+ 8001bf6: f403 5300 and.w r3, r3, #8192 ; 0x2000
+ 8001bfa: 2b00 cmp r3, #0
+ 8001bfc: d00a beq.n 8001c14 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
- 8001b5a: 4b40 ldr r3, [pc, #256] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b5c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001b60: f423 4240 bic.w r2, r3, #49152 ; 0xc000
- 8001b64: 687b ldr r3, [r7, #4]
- 8001b66: 6e1b ldr r3, [r3, #96] ; 0x60
- 8001b68: 493c ldr r1, [pc, #240] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b6a: 4313 orrs r3, r2
- 8001b6c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001bfe: 4b40 ldr r3, [pc, #256] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c00: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c04: f423 4240 bic.w r2, r3, #49152 ; 0xc000
+ 8001c08: 687b ldr r3, [r7, #4]
+ 8001c0a: 6e1b ldr r3, [r3, #96] ; 0x60
+ 8001c0c: 493c ldr r1, [pc, #240] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c0e: 4313 orrs r3, r2
+ 8001c10: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*--------------------------------------- CEC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
- 8001b70: 687b ldr r3, [r7, #4]
- 8001b72: 681b ldr r3, [r3, #0]
- 8001b74: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8001b78: 2b00 cmp r3, #0
- 8001b7a: d00a beq.n 8001b92 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
+ 8001c14: 687b ldr r3, [r7, #4]
+ 8001c16: 681b ldr r3, [r3, #0]
+ 8001c18: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8001c1c: 2b00 cmp r3, #0
+ 8001c1e: d00a beq.n 8001c36 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
- 8001b7c: 4b37 ldr r3, [pc, #220] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b7e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001b82: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8001b86: 687b ldr r3, [r7, #4]
- 8001b88: 6f9b ldr r3, [r3, #120] ; 0x78
- 8001b8a: 4934 ldr r1, [pc, #208] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001b8c: 4313 orrs r3, r2
- 8001b8e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001c20: 4b37 ldr r3, [pc, #220] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c22: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c26: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
+ 8001c2a: 687b ldr r3, [r7, #4]
+ 8001c2c: 6f9b ldr r3, [r3, #120] ; 0x78
+ 8001c2e: 4934 ldr r1, [pc, #208] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c30: 4313 orrs r3, r2
+ 8001c32: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
- 8001b92: 687b ldr r3, [r7, #4]
- 8001b94: 681b ldr r3, [r3, #0]
- 8001b96: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8001b9a: 2b00 cmp r3, #0
- 8001b9c: d011 beq.n 8001bc2 <HAL_RCCEx_PeriphCLKConfig+0x412>
+ 8001c36: 687b ldr r3, [r7, #4]
+ 8001c38: 681b ldr r3, [r3, #0]
+ 8001c3a: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8001c3e: 2b00 cmp r3, #0
+ 8001c40: d011 beq.n 8001c66 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- 8001b9e: 4b2f ldr r3, [pc, #188] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001ba0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001ba4: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
- 8001ba8: 687b ldr r3, [r7, #4]
- 8001baa: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8001bac: 492b ldr r1, [pc, #172] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bae: 4313 orrs r3, r2
- 8001bb0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001c42: 4b2f ldr r3, [pc, #188] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c44: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c48: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
+ 8001c4c: 687b ldr r3, [r7, #4]
+ 8001c4e: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8001c50: 492b ldr r1, [pc, #172] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c52: 4313 orrs r3, r2
+ 8001c54: f8c1 3090 str.w r3, [r1, #144] ; 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
- 8001bb4: 687b ldr r3, [r7, #4]
- 8001bb6: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8001bb8: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8001bbc: d101 bne.n 8001bc2 <HAL_RCCEx_PeriphCLKConfig+0x412>
+ 8001c58: 687b ldr r3, [r7, #4]
+ 8001c5a: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8001c5c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
+ 8001c60: d101 bne.n 8001c66 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
pllsaiused = 1;
- 8001bbe: 2301 movs r3, #1
- 8001bc0: 61bb str r3, [r7, #24]
+ 8001c62: 2301 movs r3, #1
+ 8001c64: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
- 8001bc2: 687b ldr r3, [r7, #4]
- 8001bc4: 681b ldr r3, [r3, #0]
- 8001bc6: f003 0308 and.w r3, r3, #8
- 8001bca: 2b00 cmp r3, #0
- 8001bcc: d001 beq.n 8001bd2 <HAL_RCCEx_PeriphCLKConfig+0x422>
+ 8001c66: 687b ldr r3, [r7, #4]
+ 8001c68: 681b ldr r3, [r3, #0]
+ 8001c6a: f003 0308 and.w r3, r3, #8
+ 8001c6e: 2b00 cmp r3, #0
+ 8001c70: d001 beq.n 8001c76 <HAL_RCCEx_PeriphCLKConfig+0x422>
{
pllsaiused = 1;
- 8001bce: 2301 movs r3, #1
- 8001bd0: 61bb str r3, [r7, #24]
+ 8001c72: 2301 movs r3, #1
+ 8001c74: 61bb str r3, [r7, #24]
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
- 8001bd2: 687b ldr r3, [r7, #4]
- 8001bd4: 681b ldr r3, [r3, #0]
- 8001bd6: f403 2380 and.w r3, r3, #262144 ; 0x40000
- 8001bda: 2b00 cmp r3, #0
- 8001bdc: d00a beq.n 8001bf4 <HAL_RCCEx_PeriphCLKConfig+0x444>
+ 8001c76: 687b ldr r3, [r7, #4]
+ 8001c78: 681b ldr r3, [r3, #0]
+ 8001c7a: f403 2380 and.w r3, r3, #262144 ; 0x40000
+ 8001c7e: 2b00 cmp r3, #0
+ 8001c80: d00a beq.n 8001c98 <HAL_RCCEx_PeriphCLKConfig+0x444>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
- 8001bde: 4b1f ldr r3, [pc, #124] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001be0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001be4: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
- 8001be8: 687b ldr r3, [r7, #4]
- 8001bea: 6f5b ldr r3, [r3, #116] ; 0x74
- 8001bec: 491b ldr r1, [pc, #108] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001bee: 4313 orrs r3, r2
- 8001bf0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001c82: 4b1f ldr r3, [pc, #124] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001c88: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
+ 8001c8c: 687b ldr r3, [r7, #4]
+ 8001c8e: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8001c90: 491b ldr r1, [pc, #108] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001c92: 4313 orrs r3, r2
+ 8001c94: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
- 8001bf4: 687b ldr r3, [r7, #4]
- 8001bf6: 681b ldr r3, [r3, #0]
- 8001bf8: f403 0300 and.w r3, r3, #8388608 ; 0x800000
- 8001bfc: 2b00 cmp r3, #0
- 8001bfe: d00b beq.n 8001c18 <HAL_RCCEx_PeriphCLKConfig+0x468>
+ 8001c98: 687b ldr r3, [r7, #4]
+ 8001c9a: 681b ldr r3, [r3, #0]
+ 8001c9c: f403 0300 and.w r3, r3, #8388608 ; 0x800000
+ 8001ca0: 2b00 cmp r3, #0
+ 8001ca2: d00b beq.n 8001cbc <HAL_RCCEx_PeriphCLKConfig+0x468>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
- 8001c00: 4b16 ldr r3, [pc, #88] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c02: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001c06: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
- 8001c0a: 687b ldr r3, [r7, #4]
- 8001c0c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
- 8001c10: 4912 ldr r1, [pc, #72] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c12: 4313 orrs r3, r2
- 8001c14: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001ca4: 4b16 ldr r3, [pc, #88] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001ca6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001caa: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
+ 8001cae: 687b ldr r3, [r7, #4]
+ 8001cb0: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
+ 8001cb4: 4912 ldr r1, [pc, #72] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cb6: 4313 orrs r3, r2
+ 8001cb8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
- 8001c18: 687b ldr r3, [r7, #4]
- 8001c1a: 681b ldr r3, [r3, #0]
- 8001c1c: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
- 8001c20: 2b00 cmp r3, #0
- 8001c22: d00b beq.n 8001c3c <HAL_RCCEx_PeriphCLKConfig+0x48c>
+ 8001cbc: 687b ldr r3, [r7, #4]
+ 8001cbe: 681b ldr r3, [r3, #0]
+ 8001cc0: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
+ 8001cc4: 2b00 cmp r3, #0
+ 8001cc6: d00b beq.n 8001ce0 <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
- 8001c24: 4b0d ldr r3, [pc, #52] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c26: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8001c2a: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
- 8001c2e: 687b ldr r3, [r7, #4]
- 8001c30: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001c34: 4909 ldr r1, [pc, #36] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c36: 4313 orrs r3, r2
- 8001c38: f8c1 3090 str.w r3, [r1, #144] ; 0x90
+ 8001cc8: 4b0d ldr r3, [pc, #52] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cca: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8001cce: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000
+ 8001cd2: 687b ldr r3, [r7, #4]
+ 8001cd4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001cd8: 4909 ldr r1, [pc, #36] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cda: 4313 orrs r3, r2
+ 8001cdc: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- DFSDM1 Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
- 8001c3c: 687b ldr r3, [r7, #4]
- 8001c3e: 681b ldr r3, [r3, #0]
- 8001c40: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8001c44: 2b00 cmp r3, #0
- 8001c46: d00f beq.n 8001c68 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
+ 8001ce0: 687b ldr r3, [r7, #4]
+ 8001ce2: 681b ldr r3, [r3, #0]
+ 8001ce4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8001ce8: 2b00 cmp r3, #0
+ 8001cea: d00f beq.n 8001d0c <HAL_RCCEx_PeriphCLKConfig+0x4b8>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
- 8001c48: 4b04 ldr r3, [pc, #16] ; (8001c5c <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
- 8001c4a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001c4e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
- 8001c52: 687b ldr r3, [r7, #4]
- 8001c54: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001c58: e002 b.n 8001c60 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
- 8001c5a: bf00 nop
- 8001c5c: 40023800 .word 0x40023800
- 8001c60: 4985 ldr r1, [pc, #532] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001c62: 4313 orrs r3, r2
- 8001c64: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8001cec: 4b04 ldr r3, [pc, #16] ; (8001d00 <HAL_RCCEx_PeriphCLKConfig+0x4ac>)
+ 8001cee: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001cf2: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
+ 8001cf6: 687b ldr r3, [r7, #4]
+ 8001cf8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001cfc: e002 b.n 8001d04 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
+ 8001cfe: bf00 nop
+ 8001d00: 40023800 .word 0x40023800
+ 8001d04: 4985 ldr r1, [pc, #532] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d06: 4313 orrs r3, r2
+ 8001d08: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
- 8001c68: 687b ldr r3, [r7, #4]
- 8001c6a: 681b ldr r3, [r3, #0]
- 8001c6c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001c70: 2b00 cmp r3, #0
- 8001c72: d00b beq.n 8001c8c <HAL_RCCEx_PeriphCLKConfig+0x4dc>
+ 8001d0c: 687b ldr r3, [r7, #4]
+ 8001d0e: 681b ldr r3, [r3, #0]
+ 8001d10: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001d14: 2b00 cmp r3, #0
+ 8001d16: d00b beq.n 8001d30 <HAL_RCCEx_PeriphCLKConfig+0x4dc>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
/* Configure the DFSDM interface clock source */
__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
- 8001c74: 4b80 ldr r3, [pc, #512] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001c76: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001c7a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
- 8001c7e: 687b ldr r3, [r7, #4]
- 8001c80: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001c84: 497c ldr r1, [pc, #496] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001c86: 4313 orrs r3, r2
- 8001c88: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8001d18: 4b80 ldr r3, [pc, #512] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d1a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001d1e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
+ 8001d22: 687b ldr r3, [r7, #4]
+ 8001d24: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001d28: 497c ldr r1, [pc, #496] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d2a: 4313 orrs r3, r2
+ 8001d2c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
- 8001c8c: 69fb ldr r3, [r7, #28]
- 8001c8e: 2b01 cmp r3, #1
- 8001c90: d005 beq.n 8001c9e <HAL_RCCEx_PeriphCLKConfig+0x4ee>
- 8001c92: 687b ldr r3, [r7, #4]
- 8001c94: 681b ldr r3, [r3, #0]
- 8001c96: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
- 8001c9a: f040 80d6 bne.w 8001e4a <HAL_RCCEx_PeriphCLKConfig+0x69a>
+ 8001d30: 69fb ldr r3, [r7, #28]
+ 8001d32: 2b01 cmp r3, #1
+ 8001d34: d005 beq.n 8001d42 <HAL_RCCEx_PeriphCLKConfig+0x4ee>
+ 8001d36: 687b ldr r3, [r7, #4]
+ 8001d38: 681b ldr r3, [r3, #0]
+ 8001d3a: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
+ 8001d3e: f040 80d6 bne.w 8001eee <HAL_RCCEx_PeriphCLKConfig+0x69a>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
- 8001c9e: 4b76 ldr r3, [pc, #472] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ca0: 681b ldr r3, [r3, #0]
- 8001ca2: 4a75 ldr r2, [pc, #468] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ca4: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
- 8001ca8: 6013 str r3, [r2, #0]
+ 8001d42: 4b76 ldr r3, [pc, #472] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d44: 681b ldr r3, [r3, #0]
+ 8001d46: 4a75 ldr r2, [pc, #468] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d48: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
+ 8001d4c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001caa: f7fe fe83 bl 80009b4 <HAL_GetTick>
- 8001cae: 6178 str r0, [r7, #20]
+ 8001d4e: f7fe fe83 bl 8000a58 <HAL_GetTick>
+ 8001d52: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8001cb0: e008 b.n 8001cc4 <HAL_RCCEx_PeriphCLKConfig+0x514>
+ 8001d54: e008 b.n 8001d68 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8001cb2: f7fe fe7f bl 80009b4 <HAL_GetTick>
- 8001cb6: 4602 mov r2, r0
- 8001cb8: 697b ldr r3, [r7, #20]
- 8001cba: 1ad3 subs r3, r2, r3
- 8001cbc: 2b64 cmp r3, #100 ; 0x64
- 8001cbe: d901 bls.n 8001cc4 <HAL_RCCEx_PeriphCLKConfig+0x514>
+ 8001d56: f7fe fe7f bl 8000a58 <HAL_GetTick>
+ 8001d5a: 4602 mov r2, r0
+ 8001d5c: 697b ldr r3, [r7, #20]
+ 8001d5e: 1ad3 subs r3, r2, r3
+ 8001d60: 2b64 cmp r3, #100 ; 0x64
+ 8001d62: d901 bls.n 8001d68 <HAL_RCCEx_PeriphCLKConfig+0x514>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 8001cc0: 2303 movs r3, #3
- 8001cc2: e194 b.n 8001fee <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8001d64: 2303 movs r3, #3
+ 8001d66: e194 b.n 8002092 <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
- 8001cc4: 4b6c ldr r3, [pc, #432] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001cc6: 681b ldr r3, [r3, #0]
- 8001cc8: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8001ccc: 2b00 cmp r3, #0
- 8001cce: d1f0 bne.n 8001cb2 <HAL_RCCEx_PeriphCLKConfig+0x502>
+ 8001d68: 4b6c ldr r3, [pc, #432] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d6a: 681b ldr r3, [r3, #0]
+ 8001d6c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8001d70: 2b00 cmp r3, #0
+ 8001d72: d1f0 bne.n 8001d56 <HAL_RCCEx_PeriphCLKConfig+0x502>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
- 8001cd0: 687b ldr r3, [r7, #4]
- 8001cd2: 681b ldr r3, [r3, #0]
- 8001cd4: f003 0301 and.w r3, r3, #1
- 8001cd8: 2b00 cmp r3, #0
- 8001cda: d021 beq.n 8001d20 <HAL_RCCEx_PeriphCLKConfig+0x570>
- 8001cdc: 687b ldr r3, [r7, #4]
- 8001cde: 6b5b ldr r3, [r3, #52] ; 0x34
- 8001ce0: 2b00 cmp r3, #0
- 8001ce2: d11d bne.n 8001d20 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ 8001d74: 687b ldr r3, [r7, #4]
+ 8001d76: 681b ldr r3, [r3, #0]
+ 8001d78: f003 0301 and.w r3, r3, #1
+ 8001d7c: 2b00 cmp r3, #0
+ 8001d7e: d021 beq.n 8001dc4 <HAL_RCCEx_PeriphCLKConfig+0x570>
+ 8001d80: 687b ldr r3, [r7, #4]
+ 8001d82: 6b5b ldr r3, [r3, #52] ; 0x34
+ 8001d84: 2b00 cmp r3, #0
+ 8001d86: d11d bne.n 8001dc4 <HAL_RCCEx_PeriphCLKConfig+0x570>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8001ce4: 4b64 ldr r3, [pc, #400] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001ce6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001cea: 0c1b lsrs r3, r3, #16
- 8001cec: f003 0303 and.w r3, r3, #3
- 8001cf0: 613b str r3, [r7, #16]
+ 8001d88: 4b64 ldr r3, [pc, #400] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d8a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001d8e: 0c1b lsrs r3, r3, #16
+ 8001d90: f003 0303 and.w r3, r3, #3
+ 8001d94: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8001cf2: 4b61 ldr r3, [pc, #388] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001cf4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001cf8: 0e1b lsrs r3, r3, #24
- 8001cfa: f003 030f and.w r3, r3, #15
- 8001cfe: 60fb str r3, [r7, #12]
+ 8001d96: 4b61 ldr r3, [pc, #388] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001d98: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001d9c: 0e1b lsrs r3, r3, #24
+ 8001d9e: f003 030f and.w r3, r3, #15
+ 8001da2: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
- 8001d00: 687b ldr r3, [r7, #4]
- 8001d02: 685b ldr r3, [r3, #4]
- 8001d04: 019a lsls r2, r3, #6
- 8001d06: 693b ldr r3, [r7, #16]
- 8001d08: 041b lsls r3, r3, #16
- 8001d0a: 431a orrs r2, r3
- 8001d0c: 68fb ldr r3, [r7, #12]
- 8001d0e: 061b lsls r3, r3, #24
- 8001d10: 431a orrs r2, r3
- 8001d12: 687b ldr r3, [r7, #4]
- 8001d14: 689b ldr r3, [r3, #8]
- 8001d16: 071b lsls r3, r3, #28
- 8001d18: 4957 ldr r1, [pc, #348] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001d1a: 4313 orrs r3, r2
- 8001d1c: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8001da4: 687b ldr r3, [r7, #4]
+ 8001da6: 685b ldr r3, [r3, #4]
+ 8001da8: 019a lsls r2, r3, #6
+ 8001daa: 693b ldr r3, [r7, #16]
+ 8001dac: 041b lsls r3, r3, #16
+ 8001dae: 431a orrs r2, r3
+ 8001db0: 68fb ldr r3, [r7, #12]
+ 8001db2: 061b lsls r3, r3, #24
+ 8001db4: 431a orrs r2, r3
+ 8001db6: 687b ldr r3, [r7, #4]
+ 8001db8: 689b ldr r3, [r3, #8]
+ 8001dba: 071b lsls r3, r3, #28
+ 8001dbc: 4957 ldr r1, [pc, #348] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001dbe: 4313 orrs r3, r2
+ 8001dc0: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8001d20: 687b ldr r3, [r7, #4]
- 8001d22: 681b ldr r3, [r3, #0]
- 8001d24: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8001d28: 2b00 cmp r3, #0
- 8001d2a: d004 beq.n 8001d36 <HAL_RCCEx_PeriphCLKConfig+0x586>
- 8001d2c: 687b ldr r3, [r7, #4]
- 8001d2e: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001d30: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8001d34: d00a beq.n 8001d4c <HAL_RCCEx_PeriphCLKConfig+0x59c>
+ 8001dc4: 687b ldr r3, [r7, #4]
+ 8001dc6: 681b ldr r3, [r3, #0]
+ 8001dc8: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 8001dcc: 2b00 cmp r3, #0
+ 8001dce: d004 beq.n 8001dda <HAL_RCCEx_PeriphCLKConfig+0x586>
+ 8001dd0: 687b ldr r3, [r7, #4]
+ 8001dd2: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 8001dd4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 8001dd8: d00a beq.n 8001df0 <HAL_RCCEx_PeriphCLKConfig+0x59c>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8001d36: 687b ldr r3, [r7, #4]
- 8001d38: 681b ldr r3, [r3, #0]
- 8001d3a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8001dda: 687b ldr r3, [r7, #4]
+ 8001ddc: 681b ldr r3, [r3, #0]
+ 8001dde: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- 8001d3e: 2b00 cmp r3, #0
- 8001d40: d02e beq.n 8001da0 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ 8001de2: 2b00 cmp r3, #0
+ 8001de4: d02e beq.n 8001e44 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
- 8001d42: 687b ldr r3, [r7, #4]
- 8001d44: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001d46: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8001d4a: d129 bne.n 8001da0 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
+ 8001de6: 687b ldr r3, [r7, #4]
+ 8001de8: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001dea: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8001dee: d129 bne.n 8001e44 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
- 8001d4c: 4b4a ldr r3, [pc, #296] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001d4e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001d52: 0c1b lsrs r3, r3, #16
- 8001d54: f003 0303 and.w r3, r3, #3
- 8001d58: 613b str r3, [r7, #16]
+ 8001df0: 4b4a ldr r3, [pc, #296] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001df2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001df6: 0c1b lsrs r3, r3, #16
+ 8001df8: f003 0303 and.w r3, r3, #3
+ 8001dfc: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8001d5a: 4b47 ldr r3, [pc, #284] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001d5c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001d60: 0f1b lsrs r3, r3, #28
- 8001d62: f003 0307 and.w r3, r3, #7
- 8001d66: 60fb str r3, [r7, #12]
+ 8001dfe: 4b47 ldr r3, [pc, #284] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e00: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001e04: 0f1b lsrs r3, r3, #28
+ 8001e06: f003 0307 and.w r3, r3, #7
+ 8001e0a: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
- 8001d68: 687b ldr r3, [r7, #4]
- 8001d6a: 685b ldr r3, [r3, #4]
- 8001d6c: 019a lsls r2, r3, #6
- 8001d6e: 693b ldr r3, [r7, #16]
- 8001d70: 041b lsls r3, r3, #16
- 8001d72: 431a orrs r2, r3
- 8001d74: 687b ldr r3, [r7, #4]
- 8001d76: 68db ldr r3, [r3, #12]
- 8001d78: 061b lsls r3, r3, #24
- 8001d7a: 431a orrs r2, r3
- 8001d7c: 68fb ldr r3, [r7, #12]
- 8001d7e: 071b lsls r3, r3, #28
- 8001d80: 493d ldr r1, [pc, #244] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001d82: 4313 orrs r3, r2
- 8001d84: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8001e0c: 687b ldr r3, [r7, #4]
+ 8001e0e: 685b ldr r3, [r3, #4]
+ 8001e10: 019a lsls r2, r3, #6
+ 8001e12: 693b ldr r3, [r7, #16]
+ 8001e14: 041b lsls r3, r3, #16
+ 8001e16: 431a orrs r2, r3
+ 8001e18: 687b ldr r3, [r7, #4]
+ 8001e1a: 68db ldr r3, [r3, #12]
+ 8001e1c: 061b lsls r3, r3, #24
+ 8001e1e: 431a orrs r2, r3
+ 8001e20: 68fb ldr r3, [r7, #12]
+ 8001e22: 071b lsls r3, r3, #28
+ 8001e24: 493d ldr r1, [pc, #244] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e26: 4313 orrs r3, r2
+ 8001e28: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- 8001d88: 4b3b ldr r3, [pc, #236] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001d8a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001d8e: f023 021f bic.w r2, r3, #31
- 8001d92: 687b ldr r3, [r7, #4]
- 8001d94: 6a5b ldr r3, [r3, #36] ; 0x24
- 8001d96: 3b01 subs r3, #1
- 8001d98: 4937 ldr r1, [pc, #220] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001d9a: 4313 orrs r3, r2
- 8001d9c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8001e2c: 4b3b ldr r3, [pc, #236] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e2e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001e32: f023 021f bic.w r2, r3, #31
+ 8001e36: 687b ldr r3, [r7, #4]
+ 8001e38: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001e3a: 3b01 subs r3, #1
+ 8001e3c: 4937 ldr r1, [pc, #220] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e3e: 4313 orrs r3, r2
+ 8001e40: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
- 8001da0: 687b ldr r3, [r7, #4]
- 8001da2: 681b ldr r3, [r3, #0]
- 8001da4: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
- 8001da8: 2b00 cmp r3, #0
- 8001daa: d01d beq.n 8001de8 <HAL_RCCEx_PeriphCLKConfig+0x638>
+ 8001e44: 687b ldr r3, [r7, #4]
+ 8001e46: 681b ldr r3, [r3, #0]
+ 8001e48: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
+ 8001e4c: 2b00 cmp r3, #0
+ 8001e4e: d01d beq.n 8001e8c <HAL_RCCEx_PeriphCLKConfig+0x638>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
- 8001dac: 4b32 ldr r3, [pc, #200] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001dae: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001db2: 0e1b lsrs r3, r3, #24
- 8001db4: f003 030f and.w r3, r3, #15
- 8001db8: 613b str r3, [r7, #16]
+ 8001e50: 4b32 ldr r3, [pc, #200] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e52: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001e56: 0e1b lsrs r3, r3, #24
+ 8001e58: f003 030f and.w r3, r3, #15
+ 8001e5c: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
- 8001dba: 4b2f ldr r3, [pc, #188] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001dbc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
- 8001dc0: 0f1b lsrs r3, r3, #28
- 8001dc2: f003 0307 and.w r3, r3, #7
- 8001dc6: 60fb str r3, [r7, #12]
+ 8001e5e: 4b2f ldr r3, [pc, #188] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e60: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
+ 8001e64: 0f1b lsrs r3, r3, #28
+ 8001e66: f003 0307 and.w r3, r3, #7
+ 8001e6a: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
- 8001dc8: 687b ldr r3, [r7, #4]
- 8001dca: 685b ldr r3, [r3, #4]
- 8001dcc: 019a lsls r2, r3, #6
- 8001dce: 687b ldr r3, [r7, #4]
- 8001dd0: 691b ldr r3, [r3, #16]
- 8001dd2: 041b lsls r3, r3, #16
- 8001dd4: 431a orrs r2, r3
- 8001dd6: 693b ldr r3, [r7, #16]
- 8001dd8: 061b lsls r3, r3, #24
- 8001dda: 431a orrs r2, r3
- 8001ddc: 68fb ldr r3, [r7, #12]
- 8001dde: 071b lsls r3, r3, #28
- 8001de0: 4925 ldr r1, [pc, #148] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001de2: 4313 orrs r3, r2
- 8001de4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8001e6c: 687b ldr r3, [r7, #4]
+ 8001e6e: 685b ldr r3, [r3, #4]
+ 8001e70: 019a lsls r2, r3, #6
+ 8001e72: 687b ldr r3, [r7, #4]
+ 8001e74: 691b ldr r3, [r3, #16]
+ 8001e76: 041b lsls r3, r3, #16
+ 8001e78: 431a orrs r2, r3
+ 8001e7a: 693b ldr r3, [r7, #16]
+ 8001e7c: 061b lsls r3, r3, #24
+ 8001e7e: 431a orrs r2, r3
+ 8001e80: 68fb ldr r3, [r7, #12]
+ 8001e82: 071b lsls r3, r3, #28
+ 8001e84: 4925 ldr r1, [pc, #148] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001e86: 4313 orrs r3, r2
+ 8001e88: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
- 8001de8: 687b ldr r3, [r7, #4]
- 8001dea: 681b ldr r3, [r3, #0]
- 8001dec: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8001df0: 2b00 cmp r3, #0
- 8001df2: d011 beq.n 8001e18 <HAL_RCCEx_PeriphCLKConfig+0x668>
+ 8001e8c: 687b ldr r3, [r7, #4]
+ 8001e8e: 681b ldr r3, [r3, #0]
+ 8001e90: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8001e94: 2b00 cmp r3, #0
+ 8001e96: d011 beq.n 8001ebc <HAL_RCCEx_PeriphCLKConfig+0x668>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- 8001df4: 687b ldr r3, [r7, #4]
- 8001df6: 685b ldr r3, [r3, #4]
- 8001df8: 019a lsls r2, r3, #6
- 8001dfa: 687b ldr r3, [r7, #4]
- 8001dfc: 691b ldr r3, [r3, #16]
- 8001dfe: 041b lsls r3, r3, #16
- 8001e00: 431a orrs r2, r3
- 8001e02: 687b ldr r3, [r7, #4]
- 8001e04: 68db ldr r3, [r3, #12]
- 8001e06: 061b lsls r3, r3, #24
- 8001e08: 431a orrs r2, r3
- 8001e0a: 687b ldr r3, [r7, #4]
- 8001e0c: 689b ldr r3, [r3, #8]
- 8001e0e: 071b lsls r3, r3, #28
- 8001e10: 4919 ldr r1, [pc, #100] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e12: 4313 orrs r3, r2
- 8001e14: f8c1 3084 str.w r3, [r1, #132] ; 0x84
+ 8001e98: 687b ldr r3, [r7, #4]
+ 8001e9a: 685b ldr r3, [r3, #4]
+ 8001e9c: 019a lsls r2, r3, #6
+ 8001e9e: 687b ldr r3, [r7, #4]
+ 8001ea0: 691b ldr r3, [r3, #16]
+ 8001ea2: 041b lsls r3, r3, #16
+ 8001ea4: 431a orrs r2, r3
+ 8001ea6: 687b ldr r3, [r7, #4]
+ 8001ea8: 68db ldr r3, [r3, #12]
+ 8001eaa: 061b lsls r3, r3, #24
+ 8001eac: 431a orrs r2, r3
+ 8001eae: 687b ldr r3, [r7, #4]
+ 8001eb0: 689b ldr r3, [r3, #8]
+ 8001eb2: 071b lsls r3, r3, #28
+ 8001eb4: 4919 ldr r1, [pc, #100] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001eb6: 4313 orrs r3, r2
+ 8001eb8: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
- 8001e18: 4b17 ldr r3, [pc, #92] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e1a: 681b ldr r3, [r3, #0]
- 8001e1c: 4a16 ldr r2, [pc, #88] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e1e: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
- 8001e22: 6013 str r3, [r2, #0]
+ 8001ebc: 4b17 ldr r3, [pc, #92] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001ebe: 681b ldr r3, [r3, #0]
+ 8001ec0: 4a16 ldr r2, [pc, #88] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001ec2: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
+ 8001ec6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001e24: f7fe fdc6 bl 80009b4 <HAL_GetTick>
- 8001e28: 6178 str r0, [r7, #20]
+ 8001ec8: f7fe fdc6 bl 8000a58 <HAL_GetTick>
+ 8001ecc: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 8001e2a: e008 b.n 8001e3e <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ 8001ece: e008 b.n 8001ee2 <HAL_RCCEx_PeriphCLKConfig+0x68e>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
- 8001e2c: f7fe fdc2 bl 80009b4 <HAL_GetTick>
- 8001e30: 4602 mov r2, r0
- 8001e32: 697b ldr r3, [r7, #20]
- 8001e34: 1ad3 subs r3, r2, r3
- 8001e36: 2b64 cmp r3, #100 ; 0x64
- 8001e38: d901 bls.n 8001e3e <HAL_RCCEx_PeriphCLKConfig+0x68e>
+ 8001ed0: f7fe fdc2 bl 8000a58 <HAL_GetTick>
+ 8001ed4: 4602 mov r2, r0
+ 8001ed6: 697b ldr r3, [r7, #20]
+ 8001ed8: 1ad3 subs r3, r2, r3
+ 8001eda: 2b64 cmp r3, #100 ; 0x64
+ 8001edc: d901 bls.n 8001ee2 <HAL_RCCEx_PeriphCLKConfig+0x68e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 8001e3a: 2303 movs r3, #3
- 8001e3c: e0d7 b.n 8001fee <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8001ede: 2303 movs r3, #3
+ 8001ee0: e0d7 b.n 8002092 <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
- 8001e3e: 4b0e ldr r3, [pc, #56] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e40: 681b ldr r3, [r3, #0]
- 8001e42: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
- 8001e46: 2b00 cmp r3, #0
- 8001e48: d0f0 beq.n 8001e2c <HAL_RCCEx_PeriphCLKConfig+0x67c>
+ 8001ee2: 4b0e ldr r3, [pc, #56] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001ee4: 681b ldr r3, [r3, #0]
+ 8001ee6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
+ 8001eea: 2b00 cmp r3, #0
+ 8001eec: d0f0 beq.n 8001ed0 <HAL_RCCEx_PeriphCLKConfig+0x67c>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
- 8001e4a: 69bb ldr r3, [r7, #24]
- 8001e4c: 2b01 cmp r3, #1
- 8001e4e: f040 80cd bne.w 8001fec <HAL_RCCEx_PeriphCLKConfig+0x83c>
+ 8001eee: 69bb ldr r3, [r7, #24]
+ 8001ef0: 2b01 cmp r3, #1
+ 8001ef2: f040 80cd bne.w 8002090 <HAL_RCCEx_PeriphCLKConfig+0x83c>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
- 8001e52: 4b09 ldr r3, [pc, #36] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e54: 681b ldr r3, [r3, #0]
- 8001e56: 4a08 ldr r2, [pc, #32] ; (8001e78 <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
- 8001e58: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8001e5c: 6013 str r3, [r2, #0]
+ 8001ef6: 4b09 ldr r3, [pc, #36] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001ef8: 681b ldr r3, [r3, #0]
+ 8001efa: 4a08 ldr r2, [pc, #32] ; (8001f1c <HAL_RCCEx_PeriphCLKConfig+0x6c8>)
+ 8001efc: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 8001f00: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001e5e: f7fe fda9 bl 80009b4 <HAL_GetTick>
- 8001e62: 6178 str r0, [r7, #20]
+ 8001f02: f7fe fda9 bl 8000a58 <HAL_GetTick>
+ 8001f06: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8001e64: e00a b.n 8001e7c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ 8001f08: e00a b.n 8001f20 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8001e66: f7fe fda5 bl 80009b4 <HAL_GetTick>
- 8001e6a: 4602 mov r2, r0
- 8001e6c: 697b ldr r3, [r7, #20]
- 8001e6e: 1ad3 subs r3, r2, r3
- 8001e70: 2b64 cmp r3, #100 ; 0x64
- 8001e72: d903 bls.n 8001e7c <HAL_RCCEx_PeriphCLKConfig+0x6cc>
+ 8001f0a: f7fe fda5 bl 8000a58 <HAL_GetTick>
+ 8001f0e: 4602 mov r2, r0
+ 8001f10: 697b ldr r3, [r7, #20]
+ 8001f12: 1ad3 subs r3, r2, r3
+ 8001f14: 2b64 cmp r3, #100 ; 0x64
+ 8001f16: d903 bls.n 8001f20 <HAL_RCCEx_PeriphCLKConfig+0x6cc>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 8001e74: 2303 movs r3, #3
- 8001e76: e0ba b.n 8001fee <HAL_RCCEx_PeriphCLKConfig+0x83e>
- 8001e78: 40023800 .word 0x40023800
+ 8001f18: 2303 movs r3, #3
+ 8001f1a: e0ba b.n 8002092 <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 8001f1c: 40023800 .word 0x40023800
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
- 8001e7c: 4b5e ldr r3, [pc, #376] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001e7e: 681b ldr r3, [r3, #0]
- 8001e80: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8001e84: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8001e88: d0ed beq.n 8001e66 <HAL_RCCEx_PeriphCLKConfig+0x6b6>
+ 8001f20: 4b5e ldr r3, [pc, #376] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001f22: 681b ldr r3, [r3, #0]
+ 8001f24: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
+ 8001f28: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
+ 8001f2c: d0ed beq.n 8001f0a <HAL_RCCEx_PeriphCLKConfig+0x6b6>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8001e8a: 687b ldr r3, [r7, #4]
- 8001e8c: 681b ldr r3, [r3, #0]
- 8001e8e: f403 2300 and.w r3, r3, #524288 ; 0x80000
- 8001e92: 2b00 cmp r3, #0
- 8001e94: d003 beq.n 8001e9e <HAL_RCCEx_PeriphCLKConfig+0x6ee>
- 8001e96: 687b ldr r3, [r7, #4]
- 8001e98: 6bdb ldr r3, [r3, #60] ; 0x3c
- 8001e9a: 2b00 cmp r3, #0
- 8001e9c: d009 beq.n 8001eb2 <HAL_RCCEx_PeriphCLKConfig+0x702>
+ 8001f2e: 687b ldr r3, [r7, #4]
+ 8001f30: 681b ldr r3, [r3, #0]
+ 8001f32: f403 2300 and.w r3, r3, #524288 ; 0x80000
+ 8001f36: 2b00 cmp r3, #0
+ 8001f38: d003 beq.n 8001f42 <HAL_RCCEx_PeriphCLKConfig+0x6ee>
+ 8001f3a: 687b ldr r3, [r7, #4]
+ 8001f3c: 6bdb ldr r3, [r3, #60] ; 0x3c
+ 8001f3e: 2b00 cmp r3, #0
+ 8001f40: d009 beq.n 8001f56 <HAL_RCCEx_PeriphCLKConfig+0x702>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 8001e9e: 687b ldr r3, [r7, #4]
- 8001ea0: 681b ldr r3, [r3, #0]
- 8001ea2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8001f42: 687b ldr r3, [r7, #4]
+ 8001f44: 681b ldr r3, [r3, #0]
+ 8001f46: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
- 8001ea6: 2b00 cmp r3, #0
- 8001ea8: d02e beq.n 8001f08 <HAL_RCCEx_PeriphCLKConfig+0x758>
+ 8001f4a: 2b00 cmp r3, #0
+ 8001f4c: d02e beq.n 8001fac <HAL_RCCEx_PeriphCLKConfig+0x758>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
- 8001eaa: 687b ldr r3, [r7, #4]
- 8001eac: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001eae: 2b00 cmp r3, #0
- 8001eb0: d12a bne.n 8001f08 <HAL_RCCEx_PeriphCLKConfig+0x758>
+ 8001f4e: 687b ldr r3, [r7, #4]
+ 8001f50: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001f52: 2b00 cmp r3, #0
+ 8001f54: d12a bne.n 8001fac <HAL_RCCEx_PeriphCLKConfig+0x758>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8001eb2: 4b51 ldr r3, [pc, #324] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001eb4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001eb8: 0c1b lsrs r3, r3, #16
- 8001eba: f003 0303 and.w r3, r3, #3
- 8001ebe: 613b str r3, [r7, #16]
+ 8001f56: 4b51 ldr r3, [pc, #324] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001f58: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001f5c: 0c1b lsrs r3, r3, #16
+ 8001f5e: f003 0303 and.w r3, r3, #3
+ 8001f62: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8001ec0: 4b4d ldr r3, [pc, #308] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001ec2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001ec6: 0f1b lsrs r3, r3, #28
- 8001ec8: f003 0307 and.w r3, r3, #7
- 8001ecc: 60fb str r3, [r7, #12]
+ 8001f64: 4b4d ldr r3, [pc, #308] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001f66: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001f6a: 0f1b lsrs r3, r3, #28
+ 8001f6c: f003 0307 and.w r3, r3, #7
+ 8001f70: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- 8001ece: 687b ldr r3, [r7, #4]
- 8001ed0: 695b ldr r3, [r3, #20]
- 8001ed2: 019a lsls r2, r3, #6
- 8001ed4: 693b ldr r3, [r7, #16]
- 8001ed6: 041b lsls r3, r3, #16
- 8001ed8: 431a orrs r2, r3
- 8001eda: 687b ldr r3, [r7, #4]
- 8001edc: 699b ldr r3, [r3, #24]
- 8001ede: 061b lsls r3, r3, #24
- 8001ee0: 431a orrs r2, r3
- 8001ee2: 68fb ldr r3, [r7, #12]
- 8001ee4: 071b lsls r3, r3, #28
- 8001ee6: 4944 ldr r1, [pc, #272] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001ee8: 4313 orrs r3, r2
- 8001eea: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+ 8001f72: 687b ldr r3, [r7, #4]
+ 8001f74: 695b ldr r3, [r3, #20]
+ 8001f76: 019a lsls r2, r3, #6
+ 8001f78: 693b ldr r3, [r7, #16]
+ 8001f7a: 041b lsls r3, r3, #16
+ 8001f7c: 431a orrs r2, r3
+ 8001f7e: 687b ldr r3, [r7, #4]
+ 8001f80: 699b ldr r3, [r3, #24]
+ 8001f82: 061b lsls r3, r3, #24
+ 8001f84: 431a orrs r2, r3
+ 8001f86: 68fb ldr r3, [r7, #12]
+ 8001f88: 071b lsls r3, r3, #28
+ 8001f8a: 4944 ldr r1, [pc, #272] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001f8c: 4313 orrs r3, r2
+ 8001f8e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- 8001eee: 4b42 ldr r3, [pc, #264] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001ef0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001ef4: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
- 8001ef8: 687b ldr r3, [r7, #4]
- 8001efa: 6a9b ldr r3, [r3, #40] ; 0x28
- 8001efc: 3b01 subs r3, #1
- 8001efe: 021b lsls r3, r3, #8
- 8001f00: 493d ldr r1, [pc, #244] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001f02: 4313 orrs r3, r2
- 8001f04: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8001f92: 4b42 ldr r3, [pc, #264] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001f94: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 8001f98: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
+ 8001f9c: 687b ldr r3, [r7, #4]
+ 8001f9e: 6a9b ldr r3, [r3, #40] ; 0x28
+ 8001fa0: 3b01 subs r3, #1
+ 8001fa2: 021b lsls r3, r3, #8
+ 8001fa4: 493d ldr r1, [pc, #244] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001fa6: 4313 orrs r3, r2
+ 8001fa8: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
- 8001f08: 687b ldr r3, [r7, #4]
- 8001f0a: 681b ldr r3, [r3, #0]
- 8001f0c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8001f10: 2b00 cmp r3, #0
- 8001f12: d022 beq.n 8001f5a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
- 8001f14: 687b ldr r3, [r7, #4]
- 8001f16: 6fdb ldr r3, [r3, #124] ; 0x7c
- 8001f18: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
- 8001f1c: d11d bne.n 8001f5a <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ 8001fac: 687b ldr r3, [r7, #4]
+ 8001fae: 681b ldr r3, [r3, #0]
+ 8001fb0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8001fb4: 2b00 cmp r3, #0
+ 8001fb6: d022 beq.n 8001ffe <HAL_RCCEx_PeriphCLKConfig+0x7aa>
+ 8001fb8: 687b ldr r3, [r7, #4]
+ 8001fba: 6fdb ldr r3, [r3, #124] ; 0x7c
+ 8001fbc: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
+ 8001fc0: d11d bne.n 8001ffe <HAL_RCCEx_PeriphCLKConfig+0x7aa>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 8001f1e: 4b36 ldr r3, [pc, #216] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001f20: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001f24: 0e1b lsrs r3, r3, #24
- 8001f26: f003 030f and.w r3, r3, #15
- 8001f2a: 613b str r3, [r7, #16]
+ 8001fc2: 4b36 ldr r3, [pc, #216] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001fc4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001fc8: 0e1b lsrs r3, r3, #24
+ 8001fca: f003 030f and.w r3, r3, #15
+ 8001fce: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
- 8001f2c: 4b32 ldr r3, [pc, #200] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001f2e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001f32: 0f1b lsrs r3, r3, #28
- 8001f34: f003 0307 and.w r3, r3, #7
- 8001f38: 60fb str r3, [r7, #12]
+ 8001fd0: 4b32 ldr r3, [pc, #200] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001fd2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8001fd6: 0f1b lsrs r3, r3, #28
+ 8001fd8: f003 0307 and.w r3, r3, #7
+ 8001fdc: 60fb str r3, [r7, #12]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
- 8001f3a: 687b ldr r3, [r7, #4]
- 8001f3c: 695b ldr r3, [r3, #20]
- 8001f3e: 019a lsls r2, r3, #6
- 8001f40: 687b ldr r3, [r7, #4]
- 8001f42: 6a1b ldr r3, [r3, #32]
- 8001f44: 041b lsls r3, r3, #16
- 8001f46: 431a orrs r2, r3
- 8001f48: 693b ldr r3, [r7, #16]
- 8001f4a: 061b lsls r3, r3, #24
- 8001f4c: 431a orrs r2, r3
- 8001f4e: 68fb ldr r3, [r7, #12]
- 8001f50: 071b lsls r3, r3, #28
- 8001f52: 4929 ldr r1, [pc, #164] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001f54: 4313 orrs r3, r2
- 8001f56: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+ 8001fde: 687b ldr r3, [r7, #4]
+ 8001fe0: 695b ldr r3, [r3, #20]
+ 8001fe2: 019a lsls r2, r3, #6
+ 8001fe4: 687b ldr r3, [r7, #4]
+ 8001fe6: 6a1b ldr r3, [r3, #32]
+ 8001fe8: 041b lsls r3, r3, #16
+ 8001fea: 431a orrs r2, r3
+ 8001fec: 693b ldr r3, [r7, #16]
+ 8001fee: 061b lsls r3, r3, #24
+ 8001ff0: 431a orrs r2, r3
+ 8001ff2: 68fb ldr r3, [r7, #12]
+ 8001ff4: 071b lsls r3, r3, #28
+ 8001ff6: 4929 ldr r1, [pc, #164] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8001ff8: 4313 orrs r3, r2
+ 8001ffa: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
- 8001f5a: 687b ldr r3, [r7, #4]
- 8001f5c: 681b ldr r3, [r3, #0]
- 8001f5e: f003 0308 and.w r3, r3, #8
- 8001f62: 2b00 cmp r3, #0
- 8001f64: d028 beq.n 8001fb8 <HAL_RCCEx_PeriphCLKConfig+0x808>
+ 8001ffe: 687b ldr r3, [r7, #4]
+ 8002000: 681b ldr r3, [r3, #0]
+ 8002002: f003 0308 and.w r3, r3, #8
+ 8002006: 2b00 cmp r3, #0
+ 8002008: d028 beq.n 800205c <HAL_RCCEx_PeriphCLKConfig+0x808>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
- 8001f66: 4b24 ldr r3, [pc, #144] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001f68: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001f6c: 0e1b lsrs r3, r3, #24
- 8001f6e: f003 030f and.w r3, r3, #15
- 8001f72: 613b str r3, [r7, #16]
+ 800200a: 4b24 ldr r3, [pc, #144] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800200c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8002010: 0e1b lsrs r3, r3, #24
+ 8002012: f003 030f and.w r3, r3, #15
+ 8002016: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
- 8001f74: 4b20 ldr r3, [pc, #128] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001f76: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8001f7a: 0c1b lsrs r3, r3, #16
- 8001f7c: f003 0303 and.w r3, r3, #3
- 8001f80: 60fb str r3, [r7, #12]
+ 8002018: 4b20 ldr r3, [pc, #128] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800201a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 800201e: 0c1b lsrs r3, r3, #16
+ 8002020: f003 0303 and.w r3, r3, #3
+ 8002024: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
- 8001f82: 687b ldr r3, [r7, #4]
- 8001f84: 695b ldr r3, [r3, #20]
- 8001f86: 019a lsls r2, r3, #6
- 8001f88: 68fb ldr r3, [r7, #12]
- 8001f8a: 041b lsls r3, r3, #16
- 8001f8c: 431a orrs r2, r3
- 8001f8e: 693b ldr r3, [r7, #16]
- 8001f90: 061b lsls r3, r3, #24
- 8001f92: 431a orrs r2, r3
- 8001f94: 687b ldr r3, [r7, #4]
- 8001f96: 69db ldr r3, [r3, #28]
- 8001f98: 071b lsls r3, r3, #28
- 8001f9a: 4917 ldr r1, [pc, #92] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001f9c: 4313 orrs r3, r2
- 8001f9e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
+ 8002026: 687b ldr r3, [r7, #4]
+ 8002028: 695b ldr r3, [r3, #20]
+ 800202a: 019a lsls r2, r3, #6
+ 800202c: 68fb ldr r3, [r7, #12]
+ 800202e: 041b lsls r3, r3, #16
+ 8002030: 431a orrs r2, r3
+ 8002032: 693b ldr r3, [r7, #16]
+ 8002034: 061b lsls r3, r3, #24
+ 8002036: 431a orrs r2, r3
+ 8002038: 687b ldr r3, [r7, #4]
+ 800203a: 69db ldr r3, [r3, #28]
+ 800203c: 071b lsls r3, r3, #28
+ 800203e: 4917 ldr r1, [pc, #92] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002040: 4313 orrs r3, r2
+ 8002042: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- 8001fa2: 4b15 ldr r3, [pc, #84] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001fa4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
- 8001fa8: f423 3240 bic.w r2, r3, #196608 ; 0x30000
- 8001fac: 687b ldr r3, [r7, #4]
- 8001fae: 6adb ldr r3, [r3, #44] ; 0x2c
- 8001fb0: 4911 ldr r1, [pc, #68] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001fb2: 4313 orrs r3, r2
- 8001fb4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
+ 8002046: 4b15 ldr r3, [pc, #84] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002048: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
+ 800204c: f423 3240 bic.w r2, r3, #196608 ; 0x30000
+ 8002050: 687b ldr r3, [r7, #4]
+ 8002052: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8002054: 4911 ldr r1, [pc, #68] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002056: 4313 orrs r3, r2
+ 8002058: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
- 8001fb8: 4b0f ldr r3, [pc, #60] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001fba: 681b ldr r3, [r3, #0]
- 8001fbc: 4a0e ldr r2, [pc, #56] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001fbe: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8001fc2: 6013 str r3, [r2, #0]
+ 800205c: 4b0f ldr r3, [pc, #60] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 800205e: 681b ldr r3, [r3, #0]
+ 8002060: 4a0e ldr r2, [pc, #56] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002062: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8002066: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001fc4: f7fe fcf6 bl 80009b4 <HAL_GetTick>
- 8001fc8: 6178 str r0, [r7, #20]
+ 8002068: f7fe fcf6 bl 8000a58 <HAL_GetTick>
+ 800206c: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 8001fca: e008 b.n 8001fde <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ 800206e: e008 b.n 8002082 <HAL_RCCEx_PeriphCLKConfig+0x82e>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
- 8001fcc: f7fe fcf2 bl 80009b4 <HAL_GetTick>
- 8001fd0: 4602 mov r2, r0
- 8001fd2: 697b ldr r3, [r7, #20]
- 8001fd4: 1ad3 subs r3, r2, r3
- 8001fd6: 2b64 cmp r3, #100 ; 0x64
- 8001fd8: d901 bls.n 8001fde <HAL_RCCEx_PeriphCLKConfig+0x82e>
+ 8002070: f7fe fcf2 bl 8000a58 <HAL_GetTick>
+ 8002074: 4602 mov r2, r0
+ 8002076: 697b ldr r3, [r7, #20]
+ 8002078: 1ad3 subs r3, r2, r3
+ 800207a: 2b64 cmp r3, #100 ; 0x64
+ 800207c: d901 bls.n 8002082 <HAL_RCCEx_PeriphCLKConfig+0x82e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- 8001fda: 2303 movs r3, #3
- 8001fdc: e007 b.n 8001fee <HAL_RCCEx_PeriphCLKConfig+0x83e>
+ 800207e: 2303 movs r3, #3
+ 8002080: e007 b.n 8002092 <HAL_RCCEx_PeriphCLKConfig+0x83e>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
- 8001fde: 4b06 ldr r3, [pc, #24] ; (8001ff8 <HAL_RCCEx_PeriphCLKConfig+0x848>)
- 8001fe0: 681b ldr r3, [r3, #0]
- 8001fe2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
- 8001fe6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
- 8001fea: d1ef bne.n 8001fcc <HAL_RCCEx_PeriphCLKConfig+0x81c>
+ 8002082: 4b06 ldr r3, [pc, #24] ; (800209c <HAL_RCCEx_PeriphCLKConfig+0x848>)
+ 8002084: 681b ldr r3, [r3, #0]
+ 8002086: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
+ 800208a: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
+ 800208e: d1ef bne.n 8002070 <HAL_RCCEx_PeriphCLKConfig+0x81c>
}
}
}
return HAL_OK;
- 8001fec: 2300 movs r3, #0
+ 8002090: 2300 movs r3, #0
}
- 8001fee: 4618 mov r0, r3
- 8001ff0: 3720 adds r7, #32
- 8001ff2: 46bd mov sp, r7
- 8001ff4: bd80 pop {r7, pc}
- 8001ff6: bf00 nop
- 8001ff8: 40023800 .word 0x40023800
-
-08001ffc <HAL_UART_Init>:
+ 8002092: 4618 mov r0, r3
+ 8002094: 3720 adds r7, #32
+ 8002096: 46bd mov sp, r7
+ 8002098: bd80 pop {r7, pc}
+ 800209a: bf00 nop
+ 800209c: 40023800 .word 0x40023800
+
+080020a0 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
- 8001ffc: b580 push {r7, lr}
- 8001ffe: b082 sub sp, #8
- 8002000: af00 add r7, sp, #0
- 8002002: 6078 str r0, [r7, #4]
+ 80020a0: b580 push {r7, lr}
+ 80020a2: b082 sub sp, #8
+ 80020a4: af00 add r7, sp, #0
+ 80020a6: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
- 8002004: 687b ldr r3, [r7, #4]
- 8002006: 2b00 cmp r3, #0
- 8002008: d101 bne.n 800200e <HAL_UART_Init+0x12>
+ 80020a8: 687b ldr r3, [r7, #4]
+ 80020aa: 2b00 cmp r3, #0
+ 80020ac: d101 bne.n 80020b2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
- 800200a: 2301 movs r3, #1
- 800200c: e040 b.n 8002090 <HAL_UART_Init+0x94>
+ 80020ae: 2301 movs r3, #1
+ 80020b0: e040 b.n 8002134 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
- 800200e: 687b ldr r3, [r7, #4]
- 8002010: 6f5b ldr r3, [r3, #116] ; 0x74
- 8002012: 2b00 cmp r3, #0
- 8002014: d106 bne.n 8002024 <HAL_UART_Init+0x28>
+ 80020b2: 687b ldr r3, [r7, #4]
+ 80020b4: 6f5b ldr r3, [r3, #116] ; 0x74
+ 80020b6: 2b00 cmp r3, #0
+ 80020b8: d106 bne.n 80020c8 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
- 8002016: 687b ldr r3, [r7, #4]
- 8002018: 2200 movs r2, #0
- 800201a: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 80020ba: 687b ldr r3, [r7, #4]
+ 80020bc: 2200 movs r2, #0
+ 80020be: f883 2070 strb.w r2, [r3, #112] ; 0x70
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
- 800201e: 6878 ldr r0, [r7, #4]
- 8002020: f7fe fba6 bl 8000770 <HAL_UART_MspInit>
+ 80020c2: 6878 ldr r0, [r7, #4]
+ 80020c4: f7fe fb88 bl 80007d8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
- 8002024: 687b ldr r3, [r7, #4]
- 8002026: 2224 movs r2, #36 ; 0x24
- 8002028: 675a str r2, [r3, #116] ; 0x74
+ 80020c8: 687b ldr r3, [r7, #4]
+ 80020ca: 2224 movs r2, #36 ; 0x24
+ 80020cc: 675a str r2, [r3, #116] ; 0x74
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
- 800202a: 687b ldr r3, [r7, #4]
- 800202c: 681b ldr r3, [r3, #0]
- 800202e: 681a ldr r2, [r3, #0]
- 8002030: 687b ldr r3, [r7, #4]
- 8002032: 681b ldr r3, [r3, #0]
- 8002034: f022 0201 bic.w r2, r2, #1
- 8002038: 601a str r2, [r3, #0]
+ 80020ce: 687b ldr r3, [r7, #4]
+ 80020d0: 681b ldr r3, [r3, #0]
+ 80020d2: 681a ldr r2, [r3, #0]
+ 80020d4: 687b ldr r3, [r7, #4]
+ 80020d6: 681b ldr r3, [r3, #0]
+ 80020d8: f022 0201 bic.w r2, r2, #1
+ 80020dc: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
- 800203a: 6878 ldr r0, [r7, #4]
- 800203c: f000 f8be bl 80021bc <UART_SetConfig>
- 8002040: 4603 mov r3, r0
- 8002042: 2b01 cmp r3, #1
- 8002044: d101 bne.n 800204a <HAL_UART_Init+0x4e>
+ 80020de: 6878 ldr r0, [r7, #4]
+ 80020e0: f000 f8be bl 8002260 <UART_SetConfig>
+ 80020e4: 4603 mov r3, r0
+ 80020e6: 2b01 cmp r3, #1
+ 80020e8: d101 bne.n 80020ee <HAL_UART_Init+0x4e>
{
return HAL_ERROR;
- 8002046: 2301 movs r3, #1
- 8002048: e022 b.n 8002090 <HAL_UART_Init+0x94>
+ 80020ea: 2301 movs r3, #1
+ 80020ec: e022 b.n 8002134 <HAL_UART_Init+0x94>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 800204a: 687b ldr r3, [r7, #4]
- 800204c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800204e: 2b00 cmp r3, #0
- 8002050: d002 beq.n 8002058 <HAL_UART_Init+0x5c>
+ 80020ee: 687b ldr r3, [r7, #4]
+ 80020f0: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80020f2: 2b00 cmp r3, #0
+ 80020f4: d002 beq.n 80020fc <HAL_UART_Init+0x5c>
{
UART_AdvFeatureConfig(huart);
- 8002052: 6878 ldr r0, [r7, #4]
- 8002054: f000 fb56 bl 8002704 <UART_AdvFeatureConfig>
+ 80020f6: 6878 ldr r0, [r7, #4]
+ 80020f8: f000 fb56 bl 80027a8 <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8002058: 687b ldr r3, [r7, #4]
- 800205a: 681b ldr r3, [r3, #0]
- 800205c: 685a ldr r2, [r3, #4]
- 800205e: 687b ldr r3, [r7, #4]
- 8002060: 681b ldr r3, [r3, #0]
- 8002062: f422 4290 bic.w r2, r2, #18432 ; 0x4800
- 8002066: 605a str r2, [r3, #4]
+ 80020fc: 687b ldr r3, [r7, #4]
+ 80020fe: 681b ldr r3, [r3, #0]
+ 8002100: 685a ldr r2, [r3, #4]
+ 8002102: 687b ldr r3, [r7, #4]
+ 8002104: 681b ldr r3, [r3, #0]
+ 8002106: f422 4290 bic.w r2, r2, #18432 ; 0x4800
+ 800210a: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8002068: 687b ldr r3, [r7, #4]
- 800206a: 681b ldr r3, [r3, #0]
- 800206c: 689a ldr r2, [r3, #8]
- 800206e: 687b ldr r3, [r7, #4]
- 8002070: 681b ldr r3, [r3, #0]
- 8002072: f022 022a bic.w r2, r2, #42 ; 0x2a
- 8002076: 609a str r2, [r3, #8]
+ 800210c: 687b ldr r3, [r7, #4]
+ 800210e: 681b ldr r3, [r3, #0]
+ 8002110: 689a ldr r2, [r3, #8]
+ 8002112: 687b ldr r3, [r7, #4]
+ 8002114: 681b ldr r3, [r3, #0]
+ 8002116: f022 022a bic.w r2, r2, #42 ; 0x2a
+ 800211a: 609a str r2, [r3, #8]
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- 8002078: 687b ldr r3, [r7, #4]
- 800207a: 681b ldr r3, [r3, #0]
- 800207c: 681a ldr r2, [r3, #0]
- 800207e: 687b ldr r3, [r7, #4]
- 8002080: 681b ldr r3, [r3, #0]
- 8002082: f042 0201 orr.w r2, r2, #1
- 8002086: 601a str r2, [r3, #0]
+ 800211c: 687b ldr r3, [r7, #4]
+ 800211e: 681b ldr r3, [r3, #0]
+ 8002120: 681a ldr r2, [r3, #0]
+ 8002122: 687b ldr r3, [r7, #4]
+ 8002124: 681b ldr r3, [r3, #0]
+ 8002126: f042 0201 orr.w r2, r2, #1
+ 800212a: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
- 8002088: 6878 ldr r0, [r7, #4]
- 800208a: f000 fbdd bl 8002848 <UART_CheckIdleState>
- 800208e: 4603 mov r3, r0
+ 800212c: 6878 ldr r0, [r7, #4]
+ 800212e: f000 fbdd bl 80028ec <UART_CheckIdleState>
+ 8002132: 4603 mov r3, r0
}
- 8002090: 4618 mov r0, r3
- 8002092: 3708 adds r7, #8
- 8002094: 46bd mov sp, r7
- 8002096: bd80 pop {r7, pc}
+ 8002134: 4618 mov r0, r3
+ 8002136: 3708 adds r7, #8
+ 8002138: 46bd mov sp, r7
+ 800213a: bd80 pop {r7, pc}
-08002098 <HAL_UART_Transmit>:
+0800213c <HAL_UART_Transmit>:
* @param Size Amount of data to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- 8002098: b580 push {r7, lr}
- 800209a: b08a sub sp, #40 ; 0x28
- 800209c: af02 add r7, sp, #8
- 800209e: 60f8 str r0, [r7, #12]
- 80020a0: 60b9 str r1, [r7, #8]
- 80020a2: 603b str r3, [r7, #0]
- 80020a4: 4613 mov r3, r2
- 80020a6: 80fb strh r3, [r7, #6]
+ 800213c: b580 push {r7, lr}
+ 800213e: b08a sub sp, #40 ; 0x28
+ 8002140: af02 add r7, sp, #8
+ 8002142: 60f8 str r0, [r7, #12]
+ 8002144: 60b9 str r1, [r7, #8]
+ 8002146: 603b str r3, [r7, #0]
+ 8002148: 4613 mov r3, r2
+ 800214a: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
- 80020a8: 68fb ldr r3, [r7, #12]
- 80020aa: 6f5b ldr r3, [r3, #116] ; 0x74
- 80020ac: 2b20 cmp r3, #32
- 80020ae: d17f bne.n 80021b0 <HAL_UART_Transmit+0x118>
+ 800214c: 68fb ldr r3, [r7, #12]
+ 800214e: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8002150: 2b20 cmp r3, #32
+ 8002152: d17f bne.n 8002254 <HAL_UART_Transmit+0x118>
{
if ((pData == NULL) || (Size == 0U))
- 80020b0: 68bb ldr r3, [r7, #8]
- 80020b2: 2b00 cmp r3, #0
- 80020b4: d002 beq.n 80020bc <HAL_UART_Transmit+0x24>
- 80020b6: 88fb ldrh r3, [r7, #6]
- 80020b8: 2b00 cmp r3, #0
- 80020ba: d101 bne.n 80020c0 <HAL_UART_Transmit+0x28>
+ 8002154: 68bb ldr r3, [r7, #8]
+ 8002156: 2b00 cmp r3, #0
+ 8002158: d002 beq.n 8002160 <HAL_UART_Transmit+0x24>
+ 800215a: 88fb ldrh r3, [r7, #6]
+ 800215c: 2b00 cmp r3, #0
+ 800215e: d101 bne.n 8002164 <HAL_UART_Transmit+0x28>
{
return HAL_ERROR;
- 80020bc: 2301 movs r3, #1
- 80020be: e078 b.n 80021b2 <HAL_UART_Transmit+0x11a>
+ 8002160: 2301 movs r3, #1
+ 8002162: e078 b.n 8002256 <HAL_UART_Transmit+0x11a>
}
/* Process Locked */
__HAL_LOCK(huart);
- 80020c0: 68fb ldr r3, [r7, #12]
- 80020c2: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
- 80020c6: 2b01 cmp r3, #1
- 80020c8: d101 bne.n 80020ce <HAL_UART_Transmit+0x36>
- 80020ca: 2302 movs r3, #2
- 80020cc: e071 b.n 80021b2 <HAL_UART_Transmit+0x11a>
- 80020ce: 68fb ldr r3, [r7, #12]
- 80020d0: 2201 movs r2, #1
- 80020d2: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 8002164: 68fb ldr r3, [r7, #12]
+ 8002166: f893 3070 ldrb.w r3, [r3, #112] ; 0x70
+ 800216a: 2b01 cmp r3, #1
+ 800216c: d101 bne.n 8002172 <HAL_UART_Transmit+0x36>
+ 800216e: 2302 movs r3, #2
+ 8002170: e071 b.n 8002256 <HAL_UART_Transmit+0x11a>
+ 8002172: 68fb ldr r3, [r7, #12]
+ 8002174: 2201 movs r2, #1
+ 8002176: f883 2070 strb.w r2, [r3, #112] ; 0x70
huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80020d6: 68fb ldr r3, [r7, #12]
- 80020d8: 2200 movs r2, #0
- 80020da: 67da str r2, [r3, #124] ; 0x7c
+ 800217a: 68fb ldr r3, [r7, #12]
+ 800217c: 2200 movs r2, #0
+ 800217e: 67da str r2, [r3, #124] ; 0x7c
huart->gState = HAL_UART_STATE_BUSY_TX;
- 80020dc: 68fb ldr r3, [r7, #12]
- 80020de: 2221 movs r2, #33 ; 0x21
- 80020e0: 675a str r2, [r3, #116] ; 0x74
+ 8002180: 68fb ldr r3, [r7, #12]
+ 8002182: 2221 movs r2, #33 ; 0x21
+ 8002184: 675a str r2, [r3, #116] ; 0x74
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- 80020e2: f7fe fc67 bl 80009b4 <HAL_GetTick>
- 80020e6: 6178 str r0, [r7, #20]
+ 8002186: f7fe fc67 bl 8000a58 <HAL_GetTick>
+ 800218a: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
- 80020e8: 68fb ldr r3, [r7, #12]
- 80020ea: 88fa ldrh r2, [r7, #6]
- 80020ec: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
+ 800218c: 68fb ldr r3, [r7, #12]
+ 800218e: 88fa ldrh r2, [r7, #6]
+ 8002190: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
huart->TxXferCount = Size;
- 80020f0: 68fb ldr r3, [r7, #12]
- 80020f2: 88fa ldrh r2, [r7, #6]
- 80020f4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+ 8002194: 68fb ldr r3, [r7, #12]
+ 8002196: 88fa ldrh r2, [r7, #6]
+ 8002198: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 80020f8: 68fb ldr r3, [r7, #12]
- 80020fa: 689b ldr r3, [r3, #8]
- 80020fc: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8002100: d108 bne.n 8002114 <HAL_UART_Transmit+0x7c>
- 8002102: 68fb ldr r3, [r7, #12]
- 8002104: 691b ldr r3, [r3, #16]
- 8002106: 2b00 cmp r3, #0
- 8002108: d104 bne.n 8002114 <HAL_UART_Transmit+0x7c>
+ 800219c: 68fb ldr r3, [r7, #12]
+ 800219e: 689b ldr r3, [r3, #8]
+ 80021a0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 80021a4: d108 bne.n 80021b8 <HAL_UART_Transmit+0x7c>
+ 80021a6: 68fb ldr r3, [r7, #12]
+ 80021a8: 691b ldr r3, [r3, #16]
+ 80021aa: 2b00 cmp r3, #0
+ 80021ac: d104 bne.n 80021b8 <HAL_UART_Transmit+0x7c>
{
pdata8bits = NULL;
- 800210a: 2300 movs r3, #0
- 800210c: 61fb str r3, [r7, #28]
+ 80021ae: 2300 movs r3, #0
+ 80021b0: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
- 800210e: 68bb ldr r3, [r7, #8]
- 8002110: 61bb str r3, [r7, #24]
- 8002112: e003 b.n 800211c <HAL_UART_Transmit+0x84>
+ 80021b2: 68bb ldr r3, [r7, #8]
+ 80021b4: 61bb str r3, [r7, #24]
+ 80021b6: e003 b.n 80021c0 <HAL_UART_Transmit+0x84>
}
else
{
pdata8bits = pData;
- 8002114: 68bb ldr r3, [r7, #8]
- 8002116: 61fb str r3, [r7, #28]
+ 80021b8: 68bb ldr r3, [r7, #8]
+ 80021ba: 61fb str r3, [r7, #28]
pdata16bits = NULL;
- 8002118: 2300 movs r3, #0
- 800211a: 61bb str r3, [r7, #24]
+ 80021bc: 2300 movs r3, #0
+ 80021be: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
- 800211c: e02c b.n 8002178 <HAL_UART_Transmit+0xe0>
+ 80021c0: e02c b.n 800221c <HAL_UART_Transmit+0xe0>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 800211e: 683b ldr r3, [r7, #0]
- 8002120: 9300 str r3, [sp, #0]
- 8002122: 697b ldr r3, [r7, #20]
- 8002124: 2200 movs r2, #0
- 8002126: 2180 movs r1, #128 ; 0x80
- 8002128: 68f8 ldr r0, [r7, #12]
- 800212a: f000 fbbc bl 80028a6 <UART_WaitOnFlagUntilTimeout>
- 800212e: 4603 mov r3, r0
- 8002130: 2b00 cmp r3, #0
- 8002132: d001 beq.n 8002138 <HAL_UART_Transmit+0xa0>
+ 80021c2: 683b ldr r3, [r7, #0]
+ 80021c4: 9300 str r3, [sp, #0]
+ 80021c6: 697b ldr r3, [r7, #20]
+ 80021c8: 2200 movs r2, #0
+ 80021ca: 2180 movs r1, #128 ; 0x80
+ 80021cc: 68f8 ldr r0, [r7, #12]
+ 80021ce: f000 fbbc bl 800294a <UART_WaitOnFlagUntilTimeout>
+ 80021d2: 4603 mov r3, r0
+ 80021d4: 2b00 cmp r3, #0
+ 80021d6: d001 beq.n 80021dc <HAL_UART_Transmit+0xa0>
{
return HAL_TIMEOUT;
- 8002134: 2303 movs r3, #3
- 8002136: e03c b.n 80021b2 <HAL_UART_Transmit+0x11a>
+ 80021d8: 2303 movs r3, #3
+ 80021da: e03c b.n 8002256 <HAL_UART_Transmit+0x11a>
}
if (pdata8bits == NULL)
- 8002138: 69fb ldr r3, [r7, #28]
- 800213a: 2b00 cmp r3, #0
- 800213c: d10b bne.n 8002156 <HAL_UART_Transmit+0xbe>
+ 80021dc: 69fb ldr r3, [r7, #28]
+ 80021de: 2b00 cmp r3, #0
+ 80021e0: d10b bne.n 80021fa <HAL_UART_Transmit+0xbe>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 800213e: 69bb ldr r3, [r7, #24]
- 8002140: 881b ldrh r3, [r3, #0]
- 8002142: 461a mov r2, r3
- 8002144: 68fb ldr r3, [r7, #12]
- 8002146: 681b ldr r3, [r3, #0]
- 8002148: f3c2 0208 ubfx r2, r2, #0, #9
- 800214c: 629a str r2, [r3, #40] ; 0x28
+ 80021e2: 69bb ldr r3, [r7, #24]
+ 80021e4: 881b ldrh r3, [r3, #0]
+ 80021e6: 461a mov r2, r3
+ 80021e8: 68fb ldr r3, [r7, #12]
+ 80021ea: 681b ldr r3, [r3, #0]
+ 80021ec: f3c2 0208 ubfx r2, r2, #0, #9
+ 80021f0: 629a str r2, [r3, #40] ; 0x28
pdata16bits++;
- 800214e: 69bb ldr r3, [r7, #24]
- 8002150: 3302 adds r3, #2
- 8002152: 61bb str r3, [r7, #24]
- 8002154: e007 b.n 8002166 <HAL_UART_Transmit+0xce>
+ 80021f2: 69bb ldr r3, [r7, #24]
+ 80021f4: 3302 adds r3, #2
+ 80021f6: 61bb str r3, [r7, #24]
+ 80021f8: e007 b.n 800220a <HAL_UART_Transmit+0xce>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 8002156: 69fb ldr r3, [r7, #28]
- 8002158: 781a ldrb r2, [r3, #0]
- 800215a: 68fb ldr r3, [r7, #12]
- 800215c: 681b ldr r3, [r3, #0]
- 800215e: 629a str r2, [r3, #40] ; 0x28
+ 80021fa: 69fb ldr r3, [r7, #28]
+ 80021fc: 781a ldrb r2, [r3, #0]
+ 80021fe: 68fb ldr r3, [r7, #12]
+ 8002200: 681b ldr r3, [r3, #0]
+ 8002202: 629a str r2, [r3, #40] ; 0x28
pdata8bits++;
- 8002160: 69fb ldr r3, [r7, #28]
- 8002162: 3301 adds r3, #1
- 8002164: 61fb str r3, [r7, #28]
+ 8002204: 69fb ldr r3, [r7, #28]
+ 8002206: 3301 adds r3, #1
+ 8002208: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
- 8002166: 68fb ldr r3, [r7, #12]
- 8002168: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 800216c: b29b uxth r3, r3
- 800216e: 3b01 subs r3, #1
- 8002170: b29a uxth r2, r3
- 8002172: 68fb ldr r3, [r7, #12]
- 8002174: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
+ 800220a: 68fb ldr r3, [r7, #12]
+ 800220c: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
+ 8002210: b29b uxth r3, r3
+ 8002212: 3b01 subs r3, #1
+ 8002214: b29a uxth r2, r3
+ 8002216: 68fb ldr r3, [r7, #12]
+ 8002218: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
while (huart->TxXferCount > 0U)
- 8002178: 68fb ldr r3, [r7, #12]
- 800217a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
- 800217e: b29b uxth r3, r3
- 8002180: 2b00 cmp r3, #0
- 8002182: d1cc bne.n 800211e <HAL_UART_Transmit+0x86>
+ 800221c: 68fb ldr r3, [r7, #12]
+ 800221e: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
+ 8002222: b29b uxth r3, r3
+ 8002224: 2b00 cmp r3, #0
+ 8002226: d1cc bne.n 80021c2 <HAL_UART_Transmit+0x86>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 8002184: 683b ldr r3, [r7, #0]
- 8002186: 9300 str r3, [sp, #0]
- 8002188: 697b ldr r3, [r7, #20]
- 800218a: 2200 movs r2, #0
- 800218c: 2140 movs r1, #64 ; 0x40
- 800218e: 68f8 ldr r0, [r7, #12]
- 8002190: f000 fb89 bl 80028a6 <UART_WaitOnFlagUntilTimeout>
- 8002194: 4603 mov r3, r0
- 8002196: 2b00 cmp r3, #0
- 8002198: d001 beq.n 800219e <HAL_UART_Transmit+0x106>
+ 8002228: 683b ldr r3, [r7, #0]
+ 800222a: 9300 str r3, [sp, #0]
+ 800222c: 697b ldr r3, [r7, #20]
+ 800222e: 2200 movs r2, #0
+ 8002230: 2140 movs r1, #64 ; 0x40
+ 8002232: 68f8 ldr r0, [r7, #12]
+ 8002234: f000 fb89 bl 800294a <UART_WaitOnFlagUntilTimeout>
+ 8002238: 4603 mov r3, r0
+ 800223a: 2b00 cmp r3, #0
+ 800223c: d001 beq.n 8002242 <HAL_UART_Transmit+0x106>
{
return HAL_TIMEOUT;
- 800219a: 2303 movs r3, #3
- 800219c: e009 b.n 80021b2 <HAL_UART_Transmit+0x11a>
+ 800223e: 2303 movs r3, #3
+ 8002240: e009 b.n 8002256 <HAL_UART_Transmit+0x11a>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- 800219e: 68fb ldr r3, [r7, #12]
- 80021a0: 2220 movs r2, #32
- 80021a2: 675a str r2, [r3, #116] ; 0x74
+ 8002242: 68fb ldr r3, [r7, #12]
+ 8002244: 2220 movs r2, #32
+ 8002246: 675a str r2, [r3, #116] ; 0x74
/* Process Unlocked */
__HAL_UNLOCK(huart);
- 80021a4: 68fb ldr r3, [r7, #12]
- 80021a6: 2200 movs r2, #0
- 80021a8: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 8002248: 68fb ldr r3, [r7, #12]
+ 800224a: 2200 movs r2, #0
+ 800224c: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_OK;
- 80021ac: 2300 movs r3, #0
- 80021ae: e000 b.n 80021b2 <HAL_UART_Transmit+0x11a>
+ 8002250: 2300 movs r3, #0
+ 8002252: e000 b.n 8002256 <HAL_UART_Transmit+0x11a>
}
else
{
return HAL_BUSY;
- 80021b0: 2302 movs r3, #2
+ 8002254: 2302 movs r3, #2
}
}
- 80021b2: 4618 mov r0, r3
- 80021b4: 3720 adds r7, #32
- 80021b6: 46bd mov sp, r7
- 80021b8: bd80 pop {r7, pc}
+ 8002256: 4618 mov r0, r3
+ 8002258: 3720 adds r7, #32
+ 800225a: 46bd mov sp, r7
+ 800225c: bd80 pop {r7, pc}
...
-080021bc <UART_SetConfig>:
+08002260 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
- 80021bc: b580 push {r7, lr}
- 80021be: b088 sub sp, #32
- 80021c0: af00 add r7, sp, #0
- 80021c2: 6078 str r0, [r7, #4]
+ 8002260: b580 push {r7, lr}
+ 8002262: b088 sub sp, #32
+ 8002264: af00 add r7, sp, #0
+ 8002266: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv = 0x00000000U;
- 80021c4: 2300 movs r3, #0
- 80021c6: 61bb str r3, [r7, #24]
+ 8002268: 2300 movs r3, #0
+ 800226a: 61bb str r3, [r7, #24]
HAL_StatusTypeDef ret = HAL_OK;
- 80021c8: 2300 movs r3, #0
- 80021ca: 75fb strb r3, [r7, #23]
+ 800226c: 2300 movs r3, #0
+ 800226e: 75fb strb r3, [r7, #23]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 80021cc: 687b ldr r3, [r7, #4]
- 80021ce: 689a ldr r2, [r3, #8]
- 80021d0: 687b ldr r3, [r7, #4]
- 80021d2: 691b ldr r3, [r3, #16]
- 80021d4: 431a orrs r2, r3
- 80021d6: 687b ldr r3, [r7, #4]
- 80021d8: 695b ldr r3, [r3, #20]
- 80021da: 431a orrs r2, r3
- 80021dc: 687b ldr r3, [r7, #4]
- 80021de: 69db ldr r3, [r3, #28]
- 80021e0: 4313 orrs r3, r2
- 80021e2: 613b str r3, [r7, #16]
+ 8002270: 687b ldr r3, [r7, #4]
+ 8002272: 689a ldr r2, [r3, #8]
+ 8002274: 687b ldr r3, [r7, #4]
+ 8002276: 691b ldr r3, [r3, #16]
+ 8002278: 431a orrs r2, r3
+ 800227a: 687b ldr r3, [r7, #4]
+ 800227c: 695b ldr r3, [r3, #20]
+ 800227e: 431a orrs r2, r3
+ 8002280: 687b ldr r3, [r7, #4]
+ 8002282: 69db ldr r3, [r3, #28]
+ 8002284: 4313 orrs r3, r2
+ 8002286: 613b str r3, [r7, #16]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 80021e4: 687b ldr r3, [r7, #4]
- 80021e6: 681b ldr r3, [r3, #0]
- 80021e8: 681a ldr r2, [r3, #0]
- 80021ea: 4bb1 ldr r3, [pc, #708] ; (80024b0 <UART_SetConfig+0x2f4>)
- 80021ec: 4013 ands r3, r2
- 80021ee: 687a ldr r2, [r7, #4]
- 80021f0: 6812 ldr r2, [r2, #0]
- 80021f2: 6939 ldr r1, [r7, #16]
- 80021f4: 430b orrs r3, r1
- 80021f6: 6013 str r3, [r2, #0]
+ 8002288: 687b ldr r3, [r7, #4]
+ 800228a: 681b ldr r3, [r3, #0]
+ 800228c: 681a ldr r2, [r3, #0]
+ 800228e: 4bb1 ldr r3, [pc, #708] ; (8002554 <UART_SetConfig+0x2f4>)
+ 8002290: 4013 ands r3, r2
+ 8002292: 687a ldr r2, [r7, #4]
+ 8002294: 6812 ldr r2, [r2, #0]
+ 8002296: 6939 ldr r1, [r7, #16]
+ 8002298: 430b orrs r3, r1
+ 800229a: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 80021f8: 687b ldr r3, [r7, #4]
- 80021fa: 681b ldr r3, [r3, #0]
- 80021fc: 685b ldr r3, [r3, #4]
- 80021fe: f423 5140 bic.w r1, r3, #12288 ; 0x3000
- 8002202: 687b ldr r3, [r7, #4]
- 8002204: 68da ldr r2, [r3, #12]
- 8002206: 687b ldr r3, [r7, #4]
- 8002208: 681b ldr r3, [r3, #0]
- 800220a: 430a orrs r2, r1
- 800220c: 605a str r2, [r3, #4]
+ 800229c: 687b ldr r3, [r7, #4]
+ 800229e: 681b ldr r3, [r3, #0]
+ 80022a0: 685b ldr r3, [r3, #4]
+ 80022a2: f423 5140 bic.w r1, r3, #12288 ; 0x3000
+ 80022a6: 687b ldr r3, [r7, #4]
+ 80022a8: 68da ldr r2, [r3, #12]
+ 80022aa: 687b ldr r3, [r7, #4]
+ 80022ac: 681b ldr r3, [r3, #0]
+ 80022ae: 430a orrs r2, r1
+ 80022b0: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 800220e: 687b ldr r3, [r7, #4]
- 8002210: 699b ldr r3, [r3, #24]
- 8002212: 613b str r3, [r7, #16]
+ 80022b2: 687b ldr r3, [r7, #4]
+ 80022b4: 699b ldr r3, [r3, #24]
+ 80022b6: 613b str r3, [r7, #16]
tmpreg |= huart->Init.OneBitSampling;
- 8002214: 687b ldr r3, [r7, #4]
- 8002216: 6a1b ldr r3, [r3, #32]
- 8002218: 693a ldr r2, [r7, #16]
- 800221a: 4313 orrs r3, r2
- 800221c: 613b str r3, [r7, #16]
+ 80022b8: 687b ldr r3, [r7, #4]
+ 80022ba: 6a1b ldr r3, [r3, #32]
+ 80022bc: 693a ldr r2, [r7, #16]
+ 80022be: 4313 orrs r3, r2
+ 80022c0: 613b str r3, [r7, #16]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 800221e: 687b ldr r3, [r7, #4]
- 8002220: 681b ldr r3, [r3, #0]
- 8002222: 689b ldr r3, [r3, #8]
- 8002224: f423 6130 bic.w r1, r3, #2816 ; 0xb00
- 8002228: 687b ldr r3, [r7, #4]
- 800222a: 681b ldr r3, [r3, #0]
- 800222c: 693a ldr r2, [r7, #16]
- 800222e: 430a orrs r2, r1
- 8002230: 609a str r2, [r3, #8]
+ 80022c2: 687b ldr r3, [r7, #4]
+ 80022c4: 681b ldr r3, [r3, #0]
+ 80022c6: 689b ldr r3, [r3, #8]
+ 80022c8: f423 6130 bic.w r1, r3, #2816 ; 0xb00
+ 80022cc: 687b ldr r3, [r7, #4]
+ 80022ce: 681b ldr r3, [r3, #0]
+ 80022d0: 693a ldr r2, [r7, #16]
+ 80022d2: 430a orrs r2, r1
+ 80022d4: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
- 8002232: 687b ldr r3, [r7, #4]
- 8002234: 681b ldr r3, [r3, #0]
- 8002236: 4a9f ldr r2, [pc, #636] ; (80024b4 <UART_SetConfig+0x2f8>)
- 8002238: 4293 cmp r3, r2
- 800223a: d121 bne.n 8002280 <UART_SetConfig+0xc4>
- 800223c: 4b9e ldr r3, [pc, #632] ; (80024b8 <UART_SetConfig+0x2fc>)
- 800223e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002242: f003 0303 and.w r3, r3, #3
- 8002246: 2b03 cmp r3, #3
- 8002248: d816 bhi.n 8002278 <UART_SetConfig+0xbc>
- 800224a: a201 add r2, pc, #4 ; (adr r2, 8002250 <UART_SetConfig+0x94>)
- 800224c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8002250: 08002261 .word 0x08002261
- 8002254: 0800226d .word 0x0800226d
- 8002258: 08002267 .word 0x08002267
- 800225c: 08002273 .word 0x08002273
- 8002260: 2301 movs r3, #1
- 8002262: 77fb strb r3, [r7, #31]
- 8002264: e151 b.n 800250a <UART_SetConfig+0x34e>
- 8002266: 2302 movs r3, #2
- 8002268: 77fb strb r3, [r7, #31]
- 800226a: e14e b.n 800250a <UART_SetConfig+0x34e>
- 800226c: 2304 movs r3, #4
- 800226e: 77fb strb r3, [r7, #31]
- 8002270: e14b b.n 800250a <UART_SetConfig+0x34e>
- 8002272: 2308 movs r3, #8
- 8002274: 77fb strb r3, [r7, #31]
- 8002276: e148 b.n 800250a <UART_SetConfig+0x34e>
- 8002278: 2310 movs r3, #16
- 800227a: 77fb strb r3, [r7, #31]
- 800227c: bf00 nop
- 800227e: e144 b.n 800250a <UART_SetConfig+0x34e>
- 8002280: 687b ldr r3, [r7, #4]
- 8002282: 681b ldr r3, [r3, #0]
- 8002284: 4a8d ldr r2, [pc, #564] ; (80024bc <UART_SetConfig+0x300>)
- 8002286: 4293 cmp r3, r2
- 8002288: d134 bne.n 80022f4 <UART_SetConfig+0x138>
- 800228a: 4b8b ldr r3, [pc, #556] ; (80024b8 <UART_SetConfig+0x2fc>)
- 800228c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002290: f003 030c and.w r3, r3, #12
- 8002294: 2b0c cmp r3, #12
- 8002296: d829 bhi.n 80022ec <UART_SetConfig+0x130>
- 8002298: a201 add r2, pc, #4 ; (adr r2, 80022a0 <UART_SetConfig+0xe4>)
- 800229a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 800229e: bf00 nop
- 80022a0: 080022d5 .word 0x080022d5
- 80022a4: 080022ed .word 0x080022ed
- 80022a8: 080022ed .word 0x080022ed
- 80022ac: 080022ed .word 0x080022ed
- 80022b0: 080022e1 .word 0x080022e1
- 80022b4: 080022ed .word 0x080022ed
- 80022b8: 080022ed .word 0x080022ed
- 80022bc: 080022ed .word 0x080022ed
- 80022c0: 080022db .word 0x080022db
- 80022c4: 080022ed .word 0x080022ed
- 80022c8: 080022ed .word 0x080022ed
- 80022cc: 080022ed .word 0x080022ed
- 80022d0: 080022e7 .word 0x080022e7
- 80022d4: 2300 movs r3, #0
- 80022d6: 77fb strb r3, [r7, #31]
- 80022d8: e117 b.n 800250a <UART_SetConfig+0x34e>
- 80022da: 2302 movs r3, #2
- 80022dc: 77fb strb r3, [r7, #31]
- 80022de: e114 b.n 800250a <UART_SetConfig+0x34e>
- 80022e0: 2304 movs r3, #4
- 80022e2: 77fb strb r3, [r7, #31]
- 80022e4: e111 b.n 800250a <UART_SetConfig+0x34e>
- 80022e6: 2308 movs r3, #8
- 80022e8: 77fb strb r3, [r7, #31]
- 80022ea: e10e b.n 800250a <UART_SetConfig+0x34e>
- 80022ec: 2310 movs r3, #16
- 80022ee: 77fb strb r3, [r7, #31]
- 80022f0: bf00 nop
- 80022f2: e10a b.n 800250a <UART_SetConfig+0x34e>
- 80022f4: 687b ldr r3, [r7, #4]
- 80022f6: 681b ldr r3, [r3, #0]
- 80022f8: 4a71 ldr r2, [pc, #452] ; (80024c0 <UART_SetConfig+0x304>)
- 80022fa: 4293 cmp r3, r2
- 80022fc: d120 bne.n 8002340 <UART_SetConfig+0x184>
- 80022fe: 4b6e ldr r3, [pc, #440] ; (80024b8 <UART_SetConfig+0x2fc>)
- 8002300: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002304: f003 0330 and.w r3, r3, #48 ; 0x30
- 8002308: 2b10 cmp r3, #16
- 800230a: d00f beq.n 800232c <UART_SetConfig+0x170>
- 800230c: 2b10 cmp r3, #16
- 800230e: d802 bhi.n 8002316 <UART_SetConfig+0x15a>
- 8002310: 2b00 cmp r3, #0
- 8002312: d005 beq.n 8002320 <UART_SetConfig+0x164>
- 8002314: e010 b.n 8002338 <UART_SetConfig+0x17c>
- 8002316: 2b20 cmp r3, #32
- 8002318: d005 beq.n 8002326 <UART_SetConfig+0x16a>
- 800231a: 2b30 cmp r3, #48 ; 0x30
- 800231c: d009 beq.n 8002332 <UART_SetConfig+0x176>
- 800231e: e00b b.n 8002338 <UART_SetConfig+0x17c>
- 8002320: 2300 movs r3, #0
- 8002322: 77fb strb r3, [r7, #31]
- 8002324: e0f1 b.n 800250a <UART_SetConfig+0x34e>
- 8002326: 2302 movs r3, #2
- 8002328: 77fb strb r3, [r7, #31]
- 800232a: e0ee b.n 800250a <UART_SetConfig+0x34e>
- 800232c: 2304 movs r3, #4
- 800232e: 77fb strb r3, [r7, #31]
- 8002330: e0eb b.n 800250a <UART_SetConfig+0x34e>
- 8002332: 2308 movs r3, #8
- 8002334: 77fb strb r3, [r7, #31]
- 8002336: e0e8 b.n 800250a <UART_SetConfig+0x34e>
- 8002338: 2310 movs r3, #16
- 800233a: 77fb strb r3, [r7, #31]
- 800233c: bf00 nop
- 800233e: e0e4 b.n 800250a <UART_SetConfig+0x34e>
- 8002340: 687b ldr r3, [r7, #4]
- 8002342: 681b ldr r3, [r3, #0]
- 8002344: 4a5f ldr r2, [pc, #380] ; (80024c4 <UART_SetConfig+0x308>)
- 8002346: 4293 cmp r3, r2
- 8002348: d120 bne.n 800238c <UART_SetConfig+0x1d0>
- 800234a: 4b5b ldr r3, [pc, #364] ; (80024b8 <UART_SetConfig+0x2fc>)
- 800234c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002350: f003 03c0 and.w r3, r3, #192 ; 0xc0
- 8002354: 2b40 cmp r3, #64 ; 0x40
- 8002356: d00f beq.n 8002378 <UART_SetConfig+0x1bc>
- 8002358: 2b40 cmp r3, #64 ; 0x40
- 800235a: d802 bhi.n 8002362 <UART_SetConfig+0x1a6>
- 800235c: 2b00 cmp r3, #0
- 800235e: d005 beq.n 800236c <UART_SetConfig+0x1b0>
- 8002360: e010 b.n 8002384 <UART_SetConfig+0x1c8>
- 8002362: 2b80 cmp r3, #128 ; 0x80
- 8002364: d005 beq.n 8002372 <UART_SetConfig+0x1b6>
- 8002366: 2bc0 cmp r3, #192 ; 0xc0
- 8002368: d009 beq.n 800237e <UART_SetConfig+0x1c2>
- 800236a: e00b b.n 8002384 <UART_SetConfig+0x1c8>
- 800236c: 2300 movs r3, #0
- 800236e: 77fb strb r3, [r7, #31]
- 8002370: e0cb b.n 800250a <UART_SetConfig+0x34e>
- 8002372: 2302 movs r3, #2
- 8002374: 77fb strb r3, [r7, #31]
- 8002376: e0c8 b.n 800250a <UART_SetConfig+0x34e>
- 8002378: 2304 movs r3, #4
+ 80022d6: 687b ldr r3, [r7, #4]
+ 80022d8: 681b ldr r3, [r3, #0]
+ 80022da: 4a9f ldr r2, [pc, #636] ; (8002558 <UART_SetConfig+0x2f8>)
+ 80022dc: 4293 cmp r3, r2
+ 80022de: d121 bne.n 8002324 <UART_SetConfig+0xc4>
+ 80022e0: 4b9e ldr r3, [pc, #632] ; (800255c <UART_SetConfig+0x2fc>)
+ 80022e2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 80022e6: f003 0303 and.w r3, r3, #3
+ 80022ea: 2b03 cmp r3, #3
+ 80022ec: d816 bhi.n 800231c <UART_SetConfig+0xbc>
+ 80022ee: a201 add r2, pc, #4 ; (adr r2, 80022f4 <UART_SetConfig+0x94>)
+ 80022f0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80022f4: 08002305 .word 0x08002305
+ 80022f8: 08002311 .word 0x08002311
+ 80022fc: 0800230b .word 0x0800230b
+ 8002300: 08002317 .word 0x08002317
+ 8002304: 2301 movs r3, #1
+ 8002306: 77fb strb r3, [r7, #31]
+ 8002308: e151 b.n 80025ae <UART_SetConfig+0x34e>
+ 800230a: 2302 movs r3, #2
+ 800230c: 77fb strb r3, [r7, #31]
+ 800230e: e14e b.n 80025ae <UART_SetConfig+0x34e>
+ 8002310: 2304 movs r3, #4
+ 8002312: 77fb strb r3, [r7, #31]
+ 8002314: e14b b.n 80025ae <UART_SetConfig+0x34e>
+ 8002316: 2308 movs r3, #8
+ 8002318: 77fb strb r3, [r7, #31]
+ 800231a: e148 b.n 80025ae <UART_SetConfig+0x34e>
+ 800231c: 2310 movs r3, #16
+ 800231e: 77fb strb r3, [r7, #31]
+ 8002320: bf00 nop
+ 8002322: e144 b.n 80025ae <UART_SetConfig+0x34e>
+ 8002324: 687b ldr r3, [r7, #4]
+ 8002326: 681b ldr r3, [r3, #0]
+ 8002328: 4a8d ldr r2, [pc, #564] ; (8002560 <UART_SetConfig+0x300>)
+ 800232a: 4293 cmp r3, r2
+ 800232c: d134 bne.n 8002398 <UART_SetConfig+0x138>
+ 800232e: 4b8b ldr r3, [pc, #556] ; (800255c <UART_SetConfig+0x2fc>)
+ 8002330: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002334: f003 030c and.w r3, r3, #12
+ 8002338: 2b0c cmp r3, #12
+ 800233a: d829 bhi.n 8002390 <UART_SetConfig+0x130>
+ 800233c: a201 add r2, pc, #4 ; (adr r2, 8002344 <UART_SetConfig+0xe4>)
+ 800233e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 8002342: bf00 nop
+ 8002344: 08002379 .word 0x08002379
+ 8002348: 08002391 .word 0x08002391
+ 800234c: 08002391 .word 0x08002391
+ 8002350: 08002391 .word 0x08002391
+ 8002354: 08002385 .word 0x08002385
+ 8002358: 08002391 .word 0x08002391
+ 800235c: 08002391 .word 0x08002391
+ 8002360: 08002391 .word 0x08002391
+ 8002364: 0800237f .word 0x0800237f
+ 8002368: 08002391 .word 0x08002391
+ 800236c: 08002391 .word 0x08002391
+ 8002370: 08002391 .word 0x08002391
+ 8002374: 0800238b .word 0x0800238b
+ 8002378: 2300 movs r3, #0
800237a: 77fb strb r3, [r7, #31]
- 800237c: e0c5 b.n 800250a <UART_SetConfig+0x34e>
- 800237e: 2308 movs r3, #8
+ 800237c: e117 b.n 80025ae <UART_SetConfig+0x34e>
+ 800237e: 2302 movs r3, #2
8002380: 77fb strb r3, [r7, #31]
- 8002382: e0c2 b.n 800250a <UART_SetConfig+0x34e>
- 8002384: 2310 movs r3, #16
+ 8002382: e114 b.n 80025ae <UART_SetConfig+0x34e>
+ 8002384: 2304 movs r3, #4
8002386: 77fb strb r3, [r7, #31]
- 8002388: bf00 nop
- 800238a: e0be b.n 800250a <UART_SetConfig+0x34e>
- 800238c: 687b ldr r3, [r7, #4]
- 800238e: 681b ldr r3, [r3, #0]
- 8002390: 4a4d ldr r2, [pc, #308] ; (80024c8 <UART_SetConfig+0x30c>)
- 8002392: 4293 cmp r3, r2
- 8002394: d124 bne.n 80023e0 <UART_SetConfig+0x224>
- 8002396: 4b48 ldr r3, [pc, #288] ; (80024b8 <UART_SetConfig+0x2fc>)
- 8002398: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 800239c: f403 7340 and.w r3, r3, #768 ; 0x300
- 80023a0: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 80023a4: d012 beq.n 80023cc <UART_SetConfig+0x210>
- 80023a6: f5b3 7f80 cmp.w r3, #256 ; 0x100
- 80023aa: d802 bhi.n 80023b2 <UART_SetConfig+0x1f6>
- 80023ac: 2b00 cmp r3, #0
- 80023ae: d007 beq.n 80023c0 <UART_SetConfig+0x204>
- 80023b0: e012 b.n 80023d8 <UART_SetConfig+0x21c>
- 80023b2: f5b3 7f00 cmp.w r3, #512 ; 0x200
- 80023b6: d006 beq.n 80023c6 <UART_SetConfig+0x20a>
- 80023b8: f5b3 7f40 cmp.w r3, #768 ; 0x300
- 80023bc: d009 beq.n 80023d2 <UART_SetConfig+0x216>
- 80023be: e00b b.n 80023d8 <UART_SetConfig+0x21c>
- 80023c0: 2300 movs r3, #0
- 80023c2: 77fb strb r3, [r7, #31]
- 80023c4: e0a1 b.n 800250a <UART_SetConfig+0x34e>
- 80023c6: 2302 movs r3, #2
- 80023c8: 77fb strb r3, [r7, #31]
- 80023ca: e09e b.n 800250a <UART_SetConfig+0x34e>
- 80023cc: 2304 movs r3, #4
- 80023ce: 77fb strb r3, [r7, #31]
- 80023d0: e09b b.n 800250a <UART_SetConfig+0x34e>
- 80023d2: 2308 movs r3, #8
- 80023d4: 77fb strb r3, [r7, #31]
- 80023d6: e098 b.n 800250a <UART_SetConfig+0x34e>
- 80023d8: 2310 movs r3, #16
- 80023da: 77fb strb r3, [r7, #31]
- 80023dc: bf00 nop
- 80023de: e094 b.n 800250a <UART_SetConfig+0x34e>
- 80023e0: 687b ldr r3, [r7, #4]
- 80023e2: 681b ldr r3, [r3, #0]
- 80023e4: 4a39 ldr r2, [pc, #228] ; (80024cc <UART_SetConfig+0x310>)
- 80023e6: 4293 cmp r3, r2
- 80023e8: d124 bne.n 8002434 <UART_SetConfig+0x278>
- 80023ea: 4b33 ldr r3, [pc, #204] ; (80024b8 <UART_SetConfig+0x2fc>)
- 80023ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 80023f0: f403 6340 and.w r3, r3, #3072 ; 0xc00
- 80023f4: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 80023f8: d012 beq.n 8002420 <UART_SetConfig+0x264>
- 80023fa: f5b3 6f80 cmp.w r3, #1024 ; 0x400
- 80023fe: d802 bhi.n 8002406 <UART_SetConfig+0x24a>
+ 8002388: e111 b.n 80025ae <UART_SetConfig+0x34e>
+ 800238a: 2308 movs r3, #8
+ 800238c: 77fb strb r3, [r7, #31]
+ 800238e: e10e b.n 80025ae <UART_SetConfig+0x34e>
+ 8002390: 2310 movs r3, #16
+ 8002392: 77fb strb r3, [r7, #31]
+ 8002394: bf00 nop
+ 8002396: e10a b.n 80025ae <UART_SetConfig+0x34e>
+ 8002398: 687b ldr r3, [r7, #4]
+ 800239a: 681b ldr r3, [r3, #0]
+ 800239c: 4a71 ldr r2, [pc, #452] ; (8002564 <UART_SetConfig+0x304>)
+ 800239e: 4293 cmp r3, r2
+ 80023a0: d120 bne.n 80023e4 <UART_SetConfig+0x184>
+ 80023a2: 4b6e ldr r3, [pc, #440] ; (800255c <UART_SetConfig+0x2fc>)
+ 80023a4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 80023a8: f003 0330 and.w r3, r3, #48 ; 0x30
+ 80023ac: 2b10 cmp r3, #16
+ 80023ae: d00f beq.n 80023d0 <UART_SetConfig+0x170>
+ 80023b0: 2b10 cmp r3, #16
+ 80023b2: d802 bhi.n 80023ba <UART_SetConfig+0x15a>
+ 80023b4: 2b00 cmp r3, #0
+ 80023b6: d005 beq.n 80023c4 <UART_SetConfig+0x164>
+ 80023b8: e010 b.n 80023dc <UART_SetConfig+0x17c>
+ 80023ba: 2b20 cmp r3, #32
+ 80023bc: d005 beq.n 80023ca <UART_SetConfig+0x16a>
+ 80023be: 2b30 cmp r3, #48 ; 0x30
+ 80023c0: d009 beq.n 80023d6 <UART_SetConfig+0x176>
+ 80023c2: e00b b.n 80023dc <UART_SetConfig+0x17c>
+ 80023c4: 2300 movs r3, #0
+ 80023c6: 77fb strb r3, [r7, #31]
+ 80023c8: e0f1 b.n 80025ae <UART_SetConfig+0x34e>
+ 80023ca: 2302 movs r3, #2
+ 80023cc: 77fb strb r3, [r7, #31]
+ 80023ce: e0ee b.n 80025ae <UART_SetConfig+0x34e>
+ 80023d0: 2304 movs r3, #4
+ 80023d2: 77fb strb r3, [r7, #31]
+ 80023d4: e0eb b.n 80025ae <UART_SetConfig+0x34e>
+ 80023d6: 2308 movs r3, #8
+ 80023d8: 77fb strb r3, [r7, #31]
+ 80023da: e0e8 b.n 80025ae <UART_SetConfig+0x34e>
+ 80023dc: 2310 movs r3, #16
+ 80023de: 77fb strb r3, [r7, #31]
+ 80023e0: bf00 nop
+ 80023e2: e0e4 b.n 80025ae <UART_SetConfig+0x34e>
+ 80023e4: 687b ldr r3, [r7, #4]
+ 80023e6: 681b ldr r3, [r3, #0]
+ 80023e8: 4a5f ldr r2, [pc, #380] ; (8002568 <UART_SetConfig+0x308>)
+ 80023ea: 4293 cmp r3, r2
+ 80023ec: d120 bne.n 8002430 <UART_SetConfig+0x1d0>
+ 80023ee: 4b5b ldr r3, [pc, #364] ; (800255c <UART_SetConfig+0x2fc>)
+ 80023f0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 80023f4: f003 03c0 and.w r3, r3, #192 ; 0xc0
+ 80023f8: 2b40 cmp r3, #64 ; 0x40
+ 80023fa: d00f beq.n 800241c <UART_SetConfig+0x1bc>
+ 80023fc: 2b40 cmp r3, #64 ; 0x40
+ 80023fe: d802 bhi.n 8002406 <UART_SetConfig+0x1a6>
8002400: 2b00 cmp r3, #0
- 8002402: d007 beq.n 8002414 <UART_SetConfig+0x258>
- 8002404: e012 b.n 800242c <UART_SetConfig+0x270>
- 8002406: f5b3 6f00 cmp.w r3, #2048 ; 0x800
- 800240a: d006 beq.n 800241a <UART_SetConfig+0x25e>
- 800240c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
- 8002410: d009 beq.n 8002426 <UART_SetConfig+0x26a>
- 8002412: e00b b.n 800242c <UART_SetConfig+0x270>
- 8002414: 2301 movs r3, #1
- 8002416: 77fb strb r3, [r7, #31]
- 8002418: e077 b.n 800250a <UART_SetConfig+0x34e>
- 800241a: 2302 movs r3, #2
- 800241c: 77fb strb r3, [r7, #31]
- 800241e: e074 b.n 800250a <UART_SetConfig+0x34e>
- 8002420: 2304 movs r3, #4
- 8002422: 77fb strb r3, [r7, #31]
- 8002424: e071 b.n 800250a <UART_SetConfig+0x34e>
- 8002426: 2308 movs r3, #8
- 8002428: 77fb strb r3, [r7, #31]
- 800242a: e06e b.n 800250a <UART_SetConfig+0x34e>
- 800242c: 2310 movs r3, #16
- 800242e: 77fb strb r3, [r7, #31]
- 8002430: bf00 nop
- 8002432: e06a b.n 800250a <UART_SetConfig+0x34e>
- 8002434: 687b ldr r3, [r7, #4]
- 8002436: 681b ldr r3, [r3, #0]
- 8002438: 4a25 ldr r2, [pc, #148] ; (80024d0 <UART_SetConfig+0x314>)
- 800243a: 4293 cmp r3, r2
- 800243c: d124 bne.n 8002488 <UART_SetConfig+0x2cc>
- 800243e: 4b1e ldr r3, [pc, #120] ; (80024b8 <UART_SetConfig+0x2fc>)
- 8002440: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002444: f403 5340 and.w r3, r3, #12288 ; 0x3000
- 8002448: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 800244c: d012 beq.n 8002474 <UART_SetConfig+0x2b8>
- 800244e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
- 8002452: d802 bhi.n 800245a <UART_SetConfig+0x29e>
- 8002454: 2b00 cmp r3, #0
- 8002456: d007 beq.n 8002468 <UART_SetConfig+0x2ac>
- 8002458: e012 b.n 8002480 <UART_SetConfig+0x2c4>
- 800245a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
- 800245e: d006 beq.n 800246e <UART_SetConfig+0x2b2>
- 8002460: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
- 8002464: d009 beq.n 800247a <UART_SetConfig+0x2be>
- 8002466: e00b b.n 8002480 <UART_SetConfig+0x2c4>
- 8002468: 2300 movs r3, #0
- 800246a: 77fb strb r3, [r7, #31]
- 800246c: e04d b.n 800250a <UART_SetConfig+0x34e>
- 800246e: 2302 movs r3, #2
- 8002470: 77fb strb r3, [r7, #31]
- 8002472: e04a b.n 800250a <UART_SetConfig+0x34e>
- 8002474: 2304 movs r3, #4
- 8002476: 77fb strb r3, [r7, #31]
- 8002478: e047 b.n 800250a <UART_SetConfig+0x34e>
- 800247a: 2308 movs r3, #8
- 800247c: 77fb strb r3, [r7, #31]
- 800247e: e044 b.n 800250a <UART_SetConfig+0x34e>
- 8002480: 2310 movs r3, #16
- 8002482: 77fb strb r3, [r7, #31]
- 8002484: bf00 nop
- 8002486: e040 b.n 800250a <UART_SetConfig+0x34e>
- 8002488: 687b ldr r3, [r7, #4]
- 800248a: 681b ldr r3, [r3, #0]
- 800248c: 4a11 ldr r2, [pc, #68] ; (80024d4 <UART_SetConfig+0x318>)
- 800248e: 4293 cmp r3, r2
- 8002490: d139 bne.n 8002506 <UART_SetConfig+0x34a>
- 8002492: 4b09 ldr r3, [pc, #36] ; (80024b8 <UART_SetConfig+0x2fc>)
- 8002494: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
- 8002498: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 800249c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 80024a0: d027 beq.n 80024f2 <UART_SetConfig+0x336>
- 80024a2: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
- 80024a6: d817 bhi.n 80024d8 <UART_SetConfig+0x31c>
- 80024a8: 2b00 cmp r3, #0
- 80024aa: d01c beq.n 80024e6 <UART_SetConfig+0x32a>
- 80024ac: e027 b.n 80024fe <UART_SetConfig+0x342>
- 80024ae: bf00 nop
- 80024b0: efff69f3 .word 0xefff69f3
- 80024b4: 40011000 .word 0x40011000
- 80024b8: 40023800 .word 0x40023800
- 80024bc: 40004400 .word 0x40004400
- 80024c0: 40004800 .word 0x40004800
- 80024c4: 40004c00 .word 0x40004c00
- 80024c8: 40005000 .word 0x40005000
- 80024cc: 40011400 .word 0x40011400
- 80024d0: 40007800 .word 0x40007800
- 80024d4: 40007c00 .word 0x40007c00
- 80024d8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 80024dc: d006 beq.n 80024ec <UART_SetConfig+0x330>
- 80024de: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
- 80024e2: d009 beq.n 80024f8 <UART_SetConfig+0x33c>
- 80024e4: e00b b.n 80024fe <UART_SetConfig+0x342>
- 80024e6: 2300 movs r3, #0
- 80024e8: 77fb strb r3, [r7, #31]
- 80024ea: e00e b.n 800250a <UART_SetConfig+0x34e>
- 80024ec: 2302 movs r3, #2
- 80024ee: 77fb strb r3, [r7, #31]
- 80024f0: e00b b.n 800250a <UART_SetConfig+0x34e>
- 80024f2: 2304 movs r3, #4
- 80024f4: 77fb strb r3, [r7, #31]
- 80024f6: e008 b.n 800250a <UART_SetConfig+0x34e>
- 80024f8: 2308 movs r3, #8
- 80024fa: 77fb strb r3, [r7, #31]
- 80024fc: e005 b.n 800250a <UART_SetConfig+0x34e>
- 80024fe: 2310 movs r3, #16
- 8002500: 77fb strb r3, [r7, #31]
- 8002502: bf00 nop
- 8002504: e001 b.n 800250a <UART_SetConfig+0x34e>
- 8002506: 2310 movs r3, #16
- 8002508: 77fb strb r3, [r7, #31]
+ 8002402: d005 beq.n 8002410 <UART_SetConfig+0x1b0>
+ 8002404: e010 b.n 8002428 <UART_SetConfig+0x1c8>
+ 8002406: 2b80 cmp r3, #128 ; 0x80
+ 8002408: d005 beq.n 8002416 <UART_SetConfig+0x1b6>
+ 800240a: 2bc0 cmp r3, #192 ; 0xc0
+ 800240c: d009 beq.n 8002422 <UART_SetConfig+0x1c2>
+ 800240e: e00b b.n 8002428 <UART_SetConfig+0x1c8>
+ 8002410: 2300 movs r3, #0
+ 8002412: 77fb strb r3, [r7, #31]
+ 8002414: e0cb b.n 80025ae <UART_SetConfig+0x34e>
+ 8002416: 2302 movs r3, #2
+ 8002418: 77fb strb r3, [r7, #31]
+ 800241a: e0c8 b.n 80025ae <UART_SetConfig+0x34e>
+ 800241c: 2304 movs r3, #4
+ 800241e: 77fb strb r3, [r7, #31]
+ 8002420: e0c5 b.n 80025ae <UART_SetConfig+0x34e>
+ 8002422: 2308 movs r3, #8
+ 8002424: 77fb strb r3, [r7, #31]
+ 8002426: e0c2 b.n 80025ae <UART_SetConfig+0x34e>
+ 8002428: 2310 movs r3, #16
+ 800242a: 77fb strb r3, [r7, #31]
+ 800242c: bf00 nop
+ 800242e: e0be b.n 80025ae <UART_SetConfig+0x34e>
+ 8002430: 687b ldr r3, [r7, #4]
+ 8002432: 681b ldr r3, [r3, #0]
+ 8002434: 4a4d ldr r2, [pc, #308] ; (800256c <UART_SetConfig+0x30c>)
+ 8002436: 4293 cmp r3, r2
+ 8002438: d124 bne.n 8002484 <UART_SetConfig+0x224>
+ 800243a: 4b48 ldr r3, [pc, #288] ; (800255c <UART_SetConfig+0x2fc>)
+ 800243c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002440: f403 7340 and.w r3, r3, #768 ; 0x300
+ 8002444: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 8002448: d012 beq.n 8002470 <UART_SetConfig+0x210>
+ 800244a: f5b3 7f80 cmp.w r3, #256 ; 0x100
+ 800244e: d802 bhi.n 8002456 <UART_SetConfig+0x1f6>
+ 8002450: 2b00 cmp r3, #0
+ 8002452: d007 beq.n 8002464 <UART_SetConfig+0x204>
+ 8002454: e012 b.n 800247c <UART_SetConfig+0x21c>
+ 8002456: f5b3 7f00 cmp.w r3, #512 ; 0x200
+ 800245a: d006 beq.n 800246a <UART_SetConfig+0x20a>
+ 800245c: f5b3 7f40 cmp.w r3, #768 ; 0x300
+ 8002460: d009 beq.n 8002476 <UART_SetConfig+0x216>
+ 8002462: e00b b.n 800247c <UART_SetConfig+0x21c>
+ 8002464: 2300 movs r3, #0
+ 8002466: 77fb strb r3, [r7, #31]
+ 8002468: e0a1 b.n 80025ae <UART_SetConfig+0x34e>
+ 800246a: 2302 movs r3, #2
+ 800246c: 77fb strb r3, [r7, #31]
+ 800246e: e09e b.n 80025ae <UART_SetConfig+0x34e>
+ 8002470: 2304 movs r3, #4
+ 8002472: 77fb strb r3, [r7, #31]
+ 8002474: e09b b.n 80025ae <UART_SetConfig+0x34e>
+ 8002476: 2308 movs r3, #8
+ 8002478: 77fb strb r3, [r7, #31]
+ 800247a: e098 b.n 80025ae <UART_SetConfig+0x34e>
+ 800247c: 2310 movs r3, #16
+ 800247e: 77fb strb r3, [r7, #31]
+ 8002480: bf00 nop
+ 8002482: e094 b.n 80025ae <UART_SetConfig+0x34e>
+ 8002484: 687b ldr r3, [r7, #4]
+ 8002486: 681b ldr r3, [r3, #0]
+ 8002488: 4a39 ldr r2, [pc, #228] ; (8002570 <UART_SetConfig+0x310>)
+ 800248a: 4293 cmp r3, r2
+ 800248c: d124 bne.n 80024d8 <UART_SetConfig+0x278>
+ 800248e: 4b33 ldr r3, [pc, #204] ; (800255c <UART_SetConfig+0x2fc>)
+ 8002490: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 8002494: f403 6340 and.w r3, r3, #3072 ; 0xc00
+ 8002498: f5b3 6f80 cmp.w r3, #1024 ; 0x400
+ 800249c: d012 beq.n 80024c4 <UART_SetConfig+0x264>
+ 800249e: f5b3 6f80 cmp.w r3, #1024 ; 0x400
+ 80024a2: d802 bhi.n 80024aa <UART_SetConfig+0x24a>
+ 80024a4: 2b00 cmp r3, #0
+ 80024a6: d007 beq.n 80024b8 <UART_SetConfig+0x258>
+ 80024a8: e012 b.n 80024d0 <UART_SetConfig+0x270>
+ 80024aa: f5b3 6f00 cmp.w r3, #2048 ; 0x800
+ 80024ae: d006 beq.n 80024be <UART_SetConfig+0x25e>
+ 80024b0: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
+ 80024b4: d009 beq.n 80024ca <UART_SetConfig+0x26a>
+ 80024b6: e00b b.n 80024d0 <UART_SetConfig+0x270>
+ 80024b8: 2301 movs r3, #1
+ 80024ba: 77fb strb r3, [r7, #31]
+ 80024bc: e077 b.n 80025ae <UART_SetConfig+0x34e>
+ 80024be: 2302 movs r3, #2
+ 80024c0: 77fb strb r3, [r7, #31]
+ 80024c2: e074 b.n 80025ae <UART_SetConfig+0x34e>
+ 80024c4: 2304 movs r3, #4
+ 80024c6: 77fb strb r3, [r7, #31]
+ 80024c8: e071 b.n 80025ae <UART_SetConfig+0x34e>
+ 80024ca: 2308 movs r3, #8
+ 80024cc: 77fb strb r3, [r7, #31]
+ 80024ce: e06e b.n 80025ae <UART_SetConfig+0x34e>
+ 80024d0: 2310 movs r3, #16
+ 80024d2: 77fb strb r3, [r7, #31]
+ 80024d4: bf00 nop
+ 80024d6: e06a b.n 80025ae <UART_SetConfig+0x34e>
+ 80024d8: 687b ldr r3, [r7, #4]
+ 80024da: 681b ldr r3, [r3, #0]
+ 80024dc: 4a25 ldr r2, [pc, #148] ; (8002574 <UART_SetConfig+0x314>)
+ 80024de: 4293 cmp r3, r2
+ 80024e0: d124 bne.n 800252c <UART_SetConfig+0x2cc>
+ 80024e2: 4b1e ldr r3, [pc, #120] ; (800255c <UART_SetConfig+0x2fc>)
+ 80024e4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 80024e8: f403 5340 and.w r3, r3, #12288 ; 0x3000
+ 80024ec: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 80024f0: d012 beq.n 8002518 <UART_SetConfig+0x2b8>
+ 80024f2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
+ 80024f6: d802 bhi.n 80024fe <UART_SetConfig+0x29e>
+ 80024f8: 2b00 cmp r3, #0
+ 80024fa: d007 beq.n 800250c <UART_SetConfig+0x2ac>
+ 80024fc: e012 b.n 8002524 <UART_SetConfig+0x2c4>
+ 80024fe: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
+ 8002502: d006 beq.n 8002512 <UART_SetConfig+0x2b2>
+ 8002504: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
+ 8002508: d009 beq.n 800251e <UART_SetConfig+0x2be>
+ 800250a: e00b b.n 8002524 <UART_SetConfig+0x2c4>
+ 800250c: 2300 movs r3, #0
+ 800250e: 77fb strb r3, [r7, #31]
+ 8002510: e04d b.n 80025ae <UART_SetConfig+0x34e>
+ 8002512: 2302 movs r3, #2
+ 8002514: 77fb strb r3, [r7, #31]
+ 8002516: e04a b.n 80025ae <UART_SetConfig+0x34e>
+ 8002518: 2304 movs r3, #4
+ 800251a: 77fb strb r3, [r7, #31]
+ 800251c: e047 b.n 80025ae <UART_SetConfig+0x34e>
+ 800251e: 2308 movs r3, #8
+ 8002520: 77fb strb r3, [r7, #31]
+ 8002522: e044 b.n 80025ae <UART_SetConfig+0x34e>
+ 8002524: 2310 movs r3, #16
+ 8002526: 77fb strb r3, [r7, #31]
+ 8002528: bf00 nop
+ 800252a: e040 b.n 80025ae <UART_SetConfig+0x34e>
+ 800252c: 687b ldr r3, [r7, #4]
+ 800252e: 681b ldr r3, [r3, #0]
+ 8002530: 4a11 ldr r2, [pc, #68] ; (8002578 <UART_SetConfig+0x318>)
+ 8002532: 4293 cmp r3, r2
+ 8002534: d139 bne.n 80025aa <UART_SetConfig+0x34a>
+ 8002536: 4b09 ldr r3, [pc, #36] ; (800255c <UART_SetConfig+0x2fc>)
+ 8002538: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
+ 800253c: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 8002540: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
+ 8002544: d027 beq.n 8002596 <UART_SetConfig+0x336>
+ 8002546: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
+ 800254a: d817 bhi.n 800257c <UART_SetConfig+0x31c>
+ 800254c: 2b00 cmp r3, #0
+ 800254e: d01c beq.n 800258a <UART_SetConfig+0x32a>
+ 8002550: e027 b.n 80025a2 <UART_SetConfig+0x342>
+ 8002552: bf00 nop
+ 8002554: efff69f3 .word 0xefff69f3
+ 8002558: 40011000 .word 0x40011000
+ 800255c: 40023800 .word 0x40023800
+ 8002560: 40004400 .word 0x40004400
+ 8002564: 40004800 .word 0x40004800
+ 8002568: 40004c00 .word 0x40004c00
+ 800256c: 40005000 .word 0x40005000
+ 8002570: 40011400 .word 0x40011400
+ 8002574: 40007800 .word 0x40007800
+ 8002578: 40007c00 .word 0x40007c00
+ 800257c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
+ 8002580: d006 beq.n 8002590 <UART_SetConfig+0x330>
+ 8002582: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
+ 8002586: d009 beq.n 800259c <UART_SetConfig+0x33c>
+ 8002588: e00b b.n 80025a2 <UART_SetConfig+0x342>
+ 800258a: 2300 movs r3, #0
+ 800258c: 77fb strb r3, [r7, #31]
+ 800258e: e00e b.n 80025ae <UART_SetConfig+0x34e>
+ 8002590: 2302 movs r3, #2
+ 8002592: 77fb strb r3, [r7, #31]
+ 8002594: e00b b.n 80025ae <UART_SetConfig+0x34e>
+ 8002596: 2304 movs r3, #4
+ 8002598: 77fb strb r3, [r7, #31]
+ 800259a: e008 b.n 80025ae <UART_SetConfig+0x34e>
+ 800259c: 2308 movs r3, #8
+ 800259e: 77fb strb r3, [r7, #31]
+ 80025a0: e005 b.n 80025ae <UART_SetConfig+0x34e>
+ 80025a2: 2310 movs r3, #16
+ 80025a4: 77fb strb r3, [r7, #31]
+ 80025a6: bf00 nop
+ 80025a8: e001 b.n 80025ae <UART_SetConfig+0x34e>
+ 80025aa: 2310 movs r3, #16
+ 80025ac: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 800250a: 687b ldr r3, [r7, #4]
- 800250c: 69db ldr r3, [r3, #28]
- 800250e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
- 8002512: d17c bne.n 800260e <UART_SetConfig+0x452>
+ 80025ae: 687b ldr r3, [r7, #4]
+ 80025b0: 69db ldr r3, [r3, #28]
+ 80025b2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
+ 80025b6: d17c bne.n 80026b2 <UART_SetConfig+0x452>
{
switch (clocksource)
- 8002514: 7ffb ldrb r3, [r7, #31]
- 8002516: 2b08 cmp r3, #8
- 8002518: d859 bhi.n 80025ce <UART_SetConfig+0x412>
- 800251a: a201 add r2, pc, #4 ; (adr r2, 8002520 <UART_SetConfig+0x364>)
- 800251c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8002520: 08002545 .word 0x08002545
- 8002524: 08002563 .word 0x08002563
- 8002528: 08002581 .word 0x08002581
- 800252c: 080025cf .word 0x080025cf
- 8002530: 08002599 .word 0x08002599
- 8002534: 080025cf .word 0x080025cf
- 8002538: 080025cf .word 0x080025cf
- 800253c: 080025cf .word 0x080025cf
- 8002540: 080025b7 .word 0x080025b7
+ 80025b8: 7ffb ldrb r3, [r7, #31]
+ 80025ba: 2b08 cmp r3, #8
+ 80025bc: d859 bhi.n 8002672 <UART_SetConfig+0x412>
+ 80025be: a201 add r2, pc, #4 ; (adr r2, 80025c4 <UART_SetConfig+0x364>)
+ 80025c0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80025c4: 080025e9 .word 0x080025e9
+ 80025c8: 08002607 .word 0x08002607
+ 80025cc: 08002625 .word 0x08002625
+ 80025d0: 08002673 .word 0x08002673
+ 80025d4: 0800263d .word 0x0800263d
+ 80025d8: 08002673 .word 0x08002673
+ 80025dc: 08002673 .word 0x08002673
+ 80025e0: 08002673 .word 0x08002673
+ 80025e4: 0800265b .word 0x0800265b
{
case UART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8002544: f7ff f90c bl 8001760 <HAL_RCC_GetPCLK1Freq>
- 8002548: 4603 mov r3, r0
- 800254a: 005a lsls r2, r3, #1
- 800254c: 687b ldr r3, [r7, #4]
- 800254e: 685b ldr r3, [r3, #4]
- 8002550: 085b lsrs r3, r3, #1
- 8002552: 441a add r2, r3
- 8002554: 687b ldr r3, [r7, #4]
- 8002556: 685b ldr r3, [r3, #4]
- 8002558: fbb2 f3f3 udiv r3, r2, r3
- 800255c: b29b uxth r3, r3
- 800255e: 61bb str r3, [r7, #24]
+ 80025e8: f7ff f90c bl 8001804 <HAL_RCC_GetPCLK1Freq>
+ 80025ec: 4603 mov r3, r0
+ 80025ee: 005a lsls r2, r3, #1
+ 80025f0: 687b ldr r3, [r7, #4]
+ 80025f2: 685b ldr r3, [r3, #4]
+ 80025f4: 085b lsrs r3, r3, #1
+ 80025f6: 441a add r2, r3
+ 80025f8: 687b ldr r3, [r7, #4]
+ 80025fa: 685b ldr r3, [r3, #4]
+ 80025fc: fbb2 f3f3 udiv r3, r2, r3
+ 8002600: b29b uxth r3, r3
+ 8002602: 61bb str r3, [r7, #24]
break;
- 8002560: e038 b.n 80025d4 <UART_SetConfig+0x418>
+ 8002604: e038 b.n 8002678 <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 8002562: f7ff f911 bl 8001788 <HAL_RCC_GetPCLK2Freq>
- 8002566: 4603 mov r3, r0
- 8002568: 005a lsls r2, r3, #1
- 800256a: 687b ldr r3, [r7, #4]
- 800256c: 685b ldr r3, [r3, #4]
- 800256e: 085b lsrs r3, r3, #1
- 8002570: 441a add r2, r3
- 8002572: 687b ldr r3, [r7, #4]
- 8002574: 685b ldr r3, [r3, #4]
- 8002576: fbb2 f3f3 udiv r3, r2, r3
- 800257a: b29b uxth r3, r3
- 800257c: 61bb str r3, [r7, #24]
+ 8002606: f7ff f911 bl 800182c <HAL_RCC_GetPCLK2Freq>
+ 800260a: 4603 mov r3, r0
+ 800260c: 005a lsls r2, r3, #1
+ 800260e: 687b ldr r3, [r7, #4]
+ 8002610: 685b ldr r3, [r3, #4]
+ 8002612: 085b lsrs r3, r3, #1
+ 8002614: 441a add r2, r3
+ 8002616: 687b ldr r3, [r7, #4]
+ 8002618: 685b ldr r3, [r3, #4]
+ 800261a: fbb2 f3f3 udiv r3, r2, r3
+ 800261e: b29b uxth r3, r3
+ 8002620: 61bb str r3, [r7, #24]
break;
- 800257e: e029 b.n 80025d4 <UART_SetConfig+0x418>
+ 8002622: e029 b.n 8002678 <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- 8002580: 687b ldr r3, [r7, #4]
- 8002582: 685b ldr r3, [r3, #4]
- 8002584: 085a lsrs r2, r3, #1
- 8002586: 4b5d ldr r3, [pc, #372] ; (80026fc <UART_SetConfig+0x540>)
- 8002588: 4413 add r3, r2
- 800258a: 687a ldr r2, [r7, #4]
- 800258c: 6852 ldr r2, [r2, #4]
- 800258e: fbb3 f3f2 udiv r3, r3, r2
- 8002592: b29b uxth r3, r3
- 8002594: 61bb str r3, [r7, #24]
+ 8002624: 687b ldr r3, [r7, #4]
+ 8002626: 685b ldr r3, [r3, #4]
+ 8002628: 085a lsrs r2, r3, #1
+ 800262a: 4b5d ldr r3, [pc, #372] ; (80027a0 <UART_SetConfig+0x540>)
+ 800262c: 4413 add r3, r2
+ 800262e: 687a ldr r2, [r7, #4]
+ 8002630: 6852 ldr r2, [r2, #4]
+ 8002632: fbb3 f3f2 udiv r3, r3, r2
+ 8002636: b29b uxth r3, r3
+ 8002638: 61bb str r3, [r7, #24]
break;
- 8002596: e01d b.n 80025d4 <UART_SetConfig+0x418>
+ 800263a: e01d b.n 8002678 <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8002598: f7ff f824 bl 80015e4 <HAL_RCC_GetSysClockFreq>
- 800259c: 4603 mov r3, r0
- 800259e: 005a lsls r2, r3, #1
- 80025a0: 687b ldr r3, [r7, #4]
- 80025a2: 685b ldr r3, [r3, #4]
- 80025a4: 085b lsrs r3, r3, #1
- 80025a6: 441a add r2, r3
- 80025a8: 687b ldr r3, [r7, #4]
- 80025aa: 685b ldr r3, [r3, #4]
- 80025ac: fbb2 f3f3 udiv r3, r2, r3
- 80025b0: b29b uxth r3, r3
- 80025b2: 61bb str r3, [r7, #24]
+ 800263c: f7ff f824 bl 8001688 <HAL_RCC_GetSysClockFreq>
+ 8002640: 4603 mov r3, r0
+ 8002642: 005a lsls r2, r3, #1
+ 8002644: 687b ldr r3, [r7, #4]
+ 8002646: 685b ldr r3, [r3, #4]
+ 8002648: 085b lsrs r3, r3, #1
+ 800264a: 441a add r2, r3
+ 800264c: 687b ldr r3, [r7, #4]
+ 800264e: 685b ldr r3, [r3, #4]
+ 8002650: fbb2 f3f3 udiv r3, r2, r3
+ 8002654: b29b uxth r3, r3
+ 8002656: 61bb str r3, [r7, #24]
break;
- 80025b4: e00e b.n 80025d4 <UART_SetConfig+0x418>
+ 8002658: e00e b.n 8002678 <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- 80025b6: 687b ldr r3, [r7, #4]
- 80025b8: 685b ldr r3, [r3, #4]
- 80025ba: 085b lsrs r3, r3, #1
- 80025bc: f503 3280 add.w r2, r3, #65536 ; 0x10000
- 80025c0: 687b ldr r3, [r7, #4]
- 80025c2: 685b ldr r3, [r3, #4]
- 80025c4: fbb2 f3f3 udiv r3, r2, r3
- 80025c8: b29b uxth r3, r3
- 80025ca: 61bb str r3, [r7, #24]
+ 800265a: 687b ldr r3, [r7, #4]
+ 800265c: 685b ldr r3, [r3, #4]
+ 800265e: 085b lsrs r3, r3, #1
+ 8002660: f503 3280 add.w r2, r3, #65536 ; 0x10000
+ 8002664: 687b ldr r3, [r7, #4]
+ 8002666: 685b ldr r3, [r3, #4]
+ 8002668: fbb2 f3f3 udiv r3, r2, r3
+ 800266c: b29b uxth r3, r3
+ 800266e: 61bb str r3, [r7, #24]
break;
- 80025cc: e002 b.n 80025d4 <UART_SetConfig+0x418>
+ 8002670: e002 b.n 8002678 <UART_SetConfig+0x418>
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
- 80025ce: 2301 movs r3, #1
- 80025d0: 75fb strb r3, [r7, #23]
+ 8002672: 2301 movs r3, #1
+ 8002674: 75fb strb r3, [r7, #23]
break;
- 80025d2: bf00 nop
+ 8002676: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 80025d4: 69bb ldr r3, [r7, #24]
- 80025d6: 2b0f cmp r3, #15
- 80025d8: d916 bls.n 8002608 <UART_SetConfig+0x44c>
- 80025da: 69bb ldr r3, [r7, #24]
- 80025dc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 80025e0: d212 bcs.n 8002608 <UART_SetConfig+0x44c>
+ 8002678: 69bb ldr r3, [r7, #24]
+ 800267a: 2b0f cmp r3, #15
+ 800267c: d916 bls.n 80026ac <UART_SetConfig+0x44c>
+ 800267e: 69bb ldr r3, [r7, #24]
+ 8002680: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8002684: d212 bcs.n 80026ac <UART_SetConfig+0x44c>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 80025e2: 69bb ldr r3, [r7, #24]
- 80025e4: b29b uxth r3, r3
- 80025e6: f023 030f bic.w r3, r3, #15
- 80025ea: 81fb strh r3, [r7, #14]
+ 8002686: 69bb ldr r3, [r7, #24]
+ 8002688: b29b uxth r3, r3
+ 800268a: f023 030f bic.w r3, r3, #15
+ 800268e: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 80025ec: 69bb ldr r3, [r7, #24]
- 80025ee: 085b lsrs r3, r3, #1
- 80025f0: b29b uxth r3, r3
- 80025f2: f003 0307 and.w r3, r3, #7
- 80025f6: b29a uxth r2, r3
- 80025f8: 89fb ldrh r3, [r7, #14]
- 80025fa: 4313 orrs r3, r2
- 80025fc: 81fb strh r3, [r7, #14]
+ 8002690: 69bb ldr r3, [r7, #24]
+ 8002692: 085b lsrs r3, r3, #1
+ 8002694: b29b uxth r3, r3
+ 8002696: f003 0307 and.w r3, r3, #7
+ 800269a: b29a uxth r2, r3
+ 800269c: 89fb ldrh r3, [r7, #14]
+ 800269e: 4313 orrs r3, r2
+ 80026a0: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
- 80025fe: 687b ldr r3, [r7, #4]
- 8002600: 681b ldr r3, [r3, #0]
- 8002602: 89fa ldrh r2, [r7, #14]
- 8002604: 60da str r2, [r3, #12]
- 8002606: e06e b.n 80026e6 <UART_SetConfig+0x52a>
+ 80026a2: 687b ldr r3, [r7, #4]
+ 80026a4: 681b ldr r3, [r3, #0]
+ 80026a6: 89fa ldrh r2, [r7, #14]
+ 80026a8: 60da str r2, [r3, #12]
+ 80026aa: e06e b.n 800278a <UART_SetConfig+0x52a>
}
else
{
ret = HAL_ERROR;
- 8002608: 2301 movs r3, #1
- 800260a: 75fb strb r3, [r7, #23]
- 800260c: e06b b.n 80026e6 <UART_SetConfig+0x52a>
+ 80026ac: 2301 movs r3, #1
+ 80026ae: 75fb strb r3, [r7, #23]
+ 80026b0: e06b b.n 800278a <UART_SetConfig+0x52a>
}
}
else
{
switch (clocksource)
- 800260e: 7ffb ldrb r3, [r7, #31]
- 8002610: 2b08 cmp r3, #8
- 8002612: d857 bhi.n 80026c4 <UART_SetConfig+0x508>
- 8002614: a201 add r2, pc, #4 ; (adr r2, 800261c <UART_SetConfig+0x460>)
- 8002616: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 800261a: bf00 nop
- 800261c: 08002641 .word 0x08002641
- 8002620: 0800265d .word 0x0800265d
- 8002624: 08002679 .word 0x08002679
- 8002628: 080026c5 .word 0x080026c5
- 800262c: 08002691 .word 0x08002691
- 8002630: 080026c5 .word 0x080026c5
- 8002634: 080026c5 .word 0x080026c5
- 8002638: 080026c5 .word 0x080026c5
- 800263c: 080026ad .word 0x080026ad
+ 80026b2: 7ffb ldrb r3, [r7, #31]
+ 80026b4: 2b08 cmp r3, #8
+ 80026b6: d857 bhi.n 8002768 <UART_SetConfig+0x508>
+ 80026b8: a201 add r2, pc, #4 ; (adr r2, 80026c0 <UART_SetConfig+0x460>)
+ 80026ba: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80026be: bf00 nop
+ 80026c0: 080026e5 .word 0x080026e5
+ 80026c4: 08002701 .word 0x08002701
+ 80026c8: 0800271d .word 0x0800271d
+ 80026cc: 08002769 .word 0x08002769
+ 80026d0: 08002735 .word 0x08002735
+ 80026d4: 08002769 .word 0x08002769
+ 80026d8: 08002769 .word 0x08002769
+ 80026dc: 08002769 .word 0x08002769
+ 80026e0: 08002751 .word 0x08002751
{
case UART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- 8002640: f7ff f88e bl 8001760 <HAL_RCC_GetPCLK1Freq>
- 8002644: 4602 mov r2, r0
- 8002646: 687b ldr r3, [r7, #4]
- 8002648: 685b ldr r3, [r3, #4]
- 800264a: 085b lsrs r3, r3, #1
- 800264c: 441a add r2, r3
- 800264e: 687b ldr r3, [r7, #4]
- 8002650: 685b ldr r3, [r3, #4]
- 8002652: fbb2 f3f3 udiv r3, r2, r3
- 8002656: b29b uxth r3, r3
- 8002658: 61bb str r3, [r7, #24]
+ 80026e4: f7ff f88e bl 8001804 <HAL_RCC_GetPCLK1Freq>
+ 80026e8: 4602 mov r2, r0
+ 80026ea: 687b ldr r3, [r7, #4]
+ 80026ec: 685b ldr r3, [r3, #4]
+ 80026ee: 085b lsrs r3, r3, #1
+ 80026f0: 441a add r2, r3
+ 80026f2: 687b ldr r3, [r7, #4]
+ 80026f4: 685b ldr r3, [r3, #4]
+ 80026f6: fbb2 f3f3 udiv r3, r2, r3
+ 80026fa: b29b uxth r3, r3
+ 80026fc: 61bb str r3, [r7, #24]
break;
- 800265a: e036 b.n 80026ca <UART_SetConfig+0x50e>
+ 80026fe: e036 b.n 800276e <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_PCLK2:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
- 800265c: f7ff f894 bl 8001788 <HAL_RCC_GetPCLK2Freq>
- 8002660: 4602 mov r2, r0
- 8002662: 687b ldr r3, [r7, #4]
- 8002664: 685b ldr r3, [r3, #4]
- 8002666: 085b lsrs r3, r3, #1
- 8002668: 441a add r2, r3
- 800266a: 687b ldr r3, [r7, #4]
- 800266c: 685b ldr r3, [r3, #4]
- 800266e: fbb2 f3f3 udiv r3, r2, r3
- 8002672: b29b uxth r3, r3
- 8002674: 61bb str r3, [r7, #24]
+ 8002700: f7ff f894 bl 800182c <HAL_RCC_GetPCLK2Freq>
+ 8002704: 4602 mov r2, r0
+ 8002706: 687b ldr r3, [r7, #4]
+ 8002708: 685b ldr r3, [r3, #4]
+ 800270a: 085b lsrs r3, r3, #1
+ 800270c: 441a add r2, r3
+ 800270e: 687b ldr r3, [r7, #4]
+ 8002710: 685b ldr r3, [r3, #4]
+ 8002712: fbb2 f3f3 udiv r3, r2, r3
+ 8002716: b29b uxth r3, r3
+ 8002718: 61bb str r3, [r7, #24]
break;
- 8002676: e028 b.n 80026ca <UART_SetConfig+0x50e>
+ 800271a: e028 b.n 800276e <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- 8002678: 687b ldr r3, [r7, #4]
- 800267a: 685b ldr r3, [r3, #4]
- 800267c: 085a lsrs r2, r3, #1
- 800267e: 4b20 ldr r3, [pc, #128] ; (8002700 <UART_SetConfig+0x544>)
- 8002680: 4413 add r3, r2
- 8002682: 687a ldr r2, [r7, #4]
- 8002684: 6852 ldr r2, [r2, #4]
- 8002686: fbb3 f3f2 udiv r3, r3, r2
- 800268a: b29b uxth r3, r3
- 800268c: 61bb str r3, [r7, #24]
+ 800271c: 687b ldr r3, [r7, #4]
+ 800271e: 685b ldr r3, [r3, #4]
+ 8002720: 085a lsrs r2, r3, #1
+ 8002722: 4b20 ldr r3, [pc, #128] ; (80027a4 <UART_SetConfig+0x544>)
+ 8002724: 4413 add r3, r2
+ 8002726: 687a ldr r2, [r7, #4]
+ 8002728: 6852 ldr r2, [r2, #4]
+ 800272a: fbb3 f3f2 udiv r3, r3, r2
+ 800272e: b29b uxth r3, r3
+ 8002730: 61bb str r3, [r7, #24]
break;
- 800268e: e01c b.n 80026ca <UART_SetConfig+0x50e>
+ 8002732: e01c b.n 800276e <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- 8002690: f7fe ffa8 bl 80015e4 <HAL_RCC_GetSysClockFreq>
- 8002694: 4602 mov r2, r0
- 8002696: 687b ldr r3, [r7, #4]
- 8002698: 685b ldr r3, [r3, #4]
- 800269a: 085b lsrs r3, r3, #1
- 800269c: 441a add r2, r3
- 800269e: 687b ldr r3, [r7, #4]
- 80026a0: 685b ldr r3, [r3, #4]
- 80026a2: fbb2 f3f3 udiv r3, r2, r3
- 80026a6: b29b uxth r3, r3
- 80026a8: 61bb str r3, [r7, #24]
+ 8002734: f7fe ffa8 bl 8001688 <HAL_RCC_GetSysClockFreq>
+ 8002738: 4602 mov r2, r0
+ 800273a: 687b ldr r3, [r7, #4]
+ 800273c: 685b ldr r3, [r3, #4]
+ 800273e: 085b lsrs r3, r3, #1
+ 8002740: 441a add r2, r3
+ 8002742: 687b ldr r3, [r7, #4]
+ 8002744: 685b ldr r3, [r3, #4]
+ 8002746: fbb2 f3f3 udiv r3, r2, r3
+ 800274a: b29b uxth r3, r3
+ 800274c: 61bb str r3, [r7, #24]
break;
- 80026aa: e00e b.n 80026ca <UART_SetConfig+0x50e>
+ 800274e: e00e b.n 800276e <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- 80026ac: 687b ldr r3, [r7, #4]
- 80026ae: 685b ldr r3, [r3, #4]
- 80026b0: 085b lsrs r3, r3, #1
- 80026b2: f503 4200 add.w r2, r3, #32768 ; 0x8000
- 80026b6: 687b ldr r3, [r7, #4]
- 80026b8: 685b ldr r3, [r3, #4]
- 80026ba: fbb2 f3f3 udiv r3, r2, r3
- 80026be: b29b uxth r3, r3
- 80026c0: 61bb str r3, [r7, #24]
+ 8002750: 687b ldr r3, [r7, #4]
+ 8002752: 685b ldr r3, [r3, #4]
+ 8002754: 085b lsrs r3, r3, #1
+ 8002756: f503 4200 add.w r2, r3, #32768 ; 0x8000
+ 800275a: 687b ldr r3, [r7, #4]
+ 800275c: 685b ldr r3, [r3, #4]
+ 800275e: fbb2 f3f3 udiv r3, r2, r3
+ 8002762: b29b uxth r3, r3
+ 8002764: 61bb str r3, [r7, #24]
break;
- 80026c2: e002 b.n 80026ca <UART_SetConfig+0x50e>
+ 8002766: e002 b.n 800276e <UART_SetConfig+0x50e>
case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
- 80026c4: 2301 movs r3, #1
- 80026c6: 75fb strb r3, [r7, #23]
+ 8002768: 2301 movs r3, #1
+ 800276a: 75fb strb r3, [r7, #23]
break;
- 80026c8: bf00 nop
+ 800276c: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 80026ca: 69bb ldr r3, [r7, #24]
- 80026cc: 2b0f cmp r3, #15
- 80026ce: d908 bls.n 80026e2 <UART_SetConfig+0x526>
- 80026d0: 69bb ldr r3, [r7, #24]
- 80026d2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 80026d6: d204 bcs.n 80026e2 <UART_SetConfig+0x526>
+ 800276e: 69bb ldr r3, [r7, #24]
+ 8002770: 2b0f cmp r3, #15
+ 8002772: d908 bls.n 8002786 <UART_SetConfig+0x526>
+ 8002774: 69bb ldr r3, [r7, #24]
+ 8002776: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 800277a: d204 bcs.n 8002786 <UART_SetConfig+0x526>
{
huart->Instance->BRR = usartdiv;
- 80026d8: 687b ldr r3, [r7, #4]
- 80026da: 681b ldr r3, [r3, #0]
- 80026dc: 69ba ldr r2, [r7, #24]
- 80026de: 60da str r2, [r3, #12]
- 80026e0: e001 b.n 80026e6 <UART_SetConfig+0x52a>
+ 800277c: 687b ldr r3, [r7, #4]
+ 800277e: 681b ldr r3, [r3, #0]
+ 8002780: 69ba ldr r2, [r7, #24]
+ 8002782: 60da str r2, [r3, #12]
+ 8002784: e001 b.n 800278a <UART_SetConfig+0x52a>
}
else
{
ret = HAL_ERROR;
- 80026e2: 2301 movs r3, #1
- 80026e4: 75fb strb r3, [r7, #23]
+ 8002786: 2301 movs r3, #1
+ 8002788: 75fb strb r3, [r7, #23]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
- 80026e6: 687b ldr r3, [r7, #4]
- 80026e8: 2200 movs r2, #0
- 80026ea: 661a str r2, [r3, #96] ; 0x60
+ 800278a: 687b ldr r3, [r7, #4]
+ 800278c: 2200 movs r2, #0
+ 800278e: 661a str r2, [r3, #96] ; 0x60
huart->TxISR = NULL;
- 80026ec: 687b ldr r3, [r7, #4]
- 80026ee: 2200 movs r2, #0
- 80026f0: 665a str r2, [r3, #100] ; 0x64
+ 8002790: 687b ldr r3, [r7, #4]
+ 8002792: 2200 movs r2, #0
+ 8002794: 665a str r2, [r3, #100] ; 0x64
return ret;
- 80026f2: 7dfb ldrb r3, [r7, #23]
+ 8002796: 7dfb ldrb r3, [r7, #23]
}
- 80026f4: 4618 mov r0, r3
- 80026f6: 3720 adds r7, #32
- 80026f8: 46bd mov sp, r7
- 80026fa: bd80 pop {r7, pc}
- 80026fc: 01e84800 .word 0x01e84800
- 8002700: 00f42400 .word 0x00f42400
-
-08002704 <UART_AdvFeatureConfig>:
+ 8002798: 4618 mov r0, r3
+ 800279a: 3720 adds r7, #32
+ 800279c: 46bd mov sp, r7
+ 800279e: bd80 pop {r7, pc}
+ 80027a0: 01e84800 .word 0x01e84800
+ 80027a4: 00f42400 .word 0x00f42400
+
+080027a8 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
- 8002704: b480 push {r7}
- 8002706: b083 sub sp, #12
- 8002708: af00 add r7, sp, #0
- 800270a: 6078 str r0, [r7, #4]
+ 80027a8: b480 push {r7}
+ 80027aa: b083 sub sp, #12
+ 80027ac: af00 add r7, sp, #0
+ 80027ae: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 800270c: 687b ldr r3, [r7, #4]
- 800270e: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002710: f003 0301 and.w r3, r3, #1
- 8002714: 2b00 cmp r3, #0
- 8002716: d00a beq.n 800272e <UART_AdvFeatureConfig+0x2a>
+ 80027b0: 687b ldr r3, [r7, #4]
+ 80027b2: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80027b4: f003 0301 and.w r3, r3, #1
+ 80027b8: 2b00 cmp r3, #0
+ 80027ba: d00a beq.n 80027d2 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8002718: 687b ldr r3, [r7, #4]
- 800271a: 681b ldr r3, [r3, #0]
- 800271c: 685b ldr r3, [r3, #4]
- 800271e: f423 3100 bic.w r1, r3, #131072 ; 0x20000
- 8002722: 687b ldr r3, [r7, #4]
- 8002724: 6a9a ldr r2, [r3, #40] ; 0x28
- 8002726: 687b ldr r3, [r7, #4]
- 8002728: 681b ldr r3, [r3, #0]
- 800272a: 430a orrs r2, r1
- 800272c: 605a str r2, [r3, #4]
+ 80027bc: 687b ldr r3, [r7, #4]
+ 80027be: 681b ldr r3, [r3, #0]
+ 80027c0: 685b ldr r3, [r3, #4]
+ 80027c2: f423 3100 bic.w r1, r3, #131072 ; 0x20000
+ 80027c6: 687b ldr r3, [r7, #4]
+ 80027c8: 6a9a ldr r2, [r3, #40] ; 0x28
+ 80027ca: 687b ldr r3, [r7, #4]
+ 80027cc: 681b ldr r3, [r3, #0]
+ 80027ce: 430a orrs r2, r1
+ 80027d0: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 800272e: 687b ldr r3, [r7, #4]
- 8002730: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002732: f003 0302 and.w r3, r3, #2
- 8002736: 2b00 cmp r3, #0
- 8002738: d00a beq.n 8002750 <UART_AdvFeatureConfig+0x4c>
+ 80027d2: 687b ldr r3, [r7, #4]
+ 80027d4: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80027d6: f003 0302 and.w r3, r3, #2
+ 80027da: 2b00 cmp r3, #0
+ 80027dc: d00a beq.n 80027f4 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 800273a: 687b ldr r3, [r7, #4]
- 800273c: 681b ldr r3, [r3, #0]
- 800273e: 685b ldr r3, [r3, #4]
- 8002740: f423 3180 bic.w r1, r3, #65536 ; 0x10000
- 8002744: 687b ldr r3, [r7, #4]
- 8002746: 6ada ldr r2, [r3, #44] ; 0x2c
- 8002748: 687b ldr r3, [r7, #4]
- 800274a: 681b ldr r3, [r3, #0]
- 800274c: 430a orrs r2, r1
- 800274e: 605a str r2, [r3, #4]
+ 80027de: 687b ldr r3, [r7, #4]
+ 80027e0: 681b ldr r3, [r3, #0]
+ 80027e2: 685b ldr r3, [r3, #4]
+ 80027e4: f423 3180 bic.w r1, r3, #65536 ; 0x10000
+ 80027e8: 687b ldr r3, [r7, #4]
+ 80027ea: 6ada ldr r2, [r3, #44] ; 0x2c
+ 80027ec: 687b ldr r3, [r7, #4]
+ 80027ee: 681b ldr r3, [r3, #0]
+ 80027f0: 430a orrs r2, r1
+ 80027f2: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 8002750: 687b ldr r3, [r7, #4]
- 8002752: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002754: f003 0304 and.w r3, r3, #4
- 8002758: 2b00 cmp r3, #0
- 800275a: d00a beq.n 8002772 <UART_AdvFeatureConfig+0x6e>
+ 80027f4: 687b ldr r3, [r7, #4]
+ 80027f6: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80027f8: f003 0304 and.w r3, r3, #4
+ 80027fc: 2b00 cmp r3, #0
+ 80027fe: d00a beq.n 8002816 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 800275c: 687b ldr r3, [r7, #4]
- 800275e: 681b ldr r3, [r3, #0]
- 8002760: 685b ldr r3, [r3, #4]
- 8002762: f423 2180 bic.w r1, r3, #262144 ; 0x40000
- 8002766: 687b ldr r3, [r7, #4]
- 8002768: 6b1a ldr r2, [r3, #48] ; 0x30
- 800276a: 687b ldr r3, [r7, #4]
- 800276c: 681b ldr r3, [r3, #0]
- 800276e: 430a orrs r2, r1
- 8002770: 605a str r2, [r3, #4]
+ 8002800: 687b ldr r3, [r7, #4]
+ 8002802: 681b ldr r3, [r3, #0]
+ 8002804: 685b ldr r3, [r3, #4]
+ 8002806: f423 2180 bic.w r1, r3, #262144 ; 0x40000
+ 800280a: 687b ldr r3, [r7, #4]
+ 800280c: 6b1a ldr r2, [r3, #48] ; 0x30
+ 800280e: 687b ldr r3, [r7, #4]
+ 8002810: 681b ldr r3, [r3, #0]
+ 8002812: 430a orrs r2, r1
+ 8002814: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 8002772: 687b ldr r3, [r7, #4]
- 8002774: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002776: f003 0308 and.w r3, r3, #8
- 800277a: 2b00 cmp r3, #0
- 800277c: d00a beq.n 8002794 <UART_AdvFeatureConfig+0x90>
+ 8002816: 687b ldr r3, [r7, #4]
+ 8002818: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800281a: f003 0308 and.w r3, r3, #8
+ 800281e: 2b00 cmp r3, #0
+ 8002820: d00a beq.n 8002838 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 800277e: 687b ldr r3, [r7, #4]
- 8002780: 681b ldr r3, [r3, #0]
- 8002782: 685b ldr r3, [r3, #4]
- 8002784: f423 4100 bic.w r1, r3, #32768 ; 0x8000
- 8002788: 687b ldr r3, [r7, #4]
- 800278a: 6b5a ldr r2, [r3, #52] ; 0x34
- 800278c: 687b ldr r3, [r7, #4]
- 800278e: 681b ldr r3, [r3, #0]
- 8002790: 430a orrs r2, r1
- 8002792: 605a str r2, [r3, #4]
+ 8002822: 687b ldr r3, [r7, #4]
+ 8002824: 681b ldr r3, [r3, #0]
+ 8002826: 685b ldr r3, [r3, #4]
+ 8002828: f423 4100 bic.w r1, r3, #32768 ; 0x8000
+ 800282c: 687b ldr r3, [r7, #4]
+ 800282e: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8002830: 687b ldr r3, [r7, #4]
+ 8002832: 681b ldr r3, [r3, #0]
+ 8002834: 430a orrs r2, r1
+ 8002836: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 8002794: 687b ldr r3, [r7, #4]
- 8002796: 6a5b ldr r3, [r3, #36] ; 0x24
- 8002798: f003 0310 and.w r3, r3, #16
- 800279c: 2b00 cmp r3, #0
- 800279e: d00a beq.n 80027b6 <UART_AdvFeatureConfig+0xb2>
+ 8002838: 687b ldr r3, [r7, #4]
+ 800283a: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800283c: f003 0310 and.w r3, r3, #16
+ 8002840: 2b00 cmp r3, #0
+ 8002842: d00a beq.n 800285a <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 80027a0: 687b ldr r3, [r7, #4]
- 80027a2: 681b ldr r3, [r3, #0]
- 80027a4: 689b ldr r3, [r3, #8]
- 80027a6: f423 5180 bic.w r1, r3, #4096 ; 0x1000
- 80027aa: 687b ldr r3, [r7, #4]
- 80027ac: 6b9a ldr r2, [r3, #56] ; 0x38
- 80027ae: 687b ldr r3, [r7, #4]
- 80027b0: 681b ldr r3, [r3, #0]
- 80027b2: 430a orrs r2, r1
- 80027b4: 609a str r2, [r3, #8]
+ 8002844: 687b ldr r3, [r7, #4]
+ 8002846: 681b ldr r3, [r3, #0]
+ 8002848: 689b ldr r3, [r3, #8]
+ 800284a: f423 5180 bic.w r1, r3, #4096 ; 0x1000
+ 800284e: 687b ldr r3, [r7, #4]
+ 8002850: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8002852: 687b ldr r3, [r7, #4]
+ 8002854: 681b ldr r3, [r3, #0]
+ 8002856: 430a orrs r2, r1
+ 8002858: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 80027b6: 687b ldr r3, [r7, #4]
- 80027b8: 6a5b ldr r3, [r3, #36] ; 0x24
- 80027ba: f003 0320 and.w r3, r3, #32
- 80027be: 2b00 cmp r3, #0
- 80027c0: d00a beq.n 80027d8 <UART_AdvFeatureConfig+0xd4>
+ 800285a: 687b ldr r3, [r7, #4]
+ 800285c: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800285e: f003 0320 and.w r3, r3, #32
+ 8002862: 2b00 cmp r3, #0
+ 8002864: d00a beq.n 800287c <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 80027c2: 687b ldr r3, [r7, #4]
- 80027c4: 681b ldr r3, [r3, #0]
- 80027c6: 689b ldr r3, [r3, #8]
- 80027c8: f423 5100 bic.w r1, r3, #8192 ; 0x2000
- 80027cc: 687b ldr r3, [r7, #4]
- 80027ce: 6bda ldr r2, [r3, #60] ; 0x3c
- 80027d0: 687b ldr r3, [r7, #4]
- 80027d2: 681b ldr r3, [r3, #0]
- 80027d4: 430a orrs r2, r1
- 80027d6: 609a str r2, [r3, #8]
+ 8002866: 687b ldr r3, [r7, #4]
+ 8002868: 681b ldr r3, [r3, #0]
+ 800286a: 689b ldr r3, [r3, #8]
+ 800286c: f423 5100 bic.w r1, r3, #8192 ; 0x2000
+ 8002870: 687b ldr r3, [r7, #4]
+ 8002872: 6bda ldr r2, [r3, #60] ; 0x3c
+ 8002874: 687b ldr r3, [r7, #4]
+ 8002876: 681b ldr r3, [r3, #0]
+ 8002878: 430a orrs r2, r1
+ 800287a: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 80027d8: 687b ldr r3, [r7, #4]
- 80027da: 6a5b ldr r3, [r3, #36] ; 0x24
- 80027dc: f003 0340 and.w r3, r3, #64 ; 0x40
- 80027e0: 2b00 cmp r3, #0
- 80027e2: d01a beq.n 800281a <UART_AdvFeatureConfig+0x116>
+ 800287c: 687b ldr r3, [r7, #4]
+ 800287e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8002880: f003 0340 and.w r3, r3, #64 ; 0x40
+ 8002884: 2b00 cmp r3, #0
+ 8002886: d01a beq.n 80028be <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 80027e4: 687b ldr r3, [r7, #4]
- 80027e6: 681b ldr r3, [r3, #0]
- 80027e8: 685b ldr r3, [r3, #4]
- 80027ea: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
- 80027ee: 687b ldr r3, [r7, #4]
- 80027f0: 6c1a ldr r2, [r3, #64] ; 0x40
- 80027f2: 687b ldr r3, [r7, #4]
- 80027f4: 681b ldr r3, [r3, #0]
- 80027f6: 430a orrs r2, r1
- 80027f8: 605a str r2, [r3, #4]
+ 8002888: 687b ldr r3, [r7, #4]
+ 800288a: 681b ldr r3, [r3, #0]
+ 800288c: 685b ldr r3, [r3, #4]
+ 800288e: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
+ 8002892: 687b ldr r3, [r7, #4]
+ 8002894: 6c1a ldr r2, [r3, #64] ; 0x40
+ 8002896: 687b ldr r3, [r7, #4]
+ 8002898: 681b ldr r3, [r3, #0]
+ 800289a: 430a orrs r2, r1
+ 800289c: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 80027fa: 687b ldr r3, [r7, #4]
- 80027fc: 6c1b ldr r3, [r3, #64] ; 0x40
- 80027fe: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
- 8002802: d10a bne.n 800281a <UART_AdvFeatureConfig+0x116>
+ 800289e: 687b ldr r3, [r7, #4]
+ 80028a0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80028a2: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
+ 80028a6: d10a bne.n 80028be <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8002804: 687b ldr r3, [r7, #4]
- 8002806: 681b ldr r3, [r3, #0]
- 8002808: 685b ldr r3, [r3, #4]
- 800280a: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
- 800280e: 687b ldr r3, [r7, #4]
- 8002810: 6c5a ldr r2, [r3, #68] ; 0x44
- 8002812: 687b ldr r3, [r7, #4]
- 8002814: 681b ldr r3, [r3, #0]
- 8002816: 430a orrs r2, r1
- 8002818: 605a str r2, [r3, #4]
+ 80028a8: 687b ldr r3, [r7, #4]
+ 80028aa: 681b ldr r3, [r3, #0]
+ 80028ac: 685b ldr r3, [r3, #4]
+ 80028ae: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
+ 80028b2: 687b ldr r3, [r7, #4]
+ 80028b4: 6c5a ldr r2, [r3, #68] ; 0x44
+ 80028b6: 687b ldr r3, [r7, #4]
+ 80028b8: 681b ldr r3, [r3, #0]
+ 80028ba: 430a orrs r2, r1
+ 80028bc: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 800281a: 687b ldr r3, [r7, #4]
- 800281c: 6a5b ldr r3, [r3, #36] ; 0x24
- 800281e: f003 0380 and.w r3, r3, #128 ; 0x80
- 8002822: 2b00 cmp r3, #0
- 8002824: d00a beq.n 800283c <UART_AdvFeatureConfig+0x138>
+ 80028be: 687b ldr r3, [r7, #4]
+ 80028c0: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80028c2: f003 0380 and.w r3, r3, #128 ; 0x80
+ 80028c6: 2b00 cmp r3, #0
+ 80028c8: d00a beq.n 80028e0 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 8002826: 687b ldr r3, [r7, #4]
- 8002828: 681b ldr r3, [r3, #0]
- 800282a: 685b ldr r3, [r3, #4]
- 800282c: f423 2100 bic.w r1, r3, #524288 ; 0x80000
- 8002830: 687b ldr r3, [r7, #4]
- 8002832: 6c9a ldr r2, [r3, #72] ; 0x48
- 8002834: 687b ldr r3, [r7, #4]
- 8002836: 681b ldr r3, [r3, #0]
- 8002838: 430a orrs r2, r1
- 800283a: 605a str r2, [r3, #4]
+ 80028ca: 687b ldr r3, [r7, #4]
+ 80028cc: 681b ldr r3, [r3, #0]
+ 80028ce: 685b ldr r3, [r3, #4]
+ 80028d0: f423 2100 bic.w r1, r3, #524288 ; 0x80000
+ 80028d4: 687b ldr r3, [r7, #4]
+ 80028d6: 6c9a ldr r2, [r3, #72] ; 0x48
+ 80028d8: 687b ldr r3, [r7, #4]
+ 80028da: 681b ldr r3, [r3, #0]
+ 80028dc: 430a orrs r2, r1
+ 80028de: 605a str r2, [r3, #4]
}
}
- 800283c: bf00 nop
- 800283e: 370c adds r7, #12
- 8002840: 46bd mov sp, r7
- 8002842: f85d 7b04 ldr.w r7, [sp], #4
- 8002846: 4770 bx lr
+ 80028e0: bf00 nop
+ 80028e2: 370c adds r7, #12
+ 80028e4: 46bd mov sp, r7
+ 80028e6: f85d 7b04 ldr.w r7, [sp], #4
+ 80028ea: 4770 bx lr
-08002848 <UART_CheckIdleState>:
+080028ec <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
- 8002848: b580 push {r7, lr}
- 800284a: b086 sub sp, #24
- 800284c: af02 add r7, sp, #8
- 800284e: 6078 str r0, [r7, #4]
+ 80028ec: b580 push {r7, lr}
+ 80028ee: b086 sub sp, #24
+ 80028f0: af02 add r7, sp, #8
+ 80028f2: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8002850: 687b ldr r3, [r7, #4]
- 8002852: 2200 movs r2, #0
- 8002854: 67da str r2, [r3, #124] ; 0x7c
+ 80028f4: 687b ldr r3, [r7, #4]
+ 80028f6: 2200 movs r2, #0
+ 80028f8: 67da str r2, [r3, #124] ; 0x7c
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- 8002856: f7fe f8ad bl 80009b4 <HAL_GetTick>
- 800285a: 60f8 str r0, [r7, #12]
+ 80028fa: f7fe f8ad bl 8000a58 <HAL_GetTick>
+ 80028fe: 60f8 str r0, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 800285c: 687b ldr r3, [r7, #4]
- 800285e: 681b ldr r3, [r3, #0]
- 8002860: 681b ldr r3, [r3, #0]
- 8002862: f003 0308 and.w r3, r3, #8
- 8002866: 2b08 cmp r3, #8
- 8002868: d10e bne.n 8002888 <UART_CheckIdleState+0x40>
+ 8002900: 687b ldr r3, [r7, #4]
+ 8002902: 681b ldr r3, [r3, #0]
+ 8002904: 681b ldr r3, [r3, #0]
+ 8002906: f003 0308 and.w r3, r3, #8
+ 800290a: 2b08 cmp r3, #8
+ 800290c: d10e bne.n 800292c <UART_CheckIdleState+0x40>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 800286a: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
- 800286e: 9300 str r3, [sp, #0]
- 8002870: 68fb ldr r3, [r7, #12]
- 8002872: 2200 movs r2, #0
- 8002874: f44f 1100 mov.w r1, #2097152 ; 0x200000
- 8002878: 6878 ldr r0, [r7, #4]
- 800287a: f000 f814 bl 80028a6 <UART_WaitOnFlagUntilTimeout>
- 800287e: 4603 mov r3, r0
- 8002880: 2b00 cmp r3, #0
- 8002882: d001 beq.n 8002888 <UART_CheckIdleState+0x40>
+ 800290e: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
+ 8002912: 9300 str r3, [sp, #0]
+ 8002914: 68fb ldr r3, [r7, #12]
+ 8002916: 2200 movs r2, #0
+ 8002918: f44f 1100 mov.w r1, #2097152 ; 0x200000
+ 800291c: 6878 ldr r0, [r7, #4]
+ 800291e: f000 f814 bl 800294a <UART_WaitOnFlagUntilTimeout>
+ 8002922: 4603 mov r3, r0
+ 8002924: 2b00 cmp r3, #0
+ 8002926: d001 beq.n 800292c <UART_CheckIdleState+0x40>
{
/* Timeout occurred */
return HAL_TIMEOUT;
- 8002884: 2303 movs r3, #3
- 8002886: e00a b.n 800289e <UART_CheckIdleState+0x56>
+ 8002928: 2303 movs r3, #3
+ 800292a: e00a b.n 8002942 <UART_CheckIdleState+0x56>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
- 8002888: 687b ldr r3, [r7, #4]
- 800288a: 2220 movs r2, #32
- 800288c: 675a str r2, [r3, #116] ; 0x74
+ 800292c: 687b ldr r3, [r7, #4]
+ 800292e: 2220 movs r2, #32
+ 8002930: 675a str r2, [r3, #116] ; 0x74
huart->RxState = HAL_UART_STATE_READY;
- 800288e: 687b ldr r3, [r7, #4]
- 8002890: 2220 movs r2, #32
- 8002892: 679a str r2, [r3, #120] ; 0x78
+ 8002932: 687b ldr r3, [r7, #4]
+ 8002934: 2220 movs r2, #32
+ 8002936: 679a str r2, [r3, #120] ; 0x78
/* Process Unlocked */
__HAL_UNLOCK(huart);
- 8002894: 687b ldr r3, [r7, #4]
- 8002896: 2200 movs r2, #0
- 8002898: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 8002938: 687b ldr r3, [r7, #4]
+ 800293a: 2200 movs r2, #0
+ 800293c: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_OK;
- 800289c: 2300 movs r3, #0
+ 8002940: 2300 movs r3, #0
}
- 800289e: 4618 mov r0, r3
- 80028a0: 3710 adds r7, #16
- 80028a2: 46bd mov sp, r7
- 80028a4: bd80 pop {r7, pc}
+ 8002942: 4618 mov r0, r3
+ 8002944: 3710 adds r7, #16
+ 8002946: 46bd mov sp, r7
+ 8002948: bd80 pop {r7, pc}
-080028a6 <UART_WaitOnFlagUntilTimeout>:
+0800294a <UART_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- 80028a6: b580 push {r7, lr}
- 80028a8: b084 sub sp, #16
- 80028aa: af00 add r7, sp, #0
- 80028ac: 60f8 str r0, [r7, #12]
- 80028ae: 60b9 str r1, [r7, #8]
- 80028b0: 603b str r3, [r7, #0]
- 80028b2: 4613 mov r3, r2
- 80028b4: 71fb strb r3, [r7, #7]
+ 800294a: b580 push {r7, lr}
+ 800294c: b084 sub sp, #16
+ 800294e: af00 add r7, sp, #0
+ 8002950: 60f8 str r0, [r7, #12]
+ 8002952: 60b9 str r1, [r7, #8]
+ 8002954: 603b str r3, [r7, #0]
+ 8002956: 4613 mov r3, r2
+ 8002958: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 80028b6: e02a b.n 800290e <UART_WaitOnFlagUntilTimeout+0x68>
+ 800295a: e02a b.n 80029b2 <UART_WaitOnFlagUntilTimeout+0x68>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
- 80028b8: 69bb ldr r3, [r7, #24]
- 80028ba: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 80028be: d026 beq.n 800290e <UART_WaitOnFlagUntilTimeout+0x68>
+ 800295c: 69bb ldr r3, [r7, #24]
+ 800295e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
+ 8002962: d026 beq.n 80029b2 <UART_WaitOnFlagUntilTimeout+0x68>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 80028c0: f7fe f878 bl 80009b4 <HAL_GetTick>
- 80028c4: 4602 mov r2, r0
- 80028c6: 683b ldr r3, [r7, #0]
- 80028c8: 1ad3 subs r3, r2, r3
- 80028ca: 69ba ldr r2, [r7, #24]
- 80028cc: 429a cmp r2, r3
- 80028ce: d302 bcc.n 80028d6 <UART_WaitOnFlagUntilTimeout+0x30>
- 80028d0: 69bb ldr r3, [r7, #24]
- 80028d2: 2b00 cmp r3, #0
- 80028d4: d11b bne.n 800290e <UART_WaitOnFlagUntilTimeout+0x68>
+ 8002964: f7fe f878 bl 8000a58 <HAL_GetTick>
+ 8002968: 4602 mov r2, r0
+ 800296a: 683b ldr r3, [r7, #0]
+ 800296c: 1ad3 subs r3, r2, r3
+ 800296e: 69ba ldr r2, [r7, #24]
+ 8002970: 429a cmp r2, r3
+ 8002972: d302 bcc.n 800297a <UART_WaitOnFlagUntilTimeout+0x30>
+ 8002974: 69bb ldr r3, [r7, #24]
+ 8002976: 2b00 cmp r3, #0
+ 8002978: d11b bne.n 80029b2 <UART_WaitOnFlagUntilTimeout+0x68>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 80028d6: 68fb ldr r3, [r7, #12]
- 80028d8: 681b ldr r3, [r3, #0]
- 80028da: 681a ldr r2, [r3, #0]
- 80028dc: 68fb ldr r3, [r7, #12]
- 80028de: 681b ldr r3, [r3, #0]
- 80028e0: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
- 80028e4: 601a str r2, [r3, #0]
+ 800297a: 68fb ldr r3, [r7, #12]
+ 800297c: 681b ldr r3, [r3, #0]
+ 800297e: 681a ldr r2, [r3, #0]
+ 8002980: 68fb ldr r3, [r7, #12]
+ 8002982: 681b ldr r3, [r3, #0]
+ 8002984: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
+ 8002988: 601a str r2, [r3, #0]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80028e6: 68fb ldr r3, [r7, #12]
- 80028e8: 681b ldr r3, [r3, #0]
- 80028ea: 689a ldr r2, [r3, #8]
- 80028ec: 68fb ldr r3, [r7, #12]
- 80028ee: 681b ldr r3, [r3, #0]
- 80028f0: f022 0201 bic.w r2, r2, #1
- 80028f4: 609a str r2, [r3, #8]
+ 800298a: 68fb ldr r3, [r7, #12]
+ 800298c: 681b ldr r3, [r3, #0]
+ 800298e: 689a ldr r2, [r3, #8]
+ 8002990: 68fb ldr r3, [r7, #12]
+ 8002992: 681b ldr r3, [r3, #0]
+ 8002994: f022 0201 bic.w r2, r2, #1
+ 8002998: 609a str r2, [r3, #8]
huart->gState = HAL_UART_STATE_READY;
- 80028f6: 68fb ldr r3, [r7, #12]
- 80028f8: 2220 movs r2, #32
- 80028fa: 675a str r2, [r3, #116] ; 0x74
+ 800299a: 68fb ldr r3, [r7, #12]
+ 800299c: 2220 movs r2, #32
+ 800299e: 675a str r2, [r3, #116] ; 0x74
huart->RxState = HAL_UART_STATE_READY;
- 80028fc: 68fb ldr r3, [r7, #12]
- 80028fe: 2220 movs r2, #32
- 8002900: 679a str r2, [r3, #120] ; 0x78
+ 80029a0: 68fb ldr r3, [r7, #12]
+ 80029a2: 2220 movs r2, #32
+ 80029a4: 679a str r2, [r3, #120] ; 0x78
/* Process Unlocked */
__HAL_UNLOCK(huart);
- 8002902: 68fb ldr r3, [r7, #12]
- 8002904: 2200 movs r2, #0
- 8002906: f883 2070 strb.w r2, [r3, #112] ; 0x70
+ 80029a6: 68fb ldr r3, [r7, #12]
+ 80029a8: 2200 movs r2, #0
+ 80029aa: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_TIMEOUT;
- 800290a: 2303 movs r3, #3
- 800290c: e00f b.n 800292e <UART_WaitOnFlagUntilTimeout+0x88>
+ 80029ae: 2303 movs r3, #3
+ 80029b0: e00f b.n 80029d2 <UART_WaitOnFlagUntilTimeout+0x88>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 800290e: 68fb ldr r3, [r7, #12]
- 8002910: 681b ldr r3, [r3, #0]
- 8002912: 69da ldr r2, [r3, #28]
- 8002914: 68bb ldr r3, [r7, #8]
- 8002916: 4013 ands r3, r2
- 8002918: 68ba ldr r2, [r7, #8]
- 800291a: 429a cmp r2, r3
- 800291c: bf0c ite eq
- 800291e: 2301 moveq r3, #1
- 8002920: 2300 movne r3, #0
- 8002922: b2db uxtb r3, r3
- 8002924: 461a mov r2, r3
- 8002926: 79fb ldrb r3, [r7, #7]
- 8002928: 429a cmp r2, r3
- 800292a: d0c5 beq.n 80028b8 <UART_WaitOnFlagUntilTimeout+0x12>
+ 80029b2: 68fb ldr r3, [r7, #12]
+ 80029b4: 681b ldr r3, [r3, #0]
+ 80029b6: 69da ldr r2, [r3, #28]
+ 80029b8: 68bb ldr r3, [r7, #8]
+ 80029ba: 4013 ands r3, r2
+ 80029bc: 68ba ldr r2, [r7, #8]
+ 80029be: 429a cmp r2, r3
+ 80029c0: bf0c ite eq
+ 80029c2: 2301 moveq r3, #1
+ 80029c4: 2300 movne r3, #0
+ 80029c6: b2db uxtb r3, r3
+ 80029c8: 461a mov r2, r3
+ 80029ca: 79fb ldrb r3, [r7, #7]
+ 80029cc: 429a cmp r2, r3
+ 80029ce: d0c5 beq.n 800295c <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
- 800292c: 2300 movs r3, #0
+ 80029d0: 2300 movs r3, #0
}
- 800292e: 4618 mov r0, r3
- 8002930: 3710 adds r7, #16
- 8002932: 46bd mov sp, r7
- 8002934: bd80 pop {r7, pc}
+ 80029d2: 4618 mov r0, r3
+ 80029d4: 3710 adds r7, #16
+ 80029d6: 46bd mov sp, r7
+ 80029d8: bd80 pop {r7, pc}
...
-08002938 <__libc_init_array>:
- 8002938: b570 push {r4, r5, r6, lr}
- 800293a: 4e0d ldr r6, [pc, #52] ; (8002970 <__libc_init_array+0x38>)
- 800293c: 4c0d ldr r4, [pc, #52] ; (8002974 <__libc_init_array+0x3c>)
- 800293e: 1ba4 subs r4, r4, r6
- 8002940: 10a4 asrs r4, r4, #2
- 8002942: 2500 movs r5, #0
- 8002944: 42a5 cmp r5, r4
- 8002946: d109 bne.n 800295c <__libc_init_array+0x24>
- 8002948: 4e0b ldr r6, [pc, #44] ; (8002978 <__libc_init_array+0x40>)
- 800294a: 4c0c ldr r4, [pc, #48] ; (800297c <__libc_init_array+0x44>)
- 800294c: f000 f820 bl 8002990 <_init>
- 8002950: 1ba4 subs r4, r4, r6
- 8002952: 10a4 asrs r4, r4, #2
- 8002954: 2500 movs r5, #0
- 8002956: 42a5 cmp r5, r4
- 8002958: d105 bne.n 8002966 <__libc_init_array+0x2e>
- 800295a: bd70 pop {r4, r5, r6, pc}
- 800295c: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8002960: 4798 blx r3
- 8002962: 3501 adds r5, #1
- 8002964: e7ee b.n 8002944 <__libc_init_array+0xc>
- 8002966: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 800296a: 4798 blx r3
- 800296c: 3501 adds r5, #1
- 800296e: e7f2 b.n 8002956 <__libc_init_array+0x1e>
- 8002970: 080029d8 .word 0x080029d8
- 8002974: 080029d8 .word 0x080029d8
- 8002978: 080029d8 .word 0x080029d8
- 800297c: 080029dc .word 0x080029dc
-
-08002980 <memset>:
- 8002980: 4402 add r2, r0
- 8002982: 4603 mov r3, r0
- 8002984: 4293 cmp r3, r2
- 8002986: d100 bne.n 800298a <memset+0xa>
- 8002988: 4770 bx lr
- 800298a: f803 1b01 strb.w r1, [r3], #1
- 800298e: e7f9 b.n 8002984 <memset+0x4>
-
-08002990 <_init>:
- 8002990: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8002992: bf00 nop
- 8002994: bcf8 pop {r3, r4, r5, r6, r7}
- 8002996: bc08 pop {r3}
- 8002998: 469e mov lr, r3
- 800299a: 4770 bx lr
-
-0800299c <_fini>:
- 800299c: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800299e: bf00 nop
- 80029a0: bcf8 pop {r3, r4, r5, r6, r7}
- 80029a2: bc08 pop {r3}
- 80029a4: 469e mov lr, r3
- 80029a6: 4770 bx lr
+080029dc <__libc_init_array>:
+ 80029dc: b570 push {r4, r5, r6, lr}
+ 80029de: 4e0d ldr r6, [pc, #52] ; (8002a14 <__libc_init_array+0x38>)
+ 80029e0: 4c0d ldr r4, [pc, #52] ; (8002a18 <__libc_init_array+0x3c>)
+ 80029e2: 1ba4 subs r4, r4, r6
+ 80029e4: 10a4 asrs r4, r4, #2
+ 80029e6: 2500 movs r5, #0
+ 80029e8: 42a5 cmp r5, r4
+ 80029ea: d109 bne.n 8002a00 <__libc_init_array+0x24>
+ 80029ec: 4e0b ldr r6, [pc, #44] ; (8002a1c <__libc_init_array+0x40>)
+ 80029ee: 4c0c ldr r4, [pc, #48] ; (8002a20 <__libc_init_array+0x44>)
+ 80029f0: f000 f820 bl 8002a34 <_init>
+ 80029f4: 1ba4 subs r4, r4, r6
+ 80029f6: 10a4 asrs r4, r4, #2
+ 80029f8: 2500 movs r5, #0
+ 80029fa: 42a5 cmp r5, r4
+ 80029fc: d105 bne.n 8002a0a <__libc_init_array+0x2e>
+ 80029fe: bd70 pop {r4, r5, r6, pc}
+ 8002a00: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8002a04: 4798 blx r3
+ 8002a06: 3501 adds r5, #1
+ 8002a08: e7ee b.n 80029e8 <__libc_init_array+0xc>
+ 8002a0a: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8002a0e: 4798 blx r3
+ 8002a10: 3501 adds r5, #1
+ 8002a12: e7f2 b.n 80029fa <__libc_init_array+0x1e>
+ 8002a14: 08002a7c .word 0x08002a7c
+ 8002a18: 08002a7c .word 0x08002a7c
+ 8002a1c: 08002a7c .word 0x08002a7c
+ 8002a20: 08002a80 .word 0x08002a80
+
+08002a24 <memset>:
+ 8002a24: 4402 add r2, r0
+ 8002a26: 4603 mov r3, r0
+ 8002a28: 4293 cmp r3, r2
+ 8002a2a: d100 bne.n 8002a2e <memset+0xa>
+ 8002a2c: 4770 bx lr
+ 8002a2e: f803 1b01 strb.w r1, [r3], #1
+ 8002a32: e7f9 b.n 8002a28 <memset+0x4>
+
+08002a34 <_init>:
+ 8002a34: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8002a36: bf00 nop
+ 8002a38: bcf8 pop {r3, r4, r5, r6, r7}
+ 8002a3a: bc08 pop {r3}
+ 8002a3c: 469e mov lr, r3
+ 8002a3e: 4770 bx lr
+
+08002a40 <_fini>:
+ 8002a40: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8002a42: bf00 nop
+ 8002a44: bcf8 pop {r3, r4, r5, r6, r7}
+ 8002a46: bc08 pop {r3}
+ 8002a48: 469e mov lr, r3
+ 8002a4a: 4770 bx lr
projects / pioneer-stm32 / commitdiff