Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001f8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 00002054 080001f8 080001f8 000101f8 2**2
+ 1 .text 000020c4 080001f8 080001f8 000101f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 00000010 0800224c 0800224c 0001224c 2**2
+ 2 .rodata 00000010 080022bc 080022bc 000122bc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 0800225c 0800225c 0002000c 2**0
+ 3 .ARM.extab 00000000 080022cc 080022cc 0002000c 2**0
CONTENTS
- 4 .ARM 00000008 0800225c 0800225c 0001225c 2**2
+ 4 .ARM 00000008 080022cc 080022cc 000122cc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 08002264 08002264 0002000c 2**0
+ 5 .preinit_array 00000000 080022d4 080022d4 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000004 08002264 08002264 00012264 2**2
+ 6 .init_array 00000004 080022d4 080022d4 000122d4 2**2
CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 08002268 08002268 00012268 2**2
+ 7 .fini_array 00000004 080022d8 080022d8 000122d8 2**2
CONTENTS, ALLOC, LOAD, DATA
- 8 .data 0000000c 20000000 0800226c 00020000 2**2
+ 8 .data 0000000c 20000000 080022dc 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 00000060 2000000c 08002278 0002000c 2**2
+ 9 .bss 00000060 2000000c 080022e8 0002000c 2**2
ALLOC
- 10 ._user_heap_stack 00000604 2000006c 08002278 0002006c 2**0
+ 10 ._user_heap_stack 00000604 2000006c 080022e8 0002006c 2**0
ALLOC
11 .ARM.attributes 0000002e 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
- 12 .debug_info 00008498 00000000 00000000 0002003a 2**0
+ 12 .debug_info 00008b7e 00000000 00000000 0002003a 2**0
CONTENTS, READONLY, DEBUGGING
- 13 .debug_abbrev 0000130e 00000000 00000000 000284d2 2**0
+ 13 .debug_abbrev 0000145f 00000000 00000000 00028bb8 2**0
CONTENTS, READONLY, DEBUGGING
- 14 .debug_aranges 00000958 00000000 00000000 000297e0 2**3
+ 14 .debug_aranges 00000970 00000000 00000000 0002a018 2**3
CONTENTS, READONLY, DEBUGGING
- 15 .debug_ranges 000008b0 00000000 00000000 0002a138 2**3
+ 15 .debug_ranges 000008b8 00000000 00000000 0002a988 2**3
CONTENTS, READONLY, DEBUGGING
- 16 .debug_macro 00025363 00000000 00000000 0002a9e8 2**0
+ 16 .debug_macro 00025536 00000000 00000000 0002b240 2**0
CONTENTS, READONLY, DEBUGGING
- 17 .debug_line 000067ba 00000000 00000000 0004fd4b 2**0
+ 17 .debug_line 00006e2c 00000000 00000000 00050776 2**0
CONTENTS, READONLY, DEBUGGING
- 18 .debug_str 000eb697 00000000 00000000 00056505 2**0
+ 18 .debug_str 000eb6a0 00000000 00000000 000575a2 2**0
CONTENTS, READONLY, DEBUGGING
- 19 .comment 0000007b 00000000 00000000 00141b9c 2**0
+ 19 .comment 0000007b 00000000 00000000 00142c42 2**0
CONTENTS, READONLY
- 20 .debug_frame 000026e8 00000000 00000000 00141c18 2**2
+ 20 .debug_frame 00002708 00000000 00000000 00142cc0 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
800020e: bd10 pop {r4, pc}
8000210: 2000000c .word 0x2000000c
8000214: 00000000 .word 0x00000000
- 8000218: 08002234 .word 0x08002234
+ 8000218: 080022a4 .word 0x080022a4
0800021c <frame_dummy>:
800021c: b508 push {r3, lr}
800022a: bd08 pop {r3, pc}
800022c: 00000000 .word 0x00000000
8000230: 20000010 .word 0x20000010
- 8000234: 08002234 .word 0x08002234
+ 8000234: 080022a4 .word 0x080022a4
08000238 <__aeabi_uldivmod>:
8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800053c: 2003 movs r0, #3
- 800053e: f000 f92d bl 800079c <HAL_NVIC_SetPriorityGrouping>
+ 800053e: f000 f90b bl 8000758 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
/* Init the low level hardware */
HAL_MspInit();
- 8000548: f001 fd3e bl 8001fc8 <HAL_MspInit>
+ 8000548: f001 fd76 bl 8002038 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800056a: fbb3 f3f1 udiv r3, r3, r1
800056e: fbb2 f3f3 udiv r3, r2, r3
8000572: 4618 mov r0, r3
- 8000574: f000 f939 bl 80007ea <HAL_SYSTICK_Config>
+ 8000574: f000 f917 bl 80007a6 <HAL_SYSTICK_Config>
8000578: 4603 mov r3, r0
800057a: 2b00 cmp r3, #0
800057c: d001 beq.n 8000582 <HAL_InitTick+0x2e>
8000588: 2200 movs r2, #0
800058a: 6879 ldr r1, [r7, #4]
800058c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 8000590: f000 f90f bl 80007b2 <HAL_NVIC_SetPriority>
+ 8000590: f000 f8ed bl 800076e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000594: 4a06 ldr r2, [pc, #24] ; (80005b0 <HAL_InitTick+0x5c>)
8000596: 687b ldr r3, [r7, #4]
80005ee: bf00 nop
80005f0: 20000028 .word 0x20000028
-080005f4 <HAL_Delay>:
- * implementations in user file.
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-__weak void HAL_Delay(uint32_t Delay)
-{
- 80005f4: b580 push {r7, lr}
- 80005f6: b084 sub sp, #16
- 80005f8: af00 add r7, sp, #0
- 80005fa: 6078 str r0, [r7, #4]
- uint32_t tickstart = HAL_GetTick();
- 80005fc: f7ff ffee bl 80005dc <HAL_GetTick>
- 8000600: 60b8 str r0, [r7, #8]
- uint32_t wait = Delay;
- 8000602: 687b ldr r3, [r7, #4]
- 8000604: 60fb str r3, [r7, #12]
-
- /* Add a freq to guarantee minimum wait */
- if (wait < HAL_MAX_DELAY)
- 8000606: 68fb ldr r3, [r7, #12]
- 8000608: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
- 800060c: d005 beq.n 800061a <HAL_Delay+0x26>
- {
- wait += (uint32_t)(uwTickFreq);
- 800060e: 4b09 ldr r3, [pc, #36] ; (8000634 <HAL_Delay+0x40>)
- 8000610: 781b ldrb r3, [r3, #0]
- 8000612: 461a mov r2, r3
- 8000614: 68fb ldr r3, [r7, #12]
- 8000616: 4413 add r3, r2
- 8000618: 60fb str r3, [r7, #12]
- }
-
- while ((HAL_GetTick() - tickstart) < wait)
- 800061a: bf00 nop
- 800061c: f7ff ffde bl 80005dc <HAL_GetTick>
- 8000620: 4602 mov r2, r0
- 8000622: 68bb ldr r3, [r7, #8]
- 8000624: 1ad3 subs r3, r2, r3
- 8000626: 68fa ldr r2, [r7, #12]
- 8000628: 429a cmp r2, r3
- 800062a: d8f7 bhi.n 800061c <HAL_Delay+0x28>
- {
- }
-}
- 800062c: bf00 nop
- 800062e: 3710 adds r7, #16
- 8000630: 46bd mov sp, r7
- 8000632: bd80 pop {r7, pc}
- 8000634: 20000004 .word 0x20000004
-
-08000638 <__NVIC_SetPriorityGrouping>:
+080005f4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
- 8000638: b480 push {r7}
- 800063a: b085 sub sp, #20
- 800063c: af00 add r7, sp, #0
- 800063e: 6078 str r0, [r7, #4]
+ 80005f4: b480 push {r7}
+ 80005f6: b085 sub sp, #20
+ 80005f8: af00 add r7, sp, #0
+ 80005fa: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 8000640: 687b ldr r3, [r7, #4]
- 8000642: f003 0307 and.w r3, r3, #7
- 8000646: 60fb str r3, [r7, #12]
+ 80005fc: 687b ldr r3, [r7, #4]
+ 80005fe: f003 0307 and.w r3, r3, #7
+ 8000602: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
- 8000648: 4b0b ldr r3, [pc, #44] ; (8000678 <__NVIC_SetPriorityGrouping+0x40>)
- 800064a: 68db ldr r3, [r3, #12]
- 800064c: 60bb str r3, [r7, #8]
+ 8000604: 4b0b ldr r3, [pc, #44] ; (8000634 <__NVIC_SetPriorityGrouping+0x40>)
+ 8000606: 68db ldr r3, [r3, #12]
+ 8000608: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- 800064e: 68ba ldr r2, [r7, #8]
- 8000650: f64f 03ff movw r3, #63743 ; 0xf8ff
- 8000654: 4013 ands r3, r2
- 8000656: 60bb str r3, [r7, #8]
+ 800060a: 68ba ldr r2, [r7, #8]
+ 800060c: f64f 03ff movw r3, #63743 ; 0xf8ff
+ 8000610: 4013 ands r3, r2
+ 8000612: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- 8000658: 68fb ldr r3, [r7, #12]
- 800065a: 021a lsls r2, r3, #8
+ 8000614: 68fb ldr r3, [r7, #12]
+ 8000616: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 800065c: 68bb ldr r3, [r7, #8]
- 800065e: 431a orrs r2, r3
+ 8000618: 68bb ldr r3, [r7, #8]
+ 800061a: 431a orrs r2, r3
reg_value = (reg_value |
- 8000660: 4b06 ldr r3, [pc, #24] ; (800067c <__NVIC_SetPriorityGrouping+0x44>)
- 8000662: 4313 orrs r3, r2
- 8000664: 60bb str r3, [r7, #8]
+ 800061c: 4b06 ldr r3, [pc, #24] ; (8000638 <__NVIC_SetPriorityGrouping+0x44>)
+ 800061e: 4313 orrs r3, r2
+ 8000620: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
- 8000666: 4a04 ldr r2, [pc, #16] ; (8000678 <__NVIC_SetPriorityGrouping+0x40>)
- 8000668: 68bb ldr r3, [r7, #8]
- 800066a: 60d3 str r3, [r2, #12]
+ 8000622: 4a04 ldr r2, [pc, #16] ; (8000634 <__NVIC_SetPriorityGrouping+0x40>)
+ 8000624: 68bb ldr r3, [r7, #8]
+ 8000626: 60d3 str r3, [r2, #12]
}
- 800066c: bf00 nop
- 800066e: 3714 adds r7, #20
- 8000670: 46bd mov sp, r7
- 8000672: f85d 7b04 ldr.w r7, [sp], #4
- 8000676: 4770 bx lr
- 8000678: e000ed00 .word 0xe000ed00
- 800067c: 05fa0000 .word 0x05fa0000
-
-08000680 <__NVIC_GetPriorityGrouping>:
+ 8000628: bf00 nop
+ 800062a: 3714 adds r7, #20
+ 800062c: 46bd mov sp, r7
+ 800062e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000632: 4770 bx lr
+ 8000634: e000ed00 .word 0xe000ed00
+ 8000638: 05fa0000 .word 0x05fa0000
+
+0800063c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
- 8000680: b480 push {r7}
- 8000682: af00 add r7, sp, #0
+ 800063c: b480 push {r7}
+ 800063e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 8000684: 4b04 ldr r3, [pc, #16] ; (8000698 <__NVIC_GetPriorityGrouping+0x18>)
- 8000686: 68db ldr r3, [r3, #12]
- 8000688: 0a1b lsrs r3, r3, #8
- 800068a: f003 0307 and.w r3, r3, #7
+ 8000640: 4b04 ldr r3, [pc, #16] ; (8000654 <__NVIC_GetPriorityGrouping+0x18>)
+ 8000642: 68db ldr r3, [r3, #12]
+ 8000644: 0a1b lsrs r3, r3, #8
+ 8000646: f003 0307 and.w r3, r3, #7
}
- 800068e: 4618 mov r0, r3
- 8000690: 46bd mov sp, r7
- 8000692: f85d 7b04 ldr.w r7, [sp], #4
- 8000696: 4770 bx lr
- 8000698: e000ed00 .word 0xe000ed00
+ 800064a: 4618 mov r0, r3
+ 800064c: 46bd mov sp, r7
+ 800064e: f85d 7b04 ldr.w r7, [sp], #4
+ 8000652: 4770 bx lr
+ 8000654: e000ed00 .word 0xe000ed00
-0800069c <__NVIC_SetPriority>:
+08000658 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- 800069c: b480 push {r7}
- 800069e: b083 sub sp, #12
- 80006a0: af00 add r7, sp, #0
- 80006a2: 4603 mov r3, r0
- 80006a4: 6039 str r1, [r7, #0]
- 80006a6: 71fb strb r3, [r7, #7]
+ 8000658: b480 push {r7}
+ 800065a: b083 sub sp, #12
+ 800065c: af00 add r7, sp, #0
+ 800065e: 4603 mov r3, r0
+ 8000660: 6039 str r1, [r7, #0]
+ 8000662: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
- 80006a8: f997 3007 ldrsb.w r3, [r7, #7]
- 80006ac: 2b00 cmp r3, #0
- 80006ae: db0a blt.n 80006c6 <__NVIC_SetPriority+0x2a>
+ 8000664: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000668: 2b00 cmp r3, #0
+ 800066a: db0a blt.n 8000682 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 80006b0: 683b ldr r3, [r7, #0]
- 80006b2: b2da uxtb r2, r3
- 80006b4: 490c ldr r1, [pc, #48] ; (80006e8 <__NVIC_SetPriority+0x4c>)
- 80006b6: f997 3007 ldrsb.w r3, [r7, #7]
- 80006ba: 0112 lsls r2, r2, #4
- 80006bc: b2d2 uxtb r2, r2
- 80006be: 440b add r3, r1
- 80006c0: f883 2300 strb.w r2, [r3, #768] ; 0x300
+ 800066c: 683b ldr r3, [r7, #0]
+ 800066e: b2da uxtb r2, r3
+ 8000670: 490c ldr r1, [pc, #48] ; (80006a4 <__NVIC_SetPriority+0x4c>)
+ 8000672: f997 3007 ldrsb.w r3, [r7, #7]
+ 8000676: 0112 lsls r2, r2, #4
+ 8000678: b2d2 uxtb r2, r2
+ 800067a: 440b add r3, r1
+ 800067c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
- 80006c4: e00a b.n 80006dc <__NVIC_SetPriority+0x40>
+ 8000680: e00a b.n 8000698 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 80006c6: 683b ldr r3, [r7, #0]
- 80006c8: b2da uxtb r2, r3
- 80006ca: 4908 ldr r1, [pc, #32] ; (80006ec <__NVIC_SetPriority+0x50>)
- 80006cc: 79fb ldrb r3, [r7, #7]
- 80006ce: f003 030f and.w r3, r3, #15
- 80006d2: 3b04 subs r3, #4
- 80006d4: 0112 lsls r2, r2, #4
- 80006d6: b2d2 uxtb r2, r2
- 80006d8: 440b add r3, r1
- 80006da: 761a strb r2, [r3, #24]
+ 8000682: 683b ldr r3, [r7, #0]
+ 8000684: b2da uxtb r2, r3
+ 8000686: 4908 ldr r1, [pc, #32] ; (80006a8 <__NVIC_SetPriority+0x50>)
+ 8000688: 79fb ldrb r3, [r7, #7]
+ 800068a: f003 030f and.w r3, r3, #15
+ 800068e: 3b04 subs r3, #4
+ 8000690: 0112 lsls r2, r2, #4
+ 8000692: b2d2 uxtb r2, r2
+ 8000694: 440b add r3, r1
+ 8000696: 761a strb r2, [r3, #24]
}
- 80006dc: bf00 nop
- 80006de: 370c adds r7, #12
- 80006e0: 46bd mov sp, r7
- 80006e2: f85d 7b04 ldr.w r7, [sp], #4
- 80006e6: 4770 bx lr
- 80006e8: e000e100 .word 0xe000e100
- 80006ec: e000ed00 .word 0xe000ed00
-
-080006f0 <NVIC_EncodePriority>:
+ 8000698: bf00 nop
+ 800069a: 370c adds r7, #12
+ 800069c: 46bd mov sp, r7
+ 800069e: f85d 7b04 ldr.w r7, [sp], #4
+ 80006a2: 4770 bx lr
+ 80006a4: e000e100 .word 0xe000e100
+ 80006a8: e000ed00 .word 0xe000ed00
+
+080006ac <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- 80006f0: b480 push {r7}
- 80006f2: b089 sub sp, #36 ; 0x24
- 80006f4: af00 add r7, sp, #0
- 80006f6: 60f8 str r0, [r7, #12]
- 80006f8: 60b9 str r1, [r7, #8]
- 80006fa: 607a str r2, [r7, #4]
+ 80006ac: b480 push {r7}
+ 80006ae: b089 sub sp, #36 ; 0x24
+ 80006b0: af00 add r7, sp, #0
+ 80006b2: 60f8 str r0, [r7, #12]
+ 80006b4: 60b9 str r1, [r7, #8]
+ 80006b6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- 80006fc: 68fb ldr r3, [r7, #12]
- 80006fe: f003 0307 and.w r3, r3, #7
- 8000702: 61fb str r3, [r7, #28]
+ 80006b8: 68fb ldr r3, [r7, #12]
+ 80006ba: f003 0307 and.w r3, r3, #7
+ 80006be: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8000704: 69fb ldr r3, [r7, #28]
- 8000706: f1c3 0307 rsb r3, r3, #7
- 800070a: 2b04 cmp r3, #4
- 800070c: bf28 it cs
- 800070e: 2304 movcs r3, #4
- 8000710: 61bb str r3, [r7, #24]
+ 80006c0: 69fb ldr r3, [r7, #28]
+ 80006c2: f1c3 0307 rsb r3, r3, #7
+ 80006c6: 2b04 cmp r3, #4
+ 80006c8: bf28 it cs
+ 80006ca: 2304 movcs r3, #4
+ 80006cc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8000712: 69fb ldr r3, [r7, #28]
- 8000714: 3304 adds r3, #4
- 8000716: 2b06 cmp r3, #6
- 8000718: d902 bls.n 8000720 <NVIC_EncodePriority+0x30>
- 800071a: 69fb ldr r3, [r7, #28]
- 800071c: 3b03 subs r3, #3
- 800071e: e000 b.n 8000722 <NVIC_EncodePriority+0x32>
- 8000720: 2300 movs r3, #0
- 8000722: 617b str r3, [r7, #20]
+ 80006ce: 69fb ldr r3, [r7, #28]
+ 80006d0: 3304 adds r3, #4
+ 80006d2: 2b06 cmp r3, #6
+ 80006d4: d902 bls.n 80006dc <NVIC_EncodePriority+0x30>
+ 80006d6: 69fb ldr r3, [r7, #28]
+ 80006d8: 3b03 subs r3, #3
+ 80006da: e000 b.n 80006de <NVIC_EncodePriority+0x32>
+ 80006dc: 2300 movs r3, #0
+ 80006de: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000724: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
- 8000728: 69bb ldr r3, [r7, #24]
- 800072a: fa02 f303 lsl.w r3, r2, r3
- 800072e: 43da mvns r2, r3
- 8000730: 68bb ldr r3, [r7, #8]
- 8000732: 401a ands r2, r3
- 8000734: 697b ldr r3, [r7, #20]
- 8000736: 409a lsls r2, r3
+ 80006e0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
+ 80006e4: 69bb ldr r3, [r7, #24]
+ 80006e6: fa02 f303 lsl.w r3, r2, r3
+ 80006ea: 43da mvns r2, r3
+ 80006ec: 68bb ldr r3, [r7, #8]
+ 80006ee: 401a ands r2, r3
+ 80006f0: 697b ldr r3, [r7, #20]
+ 80006f2: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- 8000738: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
- 800073c: 697b ldr r3, [r7, #20]
- 800073e: fa01 f303 lsl.w r3, r1, r3
- 8000742: 43d9 mvns r1, r3
- 8000744: 687b ldr r3, [r7, #4]
- 8000746: 400b ands r3, r1
+ 80006f4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
+ 80006f8: 697b ldr r3, [r7, #20]
+ 80006fa: fa01 f303 lsl.w r3, r1, r3
+ 80006fe: 43d9 mvns r1, r3
+ 8000700: 687b ldr r3, [r7, #4]
+ 8000702: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000748: 4313 orrs r3, r2
+ 8000704: 4313 orrs r3, r2
);
}
- 800074a: 4618 mov r0, r3
- 800074c: 3724 adds r7, #36 ; 0x24
- 800074e: 46bd mov sp, r7
- 8000750: f85d 7b04 ldr.w r7, [sp], #4
- 8000754: 4770 bx lr
+ 8000706: 4618 mov r0, r3
+ 8000708: 3724 adds r7, #36 ; 0x24
+ 800070a: 46bd mov sp, r7
+ 800070c: f85d 7b04 ldr.w r7, [sp], #4
+ 8000710: 4770 bx lr
...
-08000758 <SysTick_Config>:
+08000714 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- 8000758: b580 push {r7, lr}
- 800075a: b082 sub sp, #8
- 800075c: af00 add r7, sp, #0
- 800075e: 6078 str r0, [r7, #4]
+ 8000714: b580 push {r7, lr}
+ 8000716: b082 sub sp, #8
+ 8000718: af00 add r7, sp, #0
+ 800071a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8000760: 687b ldr r3, [r7, #4]
- 8000762: 3b01 subs r3, #1
- 8000764: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
- 8000768: d301 bcc.n 800076e <SysTick_Config+0x16>
+ 800071c: 687b ldr r3, [r7, #4]
+ 800071e: 3b01 subs r3, #1
+ 8000720: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
+ 8000724: d301 bcc.n 800072a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
- 800076a: 2301 movs r3, #1
- 800076c: e00f b.n 800078e <SysTick_Config+0x36>
+ 8000726: 2301 movs r3, #1
+ 8000728: e00f b.n 800074a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 800076e: 4a0a ldr r2, [pc, #40] ; (8000798 <SysTick_Config+0x40>)
- 8000770: 687b ldr r3, [r7, #4]
- 8000772: 3b01 subs r3, #1
- 8000774: 6053 str r3, [r2, #4]
+ 800072a: 4a0a ldr r2, [pc, #40] ; (8000754 <SysTick_Config+0x40>)
+ 800072c: 687b ldr r3, [r7, #4]
+ 800072e: 3b01 subs r3, #1
+ 8000730: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8000776: 210f movs r1, #15
- 8000778: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
- 800077c: f7ff ff8e bl 800069c <__NVIC_SetPriority>
+ 8000732: 210f movs r1, #15
+ 8000734: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
+ 8000738: f7ff ff8e bl 8000658 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 8000780: 4b05 ldr r3, [pc, #20] ; (8000798 <SysTick_Config+0x40>)
- 8000782: 2200 movs r2, #0
- 8000784: 609a str r2, [r3, #8]
+ 800073c: 4b05 ldr r3, [pc, #20] ; (8000754 <SysTick_Config+0x40>)
+ 800073e: 2200 movs r2, #0
+ 8000740: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8000786: 4b04 ldr r3, [pc, #16] ; (8000798 <SysTick_Config+0x40>)
- 8000788: 2207 movs r2, #7
- 800078a: 601a str r2, [r3, #0]
+ 8000742: 4b04 ldr r3, [pc, #16] ; (8000754 <SysTick_Config+0x40>)
+ 8000744: 2207 movs r2, #7
+ 8000746: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
- 800078c: 2300 movs r3, #0
+ 8000748: 2300 movs r3, #0
}
- 800078e: 4618 mov r0, r3
- 8000790: 3708 adds r7, #8
- 8000792: 46bd mov sp, r7
- 8000794: bd80 pop {r7, pc}
- 8000796: bf00 nop
- 8000798: e000e010 .word 0xe000e010
-
-0800079c <HAL_NVIC_SetPriorityGrouping>:
+ 800074a: 4618 mov r0, r3
+ 800074c: 3708 adds r7, #8
+ 800074e: 46bd mov sp, r7
+ 8000750: bd80 pop {r7, pc}
+ 8000752: bf00 nop
+ 8000754: e000e010 .word 0xe000e010
+
+08000758 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
- 800079c: b580 push {r7, lr}
- 800079e: b082 sub sp, #8
- 80007a0: af00 add r7, sp, #0
- 80007a2: 6078 str r0, [r7, #4]
+ 8000758: b580 push {r7, lr}
+ 800075a: b082 sub sp, #8
+ 800075c: af00 add r7, sp, #0
+ 800075e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
- 80007a4: 6878 ldr r0, [r7, #4]
- 80007a6: f7ff ff47 bl 8000638 <__NVIC_SetPriorityGrouping>
+ 8000760: 6878 ldr r0, [r7, #4]
+ 8000762: f7ff ff47 bl 80005f4 <__NVIC_SetPriorityGrouping>
}
- 80007aa: bf00 nop
- 80007ac: 3708 adds r7, #8
- 80007ae: 46bd mov sp, r7
- 80007b0: bd80 pop {r7, pc}
+ 8000766: bf00 nop
+ 8000768: 3708 adds r7, #8
+ 800076a: 46bd mov sp, r7
+ 800076c: bd80 pop {r7, pc}
-080007b2 <HAL_NVIC_SetPriority>:
+0800076e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
- 80007b2: b580 push {r7, lr}
- 80007b4: b086 sub sp, #24
- 80007b6: af00 add r7, sp, #0
- 80007b8: 4603 mov r3, r0
- 80007ba: 60b9 str r1, [r7, #8]
- 80007bc: 607a str r2, [r7, #4]
- 80007be: 73fb strb r3, [r7, #15]
+ 800076e: b580 push {r7, lr}
+ 8000770: b086 sub sp, #24
+ 8000772: af00 add r7, sp, #0
+ 8000774: 4603 mov r3, r0
+ 8000776: 60b9 str r1, [r7, #8]
+ 8000778: 607a str r2, [r7, #4]
+ 800077a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
- 80007c0: 2300 movs r3, #0
- 80007c2: 617b str r3, [r7, #20]
+ 800077c: 2300 movs r3, #0
+ 800077e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
- 80007c4: f7ff ff5c bl 8000680 <__NVIC_GetPriorityGrouping>
- 80007c8: 6178 str r0, [r7, #20]
+ 8000780: f7ff ff5c bl 800063c <__NVIC_GetPriorityGrouping>
+ 8000784: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 80007ca: 687a ldr r2, [r7, #4]
- 80007cc: 68b9 ldr r1, [r7, #8]
- 80007ce: 6978 ldr r0, [r7, #20]
- 80007d0: f7ff ff8e bl 80006f0 <NVIC_EncodePriority>
- 80007d4: 4602 mov r2, r0
- 80007d6: f997 300f ldrsb.w r3, [r7, #15]
- 80007da: 4611 mov r1, r2
- 80007dc: 4618 mov r0, r3
- 80007de: f7ff ff5d bl 800069c <__NVIC_SetPriority>
+ 8000786: 687a ldr r2, [r7, #4]
+ 8000788: 68b9 ldr r1, [r7, #8]
+ 800078a: 6978 ldr r0, [r7, #20]
+ 800078c: f7ff ff8e bl 80006ac <NVIC_EncodePriority>
+ 8000790: 4602 mov r2, r0
+ 8000792: f997 300f ldrsb.w r3, [r7, #15]
+ 8000796: 4611 mov r1, r2
+ 8000798: 4618 mov r0, r3
+ 800079a: f7ff ff5d bl 8000658 <__NVIC_SetPriority>
}
- 80007e2: bf00 nop
- 80007e4: 3718 adds r7, #24
- 80007e6: 46bd mov sp, r7
- 80007e8: bd80 pop {r7, pc}
+ 800079e: bf00 nop
+ 80007a0: 3718 adds r7, #24
+ 80007a2: 46bd mov sp, r7
+ 80007a4: bd80 pop {r7, pc}
-080007ea <HAL_SYSTICK_Config>:
+080007a6 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
- 80007ea: b580 push {r7, lr}
- 80007ec: b082 sub sp, #8
- 80007ee: af00 add r7, sp, #0
- 80007f0: 6078 str r0, [r7, #4]
+ 80007a6: b580 push {r7, lr}
+ 80007a8: b082 sub sp, #8
+ 80007aa: af00 add r7, sp, #0
+ 80007ac: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
- 80007f2: 6878 ldr r0, [r7, #4]
- 80007f4: f7ff ffb0 bl 8000758 <SysTick_Config>
- 80007f8: 4603 mov r3, r0
+ 80007ae: 6878 ldr r0, [r7, #4]
+ 80007b0: f7ff ffb0 bl 8000714 <SysTick_Config>
+ 80007b4: 4603 mov r3, r0
}
- 80007fa: 4618 mov r0, r3
- 80007fc: 3708 adds r7, #8
- 80007fe: 46bd mov sp, r7
- 8000800: bd80 pop {r7, pc}
+ 80007b6: 4618 mov r0, r3
+ 80007b8: 3708 adds r7, #8
+ 80007ba: 46bd mov sp, r7
+ 80007bc: bd80 pop {r7, pc}
...
-08000804 <HAL_GPIO_Init>:
+080007c0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
- 8000804: b480 push {r7}
- 8000806: b089 sub sp, #36 ; 0x24
- 8000808: af00 add r7, sp, #0
- 800080a: 6078 str r0, [r7, #4]
- 800080c: 6039 str r1, [r7, #0]
+ 80007c0: b480 push {r7}
+ 80007c2: b089 sub sp, #36 ; 0x24
+ 80007c4: af00 add r7, sp, #0
+ 80007c6: 6078 str r0, [r7, #4]
+ 80007c8: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
- 800080e: 2300 movs r3, #0
- 8000810: 61fb str r3, [r7, #28]
+ 80007ca: 2300 movs r3, #0
+ 80007cc: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
- 8000812: 2300 movs r3, #0
- 8000814: 617b str r3, [r7, #20]
+ 80007ce: 2300 movs r3, #0
+ 80007d0: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
- 8000816: 2300 movs r3, #0
- 8000818: 613b str r3, [r7, #16]
+ 80007d2: 2300 movs r3, #0
+ 80007d4: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
- 800081a: 2300 movs r3, #0
- 800081c: 61bb str r3, [r7, #24]
+ 80007d6: 2300 movs r3, #0
+ 80007d8: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
- 800081e: 2300 movs r3, #0
- 8000820: 61fb str r3, [r7, #28]
- 8000822: e175 b.n 8000b10 <HAL_GPIO_Init+0x30c>
+ 80007da: 2300 movs r3, #0
+ 80007dc: 61fb str r3, [r7, #28]
+ 80007de: e175 b.n 8000acc <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
- 8000824: 2201 movs r2, #1
- 8000826: 69fb ldr r3, [r7, #28]
- 8000828: fa02 f303 lsl.w r3, r2, r3
- 800082c: 617b str r3, [r7, #20]
+ 80007e0: 2201 movs r2, #1
+ 80007e2: 69fb ldr r3, [r7, #28]
+ 80007e4: fa02 f303 lsl.w r3, r2, r3
+ 80007e8: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 800082e: 683b ldr r3, [r7, #0]
- 8000830: 681b ldr r3, [r3, #0]
- 8000832: 697a ldr r2, [r7, #20]
- 8000834: 4013 ands r3, r2
- 8000836: 613b str r3, [r7, #16]
+ 80007ea: 683b ldr r3, [r7, #0]
+ 80007ec: 681b ldr r3, [r3, #0]
+ 80007ee: 697a ldr r2, [r7, #20]
+ 80007f0: 4013 ands r3, r2
+ 80007f2: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
- 8000838: 693a ldr r2, [r7, #16]
- 800083a: 697b ldr r3, [r7, #20]
- 800083c: 429a cmp r2, r3
- 800083e: f040 8164 bne.w 8000b0a <HAL_GPIO_Init+0x306>
+ 80007f4: 693a ldr r2, [r7, #16]
+ 80007f6: 697b ldr r3, [r7, #20]
+ 80007f8: 429a cmp r2, r3
+ 80007fa: f040 8164 bne.w 8000ac6 <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 8000842: 683b ldr r3, [r7, #0]
- 8000844: 685b ldr r3, [r3, #4]
- 8000846: 2b02 cmp r3, #2
- 8000848: d003 beq.n 8000852 <HAL_GPIO_Init+0x4e>
- 800084a: 683b ldr r3, [r7, #0]
- 800084c: 685b ldr r3, [r3, #4]
- 800084e: 2b12 cmp r3, #18
- 8000850: d123 bne.n 800089a <HAL_GPIO_Init+0x96>
+ 80007fe: 683b ldr r3, [r7, #0]
+ 8000800: 685b ldr r3, [r3, #4]
+ 8000802: 2b02 cmp r3, #2
+ 8000804: d003 beq.n 800080e <HAL_GPIO_Init+0x4e>
+ 8000806: 683b ldr r3, [r7, #0]
+ 8000808: 685b ldr r3, [r3, #4]
+ 800080a: 2b12 cmp r3, #18
+ 800080c: d123 bne.n 8000856 <HAL_GPIO_Init+0x96>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
- 8000852: 69fb ldr r3, [r7, #28]
- 8000854: 08da lsrs r2, r3, #3
- 8000856: 687b ldr r3, [r7, #4]
- 8000858: 3208 adds r2, #8
- 800085a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
- 800085e: 61bb str r3, [r7, #24]
+ 800080e: 69fb ldr r3, [r7, #28]
+ 8000810: 08da lsrs r2, r3, #3
+ 8000812: 687b ldr r3, [r7, #4]
+ 8000814: 3208 adds r2, #8
+ 8000816: f853 3022 ldr.w r3, [r3, r2, lsl #2]
+ 800081a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- 8000860: 69fb ldr r3, [r7, #28]
- 8000862: f003 0307 and.w r3, r3, #7
- 8000866: 009b lsls r3, r3, #2
- 8000868: 220f movs r2, #15
- 800086a: fa02 f303 lsl.w r3, r2, r3
- 800086e: 43db mvns r3, r3
- 8000870: 69ba ldr r2, [r7, #24]
- 8000872: 4013 ands r3, r2
- 8000874: 61bb str r3, [r7, #24]
+ 800081c: 69fb ldr r3, [r7, #28]
+ 800081e: f003 0307 and.w r3, r3, #7
+ 8000822: 009b lsls r3, r3, #2
+ 8000824: 220f movs r2, #15
+ 8000826: fa02 f303 lsl.w r3, r2, r3
+ 800082a: 43db mvns r3, r3
+ 800082c: 69ba ldr r2, [r7, #24]
+ 800082e: 4013 ands r3, r2
+ 8000830: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
- 8000876: 683b ldr r3, [r7, #0]
- 8000878: 691a ldr r2, [r3, #16]
- 800087a: 69fb ldr r3, [r7, #28]
- 800087c: f003 0307 and.w r3, r3, #7
- 8000880: 009b lsls r3, r3, #2
- 8000882: fa02 f303 lsl.w r3, r2, r3
- 8000886: 69ba ldr r2, [r7, #24]
- 8000888: 4313 orrs r3, r2
- 800088a: 61bb str r3, [r7, #24]
+ 8000832: 683b ldr r3, [r7, #0]
+ 8000834: 691a ldr r2, [r3, #16]
+ 8000836: 69fb ldr r3, [r7, #28]
+ 8000838: f003 0307 and.w r3, r3, #7
+ 800083c: 009b lsls r3, r3, #2
+ 800083e: fa02 f303 lsl.w r3, r2, r3
+ 8000842: 69ba ldr r2, [r7, #24]
+ 8000844: 4313 orrs r3, r2
+ 8000846: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
- 800088c: 69fb ldr r3, [r7, #28]
- 800088e: 08da lsrs r2, r3, #3
- 8000890: 687b ldr r3, [r7, #4]
- 8000892: 3208 adds r2, #8
- 8000894: 69b9 ldr r1, [r7, #24]
- 8000896: f843 1022 str.w r1, [r3, r2, lsl #2]
+ 8000848: 69fb ldr r3, [r7, #28]
+ 800084a: 08da lsrs r2, r3, #3
+ 800084c: 687b ldr r3, [r7, #4]
+ 800084e: 3208 adds r2, #8
+ 8000850: 69b9 ldr r1, [r7, #24]
+ 8000852: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
- 800089a: 687b ldr r3, [r7, #4]
- 800089c: 681b ldr r3, [r3, #0]
- 800089e: 61bb str r3, [r7, #24]
+ 8000856: 687b ldr r3, [r7, #4]
+ 8000858: 681b ldr r3, [r3, #0]
+ 800085a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- 80008a0: 69fb ldr r3, [r7, #28]
- 80008a2: 005b lsls r3, r3, #1
- 80008a4: 2203 movs r2, #3
- 80008a6: fa02 f303 lsl.w r3, r2, r3
- 80008aa: 43db mvns r3, r3
- 80008ac: 69ba ldr r2, [r7, #24]
- 80008ae: 4013 ands r3, r2
- 80008b0: 61bb str r3, [r7, #24]
+ 800085c: 69fb ldr r3, [r7, #28]
+ 800085e: 005b lsls r3, r3, #1
+ 8000860: 2203 movs r2, #3
+ 8000862: fa02 f303 lsl.w r3, r2, r3
+ 8000866: 43db mvns r3, r3
+ 8000868: 69ba ldr r2, [r7, #24]
+ 800086a: 4013 ands r3, r2
+ 800086c: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 80008b2: 683b ldr r3, [r7, #0]
- 80008b4: 685b ldr r3, [r3, #4]
- 80008b6: f003 0203 and.w r2, r3, #3
- 80008ba: 69fb ldr r3, [r7, #28]
- 80008bc: 005b lsls r3, r3, #1
- 80008be: fa02 f303 lsl.w r3, r2, r3
- 80008c2: 69ba ldr r2, [r7, #24]
- 80008c4: 4313 orrs r3, r2
- 80008c6: 61bb str r3, [r7, #24]
+ 800086e: 683b ldr r3, [r7, #0]
+ 8000870: 685b ldr r3, [r3, #4]
+ 8000872: f003 0203 and.w r2, r3, #3
+ 8000876: 69fb ldr r3, [r7, #28]
+ 8000878: 005b lsls r3, r3, #1
+ 800087a: fa02 f303 lsl.w r3, r2, r3
+ 800087e: 69ba ldr r2, [r7, #24]
+ 8000880: 4313 orrs r3, r2
+ 8000882: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
- 80008c8: 687b ldr r3, [r7, #4]
- 80008ca: 69ba ldr r2, [r7, #24]
- 80008cc: 601a str r2, [r3, #0]
+ 8000884: 687b ldr r3, [r7, #4]
+ 8000886: 69ba ldr r2, [r7, #24]
+ 8000888: 601a str r2, [r3, #0]
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 80008ce: 683b ldr r3, [r7, #0]
- 80008d0: 685b ldr r3, [r3, #4]
- 80008d2: 2b01 cmp r3, #1
- 80008d4: d00b beq.n 80008ee <HAL_GPIO_Init+0xea>
- 80008d6: 683b ldr r3, [r7, #0]
- 80008d8: 685b ldr r3, [r3, #4]
- 80008da: 2b02 cmp r3, #2
- 80008dc: d007 beq.n 80008ee <HAL_GPIO_Init+0xea>
+ 800088a: 683b ldr r3, [r7, #0]
+ 800088c: 685b ldr r3, [r3, #4]
+ 800088e: 2b01 cmp r3, #1
+ 8000890: d00b beq.n 80008aa <HAL_GPIO_Init+0xea>
+ 8000892: 683b ldr r3, [r7, #0]
+ 8000894: 685b ldr r3, [r3, #4]
+ 8000896: 2b02 cmp r3, #2
+ 8000898: d007 beq.n 80008aa <HAL_GPIO_Init+0xea>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 80008de: 683b ldr r3, [r7, #0]
- 80008e0: 685b ldr r3, [r3, #4]
+ 800089a: 683b ldr r3, [r7, #0]
+ 800089c: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 80008e2: 2b11 cmp r3, #17
- 80008e4: d003 beq.n 80008ee <HAL_GPIO_Init+0xea>
+ 800089e: 2b11 cmp r3, #17
+ 80008a0: d003 beq.n 80008aa <HAL_GPIO_Init+0xea>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- 80008e6: 683b ldr r3, [r7, #0]
- 80008e8: 685b ldr r3, [r3, #4]
- 80008ea: 2b12 cmp r3, #18
- 80008ec: d130 bne.n 8000950 <HAL_GPIO_Init+0x14c>
+ 80008a2: 683b ldr r3, [r7, #0]
+ 80008a4: 685b ldr r3, [r3, #4]
+ 80008a6: 2b12 cmp r3, #18
+ 80008a8: d130 bne.n 800090c <HAL_GPIO_Init+0x14c>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
- 80008ee: 687b ldr r3, [r7, #4]
- 80008f0: 689b ldr r3, [r3, #8]
- 80008f2: 61bb str r3, [r7, #24]
+ 80008aa: 687b ldr r3, [r7, #4]
+ 80008ac: 689b ldr r3, [r3, #8]
+ 80008ae: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 80008f4: 69fb ldr r3, [r7, #28]
- 80008f6: 005b lsls r3, r3, #1
- 80008f8: 2203 movs r2, #3
- 80008fa: fa02 f303 lsl.w r3, r2, r3
- 80008fe: 43db mvns r3, r3
- 8000900: 69ba ldr r2, [r7, #24]
- 8000902: 4013 ands r3, r2
- 8000904: 61bb str r3, [r7, #24]
+ 80008b0: 69fb ldr r3, [r7, #28]
+ 80008b2: 005b lsls r3, r3, #1
+ 80008b4: 2203 movs r2, #3
+ 80008b6: fa02 f303 lsl.w r3, r2, r3
+ 80008ba: 43db mvns r3, r3
+ 80008bc: 69ba ldr r2, [r7, #24]
+ 80008be: 4013 ands r3, r2
+ 80008c0: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
- 8000906: 683b ldr r3, [r7, #0]
- 8000908: 68da ldr r2, [r3, #12]
- 800090a: 69fb ldr r3, [r7, #28]
- 800090c: 005b lsls r3, r3, #1
- 800090e: fa02 f303 lsl.w r3, r2, r3
- 8000912: 69ba ldr r2, [r7, #24]
- 8000914: 4313 orrs r3, r2
- 8000916: 61bb str r3, [r7, #24]
+ 80008c2: 683b ldr r3, [r7, #0]
+ 80008c4: 68da ldr r2, [r3, #12]
+ 80008c6: 69fb ldr r3, [r7, #28]
+ 80008c8: 005b lsls r3, r3, #1
+ 80008ca: fa02 f303 lsl.w r3, r2, r3
+ 80008ce: 69ba ldr r2, [r7, #24]
+ 80008d0: 4313 orrs r3, r2
+ 80008d2: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
- 8000918: 687b ldr r3, [r7, #4]
- 800091a: 69ba ldr r2, [r7, #24]
- 800091c: 609a str r2, [r3, #8]
+ 80008d4: 687b ldr r3, [r7, #4]
+ 80008d6: 69ba ldr r2, [r7, #24]
+ 80008d8: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
- 800091e: 687b ldr r3, [r7, #4]
- 8000920: 685b ldr r3, [r3, #4]
- 8000922: 61bb str r3, [r7, #24]
+ 80008da: 687b ldr r3, [r7, #4]
+ 80008dc: 685b ldr r3, [r3, #4]
+ 80008de: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 8000924: 2201 movs r2, #1
- 8000926: 69fb ldr r3, [r7, #28]
- 8000928: fa02 f303 lsl.w r3, r2, r3
- 800092c: 43db mvns r3, r3
- 800092e: 69ba ldr r2, [r7, #24]
- 8000930: 4013 ands r3, r2
- 8000932: 61bb str r3, [r7, #24]
+ 80008e0: 2201 movs r2, #1
+ 80008e2: 69fb ldr r3, [r7, #28]
+ 80008e4: fa02 f303 lsl.w r3, r2, r3
+ 80008e8: 43db mvns r3, r3
+ 80008ea: 69ba ldr r2, [r7, #24]
+ 80008ec: 4013 ands r3, r2
+ 80008ee: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
- 8000934: 683b ldr r3, [r7, #0]
- 8000936: 685b ldr r3, [r3, #4]
- 8000938: 091b lsrs r3, r3, #4
- 800093a: f003 0201 and.w r2, r3, #1
- 800093e: 69fb ldr r3, [r7, #28]
- 8000940: fa02 f303 lsl.w r3, r2, r3
- 8000944: 69ba ldr r2, [r7, #24]
- 8000946: 4313 orrs r3, r2
- 8000948: 61bb str r3, [r7, #24]
+ 80008f0: 683b ldr r3, [r7, #0]
+ 80008f2: 685b ldr r3, [r3, #4]
+ 80008f4: 091b lsrs r3, r3, #4
+ 80008f6: f003 0201 and.w r2, r3, #1
+ 80008fa: 69fb ldr r3, [r7, #28]
+ 80008fc: fa02 f303 lsl.w r3, r2, r3
+ 8000900: 69ba ldr r2, [r7, #24]
+ 8000902: 4313 orrs r3, r2
+ 8000904: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
- 800094a: 687b ldr r3, [r7, #4]
- 800094c: 69ba ldr r2, [r7, #24]
- 800094e: 605a str r2, [r3, #4]
+ 8000906: 687b ldr r3, [r7, #4]
+ 8000908: 69ba ldr r2, [r7, #24]
+ 800090a: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
- 8000950: 687b ldr r3, [r7, #4]
- 8000952: 68db ldr r3, [r3, #12]
- 8000954: 61bb str r3, [r7, #24]
+ 800090c: 687b ldr r3, [r7, #4]
+ 800090e: 68db ldr r3, [r3, #12]
+ 8000910: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- 8000956: 69fb ldr r3, [r7, #28]
- 8000958: 005b lsls r3, r3, #1
- 800095a: 2203 movs r2, #3
- 800095c: fa02 f303 lsl.w r3, r2, r3
- 8000960: 43db mvns r3, r3
- 8000962: 69ba ldr r2, [r7, #24]
- 8000964: 4013 ands r3, r2
- 8000966: 61bb str r3, [r7, #24]
+ 8000912: 69fb ldr r3, [r7, #28]
+ 8000914: 005b lsls r3, r3, #1
+ 8000916: 2203 movs r2, #3
+ 8000918: fa02 f303 lsl.w r3, r2, r3
+ 800091c: 43db mvns r3, r3
+ 800091e: 69ba ldr r2, [r7, #24]
+ 8000920: 4013 ands r3, r2
+ 8000922: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
- 8000968: 683b ldr r3, [r7, #0]
- 800096a: 689a ldr r2, [r3, #8]
- 800096c: 69fb ldr r3, [r7, #28]
- 800096e: 005b lsls r3, r3, #1
- 8000970: fa02 f303 lsl.w r3, r2, r3
- 8000974: 69ba ldr r2, [r7, #24]
- 8000976: 4313 orrs r3, r2
- 8000978: 61bb str r3, [r7, #24]
+ 8000924: 683b ldr r3, [r7, #0]
+ 8000926: 689a ldr r2, [r3, #8]
+ 8000928: 69fb ldr r3, [r7, #28]
+ 800092a: 005b lsls r3, r3, #1
+ 800092c: fa02 f303 lsl.w r3, r2, r3
+ 8000930: 69ba ldr r2, [r7, #24]
+ 8000932: 4313 orrs r3, r2
+ 8000934: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
- 800097a: 687b ldr r3, [r7, #4]
- 800097c: 69ba ldr r2, [r7, #24]
- 800097e: 60da str r2, [r3, #12]
+ 8000936: 687b ldr r3, [r7, #4]
+ 8000938: 69ba ldr r2, [r7, #24]
+ 800093a: 60da str r2, [r3, #12]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 8000980: 683b ldr r3, [r7, #0]
- 8000982: 685b ldr r3, [r3, #4]
- 8000984: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000988: 2b00 cmp r3, #0
- 800098a: f000 80be beq.w 8000b0a <HAL_GPIO_Init+0x306>
+ 800093c: 683b ldr r3, [r7, #0]
+ 800093e: 685b ldr r3, [r3, #4]
+ 8000940: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000944: 2b00 cmp r3, #0
+ 8000946: f000 80be beq.w 8000ac6 <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 800098e: 4b65 ldr r3, [pc, #404] ; (8000b24 <HAL_GPIO_Init+0x320>)
- 8000990: 6c5b ldr r3, [r3, #68] ; 0x44
- 8000992: 4a64 ldr r2, [pc, #400] ; (8000b24 <HAL_GPIO_Init+0x320>)
- 8000994: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8000998: 6453 str r3, [r2, #68] ; 0x44
- 800099a: 4b62 ldr r3, [pc, #392] ; (8000b24 <HAL_GPIO_Init+0x320>)
- 800099c: 6c5b ldr r3, [r3, #68] ; 0x44
- 800099e: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 80009a2: 60fb str r3, [r7, #12]
- 80009a4: 68fb ldr r3, [r7, #12]
+ 800094a: 4b65 ldr r3, [pc, #404] ; (8000ae0 <HAL_GPIO_Init+0x320>)
+ 800094c: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800094e: 4a64 ldr r2, [pc, #400] ; (8000ae0 <HAL_GPIO_Init+0x320>)
+ 8000950: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8000954: 6453 str r3, [r2, #68] ; 0x44
+ 8000956: 4b62 ldr r3, [pc, #392] ; (8000ae0 <HAL_GPIO_Init+0x320>)
+ 8000958: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800095a: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 800095e: 60fb str r3, [r7, #12]
+ 8000960: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
- 80009a6: 4a60 ldr r2, [pc, #384] ; (8000b28 <HAL_GPIO_Init+0x324>)
- 80009a8: 69fb ldr r3, [r7, #28]
- 80009aa: 089b lsrs r3, r3, #2
- 80009ac: 3302 adds r3, #2
- 80009ae: f852 3023 ldr.w r3, [r2, r3, lsl #2]
- 80009b2: 61bb str r3, [r7, #24]
+ 8000962: 4a60 ldr r2, [pc, #384] ; (8000ae4 <HAL_GPIO_Init+0x324>)
+ 8000964: 69fb ldr r3, [r7, #28]
+ 8000966: 089b lsrs r3, r3, #2
+ 8000968: 3302 adds r3, #2
+ 800096a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
+ 800096e: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- 80009b4: 69fb ldr r3, [r7, #28]
- 80009b6: f003 0303 and.w r3, r3, #3
- 80009ba: 009b lsls r3, r3, #2
- 80009bc: 220f movs r2, #15
- 80009be: fa02 f303 lsl.w r3, r2, r3
- 80009c2: 43db mvns r3, r3
- 80009c4: 69ba ldr r2, [r7, #24]
- 80009c6: 4013 ands r3, r2
- 80009c8: 61bb str r3, [r7, #24]
+ 8000970: 69fb ldr r3, [r7, #28]
+ 8000972: f003 0303 and.w r3, r3, #3
+ 8000976: 009b lsls r3, r3, #2
+ 8000978: 220f movs r2, #15
+ 800097a: fa02 f303 lsl.w r3, r2, r3
+ 800097e: 43db mvns r3, r3
+ 8000980: 69ba ldr r2, [r7, #24]
+ 8000982: 4013 ands r3, r2
+ 8000984: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 80009ca: 687b ldr r3, [r7, #4]
- 80009cc: 4a57 ldr r2, [pc, #348] ; (8000b2c <HAL_GPIO_Init+0x328>)
- 80009ce: 4293 cmp r3, r2
- 80009d0: d037 beq.n 8000a42 <HAL_GPIO_Init+0x23e>
- 80009d2: 687b ldr r3, [r7, #4]
- 80009d4: 4a56 ldr r2, [pc, #344] ; (8000b30 <HAL_GPIO_Init+0x32c>)
- 80009d6: 4293 cmp r3, r2
- 80009d8: d031 beq.n 8000a3e <HAL_GPIO_Init+0x23a>
- 80009da: 687b ldr r3, [r7, #4]
- 80009dc: 4a55 ldr r2, [pc, #340] ; (8000b34 <HAL_GPIO_Init+0x330>)
- 80009de: 4293 cmp r3, r2
- 80009e0: d02b beq.n 8000a3a <HAL_GPIO_Init+0x236>
- 80009e2: 687b ldr r3, [r7, #4]
- 80009e4: 4a54 ldr r2, [pc, #336] ; (8000b38 <HAL_GPIO_Init+0x334>)
- 80009e6: 4293 cmp r3, r2
- 80009e8: d025 beq.n 8000a36 <HAL_GPIO_Init+0x232>
- 80009ea: 687b ldr r3, [r7, #4]
- 80009ec: 4a53 ldr r2, [pc, #332] ; (8000b3c <HAL_GPIO_Init+0x338>)
- 80009ee: 4293 cmp r3, r2
- 80009f0: d01f beq.n 8000a32 <HAL_GPIO_Init+0x22e>
- 80009f2: 687b ldr r3, [r7, #4]
- 80009f4: 4a52 ldr r2, [pc, #328] ; (8000b40 <HAL_GPIO_Init+0x33c>)
- 80009f6: 4293 cmp r3, r2
- 80009f8: d019 beq.n 8000a2e <HAL_GPIO_Init+0x22a>
- 80009fa: 687b ldr r3, [r7, #4]
- 80009fc: 4a51 ldr r2, [pc, #324] ; (8000b44 <HAL_GPIO_Init+0x340>)
- 80009fe: 4293 cmp r3, r2
- 8000a00: d013 beq.n 8000a2a <HAL_GPIO_Init+0x226>
- 8000a02: 687b ldr r3, [r7, #4]
- 8000a04: 4a50 ldr r2, [pc, #320] ; (8000b48 <HAL_GPIO_Init+0x344>)
- 8000a06: 4293 cmp r3, r2
- 8000a08: d00d beq.n 8000a26 <HAL_GPIO_Init+0x222>
- 8000a0a: 687b ldr r3, [r7, #4]
- 8000a0c: 4a4f ldr r2, [pc, #316] ; (8000b4c <HAL_GPIO_Init+0x348>)
- 8000a0e: 4293 cmp r3, r2
- 8000a10: d007 beq.n 8000a22 <HAL_GPIO_Init+0x21e>
- 8000a12: 687b ldr r3, [r7, #4]
- 8000a14: 4a4e ldr r2, [pc, #312] ; (8000b50 <HAL_GPIO_Init+0x34c>)
- 8000a16: 4293 cmp r3, r2
- 8000a18: d101 bne.n 8000a1e <HAL_GPIO_Init+0x21a>
- 8000a1a: 2309 movs r3, #9
- 8000a1c: e012 b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a1e: 230a movs r3, #10
- 8000a20: e010 b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a22: 2308 movs r3, #8
- 8000a24: e00e b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a26: 2307 movs r3, #7
- 8000a28: e00c b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a2a: 2306 movs r3, #6
- 8000a2c: e00a b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a2e: 2305 movs r3, #5
- 8000a30: e008 b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a32: 2304 movs r3, #4
- 8000a34: e006 b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a36: 2303 movs r3, #3
- 8000a38: e004 b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a3a: 2302 movs r3, #2
- 8000a3c: e002 b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a3e: 2301 movs r3, #1
- 8000a40: e000 b.n 8000a44 <HAL_GPIO_Init+0x240>
- 8000a42: 2300 movs r3, #0
- 8000a44: 69fa ldr r2, [r7, #28]
- 8000a46: f002 0203 and.w r2, r2, #3
- 8000a4a: 0092 lsls r2, r2, #2
- 8000a4c: 4093 lsls r3, r2
- 8000a4e: 69ba ldr r2, [r7, #24]
- 8000a50: 4313 orrs r3, r2
- 8000a52: 61bb str r3, [r7, #24]
+ 8000986: 687b ldr r3, [r7, #4]
+ 8000988: 4a57 ldr r2, [pc, #348] ; (8000ae8 <HAL_GPIO_Init+0x328>)
+ 800098a: 4293 cmp r3, r2
+ 800098c: d037 beq.n 80009fe <HAL_GPIO_Init+0x23e>
+ 800098e: 687b ldr r3, [r7, #4]
+ 8000990: 4a56 ldr r2, [pc, #344] ; (8000aec <HAL_GPIO_Init+0x32c>)
+ 8000992: 4293 cmp r3, r2
+ 8000994: d031 beq.n 80009fa <HAL_GPIO_Init+0x23a>
+ 8000996: 687b ldr r3, [r7, #4]
+ 8000998: 4a55 ldr r2, [pc, #340] ; (8000af0 <HAL_GPIO_Init+0x330>)
+ 800099a: 4293 cmp r3, r2
+ 800099c: d02b beq.n 80009f6 <HAL_GPIO_Init+0x236>
+ 800099e: 687b ldr r3, [r7, #4]
+ 80009a0: 4a54 ldr r2, [pc, #336] ; (8000af4 <HAL_GPIO_Init+0x334>)
+ 80009a2: 4293 cmp r3, r2
+ 80009a4: d025 beq.n 80009f2 <HAL_GPIO_Init+0x232>
+ 80009a6: 687b ldr r3, [r7, #4]
+ 80009a8: 4a53 ldr r2, [pc, #332] ; (8000af8 <HAL_GPIO_Init+0x338>)
+ 80009aa: 4293 cmp r3, r2
+ 80009ac: d01f beq.n 80009ee <HAL_GPIO_Init+0x22e>
+ 80009ae: 687b ldr r3, [r7, #4]
+ 80009b0: 4a52 ldr r2, [pc, #328] ; (8000afc <HAL_GPIO_Init+0x33c>)
+ 80009b2: 4293 cmp r3, r2
+ 80009b4: d019 beq.n 80009ea <HAL_GPIO_Init+0x22a>
+ 80009b6: 687b ldr r3, [r7, #4]
+ 80009b8: 4a51 ldr r2, [pc, #324] ; (8000b00 <HAL_GPIO_Init+0x340>)
+ 80009ba: 4293 cmp r3, r2
+ 80009bc: d013 beq.n 80009e6 <HAL_GPIO_Init+0x226>
+ 80009be: 687b ldr r3, [r7, #4]
+ 80009c0: 4a50 ldr r2, [pc, #320] ; (8000b04 <HAL_GPIO_Init+0x344>)
+ 80009c2: 4293 cmp r3, r2
+ 80009c4: d00d beq.n 80009e2 <HAL_GPIO_Init+0x222>
+ 80009c6: 687b ldr r3, [r7, #4]
+ 80009c8: 4a4f ldr r2, [pc, #316] ; (8000b08 <HAL_GPIO_Init+0x348>)
+ 80009ca: 4293 cmp r3, r2
+ 80009cc: d007 beq.n 80009de <HAL_GPIO_Init+0x21e>
+ 80009ce: 687b ldr r3, [r7, #4]
+ 80009d0: 4a4e ldr r2, [pc, #312] ; (8000b0c <HAL_GPIO_Init+0x34c>)
+ 80009d2: 4293 cmp r3, r2
+ 80009d4: d101 bne.n 80009da <HAL_GPIO_Init+0x21a>
+ 80009d6: 2309 movs r3, #9
+ 80009d8: e012 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009da: 230a movs r3, #10
+ 80009dc: e010 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009de: 2308 movs r3, #8
+ 80009e0: e00e b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009e2: 2307 movs r3, #7
+ 80009e4: e00c b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009e6: 2306 movs r3, #6
+ 80009e8: e00a b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009ea: 2305 movs r3, #5
+ 80009ec: e008 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009ee: 2304 movs r3, #4
+ 80009f0: e006 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009f2: 2303 movs r3, #3
+ 80009f4: e004 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009f6: 2302 movs r3, #2
+ 80009f8: e002 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009fa: 2301 movs r3, #1
+ 80009fc: e000 b.n 8000a00 <HAL_GPIO_Init+0x240>
+ 80009fe: 2300 movs r3, #0
+ 8000a00: 69fa ldr r2, [r7, #28]
+ 8000a02: f002 0203 and.w r2, r2, #3
+ 8000a06: 0092 lsls r2, r2, #2
+ 8000a08: 4093 lsls r3, r2
+ 8000a0a: 69ba ldr r2, [r7, #24]
+ 8000a0c: 4313 orrs r3, r2
+ 8000a0e: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
- 8000a54: 4934 ldr r1, [pc, #208] ; (8000b28 <HAL_GPIO_Init+0x324>)
- 8000a56: 69fb ldr r3, [r7, #28]
- 8000a58: 089b lsrs r3, r3, #2
- 8000a5a: 3302 adds r3, #2
- 8000a5c: 69ba ldr r2, [r7, #24]
- 8000a5e: f841 2023 str.w r2, [r1, r3, lsl #2]
+ 8000a10: 4934 ldr r1, [pc, #208] ; (8000ae4 <HAL_GPIO_Init+0x324>)
+ 8000a12: 69fb ldr r3, [r7, #28]
+ 8000a14: 089b lsrs r3, r3, #2
+ 8000a16: 3302 adds r3, #2
+ 8000a18: 69ba ldr r2, [r7, #24]
+ 8000a1a: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
- 8000a62: 4b3c ldr r3, [pc, #240] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000a64: 681b ldr r3, [r3, #0]
- 8000a66: 61bb str r3, [r7, #24]
+ 8000a1e: 4b3c ldr r3, [pc, #240] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a20: 681b ldr r3, [r3, #0]
+ 8000a22: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000a68: 693b ldr r3, [r7, #16]
- 8000a6a: 43db mvns r3, r3
- 8000a6c: 69ba ldr r2, [r7, #24]
- 8000a6e: 4013 ands r3, r2
- 8000a70: 61bb str r3, [r7, #24]
+ 8000a24: 693b ldr r3, [r7, #16]
+ 8000a26: 43db mvns r3, r3
+ 8000a28: 69ba ldr r2, [r7, #24]
+ 8000a2a: 4013 ands r3, r2
+ 8000a2c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 8000a72: 683b ldr r3, [r7, #0]
- 8000a74: 685b ldr r3, [r3, #4]
- 8000a76: f403 3380 and.w r3, r3, #65536 ; 0x10000
- 8000a7a: 2b00 cmp r3, #0
- 8000a7c: d003 beq.n 8000a86 <HAL_GPIO_Init+0x282>
+ 8000a2e: 683b ldr r3, [r7, #0]
+ 8000a30: 685b ldr r3, [r3, #4]
+ 8000a32: f403 3380 and.w r3, r3, #65536 ; 0x10000
+ 8000a36: 2b00 cmp r3, #0
+ 8000a38: d003 beq.n 8000a42 <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
- 8000a7e: 69ba ldr r2, [r7, #24]
- 8000a80: 693b ldr r3, [r7, #16]
- 8000a82: 4313 orrs r3, r2
- 8000a84: 61bb str r3, [r7, #24]
+ 8000a3a: 69ba ldr r2, [r7, #24]
+ 8000a3c: 693b ldr r3, [r7, #16]
+ 8000a3e: 4313 orrs r3, r2
+ 8000a40: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
- 8000a86: 4a33 ldr r2, [pc, #204] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000a88: 69bb ldr r3, [r7, #24]
- 8000a8a: 6013 str r3, [r2, #0]
+ 8000a42: 4a33 ldr r2, [pc, #204] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a44: 69bb ldr r3, [r7, #24]
+ 8000a46: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
- 8000a8c: 4b31 ldr r3, [pc, #196] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000a8e: 685b ldr r3, [r3, #4]
- 8000a90: 61bb str r3, [r7, #24]
+ 8000a48: 4b31 ldr r3, [pc, #196] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a4a: 685b ldr r3, [r3, #4]
+ 8000a4c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000a92: 693b ldr r3, [r7, #16]
- 8000a94: 43db mvns r3, r3
- 8000a96: 69ba ldr r2, [r7, #24]
- 8000a98: 4013 ands r3, r2
- 8000a9a: 61bb str r3, [r7, #24]
+ 8000a4e: 693b ldr r3, [r7, #16]
+ 8000a50: 43db mvns r3, r3
+ 8000a52: 69ba ldr r2, [r7, #24]
+ 8000a54: 4013 ands r3, r2
+ 8000a56: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 8000a9c: 683b ldr r3, [r7, #0]
- 8000a9e: 685b ldr r3, [r3, #4]
- 8000aa0: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8000aa4: 2b00 cmp r3, #0
- 8000aa6: d003 beq.n 8000ab0 <HAL_GPIO_Init+0x2ac>
+ 8000a58: 683b ldr r3, [r7, #0]
+ 8000a5a: 685b ldr r3, [r3, #4]
+ 8000a5c: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000a60: 2b00 cmp r3, #0
+ 8000a62: d003 beq.n 8000a6c <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
- 8000aa8: 69ba ldr r2, [r7, #24]
- 8000aaa: 693b ldr r3, [r7, #16]
- 8000aac: 4313 orrs r3, r2
- 8000aae: 61bb str r3, [r7, #24]
+ 8000a64: 69ba ldr r2, [r7, #24]
+ 8000a66: 693b ldr r3, [r7, #16]
+ 8000a68: 4313 orrs r3, r2
+ 8000a6a: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
- 8000ab0: 4a28 ldr r2, [pc, #160] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000ab2: 69bb ldr r3, [r7, #24]
- 8000ab4: 6053 str r3, [r2, #4]
+ 8000a6c: 4a28 ldr r2, [pc, #160] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a6e: 69bb ldr r3, [r7, #24]
+ 8000a70: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
- 8000ab6: 4b27 ldr r3, [pc, #156] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000ab8: 689b ldr r3, [r3, #8]
- 8000aba: 61bb str r3, [r7, #24]
+ 8000a72: 4b27 ldr r3, [pc, #156] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a74: 689b ldr r3, [r3, #8]
+ 8000a76: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000abc: 693b ldr r3, [r7, #16]
- 8000abe: 43db mvns r3, r3
- 8000ac0: 69ba ldr r2, [r7, #24]
- 8000ac2: 4013 ands r3, r2
- 8000ac4: 61bb str r3, [r7, #24]
+ 8000a78: 693b ldr r3, [r7, #16]
+ 8000a7a: 43db mvns r3, r3
+ 8000a7c: 69ba ldr r2, [r7, #24]
+ 8000a7e: 4013 ands r3, r2
+ 8000a80: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 8000ac6: 683b ldr r3, [r7, #0]
- 8000ac8: 685b ldr r3, [r3, #4]
- 8000aca: f403 1380 and.w r3, r3, #1048576 ; 0x100000
- 8000ace: 2b00 cmp r3, #0
- 8000ad0: d003 beq.n 8000ada <HAL_GPIO_Init+0x2d6>
+ 8000a82: 683b ldr r3, [r7, #0]
+ 8000a84: 685b ldr r3, [r3, #4]
+ 8000a86: f403 1380 and.w r3, r3, #1048576 ; 0x100000
+ 8000a8a: 2b00 cmp r3, #0
+ 8000a8c: d003 beq.n 8000a96 <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
- 8000ad2: 69ba ldr r2, [r7, #24]
- 8000ad4: 693b ldr r3, [r7, #16]
- 8000ad6: 4313 orrs r3, r2
- 8000ad8: 61bb str r3, [r7, #24]
+ 8000a8e: 69ba ldr r2, [r7, #24]
+ 8000a90: 693b ldr r3, [r7, #16]
+ 8000a92: 4313 orrs r3, r2
+ 8000a94: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
- 8000ada: 4a1e ldr r2, [pc, #120] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000adc: 69bb ldr r3, [r7, #24]
- 8000ade: 6093 str r3, [r2, #8]
+ 8000a96: 4a1e ldr r2, [pc, #120] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a98: 69bb ldr r3, [r7, #24]
+ 8000a9a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
- 8000ae0: 4b1c ldr r3, [pc, #112] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000ae2: 68db ldr r3, [r3, #12]
- 8000ae4: 61bb str r3, [r7, #24]
+ 8000a9c: 4b1c ldr r3, [pc, #112] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000a9e: 68db ldr r3, [r3, #12]
+ 8000aa0: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
- 8000ae6: 693b ldr r3, [r7, #16]
- 8000ae8: 43db mvns r3, r3
- 8000aea: 69ba ldr r2, [r7, #24]
- 8000aec: 4013 ands r3, r2
- 8000aee: 61bb str r3, [r7, #24]
+ 8000aa2: 693b ldr r3, [r7, #16]
+ 8000aa4: 43db mvns r3, r3
+ 8000aa6: 69ba ldr r2, [r7, #24]
+ 8000aa8: 4013 ands r3, r2
+ 8000aaa: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 8000af0: 683b ldr r3, [r7, #0]
- 8000af2: 685b ldr r3, [r3, #4]
- 8000af4: f403 1300 and.w r3, r3, #2097152 ; 0x200000
- 8000af8: 2b00 cmp r3, #0
- 8000afa: d003 beq.n 8000b04 <HAL_GPIO_Init+0x300>
+ 8000aac: 683b ldr r3, [r7, #0]
+ 8000aae: 685b ldr r3, [r3, #4]
+ 8000ab0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
+ 8000ab4: 2b00 cmp r3, #0
+ 8000ab6: d003 beq.n 8000ac0 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
- 8000afc: 69ba ldr r2, [r7, #24]
- 8000afe: 693b ldr r3, [r7, #16]
- 8000b00: 4313 orrs r3, r2
- 8000b02: 61bb str r3, [r7, #24]
+ 8000ab8: 69ba ldr r2, [r7, #24]
+ 8000aba: 693b ldr r3, [r7, #16]
+ 8000abc: 4313 orrs r3, r2
+ 8000abe: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
- 8000b04: 4a13 ldr r2, [pc, #76] ; (8000b54 <HAL_GPIO_Init+0x350>)
- 8000b06: 69bb ldr r3, [r7, #24]
- 8000b08: 60d3 str r3, [r2, #12]
+ 8000ac0: 4a13 ldr r2, [pc, #76] ; (8000b10 <HAL_GPIO_Init+0x350>)
+ 8000ac2: 69bb ldr r3, [r7, #24]
+ 8000ac4: 60d3 str r3, [r2, #12]
for(position = 0; position < GPIO_NUMBER; position++)
- 8000b0a: 69fb ldr r3, [r7, #28]
- 8000b0c: 3301 adds r3, #1
- 8000b0e: 61fb str r3, [r7, #28]
- 8000b10: 69fb ldr r3, [r7, #28]
- 8000b12: 2b0f cmp r3, #15
- 8000b14: f67f ae86 bls.w 8000824 <HAL_GPIO_Init+0x20>
+ 8000ac6: 69fb ldr r3, [r7, #28]
+ 8000ac8: 3301 adds r3, #1
+ 8000aca: 61fb str r3, [r7, #28]
+ 8000acc: 69fb ldr r3, [r7, #28]
+ 8000ace: 2b0f cmp r3, #15
+ 8000ad0: f67f ae86 bls.w 80007e0 <HAL_GPIO_Init+0x20>
}
}
}
}
- 8000b18: bf00 nop
- 8000b1a: 3724 adds r7, #36 ; 0x24
- 8000b1c: 46bd mov sp, r7
- 8000b1e: f85d 7b04 ldr.w r7, [sp], #4
- 8000b22: 4770 bx lr
- 8000b24: 40023800 .word 0x40023800
- 8000b28: 40013800 .word 0x40013800
- 8000b2c: 40020000 .word 0x40020000
- 8000b30: 40020400 .word 0x40020400
- 8000b34: 40020800 .word 0x40020800
- 8000b38: 40020c00 .word 0x40020c00
- 8000b3c: 40021000 .word 0x40021000
- 8000b40: 40021400 .word 0x40021400
- 8000b44: 40021800 .word 0x40021800
- 8000b48: 40021c00 .word 0x40021c00
- 8000b4c: 40022000 .word 0x40022000
- 8000b50: 40022400 .word 0x40022400
- 8000b54: 40013c00 .word 0x40013c00
-
-08000b58 <HAL_RCC_OscConfig>:
+ 8000ad4: bf00 nop
+ 8000ad6: 3724 adds r7, #36 ; 0x24
+ 8000ad8: 46bd mov sp, r7
+ 8000ada: f85d 7b04 ldr.w r7, [sp], #4
+ 8000ade: 4770 bx lr
+ 8000ae0: 40023800 .word 0x40023800
+ 8000ae4: 40013800 .word 0x40013800
+ 8000ae8: 40020000 .word 0x40020000
+ 8000aec: 40020400 .word 0x40020400
+ 8000af0: 40020800 .word 0x40020800
+ 8000af4: 40020c00 .word 0x40020c00
+ 8000af8: 40021000 .word 0x40021000
+ 8000afc: 40021400 .word 0x40021400
+ 8000b00: 40021800 .word 0x40021800
+ 8000b04: 40021c00 .word 0x40021c00
+ 8000b08: 40022000 .word 0x40022000
+ 8000b0c: 40022400 .word 0x40022400
+ 8000b10: 40013c00 .word 0x40013c00
+
+08000b14 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- 8000b58: b580 push {r7, lr}
- 8000b5a: b086 sub sp, #24
- 8000b5c: af00 add r7, sp, #0
- 8000b5e: 6078 str r0, [r7, #4]
+ 8000b14: b580 push {r7, lr}
+ 8000b16: b086 sub sp, #24
+ 8000b18: af00 add r7, sp, #0
+ 8000b1a: 6078 str r0, [r7, #4]
uint32_t tickstart;
FlagStatus pwrclkchanged = RESET;
- 8000b60: 2300 movs r3, #0
- 8000b62: 75fb strb r3, [r7, #23]
+ 8000b1c: 2300 movs r3, #0
+ 8000b1e: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
- 8000b64: 687b ldr r3, [r7, #4]
- 8000b66: 2b00 cmp r3, #0
- 8000b68: d101 bne.n 8000b6e <HAL_RCC_OscConfig+0x16>
+ 8000b20: 687b ldr r3, [r7, #4]
+ 8000b22: 2b00 cmp r3, #0
+ 8000b24: d101 bne.n 8000b2a <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
- 8000b6a: 2301 movs r3, #1
- 8000b6c: e25e b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000b26: 2301 movs r3, #1
+ 8000b28: e25e b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8000b6e: 687b ldr r3, [r7, #4]
- 8000b70: 681b ldr r3, [r3, #0]
- 8000b72: f003 0301 and.w r3, r3, #1
- 8000b76: 2b00 cmp r3, #0
- 8000b78: f000 8087 beq.w 8000c8a <HAL_RCC_OscConfig+0x132>
+ 8000b2a: 687b ldr r3, [r7, #4]
+ 8000b2c: 681b ldr r3, [r3, #0]
+ 8000b2e: f003 0301 and.w r3, r3, #1
+ 8000b32: 2b00 cmp r3, #0
+ 8000b34: f000 8087 beq.w 8000c46 <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8000b7c: 4b96 ldr r3, [pc, #600] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000b7e: 689b ldr r3, [r3, #8]
- 8000b80: f003 030c and.w r3, r3, #12
- 8000b84: 2b04 cmp r3, #4
- 8000b86: d00c beq.n 8000ba2 <HAL_RCC_OscConfig+0x4a>
+ 8000b38: 4b96 ldr r3, [pc, #600] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b3a: 689b ldr r3, [r3, #8]
+ 8000b3c: f003 030c and.w r3, r3, #12
+ 8000b40: 2b04 cmp r3, #4
+ 8000b42: d00c beq.n 8000b5e <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 8000b88: 4b93 ldr r3, [pc, #588] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000b8a: 689b ldr r3, [r3, #8]
- 8000b8c: f003 030c and.w r3, r3, #12
- 8000b90: 2b08 cmp r3, #8
- 8000b92: d112 bne.n 8000bba <HAL_RCC_OscConfig+0x62>
- 8000b94: 4b90 ldr r3, [pc, #576] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000b96: 685b ldr r3, [r3, #4]
- 8000b98: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8000b9c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
- 8000ba0: d10b bne.n 8000bba <HAL_RCC_OscConfig+0x62>
+ 8000b44: 4b93 ldr r3, [pc, #588] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b46: 689b ldr r3, [r3, #8]
+ 8000b48: f003 030c and.w r3, r3, #12
+ 8000b4c: 2b08 cmp r3, #8
+ 8000b4e: d112 bne.n 8000b76 <HAL_RCC_OscConfig+0x62>
+ 8000b50: 4b90 ldr r3, [pc, #576] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b52: 685b ldr r3, [r3, #4]
+ 8000b54: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8000b58: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
+ 8000b5c: d10b bne.n 8000b76 <HAL_RCC_OscConfig+0x62>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8000ba2: 4b8d ldr r3, [pc, #564] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000ba4: 681b ldr r3, [r3, #0]
- 8000ba6: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8000baa: 2b00 cmp r3, #0
- 8000bac: d06c beq.n 8000c88 <HAL_RCC_OscConfig+0x130>
- 8000bae: 687b ldr r3, [r7, #4]
- 8000bb0: 685b ldr r3, [r3, #4]
- 8000bb2: 2b00 cmp r3, #0
- 8000bb4: d168 bne.n 8000c88 <HAL_RCC_OscConfig+0x130>
+ 8000b5e: 4b8d ldr r3, [pc, #564] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b60: 681b ldr r3, [r3, #0]
+ 8000b62: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000b66: 2b00 cmp r3, #0
+ 8000b68: d06c beq.n 8000c44 <HAL_RCC_OscConfig+0x130>
+ 8000b6a: 687b ldr r3, [r7, #4]
+ 8000b6c: 685b ldr r3, [r3, #4]
+ 8000b6e: 2b00 cmp r3, #0
+ 8000b70: d168 bne.n 8000c44 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
- 8000bb6: 2301 movs r3, #1
- 8000bb8: e238 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000b72: 2301 movs r3, #1
+ 8000b74: e238 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 8000bba: 687b ldr r3, [r7, #4]
- 8000bbc: 685b ldr r3, [r3, #4]
- 8000bbe: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8000bc2: d106 bne.n 8000bd2 <HAL_RCC_OscConfig+0x7a>
- 8000bc4: 4b84 ldr r3, [pc, #528] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000bc6: 681b ldr r3, [r3, #0]
- 8000bc8: 4a83 ldr r2, [pc, #524] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000bca: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8000bce: 6013 str r3, [r2, #0]
- 8000bd0: e02e b.n 8000c30 <HAL_RCC_OscConfig+0xd8>
- 8000bd2: 687b ldr r3, [r7, #4]
- 8000bd4: 685b ldr r3, [r3, #4]
- 8000bd6: 2b00 cmp r3, #0
- 8000bd8: d10c bne.n 8000bf4 <HAL_RCC_OscConfig+0x9c>
- 8000bda: 4b7f ldr r3, [pc, #508] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000bdc: 681b ldr r3, [r3, #0]
- 8000bde: 4a7e ldr r2, [pc, #504] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000be0: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8000be4: 6013 str r3, [r2, #0]
- 8000be6: 4b7c ldr r3, [pc, #496] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000be8: 681b ldr r3, [r3, #0]
- 8000bea: 4a7b ldr r2, [pc, #492] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000bec: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8000bf0: 6013 str r3, [r2, #0]
- 8000bf2: e01d b.n 8000c30 <HAL_RCC_OscConfig+0xd8>
- 8000bf4: 687b ldr r3, [r7, #4]
- 8000bf6: 685b ldr r3, [r3, #4]
- 8000bf8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
- 8000bfc: d10c bne.n 8000c18 <HAL_RCC_OscConfig+0xc0>
- 8000bfe: 4b76 ldr r3, [pc, #472] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c00: 681b ldr r3, [r3, #0]
- 8000c02: 4a75 ldr r2, [pc, #468] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c04: f443 2380 orr.w r3, r3, #262144 ; 0x40000
- 8000c08: 6013 str r3, [r2, #0]
- 8000c0a: 4b73 ldr r3, [pc, #460] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c0c: 681b ldr r3, [r3, #0]
- 8000c0e: 4a72 ldr r2, [pc, #456] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c10: f443 3380 orr.w r3, r3, #65536 ; 0x10000
- 8000c14: 6013 str r3, [r2, #0]
- 8000c16: e00b b.n 8000c30 <HAL_RCC_OscConfig+0xd8>
- 8000c18: 4b6f ldr r3, [pc, #444] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c1a: 681b ldr r3, [r3, #0]
- 8000c1c: 4a6e ldr r2, [pc, #440] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c1e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8000c22: 6013 str r3, [r2, #0]
- 8000c24: 4b6c ldr r3, [pc, #432] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c26: 681b ldr r3, [r3, #0]
- 8000c28: 4a6b ldr r2, [pc, #428] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c2a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8000c2e: 6013 str r3, [r2, #0]
+ 8000b76: 687b ldr r3, [r7, #4]
+ 8000b78: 685b ldr r3, [r3, #4]
+ 8000b7a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 8000b7e: d106 bne.n 8000b8e <HAL_RCC_OscConfig+0x7a>
+ 8000b80: 4b84 ldr r3, [pc, #528] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b82: 681b ldr r3, [r3, #0]
+ 8000b84: 4a83 ldr r2, [pc, #524] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b86: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8000b8a: 6013 str r3, [r2, #0]
+ 8000b8c: e02e b.n 8000bec <HAL_RCC_OscConfig+0xd8>
+ 8000b8e: 687b ldr r3, [r7, #4]
+ 8000b90: 685b ldr r3, [r3, #4]
+ 8000b92: 2b00 cmp r3, #0
+ 8000b94: d10c bne.n 8000bb0 <HAL_RCC_OscConfig+0x9c>
+ 8000b96: 4b7f ldr r3, [pc, #508] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b98: 681b ldr r3, [r3, #0]
+ 8000b9a: 4a7e ldr r2, [pc, #504] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000b9c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8000ba0: 6013 str r3, [r2, #0]
+ 8000ba2: 4b7c ldr r3, [pc, #496] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000ba4: 681b ldr r3, [r3, #0]
+ 8000ba6: 4a7b ldr r2, [pc, #492] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000ba8: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8000bac: 6013 str r3, [r2, #0]
+ 8000bae: e01d b.n 8000bec <HAL_RCC_OscConfig+0xd8>
+ 8000bb0: 687b ldr r3, [r7, #4]
+ 8000bb2: 685b ldr r3, [r3, #4]
+ 8000bb4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
+ 8000bb8: d10c bne.n 8000bd4 <HAL_RCC_OscConfig+0xc0>
+ 8000bba: 4b76 ldr r3, [pc, #472] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bbc: 681b ldr r3, [r3, #0]
+ 8000bbe: 4a75 ldr r2, [pc, #468] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bc0: f443 2380 orr.w r3, r3, #262144 ; 0x40000
+ 8000bc4: 6013 str r3, [r2, #0]
+ 8000bc6: 4b73 ldr r3, [pc, #460] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bc8: 681b ldr r3, [r3, #0]
+ 8000bca: 4a72 ldr r2, [pc, #456] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bcc: f443 3380 orr.w r3, r3, #65536 ; 0x10000
+ 8000bd0: 6013 str r3, [r2, #0]
+ 8000bd2: e00b b.n 8000bec <HAL_RCC_OscConfig+0xd8>
+ 8000bd4: 4b6f ldr r3, [pc, #444] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bd6: 681b ldr r3, [r3, #0]
+ 8000bd8: 4a6e ldr r2, [pc, #440] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000bda: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8000bde: 6013 str r3, [r2, #0]
+ 8000be0: 4b6c ldr r3, [pc, #432] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000be2: 681b ldr r3, [r3, #0]
+ 8000be4: 4a6b ldr r2, [pc, #428] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000be6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8000bea: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8000c30: 687b ldr r3, [r7, #4]
- 8000c32: 685b ldr r3, [r3, #4]
- 8000c34: 2b00 cmp r3, #0
- 8000c36: d013 beq.n 8000c60 <HAL_RCC_OscConfig+0x108>
+ 8000bec: 687b ldr r3, [r7, #4]
+ 8000bee: 685b ldr r3, [r3, #4]
+ 8000bf0: 2b00 cmp r3, #0
+ 8000bf2: d013 beq.n 8000c1c <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000c38: f7ff fcd0 bl 80005dc <HAL_GetTick>
- 8000c3c: 6138 str r0, [r7, #16]
+ 8000bf4: f7ff fcf2 bl 80005dc <HAL_GetTick>
+ 8000bf8: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8000c3e: e008 b.n 8000c52 <HAL_RCC_OscConfig+0xfa>
+ 8000bfa: e008 b.n 8000c0e <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8000c40: f7ff fccc bl 80005dc <HAL_GetTick>
- 8000c44: 4602 mov r2, r0
- 8000c46: 693b ldr r3, [r7, #16]
- 8000c48: 1ad3 subs r3, r2, r3
- 8000c4a: 2b64 cmp r3, #100 ; 0x64
- 8000c4c: d901 bls.n 8000c52 <HAL_RCC_OscConfig+0xfa>
+ 8000bfc: f7ff fcee bl 80005dc <HAL_GetTick>
+ 8000c00: 4602 mov r2, r0
+ 8000c02: 693b ldr r3, [r7, #16]
+ 8000c04: 1ad3 subs r3, r2, r3
+ 8000c06: 2b64 cmp r3, #100 ; 0x64
+ 8000c08: d901 bls.n 8000c0e <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
- 8000c4e: 2303 movs r3, #3
- 8000c50: e1ec b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000c0a: 2303 movs r3, #3
+ 8000c0c: e1ec b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8000c52: 4b61 ldr r3, [pc, #388] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c54: 681b ldr r3, [r3, #0]
- 8000c56: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8000c5a: 2b00 cmp r3, #0
- 8000c5c: d0f0 beq.n 8000c40 <HAL_RCC_OscConfig+0xe8>
- 8000c5e: e014 b.n 8000c8a <HAL_RCC_OscConfig+0x132>
+ 8000c0e: 4b61 ldr r3, [pc, #388] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c10: 681b ldr r3, [r3, #0]
+ 8000c12: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000c16: 2b00 cmp r3, #0
+ 8000c18: d0f0 beq.n 8000bfc <HAL_RCC_OscConfig+0xe8>
+ 8000c1a: e014 b.n 8000c46 <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000c60: f7ff fcbc bl 80005dc <HAL_GetTick>
- 8000c64: 6138 str r0, [r7, #16]
+ 8000c1c: f7ff fcde bl 80005dc <HAL_GetTick>
+ 8000c20: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8000c66: e008 b.n 8000c7a <HAL_RCC_OscConfig+0x122>
+ 8000c22: e008 b.n 8000c36 <HAL_RCC_OscConfig+0x122>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8000c68: f7ff fcb8 bl 80005dc <HAL_GetTick>
- 8000c6c: 4602 mov r2, r0
- 8000c6e: 693b ldr r3, [r7, #16]
- 8000c70: 1ad3 subs r3, r2, r3
- 8000c72: 2b64 cmp r3, #100 ; 0x64
- 8000c74: d901 bls.n 8000c7a <HAL_RCC_OscConfig+0x122>
+ 8000c24: f7ff fcda bl 80005dc <HAL_GetTick>
+ 8000c28: 4602 mov r2, r0
+ 8000c2a: 693b ldr r3, [r7, #16]
+ 8000c2c: 1ad3 subs r3, r2, r3
+ 8000c2e: 2b64 cmp r3, #100 ; 0x64
+ 8000c30: d901 bls.n 8000c36 <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
- 8000c76: 2303 movs r3, #3
- 8000c78: e1d8 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000c32: 2303 movs r3, #3
+ 8000c34: e1d8 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 8000c7a: 4b57 ldr r3, [pc, #348] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c7c: 681b ldr r3, [r3, #0]
- 8000c7e: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 8000c82: 2b00 cmp r3, #0
- 8000c84: d1f0 bne.n 8000c68 <HAL_RCC_OscConfig+0x110>
- 8000c86: e000 b.n 8000c8a <HAL_RCC_OscConfig+0x132>
+ 8000c36: 4b57 ldr r3, [pc, #348] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c38: 681b ldr r3, [r3, #0]
+ 8000c3a: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 8000c3e: 2b00 cmp r3, #0
+ 8000c40: d1f0 bne.n 8000c24 <HAL_RCC_OscConfig+0x110>
+ 8000c42: e000 b.n 8000c46 <HAL_RCC_OscConfig+0x132>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8000c88: bf00 nop
+ 8000c44: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8000c8a: 687b ldr r3, [r7, #4]
- 8000c8c: 681b ldr r3, [r3, #0]
- 8000c8e: f003 0302 and.w r3, r3, #2
- 8000c92: 2b00 cmp r3, #0
- 8000c94: d069 beq.n 8000d6a <HAL_RCC_OscConfig+0x212>
+ 8000c46: 687b ldr r3, [r7, #4]
+ 8000c48: 681b ldr r3, [r3, #0]
+ 8000c4a: f003 0302 and.w r3, r3, #2
+ 8000c4e: 2b00 cmp r3, #0
+ 8000c50: d069 beq.n 8000d26 <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- 8000c96: 4b50 ldr r3, [pc, #320] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000c98: 689b ldr r3, [r3, #8]
- 8000c9a: f003 030c and.w r3, r3, #12
- 8000c9e: 2b00 cmp r3, #0
- 8000ca0: d00b beq.n 8000cba <HAL_RCC_OscConfig+0x162>
+ 8000c52: 4b50 ldr r3, [pc, #320] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c54: 689b ldr r3, [r3, #8]
+ 8000c56: f003 030c and.w r3, r3, #12
+ 8000c5a: 2b00 cmp r3, #0
+ 8000c5c: d00b beq.n 8000c76 <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 8000ca2: 4b4d ldr r3, [pc, #308] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000ca4: 689b ldr r3, [r3, #8]
- 8000ca6: f003 030c and.w r3, r3, #12
- 8000caa: 2b08 cmp r3, #8
- 8000cac: d11c bne.n 8000ce8 <HAL_RCC_OscConfig+0x190>
- 8000cae: 4b4a ldr r3, [pc, #296] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000cb0: 685b ldr r3, [r3, #4]
- 8000cb2: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8000cb6: 2b00 cmp r3, #0
- 8000cb8: d116 bne.n 8000ce8 <HAL_RCC_OscConfig+0x190>
+ 8000c5e: 4b4d ldr r3, [pc, #308] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c60: 689b ldr r3, [r3, #8]
+ 8000c62: f003 030c and.w r3, r3, #12
+ 8000c66: 2b08 cmp r3, #8
+ 8000c68: d11c bne.n 8000ca4 <HAL_RCC_OscConfig+0x190>
+ 8000c6a: 4b4a ldr r3, [pc, #296] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c6c: 685b ldr r3, [r3, #4]
+ 8000c6e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8000c72: 2b00 cmp r3, #0
+ 8000c74: d116 bne.n 8000ca4 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8000cba: 4b47 ldr r3, [pc, #284] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000cbc: 681b ldr r3, [r3, #0]
- 8000cbe: f003 0302 and.w r3, r3, #2
- 8000cc2: 2b00 cmp r3, #0
- 8000cc4: d005 beq.n 8000cd2 <HAL_RCC_OscConfig+0x17a>
- 8000cc6: 687b ldr r3, [r7, #4]
- 8000cc8: 68db ldr r3, [r3, #12]
- 8000cca: 2b01 cmp r3, #1
- 8000ccc: d001 beq.n 8000cd2 <HAL_RCC_OscConfig+0x17a>
+ 8000c76: 4b47 ldr r3, [pc, #284] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c78: 681b ldr r3, [r3, #0]
+ 8000c7a: f003 0302 and.w r3, r3, #2
+ 8000c7e: 2b00 cmp r3, #0
+ 8000c80: d005 beq.n 8000c8e <HAL_RCC_OscConfig+0x17a>
+ 8000c82: 687b ldr r3, [r7, #4]
+ 8000c84: 68db ldr r3, [r3, #12]
+ 8000c86: 2b01 cmp r3, #1
+ 8000c88: d001 beq.n 8000c8e <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
- 8000cce: 2301 movs r3, #1
- 8000cd0: e1ac b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000c8a: 2301 movs r3, #1
+ 8000c8c: e1ac b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8000cd2: 4b41 ldr r3, [pc, #260] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000cd4: 681b ldr r3, [r3, #0]
- 8000cd6: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 8000cda: 687b ldr r3, [r7, #4]
- 8000cdc: 691b ldr r3, [r3, #16]
- 8000cde: 00db lsls r3, r3, #3
- 8000ce0: 493d ldr r1, [pc, #244] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000ce2: 4313 orrs r3, r2
- 8000ce4: 600b str r3, [r1, #0]
+ 8000c8e: 4b41 ldr r3, [pc, #260] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c90: 681b ldr r3, [r3, #0]
+ 8000c92: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 8000c96: 687b ldr r3, [r7, #4]
+ 8000c98: 691b ldr r3, [r3, #16]
+ 8000c9a: 00db lsls r3, r3, #3
+ 8000c9c: 493d ldr r1, [pc, #244] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000c9e: 4313 orrs r3, r2
+ 8000ca0: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8000ce6: e040 b.n 8000d6a <HAL_RCC_OscConfig+0x212>
+ 8000ca2: e040 b.n 8000d26 <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 8000ce8: 687b ldr r3, [r7, #4]
- 8000cea: 68db ldr r3, [r3, #12]
- 8000cec: 2b00 cmp r3, #0
- 8000cee: d023 beq.n 8000d38 <HAL_RCC_OscConfig+0x1e0>
+ 8000ca4: 687b ldr r3, [r7, #4]
+ 8000ca6: 68db ldr r3, [r3, #12]
+ 8000ca8: 2b00 cmp r3, #0
+ 8000caa: d023 beq.n 8000cf4 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
- 8000cf0: 4b39 ldr r3, [pc, #228] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000cf2: 681b ldr r3, [r3, #0]
- 8000cf4: 4a38 ldr r2, [pc, #224] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000cf6: f043 0301 orr.w r3, r3, #1
- 8000cfa: 6013 str r3, [r2, #0]
+ 8000cac: 4b39 ldr r3, [pc, #228] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cae: 681b ldr r3, [r3, #0]
+ 8000cb0: 4a38 ldr r2, [pc, #224] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cb2: f043 0301 orr.w r3, r3, #1
+ 8000cb6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000cfc: f7ff fc6e bl 80005dc <HAL_GetTick>
- 8000d00: 6138 str r0, [r7, #16]
+ 8000cb8: f7ff fc90 bl 80005dc <HAL_GetTick>
+ 8000cbc: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8000d02: e008 b.n 8000d16 <HAL_RCC_OscConfig+0x1be>
+ 8000cbe: e008 b.n 8000cd2 <HAL_RCC_OscConfig+0x1be>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8000d04: f7ff fc6a bl 80005dc <HAL_GetTick>
- 8000d08: 4602 mov r2, r0
- 8000d0a: 693b ldr r3, [r7, #16]
- 8000d0c: 1ad3 subs r3, r2, r3
- 8000d0e: 2b02 cmp r3, #2
- 8000d10: d901 bls.n 8000d16 <HAL_RCC_OscConfig+0x1be>
+ 8000cc0: f7ff fc8c bl 80005dc <HAL_GetTick>
+ 8000cc4: 4602 mov r2, r0
+ 8000cc6: 693b ldr r3, [r7, #16]
+ 8000cc8: 1ad3 subs r3, r2, r3
+ 8000cca: 2b02 cmp r3, #2
+ 8000ccc: d901 bls.n 8000cd2 <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
- 8000d12: 2303 movs r3, #3
- 8000d14: e18a b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000cce: 2303 movs r3, #3
+ 8000cd0: e18a b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8000d16: 4b30 ldr r3, [pc, #192] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d18: 681b ldr r3, [r3, #0]
- 8000d1a: f003 0302 and.w r3, r3, #2
- 8000d1e: 2b00 cmp r3, #0
- 8000d20: d0f0 beq.n 8000d04 <HAL_RCC_OscConfig+0x1ac>
+ 8000cd2: 4b30 ldr r3, [pc, #192] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cd4: 681b ldr r3, [r3, #0]
+ 8000cd6: f003 0302 and.w r3, r3, #2
+ 8000cda: 2b00 cmp r3, #0
+ 8000cdc: d0f0 beq.n 8000cc0 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8000d22: 4b2d ldr r3, [pc, #180] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d24: 681b ldr r3, [r3, #0]
- 8000d26: f023 02f8 bic.w r2, r3, #248 ; 0xf8
- 8000d2a: 687b ldr r3, [r7, #4]
- 8000d2c: 691b ldr r3, [r3, #16]
- 8000d2e: 00db lsls r3, r3, #3
- 8000d30: 4929 ldr r1, [pc, #164] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d32: 4313 orrs r3, r2
- 8000d34: 600b str r3, [r1, #0]
- 8000d36: e018 b.n 8000d6a <HAL_RCC_OscConfig+0x212>
+ 8000cde: 4b2d ldr r3, [pc, #180] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000ce0: 681b ldr r3, [r3, #0]
+ 8000ce2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
+ 8000ce6: 687b ldr r3, [r7, #4]
+ 8000ce8: 691b ldr r3, [r3, #16]
+ 8000cea: 00db lsls r3, r3, #3
+ 8000cec: 4929 ldr r1, [pc, #164] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cee: 4313 orrs r3, r2
+ 8000cf0: 600b str r3, [r1, #0]
+ 8000cf2: e018 b.n 8000d26 <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
- 8000d38: 4b27 ldr r3, [pc, #156] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d3a: 681b ldr r3, [r3, #0]
- 8000d3c: 4a26 ldr r2, [pc, #152] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d3e: f023 0301 bic.w r3, r3, #1
- 8000d42: 6013 str r3, [r2, #0]
+ 8000cf4: 4b27 ldr r3, [pc, #156] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cf6: 681b ldr r3, [r3, #0]
+ 8000cf8: 4a26 ldr r2, [pc, #152] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000cfa: f023 0301 bic.w r3, r3, #1
+ 8000cfe: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000d44: f7ff fc4a bl 80005dc <HAL_GetTick>
- 8000d48: 6138 str r0, [r7, #16]
+ 8000d00: f7ff fc6c bl 80005dc <HAL_GetTick>
+ 8000d04: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8000d4a: e008 b.n 8000d5e <HAL_RCC_OscConfig+0x206>
+ 8000d06: e008 b.n 8000d1a <HAL_RCC_OscConfig+0x206>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8000d4c: f7ff fc46 bl 80005dc <HAL_GetTick>
- 8000d50: 4602 mov r2, r0
- 8000d52: 693b ldr r3, [r7, #16]
- 8000d54: 1ad3 subs r3, r2, r3
- 8000d56: 2b02 cmp r3, #2
- 8000d58: d901 bls.n 8000d5e <HAL_RCC_OscConfig+0x206>
+ 8000d08: f7ff fc68 bl 80005dc <HAL_GetTick>
+ 8000d0c: 4602 mov r2, r0
+ 8000d0e: 693b ldr r3, [r7, #16]
+ 8000d10: 1ad3 subs r3, r2, r3
+ 8000d12: 2b02 cmp r3, #2
+ 8000d14: d901 bls.n 8000d1a <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
- 8000d5a: 2303 movs r3, #3
- 8000d5c: e166 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000d16: 2303 movs r3, #3
+ 8000d18: e166 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8000d5e: 4b1e ldr r3, [pc, #120] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d60: 681b ldr r3, [r3, #0]
- 8000d62: f003 0302 and.w r3, r3, #2
- 8000d66: 2b00 cmp r3, #0
- 8000d68: d1f0 bne.n 8000d4c <HAL_RCC_OscConfig+0x1f4>
+ 8000d1a: 4b1e ldr r3, [pc, #120] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d1c: 681b ldr r3, [r3, #0]
+ 8000d1e: f003 0302 and.w r3, r3, #2
+ 8000d22: 2b00 cmp r3, #0
+ 8000d24: d1f0 bne.n 8000d08 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8000d6a: 687b ldr r3, [r7, #4]
- 8000d6c: 681b ldr r3, [r3, #0]
- 8000d6e: f003 0308 and.w r3, r3, #8
- 8000d72: 2b00 cmp r3, #0
- 8000d74: d038 beq.n 8000de8 <HAL_RCC_OscConfig+0x290>
+ 8000d26: 687b ldr r3, [r7, #4]
+ 8000d28: 681b ldr r3, [r3, #0]
+ 8000d2a: f003 0308 and.w r3, r3, #8
+ 8000d2e: 2b00 cmp r3, #0
+ 8000d30: d038 beq.n 8000da4 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 8000d76: 687b ldr r3, [r7, #4]
- 8000d78: 695b ldr r3, [r3, #20]
- 8000d7a: 2b00 cmp r3, #0
- 8000d7c: d019 beq.n 8000db2 <HAL_RCC_OscConfig+0x25a>
+ 8000d32: 687b ldr r3, [r7, #4]
+ 8000d34: 695b ldr r3, [r3, #20]
+ 8000d36: 2b00 cmp r3, #0
+ 8000d38: d019 beq.n 8000d6e <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
- 8000d7e: 4b16 ldr r3, [pc, #88] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d80: 6f5b ldr r3, [r3, #116] ; 0x74
- 8000d82: 4a15 ldr r2, [pc, #84] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000d84: f043 0301 orr.w r3, r3, #1
- 8000d88: 6753 str r3, [r2, #116] ; 0x74
+ 8000d3a: 4b16 ldr r3, [pc, #88] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d3c: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d3e: 4a15 ldr r2, [pc, #84] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d40: f043 0301 orr.w r3, r3, #1
+ 8000d44: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000d8a: f7ff fc27 bl 80005dc <HAL_GetTick>
- 8000d8e: 6138 str r0, [r7, #16]
+ 8000d46: f7ff fc49 bl 80005dc <HAL_GetTick>
+ 8000d4a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8000d90: e008 b.n 8000da4 <HAL_RCC_OscConfig+0x24c>
+ 8000d4c: e008 b.n 8000d60 <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8000d92: f7ff fc23 bl 80005dc <HAL_GetTick>
- 8000d96: 4602 mov r2, r0
- 8000d98: 693b ldr r3, [r7, #16]
- 8000d9a: 1ad3 subs r3, r2, r3
- 8000d9c: 2b02 cmp r3, #2
- 8000d9e: d901 bls.n 8000da4 <HAL_RCC_OscConfig+0x24c>
+ 8000d4e: f7ff fc45 bl 80005dc <HAL_GetTick>
+ 8000d52: 4602 mov r2, r0
+ 8000d54: 693b ldr r3, [r7, #16]
+ 8000d56: 1ad3 subs r3, r2, r3
+ 8000d58: 2b02 cmp r3, #2
+ 8000d5a: d901 bls.n 8000d60 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
- 8000da0: 2303 movs r3, #3
- 8000da2: e143 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000d5c: 2303 movs r3, #3
+ 8000d5e: e143 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8000da4: 4b0c ldr r3, [pc, #48] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000da6: 6f5b ldr r3, [r3, #116] ; 0x74
- 8000da8: f003 0302 and.w r3, r3, #2
- 8000dac: 2b00 cmp r3, #0
- 8000dae: d0f0 beq.n 8000d92 <HAL_RCC_OscConfig+0x23a>
- 8000db0: e01a b.n 8000de8 <HAL_RCC_OscConfig+0x290>
+ 8000d60: 4b0c ldr r3, [pc, #48] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d62: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d64: f003 0302 and.w r3, r3, #2
+ 8000d68: 2b00 cmp r3, #0
+ 8000d6a: d0f0 beq.n 8000d4e <HAL_RCC_OscConfig+0x23a>
+ 8000d6c: e01a b.n 8000da4 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
- 8000db2: 4b09 ldr r3, [pc, #36] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000db4: 6f5b ldr r3, [r3, #116] ; 0x74
- 8000db6: 4a08 ldr r2, [pc, #32] ; (8000dd8 <HAL_RCC_OscConfig+0x280>)
- 8000db8: f023 0301 bic.w r3, r3, #1
- 8000dbc: 6753 str r3, [r2, #116] ; 0x74
+ 8000d6e: 4b09 ldr r3, [pc, #36] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d70: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d72: 4a08 ldr r2, [pc, #32] ; (8000d94 <HAL_RCC_OscConfig+0x280>)
+ 8000d74: f023 0301 bic.w r3, r3, #1
+ 8000d78: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000dbe: f7ff fc0d bl 80005dc <HAL_GetTick>
- 8000dc2: 6138 str r0, [r7, #16]
+ 8000d7a: f7ff fc2f bl 80005dc <HAL_GetTick>
+ 8000d7e: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8000dc4: e00a b.n 8000ddc <HAL_RCC_OscConfig+0x284>
+ 8000d80: e00a b.n 8000d98 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8000dc6: f7ff fc09 bl 80005dc <HAL_GetTick>
- 8000dca: 4602 mov r2, r0
- 8000dcc: 693b ldr r3, [r7, #16]
- 8000dce: 1ad3 subs r3, r2, r3
- 8000dd0: 2b02 cmp r3, #2
- 8000dd2: d903 bls.n 8000ddc <HAL_RCC_OscConfig+0x284>
+ 8000d82: f7ff fc2b bl 80005dc <HAL_GetTick>
+ 8000d86: 4602 mov r2, r0
+ 8000d88: 693b ldr r3, [r7, #16]
+ 8000d8a: 1ad3 subs r3, r2, r3
+ 8000d8c: 2b02 cmp r3, #2
+ 8000d8e: d903 bls.n 8000d98 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
- 8000dd4: 2303 movs r3, #3
- 8000dd6: e129 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
- 8000dd8: 40023800 .word 0x40023800
+ 8000d90: 2303 movs r3, #3
+ 8000d92: e129 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
+ 8000d94: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8000ddc: 4b95 ldr r3, [pc, #596] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000dde: 6f5b ldr r3, [r3, #116] ; 0x74
- 8000de0: f003 0302 and.w r3, r3, #2
- 8000de4: 2b00 cmp r3, #0
- 8000de6: d1ee bne.n 8000dc6 <HAL_RCC_OscConfig+0x26e>
+ 8000d98: 4b95 ldr r3, [pc, #596] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000d9a: 6f5b ldr r3, [r3, #116] ; 0x74
+ 8000d9c: f003 0302 and.w r3, r3, #2
+ 8000da0: 2b00 cmp r3, #0
+ 8000da2: d1ee bne.n 8000d82 <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 8000de8: 687b ldr r3, [r7, #4]
- 8000dea: 681b ldr r3, [r3, #0]
- 8000dec: f003 0304 and.w r3, r3, #4
- 8000df0: 2b00 cmp r3, #0
- 8000df2: f000 80a4 beq.w 8000f3e <HAL_RCC_OscConfig+0x3e6>
+ 8000da4: 687b ldr r3, [r7, #4]
+ 8000da6: 681b ldr r3, [r3, #0]
+ 8000da8: f003 0304 and.w r3, r3, #4
+ 8000dac: 2b00 cmp r3, #0
+ 8000dae: f000 80a4 beq.w 8000efa <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 8000df6: 4b8f ldr r3, [pc, #572] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000df8: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000dfa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000dfe: 2b00 cmp r3, #0
- 8000e00: d10d bne.n 8000e1e <HAL_RCC_OscConfig+0x2c6>
+ 8000db2: 4b8f ldr r3, [pc, #572] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000db4: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000db6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000dba: 2b00 cmp r3, #0
+ 8000dbc: d10d bne.n 8000dda <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
- 8000e02: 4b8c ldr r3, [pc, #560] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e04: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000e06: 4a8b ldr r2, [pc, #556] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e08: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8000e0c: 6413 str r3, [r2, #64] ; 0x40
- 8000e0e: 4b89 ldr r3, [pc, #548] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e10: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000e12: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8000e16: 60fb str r3, [r7, #12]
- 8000e18: 68fb ldr r3, [r7, #12]
+ 8000dbe: 4b8c ldr r3, [pc, #560] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000dc0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000dc2: 4a8b ldr r2, [pc, #556] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000dc4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8000dc8: 6413 str r3, [r2, #64] ; 0x40
+ 8000dca: 4b89 ldr r3, [pc, #548] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000dcc: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000dce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8000dd2: 60fb str r3, [r7, #12]
+ 8000dd4: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
- 8000e1a: 2301 movs r3, #1
- 8000e1c: 75fb strb r3, [r7, #23]
+ 8000dd6: 2301 movs r3, #1
+ 8000dd8: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8000e1e: 4b86 ldr r3, [pc, #536] ; (8001038 <HAL_RCC_OscConfig+0x4e0>)
- 8000e20: 681b ldr r3, [r3, #0]
- 8000e22: f403 7380 and.w r3, r3, #256 ; 0x100
- 8000e26: 2b00 cmp r3, #0
- 8000e28: d118 bne.n 8000e5c <HAL_RCC_OscConfig+0x304>
+ 8000dda: 4b86 ldr r3, [pc, #536] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000ddc: 681b ldr r3, [r3, #0]
+ 8000dde: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8000de2: 2b00 cmp r3, #0
+ 8000de4: d118 bne.n 8000e18 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
- 8000e2a: 4b83 ldr r3, [pc, #524] ; (8001038 <HAL_RCC_OscConfig+0x4e0>)
- 8000e2c: 681b ldr r3, [r3, #0]
- 8000e2e: 4a82 ldr r2, [pc, #520] ; (8001038 <HAL_RCC_OscConfig+0x4e0>)
- 8000e30: f443 7380 orr.w r3, r3, #256 ; 0x100
- 8000e34: 6013 str r3, [r2, #0]
+ 8000de6: 4b83 ldr r3, [pc, #524] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000de8: 681b ldr r3, [r3, #0]
+ 8000dea: 4a82 ldr r2, [pc, #520] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000dec: f443 7380 orr.w r3, r3, #256 ; 0x100
+ 8000df0: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
- 8000e36: f7ff fbd1 bl 80005dc <HAL_GetTick>
- 8000e3a: 6138 str r0, [r7, #16]
+ 8000df2: f7ff fbf3 bl 80005dc <HAL_GetTick>
+ 8000df6: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8000e3c: e008 b.n 8000e50 <HAL_RCC_OscConfig+0x2f8>
+ 8000df8: e008 b.n 8000e0c <HAL_RCC_OscConfig+0x2f8>
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- 8000e3e: f7ff fbcd bl 80005dc <HAL_GetTick>
- 8000e42: 4602 mov r2, r0
- 8000e44: 693b ldr r3, [r7, #16]
- 8000e46: 1ad3 subs r3, r2, r3
- 8000e48: 2b64 cmp r3, #100 ; 0x64
- 8000e4a: d901 bls.n 8000e50 <HAL_RCC_OscConfig+0x2f8>
+ 8000dfa: f7ff fbef bl 80005dc <HAL_GetTick>
+ 8000dfe: 4602 mov r2, r0
+ 8000e00: 693b ldr r3, [r7, #16]
+ 8000e02: 1ad3 subs r3, r2, r3
+ 8000e04: 2b64 cmp r3, #100 ; 0x64
+ 8000e06: d901 bls.n 8000e0c <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
- 8000e4c: 2303 movs r3, #3
- 8000e4e: e0ed b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000e08: 2303 movs r3, #3
+ 8000e0a: e0ed b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- 8000e50: 4b79 ldr r3, [pc, #484] ; (8001038 <HAL_RCC_OscConfig+0x4e0>)
- 8000e52: 681b ldr r3, [r3, #0]
- 8000e54: f403 7380 and.w r3, r3, #256 ; 0x100
- 8000e58: 2b00 cmp r3, #0
- 8000e5a: d0f0 beq.n 8000e3e <HAL_RCC_OscConfig+0x2e6>
+ 8000e0c: 4b79 ldr r3, [pc, #484] ; (8000ff4 <HAL_RCC_OscConfig+0x4e0>)
+ 8000e0e: 681b ldr r3, [r3, #0]
+ 8000e10: f403 7380 and.w r3, r3, #256 ; 0x100
+ 8000e14: 2b00 cmp r3, #0
+ 8000e16: d0f0 beq.n 8000dfa <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8000e5c: 687b ldr r3, [r7, #4]
- 8000e5e: 689b ldr r3, [r3, #8]
- 8000e60: 2b01 cmp r3, #1
- 8000e62: d106 bne.n 8000e72 <HAL_RCC_OscConfig+0x31a>
- 8000e64: 4b73 ldr r3, [pc, #460] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e18: 687b ldr r3, [r7, #4]
+ 8000e1a: 689b ldr r3, [r3, #8]
+ 8000e1c: 2b01 cmp r3, #1
+ 8000e1e: d106 bne.n 8000e2e <HAL_RCC_OscConfig+0x31a>
+ 8000e20: 4b73 ldr r3, [pc, #460] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e22: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e24: 4a72 ldr r2, [pc, #456] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e26: f043 0301 orr.w r3, r3, #1
+ 8000e2a: 6713 str r3, [r2, #112] ; 0x70
+ 8000e2c: e02d b.n 8000e8a <HAL_RCC_OscConfig+0x376>
+ 8000e2e: 687b ldr r3, [r7, #4]
+ 8000e30: 689b ldr r3, [r3, #8]
+ 8000e32: 2b00 cmp r3, #0
+ 8000e34: d10c bne.n 8000e50 <HAL_RCC_OscConfig+0x33c>
+ 8000e36: 4b6e ldr r3, [pc, #440] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e38: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e3a: 4a6d ldr r2, [pc, #436] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e3c: f023 0301 bic.w r3, r3, #1
+ 8000e40: 6713 str r3, [r2, #112] ; 0x70
+ 8000e42: 4b6b ldr r3, [pc, #428] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e44: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e46: 4a6a ldr r2, [pc, #424] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e48: f023 0304 bic.w r3, r3, #4
+ 8000e4c: 6713 str r3, [r2, #112] ; 0x70
+ 8000e4e: e01c b.n 8000e8a <HAL_RCC_OscConfig+0x376>
+ 8000e50: 687b ldr r3, [r7, #4]
+ 8000e52: 689b ldr r3, [r3, #8]
+ 8000e54: 2b05 cmp r3, #5
+ 8000e56: d10c bne.n 8000e72 <HAL_RCC_OscConfig+0x35e>
+ 8000e58: 4b65 ldr r3, [pc, #404] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e5a: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e5c: 4a64 ldr r2, [pc, #400] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e5e: f043 0304 orr.w r3, r3, #4
+ 8000e62: 6713 str r3, [r2, #112] ; 0x70
+ 8000e64: 4b62 ldr r3, [pc, #392] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
8000e66: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000e68: 4a72 ldr r2, [pc, #456] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e68: 4a61 ldr r2, [pc, #388] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
8000e6a: f043 0301 orr.w r3, r3, #1
8000e6e: 6713 str r3, [r2, #112] ; 0x70
- 8000e70: e02d b.n 8000ece <HAL_RCC_OscConfig+0x376>
- 8000e72: 687b ldr r3, [r7, #4]
- 8000e74: 689b ldr r3, [r3, #8]
- 8000e76: 2b00 cmp r3, #0
- 8000e78: d10c bne.n 8000e94 <HAL_RCC_OscConfig+0x33c>
- 8000e7a: 4b6e ldr r3, [pc, #440] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e7c: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000e7e: 4a6d ldr r2, [pc, #436] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e80: f023 0301 bic.w r3, r3, #1
- 8000e84: 6713 str r3, [r2, #112] ; 0x70
- 8000e86: 4b6b ldr r3, [pc, #428] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e88: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000e8a: 4a6a ldr r2, [pc, #424] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e8c: f023 0304 bic.w r3, r3, #4
- 8000e90: 6713 str r3, [r2, #112] ; 0x70
- 8000e92: e01c b.n 8000ece <HAL_RCC_OscConfig+0x376>
- 8000e94: 687b ldr r3, [r7, #4]
- 8000e96: 689b ldr r3, [r3, #8]
- 8000e98: 2b05 cmp r3, #5
- 8000e9a: d10c bne.n 8000eb6 <HAL_RCC_OscConfig+0x35e>
- 8000e9c: 4b65 ldr r3, [pc, #404] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000e9e: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000ea0: 4a64 ldr r2, [pc, #400] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000ea2: f043 0304 orr.w r3, r3, #4
- 8000ea6: 6713 str r3, [r2, #112] ; 0x70
- 8000ea8: 4b62 ldr r3, [pc, #392] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000eaa: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000eac: 4a61 ldr r2, [pc, #388] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000eae: f043 0301 orr.w r3, r3, #1
- 8000eb2: 6713 str r3, [r2, #112] ; 0x70
- 8000eb4: e00b b.n 8000ece <HAL_RCC_OscConfig+0x376>
- 8000eb6: 4b5f ldr r3, [pc, #380] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000eb8: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000eba: 4a5e ldr r2, [pc, #376] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000ebc: f023 0301 bic.w r3, r3, #1
- 8000ec0: 6713 str r3, [r2, #112] ; 0x70
- 8000ec2: 4b5c ldr r3, [pc, #368] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000ec4: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000ec6: 4a5b ldr r2, [pc, #364] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000ec8: f023 0304 bic.w r3, r3, #4
- 8000ecc: 6713 str r3, [r2, #112] ; 0x70
+ 8000e70: e00b b.n 8000e8a <HAL_RCC_OscConfig+0x376>
+ 8000e72: 4b5f ldr r3, [pc, #380] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e74: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e76: 4a5e ldr r2, [pc, #376] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e78: f023 0301 bic.w r3, r3, #1
+ 8000e7c: 6713 str r3, [r2, #112] ; 0x70
+ 8000e7e: 4b5c ldr r3, [pc, #368] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e80: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000e82: 4a5b ldr r2, [pc, #364] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000e84: f023 0304 bic.w r3, r3, #4
+ 8000e88: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 8000ece: 687b ldr r3, [r7, #4]
- 8000ed0: 689b ldr r3, [r3, #8]
- 8000ed2: 2b00 cmp r3, #0
- 8000ed4: d015 beq.n 8000f02 <HAL_RCC_OscConfig+0x3aa>
+ 8000e8a: 687b ldr r3, [r7, #4]
+ 8000e8c: 689b ldr r3, [r3, #8]
+ 8000e8e: 2b00 cmp r3, #0
+ 8000e90: d015 beq.n 8000ebe <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000ed6: f7ff fb81 bl 80005dc <HAL_GetTick>
- 8000eda: 6138 str r0, [r7, #16]
+ 8000e92: f7ff fba3 bl 80005dc <HAL_GetTick>
+ 8000e96: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8000edc: e00a b.n 8000ef4 <HAL_RCC_OscConfig+0x39c>
+ 8000e98: e00a b.n 8000eb0 <HAL_RCC_OscConfig+0x39c>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8000ede: f7ff fb7d bl 80005dc <HAL_GetTick>
- 8000ee2: 4602 mov r2, r0
- 8000ee4: 693b ldr r3, [r7, #16]
- 8000ee6: 1ad3 subs r3, r2, r3
- 8000ee8: f241 3288 movw r2, #5000 ; 0x1388
- 8000eec: 4293 cmp r3, r2
- 8000eee: d901 bls.n 8000ef4 <HAL_RCC_OscConfig+0x39c>
+ 8000e9a: f7ff fb9f bl 80005dc <HAL_GetTick>
+ 8000e9e: 4602 mov r2, r0
+ 8000ea0: 693b ldr r3, [r7, #16]
+ 8000ea2: 1ad3 subs r3, r2, r3
+ 8000ea4: f241 3288 movw r2, #5000 ; 0x1388
+ 8000ea8: 4293 cmp r3, r2
+ 8000eaa: d901 bls.n 8000eb0 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
- 8000ef0: 2303 movs r3, #3
- 8000ef2: e09b b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000eac: 2303 movs r3, #3
+ 8000eae: e09b b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8000ef4: 4b4f ldr r3, [pc, #316] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000ef6: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000ef8: f003 0302 and.w r3, r3, #2
- 8000efc: 2b00 cmp r3, #0
- 8000efe: d0ee beq.n 8000ede <HAL_RCC_OscConfig+0x386>
- 8000f00: e014 b.n 8000f2c <HAL_RCC_OscConfig+0x3d4>
+ 8000eb0: 4b4f ldr r3, [pc, #316] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000eb2: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000eb4: f003 0302 and.w r3, r3, #2
+ 8000eb8: 2b00 cmp r3, #0
+ 8000eba: d0ee beq.n 8000e9a <HAL_RCC_OscConfig+0x386>
+ 8000ebc: e014 b.n 8000ee8 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000f02: f7ff fb6b bl 80005dc <HAL_GetTick>
- 8000f06: 6138 str r0, [r7, #16]
+ 8000ebe: f7ff fb8d bl 80005dc <HAL_GetTick>
+ 8000ec2: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8000f08: e00a b.n 8000f20 <HAL_RCC_OscConfig+0x3c8>
+ 8000ec4: e00a b.n 8000edc <HAL_RCC_OscConfig+0x3c8>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8000f0a: f7ff fb67 bl 80005dc <HAL_GetTick>
- 8000f0e: 4602 mov r2, r0
- 8000f10: 693b ldr r3, [r7, #16]
- 8000f12: 1ad3 subs r3, r2, r3
- 8000f14: f241 3288 movw r2, #5000 ; 0x1388
- 8000f18: 4293 cmp r3, r2
- 8000f1a: d901 bls.n 8000f20 <HAL_RCC_OscConfig+0x3c8>
+ 8000ec6: f7ff fb89 bl 80005dc <HAL_GetTick>
+ 8000eca: 4602 mov r2, r0
+ 8000ecc: 693b ldr r3, [r7, #16]
+ 8000ece: 1ad3 subs r3, r2, r3
+ 8000ed0: f241 3288 movw r2, #5000 ; 0x1388
+ 8000ed4: 4293 cmp r3, r2
+ 8000ed6: d901 bls.n 8000edc <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
- 8000f1c: 2303 movs r3, #3
- 8000f1e: e085 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000ed8: 2303 movs r3, #3
+ 8000eda: e085 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8000f20: 4b44 ldr r3, [pc, #272] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000f22: 6f1b ldr r3, [r3, #112] ; 0x70
- 8000f24: f003 0302 and.w r3, r3, #2
- 8000f28: 2b00 cmp r3, #0
- 8000f2a: d1ee bne.n 8000f0a <HAL_RCC_OscConfig+0x3b2>
+ 8000edc: 4b44 ldr r3, [pc, #272] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000ede: 6f1b ldr r3, [r3, #112] ; 0x70
+ 8000ee0: f003 0302 and.w r3, r3, #2
+ 8000ee4: 2b00 cmp r3, #0
+ 8000ee6: d1ee bne.n 8000ec6 <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
- 8000f2c: 7dfb ldrb r3, [r7, #23]
- 8000f2e: 2b01 cmp r3, #1
- 8000f30: d105 bne.n 8000f3e <HAL_RCC_OscConfig+0x3e6>
+ 8000ee8: 7dfb ldrb r3, [r7, #23]
+ 8000eea: 2b01 cmp r3, #1
+ 8000eec: d105 bne.n 8000efa <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
- 8000f32: 4b40 ldr r3, [pc, #256] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000f34: 6c1b ldr r3, [r3, #64] ; 0x40
- 8000f36: 4a3f ldr r2, [pc, #252] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000f38: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
- 8000f3c: 6413 str r3, [r2, #64] ; 0x40
+ 8000eee: 4b40 ldr r3, [pc, #256] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000ef0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8000ef2: 4a3f ldr r2, [pc, #252] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000ef4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
+ 8000ef8: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8000f3e: 687b ldr r3, [r7, #4]
- 8000f40: 699b ldr r3, [r3, #24]
- 8000f42: 2b00 cmp r3, #0
- 8000f44: d071 beq.n 800102a <HAL_RCC_OscConfig+0x4d2>
+ 8000efa: 687b ldr r3, [r7, #4]
+ 8000efc: 699b ldr r3, [r3, #24]
+ 8000efe: 2b00 cmp r3, #0
+ 8000f00: d071 beq.n 8000fe6 <HAL_RCC_OscConfig+0x4d2>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 8000f46: 4b3b ldr r3, [pc, #236] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000f48: 689b ldr r3, [r3, #8]
- 8000f4a: f003 030c and.w r3, r3, #12
- 8000f4e: 2b08 cmp r3, #8
- 8000f50: d069 beq.n 8001026 <HAL_RCC_OscConfig+0x4ce>
+ 8000f02: 4b3b ldr r3, [pc, #236] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f04: 689b ldr r3, [r3, #8]
+ 8000f06: f003 030c and.w r3, r3, #12
+ 8000f0a: 2b08 cmp r3, #8
+ 8000f0c: d069 beq.n 8000fe2 <HAL_RCC_OscConfig+0x4ce>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8000f52: 687b ldr r3, [r7, #4]
- 8000f54: 699b ldr r3, [r3, #24]
- 8000f56: 2b02 cmp r3, #2
- 8000f58: d14b bne.n 8000ff2 <HAL_RCC_OscConfig+0x49a>
+ 8000f0e: 687b ldr r3, [r7, #4]
+ 8000f10: 699b ldr r3, [r3, #24]
+ 8000f12: 2b02 cmp r3, #2
+ 8000f14: d14b bne.n 8000fae <HAL_RCC_OscConfig+0x49a>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 8000f5a: 4b36 ldr r3, [pc, #216] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000f5c: 681b ldr r3, [r3, #0]
- 8000f5e: 4a35 ldr r2, [pc, #212] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000f60: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8000f64: 6013 str r3, [r2, #0]
+ 8000f16: 4b36 ldr r3, [pc, #216] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f18: 681b ldr r3, [r3, #0]
+ 8000f1a: 4a35 ldr r2, [pc, #212] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f1c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8000f20: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000f66: f7ff fb39 bl 80005dc <HAL_GetTick>
- 8000f6a: 6138 str r0, [r7, #16]
+ 8000f22: f7ff fb5b bl 80005dc <HAL_GetTick>
+ 8000f26: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8000f6c: e008 b.n 8000f80 <HAL_RCC_OscConfig+0x428>
+ 8000f28: e008 b.n 8000f3c <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8000f6e: f7ff fb35 bl 80005dc <HAL_GetTick>
- 8000f72: 4602 mov r2, r0
- 8000f74: 693b ldr r3, [r7, #16]
- 8000f76: 1ad3 subs r3, r2, r3
- 8000f78: 2b02 cmp r3, #2
- 8000f7a: d901 bls.n 8000f80 <HAL_RCC_OscConfig+0x428>
+ 8000f2a: f7ff fb57 bl 80005dc <HAL_GetTick>
+ 8000f2e: 4602 mov r2, r0
+ 8000f30: 693b ldr r3, [r7, #16]
+ 8000f32: 1ad3 subs r3, r2, r3
+ 8000f34: 2b02 cmp r3, #2
+ 8000f36: d901 bls.n 8000f3c <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
- 8000f7c: 2303 movs r3, #3
- 8000f7e: e055 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000f38: 2303 movs r3, #3
+ 8000f3a: e055 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8000f80: 4b2c ldr r3, [pc, #176] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000f82: 681b ldr r3, [r3, #0]
- 8000f84: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8000f88: 2b00 cmp r3, #0
- 8000f8a: d1f0 bne.n 8000f6e <HAL_RCC_OscConfig+0x416>
+ 8000f3c: 4b2c ldr r3, [pc, #176] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f3e: 681b ldr r3, [r3, #0]
+ 8000f40: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8000f44: 2b00 cmp r3, #0
+ 8000f46: d1f0 bne.n 8000f2a <HAL_RCC_OscConfig+0x416>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined (RCC_PLLCFGR_PLLR)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8000f8c: 687b ldr r3, [r7, #4]
- 8000f8e: 69da ldr r2, [r3, #28]
- 8000f90: 687b ldr r3, [r7, #4]
- 8000f92: 6a1b ldr r3, [r3, #32]
- 8000f94: 431a orrs r2, r3
- 8000f96: 687b ldr r3, [r7, #4]
- 8000f98: 6a5b ldr r3, [r3, #36] ; 0x24
- 8000f9a: 019b lsls r3, r3, #6
- 8000f9c: 431a orrs r2, r3
- 8000f9e: 687b ldr r3, [r7, #4]
- 8000fa0: 6a9b ldr r3, [r3, #40] ; 0x28
- 8000fa2: 085b lsrs r3, r3, #1
- 8000fa4: 3b01 subs r3, #1
- 8000fa6: 041b lsls r3, r3, #16
- 8000fa8: 431a orrs r2, r3
- 8000faa: 687b ldr r3, [r7, #4]
- 8000fac: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000fae: 061b lsls r3, r3, #24
- 8000fb0: 431a orrs r2, r3
- 8000fb2: 687b ldr r3, [r7, #4]
- 8000fb4: 6b1b ldr r3, [r3, #48] ; 0x30
- 8000fb6: 071b lsls r3, r3, #28
- 8000fb8: 491e ldr r1, [pc, #120] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000fba: 4313 orrs r3, r2
- 8000fbc: 604b str r3, [r1, #4]
+ 8000f48: 687b ldr r3, [r7, #4]
+ 8000f4a: 69da ldr r2, [r3, #28]
+ 8000f4c: 687b ldr r3, [r7, #4]
+ 8000f4e: 6a1b ldr r3, [r3, #32]
+ 8000f50: 431a orrs r2, r3
+ 8000f52: 687b ldr r3, [r7, #4]
+ 8000f54: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8000f56: 019b lsls r3, r3, #6
+ 8000f58: 431a orrs r2, r3
+ 8000f5a: 687b ldr r3, [r7, #4]
+ 8000f5c: 6a9b ldr r3, [r3, #40] ; 0x28
+ 8000f5e: 085b lsrs r3, r3, #1
+ 8000f60: 3b01 subs r3, #1
+ 8000f62: 041b lsls r3, r3, #16
+ 8000f64: 431a orrs r2, r3
+ 8000f66: 687b ldr r3, [r7, #4]
+ 8000f68: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000f6a: 061b lsls r3, r3, #24
+ 8000f6c: 431a orrs r2, r3
+ 8000f6e: 687b ldr r3, [r7, #4]
+ 8000f70: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8000f72: 071b lsls r3, r3, #28
+ 8000f74: 491e ldr r1, [pc, #120] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f76: 4313 orrs r3, r2
+ 8000f78: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- 8000fbe: 4b1d ldr r3, [pc, #116] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000fc0: 681b ldr r3, [r3, #0]
- 8000fc2: 4a1c ldr r2, [pc, #112] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000fc4: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
- 8000fc8: 6013 str r3, [r2, #0]
+ 8000f7a: 4b1d ldr r3, [pc, #116] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f7c: 681b ldr r3, [r3, #0]
+ 8000f7e: 4a1c ldr r2, [pc, #112] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000f80: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
+ 8000f84: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000fca: f7ff fb07 bl 80005dc <HAL_GetTick>
- 8000fce: 6138 str r0, [r7, #16]
+ 8000f86: f7ff fb29 bl 80005dc <HAL_GetTick>
+ 8000f8a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8000fd0: e008 b.n 8000fe4 <HAL_RCC_OscConfig+0x48c>
+ 8000f8c: e008 b.n 8000fa0 <HAL_RCC_OscConfig+0x48c>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8000fd2: f7ff fb03 bl 80005dc <HAL_GetTick>
- 8000fd6: 4602 mov r2, r0
- 8000fd8: 693b ldr r3, [r7, #16]
- 8000fda: 1ad3 subs r3, r2, r3
- 8000fdc: 2b02 cmp r3, #2
- 8000fde: d901 bls.n 8000fe4 <HAL_RCC_OscConfig+0x48c>
+ 8000f8e: f7ff fb25 bl 80005dc <HAL_GetTick>
+ 8000f92: 4602 mov r2, r0
+ 8000f94: 693b ldr r3, [r7, #16]
+ 8000f96: 1ad3 subs r3, r2, r3
+ 8000f98: 2b02 cmp r3, #2
+ 8000f9a: d901 bls.n 8000fa0 <HAL_RCC_OscConfig+0x48c>
{
return HAL_TIMEOUT;
- 8000fe0: 2303 movs r3, #3
- 8000fe2: e023 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000f9c: 2303 movs r3, #3
+ 8000f9e: e023 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8000fe4: 4b13 ldr r3, [pc, #76] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000fe6: 681b ldr r3, [r3, #0]
- 8000fe8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8000fec: 2b00 cmp r3, #0
- 8000fee: d0f0 beq.n 8000fd2 <HAL_RCC_OscConfig+0x47a>
- 8000ff0: e01b b.n 800102a <HAL_RCC_OscConfig+0x4d2>
+ 8000fa0: 4b13 ldr r3, [pc, #76] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fa2: 681b ldr r3, [r3, #0]
+ 8000fa4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8000fa8: 2b00 cmp r3, #0
+ 8000faa: d0f0 beq.n 8000f8e <HAL_RCC_OscConfig+0x47a>
+ 8000fac: e01b b.n 8000fe6 <HAL_RCC_OscConfig+0x4d2>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 8000ff2: 4b10 ldr r3, [pc, #64] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000ff4: 681b ldr r3, [r3, #0]
- 8000ff6: 4a0f ldr r2, [pc, #60] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 8000ff8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
- 8000ffc: 6013 str r3, [r2, #0]
+ 8000fae: 4b10 ldr r3, [pc, #64] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fb0: 681b ldr r3, [r3, #0]
+ 8000fb2: 4a0f ldr r2, [pc, #60] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fb4: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
+ 8000fb8: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8000ffe: f7ff faed bl 80005dc <HAL_GetTick>
- 8001002: 6138 str r0, [r7, #16]
+ 8000fba: f7ff fb0f bl 80005dc <HAL_GetTick>
+ 8000fbe: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001004: e008 b.n 8001018 <HAL_RCC_OscConfig+0x4c0>
+ 8000fc0: e008 b.n 8000fd4 <HAL_RCC_OscConfig+0x4c0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001006: f7ff fae9 bl 80005dc <HAL_GetTick>
- 800100a: 4602 mov r2, r0
- 800100c: 693b ldr r3, [r7, #16]
- 800100e: 1ad3 subs r3, r2, r3
- 8001010: 2b02 cmp r3, #2
- 8001012: d901 bls.n 8001018 <HAL_RCC_OscConfig+0x4c0>
+ 8000fc2: f7ff fb0b bl 80005dc <HAL_GetTick>
+ 8000fc6: 4602 mov r2, r0
+ 8000fc8: 693b ldr r3, [r7, #16]
+ 8000fca: 1ad3 subs r3, r2, r3
+ 8000fcc: 2b02 cmp r3, #2
+ 8000fce: d901 bls.n 8000fd4 <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
- 8001014: 2303 movs r3, #3
- 8001016: e009 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000fd0: 2303 movs r3, #3
+ 8000fd2: e009 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001018: 4b06 ldr r3, [pc, #24] ; (8001034 <HAL_RCC_OscConfig+0x4dc>)
- 800101a: 681b ldr r3, [r3, #0]
- 800101c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8001020: 2b00 cmp r3, #0
- 8001022: d1f0 bne.n 8001006 <HAL_RCC_OscConfig+0x4ae>
- 8001024: e001 b.n 800102a <HAL_RCC_OscConfig+0x4d2>
+ 8000fd4: 4b06 ldr r3, [pc, #24] ; (8000ff0 <HAL_RCC_OscConfig+0x4dc>)
+ 8000fd6: 681b ldr r3, [r3, #0]
+ 8000fd8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 8000fdc: 2b00 cmp r3, #0
+ 8000fde: d1f0 bne.n 8000fc2 <HAL_RCC_OscConfig+0x4ae>
+ 8000fe0: e001 b.n 8000fe6 <HAL_RCC_OscConfig+0x4d2>
}
}
}
else
{
return HAL_ERROR;
- 8001026: 2301 movs r3, #1
- 8001028: e000 b.n 800102c <HAL_RCC_OscConfig+0x4d4>
+ 8000fe2: 2301 movs r3, #1
+ 8000fe4: e000 b.n 8000fe8 <HAL_RCC_OscConfig+0x4d4>
}
}
return HAL_OK;
- 800102a: 2300 movs r3, #0
+ 8000fe6: 2300 movs r3, #0
}
- 800102c: 4618 mov r0, r3
- 800102e: 3718 adds r7, #24
- 8001030: 46bd mov sp, r7
- 8001032: bd80 pop {r7, pc}
- 8001034: 40023800 .word 0x40023800
- 8001038: 40007000 .word 0x40007000
-
-0800103c <HAL_RCC_ClockConfig>:
+ 8000fe8: 4618 mov r0, r3
+ 8000fea: 3718 adds r7, #24
+ 8000fec: 46bd mov sp, r7
+ 8000fee: bd80 pop {r7, pc}
+ 8000ff0: 40023800 .word 0x40023800
+ 8000ff4: 40007000 .word 0x40007000
+
+08000ff8 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- 800103c: b580 push {r7, lr}
- 800103e: b084 sub sp, #16
- 8001040: af00 add r7, sp, #0
- 8001042: 6078 str r0, [r7, #4]
- 8001044: 6039 str r1, [r7, #0]
+ 8000ff8: b580 push {r7, lr}
+ 8000ffa: b084 sub sp, #16
+ 8000ffc: af00 add r7, sp, #0
+ 8000ffe: 6078 str r0, [r7, #4]
+ 8001000: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
- 8001046: 2300 movs r3, #0
- 8001048: 60fb str r3, [r7, #12]
+ 8001002: 2300 movs r3, #0
+ 8001004: 60fb str r3, [r7, #12]
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
- 800104a: 687b ldr r3, [r7, #4]
- 800104c: 2b00 cmp r3, #0
- 800104e: d101 bne.n 8001054 <HAL_RCC_ClockConfig+0x18>
+ 8001006: 687b ldr r3, [r7, #4]
+ 8001008: 2b00 cmp r3, #0
+ 800100a: d101 bne.n 8001010 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
- 8001050: 2301 movs r3, #1
- 8001052: e0ce b.n 80011f2 <HAL_RCC_ClockConfig+0x1b6>
+ 800100c: 2301 movs r3, #1
+ 800100e: e0ce b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8001054: 4b69 ldr r3, [pc, #420] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 8001056: 681b ldr r3, [r3, #0]
- 8001058: f003 030f and.w r3, r3, #15
- 800105c: 683a ldr r2, [r7, #0]
- 800105e: 429a cmp r2, r3
- 8001060: d910 bls.n 8001084 <HAL_RCC_ClockConfig+0x48>
+ 8001010: 4b69 ldr r3, [pc, #420] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001012: 681b ldr r3, [r3, #0]
+ 8001014: f003 030f and.w r3, r3, #15
+ 8001018: 683a ldr r2, [r7, #0]
+ 800101a: 429a cmp r2, r3
+ 800101c: d910 bls.n 8001040 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 8001062: 4b66 ldr r3, [pc, #408] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 8001064: 681b ldr r3, [r3, #0]
- 8001066: f023 020f bic.w r2, r3, #15
- 800106a: 4964 ldr r1, [pc, #400] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 800106c: 683b ldr r3, [r7, #0]
- 800106e: 4313 orrs r3, r2
- 8001070: 600b str r3, [r1, #0]
+ 800101e: 4b66 ldr r3, [pc, #408] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001020: 681b ldr r3, [r3, #0]
+ 8001022: f023 020f bic.w r2, r3, #15
+ 8001026: 4964 ldr r1, [pc, #400] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001028: 683b ldr r3, [r7, #0]
+ 800102a: 4313 orrs r3, r2
+ 800102c: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8001072: 4b62 ldr r3, [pc, #392] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 8001074: 681b ldr r3, [r3, #0]
- 8001076: f003 030f and.w r3, r3, #15
- 800107a: 683a ldr r2, [r7, #0]
- 800107c: 429a cmp r2, r3
- 800107e: d001 beq.n 8001084 <HAL_RCC_ClockConfig+0x48>
+ 800102e: 4b62 ldr r3, [pc, #392] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001030: 681b ldr r3, [r3, #0]
+ 8001032: f003 030f and.w r3, r3, #15
+ 8001036: 683a ldr r2, [r7, #0]
+ 8001038: 429a cmp r2, r3
+ 800103a: d001 beq.n 8001040 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
- 8001080: 2301 movs r3, #1
- 8001082: e0b6 b.n 80011f2 <HAL_RCC_ClockConfig+0x1b6>
+ 800103c: 2301 movs r3, #1
+ 800103e: e0b6 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8001084: 687b ldr r3, [r7, #4]
- 8001086: 681b ldr r3, [r3, #0]
- 8001088: f003 0302 and.w r3, r3, #2
- 800108c: 2b00 cmp r3, #0
- 800108e: d020 beq.n 80010d2 <HAL_RCC_ClockConfig+0x96>
+ 8001040: 687b ldr r3, [r7, #4]
+ 8001042: 681b ldr r3, [r3, #0]
+ 8001044: f003 0302 and.w r3, r3, #2
+ 8001048: 2b00 cmp r3, #0
+ 800104a: d020 beq.n 800108e <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001090: 687b ldr r3, [r7, #4]
- 8001092: 681b ldr r3, [r3, #0]
- 8001094: f003 0304 and.w r3, r3, #4
- 8001098: 2b00 cmp r3, #0
- 800109a: d005 beq.n 80010a8 <HAL_RCC_ClockConfig+0x6c>
+ 800104c: 687b ldr r3, [r7, #4]
+ 800104e: 681b ldr r3, [r3, #0]
+ 8001050: f003 0304 and.w r3, r3, #4
+ 8001054: 2b00 cmp r3, #0
+ 8001056: d005 beq.n 8001064 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 800109c: 4b58 ldr r3, [pc, #352] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 800109e: 689b ldr r3, [r3, #8]
- 80010a0: 4a57 ldr r2, [pc, #348] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80010a2: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
- 80010a6: 6093 str r3, [r2, #8]
+ 8001058: 4b58 ldr r3, [pc, #352] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800105a: 689b ldr r3, [r3, #8]
+ 800105c: 4a57 ldr r2, [pc, #348] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800105e: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
+ 8001062: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 80010a8: 687b ldr r3, [r7, #4]
- 80010aa: 681b ldr r3, [r3, #0]
- 80010ac: f003 0308 and.w r3, r3, #8
- 80010b0: 2b00 cmp r3, #0
- 80010b2: d005 beq.n 80010c0 <HAL_RCC_ClockConfig+0x84>
+ 8001064: 687b ldr r3, [r7, #4]
+ 8001066: 681b ldr r3, [r3, #0]
+ 8001068: f003 0308 and.w r3, r3, #8
+ 800106c: 2b00 cmp r3, #0
+ 800106e: d005 beq.n 800107c <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 80010b4: 4b52 ldr r3, [pc, #328] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80010b6: 689b ldr r3, [r3, #8]
- 80010b8: 4a51 ldr r2, [pc, #324] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80010ba: f443 4360 orr.w r3, r3, #57344 ; 0xe000
- 80010be: 6093 str r3, [r2, #8]
+ 8001070: 4b52 ldr r3, [pc, #328] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001072: 689b ldr r3, [r3, #8]
+ 8001074: 4a51 ldr r2, [pc, #324] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001076: f443 4360 orr.w r3, r3, #57344 ; 0xe000
+ 800107a: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 80010c0: 4b4f ldr r3, [pc, #316] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80010c2: 689b ldr r3, [r3, #8]
- 80010c4: f023 02f0 bic.w r2, r3, #240 ; 0xf0
- 80010c8: 687b ldr r3, [r7, #4]
- 80010ca: 689b ldr r3, [r3, #8]
- 80010cc: 494c ldr r1, [pc, #304] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80010ce: 4313 orrs r3, r2
- 80010d0: 608b str r3, [r1, #8]
+ 800107c: 4b4f ldr r3, [pc, #316] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800107e: 689b ldr r3, [r3, #8]
+ 8001080: f023 02f0 bic.w r2, r3, #240 ; 0xf0
+ 8001084: 687b ldr r3, [r7, #4]
+ 8001086: 689b ldr r3, [r3, #8]
+ 8001088: 494c ldr r1, [pc, #304] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800108a: 4313 orrs r3, r2
+ 800108c: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 80010d2: 687b ldr r3, [r7, #4]
- 80010d4: 681b ldr r3, [r3, #0]
- 80010d6: f003 0301 and.w r3, r3, #1
- 80010da: 2b00 cmp r3, #0
- 80010dc: d040 beq.n 8001160 <HAL_RCC_ClockConfig+0x124>
+ 800108e: 687b ldr r3, [r7, #4]
+ 8001090: 681b ldr r3, [r3, #0]
+ 8001092: f003 0301 and.w r3, r3, #1
+ 8001096: 2b00 cmp r3, #0
+ 8001098: d040 beq.n 800111c <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 80010de: 687b ldr r3, [r7, #4]
- 80010e0: 685b ldr r3, [r3, #4]
- 80010e2: 2b01 cmp r3, #1
- 80010e4: d107 bne.n 80010f6 <HAL_RCC_ClockConfig+0xba>
+ 800109a: 687b ldr r3, [r7, #4]
+ 800109c: 685b ldr r3, [r3, #4]
+ 800109e: 2b01 cmp r3, #1
+ 80010a0: d107 bne.n 80010b2 <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 80010e6: 4b46 ldr r3, [pc, #280] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80010e8: 681b ldr r3, [r3, #0]
- 80010ea: f403 3300 and.w r3, r3, #131072 ; 0x20000
- 80010ee: 2b00 cmp r3, #0
- 80010f0: d115 bne.n 800111e <HAL_RCC_ClockConfig+0xe2>
+ 80010a2: 4b46 ldr r3, [pc, #280] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010a4: 681b ldr r3, [r3, #0]
+ 80010a6: f403 3300 and.w r3, r3, #131072 ; 0x20000
+ 80010aa: 2b00 cmp r3, #0
+ 80010ac: d115 bne.n 80010da <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 80010f2: 2301 movs r3, #1
- 80010f4: e07d b.n 80011f2 <HAL_RCC_ClockConfig+0x1b6>
+ 80010ae: 2301 movs r3, #1
+ 80010b0: e07d b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 80010f6: 687b ldr r3, [r7, #4]
- 80010f8: 685b ldr r3, [r3, #4]
- 80010fa: 2b02 cmp r3, #2
- 80010fc: d107 bne.n 800110e <HAL_RCC_ClockConfig+0xd2>
+ 80010b2: 687b ldr r3, [r7, #4]
+ 80010b4: 685b ldr r3, [r3, #4]
+ 80010b6: 2b02 cmp r3, #2
+ 80010b8: d107 bne.n 80010ca <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 80010fe: 4b40 ldr r3, [pc, #256] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 8001100: 681b ldr r3, [r3, #0]
- 8001102: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
- 8001106: 2b00 cmp r3, #0
- 8001108: d109 bne.n 800111e <HAL_RCC_ClockConfig+0xe2>
+ 80010ba: 4b40 ldr r3, [pc, #256] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010bc: 681b ldr r3, [r3, #0]
+ 80010be: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
+ 80010c2: 2b00 cmp r3, #0
+ 80010c4: d109 bne.n 80010da <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 800110a: 2301 movs r3, #1
- 800110c: e071 b.n 80011f2 <HAL_RCC_ClockConfig+0x1b6>
+ 80010c6: 2301 movs r3, #1
+ 80010c8: e071 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 800110e: 4b3c ldr r3, [pc, #240] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 8001110: 681b ldr r3, [r3, #0]
- 8001112: f003 0302 and.w r3, r3, #2
- 8001116: 2b00 cmp r3, #0
- 8001118: d101 bne.n 800111e <HAL_RCC_ClockConfig+0xe2>
+ 80010ca: 4b3c ldr r3, [pc, #240] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010cc: 681b ldr r3, [r3, #0]
+ 80010ce: f003 0302 and.w r3, r3, #2
+ 80010d2: 2b00 cmp r3, #0
+ 80010d4: d101 bne.n 80010da <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
- 800111a: 2301 movs r3, #1
- 800111c: e069 b.n 80011f2 <HAL_RCC_ClockConfig+0x1b6>
+ 80010d6: 2301 movs r3, #1
+ 80010d8: e069 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 800111e: 4b38 ldr r3, [pc, #224] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 8001120: 689b ldr r3, [r3, #8]
- 8001122: f023 0203 bic.w r2, r3, #3
- 8001126: 687b ldr r3, [r7, #4]
- 8001128: 685b ldr r3, [r3, #4]
- 800112a: 4935 ldr r1, [pc, #212] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 800112c: 4313 orrs r3, r2
- 800112e: 608b str r3, [r1, #8]
+ 80010da: 4b38 ldr r3, [pc, #224] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010dc: 689b ldr r3, [r3, #8]
+ 80010de: f023 0203 bic.w r2, r3, #3
+ 80010e2: 687b ldr r3, [r7, #4]
+ 80010e4: 685b ldr r3, [r3, #4]
+ 80010e6: 4935 ldr r1, [pc, #212] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 80010e8: 4313 orrs r3, r2
+ 80010ea: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
- 8001130: f7ff fa54 bl 80005dc <HAL_GetTick>
- 8001134: 60f8 str r0, [r7, #12]
+ 80010ec: f7ff fa76 bl 80005dc <HAL_GetTick>
+ 80010f0: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8001136: e00a b.n 800114e <HAL_RCC_ClockConfig+0x112>
+ 80010f2: e00a b.n 800110a <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8001138: f7ff fa50 bl 80005dc <HAL_GetTick>
- 800113c: 4602 mov r2, r0
- 800113e: 68fb ldr r3, [r7, #12]
- 8001140: 1ad3 subs r3, r2, r3
- 8001142: f241 3288 movw r2, #5000 ; 0x1388
- 8001146: 4293 cmp r3, r2
- 8001148: d901 bls.n 800114e <HAL_RCC_ClockConfig+0x112>
+ 80010f4: f7ff fa72 bl 80005dc <HAL_GetTick>
+ 80010f8: 4602 mov r2, r0
+ 80010fa: 68fb ldr r3, [r7, #12]
+ 80010fc: 1ad3 subs r3, r2, r3
+ 80010fe: f241 3288 movw r2, #5000 ; 0x1388
+ 8001102: 4293 cmp r3, r2
+ 8001104: d901 bls.n 800110a <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
- 800114a: 2303 movs r3, #3
- 800114c: e051 b.n 80011f2 <HAL_RCC_ClockConfig+0x1b6>
+ 8001106: 2303 movs r3, #3
+ 8001108: e051 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 800114e: 4b2c ldr r3, [pc, #176] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 8001150: 689b ldr r3, [r3, #8]
- 8001152: f003 020c and.w r2, r3, #12
- 8001156: 687b ldr r3, [r7, #4]
- 8001158: 685b ldr r3, [r3, #4]
- 800115a: 009b lsls r3, r3, #2
- 800115c: 429a cmp r2, r3
- 800115e: d1eb bne.n 8001138 <HAL_RCC_ClockConfig+0xfc>
+ 800110a: 4b2c ldr r3, [pc, #176] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800110c: 689b ldr r3, [r3, #8]
+ 800110e: f003 020c and.w r2, r3, #12
+ 8001112: 687b ldr r3, [r7, #4]
+ 8001114: 685b ldr r3, [r3, #4]
+ 8001116: 009b lsls r3, r3, #2
+ 8001118: 429a cmp r2, r3
+ 800111a: d1eb bne.n 80010f4 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8001160: 4b26 ldr r3, [pc, #152] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 8001162: 681b ldr r3, [r3, #0]
- 8001164: f003 030f and.w r3, r3, #15
- 8001168: 683a ldr r2, [r7, #0]
- 800116a: 429a cmp r2, r3
- 800116c: d210 bcs.n 8001190 <HAL_RCC_ClockConfig+0x154>
+ 800111c: 4b26 ldr r3, [pc, #152] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 800111e: 681b ldr r3, [r3, #0]
+ 8001120: f003 030f and.w r3, r3, #15
+ 8001124: 683a ldr r2, [r7, #0]
+ 8001126: 429a cmp r2, r3
+ 8001128: d210 bcs.n 800114c <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 800116e: 4b23 ldr r3, [pc, #140] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 8001170: 681b ldr r3, [r3, #0]
- 8001172: f023 020f bic.w r2, r3, #15
- 8001176: 4921 ldr r1, [pc, #132] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 8001178: 683b ldr r3, [r7, #0]
- 800117a: 4313 orrs r3, r2
- 800117c: 600b str r3, [r1, #0]
+ 800112a: 4b23 ldr r3, [pc, #140] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 800112c: 681b ldr r3, [r3, #0]
+ 800112e: f023 020f bic.w r2, r3, #15
+ 8001132: 4921 ldr r1, [pc, #132] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 8001134: 683b ldr r3, [r7, #0]
+ 8001136: 4313 orrs r3, r2
+ 8001138: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 800117e: 4b1f ldr r3, [pc, #124] ; (80011fc <HAL_RCC_ClockConfig+0x1c0>)
- 8001180: 681b ldr r3, [r3, #0]
- 8001182: f003 030f and.w r3, r3, #15
- 8001186: 683a ldr r2, [r7, #0]
- 8001188: 429a cmp r2, r3
- 800118a: d001 beq.n 8001190 <HAL_RCC_ClockConfig+0x154>
+ 800113a: 4b1f ldr r3, [pc, #124] ; (80011b8 <HAL_RCC_ClockConfig+0x1c0>)
+ 800113c: 681b ldr r3, [r3, #0]
+ 800113e: f003 030f and.w r3, r3, #15
+ 8001142: 683a ldr r2, [r7, #0]
+ 8001144: 429a cmp r2, r3
+ 8001146: d001 beq.n 800114c <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
- 800118c: 2301 movs r3, #1
- 800118e: e030 b.n 80011f2 <HAL_RCC_ClockConfig+0x1b6>
+ 8001148: 2301 movs r3, #1
+ 800114a: e030 b.n 80011ae <HAL_RCC_ClockConfig+0x1b6>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001190: 687b ldr r3, [r7, #4]
- 8001192: 681b ldr r3, [r3, #0]
- 8001194: f003 0304 and.w r3, r3, #4
- 8001198: 2b00 cmp r3, #0
- 800119a: d008 beq.n 80011ae <HAL_RCC_ClockConfig+0x172>
+ 800114c: 687b ldr r3, [r7, #4]
+ 800114e: 681b ldr r3, [r3, #0]
+ 8001150: f003 0304 and.w r3, r3, #4
+ 8001154: 2b00 cmp r3, #0
+ 8001156: d008 beq.n 800116a <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 800119c: 4b18 ldr r3, [pc, #96] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 800119e: 689b ldr r3, [r3, #8]
- 80011a0: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
- 80011a4: 687b ldr r3, [r7, #4]
- 80011a6: 68db ldr r3, [r3, #12]
- 80011a8: 4915 ldr r1, [pc, #84] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80011aa: 4313 orrs r3, r2
- 80011ac: 608b str r3, [r1, #8]
+ 8001158: 4b18 ldr r3, [pc, #96] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 800115a: 689b ldr r3, [r3, #8]
+ 800115c: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
+ 8001160: 687b ldr r3, [r7, #4]
+ 8001162: 68db ldr r3, [r3, #12]
+ 8001164: 4915 ldr r1, [pc, #84] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001166: 4313 orrs r3, r2
+ 8001168: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 80011ae: 687b ldr r3, [r7, #4]
- 80011b0: 681b ldr r3, [r3, #0]
- 80011b2: f003 0308 and.w r3, r3, #8
- 80011b6: 2b00 cmp r3, #0
- 80011b8: d009 beq.n 80011ce <HAL_RCC_ClockConfig+0x192>
+ 800116a: 687b ldr r3, [r7, #4]
+ 800116c: 681b ldr r3, [r3, #0]
+ 800116e: f003 0308 and.w r3, r3, #8
+ 8001172: 2b00 cmp r3, #0
+ 8001174: d009 beq.n 800118a <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 80011ba: 4b11 ldr r3, [pc, #68] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80011bc: 689b ldr r3, [r3, #8]
- 80011be: f423 4260 bic.w r2, r3, #57344 ; 0xe000
- 80011c2: 687b ldr r3, [r7, #4]
- 80011c4: 691b ldr r3, [r3, #16]
- 80011c6: 00db lsls r3, r3, #3
- 80011c8: 490d ldr r1, [pc, #52] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80011ca: 4313 orrs r3, r2
- 80011cc: 608b str r3, [r1, #8]
+ 8001176: 4b11 ldr r3, [pc, #68] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001178: 689b ldr r3, [r3, #8]
+ 800117a: f423 4260 bic.w r2, r3, #57344 ; 0xe000
+ 800117e: 687b ldr r3, [r7, #4]
+ 8001180: 691b ldr r3, [r3, #16]
+ 8001182: 00db lsls r3, r3, #3
+ 8001184: 490d ldr r1, [pc, #52] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001186: 4313 orrs r3, r2
+ 8001188: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 80011ce: f000 f81d bl 800120c <HAL_RCC_GetSysClockFreq>
- 80011d2: 4601 mov r1, r0
- 80011d4: 4b0a ldr r3, [pc, #40] ; (8001200 <HAL_RCC_ClockConfig+0x1c4>)
- 80011d6: 689b ldr r3, [r3, #8]
- 80011d8: 091b lsrs r3, r3, #4
- 80011da: f003 030f and.w r3, r3, #15
- 80011de: 4a09 ldr r2, [pc, #36] ; (8001204 <HAL_RCC_ClockConfig+0x1c8>)
- 80011e0: 5cd3 ldrb r3, [r2, r3]
- 80011e2: fa21 f303 lsr.w r3, r1, r3
- 80011e6: 4a08 ldr r2, [pc, #32] ; (8001208 <HAL_RCC_ClockConfig+0x1cc>)
- 80011e8: 6013 str r3, [r2, #0]
+ 800118a: f000 f81d bl 80011c8 <HAL_RCC_GetSysClockFreq>
+ 800118e: 4601 mov r1, r0
+ 8001190: 4b0a ldr r3, [pc, #40] ; (80011bc <HAL_RCC_ClockConfig+0x1c4>)
+ 8001192: 689b ldr r3, [r3, #8]
+ 8001194: 091b lsrs r3, r3, #4
+ 8001196: f003 030f and.w r3, r3, #15
+ 800119a: 4a09 ldr r2, [pc, #36] ; (80011c0 <HAL_RCC_ClockConfig+0x1c8>)
+ 800119c: 5cd3 ldrb r3, [r2, r3]
+ 800119e: fa21 f303 lsr.w r3, r1, r3
+ 80011a2: 4a08 ldr r2, [pc, #32] ; (80011c4 <HAL_RCC_ClockConfig+0x1cc>)
+ 80011a4: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
- 80011ea: 2000 movs r0, #0
- 80011ec: f7ff f9b2 bl 8000554 <HAL_InitTick>
+ 80011a6: 2000 movs r0, #0
+ 80011a8: f7ff f9d4 bl 8000554 <HAL_InitTick>
return HAL_OK;
- 80011f0: 2300 movs r3, #0
+ 80011ac: 2300 movs r3, #0
}
- 80011f2: 4618 mov r0, r3
- 80011f4: 3710 adds r7, #16
- 80011f6: 46bd mov sp, r7
- 80011f8: bd80 pop {r7, pc}
- 80011fa: bf00 nop
- 80011fc: 40023c00 .word 0x40023c00
- 8001200: 40023800 .word 0x40023800
- 8001204: 0800224c .word 0x0800224c
- 8001208: 20000008 .word 0x20000008
-
-0800120c <HAL_RCC_GetSysClockFreq>:
+ 80011ae: 4618 mov r0, r3
+ 80011b0: 3710 adds r7, #16
+ 80011b2: 46bd mov sp, r7
+ 80011b4: bd80 pop {r7, pc}
+ 80011b6: bf00 nop
+ 80011b8: 40023c00 .word 0x40023c00
+ 80011bc: 40023800 .word 0x40023800
+ 80011c0: 080022bc .word 0x080022bc
+ 80011c4: 20000008 .word 0x20000008
+
+080011c8 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
- 800120c: b5f0 push {r4, r5, r6, r7, lr}
- 800120e: b085 sub sp, #20
- 8001210: af00 add r7, sp, #0
+ 80011c8: b5f0 push {r4, r5, r6, r7, lr}
+ 80011ca: b085 sub sp, #20
+ 80011cc: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
- 8001212: 2300 movs r3, #0
- 8001214: 607b str r3, [r7, #4]
- 8001216: 2300 movs r3, #0
- 8001218: 60fb str r3, [r7, #12]
- 800121a: 2300 movs r3, #0
- 800121c: 603b str r3, [r7, #0]
+ 80011ce: 2300 movs r3, #0
+ 80011d0: 607b str r3, [r7, #4]
+ 80011d2: 2300 movs r3, #0
+ 80011d4: 60fb str r3, [r7, #12]
+ 80011d6: 2300 movs r3, #0
+ 80011d8: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0;
- 800121e: 2300 movs r3, #0
- 8001220: 60bb str r3, [r7, #8]
+ 80011da: 2300 movs r3, #0
+ 80011dc: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
- 8001222: 4b50 ldr r3, [pc, #320] ; (8001364 <HAL_RCC_GetSysClockFreq+0x158>)
- 8001224: 689b ldr r3, [r3, #8]
- 8001226: f003 030c and.w r3, r3, #12
- 800122a: 2b04 cmp r3, #4
- 800122c: d007 beq.n 800123e <HAL_RCC_GetSysClockFreq+0x32>
- 800122e: 2b08 cmp r3, #8
- 8001230: d008 beq.n 8001244 <HAL_RCC_GetSysClockFreq+0x38>
- 8001232: 2b00 cmp r3, #0
- 8001234: f040 808d bne.w 8001352 <HAL_RCC_GetSysClockFreq+0x146>
+ 80011de: 4b50 ldr r3, [pc, #320] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80011e0: 689b ldr r3, [r3, #8]
+ 80011e2: f003 030c and.w r3, r3, #12
+ 80011e6: 2b04 cmp r3, #4
+ 80011e8: d007 beq.n 80011fa <HAL_RCC_GetSysClockFreq+0x32>
+ 80011ea: 2b08 cmp r3, #8
+ 80011ec: d008 beq.n 8001200 <HAL_RCC_GetSysClockFreq+0x38>
+ 80011ee: 2b00 cmp r3, #0
+ 80011f0: f040 808d bne.w 800130e <HAL_RCC_GetSysClockFreq+0x146>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
- 8001238: 4b4b ldr r3, [pc, #300] ; (8001368 <HAL_RCC_GetSysClockFreq+0x15c>)
- 800123a: 60bb str r3, [r7, #8]
+ 80011f4: 4b4b ldr r3, [pc, #300] ; (8001324 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 80011f6: 60bb str r3, [r7, #8]
break;
- 800123c: e08c b.n 8001358 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80011f8: e08c b.n 8001314 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
- 800123e: 4b4b ldr r3, [pc, #300] ; (800136c <HAL_RCC_GetSysClockFreq+0x160>)
- 8001240: 60bb str r3, [r7, #8]
+ 80011fa: 4b4b ldr r3, [pc, #300] ; (8001328 <HAL_RCC_GetSysClockFreq+0x160>)
+ 80011fc: 60bb str r3, [r7, #8]
break;
- 8001242: e089 b.n 8001358 <HAL_RCC_GetSysClockFreq+0x14c>
+ 80011fe: e089 b.n 8001314 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 8001244: 4b47 ldr r3, [pc, #284] ; (8001364 <HAL_RCC_GetSysClockFreq+0x158>)
- 8001246: 685b ldr r3, [r3, #4]
- 8001248: f003 033f and.w r3, r3, #63 ; 0x3f
- 800124c: 607b str r3, [r7, #4]
+ 8001200: 4b47 ldr r3, [pc, #284] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001202: 685b ldr r3, [r3, #4]
+ 8001204: f003 033f and.w r3, r3, #63 ; 0x3f
+ 8001208: 607b str r3, [r7, #4]
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
- 800124e: 4b45 ldr r3, [pc, #276] ; (8001364 <HAL_RCC_GetSysClockFreq+0x158>)
- 8001250: 685b ldr r3, [r3, #4]
- 8001252: f403 0380 and.w r3, r3, #4194304 ; 0x400000
- 8001256: 2b00 cmp r3, #0
- 8001258: d023 beq.n 80012a2 <HAL_RCC_GetSysClockFreq+0x96>
+ 800120a: 4b45 ldr r3, [pc, #276] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 800120c: 685b ldr r3, [r3, #4]
+ 800120e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
+ 8001212: 2b00 cmp r3, #0
+ 8001214: d023 beq.n 800125e <HAL_RCC_GetSysClockFreq+0x96>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 800125a: 4b42 ldr r3, [pc, #264] ; (8001364 <HAL_RCC_GetSysClockFreq+0x158>)
- 800125c: 685b ldr r3, [r3, #4]
- 800125e: 099b lsrs r3, r3, #6
- 8001260: f04f 0400 mov.w r4, #0
- 8001264: f240 11ff movw r1, #511 ; 0x1ff
- 8001268: f04f 0200 mov.w r2, #0
- 800126c: ea03 0501 and.w r5, r3, r1
- 8001270: ea04 0602 and.w r6, r4, r2
- 8001274: 4a3d ldr r2, [pc, #244] ; (800136c <HAL_RCC_GetSysClockFreq+0x160>)
- 8001276: fb02 f106 mul.w r1, r2, r6
- 800127a: 2200 movs r2, #0
- 800127c: fb02 f205 mul.w r2, r2, r5
- 8001280: 440a add r2, r1
- 8001282: 493a ldr r1, [pc, #232] ; (800136c <HAL_RCC_GetSysClockFreq+0x160>)
- 8001284: fba5 0101 umull r0, r1, r5, r1
- 8001288: 1853 adds r3, r2, r1
- 800128a: 4619 mov r1, r3
- 800128c: 687b ldr r3, [r7, #4]
- 800128e: f04f 0400 mov.w r4, #0
- 8001292: 461a mov r2, r3
- 8001294: 4623 mov r3, r4
- 8001296: f7fe ffcf bl 8000238 <__aeabi_uldivmod>
- 800129a: 4603 mov r3, r0
- 800129c: 460c mov r4, r1
- 800129e: 60fb str r3, [r7, #12]
- 80012a0: e049 b.n 8001336 <HAL_RCC_GetSysClockFreq+0x12a>
+ 8001216: 4b42 ldr r3, [pc, #264] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001218: 685b ldr r3, [r3, #4]
+ 800121a: 099b lsrs r3, r3, #6
+ 800121c: f04f 0400 mov.w r4, #0
+ 8001220: f240 11ff movw r1, #511 ; 0x1ff
+ 8001224: f04f 0200 mov.w r2, #0
+ 8001228: ea03 0501 and.w r5, r3, r1
+ 800122c: ea04 0602 and.w r6, r4, r2
+ 8001230: 4a3d ldr r2, [pc, #244] ; (8001328 <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001232: fb02 f106 mul.w r1, r2, r6
+ 8001236: 2200 movs r2, #0
+ 8001238: fb02 f205 mul.w r2, r2, r5
+ 800123c: 440a add r2, r1
+ 800123e: 493a ldr r1, [pc, #232] ; (8001328 <HAL_RCC_GetSysClockFreq+0x160>)
+ 8001240: fba5 0101 umull r0, r1, r5, r1
+ 8001244: 1853 adds r3, r2, r1
+ 8001246: 4619 mov r1, r3
+ 8001248: 687b ldr r3, [r7, #4]
+ 800124a: f04f 0400 mov.w r4, #0
+ 800124e: 461a mov r2, r3
+ 8001250: 4623 mov r3, r4
+ 8001252: f7fe fff1 bl 8000238 <__aeabi_uldivmod>
+ 8001256: 4603 mov r3, r0
+ 8001258: 460c mov r4, r1
+ 800125a: 60fb str r3, [r7, #12]
+ 800125c: e049 b.n 80012f2 <HAL_RCC_GetSysClockFreq+0x12a>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 80012a2: 4b30 ldr r3, [pc, #192] ; (8001364 <HAL_RCC_GetSysClockFreq+0x158>)
- 80012a4: 685b ldr r3, [r3, #4]
- 80012a6: 099b lsrs r3, r3, #6
- 80012a8: f04f 0400 mov.w r4, #0
- 80012ac: f240 11ff movw r1, #511 ; 0x1ff
+ 800125e: 4b30 ldr r3, [pc, #192] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 8001260: 685b ldr r3, [r3, #4]
+ 8001262: 099b lsrs r3, r3, #6
+ 8001264: f04f 0400 mov.w r4, #0
+ 8001268: f240 11ff movw r1, #511 ; 0x1ff
+ 800126c: f04f 0200 mov.w r2, #0
+ 8001270: ea03 0501 and.w r5, r3, r1
+ 8001274: ea04 0602 and.w r6, r4, r2
+ 8001278: 4629 mov r1, r5
+ 800127a: 4632 mov r2, r6
+ 800127c: f04f 0300 mov.w r3, #0
+ 8001280: f04f 0400 mov.w r4, #0
+ 8001284: 0154 lsls r4, r2, #5
+ 8001286: ea44 64d1 orr.w r4, r4, r1, lsr #27
+ 800128a: 014b lsls r3, r1, #5
+ 800128c: 4619 mov r1, r3
+ 800128e: 4622 mov r2, r4
+ 8001290: 1b49 subs r1, r1, r5
+ 8001292: eb62 0206 sbc.w r2, r2, r6
+ 8001296: f04f 0300 mov.w r3, #0
+ 800129a: f04f 0400 mov.w r4, #0
+ 800129e: 0194 lsls r4, r2, #6
+ 80012a0: ea44 6491 orr.w r4, r4, r1, lsr #26
+ 80012a4: 018b lsls r3, r1, #6
+ 80012a6: 1a5b subs r3, r3, r1
+ 80012a8: eb64 0402 sbc.w r4, r4, r2
+ 80012ac: f04f 0100 mov.w r1, #0
80012b0: f04f 0200 mov.w r2, #0
- 80012b4: ea03 0501 and.w r5, r3, r1
- 80012b8: ea04 0602 and.w r6, r4, r2
- 80012bc: 4629 mov r1, r5
- 80012be: 4632 mov r2, r6
- 80012c0: f04f 0300 mov.w r3, #0
- 80012c4: f04f 0400 mov.w r4, #0
- 80012c8: 0154 lsls r4, r2, #5
- 80012ca: ea44 64d1 orr.w r4, r4, r1, lsr #27
- 80012ce: 014b lsls r3, r1, #5
- 80012d0: 4619 mov r1, r3
- 80012d2: 4622 mov r2, r4
- 80012d4: 1b49 subs r1, r1, r5
- 80012d6: eb62 0206 sbc.w r2, r2, r6
- 80012da: f04f 0300 mov.w r3, #0
- 80012de: f04f 0400 mov.w r4, #0
- 80012e2: 0194 lsls r4, r2, #6
- 80012e4: ea44 6491 orr.w r4, r4, r1, lsr #26
- 80012e8: 018b lsls r3, r1, #6
- 80012ea: 1a5b subs r3, r3, r1
- 80012ec: eb64 0402 sbc.w r4, r4, r2
- 80012f0: f04f 0100 mov.w r1, #0
- 80012f4: f04f 0200 mov.w r2, #0
- 80012f8: 00e2 lsls r2, r4, #3
- 80012fa: ea42 7253 orr.w r2, r2, r3, lsr #29
- 80012fe: 00d9 lsls r1, r3, #3
- 8001300: 460b mov r3, r1
- 8001302: 4614 mov r4, r2
- 8001304: 195b adds r3, r3, r5
- 8001306: eb44 0406 adc.w r4, r4, r6
- 800130a: f04f 0100 mov.w r1, #0
- 800130e: f04f 0200 mov.w r2, #0
- 8001312: 02a2 lsls r2, r4, #10
- 8001314: ea42 5293 orr.w r2, r2, r3, lsr #22
- 8001318: 0299 lsls r1, r3, #10
- 800131a: 460b mov r3, r1
- 800131c: 4614 mov r4, r2
- 800131e: 4618 mov r0, r3
- 8001320: 4621 mov r1, r4
- 8001322: 687b ldr r3, [r7, #4]
- 8001324: f04f 0400 mov.w r4, #0
- 8001328: 461a mov r2, r3
- 800132a: 4623 mov r3, r4
- 800132c: f7fe ff84 bl 8000238 <__aeabi_uldivmod>
- 8001330: 4603 mov r3, r0
- 8001332: 460c mov r4, r1
- 8001334: 60fb str r3, [r7, #12]
+ 80012b4: 00e2 lsls r2, r4, #3
+ 80012b6: ea42 7253 orr.w r2, r2, r3, lsr #29
+ 80012ba: 00d9 lsls r1, r3, #3
+ 80012bc: 460b mov r3, r1
+ 80012be: 4614 mov r4, r2
+ 80012c0: 195b adds r3, r3, r5
+ 80012c2: eb44 0406 adc.w r4, r4, r6
+ 80012c6: f04f 0100 mov.w r1, #0
+ 80012ca: f04f 0200 mov.w r2, #0
+ 80012ce: 02a2 lsls r2, r4, #10
+ 80012d0: ea42 5293 orr.w r2, r2, r3, lsr #22
+ 80012d4: 0299 lsls r1, r3, #10
+ 80012d6: 460b mov r3, r1
+ 80012d8: 4614 mov r4, r2
+ 80012da: 4618 mov r0, r3
+ 80012dc: 4621 mov r1, r4
+ 80012de: 687b ldr r3, [r7, #4]
+ 80012e0: f04f 0400 mov.w r4, #0
+ 80012e4: 461a mov r2, r3
+ 80012e6: 4623 mov r3, r4
+ 80012e8: f7fe ffa6 bl 8000238 <__aeabi_uldivmod>
+ 80012ec: 4603 mov r3, r0
+ 80012ee: 460c mov r4, r1
+ 80012f0: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
- 8001336: 4b0b ldr r3, [pc, #44] ; (8001364 <HAL_RCC_GetSysClockFreq+0x158>)
- 8001338: 685b ldr r3, [r3, #4]
- 800133a: 0c1b lsrs r3, r3, #16
- 800133c: f003 0303 and.w r3, r3, #3
- 8001340: 3301 adds r3, #1
- 8001342: 005b lsls r3, r3, #1
- 8001344: 603b str r3, [r7, #0]
+ 80012f2: 4b0b ldr r3, [pc, #44] ; (8001320 <HAL_RCC_GetSysClockFreq+0x158>)
+ 80012f4: 685b ldr r3, [r3, #4]
+ 80012f6: 0c1b lsrs r3, r3, #16
+ 80012f8: f003 0303 and.w r3, r3, #3
+ 80012fc: 3301 adds r3, #1
+ 80012fe: 005b lsls r3, r3, #1
+ 8001300: 603b str r3, [r7, #0]
sysclockfreq = pllvco/pllp;
- 8001346: 68fa ldr r2, [r7, #12]
- 8001348: 683b ldr r3, [r7, #0]
- 800134a: fbb2 f3f3 udiv r3, r2, r3
- 800134e: 60bb str r3, [r7, #8]
+ 8001302: 68fa ldr r2, [r7, #12]
+ 8001304: 683b ldr r3, [r7, #0]
+ 8001306: fbb2 f3f3 udiv r3, r2, r3
+ 800130a: 60bb str r3, [r7, #8]
break;
- 8001350: e002 b.n 8001358 <HAL_RCC_GetSysClockFreq+0x14c>
+ 800130c: e002 b.n 8001314 <HAL_RCC_GetSysClockFreq+0x14c>
}
default:
{
sysclockfreq = HSI_VALUE;
- 8001352: 4b05 ldr r3, [pc, #20] ; (8001368 <HAL_RCC_GetSysClockFreq+0x15c>)
- 8001354: 60bb str r3, [r7, #8]
+ 800130e: 4b05 ldr r3, [pc, #20] ; (8001324 <HAL_RCC_GetSysClockFreq+0x15c>)
+ 8001310: 60bb str r3, [r7, #8]
break;
- 8001356: bf00 nop
+ 8001312: bf00 nop
}
}
return sysclockfreq;
- 8001358: 68bb ldr r3, [r7, #8]
+ 8001314: 68bb ldr r3, [r7, #8]
}
- 800135a: 4618 mov r0, r3
- 800135c: 3714 adds r7, #20
- 800135e: 46bd mov sp, r7
- 8001360: bdf0 pop {r4, r5, r6, r7, pc}
- 8001362: bf00 nop
- 8001364: 40023800 .word 0x40023800
- 8001368: 00f42400 .word 0x00f42400
- 800136c: 017d7840 .word 0x017d7840
-
-08001370 <HAL_TIM_PWM_Init>:
+ 8001316: 4618 mov r0, r3
+ 8001318: 3714 adds r7, #20
+ 800131a: 46bd mov sp, r7
+ 800131c: bdf0 pop {r4, r5, r6, r7, pc}
+ 800131e: bf00 nop
+ 8001320: 40023800 .word 0x40023800
+ 8001324: 00f42400 .word 0x00f42400
+ 8001328: 017d7840 .word 0x017d7840
+
+0800132c <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
- 8001370: b580 push {r7, lr}
- 8001372: b082 sub sp, #8
- 8001374: af00 add r7, sp, #0
- 8001376: 6078 str r0, [r7, #4]
+ 800132c: b580 push {r7, lr}
+ 800132e: b082 sub sp, #8
+ 8001330: af00 add r7, sp, #0
+ 8001332: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
- 8001378: 687b ldr r3, [r7, #4]
- 800137a: 2b00 cmp r3, #0
- 800137c: d101 bne.n 8001382 <HAL_TIM_PWM_Init+0x12>
+ 8001334: 687b ldr r3, [r7, #4]
+ 8001336: 2b00 cmp r3, #0
+ 8001338: d101 bne.n 800133e <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
- 800137e: 2301 movs r3, #1
- 8001380: e01d b.n 80013be <HAL_TIM_PWM_Init+0x4e>
+ 800133a: 2301 movs r3, #1
+ 800133c: e01d b.n 800137a <HAL_TIM_PWM_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
- 8001382: 687b ldr r3, [r7, #4]
- 8001384: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
- 8001388: b2db uxtb r3, r3
- 800138a: 2b00 cmp r3, #0
- 800138c: d106 bne.n 800139c <HAL_TIM_PWM_Init+0x2c>
+ 800133e: 687b ldr r3, [r7, #4]
+ 8001340: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
+ 8001344: b2db uxtb r3, r3
+ 8001346: 2b00 cmp r3, #0
+ 8001348: d106 bne.n 8001358 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
- 800138e: 687b ldr r3, [r7, #4]
- 8001390: 2200 movs r2, #0
- 8001392: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 800134a: 687b ldr r3, [r7, #4]
+ 800134c: 2200 movs r2, #0
+ 800134e: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
- 8001396: 6878 ldr r0, [r7, #4]
- 8001398: f000 fe3a bl 8002010 <HAL_TIM_PWM_MspInit>
+ 8001352: 6878 ldr r0, [r7, #4]
+ 8001354: f000 fe94 bl 8002080 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
- 800139c: 687b ldr r3, [r7, #4]
- 800139e: 2202 movs r2, #2
- 80013a0: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8001358: 687b ldr r3, [r7, #4]
+ 800135a: 2202 movs r2, #2
+ 800135c: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80013a4: 687b ldr r3, [r7, #4]
- 80013a6: 681a ldr r2, [r3, #0]
- 80013a8: 687b ldr r3, [r7, #4]
- 80013aa: 3304 adds r3, #4
- 80013ac: 4619 mov r1, r3
- 80013ae: 4610 mov r0, r2
- 80013b0: f000 f966 bl 8001680 <TIM_Base_SetConfig>
+ 8001360: 687b ldr r3, [r7, #4]
+ 8001362: 681a ldr r2, [r3, #0]
+ 8001364: 687b ldr r3, [r7, #4]
+ 8001366: 3304 adds r3, #4
+ 8001368: 4619 mov r1, r3
+ 800136a: 4610 mov r0, r2
+ 800136c: f000 f9be bl 80016ec <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
- 80013b4: 687b ldr r3, [r7, #4]
- 80013b6: 2201 movs r2, #1
- 80013b8: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8001370: 687b ldr r3, [r7, #4]
+ 8001372: 2201 movs r2, #1
+ 8001374: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
- 80013bc: 2300 movs r3, #0
+ 8001378: 2300 movs r3, #0
}
- 80013be: 4618 mov r0, r3
- 80013c0: 3708 adds r7, #8
- 80013c2: 46bd mov sp, r7
- 80013c4: bd80 pop {r7, pc}
+ 800137a: 4618 mov r0, r3
+ 800137c: 3708 adds r7, #8
+ 800137e: 46bd mov sp, r7
+ 8001380: bd80 pop {r7, pc}
...
-080013c8 <HAL_TIM_PWM_Start>:
+08001384 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- 80013c8: b580 push {r7, lr}
- 80013ca: b084 sub sp, #16
- 80013cc: af00 add r7, sp, #0
- 80013ce: 6078 str r0, [r7, #4]
- 80013d0: 6039 str r1, [r7, #0]
+ 8001384: b580 push {r7, lr}
+ 8001386: b084 sub sp, #16
+ 8001388: af00 add r7, sp, #0
+ 800138a: 6078 str r0, [r7, #4]
+ 800138c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- 80013d2: 687b ldr r3, [r7, #4]
- 80013d4: 681b ldr r3, [r3, #0]
- 80013d6: 2201 movs r2, #1
- 80013d8: 6839 ldr r1, [r7, #0]
- 80013da: 4618 mov r0, r3
- 80013dc: f000 fc4e bl 8001c7c <TIM_CCxChannelCmd>
+ 800138e: 687b ldr r3, [r7, #4]
+ 8001390: 681b ldr r3, [r3, #0]
+ 8001392: 2201 movs r2, #1
+ 8001394: 6839 ldr r1, [r7, #0]
+ 8001396: 4618 mov r0, r3
+ 8001398: f000 fca6 bl 8001ce8 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- 80013e0: 687b ldr r3, [r7, #4]
- 80013e2: 681b ldr r3, [r3, #0]
- 80013e4: 4a17 ldr r2, [pc, #92] ; (8001444 <HAL_TIM_PWM_Start+0x7c>)
- 80013e6: 4293 cmp r3, r2
- 80013e8: d004 beq.n 80013f4 <HAL_TIM_PWM_Start+0x2c>
- 80013ea: 687b ldr r3, [r7, #4]
- 80013ec: 681b ldr r3, [r3, #0]
- 80013ee: 4a16 ldr r2, [pc, #88] ; (8001448 <HAL_TIM_PWM_Start+0x80>)
- 80013f0: 4293 cmp r3, r2
- 80013f2: d101 bne.n 80013f8 <HAL_TIM_PWM_Start+0x30>
- 80013f4: 2301 movs r3, #1
- 80013f6: e000 b.n 80013fa <HAL_TIM_PWM_Start+0x32>
- 80013f8: 2300 movs r3, #0
- 80013fa: 2b00 cmp r3, #0
- 80013fc: d007 beq.n 800140e <HAL_TIM_PWM_Start+0x46>
+ 800139c: 687b ldr r3, [r7, #4]
+ 800139e: 681b ldr r3, [r3, #0]
+ 80013a0: 4a17 ldr r2, [pc, #92] ; (8001400 <HAL_TIM_PWM_Start+0x7c>)
+ 80013a2: 4293 cmp r3, r2
+ 80013a4: d004 beq.n 80013b0 <HAL_TIM_PWM_Start+0x2c>
+ 80013a6: 687b ldr r3, [r7, #4]
+ 80013a8: 681b ldr r3, [r3, #0]
+ 80013aa: 4a16 ldr r2, [pc, #88] ; (8001404 <HAL_TIM_PWM_Start+0x80>)
+ 80013ac: 4293 cmp r3, r2
+ 80013ae: d101 bne.n 80013b4 <HAL_TIM_PWM_Start+0x30>
+ 80013b0: 2301 movs r3, #1
+ 80013b2: e000 b.n 80013b6 <HAL_TIM_PWM_Start+0x32>
+ 80013b4: 2300 movs r3, #0
+ 80013b6: 2b00 cmp r3, #0
+ 80013b8: d007 beq.n 80013ca <HAL_TIM_PWM_Start+0x46>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
- 80013fe: 687b ldr r3, [r7, #4]
- 8001400: 681b ldr r3, [r3, #0]
- 8001402: 6c5a ldr r2, [r3, #68] ; 0x44
- 8001404: 687b ldr r3, [r7, #4]
- 8001406: 681b ldr r3, [r3, #0]
- 8001408: f442 4200 orr.w r2, r2, #32768 ; 0x8000
- 800140c: 645a str r2, [r3, #68] ; 0x44
+ 80013ba: 687b ldr r3, [r7, #4]
+ 80013bc: 681b ldr r3, [r3, #0]
+ 80013be: 6c5a ldr r2, [r3, #68] ; 0x44
+ 80013c0: 687b ldr r3, [r7, #4]
+ 80013c2: 681b ldr r3, [r3, #0]
+ 80013c4: f442 4200 orr.w r2, r2, #32768 ; 0x8000
+ 80013c8: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 800140e: 687b ldr r3, [r7, #4]
- 8001410: 681b ldr r3, [r3, #0]
- 8001412: 689a ldr r2, [r3, #8]
- 8001414: 4b0d ldr r3, [pc, #52] ; (800144c <HAL_TIM_PWM_Start+0x84>)
- 8001416: 4013 ands r3, r2
- 8001418: 60fb str r3, [r7, #12]
+ 80013ca: 687b ldr r3, [r7, #4]
+ 80013cc: 681b ldr r3, [r3, #0]
+ 80013ce: 689a ldr r2, [r3, #8]
+ 80013d0: 4b0d ldr r3, [pc, #52] ; (8001408 <HAL_TIM_PWM_Start+0x84>)
+ 80013d2: 4013 ands r3, r2
+ 80013d4: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 800141a: 68fb ldr r3, [r7, #12]
- 800141c: 2b06 cmp r3, #6
- 800141e: d00b beq.n 8001438 <HAL_TIM_PWM_Start+0x70>
- 8001420: 68fb ldr r3, [r7, #12]
- 8001422: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
- 8001426: d007 beq.n 8001438 <HAL_TIM_PWM_Start+0x70>
+ 80013d6: 68fb ldr r3, [r7, #12]
+ 80013d8: 2b06 cmp r3, #6
+ 80013da: d00b beq.n 80013f4 <HAL_TIM_PWM_Start+0x70>
+ 80013dc: 68fb ldr r3, [r7, #12]
+ 80013de: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
+ 80013e2: d007 beq.n 80013f4 <HAL_TIM_PWM_Start+0x70>
{
__HAL_TIM_ENABLE(htim);
- 8001428: 687b ldr r3, [r7, #4]
- 800142a: 681b ldr r3, [r3, #0]
- 800142c: 681a ldr r2, [r3, #0]
+ 80013e4: 687b ldr r3, [r7, #4]
+ 80013e6: 681b ldr r3, [r3, #0]
+ 80013e8: 681a ldr r2, [r3, #0]
+ 80013ea: 687b ldr r3, [r7, #4]
+ 80013ec: 681b ldr r3, [r3, #0]
+ 80013ee: f042 0201 orr.w r2, r2, #1
+ 80013f2: 601a str r2, [r3, #0]
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ 80013f4: 2300 movs r3, #0
+}
+ 80013f6: 4618 mov r0, r3
+ 80013f8: 3710 adds r7, #16
+ 80013fa: 46bd mov sp, r7
+ 80013fc: bd80 pop {r7, pc}
+ 80013fe: bf00 nop
+ 8001400: 40010000 .word 0x40010000
+ 8001404: 40010400 .word 0x40010400
+ 8001408: 00010007 .word 0x00010007
+
+0800140c <HAL_TIM_PWM_Stop>:
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ 800140c: b580 push {r7, lr}
+ 800140e: b082 sub sp, #8
+ 8001410: af00 add r7, sp, #0
+ 8001412: 6078 str r0, [r7, #4]
+ 8001414: 6039 str r1, [r7, #0]
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+ 8001416: 687b ldr r3, [r7, #4]
+ 8001418: 681b ldr r3, [r3, #0]
+ 800141a: 2200 movs r2, #0
+ 800141c: 6839 ldr r1, [r7, #0]
+ 800141e: 4618 mov r0, r3
+ 8001420: f000 fc62 bl 8001ce8 <TIM_CCxChannelCmd>
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 8001424: 687b ldr r3, [r7, #4]
+ 8001426: 681b ldr r3, [r3, #0]
+ 8001428: 4a22 ldr r2, [pc, #136] ; (80014b4 <HAL_TIM_PWM_Stop+0xa8>)
+ 800142a: 4293 cmp r3, r2
+ 800142c: d004 beq.n 8001438 <HAL_TIM_PWM_Stop+0x2c>
800142e: 687b ldr r3, [r7, #4]
8001430: 681b ldr r3, [r3, #0]
- 8001432: f042 0201 orr.w r2, r2, #1
- 8001436: 601a str r2, [r3, #0]
+ 8001432: 4a21 ldr r2, [pc, #132] ; (80014b8 <HAL_TIM_PWM_Stop+0xac>)
+ 8001434: 4293 cmp r3, r2
+ 8001436: d101 bne.n 800143c <HAL_TIM_PWM_Stop+0x30>
+ 8001438: 2301 movs r3, #1
+ 800143a: e000 b.n 800143e <HAL_TIM_PWM_Stop+0x32>
+ 800143c: 2300 movs r3, #0
+ 800143e: 2b00 cmp r3, #0
+ 8001440: d017 beq.n 8001472 <HAL_TIM_PWM_Stop+0x66>
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ 8001442: 687b ldr r3, [r7, #4]
+ 8001444: 681b ldr r3, [r3, #0]
+ 8001446: 6a1a ldr r2, [r3, #32]
+ 8001448: f241 1311 movw r3, #4369 ; 0x1111
+ 800144c: 4013 ands r3, r2
+ 800144e: 2b00 cmp r3, #0
+ 8001450: d10f bne.n 8001472 <HAL_TIM_PWM_Stop+0x66>
+ 8001452: 687b ldr r3, [r7, #4]
+ 8001454: 681b ldr r3, [r3, #0]
+ 8001456: 6a1a ldr r2, [r3, #32]
+ 8001458: f240 4344 movw r3, #1092 ; 0x444
+ 800145c: 4013 ands r3, r2
+ 800145e: 2b00 cmp r3, #0
+ 8001460: d107 bne.n 8001472 <HAL_TIM_PWM_Stop+0x66>
+ 8001462: 687b ldr r3, [r7, #4]
+ 8001464: 681b ldr r3, [r3, #0]
+ 8001466: 6c5a ldr r2, [r3, #68] ; 0x44
+ 8001468: 687b ldr r3, [r7, #4]
+ 800146a: 681b ldr r3, [r3, #0]
+ 800146c: f422 4200 bic.w r2, r2, #32768 ; 0x8000
+ 8001470: 645a str r2, [r3, #68] ; 0x44
}
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+ 8001472: 687b ldr r3, [r7, #4]
+ 8001474: 681b ldr r3, [r3, #0]
+ 8001476: 6a1a ldr r2, [r3, #32]
+ 8001478: f241 1311 movw r3, #4369 ; 0x1111
+ 800147c: 4013 ands r3, r2
+ 800147e: 2b00 cmp r3, #0
+ 8001480: d10f bne.n 80014a2 <HAL_TIM_PWM_Stop+0x96>
+ 8001482: 687b ldr r3, [r7, #4]
+ 8001484: 681b ldr r3, [r3, #0]
+ 8001486: 6a1a ldr r2, [r3, #32]
+ 8001488: f240 4344 movw r3, #1092 ; 0x444
+ 800148c: 4013 ands r3, r2
+ 800148e: 2b00 cmp r3, #0
+ 8001490: d107 bne.n 80014a2 <HAL_TIM_PWM_Stop+0x96>
+ 8001492: 687b ldr r3, [r7, #4]
+ 8001494: 681b ldr r3, [r3, #0]
+ 8001496: 681a ldr r2, [r3, #0]
+ 8001498: 687b ldr r3, [r7, #4]
+ 800149a: 681b ldr r3, [r3, #0]
+ 800149c: f022 0201 bic.w r2, r2, #1
+ 80014a0: 601a str r2, [r3, #0]
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+ 80014a2: 687b ldr r3, [r7, #4]
+ 80014a4: 2201 movs r2, #1
+ 80014a6: f883 203d strb.w r2, [r3, #61] ; 0x3d
+
/* Return function status */
return HAL_OK;
- 8001438: 2300 movs r3, #0
+ 80014aa: 2300 movs r3, #0
}
- 800143a: 4618 mov r0, r3
- 800143c: 3710 adds r7, #16
- 800143e: 46bd mov sp, r7
- 8001440: bd80 pop {r7, pc}
- 8001442: bf00 nop
- 8001444: 40010000 .word 0x40010000
- 8001448: 40010400 .word 0x40010400
- 800144c: 00010007 .word 0x00010007
-
-08001450 <HAL_TIM_PWM_ConfigChannel>:
+ 80014ac: 4618 mov r0, r3
+ 80014ae: 3708 adds r7, #8
+ 80014b0: 46bd mov sp, r7
+ 80014b2: bd80 pop {r7, pc}
+ 80014b4: 40010000 .word 0x40010000
+ 80014b8: 40010400 .word 0x40010400
+
+080014bc <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
- 8001450: b580 push {r7, lr}
- 8001452: b084 sub sp, #16
- 8001454: af00 add r7, sp, #0
- 8001456: 60f8 str r0, [r7, #12]
- 8001458: 60b9 str r1, [r7, #8]
- 800145a: 607a str r2, [r7, #4]
+ 80014bc: b580 push {r7, lr}
+ 80014be: b084 sub sp, #16
+ 80014c0: af00 add r7, sp, #0
+ 80014c2: 60f8 str r0, [r7, #12]
+ 80014c4: 60b9 str r1, [r7, #8]
+ 80014c6: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
- 800145c: 68fb ldr r3, [r7, #12]
- 800145e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8001462: 2b01 cmp r3, #1
- 8001464: d101 bne.n 800146a <HAL_TIM_PWM_ConfigChannel+0x1a>
- 8001466: 2302 movs r3, #2
- 8001468: e105 b.n 8001676 <HAL_TIM_PWM_ConfigChannel+0x226>
- 800146a: 68fb ldr r3, [r7, #12]
- 800146c: 2201 movs r2, #1
- 800146e: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 80014c8: 68fb ldr r3, [r7, #12]
+ 80014ca: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 80014ce: 2b01 cmp r3, #1
+ 80014d0: d101 bne.n 80014d6 <HAL_TIM_PWM_ConfigChannel+0x1a>
+ 80014d2: 2302 movs r3, #2
+ 80014d4: e105 b.n 80016e2 <HAL_TIM_PWM_ConfigChannel+0x226>
+ 80014d6: 68fb ldr r3, [r7, #12]
+ 80014d8: 2201 movs r2, #1
+ 80014da: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
- 8001472: 68fb ldr r3, [r7, #12]
- 8001474: 2202 movs r2, #2
- 8001476: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 80014de: 68fb ldr r3, [r7, #12]
+ 80014e0: 2202 movs r2, #2
+ 80014e2: f883 203d strb.w r2, [r3, #61] ; 0x3d
switch (Channel)
- 800147a: 687b ldr r3, [r7, #4]
- 800147c: 2b14 cmp r3, #20
- 800147e: f200 80f0 bhi.w 8001662 <HAL_TIM_PWM_ConfigChannel+0x212>
- 8001482: a201 add r2, pc, #4 ; (adr r2, 8001488 <HAL_TIM_PWM_ConfigChannel+0x38>)
- 8001484: f852 f023 ldr.w pc, [r2, r3, lsl #2]
- 8001488: 080014dd .word 0x080014dd
- 800148c: 08001663 .word 0x08001663
- 8001490: 08001663 .word 0x08001663
- 8001494: 08001663 .word 0x08001663
- 8001498: 0800151d .word 0x0800151d
- 800149c: 08001663 .word 0x08001663
- 80014a0: 08001663 .word 0x08001663
- 80014a4: 08001663 .word 0x08001663
- 80014a8: 0800155f .word 0x0800155f
- 80014ac: 08001663 .word 0x08001663
- 80014b0: 08001663 .word 0x08001663
- 80014b4: 08001663 .word 0x08001663
- 80014b8: 0800159f .word 0x0800159f
- 80014bc: 08001663 .word 0x08001663
- 80014c0: 08001663 .word 0x08001663
- 80014c4: 08001663 .word 0x08001663
- 80014c8: 080015e1 .word 0x080015e1
- 80014cc: 08001663 .word 0x08001663
- 80014d0: 08001663 .word 0x08001663
- 80014d4: 08001663 .word 0x08001663
- 80014d8: 08001621 .word 0x08001621
+ 80014e6: 687b ldr r3, [r7, #4]
+ 80014e8: 2b14 cmp r3, #20
+ 80014ea: f200 80f0 bhi.w 80016ce <HAL_TIM_PWM_ConfigChannel+0x212>
+ 80014ee: a201 add r2, pc, #4 ; (adr r2, 80014f4 <HAL_TIM_PWM_ConfigChannel+0x38>)
+ 80014f0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
+ 80014f4: 08001549 .word 0x08001549
+ 80014f8: 080016cf .word 0x080016cf
+ 80014fc: 080016cf .word 0x080016cf
+ 8001500: 080016cf .word 0x080016cf
+ 8001504: 08001589 .word 0x08001589
+ 8001508: 080016cf .word 0x080016cf
+ 800150c: 080016cf .word 0x080016cf
+ 8001510: 080016cf .word 0x080016cf
+ 8001514: 080015cb .word 0x080015cb
+ 8001518: 080016cf .word 0x080016cf
+ 800151c: 080016cf .word 0x080016cf
+ 8001520: 080016cf .word 0x080016cf
+ 8001524: 0800160b .word 0x0800160b
+ 8001528: 080016cf .word 0x080016cf
+ 800152c: 080016cf .word 0x080016cf
+ 8001530: 080016cf .word 0x080016cf
+ 8001534: 0800164d .word 0x0800164d
+ 8001538: 080016cf .word 0x080016cf
+ 800153c: 080016cf .word 0x080016cf
+ 8001540: 080016cf .word 0x080016cf
+ 8001544: 0800168d .word 0x0800168d
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
- 80014dc: 68fb ldr r3, [r7, #12]
- 80014de: 681b ldr r3, [r3, #0]
- 80014e0: 68b9 ldr r1, [r7, #8]
- 80014e2: 4618 mov r0, r3
- 80014e4: f000 f96c bl 80017c0 <TIM_OC1_SetConfig>
+ 8001548: 68fb ldr r3, [r7, #12]
+ 800154a: 681b ldr r3, [r3, #0]
+ 800154c: 68b9 ldr r1, [r7, #8]
+ 800154e: 4618 mov r0, r3
+ 8001550: f000 f96c bl 800182c <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 80014e8: 68fb ldr r3, [r7, #12]
- 80014ea: 681b ldr r3, [r3, #0]
- 80014ec: 699a ldr r2, [r3, #24]
- 80014ee: 68fb ldr r3, [r7, #12]
- 80014f0: 681b ldr r3, [r3, #0]
- 80014f2: f042 0208 orr.w r2, r2, #8
- 80014f6: 619a str r2, [r3, #24]
+ 8001554: 68fb ldr r3, [r7, #12]
+ 8001556: 681b ldr r3, [r3, #0]
+ 8001558: 699a ldr r2, [r3, #24]
+ 800155a: 68fb ldr r3, [r7, #12]
+ 800155c: 681b ldr r3, [r3, #0]
+ 800155e: f042 0208 orr.w r2, r2, #8
+ 8001562: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- 80014f8: 68fb ldr r3, [r7, #12]
- 80014fa: 681b ldr r3, [r3, #0]
- 80014fc: 699a ldr r2, [r3, #24]
- 80014fe: 68fb ldr r3, [r7, #12]
- 8001500: 681b ldr r3, [r3, #0]
- 8001502: f022 0204 bic.w r2, r2, #4
- 8001506: 619a str r2, [r3, #24]
+ 8001564: 68fb ldr r3, [r7, #12]
+ 8001566: 681b ldr r3, [r3, #0]
+ 8001568: 699a ldr r2, [r3, #24]
+ 800156a: 68fb ldr r3, [r7, #12]
+ 800156c: 681b ldr r3, [r3, #0]
+ 800156e: f022 0204 bic.w r2, r2, #4
+ 8001572: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
- 8001508: 68fb ldr r3, [r7, #12]
- 800150a: 681b ldr r3, [r3, #0]
- 800150c: 6999 ldr r1, [r3, #24]
- 800150e: 68bb ldr r3, [r7, #8]
- 8001510: 691a ldr r2, [r3, #16]
- 8001512: 68fb ldr r3, [r7, #12]
- 8001514: 681b ldr r3, [r3, #0]
- 8001516: 430a orrs r2, r1
- 8001518: 619a str r2, [r3, #24]
+ 8001574: 68fb ldr r3, [r7, #12]
+ 8001576: 681b ldr r3, [r3, #0]
+ 8001578: 6999 ldr r1, [r3, #24]
+ 800157a: 68bb ldr r3, [r7, #8]
+ 800157c: 691a ldr r2, [r3, #16]
+ 800157e: 68fb ldr r3, [r7, #12]
+ 8001580: 681b ldr r3, [r3, #0]
+ 8001582: 430a orrs r2, r1
+ 8001584: 619a str r2, [r3, #24]
break;
- 800151a: e0a3 b.n 8001664 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 8001586: e0a3 b.n 80016d0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
- 800151c: 68fb ldr r3, [r7, #12]
- 800151e: 681b ldr r3, [r3, #0]
- 8001520: 68b9 ldr r1, [r7, #8]
- 8001522: 4618 mov r0, r3
- 8001524: f000 f9be bl 80018a4 <TIM_OC2_SetConfig>
+ 8001588: 68fb ldr r3, [r7, #12]
+ 800158a: 681b ldr r3, [r3, #0]
+ 800158c: 68b9 ldr r1, [r7, #8]
+ 800158e: 4618 mov r0, r3
+ 8001590: f000 f9be bl 8001910 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 8001528: 68fb ldr r3, [r7, #12]
- 800152a: 681b ldr r3, [r3, #0]
- 800152c: 699a ldr r2, [r3, #24]
- 800152e: 68fb ldr r3, [r7, #12]
- 8001530: 681b ldr r3, [r3, #0]
- 8001532: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 8001536: 619a str r2, [r3, #24]
+ 8001594: 68fb ldr r3, [r7, #12]
+ 8001596: 681b ldr r3, [r3, #0]
+ 8001598: 699a ldr r2, [r3, #24]
+ 800159a: 68fb ldr r3, [r7, #12]
+ 800159c: 681b ldr r3, [r3, #0]
+ 800159e: f442 6200 orr.w r2, r2, #2048 ; 0x800
+ 80015a2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 8001538: 68fb ldr r3, [r7, #12]
- 800153a: 681b ldr r3, [r3, #0]
- 800153c: 699a ldr r2, [r3, #24]
- 800153e: 68fb ldr r3, [r7, #12]
- 8001540: 681b ldr r3, [r3, #0]
- 8001542: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 8001546: 619a str r2, [r3, #24]
+ 80015a4: 68fb ldr r3, [r7, #12]
+ 80015a6: 681b ldr r3, [r3, #0]
+ 80015a8: 699a ldr r2, [r3, #24]
+ 80015aa: 68fb ldr r3, [r7, #12]
+ 80015ac: 681b ldr r3, [r3, #0]
+ 80015ae: f422 6280 bic.w r2, r2, #1024 ; 0x400
+ 80015b2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- 8001548: 68fb ldr r3, [r7, #12]
- 800154a: 681b ldr r3, [r3, #0]
- 800154c: 6999 ldr r1, [r3, #24]
- 800154e: 68bb ldr r3, [r7, #8]
- 8001550: 691b ldr r3, [r3, #16]
- 8001552: 021a lsls r2, r3, #8
- 8001554: 68fb ldr r3, [r7, #12]
- 8001556: 681b ldr r3, [r3, #0]
- 8001558: 430a orrs r2, r1
- 800155a: 619a str r2, [r3, #24]
+ 80015b4: 68fb ldr r3, [r7, #12]
+ 80015b6: 681b ldr r3, [r3, #0]
+ 80015b8: 6999 ldr r1, [r3, #24]
+ 80015ba: 68bb ldr r3, [r7, #8]
+ 80015bc: 691b ldr r3, [r3, #16]
+ 80015be: 021a lsls r2, r3, #8
+ 80015c0: 68fb ldr r3, [r7, #12]
+ 80015c2: 681b ldr r3, [r3, #0]
+ 80015c4: 430a orrs r2, r1
+ 80015c6: 619a str r2, [r3, #24]
break;
- 800155c: e082 b.n 8001664 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 80015c8: e082 b.n 80016d0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
- 800155e: 68fb ldr r3, [r7, #12]
- 8001560: 681b ldr r3, [r3, #0]
- 8001562: 68b9 ldr r1, [r7, #8]
- 8001564: 4618 mov r0, r3
- 8001566: f000 fa15 bl 8001994 <TIM_OC3_SetConfig>
+ 80015ca: 68fb ldr r3, [r7, #12]
+ 80015cc: 681b ldr r3, [r3, #0]
+ 80015ce: 68b9 ldr r1, [r7, #8]
+ 80015d0: 4618 mov r0, r3
+ 80015d2: f000 fa15 bl 8001a00 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 800156a: 68fb ldr r3, [r7, #12]
- 800156c: 681b ldr r3, [r3, #0]
- 800156e: 69da ldr r2, [r3, #28]
- 8001570: 68fb ldr r3, [r7, #12]
- 8001572: 681b ldr r3, [r3, #0]
- 8001574: f042 0208 orr.w r2, r2, #8
- 8001578: 61da str r2, [r3, #28]
+ 80015d6: 68fb ldr r3, [r7, #12]
+ 80015d8: 681b ldr r3, [r3, #0]
+ 80015da: 69da ldr r2, [r3, #28]
+ 80015dc: 68fb ldr r3, [r7, #12]
+ 80015de: 681b ldr r3, [r3, #0]
+ 80015e0: f042 0208 orr.w r2, r2, #8
+ 80015e4: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- 800157a: 68fb ldr r3, [r7, #12]
- 800157c: 681b ldr r3, [r3, #0]
- 800157e: 69da ldr r2, [r3, #28]
- 8001580: 68fb ldr r3, [r7, #12]
- 8001582: 681b ldr r3, [r3, #0]
- 8001584: f022 0204 bic.w r2, r2, #4
- 8001588: 61da str r2, [r3, #28]
+ 80015e6: 68fb ldr r3, [r7, #12]
+ 80015e8: 681b ldr r3, [r3, #0]
+ 80015ea: 69da ldr r2, [r3, #28]
+ 80015ec: 68fb ldr r3, [r7, #12]
+ 80015ee: 681b ldr r3, [r3, #0]
+ 80015f0: f022 0204 bic.w r2, r2, #4
+ 80015f4: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
- 800158a: 68fb ldr r3, [r7, #12]
- 800158c: 681b ldr r3, [r3, #0]
- 800158e: 69d9 ldr r1, [r3, #28]
- 8001590: 68bb ldr r3, [r7, #8]
- 8001592: 691a ldr r2, [r3, #16]
- 8001594: 68fb ldr r3, [r7, #12]
- 8001596: 681b ldr r3, [r3, #0]
- 8001598: 430a orrs r2, r1
- 800159a: 61da str r2, [r3, #28]
+ 80015f6: 68fb ldr r3, [r7, #12]
+ 80015f8: 681b ldr r3, [r3, #0]
+ 80015fa: 69d9 ldr r1, [r3, #28]
+ 80015fc: 68bb ldr r3, [r7, #8]
+ 80015fe: 691a ldr r2, [r3, #16]
+ 8001600: 68fb ldr r3, [r7, #12]
+ 8001602: 681b ldr r3, [r3, #0]
+ 8001604: 430a orrs r2, r1
+ 8001606: 61da str r2, [r3, #28]
break;
- 800159c: e062 b.n 8001664 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 8001608: e062 b.n 80016d0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
- 800159e: 68fb ldr r3, [r7, #12]
- 80015a0: 681b ldr r3, [r3, #0]
- 80015a2: 68b9 ldr r1, [r7, #8]
- 80015a4: 4618 mov r0, r3
- 80015a6: f000 fa6b bl 8001a80 <TIM_OC4_SetConfig>
+ 800160a: 68fb ldr r3, [r7, #12]
+ 800160c: 681b ldr r3, [r3, #0]
+ 800160e: 68b9 ldr r1, [r7, #8]
+ 8001610: 4618 mov r0, r3
+ 8001612: f000 fa6b bl 8001aec <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 80015aa: 68fb ldr r3, [r7, #12]
- 80015ac: 681b ldr r3, [r3, #0]
- 80015ae: 69da ldr r2, [r3, #28]
- 80015b0: 68fb ldr r3, [r7, #12]
- 80015b2: 681b ldr r3, [r3, #0]
- 80015b4: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 80015b8: 61da str r2, [r3, #28]
+ 8001616: 68fb ldr r3, [r7, #12]
+ 8001618: 681b ldr r3, [r3, #0]
+ 800161a: 69da ldr r2, [r3, #28]
+ 800161c: 68fb ldr r3, [r7, #12]
+ 800161e: 681b ldr r3, [r3, #0]
+ 8001620: f442 6200 orr.w r2, r2, #2048 ; 0x800
+ 8001624: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 80015ba: 68fb ldr r3, [r7, #12]
- 80015bc: 681b ldr r3, [r3, #0]
- 80015be: 69da ldr r2, [r3, #28]
- 80015c0: 68fb ldr r3, [r7, #12]
- 80015c2: 681b ldr r3, [r3, #0]
- 80015c4: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 80015c8: 61da str r2, [r3, #28]
+ 8001626: 68fb ldr r3, [r7, #12]
+ 8001628: 681b ldr r3, [r3, #0]
+ 800162a: 69da ldr r2, [r3, #28]
+ 800162c: 68fb ldr r3, [r7, #12]
+ 800162e: 681b ldr r3, [r3, #0]
+ 8001630: f422 6280 bic.w r2, r2, #1024 ; 0x400
+ 8001634: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- 80015ca: 68fb ldr r3, [r7, #12]
- 80015cc: 681b ldr r3, [r3, #0]
- 80015ce: 69d9 ldr r1, [r3, #28]
- 80015d0: 68bb ldr r3, [r7, #8]
- 80015d2: 691b ldr r3, [r3, #16]
- 80015d4: 021a lsls r2, r3, #8
- 80015d6: 68fb ldr r3, [r7, #12]
- 80015d8: 681b ldr r3, [r3, #0]
- 80015da: 430a orrs r2, r1
- 80015dc: 61da str r2, [r3, #28]
+ 8001636: 68fb ldr r3, [r7, #12]
+ 8001638: 681b ldr r3, [r3, #0]
+ 800163a: 69d9 ldr r1, [r3, #28]
+ 800163c: 68bb ldr r3, [r7, #8]
+ 800163e: 691b ldr r3, [r3, #16]
+ 8001640: 021a lsls r2, r3, #8
+ 8001642: 68fb ldr r3, [r7, #12]
+ 8001644: 681b ldr r3, [r3, #0]
+ 8001646: 430a orrs r2, r1
+ 8001648: 61da str r2, [r3, #28]
break;
- 80015de: e041 b.n 8001664 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 800164a: e041 b.n 80016d0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
- 80015e0: 68fb ldr r3, [r7, #12]
- 80015e2: 681b ldr r3, [r3, #0]
- 80015e4: 68b9 ldr r1, [r7, #8]
- 80015e6: 4618 mov r0, r3
- 80015e8: f000 faa2 bl 8001b30 <TIM_OC5_SetConfig>
+ 800164c: 68fb ldr r3, [r7, #12]
+ 800164e: 681b ldr r3, [r3, #0]
+ 8001650: 68b9 ldr r1, [r7, #8]
+ 8001652: 4618 mov r0, r3
+ 8001654: f000 faa2 bl 8001b9c <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
- 80015ec: 68fb ldr r3, [r7, #12]
- 80015ee: 681b ldr r3, [r3, #0]
- 80015f0: 6d5a ldr r2, [r3, #84] ; 0x54
- 80015f2: 68fb ldr r3, [r7, #12]
- 80015f4: 681b ldr r3, [r3, #0]
- 80015f6: f042 0208 orr.w r2, r2, #8
- 80015fa: 655a str r2, [r3, #84] ; 0x54
+ 8001658: 68fb ldr r3, [r7, #12]
+ 800165a: 681b ldr r3, [r3, #0]
+ 800165c: 6d5a ldr r2, [r3, #84] ; 0x54
+ 800165e: 68fb ldr r3, [r7, #12]
+ 8001660: 681b ldr r3, [r3, #0]
+ 8001662: f042 0208 orr.w r2, r2, #8
+ 8001666: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- 80015fc: 68fb ldr r3, [r7, #12]
- 80015fe: 681b ldr r3, [r3, #0]
- 8001600: 6d5a ldr r2, [r3, #84] ; 0x54
- 8001602: 68fb ldr r3, [r7, #12]
- 8001604: 681b ldr r3, [r3, #0]
- 8001606: f022 0204 bic.w r2, r2, #4
- 800160a: 655a str r2, [r3, #84] ; 0x54
+ 8001668: 68fb ldr r3, [r7, #12]
+ 800166a: 681b ldr r3, [r3, #0]
+ 800166c: 6d5a ldr r2, [r3, #84] ; 0x54
+ 800166e: 68fb ldr r3, [r7, #12]
+ 8001670: 681b ldr r3, [r3, #0]
+ 8001672: f022 0204 bic.w r2, r2, #4
+ 8001676: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
- 800160c: 68fb ldr r3, [r7, #12]
- 800160e: 681b ldr r3, [r3, #0]
- 8001610: 6d59 ldr r1, [r3, #84] ; 0x54
- 8001612: 68bb ldr r3, [r7, #8]
- 8001614: 691a ldr r2, [r3, #16]
- 8001616: 68fb ldr r3, [r7, #12]
- 8001618: 681b ldr r3, [r3, #0]
- 800161a: 430a orrs r2, r1
- 800161c: 655a str r2, [r3, #84] ; 0x54
+ 8001678: 68fb ldr r3, [r7, #12]
+ 800167a: 681b ldr r3, [r3, #0]
+ 800167c: 6d59 ldr r1, [r3, #84] ; 0x54
+ 800167e: 68bb ldr r3, [r7, #8]
+ 8001680: 691a ldr r2, [r3, #16]
+ 8001682: 68fb ldr r3, [r7, #12]
+ 8001684: 681b ldr r3, [r3, #0]
+ 8001686: 430a orrs r2, r1
+ 8001688: 655a str r2, [r3, #84] ; 0x54
break;
- 800161e: e021 b.n 8001664 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 800168a: e021 b.n 80016d0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
- 8001620: 68fb ldr r3, [r7, #12]
- 8001622: 681b ldr r3, [r3, #0]
- 8001624: 68b9 ldr r1, [r7, #8]
- 8001626: 4618 mov r0, r3
- 8001628: f000 fad4 bl 8001bd4 <TIM_OC6_SetConfig>
+ 800168c: 68fb ldr r3, [r7, #12]
+ 800168e: 681b ldr r3, [r3, #0]
+ 8001690: 68b9 ldr r1, [r7, #8]
+ 8001692: 4618 mov r0, r3
+ 8001694: f000 fad4 bl 8001c40 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
- 800162c: 68fb ldr r3, [r7, #12]
- 800162e: 681b ldr r3, [r3, #0]
- 8001630: 6d5a ldr r2, [r3, #84] ; 0x54
- 8001632: 68fb ldr r3, [r7, #12]
- 8001634: 681b ldr r3, [r3, #0]
- 8001636: f442 6200 orr.w r2, r2, #2048 ; 0x800
- 800163a: 655a str r2, [r3, #84] ; 0x54
+ 8001698: 68fb ldr r3, [r7, #12]
+ 800169a: 681b ldr r3, [r3, #0]
+ 800169c: 6d5a ldr r2, [r3, #84] ; 0x54
+ 800169e: 68fb ldr r3, [r7, #12]
+ 80016a0: 681b ldr r3, [r3, #0]
+ 80016a2: f442 6200 orr.w r2, r2, #2048 ; 0x800
+ 80016a6: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- 800163c: 68fb ldr r3, [r7, #12]
- 800163e: 681b ldr r3, [r3, #0]
- 8001640: 6d5a ldr r2, [r3, #84] ; 0x54
- 8001642: 68fb ldr r3, [r7, #12]
- 8001644: 681b ldr r3, [r3, #0]
- 8001646: f422 6280 bic.w r2, r2, #1024 ; 0x400
- 800164a: 655a str r2, [r3, #84] ; 0x54
+ 80016a8: 68fb ldr r3, [r7, #12]
+ 80016aa: 681b ldr r3, [r3, #0]
+ 80016ac: 6d5a ldr r2, [r3, #84] ; 0x54
+ 80016ae: 68fb ldr r3, [r7, #12]
+ 80016b0: 681b ldr r3, [r3, #0]
+ 80016b2: f422 6280 bic.w r2, r2, #1024 ; 0x400
+ 80016b6: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- 800164c: 68fb ldr r3, [r7, #12]
- 800164e: 681b ldr r3, [r3, #0]
- 8001650: 6d59 ldr r1, [r3, #84] ; 0x54
- 8001652: 68bb ldr r3, [r7, #8]
- 8001654: 691b ldr r3, [r3, #16]
- 8001656: 021a lsls r2, r3, #8
- 8001658: 68fb ldr r3, [r7, #12]
- 800165a: 681b ldr r3, [r3, #0]
- 800165c: 430a orrs r2, r1
- 800165e: 655a str r2, [r3, #84] ; 0x54
+ 80016b8: 68fb ldr r3, [r7, #12]
+ 80016ba: 681b ldr r3, [r3, #0]
+ 80016bc: 6d59 ldr r1, [r3, #84] ; 0x54
+ 80016be: 68bb ldr r3, [r7, #8]
+ 80016c0: 691b ldr r3, [r3, #16]
+ 80016c2: 021a lsls r2, r3, #8
+ 80016c4: 68fb ldr r3, [r7, #12]
+ 80016c6: 681b ldr r3, [r3, #0]
+ 80016c8: 430a orrs r2, r1
+ 80016ca: 655a str r2, [r3, #84] ; 0x54
break;
- 8001660: e000 b.n 8001664 <HAL_TIM_PWM_ConfigChannel+0x214>
+ 80016cc: e000 b.n 80016d0 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
break;
- 8001662: bf00 nop
+ 80016ce: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
- 8001664: 68fb ldr r3, [r7, #12]
- 8001666: 2201 movs r2, #1
- 8001668: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 80016d0: 68fb ldr r3, [r7, #12]
+ 80016d2: 2201 movs r2, #1
+ 80016d4: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
- 800166c: 68fb ldr r3, [r7, #12]
- 800166e: 2200 movs r2, #0
- 8001670: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 80016d8: 68fb ldr r3, [r7, #12]
+ 80016da: 2200 movs r2, #0
+ 80016dc: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
- 8001674: 2300 movs r3, #0
+ 80016e0: 2300 movs r3, #0
}
- 8001676: 4618 mov r0, r3
- 8001678: 3710 adds r7, #16
- 800167a: 46bd mov sp, r7
- 800167c: bd80 pop {r7, pc}
- 800167e: bf00 nop
+ 80016e2: 4618 mov r0, r3
+ 80016e4: 3710 adds r7, #16
+ 80016e6: 46bd mov sp, r7
+ 80016e8: bd80 pop {r7, pc}
+ 80016ea: bf00 nop
-08001680 <TIM_Base_SetConfig>:
+080016ec <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- 8001680: b480 push {r7}
- 8001682: b085 sub sp, #20
- 8001684: af00 add r7, sp, #0
- 8001686: 6078 str r0, [r7, #4]
- 8001688: 6039 str r1, [r7, #0]
+ 80016ec: b480 push {r7}
+ 80016ee: b085 sub sp, #20
+ 80016f0: af00 add r7, sp, #0
+ 80016f2: 6078 str r0, [r7, #4]
+ 80016f4: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
- 800168a: 687b ldr r3, [r7, #4]
- 800168c: 681b ldr r3, [r3, #0]
- 800168e: 60fb str r3, [r7, #12]
+ 80016f6: 687b ldr r3, [r7, #4]
+ 80016f8: 681b ldr r3, [r3, #0]
+ 80016fa: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8001690: 687b ldr r3, [r7, #4]
- 8001692: 4a40 ldr r2, [pc, #256] ; (8001794 <TIM_Base_SetConfig+0x114>)
- 8001694: 4293 cmp r3, r2
- 8001696: d013 beq.n 80016c0 <TIM_Base_SetConfig+0x40>
- 8001698: 687b ldr r3, [r7, #4]
- 800169a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 800169e: d00f beq.n 80016c0 <TIM_Base_SetConfig+0x40>
- 80016a0: 687b ldr r3, [r7, #4]
- 80016a2: 4a3d ldr r2, [pc, #244] ; (8001798 <TIM_Base_SetConfig+0x118>)
- 80016a4: 4293 cmp r3, r2
- 80016a6: d00b beq.n 80016c0 <TIM_Base_SetConfig+0x40>
- 80016a8: 687b ldr r3, [r7, #4]
- 80016aa: 4a3c ldr r2, [pc, #240] ; (800179c <TIM_Base_SetConfig+0x11c>)
- 80016ac: 4293 cmp r3, r2
- 80016ae: d007 beq.n 80016c0 <TIM_Base_SetConfig+0x40>
- 80016b0: 687b ldr r3, [r7, #4]
- 80016b2: 4a3b ldr r2, [pc, #236] ; (80017a0 <TIM_Base_SetConfig+0x120>)
- 80016b4: 4293 cmp r3, r2
- 80016b6: d003 beq.n 80016c0 <TIM_Base_SetConfig+0x40>
- 80016b8: 687b ldr r3, [r7, #4]
- 80016ba: 4a3a ldr r2, [pc, #232] ; (80017a4 <TIM_Base_SetConfig+0x124>)
- 80016bc: 4293 cmp r3, r2
- 80016be: d108 bne.n 80016d2 <TIM_Base_SetConfig+0x52>
+ 80016fc: 687b ldr r3, [r7, #4]
+ 80016fe: 4a40 ldr r2, [pc, #256] ; (8001800 <TIM_Base_SetConfig+0x114>)
+ 8001700: 4293 cmp r3, r2
+ 8001702: d013 beq.n 800172c <TIM_Base_SetConfig+0x40>
+ 8001704: 687b ldr r3, [r7, #4]
+ 8001706: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 800170a: d00f beq.n 800172c <TIM_Base_SetConfig+0x40>
+ 800170c: 687b ldr r3, [r7, #4]
+ 800170e: 4a3d ldr r2, [pc, #244] ; (8001804 <TIM_Base_SetConfig+0x118>)
+ 8001710: 4293 cmp r3, r2
+ 8001712: d00b beq.n 800172c <TIM_Base_SetConfig+0x40>
+ 8001714: 687b ldr r3, [r7, #4]
+ 8001716: 4a3c ldr r2, [pc, #240] ; (8001808 <TIM_Base_SetConfig+0x11c>)
+ 8001718: 4293 cmp r3, r2
+ 800171a: d007 beq.n 800172c <TIM_Base_SetConfig+0x40>
+ 800171c: 687b ldr r3, [r7, #4]
+ 800171e: 4a3b ldr r2, [pc, #236] ; (800180c <TIM_Base_SetConfig+0x120>)
+ 8001720: 4293 cmp r3, r2
+ 8001722: d003 beq.n 800172c <TIM_Base_SetConfig+0x40>
+ 8001724: 687b ldr r3, [r7, #4]
+ 8001726: 4a3a ldr r2, [pc, #232] ; (8001810 <TIM_Base_SetConfig+0x124>)
+ 8001728: 4293 cmp r3, r2
+ 800172a: d108 bne.n 800173e <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 80016c0: 68fb ldr r3, [r7, #12]
- 80016c2: f023 0370 bic.w r3, r3, #112 ; 0x70
- 80016c6: 60fb str r3, [r7, #12]
+ 800172c: 68fb ldr r3, [r7, #12]
+ 800172e: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 8001732: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
- 80016c8: 683b ldr r3, [r7, #0]
- 80016ca: 685b ldr r3, [r3, #4]
- 80016cc: 68fa ldr r2, [r7, #12]
- 80016ce: 4313 orrs r3, r2
- 80016d0: 60fb str r3, [r7, #12]
+ 8001734: 683b ldr r3, [r7, #0]
+ 8001736: 685b ldr r3, [r3, #4]
+ 8001738: 68fa ldr r2, [r7, #12]
+ 800173a: 4313 orrs r3, r2
+ 800173c: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 80016d2: 687b ldr r3, [r7, #4]
- 80016d4: 4a2f ldr r2, [pc, #188] ; (8001794 <TIM_Base_SetConfig+0x114>)
- 80016d6: 4293 cmp r3, r2
- 80016d8: d02b beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 80016da: 687b ldr r3, [r7, #4]
- 80016dc: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
- 80016e0: d027 beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 80016e2: 687b ldr r3, [r7, #4]
- 80016e4: 4a2c ldr r2, [pc, #176] ; (8001798 <TIM_Base_SetConfig+0x118>)
- 80016e6: 4293 cmp r3, r2
- 80016e8: d023 beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 80016ea: 687b ldr r3, [r7, #4]
- 80016ec: 4a2b ldr r2, [pc, #172] ; (800179c <TIM_Base_SetConfig+0x11c>)
- 80016ee: 4293 cmp r3, r2
- 80016f0: d01f beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 80016f2: 687b ldr r3, [r7, #4]
- 80016f4: 4a2a ldr r2, [pc, #168] ; (80017a0 <TIM_Base_SetConfig+0x120>)
- 80016f6: 4293 cmp r3, r2
- 80016f8: d01b beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 80016fa: 687b ldr r3, [r7, #4]
- 80016fc: 4a29 ldr r2, [pc, #164] ; (80017a4 <TIM_Base_SetConfig+0x124>)
- 80016fe: 4293 cmp r3, r2
- 8001700: d017 beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 8001702: 687b ldr r3, [r7, #4]
- 8001704: 4a28 ldr r2, [pc, #160] ; (80017a8 <TIM_Base_SetConfig+0x128>)
- 8001706: 4293 cmp r3, r2
- 8001708: d013 beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 800170a: 687b ldr r3, [r7, #4]
- 800170c: 4a27 ldr r2, [pc, #156] ; (80017ac <TIM_Base_SetConfig+0x12c>)
- 800170e: 4293 cmp r3, r2
- 8001710: d00f beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 8001712: 687b ldr r3, [r7, #4]
- 8001714: 4a26 ldr r2, [pc, #152] ; (80017b0 <TIM_Base_SetConfig+0x130>)
- 8001716: 4293 cmp r3, r2
- 8001718: d00b beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 800171a: 687b ldr r3, [r7, #4]
- 800171c: 4a25 ldr r2, [pc, #148] ; (80017b4 <TIM_Base_SetConfig+0x134>)
- 800171e: 4293 cmp r3, r2
- 8001720: d007 beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 8001722: 687b ldr r3, [r7, #4]
- 8001724: 4a24 ldr r2, [pc, #144] ; (80017b8 <TIM_Base_SetConfig+0x138>)
- 8001726: 4293 cmp r3, r2
- 8001728: d003 beq.n 8001732 <TIM_Base_SetConfig+0xb2>
- 800172a: 687b ldr r3, [r7, #4]
- 800172c: 4a23 ldr r2, [pc, #140] ; (80017bc <TIM_Base_SetConfig+0x13c>)
- 800172e: 4293 cmp r3, r2
- 8001730: d108 bne.n 8001744 <TIM_Base_SetConfig+0xc4>
+ 800173e: 687b ldr r3, [r7, #4]
+ 8001740: 4a2f ldr r2, [pc, #188] ; (8001800 <TIM_Base_SetConfig+0x114>)
+ 8001742: 4293 cmp r3, r2
+ 8001744: d02b beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 8001746: 687b ldr r3, [r7, #4]
+ 8001748: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
+ 800174c: d027 beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 800174e: 687b ldr r3, [r7, #4]
+ 8001750: 4a2c ldr r2, [pc, #176] ; (8001804 <TIM_Base_SetConfig+0x118>)
+ 8001752: 4293 cmp r3, r2
+ 8001754: d023 beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 8001756: 687b ldr r3, [r7, #4]
+ 8001758: 4a2b ldr r2, [pc, #172] ; (8001808 <TIM_Base_SetConfig+0x11c>)
+ 800175a: 4293 cmp r3, r2
+ 800175c: d01f beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 800175e: 687b ldr r3, [r7, #4]
+ 8001760: 4a2a ldr r2, [pc, #168] ; (800180c <TIM_Base_SetConfig+0x120>)
+ 8001762: 4293 cmp r3, r2
+ 8001764: d01b beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 8001766: 687b ldr r3, [r7, #4]
+ 8001768: 4a29 ldr r2, [pc, #164] ; (8001810 <TIM_Base_SetConfig+0x124>)
+ 800176a: 4293 cmp r3, r2
+ 800176c: d017 beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 800176e: 687b ldr r3, [r7, #4]
+ 8001770: 4a28 ldr r2, [pc, #160] ; (8001814 <TIM_Base_SetConfig+0x128>)
+ 8001772: 4293 cmp r3, r2
+ 8001774: d013 beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 8001776: 687b ldr r3, [r7, #4]
+ 8001778: 4a27 ldr r2, [pc, #156] ; (8001818 <TIM_Base_SetConfig+0x12c>)
+ 800177a: 4293 cmp r3, r2
+ 800177c: d00f beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 800177e: 687b ldr r3, [r7, #4]
+ 8001780: 4a26 ldr r2, [pc, #152] ; (800181c <TIM_Base_SetConfig+0x130>)
+ 8001782: 4293 cmp r3, r2
+ 8001784: d00b beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 8001786: 687b ldr r3, [r7, #4]
+ 8001788: 4a25 ldr r2, [pc, #148] ; (8001820 <TIM_Base_SetConfig+0x134>)
+ 800178a: 4293 cmp r3, r2
+ 800178c: d007 beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 800178e: 687b ldr r3, [r7, #4]
+ 8001790: 4a24 ldr r2, [pc, #144] ; (8001824 <TIM_Base_SetConfig+0x138>)
+ 8001792: 4293 cmp r3, r2
+ 8001794: d003 beq.n 800179e <TIM_Base_SetConfig+0xb2>
+ 8001796: 687b ldr r3, [r7, #4]
+ 8001798: 4a23 ldr r2, [pc, #140] ; (8001828 <TIM_Base_SetConfig+0x13c>)
+ 800179a: 4293 cmp r3, r2
+ 800179c: d108 bne.n 80017b0 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
- 8001732: 68fb ldr r3, [r7, #12]
- 8001734: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8001738: 60fb str r3, [r7, #12]
+ 800179e: 68fb ldr r3, [r7, #12]
+ 80017a0: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 80017a4: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 800173a: 683b ldr r3, [r7, #0]
- 800173c: 68db ldr r3, [r3, #12]
- 800173e: 68fa ldr r2, [r7, #12]
- 8001740: 4313 orrs r3, r2
- 8001742: 60fb str r3, [r7, #12]
+ 80017a6: 683b ldr r3, [r7, #0]
+ 80017a8: 68db ldr r3, [r3, #12]
+ 80017aa: 68fa ldr r2, [r7, #12]
+ 80017ac: 4313 orrs r3, r2
+ 80017ae: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8001744: 68fb ldr r3, [r7, #12]
- 8001746: f023 0280 bic.w r2, r3, #128 ; 0x80
- 800174a: 683b ldr r3, [r7, #0]
- 800174c: 695b ldr r3, [r3, #20]
- 800174e: 4313 orrs r3, r2
- 8001750: 60fb str r3, [r7, #12]
+ 80017b0: 68fb ldr r3, [r7, #12]
+ 80017b2: f023 0280 bic.w r2, r3, #128 ; 0x80
+ 80017b6: 683b ldr r3, [r7, #0]
+ 80017b8: 695b ldr r3, [r3, #20]
+ 80017ba: 4313 orrs r3, r2
+ 80017bc: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
- 8001752: 687b ldr r3, [r7, #4]
- 8001754: 68fa ldr r2, [r7, #12]
- 8001756: 601a str r2, [r3, #0]
+ 80017be: 687b ldr r3, [r7, #4]
+ 80017c0: 68fa ldr r2, [r7, #12]
+ 80017c2: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
- 8001758: 683b ldr r3, [r7, #0]
- 800175a: 689a ldr r2, [r3, #8]
- 800175c: 687b ldr r3, [r7, #4]
- 800175e: 62da str r2, [r3, #44] ; 0x2c
+ 80017c4: 683b ldr r3, [r7, #0]
+ 80017c6: 689a ldr r2, [r3, #8]
+ 80017c8: 687b ldr r3, [r7, #4]
+ 80017ca: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
- 8001760: 683b ldr r3, [r7, #0]
- 8001762: 681a ldr r2, [r3, #0]
- 8001764: 687b ldr r3, [r7, #4]
- 8001766: 629a str r2, [r3, #40] ; 0x28
+ 80017cc: 683b ldr r3, [r7, #0]
+ 80017ce: 681a ldr r2, [r3, #0]
+ 80017d0: 687b ldr r3, [r7, #4]
+ 80017d2: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 8001768: 687b ldr r3, [r7, #4]
- 800176a: 4a0a ldr r2, [pc, #40] ; (8001794 <TIM_Base_SetConfig+0x114>)
- 800176c: 4293 cmp r3, r2
- 800176e: d003 beq.n 8001778 <TIM_Base_SetConfig+0xf8>
- 8001770: 687b ldr r3, [r7, #4]
- 8001772: 4a0c ldr r2, [pc, #48] ; (80017a4 <TIM_Base_SetConfig+0x124>)
- 8001774: 4293 cmp r3, r2
- 8001776: d103 bne.n 8001780 <TIM_Base_SetConfig+0x100>
+ 80017d4: 687b ldr r3, [r7, #4]
+ 80017d6: 4a0a ldr r2, [pc, #40] ; (8001800 <TIM_Base_SetConfig+0x114>)
+ 80017d8: 4293 cmp r3, r2
+ 80017da: d003 beq.n 80017e4 <TIM_Base_SetConfig+0xf8>
+ 80017dc: 687b ldr r3, [r7, #4]
+ 80017de: 4a0c ldr r2, [pc, #48] ; (8001810 <TIM_Base_SetConfig+0x124>)
+ 80017e0: 4293 cmp r3, r2
+ 80017e2: d103 bne.n 80017ec <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
- 8001778: 683b ldr r3, [r7, #0]
- 800177a: 691a ldr r2, [r3, #16]
- 800177c: 687b ldr r3, [r7, #4]
- 800177e: 631a str r2, [r3, #48] ; 0x30
+ 80017e4: 683b ldr r3, [r7, #0]
+ 80017e6: 691a ldr r2, [r3, #16]
+ 80017e8: 687b ldr r3, [r7, #4]
+ 80017ea: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
- 8001780: 687b ldr r3, [r7, #4]
- 8001782: 2201 movs r2, #1
- 8001784: 615a str r2, [r3, #20]
+ 80017ec: 687b ldr r3, [r7, #4]
+ 80017ee: 2201 movs r2, #1
+ 80017f0: 615a str r2, [r3, #20]
}
- 8001786: bf00 nop
- 8001788: 3714 adds r7, #20
- 800178a: 46bd mov sp, r7
- 800178c: f85d 7b04 ldr.w r7, [sp], #4
- 8001790: 4770 bx lr
- 8001792: bf00 nop
- 8001794: 40010000 .word 0x40010000
- 8001798: 40000400 .word 0x40000400
- 800179c: 40000800 .word 0x40000800
- 80017a0: 40000c00 .word 0x40000c00
- 80017a4: 40010400 .word 0x40010400
- 80017a8: 40014000 .word 0x40014000
- 80017ac: 40014400 .word 0x40014400
- 80017b0: 40014800 .word 0x40014800
- 80017b4: 40001800 .word 0x40001800
- 80017b8: 40001c00 .word 0x40001c00
- 80017bc: 40002000 .word 0x40002000
-
-080017c0 <TIM_OC1_SetConfig>:
+ 80017f2: bf00 nop
+ 80017f4: 3714 adds r7, #20
+ 80017f6: 46bd mov sp, r7
+ 80017f8: f85d 7b04 ldr.w r7, [sp], #4
+ 80017fc: 4770 bx lr
+ 80017fe: bf00 nop
+ 8001800: 40010000 .word 0x40010000
+ 8001804: 40000400 .word 0x40000400
+ 8001808: 40000800 .word 0x40000800
+ 800180c: 40000c00 .word 0x40000c00
+ 8001810: 40010400 .word 0x40010400
+ 8001814: 40014000 .word 0x40014000
+ 8001818: 40014400 .word 0x40014400
+ 800181c: 40014800 .word 0x40014800
+ 8001820: 40001800 .word 0x40001800
+ 8001824: 40001c00 .word 0x40001c00
+ 8001828: 40002000 .word 0x40002000
+
+0800182c <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 80017c0: b480 push {r7}
- 80017c2: b087 sub sp, #28
- 80017c4: af00 add r7, sp, #0
- 80017c6: 6078 str r0, [r7, #4]
- 80017c8: 6039 str r1, [r7, #0]
+ 800182c: b480 push {r7}
+ 800182e: b087 sub sp, #28
+ 8001830: af00 add r7, sp, #0
+ 8001832: 6078 str r0, [r7, #4]
+ 8001834: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
- 80017ca: 687b ldr r3, [r7, #4]
- 80017cc: 6a1b ldr r3, [r3, #32]
- 80017ce: f023 0201 bic.w r2, r3, #1
- 80017d2: 687b ldr r3, [r7, #4]
- 80017d4: 621a str r2, [r3, #32]
+ 8001836: 687b ldr r3, [r7, #4]
+ 8001838: 6a1b ldr r3, [r3, #32]
+ 800183a: f023 0201 bic.w r2, r3, #1
+ 800183e: 687b ldr r3, [r7, #4]
+ 8001840: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 80017d6: 687b ldr r3, [r7, #4]
- 80017d8: 6a1b ldr r3, [r3, #32]
- 80017da: 617b str r3, [r7, #20]
+ 8001842: 687b ldr r3, [r7, #4]
+ 8001844: 6a1b ldr r3, [r3, #32]
+ 8001846: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 80017dc: 687b ldr r3, [r7, #4]
- 80017de: 685b ldr r3, [r3, #4]
- 80017e0: 613b str r3, [r7, #16]
+ 8001848: 687b ldr r3, [r7, #4]
+ 800184a: 685b ldr r3, [r3, #4]
+ 800184c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- 80017e2: 687b ldr r3, [r7, #4]
- 80017e4: 699b ldr r3, [r3, #24]
- 80017e6: 60fb str r3, [r7, #12]
+ 800184e: 687b ldr r3, [r7, #4]
+ 8001850: 699b ldr r3, [r3, #24]
+ 8001852: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
- 80017e8: 68fa ldr r2, [r7, #12]
- 80017ea: 4b2b ldr r3, [pc, #172] ; (8001898 <TIM_OC1_SetConfig+0xd8>)
- 80017ec: 4013 ands r3, r2
- 80017ee: 60fb str r3, [r7, #12]
+ 8001854: 68fa ldr r2, [r7, #12]
+ 8001856: 4b2b ldr r3, [pc, #172] ; (8001904 <TIM_OC1_SetConfig+0xd8>)
+ 8001858: 4013 ands r3, r2
+ 800185a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
- 80017f0: 68fb ldr r3, [r7, #12]
- 80017f2: f023 0303 bic.w r3, r3, #3
- 80017f6: 60fb str r3, [r7, #12]
+ 800185c: 68fb ldr r3, [r7, #12]
+ 800185e: f023 0303 bic.w r3, r3, #3
+ 8001862: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 80017f8: 683b ldr r3, [r7, #0]
- 80017fa: 681b ldr r3, [r3, #0]
- 80017fc: 68fa ldr r2, [r7, #12]
- 80017fe: 4313 orrs r3, r2
- 8001800: 60fb str r3, [r7, #12]
+ 8001864: 683b ldr r3, [r7, #0]
+ 8001866: 681b ldr r3, [r3, #0]
+ 8001868: 68fa ldr r2, [r7, #12]
+ 800186a: 4313 orrs r3, r2
+ 800186c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
- 8001802: 697b ldr r3, [r7, #20]
- 8001804: f023 0302 bic.w r3, r3, #2
- 8001808: 617b str r3, [r7, #20]
+ 800186e: 697b ldr r3, [r7, #20]
+ 8001870: f023 0302 bic.w r3, r3, #2
+ 8001874: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
- 800180a: 683b ldr r3, [r7, #0]
- 800180c: 689b ldr r3, [r3, #8]
- 800180e: 697a ldr r2, [r7, #20]
- 8001810: 4313 orrs r3, r2
- 8001812: 617b str r3, [r7, #20]
+ 8001876: 683b ldr r3, [r7, #0]
+ 8001878: 689b ldr r3, [r3, #8]
+ 800187a: 697a ldr r2, [r7, #20]
+ 800187c: 4313 orrs r3, r2
+ 800187e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- 8001814: 687b ldr r3, [r7, #4]
- 8001816: 4a21 ldr r2, [pc, #132] ; (800189c <TIM_OC1_SetConfig+0xdc>)
- 8001818: 4293 cmp r3, r2
- 800181a: d003 beq.n 8001824 <TIM_OC1_SetConfig+0x64>
- 800181c: 687b ldr r3, [r7, #4]
- 800181e: 4a20 ldr r2, [pc, #128] ; (80018a0 <TIM_OC1_SetConfig+0xe0>)
- 8001820: 4293 cmp r3, r2
- 8001822: d10c bne.n 800183e <TIM_OC1_SetConfig+0x7e>
+ 8001880: 687b ldr r3, [r7, #4]
+ 8001882: 4a21 ldr r2, [pc, #132] ; (8001908 <TIM_OC1_SetConfig+0xdc>)
+ 8001884: 4293 cmp r3, r2
+ 8001886: d003 beq.n 8001890 <TIM_OC1_SetConfig+0x64>
+ 8001888: 687b ldr r3, [r7, #4]
+ 800188a: 4a20 ldr r2, [pc, #128] ; (800190c <TIM_OC1_SetConfig+0xe0>)
+ 800188c: 4293 cmp r3, r2
+ 800188e: d10c bne.n 80018aa <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
- 8001824: 697b ldr r3, [r7, #20]
- 8001826: f023 0308 bic.w r3, r3, #8
- 800182a: 617b str r3, [r7, #20]
+ 8001890: 697b ldr r3, [r7, #20]
+ 8001892: f023 0308 bic.w r3, r3, #8
+ 8001896: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
- 800182c: 683b ldr r3, [r7, #0]
- 800182e: 68db ldr r3, [r3, #12]
- 8001830: 697a ldr r2, [r7, #20]
- 8001832: 4313 orrs r3, r2
- 8001834: 617b str r3, [r7, #20]
+ 8001898: 683b ldr r3, [r7, #0]
+ 800189a: 68db ldr r3, [r3, #12]
+ 800189c: 697a ldr r2, [r7, #20]
+ 800189e: 4313 orrs r3, r2
+ 80018a0: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
- 8001836: 697b ldr r3, [r7, #20]
- 8001838: f023 0304 bic.w r3, r3, #4
- 800183c: 617b str r3, [r7, #20]
+ 80018a2: 697b ldr r3, [r7, #20]
+ 80018a4: f023 0304 bic.w r3, r3, #4
+ 80018a8: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 800183e: 687b ldr r3, [r7, #4]
- 8001840: 4a16 ldr r2, [pc, #88] ; (800189c <TIM_OC1_SetConfig+0xdc>)
- 8001842: 4293 cmp r3, r2
- 8001844: d003 beq.n 800184e <TIM_OC1_SetConfig+0x8e>
- 8001846: 687b ldr r3, [r7, #4]
- 8001848: 4a15 ldr r2, [pc, #84] ; (80018a0 <TIM_OC1_SetConfig+0xe0>)
- 800184a: 4293 cmp r3, r2
- 800184c: d111 bne.n 8001872 <TIM_OC1_SetConfig+0xb2>
+ 80018aa: 687b ldr r3, [r7, #4]
+ 80018ac: 4a16 ldr r2, [pc, #88] ; (8001908 <TIM_OC1_SetConfig+0xdc>)
+ 80018ae: 4293 cmp r3, r2
+ 80018b0: d003 beq.n 80018ba <TIM_OC1_SetConfig+0x8e>
+ 80018b2: 687b ldr r3, [r7, #4]
+ 80018b4: 4a15 ldr r2, [pc, #84] ; (800190c <TIM_OC1_SetConfig+0xe0>)
+ 80018b6: 4293 cmp r3, r2
+ 80018b8: d111 bne.n 80018de <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
- 800184e: 693b ldr r3, [r7, #16]
- 8001850: f423 7380 bic.w r3, r3, #256 ; 0x100
- 8001854: 613b str r3, [r7, #16]
+ 80018ba: 693b ldr r3, [r7, #16]
+ 80018bc: f423 7380 bic.w r3, r3, #256 ; 0x100
+ 80018c0: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
- 8001856: 693b ldr r3, [r7, #16]
- 8001858: f423 7300 bic.w r3, r3, #512 ; 0x200
- 800185c: 613b str r3, [r7, #16]
+ 80018c2: 693b ldr r3, [r7, #16]
+ 80018c4: f423 7300 bic.w r3, r3, #512 ; 0x200
+ 80018c8: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
- 800185e: 683b ldr r3, [r7, #0]
- 8001860: 695b ldr r3, [r3, #20]
- 8001862: 693a ldr r2, [r7, #16]
- 8001864: 4313 orrs r3, r2
- 8001866: 613b str r3, [r7, #16]
+ 80018ca: 683b ldr r3, [r7, #0]
+ 80018cc: 695b ldr r3, [r3, #20]
+ 80018ce: 693a ldr r2, [r7, #16]
+ 80018d0: 4313 orrs r3, r2
+ 80018d2: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
- 8001868: 683b ldr r3, [r7, #0]
- 800186a: 699b ldr r3, [r3, #24]
- 800186c: 693a ldr r2, [r7, #16]
- 800186e: 4313 orrs r3, r2
- 8001870: 613b str r3, [r7, #16]
+ 80018d4: 683b ldr r3, [r7, #0]
+ 80018d6: 699b ldr r3, [r3, #24]
+ 80018d8: 693a ldr r2, [r7, #16]
+ 80018da: 4313 orrs r3, r2
+ 80018dc: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8001872: 687b ldr r3, [r7, #4]
- 8001874: 693a ldr r2, [r7, #16]
- 8001876: 605a str r2, [r3, #4]
+ 80018de: 687b ldr r3, [r7, #4]
+ 80018e0: 693a ldr r2, [r7, #16]
+ 80018e2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
- 8001878: 687b ldr r3, [r7, #4]
- 800187a: 68fa ldr r2, [r7, #12]
- 800187c: 619a str r2, [r3, #24]
+ 80018e4: 687b ldr r3, [r7, #4]
+ 80018e6: 68fa ldr r2, [r7, #12]
+ 80018e8: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
- 800187e: 683b ldr r3, [r7, #0]
- 8001880: 685a ldr r2, [r3, #4]
- 8001882: 687b ldr r3, [r7, #4]
- 8001884: 635a str r2, [r3, #52] ; 0x34
+ 80018ea: 683b ldr r3, [r7, #0]
+ 80018ec: 685a ldr r2, [r3, #4]
+ 80018ee: 687b ldr r3, [r7, #4]
+ 80018f0: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8001886: 687b ldr r3, [r7, #4]
- 8001888: 697a ldr r2, [r7, #20]
- 800188a: 621a str r2, [r3, #32]
+ 80018f2: 687b ldr r3, [r7, #4]
+ 80018f4: 697a ldr r2, [r7, #20]
+ 80018f6: 621a str r2, [r3, #32]
}
- 800188c: bf00 nop
- 800188e: 371c adds r7, #28
- 8001890: 46bd mov sp, r7
- 8001892: f85d 7b04 ldr.w r7, [sp], #4
- 8001896: 4770 bx lr
- 8001898: fffeff8f .word 0xfffeff8f
- 800189c: 40010000 .word 0x40010000
- 80018a0: 40010400 .word 0x40010400
-
-080018a4 <TIM_OC2_SetConfig>:
+ 80018f8: bf00 nop
+ 80018fa: 371c adds r7, #28
+ 80018fc: 46bd mov sp, r7
+ 80018fe: f85d 7b04 ldr.w r7, [sp], #4
+ 8001902: 4770 bx lr
+ 8001904: fffeff8f .word 0xfffeff8f
+ 8001908: 40010000 .word 0x40010000
+ 800190c: 40010400 .word 0x40010400
+
+08001910 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 80018a4: b480 push {r7}
- 80018a6: b087 sub sp, #28
- 80018a8: af00 add r7, sp, #0
- 80018aa: 6078 str r0, [r7, #4]
- 80018ac: 6039 str r1, [r7, #0]
+ 8001910: b480 push {r7}
+ 8001912: b087 sub sp, #28
+ 8001914: af00 add r7, sp, #0
+ 8001916: 6078 str r0, [r7, #4]
+ 8001918: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- 80018ae: 687b ldr r3, [r7, #4]
- 80018b0: 6a1b ldr r3, [r3, #32]
- 80018b2: f023 0210 bic.w r2, r3, #16
- 80018b6: 687b ldr r3, [r7, #4]
- 80018b8: 621a str r2, [r3, #32]
+ 800191a: 687b ldr r3, [r7, #4]
+ 800191c: 6a1b ldr r3, [r3, #32]
+ 800191e: f023 0210 bic.w r2, r3, #16
+ 8001922: 687b ldr r3, [r7, #4]
+ 8001924: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 80018ba: 687b ldr r3, [r7, #4]
- 80018bc: 6a1b ldr r3, [r3, #32]
- 80018be: 617b str r3, [r7, #20]
+ 8001926: 687b ldr r3, [r7, #4]
+ 8001928: 6a1b ldr r3, [r3, #32]
+ 800192a: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 80018c0: 687b ldr r3, [r7, #4]
- 80018c2: 685b ldr r3, [r3, #4]
- 80018c4: 613b str r3, [r7, #16]
+ 800192c: 687b ldr r3, [r7, #4]
+ 800192e: 685b ldr r3, [r3, #4]
+ 8001930: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- 80018c6: 687b ldr r3, [r7, #4]
- 80018c8: 699b ldr r3, [r3, #24]
- 80018ca: 60fb str r3, [r7, #12]
+ 8001932: 687b ldr r3, [r7, #4]
+ 8001934: 699b ldr r3, [r3, #24]
+ 8001936: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
- 80018cc: 68fa ldr r2, [r7, #12]
- 80018ce: 4b2e ldr r3, [pc, #184] ; (8001988 <TIM_OC2_SetConfig+0xe4>)
- 80018d0: 4013 ands r3, r2
- 80018d2: 60fb str r3, [r7, #12]
+ 8001938: 68fa ldr r2, [r7, #12]
+ 800193a: 4b2e ldr r3, [pc, #184] ; (80019f4 <TIM_OC2_SetConfig+0xe4>)
+ 800193c: 4013 ands r3, r2
+ 800193e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
- 80018d4: 68fb ldr r3, [r7, #12]
- 80018d6: f423 7340 bic.w r3, r3, #768 ; 0x300
- 80018da: 60fb str r3, [r7, #12]
+ 8001940: 68fb ldr r3, [r7, #12]
+ 8001942: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8001946: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 80018dc: 683b ldr r3, [r7, #0]
- 80018de: 681b ldr r3, [r3, #0]
- 80018e0: 021b lsls r3, r3, #8
- 80018e2: 68fa ldr r2, [r7, #12]
- 80018e4: 4313 orrs r3, r2
- 80018e6: 60fb str r3, [r7, #12]
+ 8001948: 683b ldr r3, [r7, #0]
+ 800194a: 681b ldr r3, [r3, #0]
+ 800194c: 021b lsls r3, r3, #8
+ 800194e: 68fa ldr r2, [r7, #12]
+ 8001950: 4313 orrs r3, r2
+ 8001952: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
- 80018e8: 697b ldr r3, [r7, #20]
- 80018ea: f023 0320 bic.w r3, r3, #32
- 80018ee: 617b str r3, [r7, #20]
+ 8001954: 697b ldr r3, [r7, #20]
+ 8001956: f023 0320 bic.w r3, r3, #32
+ 800195a: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
- 80018f0: 683b ldr r3, [r7, #0]
- 80018f2: 689b ldr r3, [r3, #8]
- 80018f4: 011b lsls r3, r3, #4
- 80018f6: 697a ldr r2, [r7, #20]
- 80018f8: 4313 orrs r3, r2
- 80018fa: 617b str r3, [r7, #20]
+ 800195c: 683b ldr r3, [r7, #0]
+ 800195e: 689b ldr r3, [r3, #8]
+ 8001960: 011b lsls r3, r3, #4
+ 8001962: 697a ldr r2, [r7, #20]
+ 8001964: 4313 orrs r3, r2
+ 8001966: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- 80018fc: 687b ldr r3, [r7, #4]
- 80018fe: 4a23 ldr r2, [pc, #140] ; (800198c <TIM_OC2_SetConfig+0xe8>)
- 8001900: 4293 cmp r3, r2
- 8001902: d003 beq.n 800190c <TIM_OC2_SetConfig+0x68>
- 8001904: 687b ldr r3, [r7, #4]
- 8001906: 4a22 ldr r2, [pc, #136] ; (8001990 <TIM_OC2_SetConfig+0xec>)
- 8001908: 4293 cmp r3, r2
- 800190a: d10d bne.n 8001928 <TIM_OC2_SetConfig+0x84>
+ 8001968: 687b ldr r3, [r7, #4]
+ 800196a: 4a23 ldr r2, [pc, #140] ; (80019f8 <TIM_OC2_SetConfig+0xe8>)
+ 800196c: 4293 cmp r3, r2
+ 800196e: d003 beq.n 8001978 <TIM_OC2_SetConfig+0x68>
+ 8001970: 687b ldr r3, [r7, #4]
+ 8001972: 4a22 ldr r2, [pc, #136] ; (80019fc <TIM_OC2_SetConfig+0xec>)
+ 8001974: 4293 cmp r3, r2
+ 8001976: d10d bne.n 8001994 <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
- 800190c: 697b ldr r3, [r7, #20]
- 800190e: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8001912: 617b str r3, [r7, #20]
+ 8001978: 697b ldr r3, [r7, #20]
+ 800197a: f023 0380 bic.w r3, r3, #128 ; 0x80
+ 800197e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
- 8001914: 683b ldr r3, [r7, #0]
- 8001916: 68db ldr r3, [r3, #12]
- 8001918: 011b lsls r3, r3, #4
- 800191a: 697a ldr r2, [r7, #20]
- 800191c: 4313 orrs r3, r2
- 800191e: 617b str r3, [r7, #20]
+ 8001980: 683b ldr r3, [r7, #0]
+ 8001982: 68db ldr r3, [r3, #12]
+ 8001984: 011b lsls r3, r3, #4
+ 8001986: 697a ldr r2, [r7, #20]
+ 8001988: 4313 orrs r3, r2
+ 800198a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
- 8001920: 697b ldr r3, [r7, #20]
- 8001922: f023 0340 bic.w r3, r3, #64 ; 0x40
- 8001926: 617b str r3, [r7, #20]
+ 800198c: 697b ldr r3, [r7, #20]
+ 800198e: f023 0340 bic.w r3, r3, #64 ; 0x40
+ 8001992: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8001928: 687b ldr r3, [r7, #4]
- 800192a: 4a18 ldr r2, [pc, #96] ; (800198c <TIM_OC2_SetConfig+0xe8>)
- 800192c: 4293 cmp r3, r2
- 800192e: d003 beq.n 8001938 <TIM_OC2_SetConfig+0x94>
- 8001930: 687b ldr r3, [r7, #4]
- 8001932: 4a17 ldr r2, [pc, #92] ; (8001990 <TIM_OC2_SetConfig+0xec>)
- 8001934: 4293 cmp r3, r2
- 8001936: d113 bne.n 8001960 <TIM_OC2_SetConfig+0xbc>
+ 8001994: 687b ldr r3, [r7, #4]
+ 8001996: 4a18 ldr r2, [pc, #96] ; (80019f8 <TIM_OC2_SetConfig+0xe8>)
+ 8001998: 4293 cmp r3, r2
+ 800199a: d003 beq.n 80019a4 <TIM_OC2_SetConfig+0x94>
+ 800199c: 687b ldr r3, [r7, #4]
+ 800199e: 4a17 ldr r2, [pc, #92] ; (80019fc <TIM_OC2_SetConfig+0xec>)
+ 80019a0: 4293 cmp r3, r2
+ 80019a2: d113 bne.n 80019cc <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
- 8001938: 693b ldr r3, [r7, #16]
- 800193a: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 800193e: 613b str r3, [r7, #16]
+ 80019a4: 693b ldr r3, [r7, #16]
+ 80019a6: f423 6380 bic.w r3, r3, #1024 ; 0x400
+ 80019aa: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
- 8001940: 693b ldr r3, [r7, #16]
- 8001942: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8001946: 613b str r3, [r7, #16]
+ 80019ac: 693b ldr r3, [r7, #16]
+ 80019ae: f423 6300 bic.w r3, r3, #2048 ; 0x800
+ 80019b2: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
- 8001948: 683b ldr r3, [r7, #0]
- 800194a: 695b ldr r3, [r3, #20]
- 800194c: 009b lsls r3, r3, #2
- 800194e: 693a ldr r2, [r7, #16]
- 8001950: 4313 orrs r3, r2
- 8001952: 613b str r3, [r7, #16]
+ 80019b4: 683b ldr r3, [r7, #0]
+ 80019b6: 695b ldr r3, [r3, #20]
+ 80019b8: 009b lsls r3, r3, #2
+ 80019ba: 693a ldr r2, [r7, #16]
+ 80019bc: 4313 orrs r3, r2
+ 80019be: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- 8001954: 683b ldr r3, [r7, #0]
- 8001956: 699b ldr r3, [r3, #24]
- 8001958: 009b lsls r3, r3, #2
- 800195a: 693a ldr r2, [r7, #16]
- 800195c: 4313 orrs r3, r2
- 800195e: 613b str r3, [r7, #16]
+ 80019c0: 683b ldr r3, [r7, #0]
+ 80019c2: 699b ldr r3, [r3, #24]
+ 80019c4: 009b lsls r3, r3, #2
+ 80019c6: 693a ldr r2, [r7, #16]
+ 80019c8: 4313 orrs r3, r2
+ 80019ca: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8001960: 687b ldr r3, [r7, #4]
- 8001962: 693a ldr r2, [r7, #16]
- 8001964: 605a str r2, [r3, #4]
+ 80019cc: 687b ldr r3, [r7, #4]
+ 80019ce: 693a ldr r2, [r7, #16]
+ 80019d0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
- 8001966: 687b ldr r3, [r7, #4]
- 8001968: 68fa ldr r2, [r7, #12]
- 800196a: 619a str r2, [r3, #24]
+ 80019d2: 687b ldr r3, [r7, #4]
+ 80019d4: 68fa ldr r2, [r7, #12]
+ 80019d6: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
- 800196c: 683b ldr r3, [r7, #0]
- 800196e: 685a ldr r2, [r3, #4]
- 8001970: 687b ldr r3, [r7, #4]
- 8001972: 639a str r2, [r3, #56] ; 0x38
+ 80019d8: 683b ldr r3, [r7, #0]
+ 80019da: 685a ldr r2, [r3, #4]
+ 80019dc: 687b ldr r3, [r7, #4]
+ 80019de: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8001974: 687b ldr r3, [r7, #4]
- 8001976: 697a ldr r2, [r7, #20]
- 8001978: 621a str r2, [r3, #32]
+ 80019e0: 687b ldr r3, [r7, #4]
+ 80019e2: 697a ldr r2, [r7, #20]
+ 80019e4: 621a str r2, [r3, #32]
}
- 800197a: bf00 nop
- 800197c: 371c adds r7, #28
- 800197e: 46bd mov sp, r7
- 8001980: f85d 7b04 ldr.w r7, [sp], #4
- 8001984: 4770 bx lr
- 8001986: bf00 nop
- 8001988: feff8fff .word 0xfeff8fff
- 800198c: 40010000 .word 0x40010000
- 8001990: 40010400 .word 0x40010400
-
-08001994 <TIM_OC3_SetConfig>:
+ 80019e6: bf00 nop
+ 80019e8: 371c adds r7, #28
+ 80019ea: 46bd mov sp, r7
+ 80019ec: f85d 7b04 ldr.w r7, [sp], #4
+ 80019f0: 4770 bx lr
+ 80019f2: bf00 nop
+ 80019f4: feff8fff .word 0xfeff8fff
+ 80019f8: 40010000 .word 0x40010000
+ 80019fc: 40010400 .word 0x40010400
+
+08001a00 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8001994: b480 push {r7}
- 8001996: b087 sub sp, #28
- 8001998: af00 add r7, sp, #0
- 800199a: 6078 str r0, [r7, #4]
- 800199c: 6039 str r1, [r7, #0]
+ 8001a00: b480 push {r7}
+ 8001a02: b087 sub sp, #28
+ 8001a04: af00 add r7, sp, #0
+ 8001a06: 6078 str r0, [r7, #4]
+ 8001a08: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
- 800199e: 687b ldr r3, [r7, #4]
- 80019a0: 6a1b ldr r3, [r3, #32]
- 80019a2: f423 7280 bic.w r2, r3, #256 ; 0x100
- 80019a6: 687b ldr r3, [r7, #4]
- 80019a8: 621a str r2, [r3, #32]
+ 8001a0a: 687b ldr r3, [r7, #4]
+ 8001a0c: 6a1b ldr r3, [r3, #32]
+ 8001a0e: f423 7280 bic.w r2, r3, #256 ; 0x100
+ 8001a12: 687b ldr r3, [r7, #4]
+ 8001a14: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 80019aa: 687b ldr r3, [r7, #4]
- 80019ac: 6a1b ldr r3, [r3, #32]
- 80019ae: 617b str r3, [r7, #20]
+ 8001a16: 687b ldr r3, [r7, #4]
+ 8001a18: 6a1b ldr r3, [r3, #32]
+ 8001a1a: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 80019b0: 687b ldr r3, [r7, #4]
- 80019b2: 685b ldr r3, [r3, #4]
- 80019b4: 613b str r3, [r7, #16]
+ 8001a1c: 687b ldr r3, [r7, #4]
+ 8001a1e: 685b ldr r3, [r3, #4]
+ 8001a20: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
- 80019b6: 687b ldr r3, [r7, #4]
- 80019b8: 69db ldr r3, [r3, #28]
- 80019ba: 60fb str r3, [r7, #12]
+ 8001a22: 687b ldr r3, [r7, #4]
+ 8001a24: 69db ldr r3, [r3, #28]
+ 8001a26: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
- 80019bc: 68fa ldr r2, [r7, #12]
- 80019be: 4b2d ldr r3, [pc, #180] ; (8001a74 <TIM_OC3_SetConfig+0xe0>)
- 80019c0: 4013 ands r3, r2
- 80019c2: 60fb str r3, [r7, #12]
+ 8001a28: 68fa ldr r2, [r7, #12]
+ 8001a2a: 4b2d ldr r3, [pc, #180] ; (8001ae0 <TIM_OC3_SetConfig+0xe0>)
+ 8001a2c: 4013 ands r3, r2
+ 8001a2e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
- 80019c4: 68fb ldr r3, [r7, #12]
- 80019c6: f023 0303 bic.w r3, r3, #3
- 80019ca: 60fb str r3, [r7, #12]
+ 8001a30: 68fb ldr r3, [r7, #12]
+ 8001a32: f023 0303 bic.w r3, r3, #3
+ 8001a36: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 80019cc: 683b ldr r3, [r7, #0]
- 80019ce: 681b ldr r3, [r3, #0]
- 80019d0: 68fa ldr r2, [r7, #12]
- 80019d2: 4313 orrs r3, r2
- 80019d4: 60fb str r3, [r7, #12]
+ 8001a38: 683b ldr r3, [r7, #0]
+ 8001a3a: 681b ldr r3, [r3, #0]
+ 8001a3c: 68fa ldr r2, [r7, #12]
+ 8001a3e: 4313 orrs r3, r2
+ 8001a40: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
- 80019d6: 697b ldr r3, [r7, #20]
- 80019d8: f423 7300 bic.w r3, r3, #512 ; 0x200
- 80019dc: 617b str r3, [r7, #20]
+ 8001a42: 697b ldr r3, [r7, #20]
+ 8001a44: f423 7300 bic.w r3, r3, #512 ; 0x200
+ 8001a48: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
- 80019de: 683b ldr r3, [r7, #0]
- 80019e0: 689b ldr r3, [r3, #8]
- 80019e2: 021b lsls r3, r3, #8
- 80019e4: 697a ldr r2, [r7, #20]
- 80019e6: 4313 orrs r3, r2
- 80019e8: 617b str r3, [r7, #20]
+ 8001a4a: 683b ldr r3, [r7, #0]
+ 8001a4c: 689b ldr r3, [r3, #8]
+ 8001a4e: 021b lsls r3, r3, #8
+ 8001a50: 697a ldr r2, [r7, #20]
+ 8001a52: 4313 orrs r3, r2
+ 8001a54: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- 80019ea: 687b ldr r3, [r7, #4]
- 80019ec: 4a22 ldr r2, [pc, #136] ; (8001a78 <TIM_OC3_SetConfig+0xe4>)
- 80019ee: 4293 cmp r3, r2
- 80019f0: d003 beq.n 80019fa <TIM_OC3_SetConfig+0x66>
- 80019f2: 687b ldr r3, [r7, #4]
- 80019f4: 4a21 ldr r2, [pc, #132] ; (8001a7c <TIM_OC3_SetConfig+0xe8>)
- 80019f6: 4293 cmp r3, r2
- 80019f8: d10d bne.n 8001a16 <TIM_OC3_SetConfig+0x82>
+ 8001a56: 687b ldr r3, [r7, #4]
+ 8001a58: 4a22 ldr r2, [pc, #136] ; (8001ae4 <TIM_OC3_SetConfig+0xe4>)
+ 8001a5a: 4293 cmp r3, r2
+ 8001a5c: d003 beq.n 8001a66 <TIM_OC3_SetConfig+0x66>
+ 8001a5e: 687b ldr r3, [r7, #4]
+ 8001a60: 4a21 ldr r2, [pc, #132] ; (8001ae8 <TIM_OC3_SetConfig+0xe8>)
+ 8001a62: 4293 cmp r3, r2
+ 8001a64: d10d bne.n 8001a82 <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
- 80019fa: 697b ldr r3, [r7, #20]
- 80019fc: f423 6300 bic.w r3, r3, #2048 ; 0x800
- 8001a00: 617b str r3, [r7, #20]
+ 8001a66: 697b ldr r3, [r7, #20]
+ 8001a68: f423 6300 bic.w r3, r3, #2048 ; 0x800
+ 8001a6c: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
- 8001a02: 683b ldr r3, [r7, #0]
- 8001a04: 68db ldr r3, [r3, #12]
- 8001a06: 021b lsls r3, r3, #8
- 8001a08: 697a ldr r2, [r7, #20]
- 8001a0a: 4313 orrs r3, r2
- 8001a0c: 617b str r3, [r7, #20]
+ 8001a6e: 683b ldr r3, [r7, #0]
+ 8001a70: 68db ldr r3, [r3, #12]
+ 8001a72: 021b lsls r3, r3, #8
+ 8001a74: 697a ldr r2, [r7, #20]
+ 8001a76: 4313 orrs r3, r2
+ 8001a78: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
- 8001a0e: 697b ldr r3, [r7, #20]
- 8001a10: f423 6380 bic.w r3, r3, #1024 ; 0x400
- 8001a14: 617b str r3, [r7, #20]
+ 8001a7a: 697b ldr r3, [r7, #20]
+ 8001a7c: f423 6380 bic.w r3, r3, #1024 ; 0x400
+ 8001a80: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8001a16: 687b ldr r3, [r7, #4]
- 8001a18: 4a17 ldr r2, [pc, #92] ; (8001a78 <TIM_OC3_SetConfig+0xe4>)
- 8001a1a: 4293 cmp r3, r2
- 8001a1c: d003 beq.n 8001a26 <TIM_OC3_SetConfig+0x92>
- 8001a1e: 687b ldr r3, [r7, #4]
- 8001a20: 4a16 ldr r2, [pc, #88] ; (8001a7c <TIM_OC3_SetConfig+0xe8>)
- 8001a22: 4293 cmp r3, r2
- 8001a24: d113 bne.n 8001a4e <TIM_OC3_SetConfig+0xba>
+ 8001a82: 687b ldr r3, [r7, #4]
+ 8001a84: 4a17 ldr r2, [pc, #92] ; (8001ae4 <TIM_OC3_SetConfig+0xe4>)
+ 8001a86: 4293 cmp r3, r2
+ 8001a88: d003 beq.n 8001a92 <TIM_OC3_SetConfig+0x92>
+ 8001a8a: 687b ldr r3, [r7, #4]
+ 8001a8c: 4a16 ldr r2, [pc, #88] ; (8001ae8 <TIM_OC3_SetConfig+0xe8>)
+ 8001a8e: 4293 cmp r3, r2
+ 8001a90: d113 bne.n 8001aba <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
- 8001a26: 693b ldr r3, [r7, #16]
- 8001a28: f423 5380 bic.w r3, r3, #4096 ; 0x1000
- 8001a2c: 613b str r3, [r7, #16]
+ 8001a92: 693b ldr r3, [r7, #16]
+ 8001a94: f423 5380 bic.w r3, r3, #4096 ; 0x1000
+ 8001a98: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
- 8001a2e: 693b ldr r3, [r7, #16]
- 8001a30: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8001a34: 613b str r3, [r7, #16]
+ 8001a9a: 693b ldr r3, [r7, #16]
+ 8001a9c: f423 5300 bic.w r3, r3, #8192 ; 0x2000
+ 8001aa0: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
- 8001a36: 683b ldr r3, [r7, #0]
- 8001a38: 695b ldr r3, [r3, #20]
- 8001a3a: 011b lsls r3, r3, #4
- 8001a3c: 693a ldr r2, [r7, #16]
- 8001a3e: 4313 orrs r3, r2
- 8001a40: 613b str r3, [r7, #16]
+ 8001aa2: 683b ldr r3, [r7, #0]
+ 8001aa4: 695b ldr r3, [r3, #20]
+ 8001aa6: 011b lsls r3, r3, #4
+ 8001aa8: 693a ldr r2, [r7, #16]
+ 8001aaa: 4313 orrs r3, r2
+ 8001aac: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- 8001a42: 683b ldr r3, [r7, #0]
- 8001a44: 699b ldr r3, [r3, #24]
- 8001a46: 011b lsls r3, r3, #4
- 8001a48: 693a ldr r2, [r7, #16]
- 8001a4a: 4313 orrs r3, r2
- 8001a4c: 613b str r3, [r7, #16]
+ 8001aae: 683b ldr r3, [r7, #0]
+ 8001ab0: 699b ldr r3, [r3, #24]
+ 8001ab2: 011b lsls r3, r3, #4
+ 8001ab4: 693a ldr r2, [r7, #16]
+ 8001ab6: 4313 orrs r3, r2
+ 8001ab8: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8001a4e: 687b ldr r3, [r7, #4]
- 8001a50: 693a ldr r2, [r7, #16]
- 8001a52: 605a str r2, [r3, #4]
+ 8001aba: 687b ldr r3, [r7, #4]
+ 8001abc: 693a ldr r2, [r7, #16]
+ 8001abe: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
- 8001a54: 687b ldr r3, [r7, #4]
- 8001a56: 68fa ldr r2, [r7, #12]
- 8001a58: 61da str r2, [r3, #28]
+ 8001ac0: 687b ldr r3, [r7, #4]
+ 8001ac2: 68fa ldr r2, [r7, #12]
+ 8001ac4: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
- 8001a5a: 683b ldr r3, [r7, #0]
- 8001a5c: 685a ldr r2, [r3, #4]
- 8001a5e: 687b ldr r3, [r7, #4]
- 8001a60: 63da str r2, [r3, #60] ; 0x3c
+ 8001ac6: 683b ldr r3, [r7, #0]
+ 8001ac8: 685a ldr r2, [r3, #4]
+ 8001aca: 687b ldr r3, [r7, #4]
+ 8001acc: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8001a62: 687b ldr r3, [r7, #4]
- 8001a64: 697a ldr r2, [r7, #20]
- 8001a66: 621a str r2, [r3, #32]
+ 8001ace: 687b ldr r3, [r7, #4]
+ 8001ad0: 697a ldr r2, [r7, #20]
+ 8001ad2: 621a str r2, [r3, #32]
}
- 8001a68: bf00 nop
- 8001a6a: 371c adds r7, #28
- 8001a6c: 46bd mov sp, r7
- 8001a6e: f85d 7b04 ldr.w r7, [sp], #4
- 8001a72: 4770 bx lr
- 8001a74: fffeff8f .word 0xfffeff8f
- 8001a78: 40010000 .word 0x40010000
- 8001a7c: 40010400 .word 0x40010400
-
-08001a80 <TIM_OC4_SetConfig>:
+ 8001ad4: bf00 nop
+ 8001ad6: 371c adds r7, #28
+ 8001ad8: 46bd mov sp, r7
+ 8001ada: f85d 7b04 ldr.w r7, [sp], #4
+ 8001ade: 4770 bx lr
+ 8001ae0: fffeff8f .word 0xfffeff8f
+ 8001ae4: 40010000 .word 0x40010000
+ 8001ae8: 40010400 .word 0x40010400
+
+08001aec <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8001a80: b480 push {r7}
- 8001a82: b087 sub sp, #28
- 8001a84: af00 add r7, sp, #0
- 8001a86: 6078 str r0, [r7, #4]
- 8001a88: 6039 str r1, [r7, #0]
+ 8001aec: b480 push {r7}
+ 8001aee: b087 sub sp, #28
+ 8001af0: af00 add r7, sp, #0
+ 8001af2: 6078 str r0, [r7, #4]
+ 8001af4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
- 8001a8a: 687b ldr r3, [r7, #4]
- 8001a8c: 6a1b ldr r3, [r3, #32]
- 8001a8e: f423 5280 bic.w r2, r3, #4096 ; 0x1000
- 8001a92: 687b ldr r3, [r7, #4]
- 8001a94: 621a str r2, [r3, #32]
+ 8001af6: 687b ldr r3, [r7, #4]
+ 8001af8: 6a1b ldr r3, [r3, #32]
+ 8001afa: f423 5280 bic.w r2, r3, #4096 ; 0x1000
+ 8001afe: 687b ldr r3, [r7, #4]
+ 8001b00: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8001a96: 687b ldr r3, [r7, #4]
- 8001a98: 6a1b ldr r3, [r3, #32]
- 8001a9a: 613b str r3, [r7, #16]
+ 8001b02: 687b ldr r3, [r7, #4]
+ 8001b04: 6a1b ldr r3, [r3, #32]
+ 8001b06: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8001a9c: 687b ldr r3, [r7, #4]
- 8001a9e: 685b ldr r3, [r3, #4]
- 8001aa0: 617b str r3, [r7, #20]
+ 8001b08: 687b ldr r3, [r7, #4]
+ 8001b0a: 685b ldr r3, [r3, #4]
+ 8001b0c: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
- 8001aa2: 687b ldr r3, [r7, #4]
- 8001aa4: 69db ldr r3, [r3, #28]
- 8001aa6: 60fb str r3, [r7, #12]
+ 8001b0e: 687b ldr r3, [r7, #4]
+ 8001b10: 69db ldr r3, [r3, #28]
+ 8001b12: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
- 8001aa8: 68fa ldr r2, [r7, #12]
- 8001aaa: 4b1e ldr r3, [pc, #120] ; (8001b24 <TIM_OC4_SetConfig+0xa4>)
- 8001aac: 4013 ands r3, r2
- 8001aae: 60fb str r3, [r7, #12]
+ 8001b14: 68fa ldr r2, [r7, #12]
+ 8001b16: 4b1e ldr r3, [pc, #120] ; (8001b90 <TIM_OC4_SetConfig+0xa4>)
+ 8001b18: 4013 ands r3, r2
+ 8001b1a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
- 8001ab0: 68fb ldr r3, [r7, #12]
- 8001ab2: f423 7340 bic.w r3, r3, #768 ; 0x300
- 8001ab6: 60fb str r3, [r7, #12]
+ 8001b1c: 68fb ldr r3, [r7, #12]
+ 8001b1e: f423 7340 bic.w r3, r3, #768 ; 0x300
+ 8001b22: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 8001ab8: 683b ldr r3, [r7, #0]
- 8001aba: 681b ldr r3, [r3, #0]
- 8001abc: 021b lsls r3, r3, #8
- 8001abe: 68fa ldr r2, [r7, #12]
- 8001ac0: 4313 orrs r3, r2
- 8001ac2: 60fb str r3, [r7, #12]
+ 8001b24: 683b ldr r3, [r7, #0]
+ 8001b26: 681b ldr r3, [r3, #0]
+ 8001b28: 021b lsls r3, r3, #8
+ 8001b2a: 68fa ldr r2, [r7, #12]
+ 8001b2c: 4313 orrs r3, r2
+ 8001b2e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
- 8001ac4: 693b ldr r3, [r7, #16]
- 8001ac6: f423 5300 bic.w r3, r3, #8192 ; 0x2000
- 8001aca: 613b str r3, [r7, #16]
+ 8001b30: 693b ldr r3, [r7, #16]
+ 8001b32: f423 5300 bic.w r3, r3, #8192 ; 0x2000
+ 8001b36: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
- 8001acc: 683b ldr r3, [r7, #0]
- 8001ace: 689b ldr r3, [r3, #8]
- 8001ad0: 031b lsls r3, r3, #12
- 8001ad2: 693a ldr r2, [r7, #16]
- 8001ad4: 4313 orrs r3, r2
- 8001ad6: 613b str r3, [r7, #16]
+ 8001b38: 683b ldr r3, [r7, #0]
+ 8001b3a: 689b ldr r3, [r3, #8]
+ 8001b3c: 031b lsls r3, r3, #12
+ 8001b3e: 693a ldr r2, [r7, #16]
+ 8001b40: 4313 orrs r3, r2
+ 8001b42: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8001ad8: 687b ldr r3, [r7, #4]
- 8001ada: 4a13 ldr r2, [pc, #76] ; (8001b28 <TIM_OC4_SetConfig+0xa8>)
- 8001adc: 4293 cmp r3, r2
- 8001ade: d003 beq.n 8001ae8 <TIM_OC4_SetConfig+0x68>
- 8001ae0: 687b ldr r3, [r7, #4]
- 8001ae2: 4a12 ldr r2, [pc, #72] ; (8001b2c <TIM_OC4_SetConfig+0xac>)
- 8001ae4: 4293 cmp r3, r2
- 8001ae6: d109 bne.n 8001afc <TIM_OC4_SetConfig+0x7c>
+ 8001b44: 687b ldr r3, [r7, #4]
+ 8001b46: 4a13 ldr r2, [pc, #76] ; (8001b94 <TIM_OC4_SetConfig+0xa8>)
+ 8001b48: 4293 cmp r3, r2
+ 8001b4a: d003 beq.n 8001b54 <TIM_OC4_SetConfig+0x68>
+ 8001b4c: 687b ldr r3, [r7, #4]
+ 8001b4e: 4a12 ldr r2, [pc, #72] ; (8001b98 <TIM_OC4_SetConfig+0xac>)
+ 8001b50: 4293 cmp r3, r2
+ 8001b52: d109 bne.n 8001b68 <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
- 8001ae8: 697b ldr r3, [r7, #20]
- 8001aea: f423 4380 bic.w r3, r3, #16384 ; 0x4000
- 8001aee: 617b str r3, [r7, #20]
+ 8001b54: 697b ldr r3, [r7, #20]
+ 8001b56: f423 4380 bic.w r3, r3, #16384 ; 0x4000
+ 8001b5a: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
- 8001af0: 683b ldr r3, [r7, #0]
- 8001af2: 695b ldr r3, [r3, #20]
- 8001af4: 019b lsls r3, r3, #6
- 8001af6: 697a ldr r2, [r7, #20]
- 8001af8: 4313 orrs r3, r2
- 8001afa: 617b str r3, [r7, #20]
+ 8001b5c: 683b ldr r3, [r7, #0]
+ 8001b5e: 695b ldr r3, [r3, #20]
+ 8001b60: 019b lsls r3, r3, #6
+ 8001b62: 697a ldr r2, [r7, #20]
+ 8001b64: 4313 orrs r3, r2
+ 8001b66: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8001afc: 687b ldr r3, [r7, #4]
- 8001afe: 697a ldr r2, [r7, #20]
- 8001b00: 605a str r2, [r3, #4]
+ 8001b68: 687b ldr r3, [r7, #4]
+ 8001b6a: 697a ldr r2, [r7, #20]
+ 8001b6c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
- 8001b02: 687b ldr r3, [r7, #4]
- 8001b04: 68fa ldr r2, [r7, #12]
- 8001b06: 61da str r2, [r3, #28]
+ 8001b6e: 687b ldr r3, [r7, #4]
+ 8001b70: 68fa ldr r2, [r7, #12]
+ 8001b72: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
- 8001b08: 683b ldr r3, [r7, #0]
- 8001b0a: 685a ldr r2, [r3, #4]
- 8001b0c: 687b ldr r3, [r7, #4]
- 8001b0e: 641a str r2, [r3, #64] ; 0x40
+ 8001b74: 683b ldr r3, [r7, #0]
+ 8001b76: 685a ldr r2, [r3, #4]
+ 8001b78: 687b ldr r3, [r7, #4]
+ 8001b7a: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8001b10: 687b ldr r3, [r7, #4]
- 8001b12: 693a ldr r2, [r7, #16]
- 8001b14: 621a str r2, [r3, #32]
+ 8001b7c: 687b ldr r3, [r7, #4]
+ 8001b7e: 693a ldr r2, [r7, #16]
+ 8001b80: 621a str r2, [r3, #32]
}
- 8001b16: bf00 nop
- 8001b18: 371c adds r7, #28
- 8001b1a: 46bd mov sp, r7
- 8001b1c: f85d 7b04 ldr.w r7, [sp], #4
- 8001b20: 4770 bx lr
- 8001b22: bf00 nop
- 8001b24: feff8fff .word 0xfeff8fff
- 8001b28: 40010000 .word 0x40010000
- 8001b2c: 40010400 .word 0x40010400
-
-08001b30 <TIM_OC5_SetConfig>:
+ 8001b82: bf00 nop
+ 8001b84: 371c adds r7, #28
+ 8001b86: 46bd mov sp, r7
+ 8001b88: f85d 7b04 ldr.w r7, [sp], #4
+ 8001b8c: 4770 bx lr
+ 8001b8e: bf00 nop
+ 8001b90: feff8fff .word 0xfeff8fff
+ 8001b94: 40010000 .word 0x40010000
+ 8001b98: 40010400 .word 0x40010400
+
+08001b9c <TIM_OC5_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
- 8001b30: b480 push {r7}
- 8001b32: b087 sub sp, #28
- 8001b34: af00 add r7, sp, #0
- 8001b36: 6078 str r0, [r7, #4]
- 8001b38: 6039 str r1, [r7, #0]
+ 8001b9c: b480 push {r7}
+ 8001b9e: b087 sub sp, #28
+ 8001ba0: af00 add r7, sp, #0
+ 8001ba2: 6078 str r0, [r7, #4]
+ 8001ba4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
- 8001b3a: 687b ldr r3, [r7, #4]
- 8001b3c: 6a1b ldr r3, [r3, #32]
- 8001b3e: f423 3280 bic.w r2, r3, #65536 ; 0x10000
- 8001b42: 687b ldr r3, [r7, #4]
- 8001b44: 621a str r2, [r3, #32]
+ 8001ba6: 687b ldr r3, [r7, #4]
+ 8001ba8: 6a1b ldr r3, [r3, #32]
+ 8001baa: f423 3280 bic.w r2, r3, #65536 ; 0x10000
+ 8001bae: 687b ldr r3, [r7, #4]
+ 8001bb0: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8001b46: 687b ldr r3, [r7, #4]
- 8001b48: 6a1b ldr r3, [r3, #32]
- 8001b4a: 613b str r3, [r7, #16]
+ 8001bb2: 687b ldr r3, [r7, #4]
+ 8001bb4: 6a1b ldr r3, [r3, #32]
+ 8001bb6: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8001b4c: 687b ldr r3, [r7, #4]
- 8001b4e: 685b ldr r3, [r3, #4]
- 8001b50: 617b str r3, [r7, #20]
+ 8001bb8: 687b ldr r3, [r7, #4]
+ 8001bba: 685b ldr r3, [r3, #4]
+ 8001bbc: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
- 8001b52: 687b ldr r3, [r7, #4]
- 8001b54: 6d5b ldr r3, [r3, #84] ; 0x54
- 8001b56: 60fb str r3, [r7, #12]
+ 8001bbe: 687b ldr r3, [r7, #4]
+ 8001bc0: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8001bc2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
- 8001b58: 68fa ldr r2, [r7, #12]
- 8001b5a: 4b1b ldr r3, [pc, #108] ; (8001bc8 <TIM_OC5_SetConfig+0x98>)
- 8001b5c: 4013 ands r3, r2
- 8001b5e: 60fb str r3, [r7, #12]
+ 8001bc4: 68fa ldr r2, [r7, #12]
+ 8001bc6: 4b1b ldr r3, [pc, #108] ; (8001c34 <TIM_OC5_SetConfig+0x98>)
+ 8001bc8: 4013 ands r3, r2
+ 8001bca: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 8001b60: 683b ldr r3, [r7, #0]
- 8001b62: 681b ldr r3, [r3, #0]
- 8001b64: 68fa ldr r2, [r7, #12]
- 8001b66: 4313 orrs r3, r2
- 8001b68: 60fb str r3, [r7, #12]
+ 8001bcc: 683b ldr r3, [r7, #0]
+ 8001bce: 681b ldr r3, [r3, #0]
+ 8001bd0: 68fa ldr r2, [r7, #12]
+ 8001bd2: 4313 orrs r3, r2
+ 8001bd4: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
- 8001b6a: 693b ldr r3, [r7, #16]
- 8001b6c: f423 3300 bic.w r3, r3, #131072 ; 0x20000
- 8001b70: 613b str r3, [r7, #16]
+ 8001bd6: 693b ldr r3, [r7, #16]
+ 8001bd8: f423 3300 bic.w r3, r3, #131072 ; 0x20000
+ 8001bdc: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
- 8001b72: 683b ldr r3, [r7, #0]
- 8001b74: 689b ldr r3, [r3, #8]
- 8001b76: 041b lsls r3, r3, #16
- 8001b78: 693a ldr r2, [r7, #16]
- 8001b7a: 4313 orrs r3, r2
- 8001b7c: 613b str r3, [r7, #16]
+ 8001bde: 683b ldr r3, [r7, #0]
+ 8001be0: 689b ldr r3, [r3, #8]
+ 8001be2: 041b lsls r3, r3, #16
+ 8001be4: 693a ldr r2, [r7, #16]
+ 8001be6: 4313 orrs r3, r2
+ 8001be8: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8001b7e: 687b ldr r3, [r7, #4]
- 8001b80: 4a12 ldr r2, [pc, #72] ; (8001bcc <TIM_OC5_SetConfig+0x9c>)
- 8001b82: 4293 cmp r3, r2
- 8001b84: d003 beq.n 8001b8e <TIM_OC5_SetConfig+0x5e>
- 8001b86: 687b ldr r3, [r7, #4]
- 8001b88: 4a11 ldr r2, [pc, #68] ; (8001bd0 <TIM_OC5_SetConfig+0xa0>)
- 8001b8a: 4293 cmp r3, r2
- 8001b8c: d109 bne.n 8001ba2 <TIM_OC5_SetConfig+0x72>
+ 8001bea: 687b ldr r3, [r7, #4]
+ 8001bec: 4a12 ldr r2, [pc, #72] ; (8001c38 <TIM_OC5_SetConfig+0x9c>)
+ 8001bee: 4293 cmp r3, r2
+ 8001bf0: d003 beq.n 8001bfa <TIM_OC5_SetConfig+0x5e>
+ 8001bf2: 687b ldr r3, [r7, #4]
+ 8001bf4: 4a11 ldr r2, [pc, #68] ; (8001c3c <TIM_OC5_SetConfig+0xa0>)
+ 8001bf6: 4293 cmp r3, r2
+ 8001bf8: d109 bne.n 8001c0e <TIM_OC5_SetConfig+0x72>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
- 8001b8e: 697b ldr r3, [r7, #20]
- 8001b90: f423 3380 bic.w r3, r3, #65536 ; 0x10000
- 8001b94: 617b str r3, [r7, #20]
+ 8001bfa: 697b ldr r3, [r7, #20]
+ 8001bfc: f423 3380 bic.w r3, r3, #65536 ; 0x10000
+ 8001c00: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
- 8001b96: 683b ldr r3, [r7, #0]
- 8001b98: 695b ldr r3, [r3, #20]
- 8001b9a: 021b lsls r3, r3, #8
- 8001b9c: 697a ldr r2, [r7, #20]
- 8001b9e: 4313 orrs r3, r2
- 8001ba0: 617b str r3, [r7, #20]
+ 8001c02: 683b ldr r3, [r7, #0]
+ 8001c04: 695b ldr r3, [r3, #20]
+ 8001c06: 021b lsls r3, r3, #8
+ 8001c08: 697a ldr r2, [r7, #20]
+ 8001c0a: 4313 orrs r3, r2
+ 8001c0c: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8001ba2: 687b ldr r3, [r7, #4]
- 8001ba4: 697a ldr r2, [r7, #20]
- 8001ba6: 605a str r2, [r3, #4]
+ 8001c0e: 687b ldr r3, [r7, #4]
+ 8001c10: 697a ldr r2, [r7, #20]
+ 8001c12: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
- 8001ba8: 687b ldr r3, [r7, #4]
- 8001baa: 68fa ldr r2, [r7, #12]
- 8001bac: 655a str r2, [r3, #84] ; 0x54
+ 8001c14: 687b ldr r3, [r7, #4]
+ 8001c16: 68fa ldr r2, [r7, #12]
+ 8001c18: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
- 8001bae: 683b ldr r3, [r7, #0]
- 8001bb0: 685a ldr r2, [r3, #4]
- 8001bb2: 687b ldr r3, [r7, #4]
- 8001bb4: 659a str r2, [r3, #88] ; 0x58
+ 8001c1a: 683b ldr r3, [r7, #0]
+ 8001c1c: 685a ldr r2, [r3, #4]
+ 8001c1e: 687b ldr r3, [r7, #4]
+ 8001c20: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8001bb6: 687b ldr r3, [r7, #4]
- 8001bb8: 693a ldr r2, [r7, #16]
- 8001bba: 621a str r2, [r3, #32]
+ 8001c22: 687b ldr r3, [r7, #4]
+ 8001c24: 693a ldr r2, [r7, #16]
+ 8001c26: 621a str r2, [r3, #32]
}
- 8001bbc: bf00 nop
- 8001bbe: 371c adds r7, #28
- 8001bc0: 46bd mov sp, r7
- 8001bc2: f85d 7b04 ldr.w r7, [sp], #4
- 8001bc6: 4770 bx lr
- 8001bc8: fffeff8f .word 0xfffeff8f
- 8001bcc: 40010000 .word 0x40010000
- 8001bd0: 40010400 .word 0x40010400
-
-08001bd4 <TIM_OC6_SetConfig>:
+ 8001c28: bf00 nop
+ 8001c2a: 371c adds r7, #28
+ 8001c2c: 46bd mov sp, r7
+ 8001c2e: f85d 7b04 ldr.w r7, [sp], #4
+ 8001c32: 4770 bx lr
+ 8001c34: fffeff8f .word 0xfffeff8f
+ 8001c38: 40010000 .word 0x40010000
+ 8001c3c: 40010400 .word 0x40010400
+
+08001c40 <TIM_OC6_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
- 8001bd4: b480 push {r7}
- 8001bd6: b087 sub sp, #28
- 8001bd8: af00 add r7, sp, #0
- 8001bda: 6078 str r0, [r7, #4]
- 8001bdc: 6039 str r1, [r7, #0]
+ 8001c40: b480 push {r7}
+ 8001c42: b087 sub sp, #28
+ 8001c44: af00 add r7, sp, #0
+ 8001c46: 6078 str r0, [r7, #4]
+ 8001c48: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
- 8001bde: 687b ldr r3, [r7, #4]
- 8001be0: 6a1b ldr r3, [r3, #32]
- 8001be2: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
- 8001be6: 687b ldr r3, [r7, #4]
- 8001be8: 621a str r2, [r3, #32]
+ 8001c4a: 687b ldr r3, [r7, #4]
+ 8001c4c: 6a1b ldr r3, [r3, #32]
+ 8001c4e: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
+ 8001c52: 687b ldr r3, [r7, #4]
+ 8001c54: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8001bea: 687b ldr r3, [r7, #4]
- 8001bec: 6a1b ldr r3, [r3, #32]
- 8001bee: 613b str r3, [r7, #16]
+ 8001c56: 687b ldr r3, [r7, #4]
+ 8001c58: 6a1b ldr r3, [r3, #32]
+ 8001c5a: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8001bf0: 687b ldr r3, [r7, #4]
- 8001bf2: 685b ldr r3, [r3, #4]
- 8001bf4: 617b str r3, [r7, #20]
+ 8001c5c: 687b ldr r3, [r7, #4]
+ 8001c5e: 685b ldr r3, [r3, #4]
+ 8001c60: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
- 8001bf6: 687b ldr r3, [r7, #4]
- 8001bf8: 6d5b ldr r3, [r3, #84] ; 0x54
- 8001bfa: 60fb str r3, [r7, #12]
+ 8001c62: 687b ldr r3, [r7, #4]
+ 8001c64: 6d5b ldr r3, [r3, #84] ; 0x54
+ 8001c66: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
- 8001bfc: 68fa ldr r2, [r7, #12]
- 8001bfe: 4b1c ldr r3, [pc, #112] ; (8001c70 <TIM_OC6_SetConfig+0x9c>)
- 8001c00: 4013 ands r3, r2
- 8001c02: 60fb str r3, [r7, #12]
+ 8001c68: 68fa ldr r2, [r7, #12]
+ 8001c6a: 4b1c ldr r3, [pc, #112] ; (8001cdc <TIM_OC6_SetConfig+0x9c>)
+ 8001c6c: 4013 ands r3, r2
+ 8001c6e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 8001c04: 683b ldr r3, [r7, #0]
- 8001c06: 681b ldr r3, [r3, #0]
- 8001c08: 021b lsls r3, r3, #8
- 8001c0a: 68fa ldr r2, [r7, #12]
- 8001c0c: 4313 orrs r3, r2
- 8001c0e: 60fb str r3, [r7, #12]
+ 8001c70: 683b ldr r3, [r7, #0]
+ 8001c72: 681b ldr r3, [r3, #0]
+ 8001c74: 021b lsls r3, r3, #8
+ 8001c76: 68fa ldr r2, [r7, #12]
+ 8001c78: 4313 orrs r3, r2
+ 8001c7a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- 8001c10: 693b ldr r3, [r7, #16]
- 8001c12: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
- 8001c16: 613b str r3, [r7, #16]
+ 8001c7c: 693b ldr r3, [r7, #16]
+ 8001c7e: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
+ 8001c82: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
- 8001c18: 683b ldr r3, [r7, #0]
- 8001c1a: 689b ldr r3, [r3, #8]
- 8001c1c: 051b lsls r3, r3, #20
- 8001c1e: 693a ldr r2, [r7, #16]
- 8001c20: 4313 orrs r3, r2
- 8001c22: 613b str r3, [r7, #16]
+ 8001c84: 683b ldr r3, [r7, #0]
+ 8001c86: 689b ldr r3, [r3, #8]
+ 8001c88: 051b lsls r3, r3, #20
+ 8001c8a: 693a ldr r2, [r7, #16]
+ 8001c8c: 4313 orrs r3, r2
+ 8001c8e: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8001c24: 687b ldr r3, [r7, #4]
- 8001c26: 4a13 ldr r2, [pc, #76] ; (8001c74 <TIM_OC6_SetConfig+0xa0>)
- 8001c28: 4293 cmp r3, r2
- 8001c2a: d003 beq.n 8001c34 <TIM_OC6_SetConfig+0x60>
- 8001c2c: 687b ldr r3, [r7, #4]
- 8001c2e: 4a12 ldr r2, [pc, #72] ; (8001c78 <TIM_OC6_SetConfig+0xa4>)
- 8001c30: 4293 cmp r3, r2
- 8001c32: d109 bne.n 8001c48 <TIM_OC6_SetConfig+0x74>
+ 8001c90: 687b ldr r3, [r7, #4]
+ 8001c92: 4a13 ldr r2, [pc, #76] ; (8001ce0 <TIM_OC6_SetConfig+0xa0>)
+ 8001c94: 4293 cmp r3, r2
+ 8001c96: d003 beq.n 8001ca0 <TIM_OC6_SetConfig+0x60>
+ 8001c98: 687b ldr r3, [r7, #4]
+ 8001c9a: 4a12 ldr r2, [pc, #72] ; (8001ce4 <TIM_OC6_SetConfig+0xa4>)
+ 8001c9c: 4293 cmp r3, r2
+ 8001c9e: d109 bne.n 8001cb4 <TIM_OC6_SetConfig+0x74>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
- 8001c34: 697b ldr r3, [r7, #20]
- 8001c36: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 8001c3a: 617b str r3, [r7, #20]
+ 8001ca0: 697b ldr r3, [r7, #20]
+ 8001ca2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 8001ca6: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
- 8001c3c: 683b ldr r3, [r7, #0]
- 8001c3e: 695b ldr r3, [r3, #20]
- 8001c40: 029b lsls r3, r3, #10
- 8001c42: 697a ldr r2, [r7, #20]
- 8001c44: 4313 orrs r3, r2
- 8001c46: 617b str r3, [r7, #20]
+ 8001ca8: 683b ldr r3, [r7, #0]
+ 8001caa: 695b ldr r3, [r3, #20]
+ 8001cac: 029b lsls r3, r3, #10
+ 8001cae: 697a ldr r2, [r7, #20]
+ 8001cb0: 4313 orrs r3, r2
+ 8001cb2: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 8001c48: 687b ldr r3, [r7, #4]
- 8001c4a: 697a ldr r2, [r7, #20]
- 8001c4c: 605a str r2, [r3, #4]
+ 8001cb4: 687b ldr r3, [r7, #4]
+ 8001cb6: 697a ldr r2, [r7, #20]
+ 8001cb8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
- 8001c4e: 687b ldr r3, [r7, #4]
- 8001c50: 68fa ldr r2, [r7, #12]
- 8001c52: 655a str r2, [r3, #84] ; 0x54
+ 8001cba: 687b ldr r3, [r7, #4]
+ 8001cbc: 68fa ldr r2, [r7, #12]
+ 8001cbe: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
- 8001c54: 683b ldr r3, [r7, #0]
- 8001c56: 685a ldr r2, [r3, #4]
- 8001c58: 687b ldr r3, [r7, #4]
- 8001c5a: 65da str r2, [r3, #92] ; 0x5c
+ 8001cc0: 683b ldr r3, [r7, #0]
+ 8001cc2: 685a ldr r2, [r3, #4]
+ 8001cc4: 687b ldr r3, [r7, #4]
+ 8001cc6: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8001c5c: 687b ldr r3, [r7, #4]
- 8001c5e: 693a ldr r2, [r7, #16]
- 8001c60: 621a str r2, [r3, #32]
+ 8001cc8: 687b ldr r3, [r7, #4]
+ 8001cca: 693a ldr r2, [r7, #16]
+ 8001ccc: 621a str r2, [r3, #32]
}
- 8001c62: bf00 nop
- 8001c64: 371c adds r7, #28
- 8001c66: 46bd mov sp, r7
- 8001c68: f85d 7b04 ldr.w r7, [sp], #4
- 8001c6c: 4770 bx lr
- 8001c6e: bf00 nop
- 8001c70: feff8fff .word 0xfeff8fff
- 8001c74: 40010000 .word 0x40010000
- 8001c78: 40010400 .word 0x40010400
-
-08001c7c <TIM_CCxChannelCmd>:
+ 8001cce: bf00 nop
+ 8001cd0: 371c adds r7, #28
+ 8001cd2: 46bd mov sp, r7
+ 8001cd4: f85d 7b04 ldr.w r7, [sp], #4
+ 8001cd8: 4770 bx lr
+ 8001cda: bf00 nop
+ 8001cdc: feff8fff .word 0xfeff8fff
+ 8001ce0: 40010000 .word 0x40010000
+ 8001ce4: 40010400 .word 0x40010400
+
+08001ce8 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
- 8001c7c: b480 push {r7}
- 8001c7e: b087 sub sp, #28
- 8001c80: af00 add r7, sp, #0
- 8001c82: 60f8 str r0, [r7, #12]
- 8001c84: 60b9 str r1, [r7, #8]
- 8001c86: 607a str r2, [r7, #4]
+ 8001ce8: b480 push {r7}
+ 8001cea: b087 sub sp, #28
+ 8001cec: af00 add r7, sp, #0
+ 8001cee: 60f8 str r0, [r7, #12]
+ 8001cf0: 60b9 str r1, [r7, #8]
+ 8001cf2: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
- 8001c88: 68bb ldr r3, [r7, #8]
- 8001c8a: f003 031f and.w r3, r3, #31
- 8001c8e: 2201 movs r2, #1
- 8001c90: fa02 f303 lsl.w r3, r2, r3
- 8001c94: 617b str r3, [r7, #20]
+ 8001cf4: 68bb ldr r3, [r7, #8]
+ 8001cf6: f003 031f and.w r3, r3, #31
+ 8001cfa: 2201 movs r2, #1
+ 8001cfc: fa02 f303 lsl.w r3, r2, r3
+ 8001d00: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
- 8001c96: 68fb ldr r3, [r7, #12]
- 8001c98: 6a1a ldr r2, [r3, #32]
- 8001c9a: 697b ldr r3, [r7, #20]
- 8001c9c: 43db mvns r3, r3
- 8001c9e: 401a ands r2, r3
- 8001ca0: 68fb ldr r3, [r7, #12]
- 8001ca2: 621a str r2, [r3, #32]
+ 8001d02: 68fb ldr r3, [r7, #12]
+ 8001d04: 6a1a ldr r2, [r3, #32]
+ 8001d06: 697b ldr r3, [r7, #20]
+ 8001d08: 43db mvns r3, r3
+ 8001d0a: 401a ands r2, r3
+ 8001d0c: 68fb ldr r3, [r7, #12]
+ 8001d0e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
- 8001ca4: 68fb ldr r3, [r7, #12]
- 8001ca6: 6a1a ldr r2, [r3, #32]
- 8001ca8: 68bb ldr r3, [r7, #8]
- 8001caa: f003 031f and.w r3, r3, #31
- 8001cae: 6879 ldr r1, [r7, #4]
- 8001cb0: fa01 f303 lsl.w r3, r1, r3
- 8001cb4: 431a orrs r2, r3
- 8001cb6: 68fb ldr r3, [r7, #12]
- 8001cb8: 621a str r2, [r3, #32]
+ 8001d10: 68fb ldr r3, [r7, #12]
+ 8001d12: 6a1a ldr r2, [r3, #32]
+ 8001d14: 68bb ldr r3, [r7, #8]
+ 8001d16: f003 031f and.w r3, r3, #31
+ 8001d1a: 6879 ldr r1, [r7, #4]
+ 8001d1c: fa01 f303 lsl.w r3, r1, r3
+ 8001d20: 431a orrs r2, r3
+ 8001d22: 68fb ldr r3, [r7, #12]
+ 8001d24: 621a str r2, [r3, #32]
}
- 8001cba: bf00 nop
- 8001cbc: 371c adds r7, #28
- 8001cbe: 46bd mov sp, r7
- 8001cc0: f85d 7b04 ldr.w r7, [sp], #4
- 8001cc4: 4770 bx lr
+ 8001d26: bf00 nop
+ 8001d28: 371c adds r7, #28
+ 8001d2a: 46bd mov sp, r7
+ 8001d2c: f85d 7b04 ldr.w r7, [sp], #4
+ 8001d30: 4770 bx lr
...
-08001cc8 <HAL_TIMEx_MasterConfigSynchronization>:
+08001d34 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
- 8001cc8: b480 push {r7}
- 8001cca: b085 sub sp, #20
- 8001ccc: af00 add r7, sp, #0
- 8001cce: 6078 str r0, [r7, #4]
- 8001cd0: 6039 str r1, [r7, #0]
+ 8001d34: b480 push {r7}
+ 8001d36: b085 sub sp, #20
+ 8001d38: af00 add r7, sp, #0
+ 8001d3a: 6078 str r0, [r7, #4]
+ 8001d3c: 6039 str r1, [r7, #0]
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
- 8001cd2: 687b ldr r3, [r7, #4]
- 8001cd4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
- 8001cd8: 2b01 cmp r3, #1
- 8001cda: d101 bne.n 8001ce0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 8001cdc: 2302 movs r3, #2
- 8001cde: e045 b.n 8001d6c <HAL_TIMEx_MasterConfigSynchronization+0xa4>
- 8001ce0: 687b ldr r3, [r7, #4]
- 8001ce2: 2201 movs r2, #1
- 8001ce4: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8001d3e: 687b ldr r3, [r7, #4]
+ 8001d40: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
+ 8001d44: 2b01 cmp r3, #1
+ 8001d46: d101 bne.n 8001d4c <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 8001d48: 2302 movs r3, #2
+ 8001d4a: e045 b.n 8001dd8 <HAL_TIMEx_MasterConfigSynchronization+0xa4>
+ 8001d4c: 687b ldr r3, [r7, #4]
+ 8001d4e: 2201 movs r2, #1
+ 8001d50: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
- 8001ce8: 687b ldr r3, [r7, #4]
- 8001cea: 2202 movs r2, #2
- 8001cec: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8001d54: 687b ldr r3, [r7, #4]
+ 8001d56: 2202 movs r2, #2
+ 8001d58: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
- 8001cf0: 687b ldr r3, [r7, #4]
- 8001cf2: 681b ldr r3, [r3, #0]
- 8001cf4: 685b ldr r3, [r3, #4]
- 8001cf6: 60fb str r3, [r7, #12]
+ 8001d5c: 687b ldr r3, [r7, #4]
+ 8001d5e: 681b ldr r3, [r3, #0]
+ 8001d60: 685b ldr r3, [r3, #4]
+ 8001d62: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
- 8001cf8: 687b ldr r3, [r7, #4]
- 8001cfa: 681b ldr r3, [r3, #0]
- 8001cfc: 689b ldr r3, [r3, #8]
- 8001cfe: 60bb str r3, [r7, #8]
+ 8001d64: 687b ldr r3, [r7, #4]
+ 8001d66: 681b ldr r3, [r3, #0]
+ 8001d68: 689b ldr r3, [r3, #8]
+ 8001d6a: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 8001d00: 687b ldr r3, [r7, #4]
- 8001d02: 681b ldr r3, [r3, #0]
- 8001d04: 4a1c ldr r2, [pc, #112] ; (8001d78 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
- 8001d06: 4293 cmp r3, r2
- 8001d08: d004 beq.n 8001d14 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
- 8001d0a: 687b ldr r3, [r7, #4]
- 8001d0c: 681b ldr r3, [r3, #0]
- 8001d0e: 4a1b ldr r2, [pc, #108] ; (8001d7c <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
- 8001d10: 4293 cmp r3, r2
- 8001d12: d108 bne.n 8001d26 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
+ 8001d6c: 687b ldr r3, [r7, #4]
+ 8001d6e: 681b ldr r3, [r3, #0]
+ 8001d70: 4a1c ldr r2, [pc, #112] ; (8001de4 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
+ 8001d72: 4293 cmp r3, r2
+ 8001d74: d004 beq.n 8001d80 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
+ 8001d76: 687b ldr r3, [r7, #4]
+ 8001d78: 681b ldr r3, [r3, #0]
+ 8001d7a: 4a1b ldr r2, [pc, #108] ; (8001de8 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
+ 8001d7c: 4293 cmp r3, r2
+ 8001d7e: d108 bne.n 8001d92 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
- 8001d14: 68fb ldr r3, [r7, #12]
- 8001d16: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
- 8001d1a: 60fb str r3, [r7, #12]
+ 8001d80: 68fb ldr r3, [r7, #12]
+ 8001d82: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
+ 8001d86: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 8001d1c: 683b ldr r3, [r7, #0]
- 8001d1e: 685b ldr r3, [r3, #4]
- 8001d20: 68fa ldr r2, [r7, #12]
- 8001d22: 4313 orrs r3, r2
- 8001d24: 60fb str r3, [r7, #12]
+ 8001d88: 683b ldr r3, [r7, #0]
+ 8001d8a: 685b ldr r3, [r3, #4]
+ 8001d8c: 68fa ldr r2, [r7, #12]
+ 8001d8e: 4313 orrs r3, r2
+ 8001d90: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
- 8001d26: 68fb ldr r3, [r7, #12]
- 8001d28: f023 0370 bic.w r3, r3, #112 ; 0x70
- 8001d2c: 60fb str r3, [r7, #12]
+ 8001d92: 68fb ldr r3, [r7, #12]
+ 8001d94: f023 0370 bic.w r3, r3, #112 ; 0x70
+ 8001d98: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 8001d2e: 683b ldr r3, [r7, #0]
- 8001d30: 681b ldr r3, [r3, #0]
- 8001d32: 68fa ldr r2, [r7, #12]
- 8001d34: 4313 orrs r3, r2
- 8001d36: 60fb str r3, [r7, #12]
+ 8001d9a: 683b ldr r3, [r7, #0]
+ 8001d9c: 681b ldr r3, [r3, #0]
+ 8001d9e: 68fa ldr r2, [r7, #12]
+ 8001da0: 4313 orrs r3, r2
+ 8001da2: 60fb str r3, [r7, #12]
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
- 8001d38: 68bb ldr r3, [r7, #8]
- 8001d3a: f023 0380 bic.w r3, r3, #128 ; 0x80
- 8001d3e: 60bb str r3, [r7, #8]
+ 8001da4: 68bb ldr r3, [r7, #8]
+ 8001da6: f023 0380 bic.w r3, r3, #128 ; 0x80
+ 8001daa: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 8001d40: 683b ldr r3, [r7, #0]
- 8001d42: 689b ldr r3, [r3, #8]
- 8001d44: 68ba ldr r2, [r7, #8]
- 8001d46: 4313 orrs r3, r2
- 8001d48: 60bb str r3, [r7, #8]
+ 8001dac: 683b ldr r3, [r7, #0]
+ 8001dae: 689b ldr r3, [r3, #8]
+ 8001db0: 68ba ldr r2, [r7, #8]
+ 8001db2: 4313 orrs r3, r2
+ 8001db4: 60bb str r3, [r7, #8]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- 8001d4a: 687b ldr r3, [r7, #4]
- 8001d4c: 681b ldr r3, [r3, #0]
- 8001d4e: 68fa ldr r2, [r7, #12]
- 8001d50: 605a str r2, [r3, #4]
+ 8001db6: 687b ldr r3, [r7, #4]
+ 8001db8: 681b ldr r3, [r3, #0]
+ 8001dba: 68fa ldr r2, [r7, #12]
+ 8001dbc: 605a str r2, [r3, #4]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
- 8001d52: 687b ldr r3, [r7, #4]
- 8001d54: 681b ldr r3, [r3, #0]
- 8001d56: 68ba ldr r2, [r7, #8]
- 8001d58: 609a str r2, [r3, #8]
+ 8001dbe: 687b ldr r3, [r7, #4]
+ 8001dc0: 681b ldr r3, [r3, #0]
+ 8001dc2: 68ba ldr r2, [r7, #8]
+ 8001dc4: 609a str r2, [r3, #8]
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
- 8001d5a: 687b ldr r3, [r7, #4]
- 8001d5c: 2201 movs r2, #1
- 8001d5e: f883 203d strb.w r2, [r3, #61] ; 0x3d
+ 8001dc6: 687b ldr r3, [r7, #4]
+ 8001dc8: 2201 movs r2, #1
+ 8001dca: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
- 8001d62: 687b ldr r3, [r7, #4]
- 8001d64: 2200 movs r2, #0
- 8001d66: f883 203c strb.w r2, [r3, #60] ; 0x3c
+ 8001dce: 687b ldr r3, [r7, #4]
+ 8001dd0: 2200 movs r2, #0
+ 8001dd2: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
- 8001d6a: 2300 movs r3, #0
+ 8001dd6: 2300 movs r3, #0
}
- 8001d6c: 4618 mov r0, r3
- 8001d6e: 3714 adds r7, #20
- 8001d70: 46bd mov sp, r7
- 8001d72: f85d 7b04 ldr.w r7, [sp], #4
- 8001d76: 4770 bx lr
- 8001d78: 40010000 .word 0x40010000
- 8001d7c: 40010400 .word 0x40010400
-
-08001d80 <main>:
+ 8001dd8: 4618 mov r0, r3
+ 8001dda: 3714 adds r7, #20
+ 8001ddc: 46bd mov sp, r7
+ 8001dde: f85d 7b04 ldr.w r7, [sp], #4
+ 8001de2: 4770 bx lr
+ 8001de4: 40010000 .word 0x40010000
+ 8001de8: 40010400 .word 0x40010400
+
+08001dec <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
- 8001d80: b580 push {r7, lr}
- 8001d82: b082 sub sp, #8
- 8001d84: af00 add r7, sp, #0
+ 8001dec: b5f0 push {r4, r5, r6, r7, lr}
+ 8001dee: b08f sub sp, #60 ; 0x3c
+ 8001df0: af0e add r7, sp, #56 ; 0x38
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
- 8001d86: f7fe fbd7 bl 8000538 <HAL_Init>
+ 8001df2: f7fe fba1 bl 8000538 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
- 8001d8a: f000 f829 bl 8001de0 <SystemClock_Config>
+ 8001df6: f000 f821 bl 8001e3c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
- 8001d8e: f000 f8dd bl 8001f4c <MX_GPIO_Init>
+ 8001dfa: f000 f8d5 bl 8001fa8 <MX_GPIO_Init>
MX_TIM4_Init();
- 8001d92: f000 f881 bl 8001e98 <MX_TIM4_Init>
+ 8001dfe: f000 f879 bl 8001ef4 <MX_TIM4_Init>
/* USER CODE BEGIN 2 */
- // PIN D9
- HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4);
- 8001d96: 210c movs r1, #12
- 8001d98: 4810 ldr r0, [pc, #64] ; (8001ddc <main+0x5c>)
- 8001d9a: f7ff fb15 bl 80013c8 <HAL_TIM_PWM_Start>
- uint16_t pwm_value = 0;
- 8001d9e: 2300 movs r3, #0
- 8001da0: 80fb strh r3, [r7, #6]
- int step = 100;
- 8001da2: 2364 movs r3, #100 ; 0x64
- 8001da4: 603b str r3, [r7, #0]
+
+ // PIN D9
+ HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4);
+ 8001e02: 210c movs r1, #12
+ 8001e04: 480c ldr r0, [pc, #48] ; (8001e38 <main+0x4c>)
+ 8001e06: f7ff fabd bl 8001384 <HAL_TIM_PWM_Start>
+
+ setPWM(htim4, TIM_CHANNEL_4, 400);
+ 8001e0a: 4e0b ldr r6, [pc, #44] ; (8001e38 <main+0x4c>)
+ 8001e0c: f44f 73c8 mov.w r3, #400 ; 0x190
+ 8001e10: 930d str r3, [sp, #52] ; 0x34
+ 8001e12: 230c movs r3, #12
+ 8001e14: 930c str r3, [sp, #48] ; 0x30
+ 8001e16: 466d mov r5, sp
+ 8001e18: f106 0410 add.w r4, r6, #16
+ 8001e1c: cc0f ldmia r4!, {r0, r1, r2, r3}
+ 8001e1e: c50f stmia r5!, {r0, r1, r2, r3}
+ 8001e20: cc0f ldmia r4!, {r0, r1, r2, r3}
+ 8001e22: c50f stmia r5!, {r0, r1, r2, r3}
+ 8001e24: e894 000f ldmia.w r4, {r0, r1, r2, r3}
+ 8001e28: e885 000f stmia.w r5, {r0, r1, r2, r3}
+ 8001e2c: e896 000f ldmia.w r6, {r0, r1, r2, r3}
+ 8001e30: f000 f8d9 bl 8001fe6 <setPWM>
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
- /* USER CODE END WHILE */
-
- /* USER CODE BEGIN 3 */
- HAL_Delay(100);
- 8001da6: 2064 movs r0, #100 ; 0x64
- 8001da8: f7fe fc24 bl 80005f4 <HAL_Delay>
- if(pwm_value==800)
- 8001dac: 88fb ldrh r3, [r7, #6]
- 8001dae: f5b3 7f48 cmp.w r3, #800 ; 0x320
- 8001db2: d103 bne.n 8001dbc <main+0x3c>
- step = -100;
- 8001db4: f06f 0363 mvn.w r3, #99 ; 0x63
- 8001db8: 603b str r3, [r7, #0]
- 8001dba: e004 b.n 8001dc6 <main+0x46>
- else if (pwm_value == 0)
- 8001dbc: 88fb ldrh r3, [r7, #6]
- 8001dbe: 2b00 cmp r3, #0
- 8001dc0: d101 bne.n 8001dc6 <main+0x46>
- step = 100;
- 8001dc2: 2364 movs r3, #100 ; 0x64
- 8001dc4: 603b str r3, [r7, #0]
-
- user_pwm_setvalue(pwm_value);
- 8001dc6: 88fb ldrh r3, [r7, #6]
- 8001dc8: 4618 mov r0, r3
- 8001dca: f000 f8d7 bl 8001f7c <user_pwm_setvalue>
- pwm_value+=step;
- 8001dce: 683b ldr r3, [r7, #0]
- 8001dd0: b29a uxth r2, r3
- 8001dd2: 88fb ldrh r3, [r7, #6]
- 8001dd4: 4413 add r3, r2
- 8001dd6: 80fb strh r3, [r7, #6]
- HAL_Delay(100);
- 8001dd8: e7e5 b.n 8001da6 <main+0x26>
- 8001dda: bf00 nop
- 8001ddc: 2000002c .word 0x2000002c
-
-08001de0 <SystemClock_Config>:
+ 8001e34: e7fe b.n 8001e34 <main+0x48>
+ 8001e36: bf00 nop
+ 8001e38: 2000002c .word 0x2000002c
+
+08001e3c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
- 8001de0: b580 push {r7, lr}
- 8001de2: b094 sub sp, #80 ; 0x50
- 8001de4: af00 add r7, sp, #0
+ 8001e3c: b580 push {r7, lr}
+ 8001e3e: b094 sub sp, #80 ; 0x50
+ 8001e40: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 8001de6: f107 031c add.w r3, r7, #28
- 8001dea: 2234 movs r2, #52 ; 0x34
- 8001dec: 2100 movs r1, #0
- 8001dee: 4618 mov r0, r3
- 8001df0: f000 fa18 bl 8002224 <memset>
+ 8001e42: f107 031c add.w r3, r7, #28
+ 8001e46: 2234 movs r2, #52 ; 0x34
+ 8001e48: 2100 movs r1, #0
+ 8001e4a: 4618 mov r0, r3
+ 8001e4c: f000 fa22 bl 8002294 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 8001df4: f107 0308 add.w r3, r7, #8
- 8001df8: 2200 movs r2, #0
- 8001dfa: 601a str r2, [r3, #0]
- 8001dfc: 605a str r2, [r3, #4]
- 8001dfe: 609a str r2, [r3, #8]
- 8001e00: 60da str r2, [r3, #12]
- 8001e02: 611a str r2, [r3, #16]
+ 8001e50: f107 0308 add.w r3, r7, #8
+ 8001e54: 2200 movs r2, #0
+ 8001e56: 601a str r2, [r3, #0]
+ 8001e58: 605a str r2, [r3, #4]
+ 8001e5a: 609a str r2, [r3, #8]
+ 8001e5c: 60da str r2, [r3, #12]
+ 8001e5e: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
- 8001e04: 4b22 ldr r3, [pc, #136] ; (8001e90 <SystemClock_Config+0xb0>)
- 8001e06: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001e08: 4a21 ldr r2, [pc, #132] ; (8001e90 <SystemClock_Config+0xb0>)
- 8001e0a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8001e0e: 6413 str r3, [r2, #64] ; 0x40
- 8001e10: 4b1f ldr r3, [pc, #124] ; (8001e90 <SystemClock_Config+0xb0>)
- 8001e12: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001e14: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001e18: 607b str r3, [r7, #4]
- 8001e1a: 687b ldr r3, [r7, #4]
+ 8001e60: 4b22 ldr r3, [pc, #136] ; (8001eec <SystemClock_Config+0xb0>)
+ 8001e62: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001e64: 4a21 ldr r2, [pc, #132] ; (8001eec <SystemClock_Config+0xb0>)
+ 8001e66: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8001e6a: 6413 str r3, [r2, #64] ; 0x40
+ 8001e6c: 4b1f ldr r3, [pc, #124] ; (8001eec <SystemClock_Config+0xb0>)
+ 8001e6e: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8001e70: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8001e74: 607b str r3, [r7, #4]
+ 8001e76: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
- 8001e1c: 4b1d ldr r3, [pc, #116] ; (8001e94 <SystemClock_Config+0xb4>)
- 8001e1e: 681b ldr r3, [r3, #0]
- 8001e20: f423 4340 bic.w r3, r3, #49152 ; 0xc000
- 8001e24: 4a1b ldr r2, [pc, #108] ; (8001e94 <SystemClock_Config+0xb4>)
- 8001e26: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8001e2a: 6013 str r3, [r2, #0]
- 8001e2c: 4b19 ldr r3, [pc, #100] ; (8001e94 <SystemClock_Config+0xb4>)
- 8001e2e: 681b ldr r3, [r3, #0]
- 8001e30: f403 4340 and.w r3, r3, #49152 ; 0xc000
- 8001e34: 603b str r3, [r7, #0]
- 8001e36: 683b ldr r3, [r7, #0]
+ 8001e78: 4b1d ldr r3, [pc, #116] ; (8001ef0 <SystemClock_Config+0xb4>)
+ 8001e7a: 681b ldr r3, [r3, #0]
+ 8001e7c: f423 4340 bic.w r3, r3, #49152 ; 0xc000
+ 8001e80: 4a1b ldr r2, [pc, #108] ; (8001ef0 <SystemClock_Config+0xb4>)
+ 8001e82: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8001e86: 6013 str r3, [r2, #0]
+ 8001e88: 4b19 ldr r3, [pc, #100] ; (8001ef0 <SystemClock_Config+0xb4>)
+ 8001e8a: 681b ldr r3, [r3, #0]
+ 8001e8c: f403 4340 and.w r3, r3, #49152 ; 0xc000
+ 8001e90: 603b str r3, [r7, #0]
+ 8001e92: 683b ldr r3, [r7, #0]
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8001e38: 2302 movs r3, #2
- 8001e3a: 61fb str r3, [r7, #28]
+ 8001e94: 2302 movs r3, #2
+ 8001e96: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8001e3c: 2301 movs r3, #1
- 8001e3e: 62bb str r3, [r7, #40] ; 0x28
+ 8001e98: 2301 movs r3, #1
+ 8001e9a: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8001e40: 2310 movs r3, #16
- 8001e42: 62fb str r3, [r7, #44] ; 0x2c
+ 8001e9c: 2310 movs r3, #16
+ 8001e9e: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 8001e44: 2300 movs r3, #0
- 8001e46: 637b str r3, [r7, #52] ; 0x34
+ 8001ea0: 2300 movs r3, #0
+ 8001ea2: 637b str r3, [r7, #52] ; 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 8001e48: f107 031c add.w r3, r7, #28
- 8001e4c: 4618 mov r0, r3
- 8001e4e: f7fe fe83 bl 8000b58 <HAL_RCC_OscConfig>
- 8001e52: 4603 mov r3, r0
- 8001e54: 2b00 cmp r3, #0
- 8001e56: d001 beq.n 8001e5c <SystemClock_Config+0x7c>
+ 8001ea4: f107 031c add.w r3, r7, #28
+ 8001ea8: 4618 mov r0, r3
+ 8001eaa: f7fe fe33 bl 8000b14 <HAL_RCC_OscConfig>
+ 8001eae: 4603 mov r3, r0
+ 8001eb0: 2b00 cmp r3, #0
+ 8001eb2: d001 beq.n 8001eb8 <SystemClock_Config+0x7c>
{
Error_Handler();
- 8001e58: f000 f8ae bl 8001fb8 <Error_Handler>
+ 8001eb4: f000 f890 bl 8001fd8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 8001e5c: 230f movs r3, #15
- 8001e5e: 60bb str r3, [r7, #8]
+ 8001eb8: 230f movs r3, #15
+ 8001eba: 60bb str r3, [r7, #8]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 8001e60: 2300 movs r3, #0
- 8001e62: 60fb str r3, [r7, #12]
+ 8001ebc: 2300 movs r3, #0
+ 8001ebe: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8001e64: 2300 movs r3, #0
- 8001e66: 613b str r3, [r7, #16]
+ 8001ec0: 2300 movs r3, #0
+ 8001ec2: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8001e68: 2300 movs r3, #0
- 8001e6a: 617b str r3, [r7, #20]
+ 8001ec4: 2300 movs r3, #0
+ 8001ec6: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8001e6c: 2300 movs r3, #0
- 8001e6e: 61bb str r3, [r7, #24]
+ 8001ec8: 2300 movs r3, #0
+ 8001eca: 61bb str r3, [r7, #24]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 8001e70: f107 0308 add.w r3, r7, #8
- 8001e74: 2100 movs r1, #0
- 8001e76: 4618 mov r0, r3
- 8001e78: f7ff f8e0 bl 800103c <HAL_RCC_ClockConfig>
- 8001e7c: 4603 mov r3, r0
- 8001e7e: 2b00 cmp r3, #0
- 8001e80: d001 beq.n 8001e86 <SystemClock_Config+0xa6>
+ 8001ecc: f107 0308 add.w r3, r7, #8
+ 8001ed0: 2100 movs r1, #0
+ 8001ed2: 4618 mov r0, r3
+ 8001ed4: f7ff f890 bl 8000ff8 <HAL_RCC_ClockConfig>
+ 8001ed8: 4603 mov r3, r0
+ 8001eda: 2b00 cmp r3, #0
+ 8001edc: d001 beq.n 8001ee2 <SystemClock_Config+0xa6>
{
Error_Handler();
- 8001e82: f000 f899 bl 8001fb8 <Error_Handler>
+ 8001ede: f000 f87b bl 8001fd8 <Error_Handler>
}
}
- 8001e86: bf00 nop
- 8001e88: 3750 adds r7, #80 ; 0x50
- 8001e8a: 46bd mov sp, r7
- 8001e8c: bd80 pop {r7, pc}
- 8001e8e: bf00 nop
- 8001e90: 40023800 .word 0x40023800
- 8001e94: 40007000 .word 0x40007000
-
-08001e98 <MX_TIM4_Init>:
+ 8001ee2: bf00 nop
+ 8001ee4: 3750 adds r7, #80 ; 0x50
+ 8001ee6: 46bd mov sp, r7
+ 8001ee8: bd80 pop {r7, pc}
+ 8001eea: bf00 nop
+ 8001eec: 40023800 .word 0x40023800
+ 8001ef0: 40007000 .word 0x40007000
+
+08001ef4 <MX_TIM4_Init>:
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
- 8001e98: b580 push {r7, lr}
- 8001e9a: b08a sub sp, #40 ; 0x28
- 8001e9c: af00 add r7, sp, #0
+ 8001ef4: b580 push {r7, lr}
+ 8001ef6: b08a sub sp, #40 ; 0x28
+ 8001ef8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
- 8001e9e: f107 031c add.w r3, r7, #28
- 8001ea2: 2200 movs r2, #0
- 8001ea4: 601a str r2, [r3, #0]
- 8001ea6: 605a str r2, [r3, #4]
- 8001ea8: 609a str r2, [r3, #8]
+ 8001efa: f107 031c add.w r3, r7, #28
+ 8001efe: 2200 movs r2, #0
+ 8001f00: 601a str r2, [r3, #0]
+ 8001f02: 605a str r2, [r3, #4]
+ 8001f04: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
- 8001eaa: 463b mov r3, r7
- 8001eac: 2200 movs r2, #0
- 8001eae: 601a str r2, [r3, #0]
- 8001eb0: 605a str r2, [r3, #4]
- 8001eb2: 609a str r2, [r3, #8]
- 8001eb4: 60da str r2, [r3, #12]
- 8001eb6: 611a str r2, [r3, #16]
- 8001eb8: 615a str r2, [r3, #20]
- 8001eba: 619a str r2, [r3, #24]
+ 8001f06: 463b mov r3, r7
+ 8001f08: 2200 movs r2, #0
+ 8001f0a: 601a str r2, [r3, #0]
+ 8001f0c: 605a str r2, [r3, #4]
+ 8001f0e: 609a str r2, [r3, #8]
+ 8001f10: 60da str r2, [r3, #12]
+ 8001f12: 611a str r2, [r3, #16]
+ 8001f14: 615a str r2, [r3, #20]
+ 8001f16: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
- 8001ebc: 4b21 ldr r3, [pc, #132] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001ebe: 4a22 ldr r2, [pc, #136] ; (8001f48 <MX_TIM4_Init+0xb0>)
- 8001ec0: 601a str r2, [r3, #0]
+ 8001f18: 4b21 ldr r3, [pc, #132] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f1a: 4a22 ldr r2, [pc, #136] ; (8001fa4 <MX_TIM4_Init+0xb0>)
+ 8001f1c: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 0;
- 8001ec2: 4b20 ldr r3, [pc, #128] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001ec4: 2200 movs r2, #0
- 8001ec6: 605a str r2, [r3, #4]
+ 8001f1e: 4b20 ldr r3, [pc, #128] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f20: 2200 movs r2, #0
+ 8001f22: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001ec8: 4b1e ldr r3, [pc, #120] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001eca: 2200 movs r2, #0
- 8001ecc: 609a str r2, [r3, #8]
+ 8001f24: 4b1e ldr r3, [pc, #120] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f26: 2200 movs r2, #0
+ 8001f28: 609a str r2, [r3, #8]
htim4.Init.Period = 799;
- 8001ece: 4b1d ldr r3, [pc, #116] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001ed0: f240 321f movw r2, #799 ; 0x31f
- 8001ed4: 60da str r2, [r3, #12]
+ 8001f2a: 4b1d ldr r3, [pc, #116] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f2c: f240 321f movw r2, #799 ; 0x31f
+ 8001f30: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8001ed6: 4b1b ldr r3, [pc, #108] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001ed8: 2200 movs r2, #0
- 8001eda: 611a str r2, [r3, #16]
+ 8001f32: 4b1b ldr r3, [pc, #108] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f34: 2200 movs r2, #0
+ 8001f36: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001edc: 4b19 ldr r3, [pc, #100] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001ede: 2200 movs r2, #0
- 8001ee0: 619a str r2, [r3, #24]
+ 8001f38: 4b19 ldr r3, [pc, #100] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f3a: 2200 movs r2, #0
+ 8001f3c: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
- 8001ee2: 4818 ldr r0, [pc, #96] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001ee4: f7ff fa44 bl 8001370 <HAL_TIM_PWM_Init>
- 8001ee8: 4603 mov r3, r0
- 8001eea: 2b00 cmp r3, #0
- 8001eec: d001 beq.n 8001ef2 <MX_TIM4_Init+0x5a>
+ 8001f3e: 4818 ldr r0, [pc, #96] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f40: f7ff f9f4 bl 800132c <HAL_TIM_PWM_Init>
+ 8001f44: 4603 mov r3, r0
+ 8001f46: 2b00 cmp r3, #0
+ 8001f48: d001 beq.n 8001f4e <MX_TIM4_Init+0x5a>
{
Error_Handler();
- 8001eee: f000 f863 bl 8001fb8 <Error_Handler>
+ 8001f4a: f000 f845 bl 8001fd8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001ef2: 2300 movs r3, #0
- 8001ef4: 61fb str r3, [r7, #28]
+ 8001f4e: 2300 movs r3, #0
+ 8001f50: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8001ef6: 2300 movs r3, #0
- 8001ef8: 627b str r3, [r7, #36] ; 0x24
+ 8001f52: 2300 movs r3, #0
+ 8001f54: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
- 8001efa: f107 031c add.w r3, r7, #28
- 8001efe: 4619 mov r1, r3
- 8001f00: 4810 ldr r0, [pc, #64] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001f02: f7ff fee1 bl 8001cc8 <HAL_TIMEx_MasterConfigSynchronization>
- 8001f06: 4603 mov r3, r0
- 8001f08: 2b00 cmp r3, #0
- 8001f0a: d001 beq.n 8001f10 <MX_TIM4_Init+0x78>
+ 8001f56: f107 031c add.w r3, r7, #28
+ 8001f5a: 4619 mov r1, r3
+ 8001f5c: 4810 ldr r0, [pc, #64] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f5e: f7ff fee9 bl 8001d34 <HAL_TIMEx_MasterConfigSynchronization>
+ 8001f62: 4603 mov r3, r0
+ 8001f64: 2b00 cmp r3, #0
+ 8001f66: d001 beq.n 8001f6c <MX_TIM4_Init+0x78>
{
Error_Handler();
- 8001f0c: f000 f854 bl 8001fb8 <Error_Handler>
+ 8001f68: f000 f836 bl 8001fd8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8001f10: 2360 movs r3, #96 ; 0x60
- 8001f12: 603b str r3, [r7, #0]
+ 8001f6c: 2360 movs r3, #96 ; 0x60
+ 8001f6e: 603b str r3, [r7, #0]
sConfigOC.Pulse = 0;
- 8001f14: 2300 movs r3, #0
- 8001f16: 607b str r3, [r7, #4]
+ 8001f70: 2300 movs r3, #0
+ 8001f72: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 8001f18: 2300 movs r3, #0
- 8001f1a: 60bb str r3, [r7, #8]
+ 8001f74: 2300 movs r3, #0
+ 8001f76: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 8001f1c: 2300 movs r3, #0
- 8001f1e: 613b str r3, [r7, #16]
+ 8001f78: 2300 movs r3, #0
+ 8001f7a: 613b str r3, [r7, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
- 8001f20: 463b mov r3, r7
- 8001f22: 220c movs r2, #12
- 8001f24: 4619 mov r1, r3
- 8001f26: 4807 ldr r0, [pc, #28] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001f28: f7ff fa92 bl 8001450 <HAL_TIM_PWM_ConfigChannel>
- 8001f2c: 4603 mov r3, r0
- 8001f2e: 2b00 cmp r3, #0
- 8001f30: d001 beq.n 8001f36 <MX_TIM4_Init+0x9e>
+ 8001f7c: 463b mov r3, r7
+ 8001f7e: 220c movs r2, #12
+ 8001f80: 4619 mov r1, r3
+ 8001f82: 4807 ldr r0, [pc, #28] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f84: f7ff fa9a bl 80014bc <HAL_TIM_PWM_ConfigChannel>
+ 8001f88: 4603 mov r3, r0
+ 8001f8a: 2b00 cmp r3, #0
+ 8001f8c: d001 beq.n 8001f92 <MX_TIM4_Init+0x9e>
{
Error_Handler();
- 8001f32: f000 f841 bl 8001fb8 <Error_Handler>
+ 8001f8e: f000 f823 bl 8001fd8 <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
- 8001f36: 4803 ldr r0, [pc, #12] ; (8001f44 <MX_TIM4_Init+0xac>)
- 8001f38: f000 f88a bl 8002050 <HAL_TIM_MspPostInit>
+ 8001f92: 4803 ldr r0, [pc, #12] ; (8001fa0 <MX_TIM4_Init+0xac>)
+ 8001f94: f000 f894 bl 80020c0 <HAL_TIM_MspPostInit>
}
- 8001f3c: bf00 nop
- 8001f3e: 3728 adds r7, #40 ; 0x28
- 8001f40: 46bd mov sp, r7
- 8001f42: bd80 pop {r7, pc}
- 8001f44: 2000002c .word 0x2000002c
- 8001f48: 40000800 .word 0x40000800
-
-08001f4c <MX_GPIO_Init>:
+ 8001f98: bf00 nop
+ 8001f9a: 3728 adds r7, #40 ; 0x28
+ 8001f9c: 46bd mov sp, r7
+ 8001f9e: bd80 pop {r7, pc}
+ 8001fa0: 2000002c .word 0x2000002c
+ 8001fa4: 40000800 .word 0x40000800
+
+08001fa8 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
- 8001f4c: b480 push {r7}
- 8001f4e: b083 sub sp, #12
- 8001f50: af00 add r7, sp, #0
+ 8001fa8: b480 push {r7}
+ 8001faa: b083 sub sp, #12
+ 8001fac: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOD_CLK_ENABLE();
- 8001f52: 4b09 ldr r3, [pc, #36] ; (8001f78 <MX_GPIO_Init+0x2c>)
- 8001f54: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001f56: 4a08 ldr r2, [pc, #32] ; (8001f78 <MX_GPIO_Init+0x2c>)
- 8001f58: f043 0308 orr.w r3, r3, #8
- 8001f5c: 6313 str r3, [r2, #48] ; 0x30
- 8001f5e: 4b06 ldr r3, [pc, #24] ; (8001f78 <MX_GPIO_Init+0x2c>)
- 8001f60: 6b1b ldr r3, [r3, #48] ; 0x30
- 8001f62: f003 0308 and.w r3, r3, #8
- 8001f66: 607b str r3, [r7, #4]
- 8001f68: 687b ldr r3, [r7, #4]
+ 8001fae: 4b09 ldr r3, [pc, #36] ; (8001fd4 <MX_GPIO_Init+0x2c>)
+ 8001fb0: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001fb2: 4a08 ldr r2, [pc, #32] ; (8001fd4 <MX_GPIO_Init+0x2c>)
+ 8001fb4: f043 0308 orr.w r3, r3, #8
+ 8001fb8: 6313 str r3, [r2, #48] ; 0x30
+ 8001fba: 4b06 ldr r3, [pc, #24] ; (8001fd4 <MX_GPIO_Init+0x2c>)
+ 8001fbc: 6b1b ldr r3, [r3, #48] ; 0x30
+ 8001fbe: f003 0308 and.w r3, r3, #8
+ 8001fc2: 607b str r3, [r7, #4]
+ 8001fc4: 687b ldr r3, [r7, #4]
}
- 8001f6a: bf00 nop
- 8001f6c: 370c adds r7, #12
- 8001f6e: 46bd mov sp, r7
- 8001f70: f85d 7b04 ldr.w r7, [sp], #4
- 8001f74: 4770 bx lr
- 8001f76: bf00 nop
- 8001f78: 40023800 .word 0x40023800
-
-08001f7c <user_pwm_setvalue>:
-
-/* USER CODE BEGIN 4 */
-void user_pwm_setvalue(uint16_t value) {
- 8001f7c: b580 push {r7, lr}
- 8001f7e: b08a sub sp, #40 ; 0x28
- 8001f80: af00 add r7, sp, #0
- 8001f82: 4603 mov r3, r0
- 8001f84: 80fb strh r3, [r7, #6]
- TIM_OC_InitTypeDef sConfigOC;
-
- sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8001f86: 2360 movs r3, #96 ; 0x60
- 8001f88: 60fb str r3, [r7, #12]
- sConfigOC.Pulse = value;
- 8001f8a: 88fb ldrh r3, [r7, #6]
- 8001f8c: 613b str r3, [r7, #16]
- sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 8001f8e: 2300 movs r3, #0
- 8001f90: 617b str r3, [r7, #20]
- sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 8001f92: 2300 movs r3, #0
- 8001f94: 61fb str r3, [r7, #28]
- HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4);
- 8001f96: f107 030c add.w r3, r7, #12
- 8001f9a: 220c movs r2, #12
- 8001f9c: 4619 mov r1, r3
- 8001f9e: 4805 ldr r0, [pc, #20] ; (8001fb4 <user_pwm_setvalue+0x38>)
- 8001fa0: f7ff fa56 bl 8001450 <HAL_TIM_PWM_ConfigChannel>
- HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4);
- 8001fa4: 210c movs r1, #12
- 8001fa6: 4803 ldr r0, [pc, #12] ; (8001fb4 <user_pwm_setvalue+0x38>)
- 8001fa8: f7ff fa0e bl 80013c8 <HAL_TIM_PWM_Start>
-}
- 8001fac: bf00 nop
- 8001fae: 3728 adds r7, #40 ; 0x28
- 8001fb0: 46bd mov sp, r7
- 8001fb2: bd80 pop {r7, pc}
- 8001fb4: 2000002c .word 0x2000002c
-
-08001fb8 <Error_Handler>:
+ 8001fc6: bf00 nop
+ 8001fc8: 370c adds r7, #12
+ 8001fca: 46bd mov sp, r7
+ 8001fcc: f85d 7b04 ldr.w r7, [sp], #4
+ 8001fd0: 4770 bx lr
+ 8001fd2: bf00 nop
+ 8001fd4: 40023800 .word 0x40023800
+
+08001fd8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
- 8001fb8: b480 push {r7}
- 8001fba: af00 add r7, sp, #0
+ 8001fd8: b480 push {r7}
+ 8001fda: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
- 8001fbc: bf00 nop
- 8001fbe: 46bd mov sp, r7
- 8001fc0: f85d 7b04 ldr.w r7, [sp], #4
- 8001fc4: 4770 bx lr
- ...
-
-08001fc8 <HAL_MspInit>:
+ 8001fdc: bf00 nop
+ 8001fde: 46bd mov sp, r7
+ 8001fe0: f85d 7b04 ldr.w r7, [sp], #4
+ 8001fe4: 4770 bx lr
+
+08001fe6 <setPWM>:
+#include "stm32f7xx_hal.h"
+#include <stdint.h>
+
+void setPWM(TIM_HandleTypeDef timer, uint32_t channel, uint16_t pulse) {
+ 8001fe6: b084 sub sp, #16
+ 8001fe8: b580 push {r7, lr}
+ 8001fea: b088 sub sp, #32
+ 8001fec: af00 add r7, sp, #0
+ 8001fee: f107 0c28 add.w ip, r7, #40 ; 0x28
+ 8001ff2: e88c 000f stmia.w ip, {r0, r1, r2, r3}
+ HAL_TIM_PWM_Stop(&timer, channel); // stop generation of pwm
+ 8001ff6: 6eb9 ldr r1, [r7, #104] ; 0x68
+ 8001ff8: f107 0028 add.w r0, r7, #40 ; 0x28
+ 8001ffc: f7ff fa06 bl 800140c <HAL_TIM_PWM_Stop>
+ TIM_OC_InitTypeDef sConfigOC;
+ sConfigOC.OCMode = TIM_OCMODE_PWM1;
+ 8002000: 2360 movs r3, #96 ; 0x60
+ 8002002: 607b str r3, [r7, #4]
+ sConfigOC.Pulse = pulse; // set the pulse duration
+ 8002004: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c
+ 8002008: 60bb str r3, [r7, #8]
+ sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 800200a: 2300 movs r3, #0
+ 800200c: 60fb str r3, [r7, #12]
+ sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ 800200e: 2300 movs r3, #0
+ 8002010: 617b str r3, [r7, #20]
+ HAL_TIM_PWM_ConfigChannel(&timer, &sConfigOC, channel);
+ 8002012: 1d3b adds r3, r7, #4
+ 8002014: 6eba ldr r2, [r7, #104] ; 0x68
+ 8002016: 4619 mov r1, r3
+ 8002018: f107 0028 add.w r0, r7, #40 ; 0x28
+ 800201c: f7ff fa4e bl 80014bc <HAL_TIM_PWM_ConfigChannel>
+ HAL_TIM_PWM_Start(&timer, channel); // start pwm generation
+ 8002020: 6eb9 ldr r1, [r7, #104] ; 0x68
+ 8002022: f107 0028 add.w r0, r7, #40 ; 0x28
+ 8002026: f7ff f9ad bl 8001384 <HAL_TIM_PWM_Start>
+}
+ 800202a: bf00 nop
+ 800202c: 3720 adds r7, #32
+ 800202e: 46bd mov sp, r7
+ 8002030: e8bd 4080 ldmia.w sp!, {r7, lr}
+ 8002034: b004 add sp, #16
+ 8002036: 4770 bx lr
+
+08002038 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
- 8001fc8: b480 push {r7}
- 8001fca: b083 sub sp, #12
- 8001fcc: af00 add r7, sp, #0
+ 8002038: b480 push {r7}
+ 800203a: b083 sub sp, #12
+ 800203c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
- 8001fce: 4b0f ldr r3, [pc, #60] ; (800200c <HAL_MspInit+0x44>)
- 8001fd0: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001fd2: 4a0e ldr r2, [pc, #56] ; (800200c <HAL_MspInit+0x44>)
- 8001fd4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
- 8001fd8: 6413 str r3, [r2, #64] ; 0x40
- 8001fda: 4b0c ldr r3, [pc, #48] ; (800200c <HAL_MspInit+0x44>)
- 8001fdc: 6c1b ldr r3, [r3, #64] ; 0x40
- 8001fde: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
- 8001fe2: 607b str r3, [r7, #4]
- 8001fe4: 687b ldr r3, [r7, #4]
+ 800203e: 4b0f ldr r3, [pc, #60] ; (800207c <HAL_MspInit+0x44>)
+ 8002040: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002042: 4a0e ldr r2, [pc, #56] ; (800207c <HAL_MspInit+0x44>)
+ 8002044: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
+ 8002048: 6413 str r3, [r2, #64] ; 0x40
+ 800204a: 4b0c ldr r3, [pc, #48] ; (800207c <HAL_MspInit+0x44>)
+ 800204c: 6c1b ldr r3, [r3, #64] ; 0x40
+ 800204e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
+ 8002052: 607b str r3, [r7, #4]
+ 8002054: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 8001fe6: 4b09 ldr r3, [pc, #36] ; (800200c <HAL_MspInit+0x44>)
- 8001fe8: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001fea: 4a08 ldr r2, [pc, #32] ; (800200c <HAL_MspInit+0x44>)
- 8001fec: f443 4380 orr.w r3, r3, #16384 ; 0x4000
- 8001ff0: 6453 str r3, [r2, #68] ; 0x44
- 8001ff2: 4b06 ldr r3, [pc, #24] ; (800200c <HAL_MspInit+0x44>)
- 8001ff4: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001ff6: f403 4380 and.w r3, r3, #16384 ; 0x4000
- 8001ffa: 603b str r3, [r7, #0]
- 8001ffc: 683b ldr r3, [r7, #0]
+ 8002056: 4b09 ldr r3, [pc, #36] ; (800207c <HAL_MspInit+0x44>)
+ 8002058: 6c5b ldr r3, [r3, #68] ; 0x44
+ 800205a: 4a08 ldr r2, [pc, #32] ; (800207c <HAL_MspInit+0x44>)
+ 800205c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
+ 8002060: 6453 str r3, [r2, #68] ; 0x44
+ 8002062: 4b06 ldr r3, [pc, #24] ; (800207c <HAL_MspInit+0x44>)
+ 8002064: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8002066: f403 4380 and.w r3, r3, #16384 ; 0x4000
+ 800206a: 603b str r3, [r7, #0]
+ 800206c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
- 8001ffe: bf00 nop
- 8002000: 370c adds r7, #12
- 8002002: 46bd mov sp, r7
- 8002004: f85d 7b04 ldr.w r7, [sp], #4
- 8002008: 4770 bx lr
- 800200a: bf00 nop
- 800200c: 40023800 .word 0x40023800
-
-08002010 <HAL_TIM_PWM_MspInit>:
+ 800206e: bf00 nop
+ 8002070: 370c adds r7, #12
+ 8002072: 46bd mov sp, r7
+ 8002074: f85d 7b04 ldr.w r7, [sp], #4
+ 8002078: 4770 bx lr
+ 800207a: bf00 nop
+ 800207c: 40023800 .word 0x40023800
+
+08002080 <HAL_TIM_PWM_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer
* @retval None
*/
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{
- 8002010: b480 push {r7}
- 8002012: b085 sub sp, #20
- 8002014: af00 add r7, sp, #0
- 8002016: 6078 str r0, [r7, #4]
+ 8002080: b480 push {r7}
+ 8002082: b085 sub sp, #20
+ 8002084: af00 add r7, sp, #0
+ 8002086: 6078 str r0, [r7, #4]
if(htim_pwm->Instance==TIM4)
- 8002018: 687b ldr r3, [r7, #4]
- 800201a: 681b ldr r3, [r3, #0]
- 800201c: 4a0a ldr r2, [pc, #40] ; (8002048 <HAL_TIM_PWM_MspInit+0x38>)
- 800201e: 4293 cmp r3, r2
- 8002020: d10b bne.n 800203a <HAL_TIM_PWM_MspInit+0x2a>
+ 8002088: 687b ldr r3, [r7, #4]
+ 800208a: 681b ldr r3, [r3, #0]
+ 800208c: 4a0a ldr r2, [pc, #40] ; (80020b8 <HAL_TIM_PWM_MspInit+0x38>)
+ 800208e: 4293 cmp r3, r2
+ 8002090: d10b bne.n 80020aa <HAL_TIM_PWM_MspInit+0x2a>
{
/* USER CODE BEGIN TIM4_MspInit 0 */
/* USER CODE END TIM4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM4_CLK_ENABLE();
- 8002022: 4b0a ldr r3, [pc, #40] ; (800204c <HAL_TIM_PWM_MspInit+0x3c>)
- 8002024: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002026: 4a09 ldr r2, [pc, #36] ; (800204c <HAL_TIM_PWM_MspInit+0x3c>)
- 8002028: f043 0304 orr.w r3, r3, #4
- 800202c: 6413 str r3, [r2, #64] ; 0x40
- 800202e: 4b07 ldr r3, [pc, #28] ; (800204c <HAL_TIM_PWM_MspInit+0x3c>)
- 8002030: 6c1b ldr r3, [r3, #64] ; 0x40
- 8002032: f003 0304 and.w r3, r3, #4
- 8002036: 60fb str r3, [r7, #12]
- 8002038: 68fb ldr r3, [r7, #12]
+ 8002092: 4b0a ldr r3, [pc, #40] ; (80020bc <HAL_TIM_PWM_MspInit+0x3c>)
+ 8002094: 6c1b ldr r3, [r3, #64] ; 0x40
+ 8002096: 4a09 ldr r2, [pc, #36] ; (80020bc <HAL_TIM_PWM_MspInit+0x3c>)
+ 8002098: f043 0304 orr.w r3, r3, #4
+ 800209c: 6413 str r3, [r2, #64] ; 0x40
+ 800209e: 4b07 ldr r3, [pc, #28] ; (80020bc <HAL_TIM_PWM_MspInit+0x3c>)
+ 80020a0: 6c1b ldr r3, [r3, #64] ; 0x40
+ 80020a2: f003 0304 and.w r3, r3, #4
+ 80020a6: 60fb str r3, [r7, #12]
+ 80020a8: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
- 800203a: bf00 nop
- 800203c: 3714 adds r7, #20
- 800203e: 46bd mov sp, r7
- 8002040: f85d 7b04 ldr.w r7, [sp], #4
- 8002044: 4770 bx lr
- 8002046: bf00 nop
- 8002048: 40000800 .word 0x40000800
- 800204c: 40023800 .word 0x40023800
+ 80020aa: bf00 nop
+ 80020ac: 3714 adds r7, #20
+ 80020ae: 46bd mov sp, r7
+ 80020b0: f85d 7b04 ldr.w r7, [sp], #4
+ 80020b4: 4770 bx lr
+ 80020b6: bf00 nop
+ 80020b8: 40000800 .word 0x40000800
+ 80020bc: 40023800 .word 0x40023800
-08002050 <HAL_TIM_MspPostInit>:
+080020c0 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
- 8002050: b580 push {r7, lr}
- 8002052: b088 sub sp, #32
- 8002054: af00 add r7, sp, #0
- 8002056: 6078 str r0, [r7, #4]
+ 80020c0: b580 push {r7, lr}
+ 80020c2: b088 sub sp, #32
+ 80020c4: af00 add r7, sp, #0
+ 80020c6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8002058: f107 030c add.w r3, r7, #12
- 800205c: 2200 movs r2, #0
- 800205e: 601a str r2, [r3, #0]
- 8002060: 605a str r2, [r3, #4]
- 8002062: 609a str r2, [r3, #8]
- 8002064: 60da str r2, [r3, #12]
- 8002066: 611a str r2, [r3, #16]
+ 80020c8: f107 030c add.w r3, r7, #12
+ 80020cc: 2200 movs r2, #0
+ 80020ce: 601a str r2, [r3, #0]
+ 80020d0: 605a str r2, [r3, #4]
+ 80020d2: 609a str r2, [r3, #8]
+ 80020d4: 60da str r2, [r3, #12]
+ 80020d6: 611a str r2, [r3, #16]
if(htim->Instance==TIM4)
- 8002068: 687b ldr r3, [r7, #4]
- 800206a: 681b ldr r3, [r3, #0]
- 800206c: 4a11 ldr r2, [pc, #68] ; (80020b4 <HAL_TIM_MspPostInit+0x64>)
- 800206e: 4293 cmp r3, r2
- 8002070: d11c bne.n 80020ac <HAL_TIM_MspPostInit+0x5c>
+ 80020d8: 687b ldr r3, [r7, #4]
+ 80020da: 681b ldr r3, [r3, #0]
+ 80020dc: 4a11 ldr r2, [pc, #68] ; (8002124 <HAL_TIM_MspPostInit+0x64>)
+ 80020de: 4293 cmp r3, r2
+ 80020e0: d11c bne.n 800211c <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM4_MspPostInit 0 */
/* USER CODE END TIM4_MspPostInit 0 */
__HAL_RCC_GPIOD_CLK_ENABLE();
- 8002072: 4b11 ldr r3, [pc, #68] ; (80020b8 <HAL_TIM_MspPostInit+0x68>)
- 8002074: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002076: 4a10 ldr r2, [pc, #64] ; (80020b8 <HAL_TIM_MspPostInit+0x68>)
- 8002078: f043 0308 orr.w r3, r3, #8
- 800207c: 6313 str r3, [r2, #48] ; 0x30
- 800207e: 4b0e ldr r3, [pc, #56] ; (80020b8 <HAL_TIM_MspPostInit+0x68>)
- 8002080: 6b1b ldr r3, [r3, #48] ; 0x30
- 8002082: f003 0308 and.w r3, r3, #8
- 8002086: 60bb str r3, [r7, #8]
- 8002088: 68bb ldr r3, [r7, #8]
+ 80020e2: 4b11 ldr r3, [pc, #68] ; (8002128 <HAL_TIM_MspPostInit+0x68>)
+ 80020e4: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80020e6: 4a10 ldr r2, [pc, #64] ; (8002128 <HAL_TIM_MspPostInit+0x68>)
+ 80020e8: f043 0308 orr.w r3, r3, #8
+ 80020ec: 6313 str r3, [r2, #48] ; 0x30
+ 80020ee: 4b0e ldr r3, [pc, #56] ; (8002128 <HAL_TIM_MspPostInit+0x68>)
+ 80020f0: 6b1b ldr r3, [r3, #48] ; 0x30
+ 80020f2: f003 0308 and.w r3, r3, #8
+ 80020f6: 60bb str r3, [r7, #8]
+ 80020f8: 68bb ldr r3, [r7, #8]
/**TIM4 GPIO Configuration
PD15 ------> TIM4_CH4
*/
GPIO_InitStruct.Pin = GPIO_PIN_15;
- 800208a: f44f 4300 mov.w r3, #32768 ; 0x8000
- 800208e: 60fb str r3, [r7, #12]
+ 80020fa: f44f 4300 mov.w r3, #32768 ; 0x8000
+ 80020fe: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8002090: 2302 movs r3, #2
- 8002092: 613b str r3, [r7, #16]
+ 8002100: 2302 movs r3, #2
+ 8002102: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8002094: 2300 movs r3, #0
- 8002096: 617b str r3, [r7, #20]
+ 8002104: 2300 movs r3, #0
+ 8002106: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
- 8002098: 2302 movs r3, #2
- 800209a: 61bb str r3, [r7, #24]
+ 8002108: 2302 movs r3, #2
+ 800210a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
- 800209c: 2302 movs r3, #2
- 800209e: 61fb str r3, [r7, #28]
+ 800210c: 2302 movs r3, #2
+ 800210e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
- 80020a0: f107 030c add.w r3, r7, #12
- 80020a4: 4619 mov r1, r3
- 80020a6: 4805 ldr r0, [pc, #20] ; (80020bc <HAL_TIM_MspPostInit+0x6c>)
- 80020a8: f7fe fbac bl 8000804 <HAL_GPIO_Init>
+ 8002110: f107 030c add.w r3, r7, #12
+ 8002114: 4619 mov r1, r3
+ 8002116: 4805 ldr r0, [pc, #20] ; (800212c <HAL_TIM_MspPostInit+0x6c>)
+ 8002118: f7fe fb52 bl 80007c0 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
- 80020ac: bf00 nop
- 80020ae: 3720 adds r7, #32
- 80020b0: 46bd mov sp, r7
- 80020b2: bd80 pop {r7, pc}
- 80020b4: 40000800 .word 0x40000800
- 80020b8: 40023800 .word 0x40023800
- 80020bc: 40020c00 .word 0x40020c00
-
-080020c0 <NMI_Handler>:
+ 800211c: bf00 nop
+ 800211e: 3720 adds r7, #32
+ 8002120: 46bd mov sp, r7
+ 8002122: bd80 pop {r7, pc}
+ 8002124: 40000800 .word 0x40000800
+ 8002128: 40023800 .word 0x40023800
+ 800212c: 40020c00 .word 0x40020c00
+
+08002130 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
- 80020c0: b480 push {r7}
- 80020c2: af00 add r7, sp, #0
+ 8002130: b480 push {r7}
+ 8002132: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
- 80020c4: bf00 nop
- 80020c6: 46bd mov sp, r7
- 80020c8: f85d 7b04 ldr.w r7, [sp], #4
- 80020cc: 4770 bx lr
+ 8002134: bf00 nop
+ 8002136: 46bd mov sp, r7
+ 8002138: f85d 7b04 ldr.w r7, [sp], #4
+ 800213c: 4770 bx lr
-080020ce <HardFault_Handler>:
+0800213e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
- 80020ce: b480 push {r7}
- 80020d0: af00 add r7, sp, #0
+ 800213e: b480 push {r7}
+ 8002140: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
- 80020d2: e7fe b.n 80020d2 <HardFault_Handler+0x4>
+ 8002142: e7fe b.n 8002142 <HardFault_Handler+0x4>
-080020d4 <MemManage_Handler>:
+08002144 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
- 80020d4: b480 push {r7}
- 80020d6: af00 add r7, sp, #0
+ 8002144: b480 push {r7}
+ 8002146: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
- 80020d8: e7fe b.n 80020d8 <MemManage_Handler+0x4>
+ 8002148: e7fe b.n 8002148 <MemManage_Handler+0x4>
-080020da <BusFault_Handler>:
+0800214a <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
- 80020da: b480 push {r7}
- 80020dc: af00 add r7, sp, #0
+ 800214a: b480 push {r7}
+ 800214c: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
- 80020de: e7fe b.n 80020de <BusFault_Handler+0x4>
+ 800214e: e7fe b.n 800214e <BusFault_Handler+0x4>
-080020e0 <UsageFault_Handler>:
+08002150 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
- 80020e0: b480 push {r7}
- 80020e2: af00 add r7, sp, #0
+ 8002150: b480 push {r7}
+ 8002152: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
- 80020e4: e7fe b.n 80020e4 <UsageFault_Handler+0x4>
+ 8002154: e7fe b.n 8002154 <UsageFault_Handler+0x4>
-080020e6 <SVC_Handler>:
+08002156 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
- 80020e6: b480 push {r7}
- 80020e8: af00 add r7, sp, #0
+ 8002156: b480 push {r7}
+ 8002158: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
- 80020ea: bf00 nop
- 80020ec: 46bd mov sp, r7
- 80020ee: f85d 7b04 ldr.w r7, [sp], #4
- 80020f2: 4770 bx lr
+ 800215a: bf00 nop
+ 800215c: 46bd mov sp, r7
+ 800215e: f85d 7b04 ldr.w r7, [sp], #4
+ 8002162: 4770 bx lr
-080020f4 <DebugMon_Handler>:
+08002164 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
- 80020f4: b480 push {r7}
- 80020f6: af00 add r7, sp, #0
+ 8002164: b480 push {r7}
+ 8002166: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
- 80020f8: bf00 nop
- 80020fa: 46bd mov sp, r7
- 80020fc: f85d 7b04 ldr.w r7, [sp], #4
- 8002100: 4770 bx lr
+ 8002168: bf00 nop
+ 800216a: 46bd mov sp, r7
+ 800216c: f85d 7b04 ldr.w r7, [sp], #4
+ 8002170: 4770 bx lr
-080021
02 <PendSV_Handler>:
+080021
72 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
- 8002102: b480 push {r7}
- 8002104: af00 add r7, sp, #0
+ 8002172: b480 push {r7}
+ 8002174: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
- 8002106: bf00 nop
- 8002108: 46bd mov sp, r7
- 800210a: f85d 7b04 ldr.w r7, [sp], #4
- 800210e: 4770 bx lr
+ 8002176: bf00 nop
+ 8002178: 46bd mov sp, r7
+ 800217a: f85d 7b04 ldr.w r7, [sp], #4
+ 800217e: 4770 bx lr
-08002110 <SysTick_Handler>:
+08002180 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
- 8002110: b580 push {r7, lr}
- 8002112: af00 add r7, sp, #0
+ 8002180: b580 push {r7, lr}
+ 8002182: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
- 8002114: f7fe fa4e bl 80005b4 <HAL_IncTick>
+ 8002184: f7fe fa16 bl 80005b4 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
- 8002118: bf00 nop
- 800211a: bd80 pop {r7, pc}
+ 8002188: bf00 nop
+ 800218a: bd80 pop {r7, pc}
-0800211c <SystemInit>:
+0800218c <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
- 800211c: b480 push {r7}
- 800211e: af00 add r7, sp, #0
+ 800218c: b480 push {r7}
+ 800218e: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- 8002120: 4b15 ldr r3, [pc, #84] ; (8002178 <SystemInit+0x5c>)
- 8002122: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
- 8002126: 4a14 ldr r2, [pc, #80] ; (8002178 <SystemInit+0x5c>)
- 8002128: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
- 800212c: f8c2 3088 str.w r3, [r2, #136] ; 0x88
+ 8002190: 4b15 ldr r3, [pc, #84] ; (80021e8 <SystemInit+0x5c>)
+ 8002192: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
+ 8002196: 4a14 ldr r2, [pc, #80] ; (80021e8 <SystemInit+0x5c>)
+ 8002198: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
+ 800219c: f8c2 3088 str.w r3, [r2, #136] ; 0x88
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
- 8002130: 4b12 ldr r3, [pc, #72] ; (800217c <SystemInit+0x60>)
- 8002132: 681b ldr r3, [r3, #0]
- 8002134: 4a11 ldr r2, [pc, #68] ; (800217c <SystemInit+0x60>)
- 8002136: f043 0301 orr.w r3, r3, #1
- 800213a: 6013 str r3, [r2, #0]
+ 80021a0: 4b12 ldr r3, [pc, #72] ; (80021ec <SystemInit+0x60>)
+ 80021a2: 681b ldr r3, [r3, #0]
+ 80021a4: 4a11 ldr r2, [pc, #68] ; (80021ec <SystemInit+0x60>)
+ 80021a6: f043 0301 orr.w r3, r3, #1
+ 80021aa: 6013 str r3, [r2, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
- 800213c: 4b0f ldr r3, [pc, #60] ; (800217c <SystemInit+0x60>)
- 800213e: 2200 movs r2, #0
- 8002140: 609a str r2, [r3, #8]
+ 80021ac: 4b0f ldr r3, [pc, #60] ; (80021ec <SystemInit+0x60>)
+ 80021ae: 2200 movs r2, #0
+ 80021b0: 609a str r2, [r3, #8]
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8002142: 4b0e ldr r3, [pc, #56] ; (800217c <SystemInit+0x60>)
- 8002144: 681a ldr r2, [r3, #0]
- 8002146: 490d ldr r1, [pc, #52] ; (800217c <SystemInit+0x60>)
- 8002148: 4b0d ldr r3, [pc, #52] ; (8002180 <SystemInit+0x64>)
- 800214a: 4013 ands r3, r2
- 800214c: 600b str r3, [r1, #0]
+ 80021b2: 4b0e ldr r3, [pc, #56] ; (80021ec <SystemInit+0x60>)
+ 80021b4: 681a ldr r2, [r3, #0]
+ 80021b6: 490d ldr r1, [pc, #52] ; (80021ec <SystemInit+0x60>)
+ 80021b8: 4b0d ldr r3, [pc, #52] ; (80021f0 <SystemInit+0x64>)
+ 80021ba: 4013 ands r3, r2
+ 80021bc: 600b str r3, [r1, #0]
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
- 800214e: 4b0b ldr r3, [pc, #44] ; (800217c <SystemInit+0x60>)
- 8002150: 4a0c ldr r2, [pc, #48] ; (8002184 <SystemInit+0x68>)
- 8002152: 605a str r2, [r3, #4]
+ 80021be: 4b0b ldr r3, [pc, #44] ; (80021ec <SystemInit+0x60>)
+ 80021c0: 4a0c ldr r2, [pc, #48] ; (80021f4 <SystemInit+0x68>)
+ 80021c2: 605a str r2, [r3, #4]
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
- 8002154: 4b09 ldr r3, [pc, #36] ; (800217c <SystemInit+0x60>)
- 8002156: 681b ldr r3, [r3, #0]
- 8002158: 4a08 ldr r2, [pc, #32] ; (800217c <SystemInit+0x60>)
- 800215a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
- 800215e: 6013 str r3, [r2, #0]
+ 80021c4: 4b09 ldr r3, [pc, #36] ; (80021ec <SystemInit+0x60>)
+ 80021c6: 681b ldr r3, [r3, #0]
+ 80021c8: 4a08 ldr r2, [pc, #32] ; (80021ec <SystemInit+0x60>)
+ 80021ca: f423 2380 bic.w r3, r3, #262144 ; 0x40000
+ 80021ce: 6013 str r3, [r2, #0]
/* Disable all interrupts */
RCC->CIR = 0x00000000;
- 8002160: 4b06 ldr r3, [pc, #24] ; (800217c <SystemInit+0x60>)
- 8002162: 2200 movs r2, #0
- 8002164: 60da str r2, [r3, #12]
+ 80021d0: 4b06 ldr r3, [pc, #24] ; (80021ec <SystemInit+0x60>)
+ 80021d2: 2200 movs r2, #0
+ 80021d4: 60da str r2, [r3, #12]
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8002166: 4b04 ldr r3, [pc, #16] ; (8002178 <SystemInit+0x5c>)
- 8002168: f04f 6200 mov.w r2, #134217728 ; 0x8000000
- 800216c: 609a str r2, [r3, #8]
+ 80021d6: 4b04 ldr r3, [pc, #16] ; (80021e8 <SystemInit+0x5c>)
+ 80021d8: f04f 6200 mov.w r2, #134217728 ; 0x8000000
+ 80021dc: 609a str r2, [r3, #8]
#endif
}
- 800216e: bf00 nop
- 8002170: 46bd mov sp, r7
- 8002172: f85d 7b04 ldr.w r7, [sp], #4
- 8002176: 4770 bx lr
- 8002178: e000ed00 .word 0xe000ed00
- 800217c: 40023800 .word 0x40023800
- 8002180: fef6ffff .word 0xfef6ffff
- 8002184: 24003010 .word 0x24003010
+ 80021de: bf00 nop
+ 80021e0: 46bd mov sp, r7
+ 80021e2: f85d 7b04 ldr.w r7, [sp], #4
+ 80021e6: 4770 bx lr
+ 80021e8: e000ed00 .word 0xe000ed00
+ 80021ec: 40023800 .word 0x40023800
+ 80021f0: fef6ffff .word 0xfef6ffff
+ 80021f4: 24003010 .word 0x24003010
-08002188 <Reset_Handler>:
+080021f8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
- 8002188: f8df d034 ldr.w sp, [pc, #52] ; 80021c0 <LoopFillZerobss+0x14>
+ 80021f8: f8df d034 ldr.w sp, [pc, #52] ; 8002230 <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
- 800218c: 2100 movs r1, #0
+ 80021fc: 2100 movs r1, #0
b LoopCopyDataInit
- 800218e: e003 b.n 8002198 <LoopCopyDataInit>
+ 80021fe: e003 b.n 8002208 <LoopCopyDataInit>
-08002190 <CopyDataInit>:
+08002200 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
- 8002190: 4b0c ldr r3, [pc, #48] ; (80021c4 <LoopFillZerobss+0x18>)
+ 8002200: 4b0c ldr r3, [pc, #48] ; (8002234 <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
- 8002192: 585b ldr r3, [r3, r1]
+ 8002202: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
- 8002194: 5043 str r3, [r0, r1]
+ 8002204: 5043 str r3, [r0, r1]
adds r1, r1, #4
- 8002196: 3104 adds r1, #4
+ 8002206: 3104 adds r1, #4
-08002198 <LoopCopyDataInit>:
+08002208 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
- 8002198: 480b ldr r0, [pc, #44] ; (80021c8 <LoopFillZerobss+0x1c>)
+ 8002208: 480b ldr r0, [pc, #44] ; (8002238 <LoopFillZerobss+0x1c>)
ldr r3, =_edata
- 800219a: 4b0c ldr r3, [pc, #48] ; (80021cc <LoopFillZerobss+0x20>)
+ 800220a: 4b0c ldr r3, [pc, #48] ; (800223c <LoopFillZerobss+0x20>)
adds r2, r0, r1
- 800219c: 1842 adds r2, r0, r1
+ 800220c: 1842 adds r2, r0, r1
cmp r2, r3
- 800219e: 429a cmp r2, r3
+ 800220e: 429a cmp r2, r3
bcc CopyDataInit
- 80021a0: d3f6 bcc.n 8002190 <CopyDataInit>
+ 8002210: d3f6 bcc.n 8002200 <CopyDataInit>
ldr r2, =_sbss
- 80021a2: 4a0b ldr r2, [pc, #44] ; (80021d0 <LoopFillZerobss+0x24>)
+ 8002212: 4a0b ldr r2, [pc, #44] ; (8002240 <LoopFillZerobss+0x24>)
b LoopFillZerobss
- 80021a4: e002 b.n 80021ac <LoopFillZerobss>
+ 8002214: e002 b.n 800221c <LoopFillZerobss>
-080021a6 <FillZerobss>:
+08002216 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
- 80021a6: 2300 movs r3, #0
+ 8002216: 2300 movs r3, #0
str r3, [r2], #4
- 80021a8: f842 3b04 str.w r3, [r2], #4
+ 8002218: f842 3b04 str.w r3, [r2], #4
-080021ac <LoopFillZerobss>:
+0800221c <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
- 80021ac: 4b09 ldr r3, [pc, #36] ; (80021d4 <LoopFillZerobss+0x28>)
+ 800221c: 4b09 ldr r3, [pc, #36] ; (8002244 <LoopFillZerobss+0x28>)
cmp r2, r3
- 80021ae: 429a cmp r2, r3
+ 800221e: 429a cmp r2, r3
bcc FillZerobss
- 80021b0: d3f9 bcc.n 80021a6 <FillZerobss>
+ 8002220: d3f9 bcc.n 8002216 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
- 80021b2: f7ff ffb3 bl 800211c <SystemInit>
+ 8002222: f7ff ffb3 bl 800218c <SystemInit>
/* Call static constructors */
bl __libc_init_array
- 80021b6: f000 f811 bl 80021dc <__libc_init_array>
+ 8002226: f000 f811 bl 800224c <__libc_init_array>
/* Call the application's entry point.*/
bl main
- 80021ba: f7ff fde1 bl 8001d80 <main>
+ 800222a: f7ff fddf bl 8001dec <main>
bx lr
- 80021be: 4770 bx lr
+ 800222e: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
- 80021c0: 20080000 .word 0x20080000
+ 8002230: 20080000 .word 0x20080000
ldr r3, =_sidata
- 80021c4: 0800226c .word 0x0800226c
+ 8002234: 080022dc .word 0x080022dc
ldr r0, =_sdata
- 80021c8: 20000000 .word 0x20000000
+ 8002238: 20000000 .word 0x20000000
ldr r3, =_edata
- 80021cc: 2000000c .word 0x2000000c
+ 800223c: 2000000c .word 0x2000000c
ldr r2, =_sbss
- 80021d0: 2000000c .word 0x2000000c
+ 8002240: 2000000c .word 0x2000000c
ldr r3, = _ebss
- 80021d4: 2000006c .word 0x2000006c
+ 8002244: 2000006c .word 0x2000006c
-08002
1d8 <ADC_IRQHandler>:
+08002
248 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 8002
1d8: e7fe b.n 80021d8 <ADC_IRQHandler>
+ 8002
248: e7fe b.n 8002248 <ADC_IRQHandler>
...
-080021dc <__libc_init_array>:
- 80021dc: b570 push {r4, r5, r6, lr}
- 80021de: 4e0d ldr r6, [pc, #52] ; (8002214 <__libc_init_array+0x38>)
- 80021e0: 4c0d ldr r4, [pc, #52] ; (8002218 <__libc_init_array+0x3c>)
- 80021e2: 1ba4 subs r4, r4, r6
- 80021e4: 10a4 asrs r4, r4, #2
- 80021e6: 2500 movs r5, #0
- 80021e8: 42a5 cmp r5, r4
- 80021ea: d109 bne.n 8002200 <__libc_init_array+0x24>
- 80021ec: 4e0b ldr r6, [pc, #44] ; (800221c <__libc_init_array+0x40>)
- 80021ee: 4c0c ldr r4, [pc, #48] ; (8002220 <__libc_init_array+0x44>)
- 80021f0: f000 f820 bl 8002234 <_init>
- 80021f4: 1ba4 subs r4, r4, r6
- 80021f6: 10a4 asrs r4, r4, #2
- 80021f8: 2500 movs r5, #0
- 80021fa: 42a5 cmp r5, r4
- 80021fc: d105 bne.n 800220a <__libc_init_array+0x2e>
- 80021fe: bd70 pop {r4, r5, r6, pc}
- 8002200: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 8002204: 4798 blx r3
- 8002206: 3501 adds r5, #1
- 8002208: e7ee b.n 80021e8 <__libc_init_array+0xc>
- 800220a: f856 3025 ldr.w r3, [r6, r5, lsl #2]
- 800220e: 4798 blx r3
- 8002210: 3501 adds r5, #1
- 8002212: e7f2 b.n 80021fa <__libc_init_array+0x1e>
- 8002214: 08002264 .word 0x08002264
- 8002218: 08002264 .word 0x08002264
- 800221c: 08002264 .word 0x08002264
- 8002220: 08002268 .word 0x08002268
-
-08002224 <memset>:
- 8002224: 4402 add r2, r0
- 8002226: 4603 mov r3, r0
- 8002228: 4293 cmp r3, r2
- 800222a: d100 bne.n 800222e <memset+0xa>
- 800222c: 4770 bx lr
- 800222e: f803 1b01 strb.w r1, [r3], #1
- 8002232: e7f9 b.n 8002228 <memset+0x4>
-
-08002234 <_init>:
- 8002234: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8002236: bf00 nop
- 8002238: bcf8 pop {r3, r4, r5, r6, r7}
- 800223a: bc08 pop {r3}
- 800223c: 469e mov lr, r3
- 800223e: 4770 bx lr
-
-08002240 <_fini>:
- 8002240: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8002242: bf00 nop
- 8002244: bcf8 pop {r3, r4, r5, r6, r7}
- 8002246: bc08 pop {r3}
- 8002248: 469e mov lr, r3
- 800224a: 4770 bx lr
+0800224c <__libc_init_array>:
+ 800224c: b570 push {r4, r5, r6, lr}
+ 800224e: 4e0d ldr r6, [pc, #52] ; (8002284 <__libc_init_array+0x38>)
+ 8002250: 4c0d ldr r4, [pc, #52] ; (8002288 <__libc_init_array+0x3c>)
+ 8002252: 1ba4 subs r4, r4, r6
+ 8002254: 10a4 asrs r4, r4, #2
+ 8002256: 2500 movs r5, #0
+ 8002258: 42a5 cmp r5, r4
+ 800225a: d109 bne.n 8002270 <__libc_init_array+0x24>
+ 800225c: 4e0b ldr r6, [pc, #44] ; (800228c <__libc_init_array+0x40>)
+ 800225e: 4c0c ldr r4, [pc, #48] ; (8002290 <__libc_init_array+0x44>)
+ 8002260: f000 f820 bl 80022a4 <_init>
+ 8002264: 1ba4 subs r4, r4, r6
+ 8002266: 10a4 asrs r4, r4, #2
+ 8002268: 2500 movs r5, #0
+ 800226a: 42a5 cmp r5, r4
+ 800226c: d105 bne.n 800227a <__libc_init_array+0x2e>
+ 800226e: bd70 pop {r4, r5, r6, pc}
+ 8002270: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 8002274: 4798 blx r3
+ 8002276: 3501 adds r5, #1
+ 8002278: e7ee b.n 8002258 <__libc_init_array+0xc>
+ 800227a: f856 3025 ldr.w r3, [r6, r5, lsl #2]
+ 800227e: 4798 blx r3
+ 8002280: 3501 adds r5, #1
+ 8002282: e7f2 b.n 800226a <__libc_init_array+0x1e>
+ 8002284: 080022d4 .word 0x080022d4
+ 8002288: 080022d4 .word 0x080022d4
+ 800228c: 080022d4 .word 0x080022d4
+ 8002290: 080022d8 .word 0x080022d8
+
+08002294 <memset>:
+ 8002294: 4402 add r2, r0
+ 8002296: 4603 mov r3, r0
+ 8002298: 4293 cmp r3, r2
+ 800229a: d100 bne.n 800229e <memset+0xa>
+ 800229c: 4770 bx lr
+ 800229e: f803 1b01 strb.w r1, [r3], #1
+ 80022a2: e7f9 b.n 8002298 <memset+0x4>
+
+080022a4 <_init>:
+ 80022a4: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 80022a6: bf00 nop
+ 80022a8: bcf8 pop {r3, r4, r5, r6, r7}
+ 80022aa: bc08 pop {r3}
+ 80022ac: 469e mov lr, r3
+ 80022ae: 4770 bx lr
+
+080022b0 <_fini>:
+ 80022b0: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 80022b2: bf00 nop
+ 80022b4: bcf8 pop {r3, r4, r5, r6, r7}
+ 80022b6: bc08 pop {r3}
+ 80022b8: 469e mov lr, r3
+ 80022ba: 4770 bx lr
projects / pioneer-stm32 / commitdiff